diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index bc45d55..80cf24a 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -4009,7 +4009,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3, @@ -4018,7 +4018,7 @@ module mkCore(CLK, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2; wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1; - wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1, + wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2, MUX_csrf_prv_reg$write_1__VAL_1, MUX_csrf_prv_reg$write_1__VAL_2; wire MUX_commitStage_rg_serial_num$write_1__SEL_1, @@ -4074,20 +4074,14 @@ module mkCore(CLK, MUX_csrf_fflags_reg$write_1__SEL_1, MUX_csrf_fs_reg$write_1__SEL_1, MUX_csrf_ie_vec_1$write_1__SEL_1, - MUX_csrf_ie_vec_1$write_1__SEL_2, - MUX_csrf_ie_vec_1$write_1__VAL_1, + MUX_csrf_ie_vec_1$write_1__VAL_2, MUX_csrf_ie_vec_3$write_1__SEL_1, - MUX_csrf_ie_vec_3$write_1__SEL_2, - MUX_csrf_ie_vec_3$write_1__VAL_1, - MUX_csrf_mpp_reg$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__SEL_1, - MUX_csrf_prev_ie_vec_1$write_1__VAL_1, - MUX_csrf_prev_ie_vec_3$write_1__SEL_1, - MUX_csrf_prev_ie_vec_3$write_1__VAL_1, + MUX_csrf_ie_vec_3$write_1__VAL_2, + MUX_csrf_prev_ie_vec_1$write_1__VAL_2, + MUX_csrf_prev_ie_vec_3$write_1__VAL_2, MUX_csrf_prv_reg$write_1__SEL_1, MUX_csrf_software_int_pend_vec_3$write_1__VAL_2, - MUX_csrf_spp_reg$write_1__SEL_1, - MUX_csrf_spp_reg$write_1__VAL_1, + MUX_csrf_spp_reg$write_1__VAL_2, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, MUX_flush_reservation$write_1__SEL_1, @@ -4099,7 +4093,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_4, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_1, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_1, @@ -4131,33 +4125,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968, - addr__h294612, - curData__h195303, - rVal1__h615931, - rVal1__h640776, + addr__h294611, + curData__h195302, + rVal1__h615930, + rVal1__h640774, trap_val__h708780, - x__h200346; + x__h200345; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q207, - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q208, - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211, - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212, - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197, - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198, - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199, - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200, - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201, - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202, - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213, - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214, - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215, - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216, - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217, - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218, - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q209, - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q210, + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q209, + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q210, + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q211, + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q212, + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q197, + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q198, + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q199, + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q200, + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q201, + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q202, + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q213, + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q214, + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q215, + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q216, + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q217, + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q218, + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q207, + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755, @@ -4169,45 +4163,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75, - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76, - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79, - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80, - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81, - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82, - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112, - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113, - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42, - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43, - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110, - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111, - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40, - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41, - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114, - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115, - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44, - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45, - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116, - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117, - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46, - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47, - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77, - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78, - _theResult___fst_sfd__h350718, - _theResult___fst_sfd__h359441, - _theResult___fst_sfd__h368023, - _theResult___fst_sfd__h377207, - _theResult___fst_sfd__h385843, - _theResult___fst_sfd__h396417, - _theResult___fst_sfd__h405138, - _theResult___fst_sfd__h413720, - _theResult___fst_sfd__h422904, - _theResult___fst_sfd__h431540, - _theResult___fst_sfd__h442112, - _theResult___fst_sfd__h450833, - _theResult___fst_sfd__h459415, - _theResult___fst_sfd__h468599, - _theResult___fst_sfd__h477235; + reg [22 : 0] CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q75, + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q76, + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q79, + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q80, + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q81, + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q82, + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q112, + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q113, + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q42, + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q43, + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q110, + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q111, + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q40, + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q41, + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q114, + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q115, + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q44, + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q45, + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q116, + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q117, + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q46, + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q47, + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q77, + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q78, + _theResult___fst_sfd__h350717, + _theResult___fst_sfd__h359440, + _theResult___fst_sfd__h368022, + _theResult___fst_sfd__h377206, + _theResult___fst_sfd__h385842, + _theResult___fst_sfd__h396416, + _theResult___fst_sfd__h405137, + _theResult___fst_sfd__h413719, + _theResult___fst_sfd__h422903, + _theResult___fst_sfd__h431539, + _theResult___fst_sfd__h442111, + _theResult___fst_sfd__h450832, + _theResult___fst_sfd__h459414, + _theResult___fst_sfd__h468598, + _theResult___fst_sfd__h477234; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, @@ -4226,29 +4220,29 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275, - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228, + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229, IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125; reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203, - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204, - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205, - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206, - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175, - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176, - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177, - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178, - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179, - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180, - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152, - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153, - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183, - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184, - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181, - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182, - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135, - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136, + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q203, + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q204, + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q205, + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q206, + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q175, + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q176, + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q177, + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q178, + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q179, + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q180, + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q152, + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q153, + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q183, + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q184, + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q181, + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q182, + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q135, + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684, @@ -4258,47 +4252,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914; - reg [7 : 0] CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60, - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61, - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68, - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69, - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73, - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74, - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97, - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98, - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27, - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28, - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95, - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96, - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25, - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26, - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103, - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104, - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33, - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34, - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108, - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109, - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38, - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39, - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62, - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63, + reg [7 : 0] CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q60, + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q61, + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q68, + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q69, + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q73, + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q74, + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q97, + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q98, + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q27, + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q28, + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q95, + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q96, + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q25, + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q26, + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q103, + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q104, + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q33, + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q34, + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q108, + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q109, + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q38, + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q39, + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q62, + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q63, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430, - _theResult___fst_exp__h350717, - _theResult___fst_exp__h359440, - _theResult___fst_exp__h368022, - _theResult___fst_exp__h377206, - _theResult___fst_exp__h385842, - _theResult___fst_exp__h396416, - _theResult___fst_exp__h405137, - _theResult___fst_exp__h413719, - _theResult___fst_exp__h422903, - _theResult___fst_exp__h431539, - _theResult___fst_exp__h442111, - _theResult___fst_exp__h450832, - _theResult___fst_exp__h459414, - _theResult___fst_exp__h468598, - _theResult___fst_exp__h477234; + _theResult___fst_exp__h350716, + _theResult___fst_exp__h359439, + _theResult___fst_exp__h368021, + _theResult___fst_exp__h377205, + _theResult___fst_exp__h385841, + _theResult___fst_exp__h396415, + _theResult___fst_exp__h405136, + _theResult___fst_exp__h413718, + _theResult___fst_exp__h422902, + _theResult___fst_exp__h431538, + _theResult___fst_exp__h442110, + _theResult___fst_exp__h450831, + _theResult___fst_exp__h459413, + _theResult___fst_exp__h468597, + _theResult___fst_exp__h477233; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263, @@ -4309,8 +4303,8 @@ module mkCore(CLK, CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226, CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13, CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260, CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261, IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14219, @@ -4329,10 +4323,10 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828, - x__h290391, - x__h296161; + x__h290390, + x__h296160; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -4360,50 +4354,50 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234, - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232, + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119, - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120, - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233, + CASE_guard05150_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, + CASE_guard05150_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, + CASE_guard08264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard14080_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, + CASE_guard14080_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, + CASE_guard17333_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard22916_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, + CASE_guard22916_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, + CASE_guard37805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard37805_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard42138_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, + CASE_guard42138_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, + CASE_guard47117_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard47117_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard50744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard50744_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard50845_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, + CASE_guard50845_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard56186_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard56186_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard59453_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, + CASE_guard59453_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, + CASE_guard59775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, + CASE_guard59775_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard68611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, + CASE_guard68611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, + CASE_guard77109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard77109_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard77219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, + CASE_guard77219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, + CASE_guard86421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard86421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard95490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard95490_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard96443_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, + CASE_guard96443_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, + CASE_guard98952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_k74091_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4488,7 +4482,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023; - wire [127 : 0] b__h608520, b__h608596, b__h608697, b__h608709, x__h609549; + wire [127 : 0] b__h608519, b__h608595, b__h608696, b__h608708, x__h609548; wire [68 : 0] execFpuSimple___d11167; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598; @@ -4523,162 +4517,162 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095, - _theResult___fst__h608920, - _theResult___snd__h608921, - a___1__h608534, - a___1__h608925, - a__h608372, + _theResult___fst__h608919, + _theResult___snd__h608920, + a___1__h608533, + a___1__h608924, + a__h608371, amoExec___d882, - b___1__h608535, - b___1__h608986, - b__h608373, + b___1__h608534, + b___1__h608985, + b__h608372, base__h710680, base__h710700, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257, - data___1__h479773, - data___1__h480705, - data__h479261, - data__h480193, - fallthrough_pc__h670385, - fallthrough_pc__h686131, - fcsr_csr__read__h616233, - fflags_csr__read__h616208, - frm_csr__read__h616219, - mcause_csr__read__h617875, - mcounteren_csr__read__h617620, - medeleg_csr__read__h617227, - mideleg_csr__read__h617322, - mie_csr__read__h617446, - mip_csr__read__h618108, - mstatus_csr__read__h617079, - mtvec_csr__read__h617528, - n___1__h201749, - n__h196841, - n__read__h618212, - n__read__h618403, + data___1__h479772, + data___1__h480704, + data__h479260, + data__h480192, + fallthrough_pc__h670383, + fallthrough_pc__h686129, + fcsr_csr__read__h616232, + fflags_csr__read__h616207, + frm_csr__read__h616218, + mcause_csr__read__h617874, + mcounteren_csr__read__h617619, + medeleg_csr__read__h617226, + mideleg_csr__read__h617321, + mie_csr__read__h617445, + mip_csr__read__h618107, + mstatus_csr__read__h617078, + mtvec_csr__read__h617527, + n___1__h201748, + n__h196840, + n__read__h618211, + n__read__h618402, n__read__h6329, - n__read__h719386, - next_pc__h718596, - q___1__h480780, - rVal1__h487142, - rVal2__h487143, - r___1__h480807, - res_data__h342519, - res_data__h342524, - res_data__h388221, - res_data__h388226, - res_data__h433916, - res_data__h433921, - resp_addr__h296627, - rg_tdata1__read__h619063, + n__read__h719387, + next_pc__h718597, + q___1__h480779, + rVal1__h487141, + rVal2__h487142, + r___1__h480806, + res_data__h342518, + res_data__h342523, + res_data__h388220, + res_data__h388225, + res_data__h433915, + res_data__h433920, + resp_addr__h296626, + rg_tdata1__read__h619062, rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954, robdeqPort_0_deq_data_BITS_95_TO_32__q262, - satp_csr__read__h616936, - scause_csr__read__h616733, - scounteren_csr__read__h616595, - shiftData__h184742, - sie_csr__read__h616499, - sip_csr__read__h616873, - sstatus_csr__read__h616429, - stvec_csr__read__h616542, + satp_csr__read__h616935, + scause_csr__read__h616732, + scounteren_csr__read__h616594, + shiftData__h184741, + sie_csr__read__h616498, + sip_csr__read__h616872, + sstatus_csr__read__h616428, + stvec_csr__read__h616541, upd__h3680, upd__h4997, - v__h614703, - v__h639702, - vaddr__h184737, - x__h155097, - x__h158644, - x__h161458, - x__h163306, + v__h614702, + v__h639700, + vaddr__h184736, + x__h155096, + x__h158643, + x__h161457, + x__h163305, x__h17931, + x__h184648, x__h184649, - x__h184650, x__h20469, - x__h291836, - x__h293690, + x__h291835, + x__h293689, x__h45838, x__h48374, + x__h487047, x__h487048, x__h487049, - x__h487050, - x__h608909, + x__h608908, + x__h623641, x__h623642, - x__h623643, - x__h646272, - x__h646273, - x__h704087, - x_addr__h318724, - x_quotient__h479957, - x_reg_ifc__read__h616338, - x_remainder__h479958, - y__h626444, - y__h648781, - y__h722605, - y_avValue__h183777, - y_avValue__h184496, - y_avValue__h484111, - y_avValue__h484832, - y_avValue__h485547, - y_avValue__h615874, - y_avValue__h621652, - y_avValue__h640721, - y_avValue__h644292, + x__h646270, + x__h646271, + x__h704086, + x_addr__h318723, + x_quotient__h479956, + x_reg_ifc__read__h616337, + x_remainder__h479957, + y__h626443, + y__h648779, + y__h722607, + y_avValue__h183776, + y_avValue__h184495, + y_avValue__h484110, + y_avValue__h484831, + y_avValue__h485546, + y_avValue__h615873, + y_avValue__h621651, + y_avValue__h640719, + y_avValue__h644290, y_avValue_new_pc__h710461, y_avValue_new_pc__h710647, - y_avValue_snd_snd_snd_snd_snd__h721999, - y_avValue_snd_snd_snd_snd_snd__h722658, - y_avValue_snd_snd_snd_snd_snd__h722687; + y_avValue_snd_snd_snd_snd_snd__h722001, + y_avValue_snd_snd_snd_snd_snd__h722660, + y_avValue_snd_snd_snd_snd_snd__h722689; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993, - r1__read__h619388, - r1__read__h619792, - r1__read__h620302, - r1__read__h620307, - r1__read__h620326, - r1__read__h620559, - r1__read__h620725, - r1__read__h620818, - r1__read__h620823, - r1__read__h620842; - wire [61 : 0] r1__read__h619390, - r1__read__h619794, - r1__read__h620309, - r1__read__h620328, - r1__read__h620561, - r1__read__h620701, - r1__read__h620727, - r1__read__h620825, - r1__read__h620844; - wire [60 : 0] r1__read__h620563, - r1__read__h620703, - r1__read__h620729, - r1__read__h620846; - wire [59 : 0] r1__read__h619392, - r1__read__h619796, - r1__read__h620320, - r1__read__h620330, - r1__read__h620565, - r1__read__h620731, - r1__read__h620836, - r1__read__h620848; - wire [58 : 0] r1__read__h619394, - r1__read__h619798, - r1__read__h620332, - r1__read__h620567, - r1__read__h620733, - r1__read__h620850; + r1__read__h619387, + r1__read__h619791, + r1__read__h620301, + r1__read__h620306, + r1__read__h620325, + r1__read__h620558, + r1__read__h620724, + r1__read__h620817, + r1__read__h620822, + r1__read__h620841; + wire [61 : 0] r1__read__h619389, + r1__read__h619793, + r1__read__h620308, + r1__read__h620327, + r1__read__h620560, + r1__read__h620700, + r1__read__h620726, + r1__read__h620824, + r1__read__h620843; + wire [60 : 0] r1__read__h620562, + r1__read__h620702, + r1__read__h620728, + r1__read__h620845; + wire [59 : 0] r1__read__h619391, + r1__read__h619795, + r1__read__h620319, + r1__read__h620329, + r1__read__h620564, + r1__read__h620730, + r1__read__h620835, + r1__read__h620847; + wire [58 : 0] r1__read__h619393, + r1__read__h619797, + r1__read__h620331, + r1__read__h620566, + r1__read__h620732, + r1__read__h620849; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, - r1__read__h619396, - r1__read__h619800, - r1__read__h620334, - r1__read__h620569, - r1__read__h620705, - r1__read__h620735, - r1__read__h620852, - y__h258434; + r1__read__h619395, + r1__read__h619799, + r1__read__h620333, + r1__read__h620568, + r1__read__h620704, + r1__read__h620734, + r1__read__h620851, + y__h258433; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91, @@ -4706,187 +4700,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438, - _theResult____h350735, - _theResult____h368374, - _theResult____h396434, - _theResult____h414071, - _theResult____h442129, - _theResult____h459766, - _theResult____h508255, - _theResult____h547108, - _theResult____h586412, - _theResult___snd__h358857, - _theResult___snd__h358868, - _theResult___snd__h358870, - _theResult___snd__h358880, - _theResult___snd__h358886, - _theResult___snd__h358909, - _theResult___snd__h367453, - _theResult___snd__h367455, - _theResult___snd__h367462, - _theResult___snd__h367468, - _theResult___snd__h367491, - _theResult___snd__h376623, - _theResult___snd__h376634, - _theResult___snd__h376636, - _theResult___snd__h376646, - _theResult___snd__h376652, - _theResult___snd__h376675, - _theResult___snd__h385243, - _theResult___snd__h385257, - _theResult___snd__h385263, - _theResult___snd__h385281, - _theResult___snd__h404554, - _theResult___snd__h404565, - _theResult___snd__h404567, - _theResult___snd__h404577, - _theResult___snd__h404583, - _theResult___snd__h404606, - _theResult___snd__h413150, - _theResult___snd__h413152, - _theResult___snd__h413159, - _theResult___snd__h413165, - _theResult___snd__h413188, - _theResult___snd__h422320, - _theResult___snd__h422331, - _theResult___snd__h422333, - _theResult___snd__h422343, - _theResult___snd__h422349, - _theResult___snd__h422372, - _theResult___snd__h430940, - _theResult___snd__h430954, - _theResult___snd__h430960, - _theResult___snd__h430978, - _theResult___snd__h450249, - _theResult___snd__h450260, - _theResult___snd__h450262, - _theResult___snd__h450272, - _theResult___snd__h450278, - _theResult___snd__h450301, - _theResult___snd__h458845, - _theResult___snd__h458847, - _theResult___snd__h458854, - _theResult___snd__h458860, - _theResult___snd__h458883, - _theResult___snd__h468015, - _theResult___snd__h468026, - _theResult___snd__h468028, - _theResult___snd__h468038, - _theResult___snd__h468044, - _theResult___snd__h468067, - _theResult___snd__h476635, - _theResult___snd__h476649, - _theResult___snd__h476655, - _theResult___snd__h476673, - _theResult___snd__h506865, - _theResult___snd__h506867, - _theResult___snd__h506874, - _theResult___snd__h506880, - _theResult___snd__h506903, - _theResult___snd__h516502, - _theResult___snd__h516513, - _theResult___snd__h516515, - _theResult___snd__h516525, - _theResult___snd__h516531, - _theResult___snd__h516554, - _theResult___snd__h525270, - _theResult___snd__h525284, - _theResult___snd__h525290, - _theResult___snd__h525308, - _theResult___snd__h545718, - _theResult___snd__h545720, - _theResult___snd__h545727, - _theResult___snd__h545733, - _theResult___snd__h545756, - _theResult___snd__h555355, - _theResult___snd__h555366, - _theResult___snd__h555368, - _theResult___snd__h555378, - _theResult___snd__h555384, - _theResult___snd__h555407, - _theResult___snd__h564123, - _theResult___snd__h564137, - _theResult___snd__h564143, - _theResult___snd__h564161, - _theResult___snd__h585022, - _theResult___snd__h585024, - _theResult___snd__h585031, - _theResult___snd__h585037, - _theResult___snd__h585060, - _theResult___snd__h594659, - _theResult___snd__h594670, - _theResult___snd__h594672, - _theResult___snd__h594682, - _theResult___snd__h594688, - _theResult___snd__h594711, - _theResult___snd__h603427, - _theResult___snd__h603441, - _theResult___snd__h603447, - _theResult___snd__h603465, - r1__read__h620571, - r1__read__h620707, - r1__read__h620737, - r1__read__h620854, - result__h368987, - result__h414684, - result__h460379, - result__h508868, - result__h547721, - result__h587025, - sfd__h343130, - sfd__h388832, - sfd__h434527, - sfd__h487888, - sfd__h526882, - sfd__h566186, - sfdin__h358840, - sfdin__h376606, - sfdin__h404537, - sfdin__h422303, - sfdin__h450232, - sfdin__h467998, - sfdin__h516485, - sfdin__h555338, - sfdin__h594642, - x__h369084, - x__h414781, - x__h460476, - x__h508963, - x__h547816, - x__h587120; - wire [55 : 0] r1__read__h619398, - r1__read__h619802, - r1__read__h620336, - r1__read__h620573, - r1__read__h620739, - r1__read__h620856; - wire [54 : 0] r1__read__h619400, - r1__read__h619804, - r1__read__h620338, - r1__read__h620575, - r1__read__h620741, - r1__read__h620858; - wire [53 : 0] r1__read__h620684, - r1__read__h620709, - r1__read__h620743, - r1__read__h620860, - sfd__h506932, - sfd__h516583, - sfd__h525343, - sfd__h545785, - sfd__h555436, - sfd__h564196, - sfd__h585089, - sfd__h594740, - sfd__h603500, - value__h351357, - value__h397054, - value__h442749; - wire [52 : 0] r1__read__h620577, - r1__read__h620686, - r1__read__h620711, - r1__read__h620745, - r1__read__h620862; + _theResult____h350734, + _theResult____h368373, + _theResult____h396433, + _theResult____h414070, + _theResult____h442128, + _theResult____h459765, + _theResult____h508254, + _theResult____h547107, + _theResult____h586411, + _theResult___snd__h358856, + _theResult___snd__h358867, + _theResult___snd__h358869, + _theResult___snd__h358879, + _theResult___snd__h358885, + _theResult___snd__h358908, + _theResult___snd__h367452, + _theResult___snd__h367454, + _theResult___snd__h367461, + _theResult___snd__h367467, + _theResult___snd__h367490, + _theResult___snd__h376622, + _theResult___snd__h376633, + _theResult___snd__h376635, + _theResult___snd__h376645, + _theResult___snd__h376651, + _theResult___snd__h376674, + _theResult___snd__h385242, + _theResult___snd__h385256, + _theResult___snd__h385262, + _theResult___snd__h385280, + _theResult___snd__h404553, + _theResult___snd__h404564, + _theResult___snd__h404566, + _theResult___snd__h404576, + _theResult___snd__h404582, + _theResult___snd__h404605, + _theResult___snd__h413149, + _theResult___snd__h413151, + _theResult___snd__h413158, + _theResult___snd__h413164, + _theResult___snd__h413187, + _theResult___snd__h422319, + _theResult___snd__h422330, + _theResult___snd__h422332, + _theResult___snd__h422342, + _theResult___snd__h422348, + _theResult___snd__h422371, + _theResult___snd__h430939, + _theResult___snd__h430953, + _theResult___snd__h430959, + _theResult___snd__h430977, + _theResult___snd__h450248, + _theResult___snd__h450259, + _theResult___snd__h450261, + _theResult___snd__h450271, + _theResult___snd__h450277, + _theResult___snd__h450300, + _theResult___snd__h458844, + _theResult___snd__h458846, + _theResult___snd__h458853, + _theResult___snd__h458859, + _theResult___snd__h458882, + _theResult___snd__h468014, + _theResult___snd__h468025, + _theResult___snd__h468027, + _theResult___snd__h468037, + _theResult___snd__h468043, + _theResult___snd__h468066, + _theResult___snd__h476634, + _theResult___snd__h476648, + _theResult___snd__h476654, + _theResult___snd__h476672, + _theResult___snd__h506864, + _theResult___snd__h506866, + _theResult___snd__h506873, + _theResult___snd__h506879, + _theResult___snd__h506902, + _theResult___snd__h516501, + _theResult___snd__h516512, + _theResult___snd__h516514, + _theResult___snd__h516524, + _theResult___snd__h516530, + _theResult___snd__h516553, + _theResult___snd__h525269, + _theResult___snd__h525283, + _theResult___snd__h525289, + _theResult___snd__h525307, + _theResult___snd__h545717, + _theResult___snd__h545719, + _theResult___snd__h545726, + _theResult___snd__h545732, + _theResult___snd__h545755, + _theResult___snd__h555354, + _theResult___snd__h555365, + _theResult___snd__h555367, + _theResult___snd__h555377, + _theResult___snd__h555383, + _theResult___snd__h555406, + _theResult___snd__h564122, + _theResult___snd__h564136, + _theResult___snd__h564142, + _theResult___snd__h564160, + _theResult___snd__h585021, + _theResult___snd__h585023, + _theResult___snd__h585030, + _theResult___snd__h585036, + _theResult___snd__h585059, + _theResult___snd__h594658, + _theResult___snd__h594669, + _theResult___snd__h594671, + _theResult___snd__h594681, + _theResult___snd__h594687, + _theResult___snd__h594710, + _theResult___snd__h603426, + _theResult___snd__h603440, + _theResult___snd__h603446, + _theResult___snd__h603464, + r1__read__h620570, + r1__read__h620706, + r1__read__h620736, + r1__read__h620853, + result__h368986, + result__h414683, + result__h460378, + result__h508867, + result__h547720, + result__h587024, + sfd__h343129, + sfd__h388831, + sfd__h434526, + sfd__h487887, + sfd__h526881, + sfd__h566185, + sfdin__h358839, + sfdin__h376605, + sfdin__h404536, + sfdin__h422302, + sfdin__h450231, + sfdin__h467997, + sfdin__h516484, + sfdin__h555337, + sfdin__h594641, + x__h369083, + x__h414780, + x__h460475, + x__h508962, + x__h547815, + x__h587119; + wire [55 : 0] r1__read__h619397, + r1__read__h619801, + r1__read__h620335, + r1__read__h620572, + r1__read__h620738, + r1__read__h620855; + wire [54 : 0] r1__read__h619399, + r1__read__h619803, + r1__read__h620337, + r1__read__h620574, + r1__read__h620740, + r1__read__h620857; + wire [53 : 0] r1__read__h620683, + r1__read__h620708, + r1__read__h620742, + r1__read__h620859, + sfd__h506931, + sfd__h516582, + sfd__h525342, + sfd__h545784, + sfd__h555435, + sfd__h564195, + sfd__h585088, + sfd__h594739, + sfd__h603499, + value__h351356, + value__h397053, + value__h442748; + wire [52 : 0] r1__read__h620576, + r1__read__h620685, + r1__read__h620710, + r1__read__h620744, + r1__read__h620861; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251, @@ -4908,109 +4902,109 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992, - _theResult___fst_sfd__h491842, - _theResult___fst_sfd__h507670, - _theResult___fst_sfd__h507673, - _theResult___fst_sfd__h517321, - _theResult___fst_sfd__h517324, - _theResult___fst_sfd__h526105, - _theResult___fst_sfd__h526108, - _theResult___fst_sfd__h526117, - _theResult___fst_sfd__h526123, - _theResult___fst_sfd__h530695, - _theResult___fst_sfd__h546523, - _theResult___fst_sfd__h546526, - _theResult___fst_sfd__h556174, - _theResult___fst_sfd__h556177, - _theResult___fst_sfd__h564958, - _theResult___fst_sfd__h564961, - _theResult___fst_sfd__h564970, - _theResult___fst_sfd__h564976, - _theResult___fst_sfd__h569999, - _theResult___fst_sfd__h585827, - _theResult___fst_sfd__h585830, - _theResult___fst_sfd__h595478, - _theResult___fst_sfd__h595481, - _theResult___fst_sfd__h604262, - _theResult___fst_sfd__h604265, - _theResult___fst_sfd__h604274, - _theResult___fst_sfd__h604280, - _theResult___sfd__h507570, - _theResult___sfd__h517221, - _theResult___sfd__h526005, - _theResult___sfd__h546423, - _theResult___sfd__h556074, - _theResult___sfd__h564858, - _theResult___sfd__h585727, - _theResult___sfd__h595378, - _theResult___sfd__h604162, - _theResult___snd_fst_sfd__h487842, - _theResult___snd_fst_sfd__h507676, - _theResult___snd_fst_sfd__h526111, - _theResult___snd_fst_sfd__h526836, - _theResult___snd_fst_sfd__h546529, - _theResult___snd_fst_sfd__h564964, - _theResult___snd_fst_sfd__h566140, - _theResult___snd_fst_sfd__h585833, - _theResult___snd_fst_sfd__h604268, - out___1_sfd__h487590, - out___1_sfd__h526584, - out___1_sfd__h565888, - out_sfd__h507573, - out_sfd__h517224, - out_sfd__h526008, - out_sfd__h546426, - out_sfd__h556077, - out_sfd__h564861, - out_sfd__h585730, - out_sfd__h595381, - out_sfd__h604165; - wire [50 : 0] r1__read__h619402, r1__read__h620579; - wire [49 : 0] r1__read__h620688; - wire [48 : 0] r1__read__h619404, r1__read__h620581, r1__read__h620690; - wire [46 : 0] r1__read__h619406, r1__read__h620583; - wire [45 : 0] r1__read__h619408, r1__read__h620585; - wire [44 : 0] r1__read__h619410, r1__read__h620587; - wire [43 : 0] r1__read__h619412, r1__read__h620589; - wire [42 : 0] r1__read__h620591; - wire [41 : 0] r1__read__h620593; - wire [40 : 0] r1__read__h620595; + _theResult___fst_sfd__h491841, + _theResult___fst_sfd__h507669, + _theResult___fst_sfd__h507672, + _theResult___fst_sfd__h517320, + _theResult___fst_sfd__h517323, + _theResult___fst_sfd__h526104, + _theResult___fst_sfd__h526107, + _theResult___fst_sfd__h526116, + _theResult___fst_sfd__h526122, + _theResult___fst_sfd__h530694, + _theResult___fst_sfd__h546522, + _theResult___fst_sfd__h546525, + _theResult___fst_sfd__h556173, + _theResult___fst_sfd__h556176, + _theResult___fst_sfd__h564957, + _theResult___fst_sfd__h564960, + _theResult___fst_sfd__h564969, + _theResult___fst_sfd__h564975, + _theResult___fst_sfd__h569998, + _theResult___fst_sfd__h585826, + _theResult___fst_sfd__h585829, + _theResult___fst_sfd__h595477, + _theResult___fst_sfd__h595480, + _theResult___fst_sfd__h604261, + _theResult___fst_sfd__h604264, + _theResult___fst_sfd__h604273, + _theResult___fst_sfd__h604279, + _theResult___sfd__h507569, + _theResult___sfd__h517220, + _theResult___sfd__h526004, + _theResult___sfd__h546422, + _theResult___sfd__h556073, + _theResult___sfd__h564857, + _theResult___sfd__h585726, + _theResult___sfd__h595377, + _theResult___sfd__h604161, + _theResult___snd_fst_sfd__h487841, + _theResult___snd_fst_sfd__h507675, + _theResult___snd_fst_sfd__h526110, + _theResult___snd_fst_sfd__h526835, + _theResult___snd_fst_sfd__h546528, + _theResult___snd_fst_sfd__h564963, + _theResult___snd_fst_sfd__h566139, + _theResult___snd_fst_sfd__h585832, + _theResult___snd_fst_sfd__h604267, + out___1_sfd__h487589, + out___1_sfd__h526583, + out___1_sfd__h565887, + out_sfd__h507572, + out_sfd__h517223, + out_sfd__h526007, + out_sfd__h546425, + out_sfd__h556076, + out_sfd__h564860, + out_sfd__h585729, + out_sfd__h595380, + out_sfd__h604164; + wire [50 : 0] r1__read__h619401, r1__read__h620578; + wire [49 : 0] r1__read__h620687; + wire [48 : 0] r1__read__h619403, r1__read__h620580, r1__read__h620689; + wire [46 : 0] r1__read__h619405, r1__read__h620582; + wire [45 : 0] r1__read__h619407, r1__read__h620584; + wire [44 : 0] r1__read__h619409, r1__read__h620586; + wire [43 : 0] r1__read__h619411, r1__read__h620588; + wire [42 : 0] r1__read__h620590; + wire [41 : 0] r1__read__h620592; + wire [40 : 0] r1__read__h620594; wire [37 : 0] IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14222, IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14383; wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5, - data79261_BITS_31_TO_0__q2, - data80193_BITS_31_TO_0__q6, - imm__h661838, - r1__read__h619414, - r1__read__h620597, - x__h196066, - x__h342534, - x__h388236, - x__h433931, + data79260_BITS_31_TO_0__q2, + data80192_BITS_31_TO_0__q6, + imm__h661836, + r1__read__h619413, + r1__read__h620596, + x__h196065, + x__h342533, + x__h388235, + x__h433930, x__h75783, x_data__h65632, - x_data_imm__h681438, - x_data_imm__h697342; - wire [29 : 0] r1__read__h619416, r1__read__h620599; - wire [27 : 0] r1__read__h620601; + x_data_imm__h681436, + x_data_imm__h697340; + wire [29 : 0] r1__read__h619415, r1__read__h620598; + wire [27 : 0] r1__read__h620600; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14268, - sfd__h358938, - sfd__h367520, - sfd__h376704, - sfd__h385316, - sfd__h404635, - sfd__h413217, - sfd__h422401, - sfd__h431013, - sfd__h450330, - sfd__h458912, - sfd__h468096, - sfd__h476708, - value__h492471, - value__h531324, - value__h570628; + sfd__h358937, + sfd__h367519, + sfd__h376703, + sfd__h385315, + sfd__h404634, + sfd__h413216, + sfd__h422400, + sfd__h431012, + sfd__h450329, + sfd__h458911, + sfd__h468095, + sfd__h476707, + value__h492470, + value__h531323, + value__h570627; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445, @@ -5035,67 +5029,67 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904, - _theResult___fst_sfd__h359444, - _theResult___fst_sfd__h368026, - _theResult___fst_sfd__h377210, - _theResult___fst_sfd__h385846, - _theResult___fst_sfd__h385855, - _theResult___fst_sfd__h385861, - _theResult___fst_sfd__h405141, - _theResult___fst_sfd__h413723, - _theResult___fst_sfd__h422907, - _theResult___fst_sfd__h431543, - _theResult___fst_sfd__h431552, - _theResult___fst_sfd__h431558, - _theResult___fst_sfd__h450836, - _theResult___fst_sfd__h459418, - _theResult___fst_sfd__h468602, - _theResult___fst_sfd__h477238, - _theResult___fst_sfd__h477247, - _theResult___fst_sfd__h477253, - _theResult___sfd__h359363, - _theResult___sfd__h367945, - _theResult___sfd__h377129, - _theResult___sfd__h385765, - _theResult___sfd__h385867, - _theResult___sfd__h405060, - _theResult___sfd__h413642, - _theResult___sfd__h422826, - _theResult___sfd__h431462, - _theResult___sfd__h431564, - _theResult___sfd__h450755, - _theResult___sfd__h459337, - _theResult___sfd__h468521, - _theResult___sfd__h477157, - _theResult___sfd__h477259, - _theResult___snd_fst_sfd__h343080, - _theResult___snd_fst_sfd__h368029, - _theResult___snd_fst_sfd__h385849, - _theResult___snd_fst_sfd__h388782, - _theResult___snd_fst_sfd__h413726, - _theResult___snd_fst_sfd__h431546, - _theResult___snd_fst_sfd__h434477, - _theResult___snd_fst_sfd__h459421, - _theResult___snd_fst_sfd__h477241, - f1_sfd__h487527, - f2_sfd__h526521, - f3_sfd__h565825, - out_f_sfd__h386144, - out_f_sfd__h431841, - out_f_sfd__h477536, - out_sfd__h359366, - out_sfd__h367948, - out_sfd__h377132, - out_sfd__h385768, - out_sfd__h405063, - out_sfd__h413645, - out_sfd__h422829, - out_sfd__h431465, - out_sfd__h450758, - out_sfd__h459340, - out_sfd__h468524, - out_sfd__h477160; - wire [19 : 0] r1__read__h620536; + _theResult___fst_sfd__h359443, + _theResult___fst_sfd__h368025, + _theResult___fst_sfd__h377209, + _theResult___fst_sfd__h385845, + _theResult___fst_sfd__h385854, + _theResult___fst_sfd__h385860, + _theResult___fst_sfd__h405140, + _theResult___fst_sfd__h413722, + _theResult___fst_sfd__h422906, + _theResult___fst_sfd__h431542, + _theResult___fst_sfd__h431551, + _theResult___fst_sfd__h431557, + _theResult___fst_sfd__h450835, + _theResult___fst_sfd__h459417, + _theResult___fst_sfd__h468601, + _theResult___fst_sfd__h477237, + _theResult___fst_sfd__h477246, + _theResult___fst_sfd__h477252, + _theResult___sfd__h359362, + _theResult___sfd__h367944, + _theResult___sfd__h377128, + _theResult___sfd__h385764, + _theResult___sfd__h385866, + _theResult___sfd__h405059, + _theResult___sfd__h413641, + _theResult___sfd__h422825, + _theResult___sfd__h431461, + _theResult___sfd__h431563, + _theResult___sfd__h450754, + _theResult___sfd__h459336, + _theResult___sfd__h468520, + _theResult___sfd__h477156, + _theResult___sfd__h477258, + _theResult___snd_fst_sfd__h343079, + _theResult___snd_fst_sfd__h368028, + _theResult___snd_fst_sfd__h385848, + _theResult___snd_fst_sfd__h388781, + _theResult___snd_fst_sfd__h413725, + _theResult___snd_fst_sfd__h431545, + _theResult___snd_fst_sfd__h434476, + _theResult___snd_fst_sfd__h459420, + _theResult___snd_fst_sfd__h477240, + f1_sfd__h487526, + f2_sfd__h526520, + f3_sfd__h565824, + out_f_sfd__h386143, + out_f_sfd__h431840, + out_f_sfd__h477535, + out_sfd__h359365, + out_sfd__h367947, + out_sfd__h377131, + out_sfd__h385767, + out_sfd__h405062, + out_sfd__h413644, + out_sfd__h422828, + out_sfd__h431464, + out_sfd__h450757, + out_sfd__h459339, + out_sfd__h468523, + out_sfd__h477159; + wire [19 : 0] r1__read__h620535; wire [12 : 0] fetchStage_pipelines_1_first__2937_BIT_173_368_ETC___d13770; wire [11 : 0] IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542, @@ -5126,30 +5120,30 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434, - _theResult____h658027, - csr_addr__h661836, - enabled_ints___1__h658440, - enabled_ints__h658486, - pend_ints__h658025, - renaming_spec_bits__h689557, - result__h653734, - result__h653785, - spec_bits__h692684, - w__h653729, - x__h369117, - x__h414814, - x__h460509, - x__h508996, - x__h547849, - x__h587153, - x__h653733, - x__h653784, - y__h653763, - y__h658452, - y__h692697, - y_avValue_fst__h685981, - y_avValue_snd_fst__h686255, - y_avValue_snd_fst__h686290; + _theResult____h658025, + csr_addr__h661834, + enabled_ints___1__h658438, + enabled_ints__h658484, + pend_ints__h658023, + renaming_spec_bits__h689555, + result__h653732, + result__h653783, + spec_bits__h692682, + w__h653727, + x__h369116, + x__h414813, + x__h460508, + x__h508995, + x__h547848, + x__h587152, + x__h653731, + x__h653782, + y__h653761, + y__h658450, + y__h692695, + y_avValue_fst__h685979, + y_avValue_snd_fst__h686253, + y_avValue_snd_fst__h686288; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167, @@ -5171,103 +5165,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172, - _theResult___exp__h507569, - _theResult___exp__h517220, - _theResult___exp__h526004, - _theResult___exp__h546422, - _theResult___exp__h556073, - _theResult___exp__h564857, - _theResult___exp__h585726, - _theResult___exp__h595377, - _theResult___exp__h604161, - _theResult___fst_exp__h491841, - _theResult___fst_exp__h506905, - _theResult___fst_exp__h506911, - _theResult___fst_exp__h506914, - _theResult___fst_exp__h507669, - _theResult___fst_exp__h507672, - _theResult___fst_exp__h516491, - _theResult___fst_exp__h516556, - _theResult___fst_exp__h516562, - _theResult___fst_exp__h516565, - _theResult___fst_exp__h517320, - _theResult___fst_exp__h517323, - _theResult___fst_exp__h525276, - _theResult___fst_exp__h525315, - _theResult___fst_exp__h525321, - _theResult___fst_exp__h525324, - _theResult___fst_exp__h526104, - _theResult___fst_exp__h526107, - _theResult___fst_exp__h526116, - _theResult___fst_exp__h526119, - _theResult___fst_exp__h530694, - _theResult___fst_exp__h545758, - _theResult___fst_exp__h545764, - _theResult___fst_exp__h545767, - _theResult___fst_exp__h546522, - _theResult___fst_exp__h546525, - _theResult___fst_exp__h555344, - _theResult___fst_exp__h555409, - _theResult___fst_exp__h555415, - _theResult___fst_exp__h555418, - _theResult___fst_exp__h556173, - _theResult___fst_exp__h556176, - _theResult___fst_exp__h564129, - _theResult___fst_exp__h564168, - _theResult___fst_exp__h564174, - _theResult___fst_exp__h564177, - _theResult___fst_exp__h564957, - _theResult___fst_exp__h564960, - _theResult___fst_exp__h564969, - _theResult___fst_exp__h564972, - _theResult___fst_exp__h569998, - _theResult___fst_exp__h585062, - _theResult___fst_exp__h585068, - _theResult___fst_exp__h585071, - _theResult___fst_exp__h585826, - _theResult___fst_exp__h585829, - _theResult___fst_exp__h594648, - _theResult___fst_exp__h594713, - _theResult___fst_exp__h594719, - _theResult___fst_exp__h594722, - _theResult___fst_exp__h595477, - _theResult___fst_exp__h595480, - _theResult___fst_exp__h603433, - _theResult___fst_exp__h603472, - _theResult___fst_exp__h603478, - _theResult___fst_exp__h603481, - _theResult___fst_exp__h604261, - _theResult___fst_exp__h604264, - _theResult___fst_exp__h604273, - _theResult___fst_exp__h604276, - _theResult___snd_fst_exp__h507675, - _theResult___snd_fst_exp__h526110, - _theResult___snd_fst_exp__h546528, - _theResult___snd_fst_exp__h564963, - _theResult___snd_fst_exp__h585832, - _theResult___snd_fst_exp__h604267, + _theResult___exp__h507568, + _theResult___exp__h517219, + _theResult___exp__h526003, + _theResult___exp__h546421, + _theResult___exp__h556072, + _theResult___exp__h564856, + _theResult___exp__h585725, + _theResult___exp__h595376, + _theResult___exp__h604160, + _theResult___fst_exp__h491840, + _theResult___fst_exp__h506904, + _theResult___fst_exp__h506910, + _theResult___fst_exp__h506913, + _theResult___fst_exp__h507668, + _theResult___fst_exp__h507671, + _theResult___fst_exp__h516490, + _theResult___fst_exp__h516555, + _theResult___fst_exp__h516561, + _theResult___fst_exp__h516564, + _theResult___fst_exp__h517319, + _theResult___fst_exp__h517322, + _theResult___fst_exp__h525275, + _theResult___fst_exp__h525314, + _theResult___fst_exp__h525320, + _theResult___fst_exp__h525323, + _theResult___fst_exp__h526103, + _theResult___fst_exp__h526106, + _theResult___fst_exp__h526115, + _theResult___fst_exp__h526118, + _theResult___fst_exp__h530693, + _theResult___fst_exp__h545757, + _theResult___fst_exp__h545763, + _theResult___fst_exp__h545766, + _theResult___fst_exp__h546521, + _theResult___fst_exp__h546524, + _theResult___fst_exp__h555343, + _theResult___fst_exp__h555408, + _theResult___fst_exp__h555414, + _theResult___fst_exp__h555417, + _theResult___fst_exp__h556172, + _theResult___fst_exp__h556175, + _theResult___fst_exp__h564128, + _theResult___fst_exp__h564167, + _theResult___fst_exp__h564173, + _theResult___fst_exp__h564176, + _theResult___fst_exp__h564956, + _theResult___fst_exp__h564959, + _theResult___fst_exp__h564968, + _theResult___fst_exp__h564971, + _theResult___fst_exp__h569997, + _theResult___fst_exp__h585061, + _theResult___fst_exp__h585067, + _theResult___fst_exp__h585070, + _theResult___fst_exp__h585825, + _theResult___fst_exp__h585828, + _theResult___fst_exp__h594647, + _theResult___fst_exp__h594712, + _theResult___fst_exp__h594718, + _theResult___fst_exp__h594721, + _theResult___fst_exp__h595476, + _theResult___fst_exp__h595479, + _theResult___fst_exp__h603432, + _theResult___fst_exp__h603471, + _theResult___fst_exp__h603477, + _theResult___fst_exp__h603480, + _theResult___fst_exp__h604260, + _theResult___fst_exp__h604263, + _theResult___fst_exp__h604272, + _theResult___fst_exp__h604275, + _theResult___snd_fst_exp__h507674, + _theResult___snd_fst_exp__h526109, + _theResult___snd_fst_exp__h546527, + _theResult___snd_fst_exp__h564962, + _theResult___snd_fst_exp__h585831, + _theResult___snd_fst_exp__h604266, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99, - din_inc___2_exp__h526164, - din_inc___2_exp__h526199, - din_inc___2_exp__h526225, - din_inc___2_exp__h565017, - din_inc___2_exp__h565052, - din_inc___2_exp__h565078, - din_inc___2_exp__h604321, - din_inc___2_exp__h604356, - din_inc___2_exp__h604382, - out_exp__h507572, - out_exp__h517223, - out_exp__h526007, - out_exp__h546425, - out_exp__h556076, - out_exp__h564860, - out_exp__h585729, - out_exp__h595380, - out_exp__h604164; - wire [9 : 0] r1__read_BITS_9_TO_0___h658462; + din_inc___2_exp__h526163, + din_inc___2_exp__h526198, + din_inc___2_exp__h526224, + din_inc___2_exp__h565016, + din_inc___2_exp__h565051, + din_inc___2_exp__h565077, + din_inc___2_exp__h604320, + din_inc___2_exp__h604355, + din_inc___2_exp__h604381, + out_exp__h507571, + out_exp__h517222, + out_exp__h526006, + out_exp__h546424, + out_exp__h556075, + out_exp__h564859, + out_exp__h585728, + out_exp__h595379, + out_exp__h604163; + wire [9 : 0] r1__read_BITS_9_TO_0___h658460; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752; @@ -5298,125 +5292,125 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105, - _theResult___exp__h359362, - _theResult___exp__h367944, - _theResult___exp__h377128, - _theResult___exp__h385764, - _theResult___exp__h385866, - _theResult___exp__h405059, - _theResult___exp__h413641, - _theResult___exp__h422825, - _theResult___exp__h431461, - _theResult___exp__h431563, - _theResult___exp__h450754, - _theResult___exp__h459336, - _theResult___exp__h468520, - _theResult___exp__h477156, - _theResult___exp__h477258, - _theResult___fst_exp__h358846, - _theResult___fst_exp__h358911, - _theResult___fst_exp__h358917, - _theResult___fst_exp__h358920, - _theResult___fst_exp__h359443, - _theResult___fst_exp__h367493, - _theResult___fst_exp__h367499, - _theResult___fst_exp__h367502, - _theResult___fst_exp__h368025, - _theResult___fst_exp__h376612, - _theResult___fst_exp__h376677, - _theResult___fst_exp__h376683, - _theResult___fst_exp__h376686, - _theResult___fst_exp__h377209, - _theResult___fst_exp__h385249, - _theResult___fst_exp__h385288, - _theResult___fst_exp__h385294, - _theResult___fst_exp__h385297, - _theResult___fst_exp__h385845, - _theResult___fst_exp__h385854, - _theResult___fst_exp__h385857, - _theResult___fst_exp__h404543, - _theResult___fst_exp__h404608, - _theResult___fst_exp__h404614, - _theResult___fst_exp__h404617, - _theResult___fst_exp__h405140, - _theResult___fst_exp__h413190, - _theResult___fst_exp__h413196, - _theResult___fst_exp__h413199, - _theResult___fst_exp__h413722, - _theResult___fst_exp__h422309, - _theResult___fst_exp__h422374, - _theResult___fst_exp__h422380, - _theResult___fst_exp__h422383, - _theResult___fst_exp__h422906, - _theResult___fst_exp__h430946, - _theResult___fst_exp__h430985, - _theResult___fst_exp__h430991, - _theResult___fst_exp__h430994, - _theResult___fst_exp__h431542, - _theResult___fst_exp__h431551, - _theResult___fst_exp__h431554, - _theResult___fst_exp__h450238, - _theResult___fst_exp__h450303, - _theResult___fst_exp__h450309, - _theResult___fst_exp__h450312, - _theResult___fst_exp__h450835, - _theResult___fst_exp__h458885, - _theResult___fst_exp__h458891, - _theResult___fst_exp__h458894, - _theResult___fst_exp__h459417, - _theResult___fst_exp__h468004, - _theResult___fst_exp__h468069, - _theResult___fst_exp__h468075, - _theResult___fst_exp__h468078, - _theResult___fst_exp__h468601, - _theResult___fst_exp__h476641, - _theResult___fst_exp__h476680, - _theResult___fst_exp__h476686, - _theResult___fst_exp__h476689, - _theResult___fst_exp__h477237, - _theResult___fst_exp__h477246, - _theResult___fst_exp__h477249, - _theResult___snd_fst_exp__h368028, - _theResult___snd_fst_exp__h385848, - _theResult___snd_fst_exp__h413725, - _theResult___snd_fst_exp__h431545, - _theResult___snd_fst_exp__h459420, - _theResult___snd_fst_exp__h477240, + _theResult___exp__h359361, + _theResult___exp__h367943, + _theResult___exp__h377127, + _theResult___exp__h385763, + _theResult___exp__h385865, + _theResult___exp__h405058, + _theResult___exp__h413640, + _theResult___exp__h422824, + _theResult___exp__h431460, + _theResult___exp__h431562, + _theResult___exp__h450753, + _theResult___exp__h459335, + _theResult___exp__h468519, + _theResult___exp__h477155, + _theResult___exp__h477257, + _theResult___fst_exp__h358845, + _theResult___fst_exp__h358910, + _theResult___fst_exp__h358916, + _theResult___fst_exp__h358919, + _theResult___fst_exp__h359442, + _theResult___fst_exp__h367492, + _theResult___fst_exp__h367498, + _theResult___fst_exp__h367501, + _theResult___fst_exp__h368024, + _theResult___fst_exp__h376611, + _theResult___fst_exp__h376676, + _theResult___fst_exp__h376682, + _theResult___fst_exp__h376685, + _theResult___fst_exp__h377208, + _theResult___fst_exp__h385248, + _theResult___fst_exp__h385287, + _theResult___fst_exp__h385293, + _theResult___fst_exp__h385296, + _theResult___fst_exp__h385844, + _theResult___fst_exp__h385853, + _theResult___fst_exp__h385856, + _theResult___fst_exp__h404542, + _theResult___fst_exp__h404607, + _theResult___fst_exp__h404613, + _theResult___fst_exp__h404616, + _theResult___fst_exp__h405139, + _theResult___fst_exp__h413189, + _theResult___fst_exp__h413195, + _theResult___fst_exp__h413198, + _theResult___fst_exp__h413721, + _theResult___fst_exp__h422308, + _theResult___fst_exp__h422373, + _theResult___fst_exp__h422379, + _theResult___fst_exp__h422382, + _theResult___fst_exp__h422905, + _theResult___fst_exp__h430945, + _theResult___fst_exp__h430984, + _theResult___fst_exp__h430990, + _theResult___fst_exp__h430993, + _theResult___fst_exp__h431541, + _theResult___fst_exp__h431550, + _theResult___fst_exp__h431553, + _theResult___fst_exp__h450237, + _theResult___fst_exp__h450302, + _theResult___fst_exp__h450308, + _theResult___fst_exp__h450311, + _theResult___fst_exp__h450834, + _theResult___fst_exp__h458884, + _theResult___fst_exp__h458890, + _theResult___fst_exp__h458893, + _theResult___fst_exp__h459416, + _theResult___fst_exp__h468003, + _theResult___fst_exp__h468068, + _theResult___fst_exp__h468074, + _theResult___fst_exp__h468077, + _theResult___fst_exp__h468600, + _theResult___fst_exp__h476640, + _theResult___fst_exp__h476679, + _theResult___fst_exp__h476685, + _theResult___fst_exp__h476688, + _theResult___fst_exp__h477236, + _theResult___fst_exp__h477245, + _theResult___fst_exp__h477248, + _theResult___snd_fst_exp__h368027, + _theResult___snd_fst_exp__h385847, + _theResult___snd_fst_exp__h413724, + _theResult___snd_fst_exp__h431544, + _theResult___snd_fst_exp__h459419, + _theResult___snd_fst_exp__h477239, csrf_external_int_en_vec_3_read__1844_AND_csrf_ETC___d12967, - din_inc___2_exp__h385879, - din_inc___2_exp__h385903, - din_inc___2_exp__h385933, - din_inc___2_exp__h385957, - din_inc___2_exp__h431576, - din_inc___2_exp__h431600, - din_inc___2_exp__h431630, - din_inc___2_exp__h431654, - din_inc___2_exp__h477271, - din_inc___2_exp__h477295, - din_inc___2_exp__h477325, - din_inc___2_exp__h477349, - f1_exp87526_MINUS_127__q128, - f1_exp__h487526, - f2_exp26520_MINUS_127__q168, - f2_exp__h526520, - f3_exp65824_MINUS_127__q145, - f3_exp__h565824, - out_exp__h359365, - out_exp__h367947, - out_exp__h377131, - out_exp__h385767, - out_exp__h405062, - out_exp__h413644, - out_exp__h422828, - out_exp__h431464, - out_exp__h450757, - out_exp__h459339, - out_exp__h468523, - out_exp__h477159, - out_f_exp__h386143, - out_f_exp__h431840, - out_f_exp__h477535, - x__h619373; + din_inc___2_exp__h385878, + din_inc___2_exp__h385902, + din_inc___2_exp__h385932, + din_inc___2_exp__h385956, + din_inc___2_exp__h431575, + din_inc___2_exp__h431599, + din_inc___2_exp__h431629, + din_inc___2_exp__h431653, + din_inc___2_exp__h477270, + din_inc___2_exp__h477294, + din_inc___2_exp__h477324, + din_inc___2_exp__h477348, + f1_exp87525_MINUS_127__q128, + f1_exp__h487525, + f2_exp26519_MINUS_127__q168, + f2_exp__h526519, + f3_exp65823_MINUS_127__q145, + f3_exp__h565823, + out_exp__h359364, + out_exp__h367946, + out_exp__h377130, + out_exp__h385766, + out_exp__h405061, + out_exp__h413643, + out_exp__h422827, + out_exp__h431463, + out_exp__h450756, + out_exp__h459338, + out_exp__h468522, + out_exp__h477158, + out_f_exp__h386142, + out_f_exp__h431839, + out_f_exp__h477534, + x__h619372; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127, @@ -5437,7 +5431,7 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15324, - x__h184871, + x__h184870, x__h710695; wire [4 : 0] IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14436, IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184, @@ -5458,19 +5452,19 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061, checkForException___d13160, checkForException___d13792, - fflags__h722582, - r1__read__h620939, - res_fflags__h342520, - res_fflags__h388222, - res_fflags__h433917, - rs1__h661837, - x__h155091, - x__h158638, - x__h161454, - x__h291824, - y_avValue_fst__h721559, - y_avValue_fst__h722501, - y_avValue_fst__h722529; + fflags__h722584, + r1__read__h620938, + res_fflags__h342519, + res_fflags__h388221, + res_fflags__h433916, + rs1__h661835, + x__h155090, + x__h158637, + x__h161453, + x__h291823, + y_avValue_fst__h721561, + y_avValue_fst__h722503, + y_avValue_fst__h722531; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879, @@ -5498,73 +5492,73 @@ module mkCore(CLK, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13385, cause_code__h707757, - vm_mode_reg__read__h620542; + vm_mode_reg__read__h620541; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, - _theResult_____2__h301171, - next_deqP___1__h301450, - v__h300591, - v__h300822, - x__h306801, - x_decodeInfo_frm__h661521; + _theResult_____2__h301170, + next_deqP___1__h301449, + v__h300590, + v__h300821, + x__h306800, + x_decodeInfo_frm__h661519; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205, - IF_sfdin04537_BIT_33_THEN_2_ELSE_0__q57, - IF_sfdin16485_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin22303_BIT_33_THEN_2_ELSE_0__q67, - IF_sfdin50232_BIT_33_THEN_2_ELSE_0__q92, - IF_sfdin55338_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin58840_BIT_33_THEN_2_ELSE_0__q22, - IF_sfdin67998_BIT_33_THEN_2_ELSE_0__q102, - IF_sfdin76606_BIT_33_THEN_2_ELSE_0__q32, - IF_sfdin94642_BIT_4_THEN_2_ELSE_0__q148, - IF_theResult___snd03427_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd06865_BIT_4_THEN_2_ELSE_0__q127, - IF_theResult___snd13150_BIT_33_THEN_2_ELSE_0__q59, - IF_theResult___snd25270_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd30940_BIT_33_THEN_2_ELSE_0__q72, - IF_theResult___snd45718_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd58845_BIT_33_THEN_2_ELSE_0__q94, - IF_theResult___snd64123_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd67453_BIT_33_THEN_2_ELSE_0__q24, - IF_theResult___snd76635_BIT_33_THEN_2_ELSE_0__q107, - IF_theResult___snd85022_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd85243_BIT_33_THEN_2_ELSE_0__q37, - guard__h350745, - guard__h359454, - guard__h368384, - guard__h377220, - guard__h396444, - guard__h405151, - guard__h414081, - guard__h422917, - guard__h442139, - guard__h450846, - guard__h459776, - guard__h468612, - guard__h498953, - guard__h508265, - guard__h517334, - guard__h537806, - guard__h547118, - guard__h556187, - guard__h577110, - guard__h586422, - guard__h595491, - prv__h724096, - prv__h724140, - r1__read_BITS_13_TO_12___h661706, - sbIdx__h158517, - v__h609619, - v__h609629, - v__h610687, - x__h718765, - x__h722829, - y_avValue_snd_snd_snd_fst__h721993, - y_avValue_snd_snd_snd_fst__h722652, - y_avValue_snd_snd_snd_fst__h722681; + IF_sfdin04536_BIT_33_THEN_2_ELSE_0__q57, + IF_sfdin16484_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin22302_BIT_33_THEN_2_ELSE_0__q67, + IF_sfdin50231_BIT_33_THEN_2_ELSE_0__q92, + IF_sfdin55337_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin58839_BIT_33_THEN_2_ELSE_0__q22, + IF_sfdin67997_BIT_33_THEN_2_ELSE_0__q102, + IF_sfdin76605_BIT_33_THEN_2_ELSE_0__q32, + IF_sfdin94641_BIT_4_THEN_2_ELSE_0__q148, + IF_theResult___snd03426_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd06864_BIT_4_THEN_2_ELSE_0__q127, + IF_theResult___snd13149_BIT_33_THEN_2_ELSE_0__q59, + IF_theResult___snd25269_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd30939_BIT_33_THEN_2_ELSE_0__q72, + IF_theResult___snd45717_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd58844_BIT_33_THEN_2_ELSE_0__q94, + IF_theResult___snd64122_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd67452_BIT_33_THEN_2_ELSE_0__q24, + IF_theResult___snd76634_BIT_33_THEN_2_ELSE_0__q107, + IF_theResult___snd85021_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd85242_BIT_33_THEN_2_ELSE_0__q37, + guard__h350744, + guard__h359453, + guard__h368383, + guard__h377219, + guard__h396443, + guard__h405150, + guard__h414080, + guard__h422916, + guard__h442138, + guard__h450845, + guard__h459775, + guard__h468611, + guard__h498952, + guard__h508264, + guard__h517333, + guard__h537805, + guard__h547117, + guard__h556186, + guard__h577109, + guard__h586421, + guard__h595490, + prv__h724098, + prv__h724142, + r1__read_BITS_13_TO_12___h661704, + sbIdx__h158516, + v__h609618, + v__h609628, + v__h610686, + x__h718766, + x__h722831, + y_avValue_snd_snd_snd_fst__h721995, + y_avValue_snd_snd_snd_fst__h722654, + y_avValue_snd_snd_snd_fst__h722683; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557, @@ -5991,7 +5985,7 @@ module mkCore(CLK, _dfoo18, _dfoo2, _dfoo20, - _dfoo28, + _dfoo26, _dfoo7, _dor1coreFix_aluExe_0_bypassWire_2$EN_wset, _dor1coreFix_aluExe_0_bypassWire_3$EN_wset, @@ -6017,11 +6011,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h309167, - _theResult_____2__h315161, - _theResult_____2__h323015, - _theResult_____2__h333359, - _theResult_____2__h336584, + _theResult_____2__h309166, + _theResult_____2__h315160, + _theResult_____2__h323014, + _theResult_____2__h333358, + _theResult_____2__h336583, coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369, coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410, coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382, @@ -6172,14 +6166,14 @@ module mkCore(CLK, fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14054, fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13889, fetchStage_pipelines_1_first__2937_BIT_68_3660_ETC___d14058, - guard__h368982, - guard__h414679, - guard__h460374, - guard__h508863, - guard__h547716, - guard__h587020, - idx__h689688, - k__h674093, + guard__h368981, + guard__h414678, + guard__h460373, + guard__h508862, + guard__h547715, + guard__h587019, + idx__h689686, + k__h674091, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6191,14 +6185,15 @@ module mkCore(CLK, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, msip__h75668, - next_deqP___1__h309446, - next_deqP___1__h315727, - next_deqP___1__h323581, - next_deqP___1__h333638, - next_deqP___1__h336863, - r1__read_BIT_20___h662370, - r__h619420, - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14022, + next_deqP___1__h309445, + next_deqP___1__h315726, + next_deqP___1__h323580, + next_deqP___1__h333637, + next_deqP___1__h336862, + r1__read_BIT_20___h662368, + r__h619419, + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407, + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14022, regRenamingTable_RDY_rename_1_getRename__4078__ETC___d14096, regRenamingTable_rename_0_canRename__3513_AND__ETC___d13583, regRenamingTable_rename_0_canRename__3513_AND__ETC___d13597, @@ -6217,21 +6212,20 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3632_AND__ETC___d14303, regRenamingTable_rename_1_canRename__3632_AND__ETC___d14387, regRenamingTable_rename_1_canRename__3632_AND__ETC___d14397, - rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407, rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13826, rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13960, rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13977, - v__h303936, - v__h304454, - v__h314450, - v__h314681, - v__h318326, - v__h318557, - v__h332927, - v__h333158, - v__h336152, - v__h336383, - x__h608935; + v__h303935, + v__h304453, + v__h314449, + v__h314680, + v__h318325, + v__h318556, + v__h332926, + v__h333157, + v__h336151, + v__h336382, + x__h608934; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -9214,32 +9208,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && - l2Tlb$RDY_toChildren_rsToC_deq && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && + l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9251,16 +9245,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9299,9 +9293,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -9601,7 +9595,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && !commitStage_commitTrap[165] && @@ -9650,8 +9644,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && rob$deqPort_0_deq_data[18] ; @@ -9879,8 +9873,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9891,8 +9885,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -9966,16 +9960,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -9986,8 +9980,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10025,8 +10019,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10123,8 +10117,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10141,8 +10135,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10164,8 +10158,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10312,8 +10306,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -10356,8 +10350,8 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; @@ -10376,8 +10370,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10608,8 +10602,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10653,9 +10647,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208 ; assign WILL_FIRE_RL_renameStage_doRenaming_Trap = CAN_FIRE_RL_renameStage_doRenaming_Trap && @@ -10664,8 +10658,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461 && rob$isEmpty ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -10749,7 +10743,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -10974,27 +10969,15 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == 6'd18) ; assign MUX_csrf_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && NOT_csrf_prv_reg_read__2956_ULE_1_4592_4656_OR_ETC___d14660 ; - assign MUX_csrf_mpp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; - assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; - assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; assign MUX_csrf_prv_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[257:253] == 5'd19 || rob$deqPort_0_deq_data[257:253] == 5'd20) ; - assign MUX_csrf_spp_reg$write_1__SEL_1 = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ; assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 = WILL_FIRE_RL_renameStage_doRenaming && fetchStage$pipelines_0_canDeq && @@ -11028,7 +11011,7 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[89] ; assign MUX_rf$write_3_wr_2__SEL_1 = MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[72] ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -11051,7 +11034,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[353:290], - x__h704087, + x__h704086, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 : @@ -11060,9 +11043,21 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = - commitStage_rg_serial_num + y__h722605 ; + commitStage_rg_serial_num + y__h722607 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h674093 == 1'd0 && + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + (k__h674091 == 1'd0 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, @@ -11083,22 +11078,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689557, + renaming_spec_bits__h689555, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -11186,7 +11169,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, @@ -11200,10 +11183,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h290391 } ; + x__h290390 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h291836, + x__h291835, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11211,7 +11194,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h294612, + addr__h294611, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11224,12 +11207,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h155091, x__h155097, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h155090, x__h155096, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h158638, x__h158644, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h158637, x__h158643, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h161454, - x__h161458, + { x__h161453, + x__h161457, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, @@ -11240,7 +11223,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255, - x__h163306, + x__h163305, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, @@ -11253,7 +11236,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h296627, + resp_addr__h296626, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11333,7 +11316,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h200346 } ; + x__h200345 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11368,8 +11351,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h195303 : - { {32{x__h196066[31]}}, x__h196066 } } ; + curData__h195302 : + { {32{x__h196065[31]}}, x__h196065 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -11402,7 +11385,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h722582 ; + csrf_fflags_reg | fflags__h722584 ; always@(IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 or robdeqPort_0_deq_data_BITS_95_TO_32__q262) begin @@ -11412,7 +11395,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13]; endcase end - assign MUX_csrf_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_ie_vec_1$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == 6'd8 || @@ -11420,7 +11403,7 @@ module mkCore(CLK, 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] : csrf_prev_ie_vec_1 ; - assign MUX_csrf_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_ie_vec_3$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == 6'd18) ? @@ -11428,10 +11411,10 @@ module mkCore(CLK, csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h719386 + 64'd1 ; + n__read__h719387 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h719386 + { 62'd0, x__h722829 } ; - assign MUX_csrf_mpp_reg$write_1__VAL_1 = + n__read__h719387 + { 62'd0, x__h722831 } ; + assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == 6'd18) ? @@ -11440,21 +11423,21 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__VAL_1 = commitStage_commitTrap[36] ? 64'd0 : trap_val__h708780 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 != 6'd8 && IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[5] ; - assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = + assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[257:253] == 5'd19) ? - x__h718765 : + x__h718766 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 ? @@ -11465,7 +11448,7 @@ module mkCore(CLK, (mmio_pRqQ_data_0[37:36] == 2'd2) ? mmio_pRqQ_data_0[0] : amoExec___d882[0] ; - assign MUX_csrf_spp_reg$write_1__VAL_1 = + assign MUX_csrf_spp_reg$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == 6'd8 || @@ -11477,12 +11460,12 @@ module mkCore(CLK, y_avValue_new_pc__h710461 : y_avValue_new_pc__h710647 ; always@(rob$deqPort_0_deq_data or - next_pc__h718596 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h718597 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[257:253]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h718596; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h718597; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11517,24 +11500,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h342524 : - res_data__h342519 ; + res_data__h342523 : + res_data__h342518 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h388226 : - res_data__h388221 ; + res_data__h388225 : + res_data__h388220 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h433921 : - res_data__h433916 ; + res_data__h433920 : + res_data__h433915 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h479773 : - data__h479261 ; + data___1__h479772 : + data__h479260 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h480705 : - data__h480193 ; + data___1__h480704 : + data__h480192 ; assign MUX_rf$write_3_wr_2__VAL_4 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -11606,24 +11589,24 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h342520 ; + res_fflags__h342519 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h388222 ; + res_fflags__h388221 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h433917 ; + res_fflags__h433916 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -11961,8 +11944,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h610687 : - v__h609619 ; + v__h610686 : + v__h609618 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -12023,7 +12006,9 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd0 && @@ -12033,9 +12018,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd1 && @@ -12045,7 +12028,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd2 && @@ -12055,7 +12038,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd3 && @@ -12065,7 +12048,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd4 && @@ -12075,7 +12058,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd5 && @@ -12085,7 +12068,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd6 && @@ -12095,7 +12078,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7 && @@ -12108,7 +12091,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h301171 ; + _theResult_____2__h301170 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12130,7 +12113,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h300591 ; + v__h300590 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12152,7 +12135,12 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN ; + { !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT || + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 || + (EN_dCacheToParent_fromP_enq ? + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] : + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]), + IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343 } ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 && NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && @@ -12161,12 +12149,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN = - { !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT || - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 || - (EN_dCacheToParent_fromP_enq ? - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] : - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]), - IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343 } ; + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 && NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && @@ -12176,7 +12159,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - _theResult_____2__h309167 ; + _theResult_____2__h309166 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12194,7 +12177,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - v__h303936 ; + v__h303935 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12294,7 +12277,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - _theResult_____2__h315161 ; + _theResult_____2__h315160 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12312,7 +12295,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - v__h314450 ; + v__h314449 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12333,16 +12316,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN ; - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 && - NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && - IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 ; - - // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 - assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN = - { x_addr__h318724, + { x_addr__h318723, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12354,6 +12328,15 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ; + assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 && + NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && + IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 ; + + // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 + assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 && NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && @@ -12363,7 +12346,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - _theResult_____2__h323015 ; + _theResult_____2__h323014 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12381,7 +12364,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - v__h318326 ; + v__h318325 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12458,7 +12441,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - _theResult_____2__h336584 ; + _theResult_____2__h336583 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12476,7 +12459,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - v__h336152 ; + v__h336151 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12519,7 +12502,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - _theResult_____2__h333359 ; + _theResult_____2__h333358 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12537,7 +12520,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - v__h332927 ; + v__h332926 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12791,25 +12774,25 @@ module mkCore(CLK, // register csrf_ie_vec_1 assign csrf_ie_vec_1$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_1 && - MUX_csrf_ie_vec_1$write_1__VAL_1 ; + !MUX_csrf_ie_vec_1$write_1__SEL_1 && + MUX_csrf_ie_vec_1$write_1__VAL_2 ; assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 ; + csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_ie_vec_3 assign csrf_ie_vec_3$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_1 && - MUX_csrf_ie_vec_3$write_1__VAL_1 ; + !MUX_csrf_ie_vec_3$write_1__SEL_1 && + MUX_csrf_ie_vec_3$write_1__VAL_2 ; assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4592_4656_OR_ETC___d14660 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4592_4656_OR_ETC___d14660 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? cause_code__h707757 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = @@ -12822,7 +12805,7 @@ module mkCore(CLK, // register csrf_mcause_interrupt_reg assign csrf_mcause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_mcycle_ehr_data_lat_0$wget[63] ; assign csrf_mcause_interrupt_reg$EN = @@ -12888,7 +12871,7 @@ module mkCore(CLK, // register csrf_mepc_csr assign csrf_mepc_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_mepc_csr$EN = @@ -12940,16 +12923,16 @@ module mkCore(CLK, // register csrf_mpp_reg assign csrf_mpp_reg$D_IN = - MUX_csrf_mpp_reg$write_1__SEL_1 ? - MUX_csrf_mpp_reg$write_1__VAL_1 : - csrf_prv_reg ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_prv_reg : + MUX_csrf_mpp_reg$write_1__VAL_2 ; assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4592_4656_OR_ETC___d14660 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4592_4656_OR_ETC___d14660 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_mprv_reg - assign csrf_mprv_reg$D_IN = csrf_mscratch_csr$D_IN[17] ; + assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ; assign csrf_mprv_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && @@ -12966,7 +12949,7 @@ module mkCore(CLK, // register csrf_mtval_csr assign csrf_mtval_csr$D_IN = - MUX_csrf_ie_vec_3$write_1__SEL_2 ? + MUX_csrf_ie_vec_3$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_mtval_csr$EN = @@ -13023,23 +13006,23 @@ module mkCore(CLK, // register csrf_prev_ie_vec_1 assign csrf_prev_ie_vec_1$D_IN = - MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_1$write_1__VAL_1 : - csrf_ie_vec_1 ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_ie_vec_1 : + MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ; assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 ; + csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prev_ie_vec_3 assign csrf_prev_ie_vec_3$D_IN = - MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ? - MUX_csrf_prev_ie_vec_3$write_1__VAL_1 : - csrf_ie_vec_3 ; + MUX_csrf_ie_vec_3$write_1__SEL_1 ? + csrf_ie_vec_3 : + MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ; assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_csrf_prv_reg_read__2956_ULE_1_4592_4656_OR_ETC___d14660 ; + NOT_csrf_prv_reg_read__2956_ULE_1_4592_4656_OR_ETC___d14660 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ; // register csrf_prv_reg assign csrf_prv_reg$D_IN = @@ -13094,9 +13077,9 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? cause_code__h707757 : - csrf_rg_tselect$D_IN[3:0] ; + csrf_rg_tdata3$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 || @@ -13107,7 +13090,7 @@ module mkCore(CLK, // register csrf_scause_interrupt_reg assign csrf_scause_interrupt_reg$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[36] : csrf_rg_tselect$D_IN[63] ; assign csrf_scause_interrupt_reg$EN = @@ -13144,7 +13127,7 @@ module mkCore(CLK, // register csrf_sepc_csr assign csrf_sepc_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? commitStage_commitTrap[164:101] : rob$deqPort_0_deq_data[95:32] ; assign csrf_sepc_csr$EN = @@ -13202,13 +13185,13 @@ module mkCore(CLK, // register csrf_spp_reg assign csrf_spp_reg$D_IN = - MUX_csrf_spp_reg$write_1__SEL_1 ? - MUX_csrf_spp_reg$write_1__VAL_1 : - csrf_prv_reg[0] ; + MUX_csrf_ie_vec_1$write_1__SEL_1 ? + csrf_prv_reg[0] : + MUX_csrf_spp_reg$write_1__VAL_2 ; assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 ; + csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ; @@ -13224,7 +13207,7 @@ module mkCore(CLK, // register csrf_stval_csr assign csrf_stval_csr$D_IN = - MUX_csrf_ie_vec_1$write_1__SEL_2 ? + MUX_csrf_ie_vec_1$write_1__SEL_1 ? MUX_csrf_mtval_csr$write_1__VAL_1 : rob$deqPort_0_deq_data[95:32] ; assign csrf_stval_csr$EN = @@ -13739,8 +13722,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h646272, - x__h646273, + x__h646270, + x__h646271, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -13878,9 +13861,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -14030,8 +14013,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], + x__h623641, x__h623642, - x__h623643, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -14073,7 +14056,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h674093 == 1'd1 && + (k__h674091 == 1'd1 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, @@ -14094,7 +14077,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689557, + renaming_spec_bits__h689555, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14192,7 +14175,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h674093 == 1'd1 && + (k__h674091 == 1'd1 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171 || fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14290 == 1'd1 && @@ -14577,12 +14560,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h608909, - b__h608373 == 64'd0, - a__h608372, + { x__h608908, + b__h608372 == 64'd0, + a__h608371, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h608935, - a__h608372[63], + x__h608934, + a__h608371[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -14597,8 +14580,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h608921 : - b__h608373 ; + _theResult___snd__h608920 : + b__h608372 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14611,7 +14594,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h609549, + { x__h609548, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -14692,9 +14675,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], + x__h487047, x__h487048, x__h487049, - x__h487050, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ; @@ -14746,7 +14729,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689557, + renaming_spec_bits__h689555, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14904,8 +14887,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h291824, - x__h291836, + { x__h291823, + x__h291835, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890, @@ -14916,13 +14899,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921, - x__h293690, + x__h293689, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h290391 ; + x__h290390 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -15559,13 +15542,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h184737[2:0], - vaddr__h184737, + coreFix_memExe_lsq$getOrigBE << vaddr__h184736[2:0], + vaddr__h184736, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h184737[2:0] != 3'd0 : + vaddr__h184736[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h184737[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184737[0]), + vaddr__h184736[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184736[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ; @@ -15595,8 +15578,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h724140, - prv__h724140 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h724142, + prv__h724142 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15721,7 +15704,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3513_AND__ETC___d14240) ? specTagManager$currentSpecBits : - renaming_spec_bits__h689557 ; + renaming_spec_bits__h689555 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3513_AND__ETC___d14248) ? @@ -15741,7 +15724,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3513_AND__ETC___d14248) ? specTagManager$currentSpecBits : - renaming_spec_bits__h689557 ; + renaming_spec_bits__h689555 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15821,7 +15804,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h184742 ; + shiftData__h184741 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -15921,8 +15904,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], + x__h184648, x__h184649, - x__h184650, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ; @@ -16186,7 +16169,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14383, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689557, + renaming_spec_bits__h689555, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16899,7 +16882,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h689557 ; + renaming_spec_bits__h689555 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17166,7 +17149,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14377, IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14436, 7'd32, - renaming_spec_bits__h689557 } ; + renaming_spec_bits__h689555 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17176,24 +17159,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -17429,16 +17412,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -17715,10 +17698,10 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h195303), + .amoExec_current_data(curData__h195302), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h196841)); + .amoExec(n__h196840)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, @@ -17755,7 +17738,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 }, fetchStage$pipelines_0_first[160], - x_data_imm__h681438 } }), + x_data_imm__h681436 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17764,12 +17747,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h661521, - r1__read_BITS_13_TO_12___h661706 != + .checkForException_csrState({ x_decodeInfo_frm__h661519, + r1__read_BITS_13_TO_12___h661704 != 2'd0, - { prv__h724096, + { prv__h724098, csrf_tvm_reg, - { r1__read_BIT_20___h662370, + { r1__read_BIT_20___h662368, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17785,7 +17768,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686, { fetchStage_pipelines_1_first__2937_BIT_173_368_ETC___d13770, fetchStage$pipelines_1_first[160], - x_data_imm__h697342 } }), + x_data_imm__h697340 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17794,12 +17777,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h661521, - r1__read_BITS_13_TO_12___h661706 != + .checkForException_csrState({ x_decodeInfo_frm__h661519, + r1__read_BITS_13_TO_12___h661704 != 2'd0, - { prv__h724096, + { prv__h724098, csrf_tvm_reg, - { r1__read_BIT_20___h662370, + { r1__read_BIT_20___h662368, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17814,1196 +17797,1196 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h487142), - .execFpuSimple_rVal2(rVal2__h487143), + .execFpuSimple_rVal1(rVal1__h487141), + .execFpuSimple_rVal2(rVal2__h487142), .execFpuSimple(execFpuSimple___d11167)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ? - _theResult___snd__h358909 : - _theResult____h350735 ; + _theResult___snd__h358908 : + _theResult____h350734 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 ? - _theResult___snd__h404606 : - _theResult____h396434 ; + _theResult___snd__h404605 : + _theResult____h396433 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 ? - _theResult___snd__h450301 : - _theResult____h442129 ; + _theResult___snd__h450300 : + _theResult____h442128 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 ? - _theResult___snd__h516554 : - _theResult____h508255 ; + _theResult___snd__h516553 : + _theResult____h508254 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723 ? - _theResult___snd__h594711 : - _theResult____h586412 ; + _theResult___snd__h594710 : + _theResult____h586411 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 ? - _theResult___snd__h555407 : - _theResult____h547108 ; + _theResult___snd__h555406 : + _theResult____h547107 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 ? - _theResult___snd__h468067 : - _theResult____h459766 ; + _theResult___snd__h468066 : + _theResult____h459765 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896 ? - _theResult___snd__h376675 : - _theResult____h368374 ; + _theResult___snd__h376674 : + _theResult____h368373 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 ? - _theResult___snd__h422372 : - _theResult____h414071 ; + _theResult___snd__h422371 : + _theResult____h414070 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 ? - _theResult___snd__h506903 : + _theResult___snd__h506902 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058 ? - _theResult___snd__h506903 : - _theResult___snd__h525308 ; + _theResult___snd__h506902 : + _theResult___snd__h525307 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426 ? - _theResult___snd__h585060 : + _theResult___snd__h585059 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773 ? - _theResult___snd__h585060 : - _theResult___snd__h603465 ; + _theResult___snd__h585059 : + _theResult___snd__h603464 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 ? - _theResult___snd__h545756 : + _theResult___snd__h545755 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543 ? - _theResult___snd__h545756 : - _theResult___snd__h564161 ; + _theResult___snd__h545755 : + _theResult___snd__h564160 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ? - _theResult___snd__h458883 : - _theResult___snd__h476673 ; + _theResult___snd__h458882 : + _theResult___snd__h476672 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ? - _theResult___snd__h367491 : + _theResult___snd__h367490 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969 ? - _theResult___snd__h367491 : - _theResult___snd__h385281 ; + _theResult___snd__h367490 : + _theResult___snd__h385280 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 ? - _theResult___snd__h413188 : + _theResult___snd__h413187 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361 ? - _theResult___snd__h413188 : - _theResult___snd__h430978 ; + _theResult___snd__h413187 : + _theResult___snd__h430977 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 ? - _theResult___snd__h458883 : + _theResult___snd__h458882 : 57'd0 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h358846 == 8'd255) ? + ((_theResult___fst_exp__h358845 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150) : - ((_theResult___fst_exp__h367502 == 8'd255) ? + ((_theResult___fst_exp__h367501 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h358846 == 8'd255) ? + ((_theResult___fst_exp__h358845 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206) : - ((_theResult___fst_exp__h367502 == 8'd255) ? + ((_theResult___fst_exp__h367501 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h404543 == 8'd255) ? + ((_theResult___fst_exp__h404542 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542) : - ((_theResult___fst_exp__h413199 == 8'd255) ? + ((_theResult___fst_exp__h413198 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h404543 == 8'd255) ? + ((_theResult___fst_exp__h404542 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598) : - ((_theResult___fst_exp__h413199 == 8'd255) ? + ((_theResult___fst_exp__h413198 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h450238 == 8'd255) ? + ((_theResult___fst_exp__h450237 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934) : - ((_theResult___fst_exp__h458894 == 8'd255) ? + ((_theResult___fst_exp__h458893 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h450238 == 8'd255) ? + ((_theResult___fst_exp__h450237 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990) : - ((_theResult___fst_exp__h458894 == 8'd255) ? + ((_theResult___fst_exp__h458893 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 = - (_theResult____h350735[56] ? + (_theResult____h350734[56] ? 6'd0 : - (_theResult____h350735[55] ? + (_theResult____h350734[55] ? 6'd1 : - (_theResult____h350735[54] ? + (_theResult____h350734[54] ? 6'd2 : - (_theResult____h350735[53] ? + (_theResult____h350734[53] ? 6'd3 : - (_theResult____h350735[52] ? + (_theResult____h350734[52] ? 6'd4 : - (_theResult____h350735[51] ? + (_theResult____h350734[51] ? 6'd5 : - (_theResult____h350735[50] ? + (_theResult____h350734[50] ? 6'd6 : - (_theResult____h350735[49] ? + (_theResult____h350734[49] ? 6'd7 : - (_theResult____h350735[48] ? + (_theResult____h350734[48] ? 6'd8 : - (_theResult____h350735[47] ? + (_theResult____h350734[47] ? 6'd9 : - (_theResult____h350735[46] ? + (_theResult____h350734[46] ? 6'd10 : - (_theResult____h350735[45] ? + (_theResult____h350734[45] ? 6'd11 : - (_theResult____h350735[44] ? + (_theResult____h350734[44] ? 6'd12 : - (_theResult____h350735[43] ? + (_theResult____h350734[43] ? 6'd13 : - (_theResult____h350735[42] ? + (_theResult____h350734[42] ? 6'd14 : - (_theResult____h350735[41] ? + (_theResult____h350734[41] ? 6'd15 : - (_theResult____h350735[40] ? + (_theResult____h350734[40] ? 6'd16 : - (_theResult____h350735[39] ? + (_theResult____h350734[39] ? 6'd17 : - (_theResult____h350735[38] ? + (_theResult____h350734[38] ? 6'd18 : - (_theResult____h350735[37] ? + (_theResult____h350734[37] ? 6'd19 : - (_theResult____h350735[36] ? + (_theResult____h350734[36] ? 6'd20 : - (_theResult____h350735[35] ? + (_theResult____h350734[35] ? 6'd21 : - (_theResult____h350735[34] ? + (_theResult____h350734[34] ? 6'd22 : - (_theResult____h350735[33] ? + (_theResult____h350734[33] ? 6'd23 : - (_theResult____h350735[32] ? + (_theResult____h350734[32] ? 6'd24 : - (_theResult____h350735[31] ? + (_theResult____h350734[31] ? 6'd25 : - (_theResult____h350735[30] ? + (_theResult____h350734[30] ? 6'd26 : - (_theResult____h350735[29] ? + (_theResult____h350734[29] ? 6'd27 : - (_theResult____h350735[28] ? + (_theResult____h350734[28] ? 6'd28 : - (_theResult____h350735[27] ? + (_theResult____h350734[27] ? 6'd29 : - (_theResult____h350735[26] ? + (_theResult____h350734[26] ? 6'd30 : - (_theResult____h350735[25] ? + (_theResult____h350734[25] ? 6'd31 : - (_theResult____h350735[24] ? + (_theResult____h350734[24] ? 6'd32 : - (_theResult____h350735[23] ? + (_theResult____h350734[23] ? 6'd33 : - (_theResult____h350735[22] ? + (_theResult____h350734[22] ? 6'd34 : - (_theResult____h350735[21] ? + (_theResult____h350734[21] ? 6'd35 : - (_theResult____h350735[20] ? + (_theResult____h350734[20] ? 6'd36 : - (_theResult____h350735[19] ? + (_theResult____h350734[19] ? 6'd37 : - (_theResult____h350735[18] ? + (_theResult____h350734[18] ? 6'd38 : - (_theResult____h350735[17] ? + (_theResult____h350734[17] ? 6'd39 : - (_theResult____h350735[16] ? + (_theResult____h350734[16] ? 6'd40 : - (_theResult____h350735[15] ? + (_theResult____h350734[15] ? 6'd41 : - (_theResult____h350735[14] ? + (_theResult____h350734[14] ? 6'd42 : - (_theResult____h350735[13] ? + (_theResult____h350734[13] ? 6'd43 : - (_theResult____h350735[12] ? + (_theResult____h350734[12] ? 6'd44 : - (_theResult____h350735[11] ? + (_theResult____h350734[11] ? 6'd45 : - (_theResult____h350735[10] ? + (_theResult____h350734[10] ? 6'd46 : - (_theResult____h350735[9] ? + (_theResult____h350734[9] ? 6'd47 : - (_theResult____h350735[8] ? + (_theResult____h350734[8] ? 6'd48 : - (_theResult____h350735[7] ? + (_theResult____h350734[7] ? 6'd49 : - (_theResult____h350735[6] ? + (_theResult____h350734[6] ? 6'd50 : - (_theResult____h350735[5] ? + (_theResult____h350734[5] ? 6'd51 : - (_theResult____h350735[4] ? + (_theResult____h350734[4] ? 6'd52 : - (_theResult____h350735[3] ? + (_theResult____h350734[3] ? 6'd53 : - (_theResult____h350735[2] ? + (_theResult____h350734[2] ? 6'd54 : - (_theResult____h350735[1] ? + (_theResult____h350734[1] ? 6'd55 : - (_theResult____h350735[0] ? + (_theResult____h350734[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 = - (_theResult____h396434[56] ? + (_theResult____h396433[56] ? 6'd0 : - (_theResult____h396434[55] ? + (_theResult____h396433[55] ? 6'd1 : - (_theResult____h396434[54] ? + (_theResult____h396433[54] ? 6'd2 : - (_theResult____h396434[53] ? + (_theResult____h396433[53] ? 6'd3 : - (_theResult____h396434[52] ? + (_theResult____h396433[52] ? 6'd4 : - (_theResult____h396434[51] ? + (_theResult____h396433[51] ? 6'd5 : - (_theResult____h396434[50] ? + (_theResult____h396433[50] ? 6'd6 : - (_theResult____h396434[49] ? + (_theResult____h396433[49] ? 6'd7 : - (_theResult____h396434[48] ? + (_theResult____h396433[48] ? 6'd8 : - (_theResult____h396434[47] ? + (_theResult____h396433[47] ? 6'd9 : - (_theResult____h396434[46] ? + (_theResult____h396433[46] ? 6'd10 : - (_theResult____h396434[45] ? + (_theResult____h396433[45] ? 6'd11 : - (_theResult____h396434[44] ? + (_theResult____h396433[44] ? 6'd12 : - (_theResult____h396434[43] ? + (_theResult____h396433[43] ? 6'd13 : - (_theResult____h396434[42] ? + (_theResult____h396433[42] ? 6'd14 : - (_theResult____h396434[41] ? + (_theResult____h396433[41] ? 6'd15 : - (_theResult____h396434[40] ? + (_theResult____h396433[40] ? 6'd16 : - (_theResult____h396434[39] ? + (_theResult____h396433[39] ? 6'd17 : - (_theResult____h396434[38] ? + (_theResult____h396433[38] ? 6'd18 : - (_theResult____h396434[37] ? + (_theResult____h396433[37] ? 6'd19 : - (_theResult____h396434[36] ? + (_theResult____h396433[36] ? 6'd20 : - (_theResult____h396434[35] ? + (_theResult____h396433[35] ? 6'd21 : - (_theResult____h396434[34] ? + (_theResult____h396433[34] ? 6'd22 : - (_theResult____h396434[33] ? + (_theResult____h396433[33] ? 6'd23 : - (_theResult____h396434[32] ? + (_theResult____h396433[32] ? 6'd24 : - (_theResult____h396434[31] ? + (_theResult____h396433[31] ? 6'd25 : - (_theResult____h396434[30] ? + (_theResult____h396433[30] ? 6'd26 : - (_theResult____h396434[29] ? + (_theResult____h396433[29] ? 6'd27 : - (_theResult____h396434[28] ? + (_theResult____h396433[28] ? 6'd28 : - (_theResult____h396434[27] ? + (_theResult____h396433[27] ? 6'd29 : - (_theResult____h396434[26] ? + (_theResult____h396433[26] ? 6'd30 : - (_theResult____h396434[25] ? + (_theResult____h396433[25] ? 6'd31 : - (_theResult____h396434[24] ? + (_theResult____h396433[24] ? 6'd32 : - (_theResult____h396434[23] ? + (_theResult____h396433[23] ? 6'd33 : - (_theResult____h396434[22] ? + (_theResult____h396433[22] ? 6'd34 : - (_theResult____h396434[21] ? + (_theResult____h396433[21] ? 6'd35 : - (_theResult____h396434[20] ? + (_theResult____h396433[20] ? 6'd36 : - (_theResult____h396434[19] ? + (_theResult____h396433[19] ? 6'd37 : - (_theResult____h396434[18] ? + (_theResult____h396433[18] ? 6'd38 : - (_theResult____h396434[17] ? + (_theResult____h396433[17] ? 6'd39 : - (_theResult____h396434[16] ? + (_theResult____h396433[16] ? 6'd40 : - (_theResult____h396434[15] ? + (_theResult____h396433[15] ? 6'd41 : - (_theResult____h396434[14] ? + (_theResult____h396433[14] ? 6'd42 : - (_theResult____h396434[13] ? + (_theResult____h396433[13] ? 6'd43 : - (_theResult____h396434[12] ? + (_theResult____h396433[12] ? 6'd44 : - (_theResult____h396434[11] ? + (_theResult____h396433[11] ? 6'd45 : - (_theResult____h396434[10] ? + (_theResult____h396433[10] ? 6'd46 : - (_theResult____h396434[9] ? + (_theResult____h396433[9] ? 6'd47 : - (_theResult____h396434[8] ? + (_theResult____h396433[8] ? 6'd48 : - (_theResult____h396434[7] ? + (_theResult____h396433[7] ? 6'd49 : - (_theResult____h396434[6] ? + (_theResult____h396433[6] ? 6'd50 : - (_theResult____h396434[5] ? + (_theResult____h396433[5] ? 6'd51 : - (_theResult____h396434[4] ? + (_theResult____h396433[4] ? 6'd52 : - (_theResult____h396434[3] ? + (_theResult____h396433[3] ? 6'd53 : - (_theResult____h396434[2] ? + (_theResult____h396433[2] ? 6'd54 : - (_theResult____h396434[1] ? + (_theResult____h396433[1] ? 6'd55 : - (_theResult____h396434[0] ? + (_theResult____h396433[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 = - (_theResult____h442129[56] ? + (_theResult____h442128[56] ? 6'd0 : - (_theResult____h442129[55] ? + (_theResult____h442128[55] ? 6'd1 : - (_theResult____h442129[54] ? + (_theResult____h442128[54] ? 6'd2 : - (_theResult____h442129[53] ? + (_theResult____h442128[53] ? 6'd3 : - (_theResult____h442129[52] ? + (_theResult____h442128[52] ? 6'd4 : - (_theResult____h442129[51] ? + (_theResult____h442128[51] ? 6'd5 : - (_theResult____h442129[50] ? + (_theResult____h442128[50] ? 6'd6 : - (_theResult____h442129[49] ? + (_theResult____h442128[49] ? 6'd7 : - (_theResult____h442129[48] ? + (_theResult____h442128[48] ? 6'd8 : - (_theResult____h442129[47] ? + (_theResult____h442128[47] ? 6'd9 : - (_theResult____h442129[46] ? + (_theResult____h442128[46] ? 6'd10 : - (_theResult____h442129[45] ? + (_theResult____h442128[45] ? 6'd11 : - (_theResult____h442129[44] ? + (_theResult____h442128[44] ? 6'd12 : - (_theResult____h442129[43] ? + (_theResult____h442128[43] ? 6'd13 : - (_theResult____h442129[42] ? + (_theResult____h442128[42] ? 6'd14 : - (_theResult____h442129[41] ? + (_theResult____h442128[41] ? 6'd15 : - (_theResult____h442129[40] ? + (_theResult____h442128[40] ? 6'd16 : - (_theResult____h442129[39] ? + (_theResult____h442128[39] ? 6'd17 : - (_theResult____h442129[38] ? + (_theResult____h442128[38] ? 6'd18 : - (_theResult____h442129[37] ? + (_theResult____h442128[37] ? 6'd19 : - (_theResult____h442129[36] ? + (_theResult____h442128[36] ? 6'd20 : - (_theResult____h442129[35] ? + (_theResult____h442128[35] ? 6'd21 : - (_theResult____h442129[34] ? + (_theResult____h442128[34] ? 6'd22 : - (_theResult____h442129[33] ? + (_theResult____h442128[33] ? 6'd23 : - (_theResult____h442129[32] ? + (_theResult____h442128[32] ? 6'd24 : - (_theResult____h442129[31] ? + (_theResult____h442128[31] ? 6'd25 : - (_theResult____h442129[30] ? + (_theResult____h442128[30] ? 6'd26 : - (_theResult____h442129[29] ? + (_theResult____h442128[29] ? 6'd27 : - (_theResult____h442129[28] ? + (_theResult____h442128[28] ? 6'd28 : - (_theResult____h442129[27] ? + (_theResult____h442128[27] ? 6'd29 : - (_theResult____h442129[26] ? + (_theResult____h442128[26] ? 6'd30 : - (_theResult____h442129[25] ? + (_theResult____h442128[25] ? 6'd31 : - (_theResult____h442129[24] ? + (_theResult____h442128[24] ? 6'd32 : - (_theResult____h442129[23] ? + (_theResult____h442128[23] ? 6'd33 : - (_theResult____h442129[22] ? + (_theResult____h442128[22] ? 6'd34 : - (_theResult____h442129[21] ? + (_theResult____h442128[21] ? 6'd35 : - (_theResult____h442129[20] ? + (_theResult____h442128[20] ? 6'd36 : - (_theResult____h442129[19] ? + (_theResult____h442128[19] ? 6'd37 : - (_theResult____h442129[18] ? + (_theResult____h442128[18] ? 6'd38 : - (_theResult____h442129[17] ? + (_theResult____h442128[17] ? 6'd39 : - (_theResult____h442129[16] ? + (_theResult____h442128[16] ? 6'd40 : - (_theResult____h442129[15] ? + (_theResult____h442128[15] ? 6'd41 : - (_theResult____h442129[14] ? + (_theResult____h442128[14] ? 6'd42 : - (_theResult____h442129[13] ? + (_theResult____h442128[13] ? 6'd43 : - (_theResult____h442129[12] ? + (_theResult____h442128[12] ? 6'd44 : - (_theResult____h442129[11] ? + (_theResult____h442128[11] ? 6'd45 : - (_theResult____h442129[10] ? + (_theResult____h442128[10] ? 6'd46 : - (_theResult____h442129[9] ? + (_theResult____h442128[9] ? 6'd47 : - (_theResult____h442129[8] ? + (_theResult____h442128[8] ? 6'd48 : - (_theResult____h442129[7] ? + (_theResult____h442128[7] ? 6'd49 : - (_theResult____h442129[6] ? + (_theResult____h442128[6] ? 6'd50 : - (_theResult____h442129[5] ? + (_theResult____h442128[5] ? 6'd51 : - (_theResult____h442129[4] ? + (_theResult____h442128[4] ? 6'd52 : - (_theResult____h442129[3] ? + (_theResult____h442128[3] ? 6'd53 : - (_theResult____h442129[2] ? + (_theResult____h442128[2] ? 6'd54 : - (_theResult____h442129[1] ? + (_theResult____h442128[1] ? 6'd55 : - (_theResult____h442129[0] ? + (_theResult____h442128[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 = - (_theResult____h547108[56] ? + (_theResult____h547107[56] ? 6'd0 : - (_theResult____h547108[55] ? + (_theResult____h547107[55] ? 6'd1 : - (_theResult____h547108[54] ? + (_theResult____h547107[54] ? 6'd2 : - (_theResult____h547108[53] ? + (_theResult____h547107[53] ? 6'd3 : - (_theResult____h547108[52] ? + (_theResult____h547107[52] ? 6'd4 : - (_theResult____h547108[51] ? + (_theResult____h547107[51] ? 6'd5 : - (_theResult____h547108[50] ? + (_theResult____h547107[50] ? 6'd6 : - (_theResult____h547108[49] ? + (_theResult____h547107[49] ? 6'd7 : - (_theResult____h547108[48] ? + (_theResult____h547107[48] ? 6'd8 : - (_theResult____h547108[47] ? + (_theResult____h547107[47] ? 6'd9 : - (_theResult____h547108[46] ? + (_theResult____h547107[46] ? 6'd10 : - (_theResult____h547108[45] ? + (_theResult____h547107[45] ? 6'd11 : - (_theResult____h547108[44] ? + (_theResult____h547107[44] ? 6'd12 : - (_theResult____h547108[43] ? + (_theResult____h547107[43] ? 6'd13 : - (_theResult____h547108[42] ? + (_theResult____h547107[42] ? 6'd14 : - (_theResult____h547108[41] ? + (_theResult____h547107[41] ? 6'd15 : - (_theResult____h547108[40] ? + (_theResult____h547107[40] ? 6'd16 : - (_theResult____h547108[39] ? + (_theResult____h547107[39] ? 6'd17 : - (_theResult____h547108[38] ? + (_theResult____h547107[38] ? 6'd18 : - (_theResult____h547108[37] ? + (_theResult____h547107[37] ? 6'd19 : - (_theResult____h547108[36] ? + (_theResult____h547107[36] ? 6'd20 : - (_theResult____h547108[35] ? + (_theResult____h547107[35] ? 6'd21 : - (_theResult____h547108[34] ? + (_theResult____h547107[34] ? 6'd22 : - (_theResult____h547108[33] ? + (_theResult____h547107[33] ? 6'd23 : - (_theResult____h547108[32] ? + (_theResult____h547107[32] ? 6'd24 : - (_theResult____h547108[31] ? + (_theResult____h547107[31] ? 6'd25 : - (_theResult____h547108[30] ? + (_theResult____h547107[30] ? 6'd26 : - (_theResult____h547108[29] ? + (_theResult____h547107[29] ? 6'd27 : - (_theResult____h547108[28] ? + (_theResult____h547107[28] ? 6'd28 : - (_theResult____h547108[27] ? + (_theResult____h547107[27] ? 6'd29 : - (_theResult____h547108[26] ? + (_theResult____h547107[26] ? 6'd30 : - (_theResult____h547108[25] ? + (_theResult____h547107[25] ? 6'd31 : - (_theResult____h547108[24] ? + (_theResult____h547107[24] ? 6'd32 : - (_theResult____h547108[23] ? + (_theResult____h547107[23] ? 6'd33 : - (_theResult____h547108[22] ? + (_theResult____h547107[22] ? 6'd34 : - (_theResult____h547108[21] ? + (_theResult____h547107[21] ? 6'd35 : - (_theResult____h547108[20] ? + (_theResult____h547107[20] ? 6'd36 : - (_theResult____h547108[19] ? + (_theResult____h547107[19] ? 6'd37 : - (_theResult____h547108[18] ? + (_theResult____h547107[18] ? 6'd38 : - (_theResult____h547108[17] ? + (_theResult____h547107[17] ? 6'd39 : - (_theResult____h547108[16] ? + (_theResult____h547107[16] ? 6'd40 : - (_theResult____h547108[15] ? + (_theResult____h547107[15] ? 6'd41 : - (_theResult____h547108[14] ? + (_theResult____h547107[14] ? 6'd42 : - (_theResult____h547108[13] ? + (_theResult____h547107[13] ? 6'd43 : - (_theResult____h547108[12] ? + (_theResult____h547107[12] ? 6'd44 : - (_theResult____h547108[11] ? + (_theResult____h547107[11] ? 6'd45 : - (_theResult____h547108[10] ? + (_theResult____h547107[10] ? 6'd46 : - (_theResult____h547108[9] ? + (_theResult____h547107[9] ? 6'd47 : - (_theResult____h547108[8] ? + (_theResult____h547107[8] ? 6'd48 : - (_theResult____h547108[7] ? + (_theResult____h547107[7] ? 6'd49 : - (_theResult____h547108[6] ? + (_theResult____h547107[6] ? 6'd50 : - (_theResult____h547108[5] ? + (_theResult____h547107[5] ? 6'd51 : - (_theResult____h547108[4] ? + (_theResult____h547107[4] ? 6'd52 : - (_theResult____h547108[3] ? + (_theResult____h547107[3] ? 6'd53 : - (_theResult____h547108[2] ? + (_theResult____h547107[2] ? 6'd54 : - (_theResult____h547108[1] ? + (_theResult____h547107[1] ? 6'd55 : - (_theResult____h547108[0] ? + (_theResult____h547107[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 = - (_theResult____h508255[56] ? + (_theResult____h508254[56] ? 6'd0 : - (_theResult____h508255[55] ? + (_theResult____h508254[55] ? 6'd1 : - (_theResult____h508255[54] ? + (_theResult____h508254[54] ? 6'd2 : - (_theResult____h508255[53] ? + (_theResult____h508254[53] ? 6'd3 : - (_theResult____h508255[52] ? + (_theResult____h508254[52] ? 6'd4 : - (_theResult____h508255[51] ? + (_theResult____h508254[51] ? 6'd5 : - (_theResult____h508255[50] ? + (_theResult____h508254[50] ? 6'd6 : - (_theResult____h508255[49] ? + (_theResult____h508254[49] ? 6'd7 : - (_theResult____h508255[48] ? + (_theResult____h508254[48] ? 6'd8 : - (_theResult____h508255[47] ? + (_theResult____h508254[47] ? 6'd9 : - (_theResult____h508255[46] ? + (_theResult____h508254[46] ? 6'd10 : - (_theResult____h508255[45] ? + (_theResult____h508254[45] ? 6'd11 : - (_theResult____h508255[44] ? + (_theResult____h508254[44] ? 6'd12 : - (_theResult____h508255[43] ? + (_theResult____h508254[43] ? 6'd13 : - (_theResult____h508255[42] ? + (_theResult____h508254[42] ? 6'd14 : - (_theResult____h508255[41] ? + (_theResult____h508254[41] ? 6'd15 : - (_theResult____h508255[40] ? + (_theResult____h508254[40] ? 6'd16 : - (_theResult____h508255[39] ? + (_theResult____h508254[39] ? 6'd17 : - (_theResult____h508255[38] ? + (_theResult____h508254[38] ? 6'd18 : - (_theResult____h508255[37] ? + (_theResult____h508254[37] ? 6'd19 : - (_theResult____h508255[36] ? + (_theResult____h508254[36] ? 6'd20 : - (_theResult____h508255[35] ? + (_theResult____h508254[35] ? 6'd21 : - (_theResult____h508255[34] ? + (_theResult____h508254[34] ? 6'd22 : - (_theResult____h508255[33] ? + (_theResult____h508254[33] ? 6'd23 : - (_theResult____h508255[32] ? + (_theResult____h508254[32] ? 6'd24 : - (_theResult____h508255[31] ? + (_theResult____h508254[31] ? 6'd25 : - (_theResult____h508255[30] ? + (_theResult____h508254[30] ? 6'd26 : - (_theResult____h508255[29] ? + (_theResult____h508254[29] ? 6'd27 : - (_theResult____h508255[28] ? + (_theResult____h508254[28] ? 6'd28 : - (_theResult____h508255[27] ? + (_theResult____h508254[27] ? 6'd29 : - (_theResult____h508255[26] ? + (_theResult____h508254[26] ? 6'd30 : - (_theResult____h508255[25] ? + (_theResult____h508254[25] ? 6'd31 : - (_theResult____h508255[24] ? + (_theResult____h508254[24] ? 6'd32 : - (_theResult____h508255[23] ? + (_theResult____h508254[23] ? 6'd33 : - (_theResult____h508255[22] ? + (_theResult____h508254[22] ? 6'd34 : - (_theResult____h508255[21] ? + (_theResult____h508254[21] ? 6'd35 : - (_theResult____h508255[20] ? + (_theResult____h508254[20] ? 6'd36 : - (_theResult____h508255[19] ? + (_theResult____h508254[19] ? 6'd37 : - (_theResult____h508255[18] ? + (_theResult____h508254[18] ? 6'd38 : - (_theResult____h508255[17] ? + (_theResult____h508254[17] ? 6'd39 : - (_theResult____h508255[16] ? + (_theResult____h508254[16] ? 6'd40 : - (_theResult____h508255[15] ? + (_theResult____h508254[15] ? 6'd41 : - (_theResult____h508255[14] ? + (_theResult____h508254[14] ? 6'd42 : - (_theResult____h508255[13] ? + (_theResult____h508254[13] ? 6'd43 : - (_theResult____h508255[12] ? + (_theResult____h508254[12] ? 6'd44 : - (_theResult____h508255[11] ? + (_theResult____h508254[11] ? 6'd45 : - (_theResult____h508255[10] ? + (_theResult____h508254[10] ? 6'd46 : - (_theResult____h508255[9] ? + (_theResult____h508254[9] ? 6'd47 : - (_theResult____h508255[8] ? + (_theResult____h508254[8] ? 6'd48 : - (_theResult____h508255[7] ? + (_theResult____h508254[7] ? 6'd49 : - (_theResult____h508255[6] ? + (_theResult____h508254[6] ? 6'd50 : - (_theResult____h508255[5] ? + (_theResult____h508254[5] ? 6'd51 : - (_theResult____h508255[4] ? + (_theResult____h508254[4] ? 6'd52 : - (_theResult____h508255[3] ? + (_theResult____h508254[3] ? 6'd53 : - (_theResult____h508255[2] ? + (_theResult____h508254[2] ? 6'd54 : - (_theResult____h508255[1] ? + (_theResult____h508254[1] ? 6'd55 : - (_theResult____h508255[0] ? + (_theResult____h508254[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 = - (_theResult____h586412[56] ? + (_theResult____h586411[56] ? 6'd0 : - (_theResult____h586412[55] ? + (_theResult____h586411[55] ? 6'd1 : - (_theResult____h586412[54] ? + (_theResult____h586411[54] ? 6'd2 : - (_theResult____h586412[53] ? + (_theResult____h586411[53] ? 6'd3 : - (_theResult____h586412[52] ? + (_theResult____h586411[52] ? 6'd4 : - (_theResult____h586412[51] ? + (_theResult____h586411[51] ? 6'd5 : - (_theResult____h586412[50] ? + (_theResult____h586411[50] ? 6'd6 : - (_theResult____h586412[49] ? + (_theResult____h586411[49] ? 6'd7 : - (_theResult____h586412[48] ? + (_theResult____h586411[48] ? 6'd8 : - (_theResult____h586412[47] ? + (_theResult____h586411[47] ? 6'd9 : - (_theResult____h586412[46] ? + (_theResult____h586411[46] ? 6'd10 : - (_theResult____h586412[45] ? + (_theResult____h586411[45] ? 6'd11 : - (_theResult____h586412[44] ? + (_theResult____h586411[44] ? 6'd12 : - (_theResult____h586412[43] ? + (_theResult____h586411[43] ? 6'd13 : - (_theResult____h586412[42] ? + (_theResult____h586411[42] ? 6'd14 : - (_theResult____h586412[41] ? + (_theResult____h586411[41] ? 6'd15 : - (_theResult____h586412[40] ? + (_theResult____h586411[40] ? 6'd16 : - (_theResult____h586412[39] ? + (_theResult____h586411[39] ? 6'd17 : - (_theResult____h586412[38] ? + (_theResult____h586411[38] ? 6'd18 : - (_theResult____h586412[37] ? + (_theResult____h586411[37] ? 6'd19 : - (_theResult____h586412[36] ? + (_theResult____h586411[36] ? 6'd20 : - (_theResult____h586412[35] ? + (_theResult____h586411[35] ? 6'd21 : - (_theResult____h586412[34] ? + (_theResult____h586411[34] ? 6'd22 : - (_theResult____h586412[33] ? + (_theResult____h586411[33] ? 6'd23 : - (_theResult____h586412[32] ? + (_theResult____h586411[32] ? 6'd24 : - (_theResult____h586412[31] ? + (_theResult____h586411[31] ? 6'd25 : - (_theResult____h586412[30] ? + (_theResult____h586411[30] ? 6'd26 : - (_theResult____h586412[29] ? + (_theResult____h586411[29] ? 6'd27 : - (_theResult____h586412[28] ? + (_theResult____h586411[28] ? 6'd28 : - (_theResult____h586412[27] ? + (_theResult____h586411[27] ? 6'd29 : - (_theResult____h586412[26] ? + (_theResult____h586411[26] ? 6'd30 : - (_theResult____h586412[25] ? + (_theResult____h586411[25] ? 6'd31 : - (_theResult____h586412[24] ? + (_theResult____h586411[24] ? 6'd32 : - (_theResult____h586412[23] ? + (_theResult____h586411[23] ? 6'd33 : - (_theResult____h586412[22] ? + (_theResult____h586411[22] ? 6'd34 : - (_theResult____h586412[21] ? + (_theResult____h586411[21] ? 6'd35 : - (_theResult____h586412[20] ? + (_theResult____h586411[20] ? 6'd36 : - (_theResult____h586412[19] ? + (_theResult____h586411[19] ? 6'd37 : - (_theResult____h586412[18] ? + (_theResult____h586411[18] ? 6'd38 : - (_theResult____h586412[17] ? + (_theResult____h586411[17] ? 6'd39 : - (_theResult____h586412[16] ? + (_theResult____h586411[16] ? 6'd40 : - (_theResult____h586412[15] ? + (_theResult____h586411[15] ? 6'd41 : - (_theResult____h586412[14] ? + (_theResult____h586411[14] ? 6'd42 : - (_theResult____h586412[13] ? + (_theResult____h586411[13] ? 6'd43 : - (_theResult____h586412[12] ? + (_theResult____h586411[12] ? 6'd44 : - (_theResult____h586412[11] ? + (_theResult____h586411[11] ? 6'd45 : - (_theResult____h586412[10] ? + (_theResult____h586411[10] ? 6'd46 : - (_theResult____h586412[9] ? + (_theResult____h586411[9] ? 6'd47 : - (_theResult____h586412[8] ? + (_theResult____h586411[8] ? 6'd48 : - (_theResult____h586412[7] ? + (_theResult____h586411[7] ? 6'd49 : - (_theResult____h586412[6] ? + (_theResult____h586411[6] ? 6'd50 : - (_theResult____h586412[5] ? + (_theResult____h586411[5] ? 6'd51 : - (_theResult____h586412[4] ? + (_theResult____h586411[4] ? 6'd52 : - (_theResult____h586412[3] ? + (_theResult____h586411[3] ? 6'd53 : - (_theResult____h586412[2] ? + (_theResult____h586411[2] ? 6'd54 : - (_theResult____h586412[1] ? + (_theResult____h586411[1] ? 6'd55 : - (_theResult____h586412[0] ? + (_theResult____h586411[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 = - (_theResult____h368374[56] ? + (_theResult____h368373[56] ? 6'd0 : - (_theResult____h368374[55] ? + (_theResult____h368373[55] ? 6'd1 : - (_theResult____h368374[54] ? + (_theResult____h368373[54] ? 6'd2 : - (_theResult____h368374[53] ? + (_theResult____h368373[53] ? 6'd3 : - (_theResult____h368374[52] ? + (_theResult____h368373[52] ? 6'd4 : - (_theResult____h368374[51] ? + (_theResult____h368373[51] ? 6'd5 : - (_theResult____h368374[50] ? + (_theResult____h368373[50] ? 6'd6 : - (_theResult____h368374[49] ? + (_theResult____h368373[49] ? 6'd7 : - (_theResult____h368374[48] ? + (_theResult____h368373[48] ? 6'd8 : - (_theResult____h368374[47] ? + (_theResult____h368373[47] ? 6'd9 : - (_theResult____h368374[46] ? + (_theResult____h368373[46] ? 6'd10 : - (_theResult____h368374[45] ? + (_theResult____h368373[45] ? 6'd11 : - (_theResult____h368374[44] ? + (_theResult____h368373[44] ? 6'd12 : - (_theResult____h368374[43] ? + (_theResult____h368373[43] ? 6'd13 : - (_theResult____h368374[42] ? + (_theResult____h368373[42] ? 6'd14 : - (_theResult____h368374[41] ? + (_theResult____h368373[41] ? 6'd15 : - (_theResult____h368374[40] ? + (_theResult____h368373[40] ? 6'd16 : - (_theResult____h368374[39] ? + (_theResult____h368373[39] ? 6'd17 : - (_theResult____h368374[38] ? + (_theResult____h368373[38] ? 6'd18 : - (_theResult____h368374[37] ? + (_theResult____h368373[37] ? 6'd19 : - (_theResult____h368374[36] ? + (_theResult____h368373[36] ? 6'd20 : - (_theResult____h368374[35] ? + (_theResult____h368373[35] ? 6'd21 : - (_theResult____h368374[34] ? + (_theResult____h368373[34] ? 6'd22 : - (_theResult____h368374[33] ? + (_theResult____h368373[33] ? 6'd23 : - (_theResult____h368374[32] ? + (_theResult____h368373[32] ? 6'd24 : - (_theResult____h368374[31] ? + (_theResult____h368373[31] ? 6'd25 : - (_theResult____h368374[30] ? + (_theResult____h368373[30] ? 6'd26 : - (_theResult____h368374[29] ? + (_theResult____h368373[29] ? 6'd27 : - (_theResult____h368374[28] ? + (_theResult____h368373[28] ? 6'd28 : - (_theResult____h368374[27] ? + (_theResult____h368373[27] ? 6'd29 : - (_theResult____h368374[26] ? + (_theResult____h368373[26] ? 6'd30 : - (_theResult____h368374[25] ? + (_theResult____h368373[25] ? 6'd31 : - (_theResult____h368374[24] ? + (_theResult____h368373[24] ? 6'd32 : - (_theResult____h368374[23] ? + (_theResult____h368373[23] ? 6'd33 : - (_theResult____h368374[22] ? + (_theResult____h368373[22] ? 6'd34 : - (_theResult____h368374[21] ? + (_theResult____h368373[21] ? 6'd35 : - (_theResult____h368374[20] ? + (_theResult____h368373[20] ? 6'd36 : - (_theResult____h368374[19] ? + (_theResult____h368373[19] ? 6'd37 : - (_theResult____h368374[18] ? + (_theResult____h368373[18] ? 6'd38 : - (_theResult____h368374[17] ? + (_theResult____h368373[17] ? 6'd39 : - (_theResult____h368374[16] ? + (_theResult____h368373[16] ? 6'd40 : - (_theResult____h368374[15] ? + (_theResult____h368373[15] ? 6'd41 : - (_theResult____h368374[14] ? + (_theResult____h368373[14] ? 6'd42 : - (_theResult____h368374[13] ? + (_theResult____h368373[13] ? 6'd43 : - (_theResult____h368374[12] ? + (_theResult____h368373[12] ? 6'd44 : - (_theResult____h368374[11] ? + (_theResult____h368373[11] ? 6'd45 : - (_theResult____h368374[10] ? + (_theResult____h368373[10] ? 6'd46 : - (_theResult____h368374[9] ? + (_theResult____h368373[9] ? 6'd47 : - (_theResult____h368374[8] ? + (_theResult____h368373[8] ? 6'd48 : - (_theResult____h368374[7] ? + (_theResult____h368373[7] ? 6'd49 : - (_theResult____h368374[6] ? + (_theResult____h368373[6] ? 6'd50 : - (_theResult____h368374[5] ? + (_theResult____h368373[5] ? 6'd51 : - (_theResult____h368374[4] ? + (_theResult____h368373[4] ? 6'd52 : - (_theResult____h368374[3] ? + (_theResult____h368373[3] ? 6'd53 : - (_theResult____h368374[2] ? + (_theResult____h368373[2] ? 6'd54 : - (_theResult____h368374[1] ? + (_theResult____h368373[1] ? 6'd55 : - (_theResult____h368374[0] ? + (_theResult____h368373[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 = - (_theResult____h414071[56] ? + (_theResult____h414070[56] ? 6'd0 : - (_theResult____h414071[55] ? + (_theResult____h414070[55] ? 6'd1 : - (_theResult____h414071[54] ? + (_theResult____h414070[54] ? 6'd2 : - (_theResult____h414071[53] ? + (_theResult____h414070[53] ? 6'd3 : - (_theResult____h414071[52] ? + (_theResult____h414070[52] ? 6'd4 : - (_theResult____h414071[51] ? + (_theResult____h414070[51] ? 6'd5 : - (_theResult____h414071[50] ? + (_theResult____h414070[50] ? 6'd6 : - (_theResult____h414071[49] ? + (_theResult____h414070[49] ? 6'd7 : - (_theResult____h414071[48] ? + (_theResult____h414070[48] ? 6'd8 : - (_theResult____h414071[47] ? + (_theResult____h414070[47] ? 6'd9 : - (_theResult____h414071[46] ? + (_theResult____h414070[46] ? 6'd10 : - (_theResult____h414071[45] ? + (_theResult____h414070[45] ? 6'd11 : - (_theResult____h414071[44] ? + (_theResult____h414070[44] ? 6'd12 : - (_theResult____h414071[43] ? + (_theResult____h414070[43] ? 6'd13 : - (_theResult____h414071[42] ? + (_theResult____h414070[42] ? 6'd14 : - (_theResult____h414071[41] ? + (_theResult____h414070[41] ? 6'd15 : - (_theResult____h414071[40] ? + (_theResult____h414070[40] ? 6'd16 : - (_theResult____h414071[39] ? + (_theResult____h414070[39] ? 6'd17 : - (_theResult____h414071[38] ? + (_theResult____h414070[38] ? 6'd18 : - (_theResult____h414071[37] ? + (_theResult____h414070[37] ? 6'd19 : - (_theResult____h414071[36] ? + (_theResult____h414070[36] ? 6'd20 : - (_theResult____h414071[35] ? + (_theResult____h414070[35] ? 6'd21 : - (_theResult____h414071[34] ? + (_theResult____h414070[34] ? 6'd22 : - (_theResult____h414071[33] ? + (_theResult____h414070[33] ? 6'd23 : - (_theResult____h414071[32] ? + (_theResult____h414070[32] ? 6'd24 : - (_theResult____h414071[31] ? + (_theResult____h414070[31] ? 6'd25 : - (_theResult____h414071[30] ? + (_theResult____h414070[30] ? 6'd26 : - (_theResult____h414071[29] ? + (_theResult____h414070[29] ? 6'd27 : - (_theResult____h414071[28] ? + (_theResult____h414070[28] ? 6'd28 : - (_theResult____h414071[27] ? + (_theResult____h414070[27] ? 6'd29 : - (_theResult____h414071[26] ? + (_theResult____h414070[26] ? 6'd30 : - (_theResult____h414071[25] ? + (_theResult____h414070[25] ? 6'd31 : - (_theResult____h414071[24] ? + (_theResult____h414070[24] ? 6'd32 : - (_theResult____h414071[23] ? + (_theResult____h414070[23] ? 6'd33 : - (_theResult____h414071[22] ? + (_theResult____h414070[22] ? 6'd34 : - (_theResult____h414071[21] ? + (_theResult____h414070[21] ? 6'd35 : - (_theResult____h414071[20] ? + (_theResult____h414070[20] ? 6'd36 : - (_theResult____h414071[19] ? + (_theResult____h414070[19] ? 6'd37 : - (_theResult____h414071[18] ? + (_theResult____h414070[18] ? 6'd38 : - (_theResult____h414071[17] ? + (_theResult____h414070[17] ? 6'd39 : - (_theResult____h414071[16] ? + (_theResult____h414070[16] ? 6'd40 : - (_theResult____h414071[15] ? + (_theResult____h414070[15] ? 6'd41 : - (_theResult____h414071[14] ? + (_theResult____h414070[14] ? 6'd42 : - (_theResult____h414071[13] ? + (_theResult____h414070[13] ? 6'd43 : - (_theResult____h414071[12] ? + (_theResult____h414070[12] ? 6'd44 : - (_theResult____h414071[11] ? + (_theResult____h414070[11] ? 6'd45 : - (_theResult____h414071[10] ? + (_theResult____h414070[10] ? 6'd46 : - (_theResult____h414071[9] ? + (_theResult____h414070[9] ? 6'd47 : - (_theResult____h414071[8] ? + (_theResult____h414070[8] ? 6'd48 : - (_theResult____h414071[7] ? + (_theResult____h414070[7] ? 6'd49 : - (_theResult____h414071[6] ? + (_theResult____h414070[6] ? 6'd50 : - (_theResult____h414071[5] ? + (_theResult____h414070[5] ? 6'd51 : - (_theResult____h414071[4] ? + (_theResult____h414070[4] ? 6'd52 : - (_theResult____h414071[3] ? + (_theResult____h414070[3] ? 6'd53 : - (_theResult____h414071[2] ? + (_theResult____h414070[2] ? 6'd54 : - (_theResult____h414071[1] ? + (_theResult____h414070[1] ? 6'd55 : - (_theResult____h414071[0] ? + (_theResult____h414070[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 = - (_theResult____h459766[56] ? + (_theResult____h459765[56] ? 6'd0 : - (_theResult____h459766[55] ? + (_theResult____h459765[55] ? 6'd1 : - (_theResult____h459766[54] ? + (_theResult____h459765[54] ? 6'd2 : - (_theResult____h459766[53] ? + (_theResult____h459765[53] ? 6'd3 : - (_theResult____h459766[52] ? + (_theResult____h459765[52] ? 6'd4 : - (_theResult____h459766[51] ? + (_theResult____h459765[51] ? 6'd5 : - (_theResult____h459766[50] ? + (_theResult____h459765[50] ? 6'd6 : - (_theResult____h459766[49] ? + (_theResult____h459765[49] ? 6'd7 : - (_theResult____h459766[48] ? + (_theResult____h459765[48] ? 6'd8 : - (_theResult____h459766[47] ? + (_theResult____h459765[47] ? 6'd9 : - (_theResult____h459766[46] ? + (_theResult____h459765[46] ? 6'd10 : - (_theResult____h459766[45] ? + (_theResult____h459765[45] ? 6'd11 : - (_theResult____h459766[44] ? + (_theResult____h459765[44] ? 6'd12 : - (_theResult____h459766[43] ? + (_theResult____h459765[43] ? 6'd13 : - (_theResult____h459766[42] ? + (_theResult____h459765[42] ? 6'd14 : - (_theResult____h459766[41] ? + (_theResult____h459765[41] ? 6'd15 : - (_theResult____h459766[40] ? + (_theResult____h459765[40] ? 6'd16 : - (_theResult____h459766[39] ? + (_theResult____h459765[39] ? 6'd17 : - (_theResult____h459766[38] ? + (_theResult____h459765[38] ? 6'd18 : - (_theResult____h459766[37] ? + (_theResult____h459765[37] ? 6'd19 : - (_theResult____h459766[36] ? + (_theResult____h459765[36] ? 6'd20 : - (_theResult____h459766[35] ? + (_theResult____h459765[35] ? 6'd21 : - (_theResult____h459766[34] ? + (_theResult____h459765[34] ? 6'd22 : - (_theResult____h459766[33] ? + (_theResult____h459765[33] ? 6'd23 : - (_theResult____h459766[32] ? + (_theResult____h459765[32] ? 6'd24 : - (_theResult____h459766[31] ? + (_theResult____h459765[31] ? 6'd25 : - (_theResult____h459766[30] ? + (_theResult____h459765[30] ? 6'd26 : - (_theResult____h459766[29] ? + (_theResult____h459765[29] ? 6'd27 : - (_theResult____h459766[28] ? + (_theResult____h459765[28] ? 6'd28 : - (_theResult____h459766[27] ? + (_theResult____h459765[27] ? 6'd29 : - (_theResult____h459766[26] ? + (_theResult____h459765[26] ? 6'd30 : - (_theResult____h459766[25] ? + (_theResult____h459765[25] ? 6'd31 : - (_theResult____h459766[24] ? + (_theResult____h459765[24] ? 6'd32 : - (_theResult____h459766[23] ? + (_theResult____h459765[23] ? 6'd33 : - (_theResult____h459766[22] ? + (_theResult____h459765[22] ? 6'd34 : - (_theResult____h459766[21] ? + (_theResult____h459765[21] ? 6'd35 : - (_theResult____h459766[20] ? + (_theResult____h459765[20] ? 6'd36 : - (_theResult____h459766[19] ? + (_theResult____h459765[19] ? 6'd37 : - (_theResult____h459766[18] ? + (_theResult____h459765[18] ? 6'd38 : - (_theResult____h459766[17] ? + (_theResult____h459765[17] ? 6'd39 : - (_theResult____h459766[16] ? + (_theResult____h459765[16] ? 6'd40 : - (_theResult____h459766[15] ? + (_theResult____h459765[15] ? 6'd41 : - (_theResult____h459766[14] ? + (_theResult____h459765[14] ? 6'd42 : - (_theResult____h459766[13] ? + (_theResult____h459765[13] ? 6'd43 : - (_theResult____h459766[12] ? + (_theResult____h459765[12] ? 6'd44 : - (_theResult____h459766[11] ? + (_theResult____h459765[11] ? 6'd45 : - (_theResult____h459766[10] ? + (_theResult____h459765[10] ? 6'd46 : - (_theResult____h459766[9] ? + (_theResult____h459765[9] ? 6'd47 : - (_theResult____h459766[8] ? + (_theResult____h459765[8] ? 6'd48 : - (_theResult____h459766[7] ? + (_theResult____h459765[7] ? 6'd49 : - (_theResult____h459766[6] ? + (_theResult____h459765[6] ? 6'd50 : - (_theResult____h459766[5] ? + (_theResult____h459765[5] ? 6'd51 : - (_theResult____h459766[4] ? + (_theResult____h459765[4] ? 6'd52 : - (_theResult____h459766[3] ? + (_theResult____h459765[3] ? 6'd53 : - (_theResult____h459766[2] ? + (_theResult____h459765[2] ? 6'd54 : - (_theResult____h459766[1] ? + (_theResult____h459765[1] ? 6'd55 : - (_theResult____h459766[0] ? + (_theResult____h459765[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10033 = - (_theResult___fst_exp__h594648 == 11'd2047) ? + (_theResult___fst_exp__h594647 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19011,10 +18994,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard86421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10535 = - (_theResult___fst_exp__h555344 == 11'd2047) ? + (_theResult___fst_exp__h555343 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19022,10 +19005,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_guard47117_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10802 = - (_theResult___fst_exp__h555344 == 11'd2047) ? + (_theResult___fst_exp__h555343 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19033,10 +19016,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard47117_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9050 = - (_theResult___fst_exp__h516491 == 11'd2047) ? + (_theResult___fst_exp__h516490 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19044,10 +19027,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard08264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9765 = - (_theResult___fst_exp__h594648 == 11'd2047) ? + (_theResult___fst_exp__h594647 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19055,538 +19038,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard86421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 = - (guard__h350745 == 2'b0 || + (guard__h350744 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h358846 : - _theResult___exp__h359362 ; + _theResult___fst_exp__h358845 : + _theResult___exp__h359361 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 = - (guard__h350745 == 2'b0) ? - _theResult___fst_exp__h358846 : + (guard__h350744 == 2'b0) ? + _theResult___fst_exp__h358845 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h359362 : - _theResult___fst_exp__h358846) ; + _theResult___exp__h359361 : + _theResult___fst_exp__h358845) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 = - (guard__h350745 == 2'b0 || + (guard__h350744 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h358840[56:34] : - _theResult___sfd__h359363 ; + sfdin__h358839[56:34] : + _theResult___sfd__h359362 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 = - (guard__h350745 == 2'b0) ? - sfdin__h358840[56:34] : + (guard__h350744 == 2'b0) ? + sfdin__h358839[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h359363 : - sfdin__h358840[56:34]) ; + _theResult___sfd__h359362 : + sfdin__h358839[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 = - (guard__h396444 == 2'b0 || + (guard__h396443 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h404543 : - _theResult___exp__h405059 ; + _theResult___fst_exp__h404542 : + _theResult___exp__h405058 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 = - (guard__h396444 == 2'b0) ? - _theResult___fst_exp__h404543 : + (guard__h396443 == 2'b0) ? + _theResult___fst_exp__h404542 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h405059 : - _theResult___fst_exp__h404543) ; + _theResult___exp__h405058 : + _theResult___fst_exp__h404542) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 = - (guard__h396444 == 2'b0 || + (guard__h396443 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h404537[56:34] : - _theResult___sfd__h405060 ; + sfdin__h404536[56:34] : + _theResult___sfd__h405059 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 = - (guard__h396444 == 2'b0) ? - sfdin__h404537[56:34] : + (guard__h396443 == 2'b0) ? + sfdin__h404536[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h405060 : - sfdin__h404537[56:34]) ; + _theResult___sfd__h405059 : + sfdin__h404536[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 = - (guard__h442139 == 2'b0 || + (guard__h442138 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h450238 : - _theResult___exp__h450754 ; + _theResult___fst_exp__h450237 : + _theResult___exp__h450753 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 = - (guard__h442139 == 2'b0) ? - _theResult___fst_exp__h450238 : + (guard__h442138 == 2'b0) ? + _theResult___fst_exp__h450237 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h450754 : - _theResult___fst_exp__h450238) ; + _theResult___exp__h450753 : + _theResult___fst_exp__h450237) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 = - (guard__h442139 == 2'b0 || + (guard__h442138 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h450232[56:34] : - _theResult___sfd__h450755 ; + sfdin__h450231[56:34] : + _theResult___sfd__h450754 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 = - (guard__h442139 == 2'b0) ? - sfdin__h450232[56:34] : + (guard__h442138 == 2'b0) ? + sfdin__h450231[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h450755 : - sfdin__h450232[56:34]) ; + _theResult___sfd__h450754 : + sfdin__h450231[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 = - (guard__h547118 == 2'b0 || + (guard__h547117 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h555344 : - _theResult___exp__h556073 ; + _theResult___fst_exp__h555343 : + _theResult___exp__h556072 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 = - (guard__h547118 == 2'b0) ? - _theResult___fst_exp__h555344 : + (guard__h547117 == 2'b0) ? + _theResult___fst_exp__h555343 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h556073 : - _theResult___fst_exp__h555344) ; + _theResult___exp__h556072 : + _theResult___fst_exp__h555343) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 = - (guard__h547118 == 2'b0 || + (guard__h547117 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h555338[56:5] : - _theResult___sfd__h556074 ; + sfdin__h555337[56:5] : + _theResult___sfd__h556073 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 = - (guard__h547118 == 2'b0) ? - sfdin__h555338[56:5] : + (guard__h547117 == 2'b0) ? + sfdin__h555337[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h556074 : - sfdin__h555338[56:5]) ; + _theResult___sfd__h556073 : + sfdin__h555337[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 = - (guard__h508265 == 2'b0 || + (guard__h508264 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h516491 : - _theResult___exp__h517220 ; + _theResult___fst_exp__h516490 : + _theResult___exp__h517219 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 = - (guard__h508265 == 2'b0) ? - _theResult___fst_exp__h516491 : + (guard__h508264 == 2'b0) ? + _theResult___fst_exp__h516490 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h517220 : - _theResult___fst_exp__h516491) ; + _theResult___exp__h517219 : + _theResult___fst_exp__h516490) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 = - (guard__h508265 == 2'b0 || + (guard__h508264 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h516485[56:5] : - _theResult___sfd__h517221 ; + sfdin__h516484[56:5] : + _theResult___sfd__h517220 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 = - (guard__h508265 == 2'b0) ? - sfdin__h516485[56:5] : + (guard__h508264 == 2'b0) ? + sfdin__h516484[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h517221 : - sfdin__h516485[56:5]) ; + _theResult___sfd__h517220 : + sfdin__h516484[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 = - (guard__h586422 == 2'b0 || + (guard__h586421 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h594648 : - _theResult___exp__h595377 ; + _theResult___fst_exp__h594647 : + _theResult___exp__h595376 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 = - (guard__h586422 == 2'b0) ? - _theResult___fst_exp__h594648 : + (guard__h586421 == 2'b0) ? + _theResult___fst_exp__h594647 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h595377 : - _theResult___fst_exp__h594648) ; + _theResult___exp__h595376 : + _theResult___fst_exp__h594647) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 = - (guard__h586422 == 2'b0 || + (guard__h586421 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h594642[56:5] : - _theResult___sfd__h595378 ; + sfdin__h594641[56:5] : + _theResult___sfd__h595377 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 = - (guard__h586422 == 2'b0) ? - sfdin__h594642[56:5] : + (guard__h586421 == 2'b0) ? + sfdin__h594641[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h595378 : - sfdin__h594642[56:5]) ; + _theResult___sfd__h595377 : + sfdin__h594641[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 = - (guard__h368384 == 2'b0 || + (guard__h368383 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h376612 : - _theResult___exp__h377128 ; + _theResult___fst_exp__h376611 : + _theResult___exp__h377127 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 = - (guard__h368384 == 2'b0) ? - _theResult___fst_exp__h376612 : + (guard__h368383 == 2'b0) ? + _theResult___fst_exp__h376611 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h377128 : - _theResult___fst_exp__h376612) ; + _theResult___exp__h377127 : + _theResult___fst_exp__h376611) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 = - (guard__h368384 == 2'b0 || + (guard__h368383 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h376606[56:34] : - _theResult___sfd__h377129 ; + sfdin__h376605[56:34] : + _theResult___sfd__h377128 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 = - (guard__h368384 == 2'b0) ? - sfdin__h376606[56:34] : + (guard__h368383 == 2'b0) ? + sfdin__h376605[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h377129 : - sfdin__h376606[56:34]) ; + _theResult___sfd__h377128 : + sfdin__h376605[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 = - (guard__h414081 == 2'b0 || + (guard__h414080 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h422309 : - _theResult___exp__h422825 ; + _theResult___fst_exp__h422308 : + _theResult___exp__h422824 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 = - (guard__h414081 == 2'b0) ? - _theResult___fst_exp__h422309 : + (guard__h414080 == 2'b0) ? + _theResult___fst_exp__h422308 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h422825 : - _theResult___fst_exp__h422309) ; + _theResult___exp__h422824 : + _theResult___fst_exp__h422308) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 = - (guard__h414081 == 2'b0 || + (guard__h414080 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h422303[56:34] : - _theResult___sfd__h422826 ; + sfdin__h422302[56:34] : + _theResult___sfd__h422825 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 = - (guard__h414081 == 2'b0) ? - sfdin__h422303[56:34] : + (guard__h414080 == 2'b0) ? + sfdin__h422302[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h422826 : - sfdin__h422303[56:34]) ; + _theResult___sfd__h422825 : + sfdin__h422302[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 = - (guard__h459776 == 2'b0 || + (guard__h459775 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h468004 : - _theResult___exp__h468520 ; + _theResult___fst_exp__h468003 : + _theResult___exp__h468519 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 = - (guard__h459776 == 2'b0) ? - _theResult___fst_exp__h468004 : + (guard__h459775 == 2'b0) ? + _theResult___fst_exp__h468003 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h468520 : - _theResult___fst_exp__h468004) ; + _theResult___exp__h468519 : + _theResult___fst_exp__h468003) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 = - (guard__h459776 == 2'b0 || + (guard__h459775 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h467998[56:34] : - _theResult___sfd__h468521 ; + sfdin__h467997[56:34] : + _theResult___sfd__h468520 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 = - (guard__h459776 == 2'b0) ? - sfdin__h467998[56:34] : + (guard__h459775 == 2'b0) ? + sfdin__h467997[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h468521 : - sfdin__h467998[56:34]) ; + _theResult___sfd__h468520 : + sfdin__h467997[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 = - (guard__h537806 == 2'b0 || + (guard__h537805 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h545767 : - _theResult___exp__h546422 ; + _theResult___fst_exp__h545766 : + _theResult___exp__h546421 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 = - (guard__h537806 == 2'b0) ? - _theResult___fst_exp__h545767 : + (guard__h537805 == 2'b0) ? + _theResult___fst_exp__h545766 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h546422 : - _theResult___fst_exp__h545767) ; + _theResult___exp__h546421 : + _theResult___fst_exp__h545766) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 = - (guard__h556187 == 2'b0 || + (guard__h556186 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h564177 : - _theResult___exp__h564857 ; + _theResult___fst_exp__h564176 : + _theResult___exp__h564856 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 = - (guard__h556187 == 2'b0) ? - _theResult___fst_exp__h564177 : + (guard__h556186 == 2'b0) ? + _theResult___fst_exp__h564176 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h564857 : - _theResult___fst_exp__h564177) ; + _theResult___exp__h564856 : + _theResult___fst_exp__h564176) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 = - (guard__h537806 == 2'b0 || + (guard__h537805 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h545718[56:5] : - _theResult___sfd__h546423 ; + _theResult___snd__h545717[56:5] : + _theResult___sfd__h546422 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 = - (guard__h537806 == 2'b0) ? - _theResult___snd__h545718[56:5] : + (guard__h537805 == 2'b0) ? + _theResult___snd__h545717[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h546423 : - _theResult___snd__h545718[56:5]) ; + _theResult___sfd__h546422 : + _theResult___snd__h545717[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 = - (guard__h556187 == 2'b0 || + (guard__h556186 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h564123[56:5] : - _theResult___sfd__h564858 ; + _theResult___snd__h564122[56:5] : + _theResult___sfd__h564857 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 = - (guard__h556187 == 2'b0) ? - _theResult___snd__h564123[56:5] : + (guard__h556186 == 2'b0) ? + _theResult___snd__h564122[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h564858 : - _theResult___snd__h564123[56:5]) ; + _theResult___sfd__h564857 : + _theResult___snd__h564122[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 = - (guard__h498953 == 2'b0 || + (guard__h498952 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h506914 : - _theResult___exp__h507569 ; + _theResult___fst_exp__h506913 : + _theResult___exp__h507568 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 = - (guard__h498953 == 2'b0) ? - _theResult___fst_exp__h506914 : + (guard__h498952 == 2'b0) ? + _theResult___fst_exp__h506913 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h507569 : - _theResult___fst_exp__h506914) ; + _theResult___exp__h507568 : + _theResult___fst_exp__h506913) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 = - (guard__h517334 == 2'b0 || + (guard__h517333 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h525324 : - _theResult___exp__h526004 ; + _theResult___fst_exp__h525323 : + _theResult___exp__h526003 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 = - (guard__h517334 == 2'b0) ? - _theResult___fst_exp__h525324 : + (guard__h517333 == 2'b0) ? + _theResult___fst_exp__h525323 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h526004 : - _theResult___fst_exp__h525324) ; + _theResult___exp__h526003 : + _theResult___fst_exp__h525323) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 = - (guard__h498953 == 2'b0 || + (guard__h498952 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h506865[56:5] : - _theResult___sfd__h507570 ; + _theResult___snd__h506864[56:5] : + _theResult___sfd__h507569 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 = - (guard__h498953 == 2'b0) ? - _theResult___snd__h506865[56:5] : + (guard__h498952 == 2'b0) ? + _theResult___snd__h506864[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h507570 : - _theResult___snd__h506865[56:5]) ; + _theResult___sfd__h507569 : + _theResult___snd__h506864[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 = - (guard__h517334 == 2'b0 || + (guard__h517333 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h525270[56:5] : - _theResult___sfd__h526005 ; + _theResult___snd__h525269[56:5] : + _theResult___sfd__h526004 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 = - (guard__h517334 == 2'b0) ? - _theResult___snd__h525270[56:5] : + (guard__h517333 == 2'b0) ? + _theResult___snd__h525269[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h526005 : - _theResult___snd__h525270[56:5]) ; + _theResult___sfd__h526004 : + _theResult___snd__h525269[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 = - (guard__h577110 == 2'b0 || + (guard__h577109 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h585071 : - _theResult___exp__h585726 ; + _theResult___fst_exp__h585070 : + _theResult___exp__h585725 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 = - (guard__h577110 == 2'b0) ? - _theResult___fst_exp__h585071 : + (guard__h577109 == 2'b0) ? + _theResult___fst_exp__h585070 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h585726 : - _theResult___fst_exp__h585071) ; + _theResult___exp__h585725 : + _theResult___fst_exp__h585070) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 = - (guard__h595491 == 2'b0 || + (guard__h595490 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h603481 : - _theResult___exp__h604161 ; + _theResult___fst_exp__h603480 : + _theResult___exp__h604160 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 = - (guard__h595491 == 2'b0) ? - _theResult___fst_exp__h603481 : + (guard__h595490 == 2'b0) ? + _theResult___fst_exp__h603480 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h604161 : - _theResult___fst_exp__h603481) ; + _theResult___exp__h604160 : + _theResult___fst_exp__h603480) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 = - (guard__h577110 == 2'b0 || + (guard__h577109 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h585022[56:5] : - _theResult___sfd__h585727 ; + _theResult___snd__h585021[56:5] : + _theResult___sfd__h585726 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 = - (guard__h577110 == 2'b0) ? - _theResult___snd__h585022[56:5] : + (guard__h577109 == 2'b0) ? + _theResult___snd__h585021[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h585727 : - _theResult___snd__h585022[56:5]) ; + _theResult___sfd__h585726 : + _theResult___snd__h585021[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 = - (guard__h595491 == 2'b0 || + (guard__h595490 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h603427[56:5] : - _theResult___sfd__h604162 ; + _theResult___snd__h603426[56:5] : + _theResult___sfd__h604161 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 = - (guard__h595491 == 2'b0) ? - _theResult___snd__h603427[56:5] : + (guard__h595490 == 2'b0) ? + _theResult___snd__h603426[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h604162 : - _theResult___snd__h603427[56:5]) ; + _theResult___sfd__h604161 : + _theResult___snd__h603426[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 = - (guard__h359454 == 2'b0 || + (guard__h359453 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h367502 : - _theResult___exp__h367944 ; + _theResult___fst_exp__h367501 : + _theResult___exp__h367943 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 = - (guard__h359454 == 2'b0) ? - _theResult___fst_exp__h367502 : + (guard__h359453 == 2'b0) ? + _theResult___fst_exp__h367501 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h367944 : - _theResult___fst_exp__h367502) ; + _theResult___exp__h367943 : + _theResult___fst_exp__h367501) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h377220 == 2'b0 || + (guard__h377219 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h385297 : - _theResult___exp__h385764 ; + _theResult___fst_exp__h385296 : + _theResult___exp__h385763 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h377220 == 2'b0) ? - _theResult___fst_exp__h385297 : + (guard__h377219 == 2'b0) ? + _theResult___fst_exp__h385296 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h385764 : - _theResult___fst_exp__h385297) ; + _theResult___exp__h385763 : + _theResult___fst_exp__h385296) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 = - (guard__h359454 == 2'b0 || + (guard__h359453 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h367453[56:34] : - _theResult___sfd__h367945 ; + _theResult___snd__h367452[56:34] : + _theResult___sfd__h367944 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 = - (guard__h359454 == 2'b0) ? - _theResult___snd__h367453[56:34] : + (guard__h359453 == 2'b0) ? + _theResult___snd__h367452[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h367945 : - _theResult___snd__h367453[56:34]) ; + _theResult___sfd__h367944 : + _theResult___snd__h367452[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 = - (guard__h377220 == 2'b0 || + (guard__h377219 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h385243[56:34] : - _theResult___sfd__h385765 ; + _theResult___snd__h385242[56:34] : + _theResult___sfd__h385764 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 = - (guard__h377220 == 2'b0) ? - _theResult___snd__h385243[56:34] : + (guard__h377219 == 2'b0) ? + _theResult___snd__h385242[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h385765 : - _theResult___snd__h385243[56:34]) ; + _theResult___sfd__h385764 : + _theResult___snd__h385242[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 = - (guard__h405151 == 2'b0 || + (guard__h405150 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h413199 : - _theResult___exp__h413641 ; + _theResult___fst_exp__h413198 : + _theResult___exp__h413640 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 = - (guard__h405151 == 2'b0) ? - _theResult___fst_exp__h413199 : + (guard__h405150 == 2'b0) ? + _theResult___fst_exp__h413198 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h413641 : - _theResult___fst_exp__h413199) ; + _theResult___exp__h413640 : + _theResult___fst_exp__h413198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h422917 == 2'b0 || + (guard__h422916 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h430994 : - _theResult___exp__h431461 ; + _theResult___fst_exp__h430993 : + _theResult___exp__h431460 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h422917 == 2'b0) ? - _theResult___fst_exp__h430994 : + (guard__h422916 == 2'b0) ? + _theResult___fst_exp__h430993 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h431461 : - _theResult___fst_exp__h430994) ; + _theResult___exp__h431460 : + _theResult___fst_exp__h430993) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 = - (guard__h405151 == 2'b0 || + (guard__h405150 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h413150[56:34] : - _theResult___sfd__h413642 ; + _theResult___snd__h413149[56:34] : + _theResult___sfd__h413641 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 = - (guard__h405151 == 2'b0) ? - _theResult___snd__h413150[56:34] : + (guard__h405150 == 2'b0) ? + _theResult___snd__h413149[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h413642 : - _theResult___snd__h413150[56:34]) ; + _theResult___sfd__h413641 : + _theResult___snd__h413149[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 = - (guard__h422917 == 2'b0 || + (guard__h422916 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h430940[56:34] : - _theResult___sfd__h431462 ; + _theResult___snd__h430939[56:34] : + _theResult___sfd__h431461 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 = - (guard__h422917 == 2'b0) ? - _theResult___snd__h430940[56:34] : + (guard__h422916 == 2'b0) ? + _theResult___snd__h430939[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h431462 : - _theResult___snd__h430940[56:34]) ; + _theResult___sfd__h431461 : + _theResult___snd__h430939[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 = - (guard__h450846 == 2'b0 || + (guard__h450845 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h458894 : - _theResult___exp__h459336 ; + _theResult___fst_exp__h458893 : + _theResult___exp__h459335 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 = - (guard__h450846 == 2'b0) ? - _theResult___fst_exp__h458894 : + (guard__h450845 == 2'b0) ? + _theResult___fst_exp__h458893 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h459336 : - _theResult___fst_exp__h458894) ; + _theResult___exp__h459335 : + _theResult___fst_exp__h458893) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h468612 == 2'b0 || + (guard__h468611 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h476689 : - _theResult___exp__h477156 ; + _theResult___fst_exp__h476688 : + _theResult___exp__h477155 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h468612 == 2'b0) ? - _theResult___fst_exp__h476689 : + (guard__h468611 == 2'b0) ? + _theResult___fst_exp__h476688 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h477156 : - _theResult___fst_exp__h476689) ; + _theResult___exp__h477155 : + _theResult___fst_exp__h476688) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 = - (guard__h450846 == 2'b0 || + (guard__h450845 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h458845[56:34] : - _theResult___sfd__h459337 ; + _theResult___snd__h458844[56:34] : + _theResult___sfd__h459336 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 = - (guard__h450846 == 2'b0) ? - _theResult___snd__h458845[56:34] : + (guard__h450845 == 2'b0) ? + _theResult___snd__h458844[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h459337 : - _theResult___snd__h458845[56:34]) ; + _theResult___sfd__h459336 : + _theResult___snd__h458844[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 = - (guard__h468612 == 2'b0 || + (guard__h468611 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h476635[56:34] : - _theResult___sfd__h477157 ; + _theResult___snd__h476634[56:34] : + _theResult___sfd__h477156 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 = - (guard__h468612 == 2'b0) ? - _theResult___snd__h476635[56:34] : + (guard__h468611 == 2'b0) ? + _theResult___snd__h476634[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h477157 : - _theResult___snd__h476635[56:34]) ; + _theResult___sfd__h477156 : + _theResult___snd__h476634[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10018 = - (_theResult___fst_exp__h585071 == 11'd2047) ? + (_theResult___fst_exp__h585070 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19594,10 +19577,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard77109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045 = - (_theResult___fst_exp__h603481 == 11'd2047) ? + (_theResult___fst_exp__h603480 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19605,10 +19588,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard95490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581 = - (_theResult___fst_exp__h564177 == 11'd2047) ? + (_theResult___fst_exp__h564176 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19616,10 +19599,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_guard56186_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10787 = - (_theResult___fst_exp__h545767 == 11'd2047) ? + (_theResult___fst_exp__h545766 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19627,10 +19610,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_guard37805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814 = - (_theResult___fst_exp__h564177 == 11'd2047) ? + (_theResult___fst_exp__h564176 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19638,10 +19621,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard56186_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 = - (_theResult___fst_exp__h525324 == 11'd2047) ? + (_theResult___fst_exp__h525323 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19649,10 +19632,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard17333_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811 = - (_theResult___fst_exp__h603481 == 11'd2047) ? + (_theResult___fst_exp__h603480 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19660,14 +19643,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard95490_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992 = - (_theResult____h658027 == 12'd0 && + (_theResult____h658025 == 12'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h658486 : - _theResult____h658027 ; + enabled_ints__h658484 : + _theResult____h658025 ; assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13204 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] || @@ -19717,7 +19700,7 @@ module mkCore(CLK, checkForException___d13792[4] || csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13881 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565823 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -19727,85 +19710,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049 = - (f3_exp__h565824 == 8'd255 && f3_sfd__h565825 != 23'd0 || - (f3_exp__h565824 == 8'd255 || f3_exp__h565824 == 8'd0) && - f3_sfd__h565825 == 23'd0) ? + (f3_exp__h565823 == 8'd255 && f3_sfd__h565824 != 23'd0 || + (f3_exp__h565823 == 8'd255 || f3_exp__h565823 == 8'd0) && + f3_sfd__h565824 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 = - ((f2_exp__h526520 == 8'd0) ? - (f2_sfd__h526521[22] ? + ((f2_exp__h526519 == 8'd0) ? + (f2_sfd__h526520[22] ? 6'd2 : - (f2_sfd__h526521[21] ? + (f2_sfd__h526520[21] ? 6'd3 : - (f2_sfd__h526521[20] ? + (f2_sfd__h526520[20] ? 6'd4 : - (f2_sfd__h526521[19] ? + (f2_sfd__h526520[19] ? 6'd5 : - (f2_sfd__h526521[18] ? + (f2_sfd__h526520[18] ? 6'd6 : - (f2_sfd__h526521[17] ? + (f2_sfd__h526520[17] ? 6'd7 : - (f2_sfd__h526521[16] ? + (f2_sfd__h526520[16] ? 6'd8 : - (f2_sfd__h526521[15] ? + (f2_sfd__h526520[15] ? 6'd9 : - (f2_sfd__h526521[14] ? + (f2_sfd__h526520[14] ? 6'd10 : - (f2_sfd__h526521[13] ? + (f2_sfd__h526520[13] ? 6'd11 : - (f2_sfd__h526521[12] ? + (f2_sfd__h526520[12] ? 6'd12 : - (f2_sfd__h526521[11] ? + (f2_sfd__h526520[11] ? 6'd13 : - (f2_sfd__h526521[10] ? + (f2_sfd__h526520[10] ? 6'd14 : - (f2_sfd__h526521[9] ? + (f2_sfd__h526520[9] ? 6'd15 : - (f2_sfd__h526521[8] ? + (f2_sfd__h526520[8] ? 6'd16 : - (f2_sfd__h526521[7] ? + (f2_sfd__h526520[7] ? 6'd17 : - (f2_sfd__h526521[6] ? + (f2_sfd__h526520[6] ? 6'd18 : - (f2_sfd__h526521[5] ? + (f2_sfd__h526520[5] ? 6'd19 : - (f2_sfd__h526521[4] ? + (f2_sfd__h526520[4] ? 6'd20 : - (f2_sfd__h526521[3] ? + (f2_sfd__h526520[3] ? 6'd21 : - (f2_sfd__h526521[2] ? + (f2_sfd__h526520[2] ? 6'd22 : - (f2_sfd__h526521[1] ? + (f2_sfd__h526520[1] ? 6'd23 : - (f2_sfd__h526521[0] ? + (f2_sfd__h526520[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585 = - (f2_exp__h526520 == 8'd255 && f2_sfd__h526521 != 23'd0 || - (f2_exp__h526520 == 8'd255 || f2_exp__h526520 == 8'd0) && - f2_sfd__h526521 == 23'd0) ? + (f2_exp__h526519 == 8'd255 && f2_sfd__h526520 != 23'd0 || + (f2_exp__h526519 == 8'd255 || f2_exp__h526519 == 8'd0) && + f2_sfd__h526520 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h526520 == 8'd0) ? + ((f2_exp__h526519 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f2_exp__h526520 == 8'd255 && f2_sfd__h526521 != 23'd0) ? - _theResult___snd_fst_sfd__h526836 : - _theResult___fst_sfd__h564976 ; + (f2_exp__h526519 == 8'd255 && f2_sfd__h526520 != 23'd0) ? + _theResult___snd_fst_sfd__h526835 : + _theResult___fst_sfd__h564975 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 = - { (f2_exp__h526520 == 8'd255) ? + { (f2_exp__h526519 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h564972, + _theResult___fst_exp__h564971, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526519 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -19815,15 +19798,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 = - (f2_exp__h526520 == 8'd255 && f2_sfd__h526521 != 23'd0 || - (f2_exp__h526520 == 8'd255 || f2_exp__h526520 == 8'd0) && - f2_sfd__h526521 == 23'd0) ? + (f2_exp__h526519 == 8'd255 && f2_sfd__h526520 != 23'd0 || + (f2_exp__h526519 == 8'd255 || f2_exp__h526519 == 8'd0) && + f2_sfd__h526520 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487525 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[4] : @@ -19831,7 +19814,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526519 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[4] : @@ -19839,7 +19822,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565823 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[4] : @@ -19847,7 +19830,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487525 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[3] : @@ -19855,7 +19838,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526519 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[3] : @@ -19863,7 +19846,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565823 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[3] : @@ -19871,208 +19854,208 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487525 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526519 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565823 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487525 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526519 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565823 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487525 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526519 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565823 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 = - ((f1_exp__h487526 == 8'd0) ? - (f1_sfd__h487527[22] ? + ((f1_exp__h487525 == 8'd0) ? + (f1_sfd__h487526[22] ? 6'd2 : - (f1_sfd__h487527[21] ? + (f1_sfd__h487526[21] ? 6'd3 : - (f1_sfd__h487527[20] ? + (f1_sfd__h487526[20] ? 6'd4 : - (f1_sfd__h487527[19] ? + (f1_sfd__h487526[19] ? 6'd5 : - (f1_sfd__h487527[18] ? + (f1_sfd__h487526[18] ? 6'd6 : - (f1_sfd__h487527[17] ? + (f1_sfd__h487526[17] ? 6'd7 : - (f1_sfd__h487527[16] ? + (f1_sfd__h487526[16] ? 6'd8 : - (f1_sfd__h487527[15] ? + (f1_sfd__h487526[15] ? 6'd9 : - (f1_sfd__h487527[14] ? + (f1_sfd__h487526[14] ? 6'd10 : - (f1_sfd__h487527[13] ? + (f1_sfd__h487526[13] ? 6'd11 : - (f1_sfd__h487527[12] ? + (f1_sfd__h487526[12] ? 6'd12 : - (f1_sfd__h487527[11] ? + (f1_sfd__h487526[11] ? 6'd13 : - (f1_sfd__h487527[10] ? + (f1_sfd__h487526[10] ? 6'd14 : - (f1_sfd__h487527[9] ? + (f1_sfd__h487526[9] ? 6'd15 : - (f1_sfd__h487527[8] ? + (f1_sfd__h487526[8] ? 6'd16 : - (f1_sfd__h487527[7] ? + (f1_sfd__h487526[7] ? 6'd17 : - (f1_sfd__h487527[6] ? + (f1_sfd__h487526[6] ? 6'd18 : - (f1_sfd__h487527[5] ? + (f1_sfd__h487526[5] ? 6'd19 : - (f1_sfd__h487527[4] ? + (f1_sfd__h487526[4] ? 6'd20 : - (f1_sfd__h487527[3] ? + (f1_sfd__h487526[3] ? 6'd21 : - (f1_sfd__h487527[2] ? + (f1_sfd__h487526[2] ? 6'd22 : - (f1_sfd__h487527[1] ? + (f1_sfd__h487526[1] ? 6'd23 : - (f1_sfd__h487527[0] ? + (f1_sfd__h487526[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100 = - (f1_exp__h487526 == 8'd255 && f1_sfd__h487527 != 23'd0 || - (f1_exp__h487526 == 8'd255 || f1_exp__h487526 == 8'd0) && - f1_sfd__h487527 == 23'd0) ? + (f1_exp__h487525 == 8'd255 && f1_sfd__h487526 != 23'd0 || + (f1_exp__h487525 == 8'd255 || f1_exp__h487525 == 8'd0) && + f1_sfd__h487526 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h487526 == 8'd0) ? + ((f1_exp__h487525 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 = - (f1_exp__h487526 == 8'd255 && f1_sfd__h487527 != 23'd0) ? - _theResult___snd_fst_sfd__h487842 : - _theResult___fst_sfd__h526123 ; + (f1_exp__h487525 == 8'd255 && f1_sfd__h487526 != 23'd0) ? + _theResult___snd_fst_sfd__h487841 : + _theResult___fst_sfd__h526122 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100, - (f1_exp__h487526 == 8'd255) ? + (f1_exp__h487525 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h526119, + _theResult___fst_exp__h526118, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 = - ((f3_exp__h565824 == 8'd0) ? - (f3_sfd__h565825[22] ? + ((f3_exp__h565823 == 8'd0) ? + (f3_sfd__h565824[22] ? 6'd2 : - (f3_sfd__h565825[21] ? + (f3_sfd__h565824[21] ? 6'd3 : - (f3_sfd__h565825[20] ? + (f3_sfd__h565824[20] ? 6'd4 : - (f3_sfd__h565825[19] ? + (f3_sfd__h565824[19] ? 6'd5 : - (f3_sfd__h565825[18] ? + (f3_sfd__h565824[18] ? 6'd6 : - (f3_sfd__h565825[17] ? + (f3_sfd__h565824[17] ? 6'd7 : - (f3_sfd__h565825[16] ? + (f3_sfd__h565824[16] ? 6'd8 : - (f3_sfd__h565825[15] ? + (f3_sfd__h565824[15] ? 6'd9 : - (f3_sfd__h565825[14] ? + (f3_sfd__h565824[14] ? 6'd10 : - (f3_sfd__h565825[13] ? + (f3_sfd__h565824[13] ? 6'd11 : - (f3_sfd__h565825[12] ? + (f3_sfd__h565824[12] ? 6'd12 : - (f3_sfd__h565825[11] ? + (f3_sfd__h565824[11] ? 6'd13 : - (f3_sfd__h565825[10] ? + (f3_sfd__h565824[10] ? 6'd14 : - (f3_sfd__h565825[9] ? + (f3_sfd__h565824[9] ? 6'd15 : - (f3_sfd__h565825[8] ? + (f3_sfd__h565824[8] ? 6'd16 : - (f3_sfd__h565825[7] ? + (f3_sfd__h565824[7] ? 6'd17 : - (f3_sfd__h565825[6] ? + (f3_sfd__h565824[6] ? 6'd18 : - (f3_sfd__h565825[5] ? + (f3_sfd__h565824[5] ? 6'd19 : - (f3_sfd__h565825[4] ? + (f3_sfd__h565824[4] ? 6'd20 : - (f3_sfd__h565825[3] ? + (f3_sfd__h565824[3] ? 6'd21 : - (f3_sfd__h565825[2] ? + (f3_sfd__h565824[2] ? 6'd22 : - (f3_sfd__h565825[1] ? + (f3_sfd__h565824[1] ? 6'd23 : - (f3_sfd__h565825[0] ? + (f3_sfd__h565824[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815 = - (f3_exp__h565824 == 8'd255 && f3_sfd__h565825 != 23'd0 || - (f3_exp__h565824 == 8'd255 || f3_exp__h565824 == 8'd0) && - f3_sfd__h565825 == 23'd0) ? + (f3_exp__h565823 == 8'd255 && f3_sfd__h565824 != 23'd0 || + (f3_exp__h565823 == 8'd255 || f3_exp__h565823 == 8'd0) && + f3_sfd__h565824 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h565824 == 8'd0) ? + ((f3_exp__h565823 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 = - (f3_exp__h565824 == 8'd255 && f3_sfd__h565825 != 23'd0) ? - _theResult___snd_fst_sfd__h566140 : - _theResult___fst_sfd__h604280 ; + (f3_exp__h565823 == 8'd255 && f3_sfd__h565824 != 23'd0) ? + _theResult___snd_fst_sfd__h566139 : + _theResult___fst_sfd__h604279 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 = - { (f3_exp__h565824 == 8'd255) ? + { (f3_exp__h565823 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h604276, + _theResult___fst_exp__h604275, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 } ; assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875 = IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864 ? @@ -20278,7 +20261,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || - _theResult___fst_exp__h545767 == 11'd2047) ? + _theResult___fst_exp__h545766 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20286,12 +20269,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_guard37805_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || - _theResult___fst_exp__h506914 == 11'd2047) ? + _theResult___fst_exp__h506913 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20299,12 +20282,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard98952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || - _theResult___fst_exp__h585071 == 11'd2047) ? + _theResult___fst_exp__h585070 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20312,7 +20295,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard77109_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ? @@ -20796,48 +20779,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[2] : - _theResult___fst_exp__h526107 == 11'd2047 && - _theResult___fst_sfd__h526108 == 52'd0 ; + _theResult___fst_exp__h526106 == 11'd2047 && + _theResult___fst_sfd__h526107 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[2] : - _theResult___fst_exp__h564960 == 11'd2047 && - _theResult___fst_sfd__h564961 == 52'd0 ; + _theResult___fst_exp__h564959 == 11'd2047 && + _theResult___fst_sfd__h564960 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[2] : - _theResult___fst_exp__h604264 == 11'd2047 && - _theResult___fst_sfd__h604265 == 52'd0 ; + _theResult___fst_exp__h604263 == 11'd2047 && + _theResult___fst_sfd__h604264 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[1] : - _theResult___fst_exp__h525324 == 11'd0 && - guard__h517334 != 2'b0 ; + _theResult___fst_exp__h525323 == 11'd0 && + guard__h517333 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[1] : - _theResult___fst_exp__h564177 == 11'd0 && - guard__h556187 != 2'b0 ; + _theResult___fst_exp__h564176 == 11'd0 && + guard__h556186 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[1] : - _theResult___fst_exp__h603481 == 11'd0 && - guard__h595491 != 2'b0 ; + _theResult___fst_exp__h603480 == 11'd0 && + guard__h595490 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[0] : - _theResult___fst_exp__h525324 != 11'd2047 && - guard__h517334 != 2'b0 ; + _theResult___fst_exp__h525323 != 11'd2047 && + guard__h517333 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[0] : - _theResult___fst_exp__h564177 != 11'd2047 && - guard__h556187 != 2'b0 ; + _theResult___fst_exp__h564176 != 11'd2047 && + guard__h556186 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[0] : - _theResult___fst_exp__h603481 != 11'd2047 && - guard__h595491 != 2'b0 ; + _theResult___fst_exp__h603480 != 11'd2047 && + guard__h595490 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? @@ -20877,35 +20860,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h376612 == 8'd255) ? + ((_theResult___fst_exp__h376611 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180) : - ((_theResult___fst_exp__h385297 == 8'd255) ? + ((_theResult___fst_exp__h385296 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h376612 == 8'd255) ? + ((_theResult___fst_exp__h376611 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223) : - ((_theResult___fst_exp__h385297 == 8'd255) ? + ((_theResult___fst_exp__h385296 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[2] : - _theResult___fst_exp__h385845 == 8'd255 && - _theResult___fst_sfd__h385846 == 23'd0 ; + _theResult___fst_exp__h385844 == 8'd255 && + _theResult___fst_sfd__h385845 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[1] : - _theResult___fst_exp__h385297 == 8'd0 && - guard__h377220 != 2'b0 ; + _theResult___fst_exp__h385296 == 8'd0 && + guard__h377219 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[0] : - _theResult___fst_exp__h385297 != 8'd255 && - guard__h377220 != 2'b0 ; + _theResult___fst_exp__h385296 != 8'd255 && + guard__h377219 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? @@ -20915,35 +20898,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h422309 == 8'd255) ? + ((_theResult___fst_exp__h422308 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572) : - ((_theResult___fst_exp__h430994 == 8'd255) ? + ((_theResult___fst_exp__h430993 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h422309 == 8'd255) ? + ((_theResult___fst_exp__h422308 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615) : - ((_theResult___fst_exp__h430994 == 8'd255) ? + ((_theResult___fst_exp__h430993 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[2] : - _theResult___fst_exp__h431542 == 8'd255 && - _theResult___fst_sfd__h431543 == 23'd0 ; + _theResult___fst_exp__h431541 == 8'd255 && + _theResult___fst_sfd__h431542 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[1] : - _theResult___fst_exp__h430994 == 8'd0 && - guard__h422917 != 2'b0 ; + _theResult___fst_exp__h430993 == 8'd0 && + guard__h422916 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[0] : - _theResult___fst_exp__h430994 != 8'd255 && - guard__h422917 != 2'b0 ; + _theResult___fst_exp__h430993 != 8'd255 && + guard__h422916 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? @@ -20953,35 +20936,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h468004 == 8'd255) ? + ((_theResult___fst_exp__h468003 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964) : - ((_theResult___fst_exp__h476689 == 8'd255) ? + ((_theResult___fst_exp__h476688 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h468004 == 8'd255) ? + ((_theResult___fst_exp__h468003 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007) : - ((_theResult___fst_exp__h476689 == 8'd255) ? + ((_theResult___fst_exp__h476688 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[2] : - _theResult___fst_exp__h477237 == 8'd255 && - _theResult___fst_sfd__h477238 == 23'd0 ; + _theResult___fst_exp__h477236 == 8'd255 && + _theResult___fst_sfd__h477237 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[1] : - _theResult___fst_exp__h476689 == 8'd0 && - guard__h468612 != 2'b0 ; + _theResult___fst_exp__h476688 == 8'd0 && + guard__h468611 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[0] : - _theResult___fst_exp__h476689 != 8'd255 && - guard__h468612 != 2'b0 ; + _theResult___fst_exp__h476688 != 8'd255 && + guard__h468611 != 2'b0 ; assign IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 = checkForException___d13160[4] ? CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 : @@ -21639,8 +21622,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h653734 : - w__h653729 ; + result__h653732 : + w__h653727 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2112 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -21662,39 +21645,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h201749 : + n___1__h201748 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21747,7 +21730,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h200346 : + x__h200345 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 ? 64'd0 : 64'd1) ; @@ -21759,7 +21742,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 = - _theResult_____2__h301171 == v__h300591 ; + _theResult_____2__h301170 == v__h300590 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21768,7 +21751,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 = - _theResult_____2__h309167 == v__h303936 ; + _theResult_____2__h309166 == v__h303935 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21797,7 +21780,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h306801 } ; + x__h306800 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -21895,35 +21878,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h196841 : + n__h196840 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -21951,7 +21934,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 = - _theResult_____2__h315161 == v__h314450 ; + _theResult_____2__h315160 == v__h314449 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21960,7 +21943,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 = - _theResult_____2__h323015 == v__h318326 ; + _theResult_____2__h323014 == v__h318325 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -22112,7 +22095,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 = - _theResult_____2__h336584 == v__h336152 ; + _theResult_____2__h336583 == v__h336151 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -22161,7 +22144,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) : IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 = - _theResult_____2__h333359 == v__h332927 ; + _theResult_____2__h333358 == v__h332926 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -22225,8 +22208,8 @@ module mkCore(CLK, assign IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14035 = IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14028 || rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; @@ -22258,8 +22241,8 @@ module mkCore(CLK, IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13922 && (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14140 || rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && regRenamingTable$RDY_rename_1_getRename && + regRenamingTable$RDY_rename_1_claimRename && fetchStage_RDY_pipelines_1_deq__2940_AND_NOT_f_ETC___d14150) ; assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14436 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && @@ -22301,60 +22284,60 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h721999 : + y_avValue_snd_snd_snd_snd_snd__h722001 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 = - rob$deqPort_0_canDeq ? y_avValue_fst__h721559 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_fst__h721561 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h721993 : + y_avValue_snd_snd_snd_fst__h721995 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4990_THEN_IF_NOT_rob__ETC___d15197 = rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__4993_BIT_25_499_ETC___d15196 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin04537_BIT_33_THEN_2_ELSE_0__q57 = - sfdin__h404537[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin16485_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h516485[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin22303_BIT_33_THEN_2_ELSE_0__q67 = - sfdin__h422303[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin50232_BIT_33_THEN_2_ELSE_0__q92 = - sfdin__h450232[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin55338_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h555338[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin58840_BIT_33_THEN_2_ELSE_0__q22 = - sfdin__h358840[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin67998_BIT_33_THEN_2_ELSE_0__q102 = - sfdin__h467998[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin76606_BIT_33_THEN_2_ELSE_0__q32 = - sfdin__h376606[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin94642_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h594642[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd03427_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h603427[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06865_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h506865[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd13150_BIT_33_THEN_2_ELSE_0__q59 = - _theResult___snd__h413150[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd25270_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h525270[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30940_BIT_33_THEN_2_ELSE_0__q72 = - _theResult___snd__h430940[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd45718_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h545718[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58845_BIT_33_THEN_2_ELSE_0__q94 = - _theResult___snd__h458845[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd64123_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h564123[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd67453_BIT_33_THEN_2_ELSE_0__q24 = - _theResult___snd__h367453[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76635_BIT_33_THEN_2_ELSE_0__q107 = - _theResult___snd__h476635[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd85022_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h585022[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd85243_BIT_33_THEN_2_ELSE_0__q37 = - _theResult___snd__h385243[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin04536_BIT_33_THEN_2_ELSE_0__q57 = + sfdin__h404536[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin16484_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h516484[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin22302_BIT_33_THEN_2_ELSE_0__q67 = + sfdin__h422302[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin50231_BIT_33_THEN_2_ELSE_0__q92 = + sfdin__h450231[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin55337_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h555337[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin58839_BIT_33_THEN_2_ELSE_0__q22 = + sfdin__h358839[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin67997_BIT_33_THEN_2_ELSE_0__q102 = + sfdin__h467997[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin76605_BIT_33_THEN_2_ELSE_0__q32 = + sfdin__h376605[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin94641_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h594641[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd03426_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h603426[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06864_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h506864[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd13149_BIT_33_THEN_2_ELSE_0__q59 = + _theResult___snd__h413149[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd25269_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h525269[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30939_BIT_33_THEN_2_ELSE_0__q72 = + _theResult___snd__h430939[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd45717_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h545717[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58844_BIT_33_THEN_2_ELSE_0__q94 = + _theResult___snd__h458844[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd64122_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h564122[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd67452_BIT_33_THEN_2_ELSE_0__q24 = + _theResult___snd__h367452[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76634_BIT_33_THEN_2_ELSE_0__q107 = + _theResult___snd__h476634[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd85021_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h585021[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd85242_BIT_33_THEN_2_ELSE_0__q37 = + _theResult___snd__h385242[33] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? @@ -22434,133 +22417,133 @@ module mkCore(CLK, !checkForException___d13792[4] && NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13817 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4986_4987_OR__ETC___d15202 = - (fflags__h722582 & csrf_fflags_reg) != fflags__h722582 || - !r__h619420 && + (fflags__h722584 & csrf_fflags_reg) != fflags__h722584 || + !r__h619419 && (IF_rob_deqPort_1_canDeq__4990_THEN_IF_NOT_rob__ETC___d15197 || - fflags__h722582 != 5'd0) ; + fflags__h722584 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 = - !f2_sfd__h526521[21] && !f2_sfd__h526521[20] && - !f2_sfd__h526521[19] && - !f2_sfd__h526521[18] && - !f2_sfd__h526521[17] && - !f2_sfd__h526521[16] && - !f2_sfd__h526521[15] && - !f2_sfd__h526521[14] && - !f2_sfd__h526521[13] && - !f2_sfd__h526521[12] && - !f2_sfd__h526521[11] && - !f2_sfd__h526521[10] && - !f2_sfd__h526521[9] && - !f2_sfd__h526521[8] && - !f2_sfd__h526521[7] && - !f2_sfd__h526521[6] && - !f2_sfd__h526521[5] && - !f2_sfd__h526521[4] && - !f2_sfd__h526521[3] && - !f2_sfd__h526521[2] && - !f2_sfd__h526521[1] && - !f2_sfd__h526521[0] ; + !f2_sfd__h526520[21] && !f2_sfd__h526520[20] && + !f2_sfd__h526520[19] && + !f2_sfd__h526520[18] && + !f2_sfd__h526520[17] && + !f2_sfd__h526520[16] && + !f2_sfd__h526520[15] && + !f2_sfd__h526520[14] && + !f2_sfd__h526520[13] && + !f2_sfd__h526520[12] && + !f2_sfd__h526520[11] && + !f2_sfd__h526520[10] && + !f2_sfd__h526520[9] && + !f2_sfd__h526520[8] && + !f2_sfd__h526520[7] && + !f2_sfd__h526520[6] && + !f2_sfd__h526520[5] && + !f2_sfd__h526520[4] && + !f2_sfd__h526520[3] && + !f2_sfd__h526520[2] && + !f2_sfd__h526520[1] && + !f2_sfd__h526520[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 == 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 != 23'd0) && + (f1_exp__h487525 != 8'd0 || f1_sfd__h487526 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526519 != 8'd255 || f2_sfd__h526520 == 23'd0) && + (f2_exp__h526519 != 8'd255 || f2_sfd__h526520 != 23'd0) && + (f2_exp__h526519 != 8'd0 || f2_sfd__h526520 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 == 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 != 23'd0) && + (f1_exp__h487525 != 8'd0 || f1_sfd__h487526 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526519 != 8'd255 || f2_sfd__h526520 == 23'd0) && + (f2_exp__h526519 != 8'd255 || f2_sfd__h526520 != 23'd0) && + (f2_exp__h526519 != 8'd0 || f2_sfd__h526520 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 == 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 != 23'd0) && + (f1_exp__h487525 != 8'd0 || f1_sfd__h487526 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526519 != 8'd255 || f2_sfd__h526520 == 23'd0) && + (f2_exp__h526519 != 8'd255 || f2_sfd__h526520 != 23'd0) && + (f2_exp__h526519 != 8'd0 || f2_sfd__h526520 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 == 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 != 23'd0) && + (f1_exp__h487525 != 8'd0 || f1_sfd__h487526 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526519 != 8'd255 || f2_sfd__h526520 == 23'd0) && + (f2_exp__h526519 != 8'd255 || f2_sfd__h526520 != 23'd0) && + (f2_exp__h526519 != 8'd0 || f2_sfd__h526520 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 == 23'd0) && + (f1_exp__h487525 != 8'd255 || f1_sfd__h487526 != 23'd0) && + (f1_exp__h487525 != 8'd0 || f1_sfd__h487526 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526519 != 8'd255 || f2_sfd__h526520 == 23'd0) && + (f2_exp__h526519 != 8'd255 || f2_sfd__h526520 != 23'd0) && + (f2_exp__h526519 != 8'd0 || f2_sfd__h526520 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 = - !f1_sfd__h487527[21] && !f1_sfd__h487527[20] && - !f1_sfd__h487527[19] && - !f1_sfd__h487527[18] && - !f1_sfd__h487527[17] && - !f1_sfd__h487527[16] && - !f1_sfd__h487527[15] && - !f1_sfd__h487527[14] && - !f1_sfd__h487527[13] && - !f1_sfd__h487527[12] && - !f1_sfd__h487527[11] && - !f1_sfd__h487527[10] && - !f1_sfd__h487527[9] && - !f1_sfd__h487527[8] && - !f1_sfd__h487527[7] && - !f1_sfd__h487527[6] && - !f1_sfd__h487527[5] && - !f1_sfd__h487527[4] && - !f1_sfd__h487527[3] && - !f1_sfd__h487527[2] && - !f1_sfd__h487527[1] && - !f1_sfd__h487527[0] ; + !f1_sfd__h487526[21] && !f1_sfd__h487526[20] && + !f1_sfd__h487526[19] && + !f1_sfd__h487526[18] && + !f1_sfd__h487526[17] && + !f1_sfd__h487526[16] && + !f1_sfd__h487526[15] && + !f1_sfd__h487526[14] && + !f1_sfd__h487526[13] && + !f1_sfd__h487526[12] && + !f1_sfd__h487526[11] && + !f1_sfd__h487526[10] && + !f1_sfd__h487526[9] && + !f1_sfd__h487526[8] && + !f1_sfd__h487526[7] && + !f1_sfd__h487526[6] && + !f1_sfd__h487526[5] && + !f1_sfd__h487526[4] && + !f1_sfd__h487526[3] && + !f1_sfd__h487526[2] && + !f1_sfd__h487526[1] && + !f1_sfd__h487526[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 = - !f3_sfd__h565825[21] && !f3_sfd__h565825[20] && - !f3_sfd__h565825[19] && - !f3_sfd__h565825[18] && - !f3_sfd__h565825[17] && - !f3_sfd__h565825[16] && - !f3_sfd__h565825[15] && - !f3_sfd__h565825[14] && - !f3_sfd__h565825[13] && - !f3_sfd__h565825[12] && - !f3_sfd__h565825[11] && - !f3_sfd__h565825[10] && - !f3_sfd__h565825[9] && - !f3_sfd__h565825[8] && - !f3_sfd__h565825[7] && - !f3_sfd__h565825[6] && - !f3_sfd__h565825[5] && - !f3_sfd__h565825[4] && - !f3_sfd__h565825[3] && - !f3_sfd__h565825[2] && - !f3_sfd__h565825[1] && - !f3_sfd__h565825[0] ; + !f3_sfd__h565824[21] && !f3_sfd__h565824[20] && + !f3_sfd__h565824[19] && + !f3_sfd__h565824[18] && + !f3_sfd__h565824[17] && + !f3_sfd__h565824[16] && + !f3_sfd__h565824[15] && + !f3_sfd__h565824[14] && + !f3_sfd__h565824[13] && + !f3_sfd__h565824[12] && + !f3_sfd__h565824[11] && + !f3_sfd__h565824[10] && + !f3_sfd__h565824[9] && + !f3_sfd__h565824[8] && + !f3_sfd__h565824[7] && + !f3_sfd__h565824[6] && + !f3_sfd__h565824[5] && + !f3_sfd__h565824[4] && + !f3_sfd__h565824[3] && + !f3_sfd__h565824[2] && + !f3_sfd__h565824[1] && + !f3_sfd__h565824[0] ; assign NOT_IF_rob_deqPort_0_deq_data__4451_BITS_97_TO_ETC___d14957 = - next_pc__h718596 != + next_pc__h718597 != rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954 ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13588 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13586 && @@ -23163,7 +23146,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 && !csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 && - csr_addr__h661836 != 12'h8FF) ; + csr_addr__h661834 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13526 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -23293,9 +23276,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h661837 == 5'd0 && - imm__h661838 == 32'd0 || - csr_addr__h661836[11:10] != 2'b11 ; + rs1__h661835 == 5'd0 && + imm__h661836 == 32'd0 || + csr_addr__h661834[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13533 = fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -23360,7 +23343,7 @@ module mkCore(CLK, specTagManager$currentSpecBits } ; assign NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14192 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h670385 ; + fallthrough_pc__h670383 ; assign NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13581 = !fetchStage$pipelines_0_first[68] && !checkForException___d13160[4] && @@ -23442,7 +23425,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[173] ; assign NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14358 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h686131 ; + fallthrough_pc__h686129 ; assign NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14301 = !fetchStage$pipelines_1_first[68] && !checkForException___d13792[4] && @@ -23471,12 +23454,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -23643,7 +23626,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - x__h296161 } ; + x__h296160 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15324 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, @@ -23668,8 +23651,8 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13889 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 = - { {4{f2_exp26520_MINUS_127__q168[7]}}, - f2_exp26520_MINUS_127__q168 } ; + { {4{f2_exp26519_MINUS_127__q168[7]}}, + f2_exp26519_MINUS_127__q168 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 ^ 12'h800) <= @@ -23679,12 +23662,12 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187 = - b__h608520 * b__h608596 ; + b__h608519 * b__h608595 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200 = - b__h608520 * b__h608709 ; + b__h608519 * b__h608708 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 = - { {4{f1_exp87526_MINUS_127__q128[7]}}, - f1_exp87526_MINUS_127__q128 } ; + { {4{f1_exp87525_MINUS_127__q128[7]}}, + f1_exp87525_MINUS_127__q128 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 ^ 12'h800) <= @@ -23694,8 +23677,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 = - { {4{f3_exp65824_MINUS_127__q145[7]}}, - f3_exp65824_MINUS_127__q145 } ; + { {4{f3_exp65823_MINUS_127__q145[7]}}, + f3_exp65823_MINUS_127__q145 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ^ 12'h800) <= @@ -23780,15 +23763,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265 = { 3'd0, - _theResult___fst_exp__h358846 == 8'd0 && - (sfdin__h358840[56:34] == 23'd0 || guard__h350745 != 2'b0), + _theResult___fst_exp__h358845 == 8'd0 && + (sfdin__h358839[56:34] == 23'd0 || guard__h350744 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h359443 == 8'd255 && - _theResult___fst_sfd__h359444 == 23'd0, + _theResult___fst_exp__h359442 == 8'd255 && + _theResult___fst_sfd__h359443 == 23'd0, 1'd0, - _theResult___fst_exp__h358846 != 8'd255 && - guard__h350745 != 2'b0 } ; + _theResult___fst_exp__h358845 != 8'd255 && + guard__h350744 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ^ @@ -23796,15 +23779,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657 = { 3'd0, - _theResult___fst_exp__h404543 == 8'd0 && - (sfdin__h404537[56:34] == 23'd0 || guard__h396444 != 2'b0), + _theResult___fst_exp__h404542 == 8'd0 && + (sfdin__h404536[56:34] == 23'd0 || guard__h396443 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h405140 == 8'd255 && - _theResult___fst_sfd__h405141 == 23'd0, + _theResult___fst_exp__h405139 == 8'd255 && + _theResult___fst_sfd__h405140 == 23'd0, 1'd0, - _theResult___fst_exp__h404543 != 8'd255 && - guard__h396444 != 2'b0 } ; + _theResult___fst_exp__h404542 != 8'd255 && + guard__h396443 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ^ @@ -23812,15 +23795,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049 = { 3'd0, - _theResult___fst_exp__h450238 == 8'd0 && - (sfdin__h450232[56:34] == 23'd0 || guard__h442139 != 2'b0), + _theResult___fst_exp__h450237 == 8'd0 && + (sfdin__h450231[56:34] == 23'd0 || guard__h442138 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h450835 == 8'd255 && - _theResult___fst_sfd__h450836 == 23'd0, + _theResult___fst_exp__h450834 == 8'd255 && + _theResult___fst_sfd__h450835 == 23'd0, 1'd0, - _theResult___fst_exp__h450238 != 8'd255 && - guard__h442139 != 2'b0 } ; + _theResult___fst_exp__h450237 != 8'd255 && + guard__h442138 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ^ @@ -23828,37 +23811,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869 = { 3'd0, - _theResult___fst_exp__h516491 == 11'd0 && - (sfdin__h516485[56:5] == 52'd0 || guard__h508265 != 2'b0), + _theResult___fst_exp__h516490 == 11'd0 && + (sfdin__h516484[56:5] == 52'd0 || guard__h508264 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h517323 == 11'd2047 && - _theResult___fst_sfd__h517324 == 52'd0, + _theResult___fst_exp__h517322 == 11'd2047 && + _theResult___fst_sfd__h517323 == 52'd0, 1'd0, - _theResult___fst_exp__h516491 != 11'd2047 && - guard__h508265 != 2'b0 } ; + _theResult___fst_exp__h516490 != 11'd2047 && + guard__h508264 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910 = { 3'd0, - _theResult___fst_exp__h555344 == 11'd0 && - (sfdin__h555338[56:5] == 52'd0 || guard__h547118 != 2'b0), + _theResult___fst_exp__h555343 == 11'd0 && + (sfdin__h555337[56:5] == 52'd0 || guard__h547117 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h556176 == 11'd2047 && - _theResult___fst_sfd__h556177 == 52'd0, + _theResult___fst_exp__h556175 == 11'd2047 && + _theResult___fst_sfd__h556176 == 52'd0, 1'd0, - _theResult___fst_exp__h555344 != 11'd2047 && - guard__h547118 != 2'b0 } ; + _theResult___fst_exp__h555343 != 11'd2047 && + guard__h547117 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954 = { 3'd0, - _theResult___fst_exp__h594648 == 11'd0 && - (sfdin__h594642[56:5] == 52'd0 || guard__h586422 != 2'b0), + _theResult___fst_exp__h594647 == 11'd0 && + (sfdin__h594641[56:5] == 52'd0 || guard__h586421 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h595480 == 11'd2047 && - _theResult___fst_sfd__h595481 == 52'd0, + _theResult___fst_exp__h595479 == 11'd2047 && + _theResult___fst_sfd__h595480 == 52'd0, 1'd0, - _theResult___fst_exp__h594648 != 11'd2047 && - guard__h586422 != 2'b0 } ; + _theResult___fst_exp__h594647 != 11'd2047 && + guard__h586421 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ^ @@ -23876,15 +23859,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294 = { 3'd0, - _theResult___fst_exp__h376612 == 8'd0 && - (sfdin__h376606[56:34] == 23'd0 || guard__h368384 != 2'b0), + _theResult___fst_exp__h376611 == 8'd0 && + (sfdin__h376605[56:34] == 23'd0 || guard__h368383 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h377209 == 8'd255 && - _theResult___fst_sfd__h377210 == 23'd0, + _theResult___fst_exp__h377208 == 8'd255 && + _theResult___fst_sfd__h377209 == 23'd0, 1'd0, - _theResult___fst_exp__h376612 != 8'd255 && - guard__h368384 != 2'b0 } ; + _theResult___fst_exp__h376611 != 8'd255 && + guard__h368383 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ^ @@ -23892,15 +23875,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686 = { 3'd0, - _theResult___fst_exp__h422309 == 8'd0 && - (sfdin__h422303[56:34] == 23'd0 || guard__h414081 != 2'b0), + _theResult___fst_exp__h422308 == 8'd0 && + (sfdin__h422302[56:34] == 23'd0 || guard__h414080 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h422906 == 8'd255 && - _theResult___fst_sfd__h422907 == 23'd0, + _theResult___fst_exp__h422905 == 8'd255 && + _theResult___fst_sfd__h422906 == 23'd0, 1'd0, - _theResult___fst_exp__h422309 != 8'd255 && - guard__h414081 != 2'b0 } ; + _theResult___fst_exp__h422308 != 8'd255 && + guard__h414080 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ^ @@ -23908,15 +23891,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078 = { 3'd0, - _theResult___fst_exp__h468004 == 8'd0 && - (sfdin__h467998[56:34] == 23'd0 || guard__h459776 != 2'b0), + _theResult___fst_exp__h468003 == 8'd0 && + (sfdin__h467997[56:34] == 23'd0 || guard__h459775 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h468601 == 8'd255 && - _theResult___fst_sfd__h468602 == 23'd0, + _theResult___fst_exp__h468600 == 8'd255 && + _theResult___fst_sfd__h468601 == 23'd0, 1'd0, - _theResult___fst_exp__h468004 != 8'd255 && - guard__h459776 != 2'b0 } ; + _theResult___fst_exp__h468003 != 8'd255 && + guard__h459775 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ^ @@ -23930,37 +23913,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852 = { 3'd0, - _theResult___fst_exp__h506914 == 11'd0 && - guard__h498953 != 2'b0, + _theResult___fst_exp__h506913 == 11'd0 && + guard__h498952 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h507672 == 11'd2047 && - _theResult___fst_sfd__h507673 == 52'd0, + _theResult___fst_exp__h507671 == 11'd2047 && + _theResult___fst_sfd__h507672 == 52'd0, 1'd0, - _theResult___fst_exp__h506914 != 11'd2047 && - guard__h498953 != 2'b0 } ; + _theResult___fst_exp__h506913 != 11'd2047 && + guard__h498952 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893 = { 3'd0, - _theResult___fst_exp__h545767 == 11'd0 && - guard__h537806 != 2'b0, + _theResult___fst_exp__h545766 == 11'd0 && + guard__h537805 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h546525 == 11'd2047 && - _theResult___fst_sfd__h546526 == 52'd0, + _theResult___fst_exp__h546524 == 11'd2047 && + _theResult___fst_sfd__h546525 == 52'd0, 1'd0, - _theResult___fst_exp__h545767 != 11'd2047 && - guard__h537806 != 2'b0 } ; + _theResult___fst_exp__h545766 != 11'd2047 && + guard__h537805 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937 = { 3'd0, - _theResult___fst_exp__h585071 == 11'd0 && - guard__h577110 != 2'b0, + _theResult___fst_exp__h585070 == 11'd0 && + guard__h577109 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h585829 == 11'd2047 && - _theResult___fst_sfd__h585830 == 52'd0, + _theResult___fst_exp__h585828 == 11'd2047 && + _theResult___fst_sfd__h585829 == 52'd0, 1'd0, - _theResult___fst_exp__h585071 != 11'd2047 && - guard__h577110 != 2'b0 } ; + _theResult___fst_exp__h585070 != 11'd2047 && + guard__h577109 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ^ @@ -23996,15 +23979,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277 = { 3'd0, - _theResult___fst_exp__h367502 == 8'd0 && - guard__h359454 != 2'b0, + _theResult___fst_exp__h367501 == 8'd0 && + guard__h359453 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h368025 == 8'd255 && - _theResult___fst_sfd__h368026 == 23'd0, + _theResult___fst_exp__h368024 == 8'd255 && + _theResult___fst_sfd__h368025 == 23'd0, 1'd0, - _theResult___fst_exp__h367502 != 8'd255 && - guard__h359454 != 2'b0 } ; + _theResult___fst_exp__h367501 != 8'd255 && + guard__h359453 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ^ @@ -24018,15 +24001,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669 = { 3'd0, - _theResult___fst_exp__h413199 == 8'd0 && - guard__h405151 != 2'b0, + _theResult___fst_exp__h413198 == 8'd0 && + guard__h405150 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h413722 == 8'd255 && - _theResult___fst_sfd__h413723 == 23'd0, + _theResult___fst_exp__h413721 == 8'd255 && + _theResult___fst_sfd__h413722 == 23'd0, 1'd0, - _theResult___fst_exp__h413199 != 8'd255 && - guard__h405151 != 2'b0 } ; + _theResult___fst_exp__h413198 != 8'd255 && + guard__h405150 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ^ @@ -24040,21 +24023,21 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061 = { 3'd0, - _theResult___fst_exp__h458894 == 8'd0 && - guard__h450846 != 2'b0, + _theResult___fst_exp__h458893 == 8'd0 && + guard__h450845 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h459417 == 8'd255 && - _theResult___fst_sfd__h459418 == 23'd0, + _theResult___fst_exp__h459416 == 8'd255 && + _theResult___fst_sfd__h459417 == 23'd0, 1'd0, - _theResult___fst_exp__h458894 != 8'd255 && - guard__h450846 != 2'b0 } ; + _theResult___fst_exp__h458893 != 8'd255 && + guard__h450845 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193 = - b__h608697 * b__h608709 ; + b__h608696 * b__h608708 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14009 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 ; + CASE_k74091_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14094 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -24066,33 +24049,33 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13889 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249 = - sfd__h526882 >> + sfd__h526881 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764 = - sfd__h487888 >> + sfd__h487887 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479 = - sfd__h566186 >> + sfd__h566185 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654 = - sfd__h343130 >> + sfd__h343129 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046 = - sfd__h388832 >> + sfd__h388831 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438 = - sfd__h434527 >> + sfd__h434526 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14629 = - medeleg_csr__read__h617227[i__h707772] ; + medeleg_csr__read__h617226[i__h707772] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14610 = - mideleg_csr__read__h617322[i__h707932] ; + mideleg_csr__read__h617321[i__h707932] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 = 12'd3074 - { 6'd0, @@ -24498,51 +24481,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120 = 12'd3970 - { 7'd0, - f2_sfd__h526521[22] ? + f2_sfd__h526520[22] ? 5'd0 : - (f2_sfd__h526521[21] ? + (f2_sfd__h526520[21] ? 5'd1 : - (f2_sfd__h526521[20] ? + (f2_sfd__h526520[20] ? 5'd2 : - (f2_sfd__h526521[19] ? + (f2_sfd__h526520[19] ? 5'd3 : - (f2_sfd__h526521[18] ? + (f2_sfd__h526520[18] ? 5'd4 : - (f2_sfd__h526521[17] ? + (f2_sfd__h526520[17] ? 5'd5 : - (f2_sfd__h526521[16] ? + (f2_sfd__h526520[16] ? 5'd6 : - (f2_sfd__h526521[15] ? + (f2_sfd__h526520[15] ? 5'd7 : - (f2_sfd__h526521[14] ? + (f2_sfd__h526520[14] ? 5'd8 : - (f2_sfd__h526521[13] ? + (f2_sfd__h526520[13] ? 5'd9 : - (f2_sfd__h526521[12] ? + (f2_sfd__h526520[12] ? 5'd10 : - (f2_sfd__h526521[11] ? + (f2_sfd__h526520[11] ? 5'd11 : - (f2_sfd__h526521[10] ? + (f2_sfd__h526520[10] ? 5'd12 : - (f2_sfd__h526521[9] ? + (f2_sfd__h526520[9] ? 5'd13 : - (f2_sfd__h526521[8] ? + (f2_sfd__h526520[8] ? 5'd14 : - (f2_sfd__h526521[7] ? + (f2_sfd__h526520[7] ? 5'd15 : - (f2_sfd__h526521[6] ? + (f2_sfd__h526520[6] ? 5'd16 : - (f2_sfd__h526521[5] ? + (f2_sfd__h526520[5] ? 5'd17 : - (f2_sfd__h526521[4] ? + (f2_sfd__h526520[4] ? 5'd18 : - (f2_sfd__h526521[3] ? + (f2_sfd__h526520[3] ? 5'd19 : - (f2_sfd__h526521[2] ? + (f2_sfd__h526520[2] ? 5'd20 : - (f2_sfd__h526521[1] ? + (f2_sfd__h526520[1] ? 5'd21 : - (f2_sfd__h526521[0] ? + (f2_sfd__h526520[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 = @@ -24556,51 +24539,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620 = 12'd3970 - { 7'd0, - f1_sfd__h487527[22] ? + f1_sfd__h487526[22] ? 5'd0 : - (f1_sfd__h487527[21] ? + (f1_sfd__h487526[21] ? 5'd1 : - (f1_sfd__h487527[20] ? + (f1_sfd__h487526[20] ? 5'd2 : - (f1_sfd__h487527[19] ? + (f1_sfd__h487526[19] ? 5'd3 : - (f1_sfd__h487527[18] ? + (f1_sfd__h487526[18] ? 5'd4 : - (f1_sfd__h487527[17] ? + (f1_sfd__h487526[17] ? 5'd5 : - (f1_sfd__h487527[16] ? + (f1_sfd__h487526[16] ? 5'd6 : - (f1_sfd__h487527[15] ? + (f1_sfd__h487526[15] ? 5'd7 : - (f1_sfd__h487527[14] ? + (f1_sfd__h487526[14] ? 5'd8 : - (f1_sfd__h487527[13] ? + (f1_sfd__h487526[13] ? 5'd9 : - (f1_sfd__h487527[12] ? + (f1_sfd__h487526[12] ? 5'd10 : - (f1_sfd__h487527[11] ? + (f1_sfd__h487526[11] ? 5'd11 : - (f1_sfd__h487527[10] ? + (f1_sfd__h487526[10] ? 5'd12 : - (f1_sfd__h487527[9] ? + (f1_sfd__h487526[9] ? 5'd13 : - (f1_sfd__h487527[8] ? + (f1_sfd__h487526[8] ? 5'd14 : - (f1_sfd__h487527[7] ? + (f1_sfd__h487526[7] ? 5'd15 : - (f1_sfd__h487527[6] ? + (f1_sfd__h487526[6] ? 5'd16 : - (f1_sfd__h487527[5] ? + (f1_sfd__h487526[5] ? 5'd17 : - (f1_sfd__h487527[4] ? + (f1_sfd__h487526[4] ? 5'd18 : - (f1_sfd__h487527[3] ? + (f1_sfd__h487526[3] ? 5'd19 : - (f1_sfd__h487527[2] ? + (f1_sfd__h487526[2] ? 5'd20 : - (f1_sfd__h487527[1] ? + (f1_sfd__h487526[1] ? 5'd21 : - (f1_sfd__h487527[0] ? + (f1_sfd__h487526[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 = @@ -24614,51 +24597,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350 = 12'd3970 - { 7'd0, - f3_sfd__h565825[22] ? + f3_sfd__h565824[22] ? 5'd0 : - (f3_sfd__h565825[21] ? + (f3_sfd__h565824[21] ? 5'd1 : - (f3_sfd__h565825[20] ? + (f3_sfd__h565824[20] ? 5'd2 : - (f3_sfd__h565825[19] ? + (f3_sfd__h565824[19] ? 5'd3 : - (f3_sfd__h565825[18] ? + (f3_sfd__h565824[18] ? 5'd4 : - (f3_sfd__h565825[17] ? + (f3_sfd__h565824[17] ? 5'd5 : - (f3_sfd__h565825[16] ? + (f3_sfd__h565824[16] ? 5'd6 : - (f3_sfd__h565825[15] ? + (f3_sfd__h565824[15] ? 5'd7 : - (f3_sfd__h565825[14] ? + (f3_sfd__h565824[14] ? 5'd8 : - (f3_sfd__h565825[13] ? + (f3_sfd__h565824[13] ? 5'd9 : - (f3_sfd__h565825[12] ? + (f3_sfd__h565824[12] ? 5'd10 : - (f3_sfd__h565825[11] ? + (f3_sfd__h565824[11] ? 5'd11 : - (f3_sfd__h565825[10] ? + (f3_sfd__h565824[10] ? 5'd12 : - (f3_sfd__h565825[9] ? + (f3_sfd__h565824[9] ? 5'd13 : - (f3_sfd__h565825[8] ? + (f3_sfd__h565824[8] ? 5'd14 : - (f3_sfd__h565825[7] ? + (f3_sfd__h565824[7] ? 5'd15 : - (f3_sfd__h565825[6] ? + (f3_sfd__h565824[6] ? 5'd16 : - (f3_sfd__h565825[5] ? + (f3_sfd__h565824[5] ? 5'd17 : - (f3_sfd__h565825[4] ? + (f3_sfd__h565824[4] ? 5'd18 : - (f3_sfd__h565825[3] ? + (f3_sfd__h565824[3] ? 5'd19 : - (f3_sfd__h565825[2] ? + (f3_sfd__h565824[2] ? 5'd20 : - (f3_sfd__h565825[1] ? + (f3_sfd__h565824[1] ? 5'd21 : - (f3_sfd__h565825[0] ? + (f3_sfd__h565824[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 = @@ -24687,7 +24670,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14371 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h674093 == 1'd0 && + k__h674091 == 1'd0 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171 || fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14290 == 1'd0 && @@ -24706,7 +24689,7 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == 6'd18 || rob$deqPort_0_deq_data[257:253] == 5'd20 ; - assign _dfoo28 = + assign _dfoo26 = rob$deqPort_0_deq_data[257:253] == 5'd13 && (IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == 6'd8 || @@ -24794,1421 +24777,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h301171 = + assign _theResult_____2__h301170 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142) ? - next_deqP___1__h301450 : + next_deqP___1__h301449 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h309167 = + assign _theResult_____2__h309166 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249) ? - next_deqP___1__h309446 : + next_deqP___1__h309445 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h315161 = + assign _theResult_____2__h315160 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420) ? - next_deqP___1__h315727 : + next_deqP___1__h315726 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h323015 = + assign _theResult_____2__h323014 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516) ? - next_deqP___1__h323581 : + next_deqP___1__h323580 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h333359 = + assign _theResult_____2__h333358 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745) ? - next_deqP___1__h333638 : + next_deqP___1__h333637 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h336584 = + assign _theResult_____2__h336583 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839) ? - next_deqP___1__h336863 : + next_deqP___1__h336862 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h350735 = - (value__h351357 == 54'd0) ? sfd__h343130 : 57'd1 ; - assign _theResult____h368374 = + assign _theResult____h350734 = + (value__h351356 == 54'd0) ? sfd__h343129 : 57'd1 ; + assign _theResult____h368373 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ^ 12'h800) < 12'd2105) ? - result__h368987 : - _theResult____h350735 ; - assign _theResult____h396434 = - (value__h397054 == 54'd0) ? sfd__h388832 : 57'd1 ; - assign _theResult____h414071 = + result__h368986 : + _theResult____h350734 ; + assign _theResult____h396433 = + (value__h397053 == 54'd0) ? sfd__h388831 : 57'd1 ; + assign _theResult____h414070 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ^ 12'h800) < 12'd2105) ? - result__h414684 : - _theResult____h396434 ; - assign _theResult____h442129 = - (value__h442749 == 54'd0) ? sfd__h434527 : 57'd1 ; - assign _theResult____h459766 = + result__h414683 : + _theResult____h396433 ; + assign _theResult____h442128 = + (value__h442748 == 54'd0) ? sfd__h434526 : 57'd1 ; + assign _theResult____h459765 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ^ 12'h800) < 12'd2105) ? - result__h460379 : - _theResult____h442129 ; - assign _theResult____h508255 = + result__h460378 : + _theResult____h442128 ; + assign _theResult____h508254 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ^ 12'h800) < 12'd2105) ? - result__h508868 : - ((value__h492471 == 25'd0) ? sfd__h487888 : 57'd1) ; - assign _theResult____h547108 = + result__h508867 : + ((value__h492470 == 25'd0) ? sfd__h487887 : 57'd1) ; + assign _theResult____h547107 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ^ 12'h800) < 12'd2105) ? - result__h547721 : - ((value__h531324 == 25'd0) ? sfd__h526882 : 57'd1) ; - assign _theResult____h586412 = + result__h547720 : + ((value__h531323 == 25'd0) ? sfd__h526881 : 57'd1) ; + assign _theResult____h586411 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ^ 12'h800) < 12'd2105) ? - result__h587025 : - ((value__h570628 == 25'd0) ? sfd__h566186 : 57'd1) ; - assign _theResult____h658027 = + result__h587024 : + ((value__h570627 == 25'd0) ? sfd__h566185 : 57'd1) ; + assign _theResult____h658025 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h658440 : + enabled_ints___1__h658438 : 12'd0 ; - assign _theResult___exp__h359362 = - sfd__h358938[24] ? - ((_theResult___fst_exp__h358846 == 8'd254) ? + assign _theResult___exp__h359361 = + sfd__h358937[24] ? + ((_theResult___fst_exp__h358845 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385879) : - ((_theResult___fst_exp__h358846 == 8'd0 && - sfd__h358938[24:23] == 2'b01) ? + din_inc___2_exp__h385878) : + ((_theResult___fst_exp__h358845 == 8'd0 && + sfd__h358937[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h358846) ; - assign _theResult___exp__h367944 = - sfd__h367520[24] ? - ((_theResult___fst_exp__h367502 == 8'd254) ? + _theResult___fst_exp__h358845) ; + assign _theResult___exp__h367943 = + sfd__h367519[24] ? + ((_theResult___fst_exp__h367501 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385903) : - ((_theResult___fst_exp__h367502 == 8'd0 && - sfd__h367520[24:23] == 2'b01) ? + din_inc___2_exp__h385902) : + ((_theResult___fst_exp__h367501 == 8'd0 && + sfd__h367519[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h367502) ; - assign _theResult___exp__h377128 = - sfd__h376704[24] ? - ((_theResult___fst_exp__h376612 == 8'd254) ? + _theResult___fst_exp__h367501) ; + assign _theResult___exp__h377127 = + sfd__h376703[24] ? + ((_theResult___fst_exp__h376611 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385933) : - ((_theResult___fst_exp__h376612 == 8'd0 && - sfd__h376704[24:23] == 2'b01) ? + din_inc___2_exp__h385932) : + ((_theResult___fst_exp__h376611 == 8'd0 && + sfd__h376703[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h376612) ; - assign _theResult___exp__h385764 = - sfd__h385316[24] ? - ((_theResult___fst_exp__h385297 == 8'd254) ? + _theResult___fst_exp__h376611) ; + assign _theResult___exp__h385763 = + sfd__h385315[24] ? + ((_theResult___fst_exp__h385296 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385957) : - ((_theResult___fst_exp__h385297 == 8'd0 && - sfd__h385316[24:23] == 2'b01) ? + din_inc___2_exp__h385956) : + ((_theResult___fst_exp__h385296 == 8'd0 && + sfd__h385315[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h385297) ; - assign _theResult___exp__h385866 = + _theResult___fst_exp__h385296) ; + assign _theResult___exp__h385865 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385857 ; - assign _theResult___exp__h405059 = - sfd__h404635[24] ? - ((_theResult___fst_exp__h404543 == 8'd254) ? + _theResult___fst_exp__h385856 ; + assign _theResult___exp__h405058 = + sfd__h404634[24] ? + ((_theResult___fst_exp__h404542 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431576) : - ((_theResult___fst_exp__h404543 == 8'd0 && - sfd__h404635[24:23] == 2'b01) ? + din_inc___2_exp__h431575) : + ((_theResult___fst_exp__h404542 == 8'd0 && + sfd__h404634[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h404543) ; - assign _theResult___exp__h413641 = - sfd__h413217[24] ? - ((_theResult___fst_exp__h413199 == 8'd254) ? + _theResult___fst_exp__h404542) ; + assign _theResult___exp__h413640 = + sfd__h413216[24] ? + ((_theResult___fst_exp__h413198 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431600) : - ((_theResult___fst_exp__h413199 == 8'd0 && - sfd__h413217[24:23] == 2'b01) ? + din_inc___2_exp__h431599) : + ((_theResult___fst_exp__h413198 == 8'd0 && + sfd__h413216[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h413199) ; - assign _theResult___exp__h422825 = - sfd__h422401[24] ? - ((_theResult___fst_exp__h422309 == 8'd254) ? + _theResult___fst_exp__h413198) ; + assign _theResult___exp__h422824 = + sfd__h422400[24] ? + ((_theResult___fst_exp__h422308 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431630) : - ((_theResult___fst_exp__h422309 == 8'd0 && - sfd__h422401[24:23] == 2'b01) ? + din_inc___2_exp__h431629) : + ((_theResult___fst_exp__h422308 == 8'd0 && + sfd__h422400[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h422309) ; - assign _theResult___exp__h431461 = - sfd__h431013[24] ? - ((_theResult___fst_exp__h430994 == 8'd254) ? + _theResult___fst_exp__h422308) ; + assign _theResult___exp__h431460 = + sfd__h431012[24] ? + ((_theResult___fst_exp__h430993 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431654) : - ((_theResult___fst_exp__h430994 == 8'd0 && - sfd__h431013[24:23] == 2'b01) ? + din_inc___2_exp__h431653) : + ((_theResult___fst_exp__h430993 == 8'd0 && + sfd__h431012[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h430994) ; - assign _theResult___exp__h431563 = + _theResult___fst_exp__h430993) ; + assign _theResult___exp__h431562 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431554 ; - assign _theResult___exp__h450754 = - sfd__h450330[24] ? - ((_theResult___fst_exp__h450238 == 8'd254) ? + _theResult___fst_exp__h431553 ; + assign _theResult___exp__h450753 = + sfd__h450329[24] ? + ((_theResult___fst_exp__h450237 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477271) : - ((_theResult___fst_exp__h450238 == 8'd0 && - sfd__h450330[24:23] == 2'b01) ? + din_inc___2_exp__h477270) : + ((_theResult___fst_exp__h450237 == 8'd0 && + sfd__h450329[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h450238) ; - assign _theResult___exp__h459336 = - sfd__h458912[24] ? - ((_theResult___fst_exp__h458894 == 8'd254) ? + _theResult___fst_exp__h450237) ; + assign _theResult___exp__h459335 = + sfd__h458911[24] ? + ((_theResult___fst_exp__h458893 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477295) : - ((_theResult___fst_exp__h458894 == 8'd0 && - sfd__h458912[24:23] == 2'b01) ? + din_inc___2_exp__h477294) : + ((_theResult___fst_exp__h458893 == 8'd0 && + sfd__h458911[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h458894) ; - assign _theResult___exp__h468520 = - sfd__h468096[24] ? - ((_theResult___fst_exp__h468004 == 8'd254) ? + _theResult___fst_exp__h458893) ; + assign _theResult___exp__h468519 = + sfd__h468095[24] ? + ((_theResult___fst_exp__h468003 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477325) : - ((_theResult___fst_exp__h468004 == 8'd0 && - sfd__h468096[24:23] == 2'b01) ? + din_inc___2_exp__h477324) : + ((_theResult___fst_exp__h468003 == 8'd0 && + sfd__h468095[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h468004) ; - assign _theResult___exp__h477156 = - sfd__h476708[24] ? - ((_theResult___fst_exp__h476689 == 8'd254) ? + _theResult___fst_exp__h468003) ; + assign _theResult___exp__h477155 = + sfd__h476707[24] ? + ((_theResult___fst_exp__h476688 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477349) : - ((_theResult___fst_exp__h476689 == 8'd0 && - sfd__h476708[24:23] == 2'b01) ? + din_inc___2_exp__h477348) : + ((_theResult___fst_exp__h476688 == 8'd0 && + sfd__h476707[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h476689) ; - assign _theResult___exp__h477258 = + _theResult___fst_exp__h476688) ; + assign _theResult___exp__h477257 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477249 ; - assign _theResult___exp__h507569 = - sfd__h506932[53] ? - ((_theResult___fst_exp__h506914 == 11'd2046) ? + _theResult___fst_exp__h477248 ; + assign _theResult___exp__h507568 = + sfd__h506931[53] ? + ((_theResult___fst_exp__h506913 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h526164) : - ((_theResult___fst_exp__h506914 == 11'd0 && - sfd__h506932[53:52] == 2'b01) ? + din_inc___2_exp__h526163) : + ((_theResult___fst_exp__h506913 == 11'd0 && + sfd__h506931[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h506914) ; - assign _theResult___exp__h517220 = - sfd__h516583[53] ? - ((_theResult___fst_exp__h516491 == 11'd2046) ? + _theResult___fst_exp__h506913) ; + assign _theResult___exp__h517219 = + sfd__h516582[53] ? + ((_theResult___fst_exp__h516490 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h526199) : - ((_theResult___fst_exp__h516491 == 11'd0 && - sfd__h516583[53:52] == 2'b01) ? + din_inc___2_exp__h526198) : + ((_theResult___fst_exp__h516490 == 11'd0 && + sfd__h516582[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h516491) ; - assign _theResult___exp__h526004 = - sfd__h525343[53] ? - ((_theResult___fst_exp__h525324 == 11'd2046) ? + _theResult___fst_exp__h516490) ; + assign _theResult___exp__h526003 = + sfd__h525342[53] ? + ((_theResult___fst_exp__h525323 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h526225) : - ((_theResult___fst_exp__h525324 == 11'd0 && - sfd__h525343[53:52] == 2'b01) ? + din_inc___2_exp__h526224) : + ((_theResult___fst_exp__h525323 == 11'd0 && + sfd__h525342[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h525324) ; - assign _theResult___exp__h546422 = - sfd__h545785[53] ? - ((_theResult___fst_exp__h545767 == 11'd2046) ? + _theResult___fst_exp__h525323) ; + assign _theResult___exp__h546421 = + sfd__h545784[53] ? + ((_theResult___fst_exp__h545766 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h565017) : - ((_theResult___fst_exp__h545767 == 11'd0 && - sfd__h545785[53:52] == 2'b01) ? + din_inc___2_exp__h565016) : + ((_theResult___fst_exp__h545766 == 11'd0 && + sfd__h545784[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h545767) ; - assign _theResult___exp__h556073 = - sfd__h555436[53] ? - ((_theResult___fst_exp__h555344 == 11'd2046) ? + _theResult___fst_exp__h545766) ; + assign _theResult___exp__h556072 = + sfd__h555435[53] ? + ((_theResult___fst_exp__h555343 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h565052) : - ((_theResult___fst_exp__h555344 == 11'd0 && - sfd__h555436[53:52] == 2'b01) ? + din_inc___2_exp__h565051) : + ((_theResult___fst_exp__h555343 == 11'd0 && + sfd__h555435[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h555344) ; - assign _theResult___exp__h564857 = - sfd__h564196[53] ? - ((_theResult___fst_exp__h564177 == 11'd2046) ? + _theResult___fst_exp__h555343) ; + assign _theResult___exp__h564856 = + sfd__h564195[53] ? + ((_theResult___fst_exp__h564176 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h565078) : - ((_theResult___fst_exp__h564177 == 11'd0 && - sfd__h564196[53:52] == 2'b01) ? + din_inc___2_exp__h565077) : + ((_theResult___fst_exp__h564176 == 11'd0 && + sfd__h564195[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h564177) ; - assign _theResult___exp__h585726 = - sfd__h585089[53] ? - ((_theResult___fst_exp__h585071 == 11'd2046) ? + _theResult___fst_exp__h564176) ; + assign _theResult___exp__h585725 = + sfd__h585088[53] ? + ((_theResult___fst_exp__h585070 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h604321) : - ((_theResult___fst_exp__h585071 == 11'd0 && - sfd__h585089[53:52] == 2'b01) ? + din_inc___2_exp__h604320) : + ((_theResult___fst_exp__h585070 == 11'd0 && + sfd__h585088[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h585071) ; - assign _theResult___exp__h595377 = - sfd__h594740[53] ? - ((_theResult___fst_exp__h594648 == 11'd2046) ? + _theResult___fst_exp__h585070) ; + assign _theResult___exp__h595376 = + sfd__h594739[53] ? + ((_theResult___fst_exp__h594647 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h604356) : - ((_theResult___fst_exp__h594648 == 11'd0 && - sfd__h594740[53:52] == 2'b01) ? + din_inc___2_exp__h604355) : + ((_theResult___fst_exp__h594647 == 11'd0 && + sfd__h594739[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h594648) ; - assign _theResult___exp__h604161 = - sfd__h603500[53] ? - ((_theResult___fst_exp__h603481 == 11'd2046) ? + _theResult___fst_exp__h594647) ; + assign _theResult___exp__h604160 = + sfd__h603499[53] ? + ((_theResult___fst_exp__h603480 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h604382) : - ((_theResult___fst_exp__h603481 == 11'd0 && - sfd__h603500[53:52] == 2'b01) ? + din_inc___2_exp__h604381) : + ((_theResult___fst_exp__h603480 == 11'd0 && + sfd__h603499[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h603481) ; - assign _theResult___fst__h608920 = - a__h608372[63] ? a___1__h608925 : a__h608372 ; - assign _theResult___fst_exp__h358846 = - _theResult____h350735[56] ? + _theResult___fst_exp__h603480) ; + assign _theResult___fst__h608919 = + a__h608371[63] ? a___1__h608924 : a__h608371 ; + assign _theResult___fst_exp__h358845 = + _theResult____h350734[56] ? 8'd2 : - _theResult___fst_exp__h358920 ; - assign _theResult___fst_exp__h358911 = + _theResult___fst_exp__h358919 ; + assign _theResult___fst_exp__h358910 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 } ; - assign _theResult___fst_exp__h358917 = - (!_theResult____h350735[56] && !_theResult____h350735[55] && - !_theResult____h350735[54] && - !_theResult____h350735[53] && - !_theResult____h350735[52] && - !_theResult____h350735[51] && - !_theResult____h350735[50] && - !_theResult____h350735[49] && - !_theResult____h350735[48] && - !_theResult____h350735[47] && - !_theResult____h350735[46] && - !_theResult____h350735[45] && - !_theResult____h350735[44] && - !_theResult____h350735[43] && - !_theResult____h350735[42] && - !_theResult____h350735[41] && - !_theResult____h350735[40] && - !_theResult____h350735[39] && - !_theResult____h350735[38] && - !_theResult____h350735[37] && - !_theResult____h350735[36] && - !_theResult____h350735[35] && - !_theResult____h350735[34] && - !_theResult____h350735[33] && - !_theResult____h350735[32] && - !_theResult____h350735[31] && - !_theResult____h350735[30] && - !_theResult____h350735[29] && - !_theResult____h350735[28] && - !_theResult____h350735[27] && - !_theResult____h350735[26] && - !_theResult____h350735[25] && - !_theResult____h350735[24] && - !_theResult____h350735[23] && - !_theResult____h350735[22] && - !_theResult____h350735[21] && - !_theResult____h350735[20] && - !_theResult____h350735[19] && - !_theResult____h350735[18] && - !_theResult____h350735[17] && - !_theResult____h350735[16] && - !_theResult____h350735[15] && - !_theResult____h350735[14] && - !_theResult____h350735[13] && - !_theResult____h350735[12] && - !_theResult____h350735[11] && - !_theResult____h350735[10] && - !_theResult____h350735[9] && - !_theResult____h350735[8] && - !_theResult____h350735[7] && - !_theResult____h350735[6] && - !_theResult____h350735[5] && - !_theResult____h350735[4] && - !_theResult____h350735[3] && - !_theResult____h350735[2] && - !_theResult____h350735[1] && - !_theResult____h350735[0] || + assign _theResult___fst_exp__h358916 = + (!_theResult____h350734[56] && !_theResult____h350734[55] && + !_theResult____h350734[54] && + !_theResult____h350734[53] && + !_theResult____h350734[52] && + !_theResult____h350734[51] && + !_theResult____h350734[50] && + !_theResult____h350734[49] && + !_theResult____h350734[48] && + !_theResult____h350734[47] && + !_theResult____h350734[46] && + !_theResult____h350734[45] && + !_theResult____h350734[44] && + !_theResult____h350734[43] && + !_theResult____h350734[42] && + !_theResult____h350734[41] && + !_theResult____h350734[40] && + !_theResult____h350734[39] && + !_theResult____h350734[38] && + !_theResult____h350734[37] && + !_theResult____h350734[36] && + !_theResult____h350734[35] && + !_theResult____h350734[34] && + !_theResult____h350734[33] && + !_theResult____h350734[32] && + !_theResult____h350734[31] && + !_theResult____h350734[30] && + !_theResult____h350734[29] && + !_theResult____h350734[28] && + !_theResult____h350734[27] && + !_theResult____h350734[26] && + !_theResult____h350734[25] && + !_theResult____h350734[24] && + !_theResult____h350734[23] && + !_theResult____h350734[22] && + !_theResult____h350734[21] && + !_theResult____h350734[20] && + !_theResult____h350734[19] && + !_theResult____h350734[18] && + !_theResult____h350734[17] && + !_theResult____h350734[16] && + !_theResult____h350734[15] && + !_theResult____h350734[14] && + !_theResult____h350734[13] && + !_theResult____h350734[12] && + !_theResult____h350734[11] && + !_theResult____h350734[10] && + !_theResult____h350734[9] && + !_theResult____h350734[8] && + !_theResult____h350734[7] && + !_theResult____h350734[6] && + !_theResult____h350734[5] && + !_theResult____h350734[4] && + !_theResult____h350734[3] && + !_theResult____h350734[2] && + !_theResult____h350734[1] && + !_theResult____h350734[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345) ? 8'd0 : - _theResult___fst_exp__h358911 ; - assign _theResult___fst_exp__h358920 = - (!_theResult____h350735[56] && _theResult____h350735[55]) ? + _theResult___fst_exp__h358910 ; + assign _theResult___fst_exp__h358919 = + (!_theResult____h350734[56] && _theResult____h350734[55]) ? 8'd1 : - _theResult___fst_exp__h358917 ; - assign _theResult___fst_exp__h359443 = - (_theResult___fst_exp__h358846 == 8'd255) ? - _theResult___fst_exp__h358846 : - _theResult___fst_exp__h359440 ; - assign _theResult___fst_exp__h367493 = + _theResult___fst_exp__h358916 ; + assign _theResult___fst_exp__h359442 = + (_theResult___fst_exp__h358845 == 8'd255) ? + _theResult___fst_exp__h358845 : + _theResult___fst_exp__h359439 ; + assign _theResult___fst_exp__h367492 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h367499 = + assign _theResult___fst_exp__h367498 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576) ? 8'd0 : - _theResult___fst_exp__h367493 ; - assign _theResult___fst_exp__h367502 = + _theResult___fst_exp__h367492 ; + assign _theResult___fst_exp__h367501 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h367499 : + _theResult___fst_exp__h367498 : 8'd129 ; - assign _theResult___fst_exp__h368025 = - (_theResult___fst_exp__h367502 == 8'd255) ? - _theResult___fst_exp__h367502 : - _theResult___fst_exp__h368022 ; - assign _theResult___fst_exp__h376612 = - _theResult____h368374[56] ? + assign _theResult___fst_exp__h368024 = + (_theResult___fst_exp__h367501 == 8'd255) ? + _theResult___fst_exp__h367501 : + _theResult___fst_exp__h368021 ; + assign _theResult___fst_exp__h376611 = + _theResult____h368373[56] ? 8'd2 : - _theResult___fst_exp__h376686 ; - assign _theResult___fst_exp__h376677 = + _theResult___fst_exp__h376685 ; + assign _theResult___fst_exp__h376676 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 } ; - assign _theResult___fst_exp__h376683 = - (!_theResult____h368374[56] && !_theResult____h368374[55] && - !_theResult____h368374[54] && - !_theResult____h368374[53] && - !_theResult____h368374[52] && - !_theResult____h368374[51] && - !_theResult____h368374[50] && - !_theResult____h368374[49] && - !_theResult____h368374[48] && - !_theResult____h368374[47] && - !_theResult____h368374[46] && - !_theResult____h368374[45] && - !_theResult____h368374[44] && - !_theResult____h368374[43] && - !_theResult____h368374[42] && - !_theResult____h368374[41] && - !_theResult____h368374[40] && - !_theResult____h368374[39] && - !_theResult____h368374[38] && - !_theResult____h368374[37] && - !_theResult____h368374[36] && - !_theResult____h368374[35] && - !_theResult____h368374[34] && - !_theResult____h368374[33] && - !_theResult____h368374[32] && - !_theResult____h368374[31] && - !_theResult____h368374[30] && - !_theResult____h368374[29] && - !_theResult____h368374[28] && - !_theResult____h368374[27] && - !_theResult____h368374[26] && - !_theResult____h368374[25] && - !_theResult____h368374[24] && - !_theResult____h368374[23] && - !_theResult____h368374[22] && - !_theResult____h368374[21] && - !_theResult____h368374[20] && - !_theResult____h368374[19] && - !_theResult____h368374[18] && - !_theResult____h368374[17] && - !_theResult____h368374[16] && - !_theResult____h368374[15] && - !_theResult____h368374[14] && - !_theResult____h368374[13] && - !_theResult____h368374[12] && - !_theResult____h368374[11] && - !_theResult____h368374[10] && - !_theResult____h368374[9] && - !_theResult____h368374[8] && - !_theResult____h368374[7] && - !_theResult____h368374[6] && - !_theResult____h368374[5] && - !_theResult____h368374[4] && - !_theResult____h368374[3] && - !_theResult____h368374[2] && - !_theResult____h368374[1] && - !_theResult____h368374[0] || + assign _theResult___fst_exp__h376682 = + (!_theResult____h368373[56] && !_theResult____h368373[55] && + !_theResult____h368373[54] && + !_theResult____h368373[53] && + !_theResult____h368373[52] && + !_theResult____h368373[51] && + !_theResult____h368373[50] && + !_theResult____h368373[49] && + !_theResult____h368373[48] && + !_theResult____h368373[47] && + !_theResult____h368373[46] && + !_theResult____h368373[45] && + !_theResult____h368373[44] && + !_theResult____h368373[43] && + !_theResult____h368373[42] && + !_theResult____h368373[41] && + !_theResult____h368373[40] && + !_theResult____h368373[39] && + !_theResult____h368373[38] && + !_theResult____h368373[37] && + !_theResult____h368373[36] && + !_theResult____h368373[35] && + !_theResult____h368373[34] && + !_theResult____h368373[33] && + !_theResult____h368373[32] && + !_theResult____h368373[31] && + !_theResult____h368373[30] && + !_theResult____h368373[29] && + !_theResult____h368373[28] && + !_theResult____h368373[27] && + !_theResult____h368373[26] && + !_theResult____h368373[25] && + !_theResult____h368373[24] && + !_theResult____h368373[23] && + !_theResult____h368373[22] && + !_theResult____h368373[21] && + !_theResult____h368373[20] && + !_theResult____h368373[19] && + !_theResult____h368373[18] && + !_theResult____h368373[17] && + !_theResult____h368373[16] && + !_theResult____h368373[15] && + !_theResult____h368373[14] && + !_theResult____h368373[13] && + !_theResult____h368373[12] && + !_theResult____h368373[11] && + !_theResult____h368373[10] && + !_theResult____h368373[9] && + !_theResult____h368373[8] && + !_theResult____h368373[7] && + !_theResult____h368373[6] && + !_theResult____h368373[5] && + !_theResult____h368373[4] && + !_theResult____h368373[3] && + !_theResult____h368373[2] && + !_theResult____h368373[1] && + !_theResult____h368373[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896) ? 8'd0 : - _theResult___fst_exp__h376677 ; - assign _theResult___fst_exp__h376686 = - (!_theResult____h368374[56] && _theResult____h368374[55]) ? + _theResult___fst_exp__h376676 ; + assign _theResult___fst_exp__h376685 = + (!_theResult____h368373[56] && _theResult____h368373[55]) ? 8'd1 : - _theResult___fst_exp__h376683 ; - assign _theResult___fst_exp__h377209 = - (_theResult___fst_exp__h376612 == 8'd255) ? - _theResult___fst_exp__h376612 : - _theResult___fst_exp__h377206 ; - assign _theResult___fst_exp__h385249 = + _theResult___fst_exp__h376682 ; + assign _theResult___fst_exp__h377208 = + (_theResult___fst_exp__h376611 == 8'd255) ? + _theResult___fst_exp__h376611 : + _theResult___fst_exp__h377205 ; + assign _theResult___fst_exp__h385248 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ; - assign _theResult___fst_exp__h385288 = + assign _theResult___fst_exp__h385287 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h385294 = + assign _theResult___fst_exp__h385293 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969) ? 8'd0 : - _theResult___fst_exp__h385288 ; - assign _theResult___fst_exp__h385297 = + _theResult___fst_exp__h385287 ; + assign _theResult___fst_exp__h385296 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h385294 : - _theResult___fst_exp__h385249 ; - assign _theResult___fst_exp__h385845 = - (_theResult___fst_exp__h385297 == 8'd255) ? - _theResult___fst_exp__h385297 : - _theResult___fst_exp__h385842 ; - assign _theResult___fst_exp__h385854 = + _theResult___fst_exp__h385293 : + _theResult___fst_exp__h385248 ; + assign _theResult___fst_exp__h385844 = + (_theResult___fst_exp__h385296 == 8'd255) ? + _theResult___fst_exp__h385296 : + _theResult___fst_exp__h385841 ; + assign _theResult___fst_exp__h385853 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_exp__h368028 : - _theResult___fst_exp__h350717) : + _theResult___snd_fst_exp__h368027 : + _theResult___fst_exp__h350716) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_exp__h385848 : - _theResult___fst_exp__h350717) ; - assign _theResult___fst_exp__h385857 = + _theResult___snd_fst_exp__h385847 : + _theResult___fst_exp__h350716) ; + assign _theResult___fst_exp__h385856 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h385854 ; - assign _theResult___fst_exp__h404543 = - _theResult____h396434[56] ? + _theResult___fst_exp__h385853 ; + assign _theResult___fst_exp__h404542 = + _theResult____h396433[56] ? 8'd2 : - _theResult___fst_exp__h404617 ; - assign _theResult___fst_exp__h404608 = + _theResult___fst_exp__h404616 ; + assign _theResult___fst_exp__h404607 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ; - assign _theResult___fst_exp__h404614 = - (!_theResult____h396434[56] && !_theResult____h396434[55] && - !_theResult____h396434[54] && - !_theResult____h396434[53] && - !_theResult____h396434[52] && - !_theResult____h396434[51] && - !_theResult____h396434[50] && - !_theResult____h396434[49] && - !_theResult____h396434[48] && - !_theResult____h396434[47] && - !_theResult____h396434[46] && - !_theResult____h396434[45] && - !_theResult____h396434[44] && - !_theResult____h396434[43] && - !_theResult____h396434[42] && - !_theResult____h396434[41] && - !_theResult____h396434[40] && - !_theResult____h396434[39] && - !_theResult____h396434[38] && - !_theResult____h396434[37] && - !_theResult____h396434[36] && - !_theResult____h396434[35] && - !_theResult____h396434[34] && - !_theResult____h396434[33] && - !_theResult____h396434[32] && - !_theResult____h396434[31] && - !_theResult____h396434[30] && - !_theResult____h396434[29] && - !_theResult____h396434[28] && - !_theResult____h396434[27] && - !_theResult____h396434[26] && - !_theResult____h396434[25] && - !_theResult____h396434[24] && - !_theResult____h396434[23] && - !_theResult____h396434[22] && - !_theResult____h396434[21] && - !_theResult____h396434[20] && - !_theResult____h396434[19] && - !_theResult____h396434[18] && - !_theResult____h396434[17] && - !_theResult____h396434[16] && - !_theResult____h396434[15] && - !_theResult____h396434[14] && - !_theResult____h396434[13] && - !_theResult____h396434[12] && - !_theResult____h396434[11] && - !_theResult____h396434[10] && - !_theResult____h396434[9] && - !_theResult____h396434[8] && - !_theResult____h396434[7] && - !_theResult____h396434[6] && - !_theResult____h396434[5] && - !_theResult____h396434[4] && - !_theResult____h396434[3] && - !_theResult____h396434[2] && - !_theResult____h396434[1] && - !_theResult____h396434[0] || + assign _theResult___fst_exp__h404613 = + (!_theResult____h396433[56] && !_theResult____h396433[55] && + !_theResult____h396433[54] && + !_theResult____h396433[53] && + !_theResult____h396433[52] && + !_theResult____h396433[51] && + !_theResult____h396433[50] && + !_theResult____h396433[49] && + !_theResult____h396433[48] && + !_theResult____h396433[47] && + !_theResult____h396433[46] && + !_theResult____h396433[45] && + !_theResult____h396433[44] && + !_theResult____h396433[43] && + !_theResult____h396433[42] && + !_theResult____h396433[41] && + !_theResult____h396433[40] && + !_theResult____h396433[39] && + !_theResult____h396433[38] && + !_theResult____h396433[37] && + !_theResult____h396433[36] && + !_theResult____h396433[35] && + !_theResult____h396433[34] && + !_theResult____h396433[33] && + !_theResult____h396433[32] && + !_theResult____h396433[31] && + !_theResult____h396433[30] && + !_theResult____h396433[29] && + !_theResult____h396433[28] && + !_theResult____h396433[27] && + !_theResult____h396433[26] && + !_theResult____h396433[25] && + !_theResult____h396433[24] && + !_theResult____h396433[23] && + !_theResult____h396433[22] && + !_theResult____h396433[21] && + !_theResult____h396433[20] && + !_theResult____h396433[19] && + !_theResult____h396433[18] && + !_theResult____h396433[17] && + !_theResult____h396433[16] && + !_theResult____h396433[15] && + !_theResult____h396433[14] && + !_theResult____h396433[13] && + !_theResult____h396433[12] && + !_theResult____h396433[11] && + !_theResult____h396433[10] && + !_theResult____h396433[9] && + !_theResult____h396433[8] && + !_theResult____h396433[7] && + !_theResult____h396433[6] && + !_theResult____h396433[5] && + !_theResult____h396433[4] && + !_theResult____h396433[3] && + !_theResult____h396433[2] && + !_theResult____h396433[1] && + !_theResult____h396433[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737) ? 8'd0 : - _theResult___fst_exp__h404608 ; - assign _theResult___fst_exp__h404617 = - (!_theResult____h396434[56] && _theResult____h396434[55]) ? + _theResult___fst_exp__h404607 ; + assign _theResult___fst_exp__h404616 = + (!_theResult____h396433[56] && _theResult____h396433[55]) ? 8'd1 : - _theResult___fst_exp__h404614 ; - assign _theResult___fst_exp__h405140 = - (_theResult___fst_exp__h404543 == 8'd255) ? - _theResult___fst_exp__h404543 : - _theResult___fst_exp__h405137 ; - assign _theResult___fst_exp__h413190 = + _theResult___fst_exp__h404613 ; + assign _theResult___fst_exp__h405139 = + (_theResult___fst_exp__h404542 == 8'd255) ? + _theResult___fst_exp__h404542 : + _theResult___fst_exp__h405136 ; + assign _theResult___fst_exp__h413189 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h413196 = + assign _theResult___fst_exp__h413195 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968) ? 8'd0 : - _theResult___fst_exp__h413190 ; - assign _theResult___fst_exp__h413199 = + _theResult___fst_exp__h413189 ; + assign _theResult___fst_exp__h413198 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h413196 : + _theResult___fst_exp__h413195 : 8'd129 ; - assign _theResult___fst_exp__h413722 = - (_theResult___fst_exp__h413199 == 8'd255) ? - _theResult___fst_exp__h413199 : - _theResult___fst_exp__h413719 ; - assign _theResult___fst_exp__h422309 = - _theResult____h414071[56] ? + assign _theResult___fst_exp__h413721 = + (_theResult___fst_exp__h413198 == 8'd255) ? + _theResult___fst_exp__h413198 : + _theResult___fst_exp__h413718 ; + assign _theResult___fst_exp__h422308 = + _theResult____h414070[56] ? 8'd2 : - _theResult___fst_exp__h422383 ; - assign _theResult___fst_exp__h422374 = + _theResult___fst_exp__h422382 ; + assign _theResult___fst_exp__h422373 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ; - assign _theResult___fst_exp__h422380 = - (!_theResult____h414071[56] && !_theResult____h414071[55] && - !_theResult____h414071[54] && - !_theResult____h414071[53] && - !_theResult____h414071[52] && - !_theResult____h414071[51] && - !_theResult____h414071[50] && - !_theResult____h414071[49] && - !_theResult____h414071[48] && - !_theResult____h414071[47] && - !_theResult____h414071[46] && - !_theResult____h414071[45] && - !_theResult____h414071[44] && - !_theResult____h414071[43] && - !_theResult____h414071[42] && - !_theResult____h414071[41] && - !_theResult____h414071[40] && - !_theResult____h414071[39] && - !_theResult____h414071[38] && - !_theResult____h414071[37] && - !_theResult____h414071[36] && - !_theResult____h414071[35] && - !_theResult____h414071[34] && - !_theResult____h414071[33] && - !_theResult____h414071[32] && - !_theResult____h414071[31] && - !_theResult____h414071[30] && - !_theResult____h414071[29] && - !_theResult____h414071[28] && - !_theResult____h414071[27] && - !_theResult____h414071[26] && - !_theResult____h414071[25] && - !_theResult____h414071[24] && - !_theResult____h414071[23] && - !_theResult____h414071[22] && - !_theResult____h414071[21] && - !_theResult____h414071[20] && - !_theResult____h414071[19] && - !_theResult____h414071[18] && - !_theResult____h414071[17] && - !_theResult____h414071[16] && - !_theResult____h414071[15] && - !_theResult____h414071[14] && - !_theResult____h414071[13] && - !_theResult____h414071[12] && - !_theResult____h414071[11] && - !_theResult____h414071[10] && - !_theResult____h414071[9] && - !_theResult____h414071[8] && - !_theResult____h414071[7] && - !_theResult____h414071[6] && - !_theResult____h414071[5] && - !_theResult____h414071[4] && - !_theResult____h414071[3] && - !_theResult____h414071[2] && - !_theResult____h414071[1] && - !_theResult____h414071[0] || + assign _theResult___fst_exp__h422379 = + (!_theResult____h414070[56] && !_theResult____h414070[55] && + !_theResult____h414070[54] && + !_theResult____h414070[53] && + !_theResult____h414070[52] && + !_theResult____h414070[51] && + !_theResult____h414070[50] && + !_theResult____h414070[49] && + !_theResult____h414070[48] && + !_theResult____h414070[47] && + !_theResult____h414070[46] && + !_theResult____h414070[45] && + !_theResult____h414070[44] && + !_theResult____h414070[43] && + !_theResult____h414070[42] && + !_theResult____h414070[41] && + !_theResult____h414070[40] && + !_theResult____h414070[39] && + !_theResult____h414070[38] && + !_theResult____h414070[37] && + !_theResult____h414070[36] && + !_theResult____h414070[35] && + !_theResult____h414070[34] && + !_theResult____h414070[33] && + !_theResult____h414070[32] && + !_theResult____h414070[31] && + !_theResult____h414070[30] && + !_theResult____h414070[29] && + !_theResult____h414070[28] && + !_theResult____h414070[27] && + !_theResult____h414070[26] && + !_theResult____h414070[25] && + !_theResult____h414070[24] && + !_theResult____h414070[23] && + !_theResult____h414070[22] && + !_theResult____h414070[21] && + !_theResult____h414070[20] && + !_theResult____h414070[19] && + !_theResult____h414070[18] && + !_theResult____h414070[17] && + !_theResult____h414070[16] && + !_theResult____h414070[15] && + !_theResult____h414070[14] && + !_theResult____h414070[13] && + !_theResult____h414070[12] && + !_theResult____h414070[11] && + !_theResult____h414070[10] && + !_theResult____h414070[9] && + !_theResult____h414070[8] && + !_theResult____h414070[7] && + !_theResult____h414070[6] && + !_theResult____h414070[5] && + !_theResult____h414070[4] && + !_theResult____h414070[3] && + !_theResult____h414070[2] && + !_theResult____h414070[1] && + !_theResult____h414070[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288) ? 8'd0 : - _theResult___fst_exp__h422374 ; - assign _theResult___fst_exp__h422383 = - (!_theResult____h414071[56] && _theResult____h414071[55]) ? + _theResult___fst_exp__h422373 ; + assign _theResult___fst_exp__h422382 = + (!_theResult____h414070[56] && _theResult____h414070[55]) ? 8'd1 : - _theResult___fst_exp__h422380 ; - assign _theResult___fst_exp__h422906 = - (_theResult___fst_exp__h422309 == 8'd255) ? - _theResult___fst_exp__h422309 : - _theResult___fst_exp__h422903 ; - assign _theResult___fst_exp__h430946 = + _theResult___fst_exp__h422379 ; + assign _theResult___fst_exp__h422905 = + (_theResult___fst_exp__h422308 == 8'd255) ? + _theResult___fst_exp__h422308 : + _theResult___fst_exp__h422902 ; + assign _theResult___fst_exp__h430945 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ; - assign _theResult___fst_exp__h430985 = + assign _theResult___fst_exp__h430984 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h430991 = + assign _theResult___fst_exp__h430990 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361) ? 8'd0 : - _theResult___fst_exp__h430985 ; - assign _theResult___fst_exp__h430994 = + _theResult___fst_exp__h430984 ; + assign _theResult___fst_exp__h430993 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h430991 : - _theResult___fst_exp__h430946 ; - assign _theResult___fst_exp__h431542 = - (_theResult___fst_exp__h430994 == 8'd255) ? - _theResult___fst_exp__h430994 : - _theResult___fst_exp__h431539 ; - assign _theResult___fst_exp__h431551 = + _theResult___fst_exp__h430990 : + _theResult___fst_exp__h430945 ; + assign _theResult___fst_exp__h431541 = + (_theResult___fst_exp__h430993 == 8'd255) ? + _theResult___fst_exp__h430993 : + _theResult___fst_exp__h431538 ; + assign _theResult___fst_exp__h431550 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_exp__h413725 : - _theResult___fst_exp__h396416) : + _theResult___snd_fst_exp__h413724 : + _theResult___fst_exp__h396415) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_exp__h431545 : - _theResult___fst_exp__h396416) ; - assign _theResult___fst_exp__h431554 = + _theResult___snd_fst_exp__h431544 : + _theResult___fst_exp__h396415) ; + assign _theResult___fst_exp__h431553 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h431551 ; - assign _theResult___fst_exp__h450238 = - _theResult____h442129[56] ? + _theResult___fst_exp__h431550 ; + assign _theResult___fst_exp__h450237 = + _theResult____h442128[56] ? 8'd2 : - _theResult___fst_exp__h450312 ; - assign _theResult___fst_exp__h450303 = + _theResult___fst_exp__h450311 ; + assign _theResult___fst_exp__h450302 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ; - assign _theResult___fst_exp__h450309 = - (!_theResult____h442129[56] && !_theResult____h442129[55] && - !_theResult____h442129[54] && - !_theResult____h442129[53] && - !_theResult____h442129[52] && - !_theResult____h442129[51] && - !_theResult____h442129[50] && - !_theResult____h442129[49] && - !_theResult____h442129[48] && - !_theResult____h442129[47] && - !_theResult____h442129[46] && - !_theResult____h442129[45] && - !_theResult____h442129[44] && - !_theResult____h442129[43] && - !_theResult____h442129[42] && - !_theResult____h442129[41] && - !_theResult____h442129[40] && - !_theResult____h442129[39] && - !_theResult____h442129[38] && - !_theResult____h442129[37] && - !_theResult____h442129[36] && - !_theResult____h442129[35] && - !_theResult____h442129[34] && - !_theResult____h442129[33] && - !_theResult____h442129[32] && - !_theResult____h442129[31] && - !_theResult____h442129[30] && - !_theResult____h442129[29] && - !_theResult____h442129[28] && - !_theResult____h442129[27] && - !_theResult____h442129[26] && - !_theResult____h442129[25] && - !_theResult____h442129[24] && - !_theResult____h442129[23] && - !_theResult____h442129[22] && - !_theResult____h442129[21] && - !_theResult____h442129[20] && - !_theResult____h442129[19] && - !_theResult____h442129[18] && - !_theResult____h442129[17] && - !_theResult____h442129[16] && - !_theResult____h442129[15] && - !_theResult____h442129[14] && - !_theResult____h442129[13] && - !_theResult____h442129[12] && - !_theResult____h442129[11] && - !_theResult____h442129[10] && - !_theResult____h442129[9] && - !_theResult____h442129[8] && - !_theResult____h442129[7] && - !_theResult____h442129[6] && - !_theResult____h442129[5] && - !_theResult____h442129[4] && - !_theResult____h442129[3] && - !_theResult____h442129[2] && - !_theResult____h442129[1] && - !_theResult____h442129[0] || + assign _theResult___fst_exp__h450308 = + (!_theResult____h442128[56] && !_theResult____h442128[55] && + !_theResult____h442128[54] && + !_theResult____h442128[53] && + !_theResult____h442128[52] && + !_theResult____h442128[51] && + !_theResult____h442128[50] && + !_theResult____h442128[49] && + !_theResult____h442128[48] && + !_theResult____h442128[47] && + !_theResult____h442128[46] && + !_theResult____h442128[45] && + !_theResult____h442128[44] && + !_theResult____h442128[43] && + !_theResult____h442128[42] && + !_theResult____h442128[41] && + !_theResult____h442128[40] && + !_theResult____h442128[39] && + !_theResult____h442128[38] && + !_theResult____h442128[37] && + !_theResult____h442128[36] && + !_theResult____h442128[35] && + !_theResult____h442128[34] && + !_theResult____h442128[33] && + !_theResult____h442128[32] && + !_theResult____h442128[31] && + !_theResult____h442128[30] && + !_theResult____h442128[29] && + !_theResult____h442128[28] && + !_theResult____h442128[27] && + !_theResult____h442128[26] && + !_theResult____h442128[25] && + !_theResult____h442128[24] && + !_theResult____h442128[23] && + !_theResult____h442128[22] && + !_theResult____h442128[21] && + !_theResult____h442128[20] && + !_theResult____h442128[19] && + !_theResult____h442128[18] && + !_theResult____h442128[17] && + !_theResult____h442128[16] && + !_theResult____h442128[15] && + !_theResult____h442128[14] && + !_theResult____h442128[13] && + !_theResult____h442128[12] && + !_theResult____h442128[11] && + !_theResult____h442128[10] && + !_theResult____h442128[9] && + !_theResult____h442128[8] && + !_theResult____h442128[7] && + !_theResult____h442128[6] && + !_theResult____h442128[5] && + !_theResult____h442128[4] && + !_theResult____h442128[3] && + !_theResult____h442128[2] && + !_theResult____h442128[1] && + !_theResult____h442128[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129) ? 8'd0 : - _theResult___fst_exp__h450303 ; - assign _theResult___fst_exp__h450312 = - (!_theResult____h442129[56] && _theResult____h442129[55]) ? + _theResult___fst_exp__h450302 ; + assign _theResult___fst_exp__h450311 = + (!_theResult____h442128[56] && _theResult____h442128[55]) ? 8'd1 : - _theResult___fst_exp__h450309 ; - assign _theResult___fst_exp__h450835 = - (_theResult___fst_exp__h450238 == 8'd255) ? - _theResult___fst_exp__h450238 : - _theResult___fst_exp__h450832 ; - assign _theResult___fst_exp__h458885 = + _theResult___fst_exp__h450308 ; + assign _theResult___fst_exp__h450834 = + (_theResult___fst_exp__h450237 == 8'd255) ? + _theResult___fst_exp__h450237 : + _theResult___fst_exp__h450831 ; + assign _theResult___fst_exp__h458884 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h458891 = + assign _theResult___fst_exp__h458890 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360) ? 8'd0 : - _theResult___fst_exp__h458885 ; - assign _theResult___fst_exp__h458894 = + _theResult___fst_exp__h458884 ; + assign _theResult___fst_exp__h458893 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h458891 : + _theResult___fst_exp__h458890 : 8'd129 ; - assign _theResult___fst_exp__h459417 = - (_theResult___fst_exp__h458894 == 8'd255) ? - _theResult___fst_exp__h458894 : - _theResult___fst_exp__h459414 ; - assign _theResult___fst_exp__h468004 = - _theResult____h459766[56] ? + assign _theResult___fst_exp__h459416 = + (_theResult___fst_exp__h458893 == 8'd255) ? + _theResult___fst_exp__h458893 : + _theResult___fst_exp__h459413 ; + assign _theResult___fst_exp__h468003 = + _theResult____h459765[56] ? 8'd2 : - _theResult___fst_exp__h468078 ; - assign _theResult___fst_exp__h468069 = + _theResult___fst_exp__h468077 ; + assign _theResult___fst_exp__h468068 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ; - assign _theResult___fst_exp__h468075 = - (!_theResult____h459766[56] && !_theResult____h459766[55] && - !_theResult____h459766[54] && - !_theResult____h459766[53] && - !_theResult____h459766[52] && - !_theResult____h459766[51] && - !_theResult____h459766[50] && - !_theResult____h459766[49] && - !_theResult____h459766[48] && - !_theResult____h459766[47] && - !_theResult____h459766[46] && - !_theResult____h459766[45] && - !_theResult____h459766[44] && - !_theResult____h459766[43] && - !_theResult____h459766[42] && - !_theResult____h459766[41] && - !_theResult____h459766[40] && - !_theResult____h459766[39] && - !_theResult____h459766[38] && - !_theResult____h459766[37] && - !_theResult____h459766[36] && - !_theResult____h459766[35] && - !_theResult____h459766[34] && - !_theResult____h459766[33] && - !_theResult____h459766[32] && - !_theResult____h459766[31] && - !_theResult____h459766[30] && - !_theResult____h459766[29] && - !_theResult____h459766[28] && - !_theResult____h459766[27] && - !_theResult____h459766[26] && - !_theResult____h459766[25] && - !_theResult____h459766[24] && - !_theResult____h459766[23] && - !_theResult____h459766[22] && - !_theResult____h459766[21] && - !_theResult____h459766[20] && - !_theResult____h459766[19] && - !_theResult____h459766[18] && - !_theResult____h459766[17] && - !_theResult____h459766[16] && - !_theResult____h459766[15] && - !_theResult____h459766[14] && - !_theResult____h459766[13] && - !_theResult____h459766[12] && - !_theResult____h459766[11] && - !_theResult____h459766[10] && - !_theResult____h459766[9] && - !_theResult____h459766[8] && - !_theResult____h459766[7] && - !_theResult____h459766[6] && - !_theResult____h459766[5] && - !_theResult____h459766[4] && - !_theResult____h459766[3] && - !_theResult____h459766[2] && - !_theResult____h459766[1] && - !_theResult____h459766[0] || + assign _theResult___fst_exp__h468074 = + (!_theResult____h459765[56] && !_theResult____h459765[55] && + !_theResult____h459765[54] && + !_theResult____h459765[53] && + !_theResult____h459765[52] && + !_theResult____h459765[51] && + !_theResult____h459765[50] && + !_theResult____h459765[49] && + !_theResult____h459765[48] && + !_theResult____h459765[47] && + !_theResult____h459765[46] && + !_theResult____h459765[45] && + !_theResult____h459765[44] && + !_theResult____h459765[43] && + !_theResult____h459765[42] && + !_theResult____h459765[41] && + !_theResult____h459765[40] && + !_theResult____h459765[39] && + !_theResult____h459765[38] && + !_theResult____h459765[37] && + !_theResult____h459765[36] && + !_theResult____h459765[35] && + !_theResult____h459765[34] && + !_theResult____h459765[33] && + !_theResult____h459765[32] && + !_theResult____h459765[31] && + !_theResult____h459765[30] && + !_theResult____h459765[29] && + !_theResult____h459765[28] && + !_theResult____h459765[27] && + !_theResult____h459765[26] && + !_theResult____h459765[25] && + !_theResult____h459765[24] && + !_theResult____h459765[23] && + !_theResult____h459765[22] && + !_theResult____h459765[21] && + !_theResult____h459765[20] && + !_theResult____h459765[19] && + !_theResult____h459765[18] && + !_theResult____h459765[17] && + !_theResult____h459765[16] && + !_theResult____h459765[15] && + !_theResult____h459765[14] && + !_theResult____h459765[13] && + !_theResult____h459765[12] && + !_theResult____h459765[11] && + !_theResult____h459765[10] && + !_theResult____h459765[9] && + !_theResult____h459765[8] && + !_theResult____h459765[7] && + !_theResult____h459765[6] && + !_theResult____h459765[5] && + !_theResult____h459765[4] && + !_theResult____h459765[3] && + !_theResult____h459765[2] && + !_theResult____h459765[1] && + !_theResult____h459765[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680) ? 8'd0 : - _theResult___fst_exp__h468069 ; - assign _theResult___fst_exp__h468078 = - (!_theResult____h459766[56] && _theResult____h459766[55]) ? + _theResult___fst_exp__h468068 ; + assign _theResult___fst_exp__h468077 = + (!_theResult____h459765[56] && _theResult____h459765[55]) ? 8'd1 : - _theResult___fst_exp__h468075 ; - assign _theResult___fst_exp__h468601 = - (_theResult___fst_exp__h468004 == 8'd255) ? - _theResult___fst_exp__h468004 : - _theResult___fst_exp__h468598 ; - assign _theResult___fst_exp__h476641 = + _theResult___fst_exp__h468074 ; + assign _theResult___fst_exp__h468600 = + (_theResult___fst_exp__h468003 == 8'd255) ? + _theResult___fst_exp__h468003 : + _theResult___fst_exp__h468597 ; + assign _theResult___fst_exp__h476640 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ; - assign _theResult___fst_exp__h476680 = + assign _theResult___fst_exp__h476679 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h476686 = + assign _theResult___fst_exp__h476685 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753) ? 8'd0 : - _theResult___fst_exp__h476680 ; - assign _theResult___fst_exp__h476689 = + _theResult___fst_exp__h476679 ; + assign _theResult___fst_exp__h476688 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h476686 : - _theResult___fst_exp__h476641 ; - assign _theResult___fst_exp__h477237 = - (_theResult___fst_exp__h476689 == 8'd255) ? - _theResult___fst_exp__h476689 : - _theResult___fst_exp__h477234 ; - assign _theResult___fst_exp__h477246 = + _theResult___fst_exp__h476685 : + _theResult___fst_exp__h476640 ; + assign _theResult___fst_exp__h477236 = + (_theResult___fst_exp__h476688 == 8'd255) ? + _theResult___fst_exp__h476688 : + _theResult___fst_exp__h477233 ; + assign _theResult___fst_exp__h477245 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_exp__h459420 : - _theResult___fst_exp__h442111) : + _theResult___snd_fst_exp__h459419 : + _theResult___fst_exp__h442110) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_exp__h477240 : - _theResult___fst_exp__h442111) ; - assign _theResult___fst_exp__h477249 = + _theResult___snd_fst_exp__h477239 : + _theResult___fst_exp__h442110) ; + assign _theResult___fst_exp__h477248 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h477246 ; - assign _theResult___fst_exp__h491841 = + _theResult___fst_exp__h477245 ; + assign _theResult___fst_exp__h491840 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_exp__h506905 = + assign _theResult___fst_exp__h506904 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h506911 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___fst_exp__h506910 = + (f1_exp__h487525 == 8'd0 && !f1_sfd__h487526[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696) ? 11'd0 : - _theResult___fst_exp__h506905 ; - assign _theResult___fst_exp__h506914 = - (f1_exp__h487526 == 8'd0) ? - _theResult___fst_exp__h506911 : + _theResult___fst_exp__h506904 ; + assign _theResult___fst_exp__h506913 = + (f1_exp__h487525 == 8'd0) ? + _theResult___fst_exp__h506910 : 11'd897 ; - assign _theResult___fst_exp__h507669 = + assign _theResult___fst_exp__h507668 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 : + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 ; - assign _theResult___fst_exp__h507672 = - (_theResult___fst_exp__h506914 == 11'd2047) ? - _theResult___fst_exp__h506914 : - _theResult___fst_exp__h507669 ; - assign _theResult___fst_exp__h516491 = - _theResult____h508255[56] ? + assign _theResult___fst_exp__h507671 = + (_theResult___fst_exp__h506913 == 11'd2047) ? + _theResult___fst_exp__h506913 : + _theResult___fst_exp__h507668 ; + assign _theResult___fst_exp__h516490 = + _theResult____h508254[56] ? 11'd2 : - _theResult___fst_exp__h516565 ; - assign _theResult___fst_exp__h516556 = + _theResult___fst_exp__h516564 ; + assign _theResult___fst_exp__h516555 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ; - assign _theResult___fst_exp__h516562 = - (!_theResult____h508255[56] && !_theResult____h508255[55] && - !_theResult____h508255[54] && - !_theResult____h508255[53] && - !_theResult____h508255[52] && - !_theResult____h508255[51] && - !_theResult____h508255[50] && - !_theResult____h508255[49] && - !_theResult____h508255[48] && - !_theResult____h508255[47] && - !_theResult____h508255[46] && - !_theResult____h508255[45] && - !_theResult____h508255[44] && - !_theResult____h508255[43] && - !_theResult____h508255[42] && - !_theResult____h508255[41] && - !_theResult____h508255[40] && - !_theResult____h508255[39] && - !_theResult____h508255[38] && - !_theResult____h508255[37] && - !_theResult____h508255[36] && - !_theResult____h508255[35] && - !_theResult____h508255[34] && - !_theResult____h508255[33] && - !_theResult____h508255[32] && - !_theResult____h508255[31] && - !_theResult____h508255[30] && - !_theResult____h508255[29] && - !_theResult____h508255[28] && - !_theResult____h508255[27] && - !_theResult____h508255[26] && - !_theResult____h508255[25] && - !_theResult____h508255[24] && - !_theResult____h508255[23] && - !_theResult____h508255[22] && - !_theResult____h508255[21] && - !_theResult____h508255[20] && - !_theResult____h508255[19] && - !_theResult____h508255[18] && - !_theResult____h508255[17] && - !_theResult____h508255[16] && - !_theResult____h508255[15] && - !_theResult____h508255[14] && - !_theResult____h508255[13] && - !_theResult____h508255[12] && - !_theResult____h508255[11] && - !_theResult____h508255[10] && - !_theResult____h508255[9] && - !_theResult____h508255[8] && - !_theResult____h508255[7] && - !_theResult____h508255[6] && - !_theResult____h508255[5] && - !_theResult____h508255[4] && - !_theResult____h508255[3] && - !_theResult____h508255[2] && - !_theResult____h508255[1] && - !_theResult____h508255[0] || + assign _theResult___fst_exp__h516561 = + (!_theResult____h508254[56] && !_theResult____h508254[55] && + !_theResult____h508254[54] && + !_theResult____h508254[53] && + !_theResult____h508254[52] && + !_theResult____h508254[51] && + !_theResult____h508254[50] && + !_theResult____h508254[49] && + !_theResult____h508254[48] && + !_theResult____h508254[47] && + !_theResult____h508254[46] && + !_theResult____h508254[45] && + !_theResult____h508254[44] && + !_theResult____h508254[43] && + !_theResult____h508254[42] && + !_theResult____h508254[41] && + !_theResult____h508254[40] && + !_theResult____h508254[39] && + !_theResult____h508254[38] && + !_theResult____h508254[37] && + !_theResult____h508254[36] && + !_theResult____h508254[35] && + !_theResult____h508254[34] && + !_theResult____h508254[33] && + !_theResult____h508254[32] && + !_theResult____h508254[31] && + !_theResult____h508254[30] && + !_theResult____h508254[29] && + !_theResult____h508254[28] && + !_theResult____h508254[27] && + !_theResult____h508254[26] && + !_theResult____h508254[25] && + !_theResult____h508254[24] && + !_theResult____h508254[23] && + !_theResult____h508254[22] && + !_theResult____h508254[21] && + !_theResult____h508254[20] && + !_theResult____h508254[19] && + !_theResult____h508254[18] && + !_theResult____h508254[17] && + !_theResult____h508254[16] && + !_theResult____h508254[15] && + !_theResult____h508254[14] && + !_theResult____h508254[13] && + !_theResult____h508254[12] && + !_theResult____h508254[11] && + !_theResult____h508254[10] && + !_theResult____h508254[9] && + !_theResult____h508254[8] && + !_theResult____h508254[7] && + !_theResult____h508254[6] && + !_theResult____h508254[5] && + !_theResult____h508254[4] && + !_theResult____h508254[3] && + !_theResult____h508254[2] && + !_theResult____h508254[1] && + !_theResult____h508254[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008) ? 11'd0 : - _theResult___fst_exp__h516556 ; - assign _theResult___fst_exp__h516565 = - (!_theResult____h508255[56] && _theResult____h508255[55]) ? + _theResult___fst_exp__h516555 ; + assign _theResult___fst_exp__h516564 = + (!_theResult____h508254[56] && _theResult____h508254[55]) ? 11'd1 : - _theResult___fst_exp__h516562 ; - assign _theResult___fst_exp__h517320 = + _theResult___fst_exp__h516561 ; + assign _theResult___fst_exp__h517319 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 : + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 ; - assign _theResult___fst_exp__h517323 = - (_theResult___fst_exp__h516491 == 11'd2047) ? - _theResult___fst_exp__h516491 : - _theResult___fst_exp__h517320 ; - assign _theResult___fst_exp__h525276 = + assign _theResult___fst_exp__h517322 = + (_theResult___fst_exp__h516490 == 11'd2047) ? + _theResult___fst_exp__h516490 : + _theResult___fst_exp__h517319 ; + assign _theResult___fst_exp__h525275 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] ; - assign _theResult___fst_exp__h525315 = + assign _theResult___fst_exp__h525314 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h525321 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___fst_exp__h525320 = + (f1_exp__h487525 == 8'd0 && !f1_sfd__h487526[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058) ? 11'd0 : - _theResult___fst_exp__h525315 ; - assign _theResult___fst_exp__h525324 = - (f1_exp__h487526 == 8'd0) ? - _theResult___fst_exp__h525321 : - _theResult___fst_exp__h525276 ; - assign _theResult___fst_exp__h526104 = + _theResult___fst_exp__h525314 ; + assign _theResult___fst_exp__h525323 = + (f1_exp__h487525 == 8'd0) ? + _theResult___fst_exp__h525320 : + _theResult___fst_exp__h525275 ; + assign _theResult___fst_exp__h526103 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 : + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 ; - assign _theResult___fst_exp__h526107 = - (_theResult___fst_exp__h525324 == 11'd2047) ? - _theResult___fst_exp__h525324 : - _theResult___fst_exp__h526104 ; - assign _theResult___fst_exp__h526116 = - (f1_exp__h487526 == 8'd0) ? + assign _theResult___fst_exp__h526106 = + (_theResult___fst_exp__h525323 == 11'd2047) ? + _theResult___fst_exp__h525323 : + _theResult___fst_exp__h526103 ; + assign _theResult___fst_exp__h526115 = + (f1_exp__h487525 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_exp__h507675 : - _theResult___fst_exp__h491841) : + _theResult___snd_fst_exp__h507674 : + _theResult___fst_exp__h491840) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_exp__h526110 : - _theResult___fst_exp__h491841) ; - assign _theResult___fst_exp__h526119 = - (f1_exp__h487526 == 8'd0 && f1_sfd__h487527 == 23'd0) ? + _theResult___snd_fst_exp__h526109 : + _theResult___fst_exp__h491840) ; + assign _theResult___fst_exp__h526118 = + (f1_exp__h487525 == 8'd0 && f1_sfd__h487526 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h526116 ; - assign _theResult___fst_exp__h530694 = + _theResult___fst_exp__h526115 ; + assign _theResult___fst_exp__h530693 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_exp__h545758 = + assign _theResult___fst_exp__h545757 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h545764 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___fst_exp__h545763 = + (f2_exp__h526519 == 8'd0 && !f2_sfd__h526520[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196) ? 11'd0 : - _theResult___fst_exp__h545758 ; - assign _theResult___fst_exp__h545767 = - (f2_exp__h526520 == 8'd0) ? - _theResult___fst_exp__h545764 : + _theResult___fst_exp__h545757 ; + assign _theResult___fst_exp__h545766 = + (f2_exp__h526519 == 8'd0) ? + _theResult___fst_exp__h545763 : 11'd897 ; - assign _theResult___fst_exp__h546522 = + assign _theResult___fst_exp__h546521 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 : + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 ; - assign _theResult___fst_exp__h546525 = - (_theResult___fst_exp__h545767 == 11'd2047) ? - _theResult___fst_exp__h545767 : - _theResult___fst_exp__h546522 ; - assign _theResult___fst_exp__h555344 = - _theResult____h547108[56] ? + assign _theResult___fst_exp__h546524 = + (_theResult___fst_exp__h545766 == 11'd2047) ? + _theResult___fst_exp__h545766 : + _theResult___fst_exp__h546521 ; + assign _theResult___fst_exp__h555343 = + _theResult____h547107[56] ? 11'd2 : - _theResult___fst_exp__h555418 ; - assign _theResult___fst_exp__h555409 = + _theResult___fst_exp__h555417 ; + assign _theResult___fst_exp__h555408 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ; - assign _theResult___fst_exp__h555415 = - (!_theResult____h547108[56] && !_theResult____h547108[55] && - !_theResult____h547108[54] && - !_theResult____h547108[53] && - !_theResult____h547108[52] && - !_theResult____h547108[51] && - !_theResult____h547108[50] && - !_theResult____h547108[49] && - !_theResult____h547108[48] && - !_theResult____h547108[47] && - !_theResult____h547108[46] && - !_theResult____h547108[45] && - !_theResult____h547108[44] && - !_theResult____h547108[43] && - !_theResult____h547108[42] && - !_theResult____h547108[41] && - !_theResult____h547108[40] && - !_theResult____h547108[39] && - !_theResult____h547108[38] && - !_theResult____h547108[37] && - !_theResult____h547108[36] && - !_theResult____h547108[35] && - !_theResult____h547108[34] && - !_theResult____h547108[33] && - !_theResult____h547108[32] && - !_theResult____h547108[31] && - !_theResult____h547108[30] && - !_theResult____h547108[29] && - !_theResult____h547108[28] && - !_theResult____h547108[27] && - !_theResult____h547108[26] && - !_theResult____h547108[25] && - !_theResult____h547108[24] && - !_theResult____h547108[23] && - !_theResult____h547108[22] && - !_theResult____h547108[21] && - !_theResult____h547108[20] && - !_theResult____h547108[19] && - !_theResult____h547108[18] && - !_theResult____h547108[17] && - !_theResult____h547108[16] && - !_theResult____h547108[15] && - !_theResult____h547108[14] && - !_theResult____h547108[13] && - !_theResult____h547108[12] && - !_theResult____h547108[11] && - !_theResult____h547108[10] && - !_theResult____h547108[9] && - !_theResult____h547108[8] && - !_theResult____h547108[7] && - !_theResult____h547108[6] && - !_theResult____h547108[5] && - !_theResult____h547108[4] && - !_theResult____h547108[3] && - !_theResult____h547108[2] && - !_theResult____h547108[1] && - !_theResult____h547108[0] || + assign _theResult___fst_exp__h555414 = + (!_theResult____h547107[56] && !_theResult____h547107[55] && + !_theResult____h547107[54] && + !_theResult____h547107[53] && + !_theResult____h547107[52] && + !_theResult____h547107[51] && + !_theResult____h547107[50] && + !_theResult____h547107[49] && + !_theResult____h547107[48] && + !_theResult____h547107[47] && + !_theResult____h547107[46] && + !_theResult____h547107[45] && + !_theResult____h547107[44] && + !_theResult____h547107[43] && + !_theResult____h547107[42] && + !_theResult____h547107[41] && + !_theResult____h547107[40] && + !_theResult____h547107[39] && + !_theResult____h547107[38] && + !_theResult____h547107[37] && + !_theResult____h547107[36] && + !_theResult____h547107[35] && + !_theResult____h547107[34] && + !_theResult____h547107[33] && + !_theResult____h547107[32] && + !_theResult____h547107[31] && + !_theResult____h547107[30] && + !_theResult____h547107[29] && + !_theResult____h547107[28] && + !_theResult____h547107[27] && + !_theResult____h547107[26] && + !_theResult____h547107[25] && + !_theResult____h547107[24] && + !_theResult____h547107[23] && + !_theResult____h547107[22] && + !_theResult____h547107[21] && + !_theResult____h547107[20] && + !_theResult____h547107[19] && + !_theResult____h547107[18] && + !_theResult____h547107[17] && + !_theResult____h547107[16] && + !_theResult____h547107[15] && + !_theResult____h547107[14] && + !_theResult____h547107[13] && + !_theResult____h547107[12] && + !_theResult____h547107[11] && + !_theResult____h547107[10] && + !_theResult____h547107[9] && + !_theResult____h547107[8] && + !_theResult____h547107[7] && + !_theResult____h547107[6] && + !_theResult____h547107[5] && + !_theResult____h547107[4] && + !_theResult____h547107[3] && + !_theResult____h547107[2] && + !_theResult____h547107[1] && + !_theResult____h547107[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493) ? 11'd0 : - _theResult___fst_exp__h555409 ; - assign _theResult___fst_exp__h555418 = - (!_theResult____h547108[56] && _theResult____h547108[55]) ? + _theResult___fst_exp__h555408 ; + assign _theResult___fst_exp__h555417 = + (!_theResult____h547107[56] && _theResult____h547107[55]) ? 11'd1 : - _theResult___fst_exp__h555415 ; - assign _theResult___fst_exp__h556173 = + _theResult___fst_exp__h555414 ; + assign _theResult___fst_exp__h556172 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 : + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 ; - assign _theResult___fst_exp__h556176 = - (_theResult___fst_exp__h555344 == 11'd2047) ? - _theResult___fst_exp__h555344 : - _theResult___fst_exp__h556173 ; - assign _theResult___fst_exp__h564129 = + assign _theResult___fst_exp__h556175 = + (_theResult___fst_exp__h555343 == 11'd2047) ? + _theResult___fst_exp__h555343 : + _theResult___fst_exp__h556172 ; + assign _theResult___fst_exp__h564128 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] ; - assign _theResult___fst_exp__h564168 = + assign _theResult___fst_exp__h564167 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h564174 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___fst_exp__h564173 = + (f2_exp__h526519 == 8'd0 && !f2_sfd__h526520[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543) ? 11'd0 : - _theResult___fst_exp__h564168 ; - assign _theResult___fst_exp__h564177 = - (f2_exp__h526520 == 8'd0) ? - _theResult___fst_exp__h564174 : - _theResult___fst_exp__h564129 ; - assign _theResult___fst_exp__h564957 = + _theResult___fst_exp__h564167 ; + assign _theResult___fst_exp__h564176 = + (f2_exp__h526519 == 8'd0) ? + _theResult___fst_exp__h564173 : + _theResult___fst_exp__h564128 ; + assign _theResult___fst_exp__h564956 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 : + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 ; - assign _theResult___fst_exp__h564960 = - (_theResult___fst_exp__h564177 == 11'd2047) ? - _theResult___fst_exp__h564177 : - _theResult___fst_exp__h564957 ; - assign _theResult___fst_exp__h564969 = - (f2_exp__h526520 == 8'd0) ? + assign _theResult___fst_exp__h564959 = + (_theResult___fst_exp__h564176 == 11'd2047) ? + _theResult___fst_exp__h564176 : + _theResult___fst_exp__h564956 ; + assign _theResult___fst_exp__h564968 = + (f2_exp__h526519 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_exp__h546528 : - _theResult___fst_exp__h530694) : + _theResult___snd_fst_exp__h546527 : + _theResult___fst_exp__h530693) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_exp__h564963 : - _theResult___fst_exp__h530694) ; - assign _theResult___fst_exp__h564972 = - (f2_exp__h526520 == 8'd0 && f2_sfd__h526521 == 23'd0) ? + _theResult___snd_fst_exp__h564962 : + _theResult___fst_exp__h530693) ; + assign _theResult___fst_exp__h564971 = + (f2_exp__h526519 == 8'd0 && f2_sfd__h526520 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h564969 ; - assign _theResult___fst_exp__h569998 = + _theResult___fst_exp__h564968 ; + assign _theResult___fst_exp__h569997 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_exp__h585062 = + assign _theResult___fst_exp__h585061 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h585068 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___fst_exp__h585067 = + (f3_exp__h565823 == 8'd0 && !f3_sfd__h565824[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426) ? 11'd0 : - _theResult___fst_exp__h585062 ; - assign _theResult___fst_exp__h585071 = - (f3_exp__h565824 == 8'd0) ? - _theResult___fst_exp__h585068 : + _theResult___fst_exp__h585061 ; + assign _theResult___fst_exp__h585070 = + (f3_exp__h565823 == 8'd0) ? + _theResult___fst_exp__h585067 : 11'd897 ; - assign _theResult___fst_exp__h585826 = + assign _theResult___fst_exp__h585825 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 : + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 ; - assign _theResult___fst_exp__h585829 = - (_theResult___fst_exp__h585071 == 11'd2047) ? - _theResult___fst_exp__h585071 : - _theResult___fst_exp__h585826 ; - assign _theResult___fst_exp__h594648 = - _theResult____h586412[56] ? + assign _theResult___fst_exp__h585828 = + (_theResult___fst_exp__h585070 == 11'd2047) ? + _theResult___fst_exp__h585070 : + _theResult___fst_exp__h585825 ; + assign _theResult___fst_exp__h594647 = + _theResult____h586411[56] ? 11'd2 : - _theResult___fst_exp__h594722 ; - assign _theResult___fst_exp__h594713 = + _theResult___fst_exp__h594721 ; + assign _theResult___fst_exp__h594712 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 } ; - assign _theResult___fst_exp__h594719 = - (!_theResult____h586412[56] && !_theResult____h586412[55] && - !_theResult____h586412[54] && - !_theResult____h586412[53] && - !_theResult____h586412[52] && - !_theResult____h586412[51] && - !_theResult____h586412[50] && - !_theResult____h586412[49] && - !_theResult____h586412[48] && - !_theResult____h586412[47] && - !_theResult____h586412[46] && - !_theResult____h586412[45] && - !_theResult____h586412[44] && - !_theResult____h586412[43] && - !_theResult____h586412[42] && - !_theResult____h586412[41] && - !_theResult____h586412[40] && - !_theResult____h586412[39] && - !_theResult____h586412[38] && - !_theResult____h586412[37] && - !_theResult____h586412[36] && - !_theResult____h586412[35] && - !_theResult____h586412[34] && - !_theResult____h586412[33] && - !_theResult____h586412[32] && - !_theResult____h586412[31] && - !_theResult____h586412[30] && - !_theResult____h586412[29] && - !_theResult____h586412[28] && - !_theResult____h586412[27] && - !_theResult____h586412[26] && - !_theResult____h586412[25] && - !_theResult____h586412[24] && - !_theResult____h586412[23] && - !_theResult____h586412[22] && - !_theResult____h586412[21] && - !_theResult____h586412[20] && - !_theResult____h586412[19] && - !_theResult____h586412[18] && - !_theResult____h586412[17] && - !_theResult____h586412[16] && - !_theResult____h586412[15] && - !_theResult____h586412[14] && - !_theResult____h586412[13] && - !_theResult____h586412[12] && - !_theResult____h586412[11] && - !_theResult____h586412[10] && - !_theResult____h586412[9] && - !_theResult____h586412[8] && - !_theResult____h586412[7] && - !_theResult____h586412[6] && - !_theResult____h586412[5] && - !_theResult____h586412[4] && - !_theResult____h586412[3] && - !_theResult____h586412[2] && - !_theResult____h586412[1] && - !_theResult____h586412[0] || + assign _theResult___fst_exp__h594718 = + (!_theResult____h586411[56] && !_theResult____h586411[55] && + !_theResult____h586411[54] && + !_theResult____h586411[53] && + !_theResult____h586411[52] && + !_theResult____h586411[51] && + !_theResult____h586411[50] && + !_theResult____h586411[49] && + !_theResult____h586411[48] && + !_theResult____h586411[47] && + !_theResult____h586411[46] && + !_theResult____h586411[45] && + !_theResult____h586411[44] && + !_theResult____h586411[43] && + !_theResult____h586411[42] && + !_theResult____h586411[41] && + !_theResult____h586411[40] && + !_theResult____h586411[39] && + !_theResult____h586411[38] && + !_theResult____h586411[37] && + !_theResult____h586411[36] && + !_theResult____h586411[35] && + !_theResult____h586411[34] && + !_theResult____h586411[33] && + !_theResult____h586411[32] && + !_theResult____h586411[31] && + !_theResult____h586411[30] && + !_theResult____h586411[29] && + !_theResult____h586411[28] && + !_theResult____h586411[27] && + !_theResult____h586411[26] && + !_theResult____h586411[25] && + !_theResult____h586411[24] && + !_theResult____h586411[23] && + !_theResult____h586411[22] && + !_theResult____h586411[21] && + !_theResult____h586411[20] && + !_theResult____h586411[19] && + !_theResult____h586411[18] && + !_theResult____h586411[17] && + !_theResult____h586411[16] && + !_theResult____h586411[15] && + !_theResult____h586411[14] && + !_theResult____h586411[13] && + !_theResult____h586411[12] && + !_theResult____h586411[11] && + !_theResult____h586411[10] && + !_theResult____h586411[9] && + !_theResult____h586411[8] && + !_theResult____h586411[7] && + !_theResult____h586411[6] && + !_theResult____h586411[5] && + !_theResult____h586411[4] && + !_theResult____h586411[3] && + !_theResult____h586411[2] && + !_theResult____h586411[1] && + !_theResult____h586411[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723) ? 11'd0 : - _theResult___fst_exp__h594713 ; - assign _theResult___fst_exp__h594722 = - (!_theResult____h586412[56] && _theResult____h586412[55]) ? + _theResult___fst_exp__h594712 ; + assign _theResult___fst_exp__h594721 = + (!_theResult____h586411[56] && _theResult____h586411[55]) ? 11'd1 : - _theResult___fst_exp__h594719 ; - assign _theResult___fst_exp__h595477 = + _theResult___fst_exp__h594718 ; + assign _theResult___fst_exp__h595476 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 : + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 ; - assign _theResult___fst_exp__h595480 = - (_theResult___fst_exp__h594648 == 11'd2047) ? - _theResult___fst_exp__h594648 : - _theResult___fst_exp__h595477 ; - assign _theResult___fst_exp__h603433 = + assign _theResult___fst_exp__h595479 = + (_theResult___fst_exp__h594647 == 11'd2047) ? + _theResult___fst_exp__h594647 : + _theResult___fst_exp__h595476 ; + assign _theResult___fst_exp__h603432 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] ; - assign _theResult___fst_exp__h603472 = + assign _theResult___fst_exp__h603471 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h603478 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___fst_exp__h603477 = + (f3_exp__h565823 == 8'd0 && !f3_sfd__h565824[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773) ? 11'd0 : - _theResult___fst_exp__h603472 ; - assign _theResult___fst_exp__h603481 = - (f3_exp__h565824 == 8'd0) ? - _theResult___fst_exp__h603478 : - _theResult___fst_exp__h603433 ; - assign _theResult___fst_exp__h604261 = + _theResult___fst_exp__h603471 ; + assign _theResult___fst_exp__h603480 = + (f3_exp__h565823 == 8'd0) ? + _theResult___fst_exp__h603477 : + _theResult___fst_exp__h603432 ; + assign _theResult___fst_exp__h604260 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 : + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 ; - assign _theResult___fst_exp__h604264 = - (_theResult___fst_exp__h603481 == 11'd2047) ? - _theResult___fst_exp__h603481 : - _theResult___fst_exp__h604261 ; - assign _theResult___fst_exp__h604273 = - (f3_exp__h565824 == 8'd0) ? + assign _theResult___fst_exp__h604263 = + (_theResult___fst_exp__h603480 == 11'd2047) ? + _theResult___fst_exp__h603480 : + _theResult___fst_exp__h604260 ; + assign _theResult___fst_exp__h604272 = + (f3_exp__h565823 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_exp__h585832 : - _theResult___fst_exp__h569998) : + _theResult___snd_fst_exp__h585831 : + _theResult___fst_exp__h569997) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_exp__h604267 : - _theResult___fst_exp__h569998) ; - assign _theResult___fst_exp__h604276 = - (f3_exp__h565824 == 8'd0 && f3_sfd__h565825 == 23'd0) ? + _theResult___snd_fst_exp__h604266 : + _theResult___fst_exp__h569997) ; + assign _theResult___fst_exp__h604275 = + (f3_exp__h565823 == 8'd0 && f3_sfd__h565824 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h604273 ; - assign _theResult___fst_sfd__h359444 = - (_theResult___fst_exp__h358846 == 8'd255) ? - sfdin__h358840[56:34] : - _theResult___fst_sfd__h359441 ; - assign _theResult___fst_sfd__h368026 = - (_theResult___fst_exp__h367502 == 8'd255) ? - _theResult___snd__h367453[56:34] : - _theResult___fst_sfd__h368023 ; - assign _theResult___fst_sfd__h377210 = - (_theResult___fst_exp__h376612 == 8'd255) ? - sfdin__h376606[56:34] : - _theResult___fst_sfd__h377207 ; - assign _theResult___fst_sfd__h385846 = - (_theResult___fst_exp__h385297 == 8'd255) ? - _theResult___snd__h385243[56:34] : - _theResult___fst_sfd__h385843 ; - assign _theResult___fst_sfd__h385855 = + _theResult___fst_exp__h604272 ; + assign _theResult___fst_sfd__h359443 = + (_theResult___fst_exp__h358845 == 8'd255) ? + sfdin__h358839[56:34] : + _theResult___fst_sfd__h359440 ; + assign _theResult___fst_sfd__h368025 = + (_theResult___fst_exp__h367501 == 8'd255) ? + _theResult___snd__h367452[56:34] : + _theResult___fst_sfd__h368022 ; + assign _theResult___fst_sfd__h377209 = + (_theResult___fst_exp__h376611 == 8'd255) ? + sfdin__h376605[56:34] : + _theResult___fst_sfd__h377206 ; + assign _theResult___fst_sfd__h385845 = + (_theResult___fst_exp__h385296 == 8'd255) ? + _theResult___snd__h385242[56:34] : + _theResult___fst_sfd__h385842 ; + assign _theResult___fst_sfd__h385854 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_sfd__h368029 : - _theResult___fst_sfd__h350718) : + _theResult___snd_fst_sfd__h368028 : + _theResult___fst_sfd__h350717) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_sfd__h385849 : - _theResult___fst_sfd__h350718) ; - assign _theResult___fst_sfd__h385861 = + _theResult___snd_fst_sfd__h385848 : + _theResult___fst_sfd__h350717) ; + assign _theResult___fst_sfd__h385860 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -26216,33 +26199,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h385855 ; - assign _theResult___fst_sfd__h405141 = - (_theResult___fst_exp__h404543 == 8'd255) ? - sfdin__h404537[56:34] : - _theResult___fst_sfd__h405138 ; - assign _theResult___fst_sfd__h413723 = - (_theResult___fst_exp__h413199 == 8'd255) ? - _theResult___snd__h413150[56:34] : - _theResult___fst_sfd__h413720 ; - assign _theResult___fst_sfd__h422907 = - (_theResult___fst_exp__h422309 == 8'd255) ? - sfdin__h422303[56:34] : - _theResult___fst_sfd__h422904 ; - assign _theResult___fst_sfd__h431543 = - (_theResult___fst_exp__h430994 == 8'd255) ? - _theResult___snd__h430940[56:34] : - _theResult___fst_sfd__h431540 ; - assign _theResult___fst_sfd__h431552 = + _theResult___fst_sfd__h385854 ; + assign _theResult___fst_sfd__h405140 = + (_theResult___fst_exp__h404542 == 8'd255) ? + sfdin__h404536[56:34] : + _theResult___fst_sfd__h405137 ; + assign _theResult___fst_sfd__h413722 = + (_theResult___fst_exp__h413198 == 8'd255) ? + _theResult___snd__h413149[56:34] : + _theResult___fst_sfd__h413719 ; + assign _theResult___fst_sfd__h422906 = + (_theResult___fst_exp__h422308 == 8'd255) ? + sfdin__h422302[56:34] : + _theResult___fst_sfd__h422903 ; + assign _theResult___fst_sfd__h431542 = + (_theResult___fst_exp__h430993 == 8'd255) ? + _theResult___snd__h430939[56:34] : + _theResult___fst_sfd__h431539 ; + assign _theResult___fst_sfd__h431551 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_sfd__h413726 : - _theResult___fst_sfd__h396417) : + _theResult___snd_fst_sfd__h413725 : + _theResult___fst_sfd__h396416) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_sfd__h431546 : - _theResult___fst_sfd__h396417) ; - assign _theResult___fst_sfd__h431558 = + _theResult___snd_fst_sfd__h431545 : + _theResult___fst_sfd__h396416) ; + assign _theResult___fst_sfd__h431557 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -26250,33 +26233,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h431552 ; - assign _theResult___fst_sfd__h450836 = - (_theResult___fst_exp__h450238 == 8'd255) ? - sfdin__h450232[56:34] : - _theResult___fst_sfd__h450833 ; - assign _theResult___fst_sfd__h459418 = - (_theResult___fst_exp__h458894 == 8'd255) ? - _theResult___snd__h458845[56:34] : - _theResult___fst_sfd__h459415 ; - assign _theResult___fst_sfd__h468602 = - (_theResult___fst_exp__h468004 == 8'd255) ? - sfdin__h467998[56:34] : - _theResult___fst_sfd__h468599 ; - assign _theResult___fst_sfd__h477238 = - (_theResult___fst_exp__h476689 == 8'd255) ? - _theResult___snd__h476635[56:34] : - _theResult___fst_sfd__h477235 ; - assign _theResult___fst_sfd__h477247 = + _theResult___fst_sfd__h431551 ; + assign _theResult___fst_sfd__h450835 = + (_theResult___fst_exp__h450237 == 8'd255) ? + sfdin__h450231[56:34] : + _theResult___fst_sfd__h450832 ; + assign _theResult___fst_sfd__h459417 = + (_theResult___fst_exp__h458893 == 8'd255) ? + _theResult___snd__h458844[56:34] : + _theResult___fst_sfd__h459414 ; + assign _theResult___fst_sfd__h468601 = + (_theResult___fst_exp__h468003 == 8'd255) ? + sfdin__h467997[56:34] : + _theResult___fst_sfd__h468598 ; + assign _theResult___fst_sfd__h477237 = + (_theResult___fst_exp__h476688 == 8'd255) ? + _theResult___snd__h476634[56:34] : + _theResult___fst_sfd__h477234 ; + assign _theResult___fst_sfd__h477246 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_sfd__h459421 : - _theResult___fst_sfd__h442112) : + _theResult___snd_fst_sfd__h459420 : + _theResult___fst_sfd__h442111) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_sfd__h477241 : - _theResult___fst_sfd__h442112) ; - assign _theResult___fst_sfd__h477253 = + _theResult___snd_fst_sfd__h477240 : + _theResult___fst_sfd__h442111) ; + assign _theResult___fst_sfd__h477252 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -26284,1308 +26267,1308 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h477247 ; - assign _theResult___fst_sfd__h491842 = + _theResult___fst_sfd__h477246 ; + assign _theResult___fst_sfd__h491841 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_sfd__h507670 = + assign _theResult___fst_sfd__h507669 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q210 : + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 ; - assign _theResult___fst_sfd__h507673 = - (_theResult___fst_exp__h506914 == 11'd2047) ? - _theResult___snd__h506865[56:5] : - _theResult___fst_sfd__h507670 ; - assign _theResult___fst_sfd__h517321 = + assign _theResult___fst_sfd__h507672 = + (_theResult___fst_exp__h506913 == 11'd2047) ? + _theResult___snd__h506864[56:5] : + _theResult___fst_sfd__h507669 ; + assign _theResult___fst_sfd__h517320 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 ; - assign _theResult___fst_sfd__h517324 = - (_theResult___fst_exp__h516491 == 11'd2047) ? - sfdin__h516485[56:5] : - _theResult___fst_sfd__h517321 ; - assign _theResult___fst_sfd__h526105 = + assign _theResult___fst_sfd__h517323 = + (_theResult___fst_exp__h516490 == 11'd2047) ? + sfdin__h516484[56:5] : + _theResult___fst_sfd__h517320 ; + assign _theResult___fst_sfd__h526104 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 : + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 ; - assign _theResult___fst_sfd__h526108 = - (_theResult___fst_exp__h525324 == 11'd2047) ? - _theResult___snd__h525270[56:5] : - _theResult___fst_sfd__h526105 ; - assign _theResult___fst_sfd__h526117 = - (f1_exp__h487526 == 8'd0) ? + assign _theResult___fst_sfd__h526107 = + (_theResult___fst_exp__h525323 == 11'd2047) ? + _theResult___snd__h525269[56:5] : + _theResult___fst_sfd__h526104 ; + assign _theResult___fst_sfd__h526116 = + (f1_exp__h487525 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_sfd__h507676 : - _theResult___fst_sfd__h491842) : + _theResult___snd_fst_sfd__h507675 : + _theResult___fst_sfd__h491841) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_sfd__h526111 : - _theResult___fst_sfd__h491842) ; - assign _theResult___fst_sfd__h526123 = - ((f1_exp__h487526 == 8'd255 || f1_exp__h487526 == 8'd0) && - f1_sfd__h487527 == 23'd0) ? + _theResult___snd_fst_sfd__h526110 : + _theResult___fst_sfd__h491841) ; + assign _theResult___fst_sfd__h526122 = + ((f1_exp__h487525 == 8'd255 || f1_exp__h487525 == 8'd0) && + f1_sfd__h487526 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h526117 ; - assign _theResult___fst_sfd__h530695 = + _theResult___fst_sfd__h526116 ; + assign _theResult___fst_sfd__h530694 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_sfd__h546523 = + assign _theResult___fst_sfd__h546522 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 : + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 ; - assign _theResult___fst_sfd__h546526 = - (_theResult___fst_exp__h545767 == 11'd2047) ? - _theResult___snd__h545718[56:5] : - _theResult___fst_sfd__h546523 ; - assign _theResult___fst_sfd__h556174 = + assign _theResult___fst_sfd__h546525 = + (_theResult___fst_exp__h545766 == 11'd2047) ? + _theResult___snd__h545717[56:5] : + _theResult___fst_sfd__h546522 ; + assign _theResult___fst_sfd__h556173 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 ; - assign _theResult___fst_sfd__h556177 = - (_theResult___fst_exp__h555344 == 11'd2047) ? - sfdin__h555338[56:5] : - _theResult___fst_sfd__h556174 ; - assign _theResult___fst_sfd__h564958 = + assign _theResult___fst_sfd__h556176 = + (_theResult___fst_exp__h555343 == 11'd2047) ? + sfdin__h555337[56:5] : + _theResult___fst_sfd__h556173 ; + assign _theResult___fst_sfd__h564957 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 : + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 ; - assign _theResult___fst_sfd__h564961 = - (_theResult___fst_exp__h564177 == 11'd2047) ? - _theResult___snd__h564123[56:5] : - _theResult___fst_sfd__h564958 ; - assign _theResult___fst_sfd__h564970 = - (f2_exp__h526520 == 8'd0) ? + assign _theResult___fst_sfd__h564960 = + (_theResult___fst_exp__h564176 == 11'd2047) ? + _theResult___snd__h564122[56:5] : + _theResult___fst_sfd__h564957 ; + assign _theResult___fst_sfd__h564969 = + (f2_exp__h526519 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_sfd__h546529 : - _theResult___fst_sfd__h530695) : + _theResult___snd_fst_sfd__h546528 : + _theResult___fst_sfd__h530694) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_sfd__h564964 : - _theResult___fst_sfd__h530695) ; - assign _theResult___fst_sfd__h564976 = - ((f2_exp__h526520 == 8'd255 || f2_exp__h526520 == 8'd0) && - f2_sfd__h526521 == 23'd0) ? + _theResult___snd_fst_sfd__h564963 : + _theResult___fst_sfd__h530694) ; + assign _theResult___fst_sfd__h564975 = + ((f2_exp__h526519 == 8'd255 || f2_exp__h526519 == 8'd0) && + f2_sfd__h526520 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h564970 ; - assign _theResult___fst_sfd__h569999 = + _theResult___fst_sfd__h564969 ; + assign _theResult___fst_sfd__h569998 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 ; - assign _theResult___fst_sfd__h585827 = + assign _theResult___fst_sfd__h585826 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 : + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 ; - assign _theResult___fst_sfd__h585830 = - (_theResult___fst_exp__h585071 == 11'd2047) ? - _theResult___snd__h585022[56:5] : - _theResult___fst_sfd__h585827 ; - assign _theResult___fst_sfd__h595478 = + assign _theResult___fst_sfd__h585829 = + (_theResult___fst_exp__h585070 == 11'd2047) ? + _theResult___snd__h585021[56:5] : + _theResult___fst_sfd__h585826 ; + assign _theResult___fst_sfd__h595477 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 ; - assign _theResult___fst_sfd__h595481 = - (_theResult___fst_exp__h594648 == 11'd2047) ? - sfdin__h594642[56:5] : - _theResult___fst_sfd__h595478 ; - assign _theResult___fst_sfd__h604262 = + assign _theResult___fst_sfd__h595480 = + (_theResult___fst_exp__h594647 == 11'd2047) ? + sfdin__h594641[56:5] : + _theResult___fst_sfd__h595477 ; + assign _theResult___fst_sfd__h604261 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 : + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 ; - assign _theResult___fst_sfd__h604265 = - (_theResult___fst_exp__h603481 == 11'd2047) ? - _theResult___snd__h603427[56:5] : - _theResult___fst_sfd__h604262 ; - assign _theResult___fst_sfd__h604274 = - (f3_exp__h565824 == 8'd0) ? + assign _theResult___fst_sfd__h604264 = + (_theResult___fst_exp__h603480 == 11'd2047) ? + _theResult___snd__h603426[56:5] : + _theResult___fst_sfd__h604261 ; + assign _theResult___fst_sfd__h604273 = + (f3_exp__h565823 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_sfd__h585833 : - _theResult___fst_sfd__h569999) : + _theResult___snd_fst_sfd__h585832 : + _theResult___fst_sfd__h569998) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_sfd__h604268 : - _theResult___fst_sfd__h569999) ; - assign _theResult___fst_sfd__h604280 = - ((f3_exp__h565824 == 8'd255 || f3_exp__h565824 == 8'd0) && - f3_sfd__h565825 == 23'd0) ? + _theResult___snd_fst_sfd__h604267 : + _theResult___fst_sfd__h569998) ; + assign _theResult___fst_sfd__h604279 = + ((f3_exp__h565823 == 8'd255 || f3_exp__h565823 == 8'd0) && + f3_sfd__h565824 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h604274 ; - assign _theResult___sfd__h359363 = - sfd__h358938[24] ? - ((_theResult___fst_exp__h358846 == 8'd254) ? + _theResult___fst_sfd__h604273 ; + assign _theResult___sfd__h359362 = + sfd__h358937[24] ? + ((_theResult___fst_exp__h358845 == 8'd254) ? 23'd0 : - sfd__h358938[23:1]) : - sfd__h358938[22:0] ; - assign _theResult___sfd__h367945 = - sfd__h367520[24] ? - ((_theResult___fst_exp__h367502 == 8'd254) ? + sfd__h358937[23:1]) : + sfd__h358937[22:0] ; + assign _theResult___sfd__h367944 = + sfd__h367519[24] ? + ((_theResult___fst_exp__h367501 == 8'd254) ? 23'd0 : - sfd__h367520[23:1]) : - sfd__h367520[22:0] ; - assign _theResult___sfd__h377129 = - sfd__h376704[24] ? - ((_theResult___fst_exp__h376612 == 8'd254) ? + sfd__h367519[23:1]) : + sfd__h367519[22:0] ; + assign _theResult___sfd__h377128 = + sfd__h376703[24] ? + ((_theResult___fst_exp__h376611 == 8'd254) ? 23'd0 : - sfd__h376704[23:1]) : - sfd__h376704[22:0] ; - assign _theResult___sfd__h385765 = - sfd__h385316[24] ? - ((_theResult___fst_exp__h385297 == 8'd254) ? + sfd__h376703[23:1]) : + sfd__h376703[22:0] ; + assign _theResult___sfd__h385764 = + sfd__h385315[24] ? + ((_theResult___fst_exp__h385296 == 8'd254) ? 23'd0 : - sfd__h385316[23:1]) : - sfd__h385316[22:0] ; - assign _theResult___sfd__h385867 = + sfd__h385315[23:1]) : + sfd__h385315[22:0] ; + assign _theResult___sfd__h385866 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h343080 : - _theResult___fst_sfd__h385861 ; - assign _theResult___sfd__h405060 = - sfd__h404635[24] ? - ((_theResult___fst_exp__h404543 == 8'd254) ? + _theResult___snd_fst_sfd__h343079 : + _theResult___fst_sfd__h385860 ; + assign _theResult___sfd__h405059 = + sfd__h404634[24] ? + ((_theResult___fst_exp__h404542 == 8'd254) ? 23'd0 : - sfd__h404635[23:1]) : - sfd__h404635[22:0] ; - assign _theResult___sfd__h413642 = - sfd__h413217[24] ? - ((_theResult___fst_exp__h413199 == 8'd254) ? + sfd__h404634[23:1]) : + sfd__h404634[22:0] ; + assign _theResult___sfd__h413641 = + sfd__h413216[24] ? + ((_theResult___fst_exp__h413198 == 8'd254) ? 23'd0 : - sfd__h413217[23:1]) : - sfd__h413217[22:0] ; - assign _theResult___sfd__h422826 = - sfd__h422401[24] ? - ((_theResult___fst_exp__h422309 == 8'd254) ? + sfd__h413216[23:1]) : + sfd__h413216[22:0] ; + assign _theResult___sfd__h422825 = + sfd__h422400[24] ? + ((_theResult___fst_exp__h422308 == 8'd254) ? 23'd0 : - sfd__h422401[23:1]) : - sfd__h422401[22:0] ; - assign _theResult___sfd__h431462 = - sfd__h431013[24] ? - ((_theResult___fst_exp__h430994 == 8'd254) ? + sfd__h422400[23:1]) : + sfd__h422400[22:0] ; + assign _theResult___sfd__h431461 = + sfd__h431012[24] ? + ((_theResult___fst_exp__h430993 == 8'd254) ? 23'd0 : - sfd__h431013[23:1]) : - sfd__h431013[22:0] ; - assign _theResult___sfd__h431564 = + sfd__h431012[23:1]) : + sfd__h431012[22:0] ; + assign _theResult___sfd__h431563 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h388782 : - _theResult___fst_sfd__h431558 ; - assign _theResult___sfd__h450755 = - sfd__h450330[24] ? - ((_theResult___fst_exp__h450238 == 8'd254) ? + _theResult___snd_fst_sfd__h388781 : + _theResult___fst_sfd__h431557 ; + assign _theResult___sfd__h450754 = + sfd__h450329[24] ? + ((_theResult___fst_exp__h450237 == 8'd254) ? 23'd0 : - sfd__h450330[23:1]) : - sfd__h450330[22:0] ; - assign _theResult___sfd__h459337 = - sfd__h458912[24] ? - ((_theResult___fst_exp__h458894 == 8'd254) ? + sfd__h450329[23:1]) : + sfd__h450329[22:0] ; + assign _theResult___sfd__h459336 = + sfd__h458911[24] ? + ((_theResult___fst_exp__h458893 == 8'd254) ? 23'd0 : - sfd__h458912[23:1]) : - sfd__h458912[22:0] ; - assign _theResult___sfd__h468521 = - sfd__h468096[24] ? - ((_theResult___fst_exp__h468004 == 8'd254) ? + sfd__h458911[23:1]) : + sfd__h458911[22:0] ; + assign _theResult___sfd__h468520 = + sfd__h468095[24] ? + ((_theResult___fst_exp__h468003 == 8'd254) ? 23'd0 : - sfd__h468096[23:1]) : - sfd__h468096[22:0] ; - assign _theResult___sfd__h477157 = - sfd__h476708[24] ? - ((_theResult___fst_exp__h476689 == 8'd254) ? + sfd__h468095[23:1]) : + sfd__h468095[22:0] ; + assign _theResult___sfd__h477156 = + sfd__h476707[24] ? + ((_theResult___fst_exp__h476688 == 8'd254) ? 23'd0 : - sfd__h476708[23:1]) : - sfd__h476708[22:0] ; - assign _theResult___sfd__h477259 = + sfd__h476707[23:1]) : + sfd__h476707[22:0] ; + assign _theResult___sfd__h477258 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h434477 : - _theResult___fst_sfd__h477253 ; - assign _theResult___sfd__h507570 = - sfd__h506932[53] ? - ((_theResult___fst_exp__h506914 == 11'd2046) ? + _theResult___snd_fst_sfd__h434476 : + _theResult___fst_sfd__h477252 ; + assign _theResult___sfd__h507569 = + sfd__h506931[53] ? + ((_theResult___fst_exp__h506913 == 11'd2046) ? 52'd0 : - sfd__h506932[52:1]) : - sfd__h506932[51:0] ; - assign _theResult___sfd__h517221 = - sfd__h516583[53] ? - ((_theResult___fst_exp__h516491 == 11'd2046) ? + sfd__h506931[52:1]) : + sfd__h506931[51:0] ; + assign _theResult___sfd__h517220 = + sfd__h516582[53] ? + ((_theResult___fst_exp__h516490 == 11'd2046) ? 52'd0 : - sfd__h516583[52:1]) : - sfd__h516583[51:0] ; - assign _theResult___sfd__h526005 = - sfd__h525343[53] ? - ((_theResult___fst_exp__h525324 == 11'd2046) ? + sfd__h516582[52:1]) : + sfd__h516582[51:0] ; + assign _theResult___sfd__h526004 = + sfd__h525342[53] ? + ((_theResult___fst_exp__h525323 == 11'd2046) ? 52'd0 : - sfd__h525343[52:1]) : - sfd__h525343[51:0] ; - assign _theResult___sfd__h546423 = - sfd__h545785[53] ? - ((_theResult___fst_exp__h545767 == 11'd2046) ? + sfd__h525342[52:1]) : + sfd__h525342[51:0] ; + assign _theResult___sfd__h546422 = + sfd__h545784[53] ? + ((_theResult___fst_exp__h545766 == 11'd2046) ? 52'd0 : - sfd__h545785[52:1]) : - sfd__h545785[51:0] ; - assign _theResult___sfd__h556074 = - sfd__h555436[53] ? - ((_theResult___fst_exp__h555344 == 11'd2046) ? + sfd__h545784[52:1]) : + sfd__h545784[51:0] ; + assign _theResult___sfd__h556073 = + sfd__h555435[53] ? + ((_theResult___fst_exp__h555343 == 11'd2046) ? 52'd0 : - sfd__h555436[52:1]) : - sfd__h555436[51:0] ; - assign _theResult___sfd__h564858 = - sfd__h564196[53] ? - ((_theResult___fst_exp__h564177 == 11'd2046) ? + sfd__h555435[52:1]) : + sfd__h555435[51:0] ; + assign _theResult___sfd__h564857 = + sfd__h564195[53] ? + ((_theResult___fst_exp__h564176 == 11'd2046) ? 52'd0 : - sfd__h564196[52:1]) : - sfd__h564196[51:0] ; - assign _theResult___sfd__h585727 = - sfd__h585089[53] ? - ((_theResult___fst_exp__h585071 == 11'd2046) ? + sfd__h564195[52:1]) : + sfd__h564195[51:0] ; + assign _theResult___sfd__h585726 = + sfd__h585088[53] ? + ((_theResult___fst_exp__h585070 == 11'd2046) ? 52'd0 : - sfd__h585089[52:1]) : - sfd__h585089[51:0] ; - assign _theResult___sfd__h595378 = - sfd__h594740[53] ? - ((_theResult___fst_exp__h594648 == 11'd2046) ? + sfd__h585088[52:1]) : + sfd__h585088[51:0] ; + assign _theResult___sfd__h595377 = + sfd__h594739[53] ? + ((_theResult___fst_exp__h594647 == 11'd2046) ? 52'd0 : - sfd__h594740[52:1]) : - sfd__h594740[51:0] ; - assign _theResult___sfd__h604162 = - sfd__h603500[53] ? - ((_theResult___fst_exp__h603481 == 11'd2046) ? + sfd__h594739[52:1]) : + sfd__h594739[51:0] ; + assign _theResult___sfd__h604161 = + sfd__h603499[53] ? + ((_theResult___fst_exp__h603480 == 11'd2046) ? 52'd0 : - sfd__h603500[52:1]) : - sfd__h603500[51:0] ; - assign _theResult___snd__h358857 = { _theResult____h350735[55:0], 1'd0 } ; - assign _theResult___snd__h358868 = - (!_theResult____h350735[56] && _theResult____h350735[55]) ? - _theResult___snd__h358870 : - _theResult___snd__h358880 ; - assign _theResult___snd__h358870 = { _theResult____h350735[54:0], 2'd0 } ; - assign _theResult___snd__h358880 = - (!_theResult____h350735[56] && !_theResult____h350735[55] && - !_theResult____h350735[54] && - !_theResult____h350735[53] && - !_theResult____h350735[52] && - !_theResult____h350735[51] && - !_theResult____h350735[50] && - !_theResult____h350735[49] && - !_theResult____h350735[48] && - !_theResult____h350735[47] && - !_theResult____h350735[46] && - !_theResult____h350735[45] && - !_theResult____h350735[44] && - !_theResult____h350735[43] && - !_theResult____h350735[42] && - !_theResult____h350735[41] && - !_theResult____h350735[40] && - !_theResult____h350735[39] && - !_theResult____h350735[38] && - !_theResult____h350735[37] && - !_theResult____h350735[36] && - !_theResult____h350735[35] && - !_theResult____h350735[34] && - !_theResult____h350735[33] && - !_theResult____h350735[32] && - !_theResult____h350735[31] && - !_theResult____h350735[30] && - !_theResult____h350735[29] && - !_theResult____h350735[28] && - !_theResult____h350735[27] && - !_theResult____h350735[26] && - !_theResult____h350735[25] && - !_theResult____h350735[24] && - !_theResult____h350735[23] && - !_theResult____h350735[22] && - !_theResult____h350735[21] && - !_theResult____h350735[20] && - !_theResult____h350735[19] && - !_theResult____h350735[18] && - !_theResult____h350735[17] && - !_theResult____h350735[16] && - !_theResult____h350735[15] && - !_theResult____h350735[14] && - !_theResult____h350735[13] && - !_theResult____h350735[12] && - !_theResult____h350735[11] && - !_theResult____h350735[10] && - !_theResult____h350735[9] && - !_theResult____h350735[8] && - !_theResult____h350735[7] && - !_theResult____h350735[6] && - !_theResult____h350735[5] && - !_theResult____h350735[4] && - !_theResult____h350735[3] && - !_theResult____h350735[2] && - !_theResult____h350735[1] && - !_theResult____h350735[0]) ? - _theResult____h350735 : - _theResult___snd__h358886 ; - assign _theResult___snd__h358886 = + sfd__h603499[52:1]) : + sfd__h603499[51:0] ; + assign _theResult___snd__h358856 = { _theResult____h350734[55:0], 1'd0 } ; + assign _theResult___snd__h358867 = + (!_theResult____h350734[56] && _theResult____h350734[55]) ? + _theResult___snd__h358869 : + _theResult___snd__h358879 ; + assign _theResult___snd__h358869 = { _theResult____h350734[54:0], 2'd0 } ; + assign _theResult___snd__h358879 = + (!_theResult____h350734[56] && !_theResult____h350734[55] && + !_theResult____h350734[54] && + !_theResult____h350734[53] && + !_theResult____h350734[52] && + !_theResult____h350734[51] && + !_theResult____h350734[50] && + !_theResult____h350734[49] && + !_theResult____h350734[48] && + !_theResult____h350734[47] && + !_theResult____h350734[46] && + !_theResult____h350734[45] && + !_theResult____h350734[44] && + !_theResult____h350734[43] && + !_theResult____h350734[42] && + !_theResult____h350734[41] && + !_theResult____h350734[40] && + !_theResult____h350734[39] && + !_theResult____h350734[38] && + !_theResult____h350734[37] && + !_theResult____h350734[36] && + !_theResult____h350734[35] && + !_theResult____h350734[34] && + !_theResult____h350734[33] && + !_theResult____h350734[32] && + !_theResult____h350734[31] && + !_theResult____h350734[30] && + !_theResult____h350734[29] && + !_theResult____h350734[28] && + !_theResult____h350734[27] && + !_theResult____h350734[26] && + !_theResult____h350734[25] && + !_theResult____h350734[24] && + !_theResult____h350734[23] && + !_theResult____h350734[22] && + !_theResult____h350734[21] && + !_theResult____h350734[20] && + !_theResult____h350734[19] && + !_theResult____h350734[18] && + !_theResult____h350734[17] && + !_theResult____h350734[16] && + !_theResult____h350734[15] && + !_theResult____h350734[14] && + !_theResult____h350734[13] && + !_theResult____h350734[12] && + !_theResult____h350734[11] && + !_theResult____h350734[10] && + !_theResult____h350734[9] && + !_theResult____h350734[8] && + !_theResult____h350734[7] && + !_theResult____h350734[6] && + !_theResult____h350734[5] && + !_theResult____h350734[4] && + !_theResult____h350734[3] && + !_theResult____h350734[2] && + !_theResult____h350734[1] && + !_theResult____h350734[0]) ? + _theResult____h350734 : + _theResult___snd__h358885 ; + assign _theResult___snd__h358885 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0], 2'd0 } ; - assign _theResult___snd__h358909 = - _theResult____h350735 << + assign _theResult___snd__h358908 = + _theResult____h350734 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 ; - assign _theResult___snd__h367453 = + assign _theResult___snd__h367452 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h367462 : - _theResult___snd__h367455 ; - assign _theResult___snd__h367455 = + _theResult___snd__h367461 : + _theResult___snd__h367454 ; + assign _theResult___snd__h367454 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h367462 = + assign _theResult___snd__h367461 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h343130 : - _theResult___snd__h367468 ; - assign _theResult___snd__h367468 = + sfd__h343129 : + _theResult___snd__h367467 ; + assign _theResult___snd__h367467 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0], 2'd0 } ; - assign _theResult___snd__h367491 = - sfd__h343130 << + assign _theResult___snd__h367490 = + sfd__h343129 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 ; - assign _theResult___snd__h376623 = { _theResult____h368374[55:0], 1'd0 } ; - assign _theResult___snd__h376634 = - (!_theResult____h368374[56] && _theResult____h368374[55]) ? - _theResult___snd__h376636 : - _theResult___snd__h376646 ; - assign _theResult___snd__h376636 = { _theResult____h368374[54:0], 2'd0 } ; - assign _theResult___snd__h376646 = - (!_theResult____h368374[56] && !_theResult____h368374[55] && - !_theResult____h368374[54] && - !_theResult____h368374[53] && - !_theResult____h368374[52] && - !_theResult____h368374[51] && - !_theResult____h368374[50] && - !_theResult____h368374[49] && - !_theResult____h368374[48] && - !_theResult____h368374[47] && - !_theResult____h368374[46] && - !_theResult____h368374[45] && - !_theResult____h368374[44] && - !_theResult____h368374[43] && - !_theResult____h368374[42] && - !_theResult____h368374[41] && - !_theResult____h368374[40] && - !_theResult____h368374[39] && - !_theResult____h368374[38] && - !_theResult____h368374[37] && - !_theResult____h368374[36] && - !_theResult____h368374[35] && - !_theResult____h368374[34] && - !_theResult____h368374[33] && - !_theResult____h368374[32] && - !_theResult____h368374[31] && - !_theResult____h368374[30] && - !_theResult____h368374[29] && - !_theResult____h368374[28] && - !_theResult____h368374[27] && - !_theResult____h368374[26] && - !_theResult____h368374[25] && - !_theResult____h368374[24] && - !_theResult____h368374[23] && - !_theResult____h368374[22] && - !_theResult____h368374[21] && - !_theResult____h368374[20] && - !_theResult____h368374[19] && - !_theResult____h368374[18] && - !_theResult____h368374[17] && - !_theResult____h368374[16] && - !_theResult____h368374[15] && - !_theResult____h368374[14] && - !_theResult____h368374[13] && - !_theResult____h368374[12] && - !_theResult____h368374[11] && - !_theResult____h368374[10] && - !_theResult____h368374[9] && - !_theResult____h368374[8] && - !_theResult____h368374[7] && - !_theResult____h368374[6] && - !_theResult____h368374[5] && - !_theResult____h368374[4] && - !_theResult____h368374[3] && - !_theResult____h368374[2] && - !_theResult____h368374[1] && - !_theResult____h368374[0]) ? - _theResult____h368374 : - _theResult___snd__h376652 ; - assign _theResult___snd__h376652 = + assign _theResult___snd__h376622 = { _theResult____h368373[55:0], 1'd0 } ; + assign _theResult___snd__h376633 = + (!_theResult____h368373[56] && _theResult____h368373[55]) ? + _theResult___snd__h376635 : + _theResult___snd__h376645 ; + assign _theResult___snd__h376635 = { _theResult____h368373[54:0], 2'd0 } ; + assign _theResult___snd__h376645 = + (!_theResult____h368373[56] && !_theResult____h368373[55] && + !_theResult____h368373[54] && + !_theResult____h368373[53] && + !_theResult____h368373[52] && + !_theResult____h368373[51] && + !_theResult____h368373[50] && + !_theResult____h368373[49] && + !_theResult____h368373[48] && + !_theResult____h368373[47] && + !_theResult____h368373[46] && + !_theResult____h368373[45] && + !_theResult____h368373[44] && + !_theResult____h368373[43] && + !_theResult____h368373[42] && + !_theResult____h368373[41] && + !_theResult____h368373[40] && + !_theResult____h368373[39] && + !_theResult____h368373[38] && + !_theResult____h368373[37] && + !_theResult____h368373[36] && + !_theResult____h368373[35] && + !_theResult____h368373[34] && + !_theResult____h368373[33] && + !_theResult____h368373[32] && + !_theResult____h368373[31] && + !_theResult____h368373[30] && + !_theResult____h368373[29] && + !_theResult____h368373[28] && + !_theResult____h368373[27] && + !_theResult____h368373[26] && + !_theResult____h368373[25] && + !_theResult____h368373[24] && + !_theResult____h368373[23] && + !_theResult____h368373[22] && + !_theResult____h368373[21] && + !_theResult____h368373[20] && + !_theResult____h368373[19] && + !_theResult____h368373[18] && + !_theResult____h368373[17] && + !_theResult____h368373[16] && + !_theResult____h368373[15] && + !_theResult____h368373[14] && + !_theResult____h368373[13] && + !_theResult____h368373[12] && + !_theResult____h368373[11] && + !_theResult____h368373[10] && + !_theResult____h368373[9] && + !_theResult____h368373[8] && + !_theResult____h368373[7] && + !_theResult____h368373[6] && + !_theResult____h368373[5] && + !_theResult____h368373[4] && + !_theResult____h368373[3] && + !_theResult____h368373[2] && + !_theResult____h368373[1] && + !_theResult____h368373[0]) ? + _theResult____h368373 : + _theResult___snd__h376651 ; + assign _theResult___snd__h376651 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31[54:0], 2'd0 } ; - assign _theResult___snd__h376675 = - _theResult____h368374 << + assign _theResult___snd__h376674 = + _theResult____h368373 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 ; - assign _theResult___snd__h385243 = + assign _theResult___snd__h385242 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h385257 : - _theResult___snd__h367455 ; - assign _theResult___snd__h385257 = + _theResult___snd__h385256 : + _theResult___snd__h367454 ; + assign _theResult___snd__h385256 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h343130 : - _theResult___snd__h385263 ; - assign _theResult___snd__h385263 = + sfd__h343129 : + _theResult___snd__h385262 ; + assign _theResult___snd__h385262 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36[54:0], 2'd0 } ; - assign _theResult___snd__h385281 = - sfd__h343130 << + assign _theResult___snd__h385280 = + sfd__h343129 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968) ; - assign _theResult___snd__h404554 = { _theResult____h396434[55:0], 1'd0 } ; - assign _theResult___snd__h404565 = - (!_theResult____h396434[56] && _theResult____h396434[55]) ? - _theResult___snd__h404567 : - _theResult___snd__h404577 ; - assign _theResult___snd__h404567 = { _theResult____h396434[54:0], 2'd0 } ; - assign _theResult___snd__h404577 = - (!_theResult____h396434[56] && !_theResult____h396434[55] && - !_theResult____h396434[54] && - !_theResult____h396434[53] && - !_theResult____h396434[52] && - !_theResult____h396434[51] && - !_theResult____h396434[50] && - !_theResult____h396434[49] && - !_theResult____h396434[48] && - !_theResult____h396434[47] && - !_theResult____h396434[46] && - !_theResult____h396434[45] && - !_theResult____h396434[44] && - !_theResult____h396434[43] && - !_theResult____h396434[42] && - !_theResult____h396434[41] && - !_theResult____h396434[40] && - !_theResult____h396434[39] && - !_theResult____h396434[38] && - !_theResult____h396434[37] && - !_theResult____h396434[36] && - !_theResult____h396434[35] && - !_theResult____h396434[34] && - !_theResult____h396434[33] && - !_theResult____h396434[32] && - !_theResult____h396434[31] && - !_theResult____h396434[30] && - !_theResult____h396434[29] && - !_theResult____h396434[28] && - !_theResult____h396434[27] && - !_theResult____h396434[26] && - !_theResult____h396434[25] && - !_theResult____h396434[24] && - !_theResult____h396434[23] && - !_theResult____h396434[22] && - !_theResult____h396434[21] && - !_theResult____h396434[20] && - !_theResult____h396434[19] && - !_theResult____h396434[18] && - !_theResult____h396434[17] && - !_theResult____h396434[16] && - !_theResult____h396434[15] && - !_theResult____h396434[14] && - !_theResult____h396434[13] && - !_theResult____h396434[12] && - !_theResult____h396434[11] && - !_theResult____h396434[10] && - !_theResult____h396434[9] && - !_theResult____h396434[8] && - !_theResult____h396434[7] && - !_theResult____h396434[6] && - !_theResult____h396434[5] && - !_theResult____h396434[4] && - !_theResult____h396434[3] && - !_theResult____h396434[2] && - !_theResult____h396434[1] && - !_theResult____h396434[0]) ? - _theResult____h396434 : - _theResult___snd__h404583 ; - assign _theResult___snd__h404583 = + assign _theResult___snd__h404553 = { _theResult____h396433[55:0], 1'd0 } ; + assign _theResult___snd__h404564 = + (!_theResult____h396433[56] && _theResult____h396433[55]) ? + _theResult___snd__h404566 : + _theResult___snd__h404576 ; + assign _theResult___snd__h404566 = { _theResult____h396433[54:0], 2'd0 } ; + assign _theResult___snd__h404576 = + (!_theResult____h396433[56] && !_theResult____h396433[55] && + !_theResult____h396433[54] && + !_theResult____h396433[53] && + !_theResult____h396433[52] && + !_theResult____h396433[51] && + !_theResult____h396433[50] && + !_theResult____h396433[49] && + !_theResult____h396433[48] && + !_theResult____h396433[47] && + !_theResult____h396433[46] && + !_theResult____h396433[45] && + !_theResult____h396433[44] && + !_theResult____h396433[43] && + !_theResult____h396433[42] && + !_theResult____h396433[41] && + !_theResult____h396433[40] && + !_theResult____h396433[39] && + !_theResult____h396433[38] && + !_theResult____h396433[37] && + !_theResult____h396433[36] && + !_theResult____h396433[35] && + !_theResult____h396433[34] && + !_theResult____h396433[33] && + !_theResult____h396433[32] && + !_theResult____h396433[31] && + !_theResult____h396433[30] && + !_theResult____h396433[29] && + !_theResult____h396433[28] && + !_theResult____h396433[27] && + !_theResult____h396433[26] && + !_theResult____h396433[25] && + !_theResult____h396433[24] && + !_theResult____h396433[23] && + !_theResult____h396433[22] && + !_theResult____h396433[21] && + !_theResult____h396433[20] && + !_theResult____h396433[19] && + !_theResult____h396433[18] && + !_theResult____h396433[17] && + !_theResult____h396433[16] && + !_theResult____h396433[15] && + !_theResult____h396433[14] && + !_theResult____h396433[13] && + !_theResult____h396433[12] && + !_theResult____h396433[11] && + !_theResult____h396433[10] && + !_theResult____h396433[9] && + !_theResult____h396433[8] && + !_theResult____h396433[7] && + !_theResult____h396433[6] && + !_theResult____h396433[5] && + !_theResult____h396433[4] && + !_theResult____h396433[3] && + !_theResult____h396433[2] && + !_theResult____h396433[1] && + !_theResult____h396433[0]) ? + _theResult____h396433 : + _theResult___snd__h404582 ; + assign _theResult___snd__h404582 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56[54:0], 2'd0 } ; - assign _theResult___snd__h404606 = - _theResult____h396434 << + assign _theResult___snd__h404605 = + _theResult____h396433 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 ; - assign _theResult___snd__h413150 = + assign _theResult___snd__h413149 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h413159 : - _theResult___snd__h413152 ; - assign _theResult___snd__h413152 = + _theResult___snd__h413158 : + _theResult___snd__h413151 ; + assign _theResult___snd__h413151 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h413159 = + assign _theResult___snd__h413158 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h388832 : - _theResult___snd__h413165 ; - assign _theResult___snd__h413165 = + sfd__h388831 : + _theResult___snd__h413164 ; + assign _theResult___snd__h413164 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58[54:0], 2'd0 } ; - assign _theResult___snd__h413188 = - sfd__h388832 << + assign _theResult___snd__h413187 = + sfd__h388831 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 ; - assign _theResult___snd__h422320 = { _theResult____h414071[55:0], 1'd0 } ; - assign _theResult___snd__h422331 = - (!_theResult____h414071[56] && _theResult____h414071[55]) ? - _theResult___snd__h422333 : - _theResult___snd__h422343 ; - assign _theResult___snd__h422333 = { _theResult____h414071[54:0], 2'd0 } ; - assign _theResult___snd__h422343 = - (!_theResult____h414071[56] && !_theResult____h414071[55] && - !_theResult____h414071[54] && - !_theResult____h414071[53] && - !_theResult____h414071[52] && - !_theResult____h414071[51] && - !_theResult____h414071[50] && - !_theResult____h414071[49] && - !_theResult____h414071[48] && - !_theResult____h414071[47] && - !_theResult____h414071[46] && - !_theResult____h414071[45] && - !_theResult____h414071[44] && - !_theResult____h414071[43] && - !_theResult____h414071[42] && - !_theResult____h414071[41] && - !_theResult____h414071[40] && - !_theResult____h414071[39] && - !_theResult____h414071[38] && - !_theResult____h414071[37] && - !_theResult____h414071[36] && - !_theResult____h414071[35] && - !_theResult____h414071[34] && - !_theResult____h414071[33] && - !_theResult____h414071[32] && - !_theResult____h414071[31] && - !_theResult____h414071[30] && - !_theResult____h414071[29] && - !_theResult____h414071[28] && - !_theResult____h414071[27] && - !_theResult____h414071[26] && - !_theResult____h414071[25] && - !_theResult____h414071[24] && - !_theResult____h414071[23] && - !_theResult____h414071[22] && - !_theResult____h414071[21] && - !_theResult____h414071[20] && - !_theResult____h414071[19] && - !_theResult____h414071[18] && - !_theResult____h414071[17] && - !_theResult____h414071[16] && - !_theResult____h414071[15] && - !_theResult____h414071[14] && - !_theResult____h414071[13] && - !_theResult____h414071[12] && - !_theResult____h414071[11] && - !_theResult____h414071[10] && - !_theResult____h414071[9] && - !_theResult____h414071[8] && - !_theResult____h414071[7] && - !_theResult____h414071[6] && - !_theResult____h414071[5] && - !_theResult____h414071[4] && - !_theResult____h414071[3] && - !_theResult____h414071[2] && - !_theResult____h414071[1] && - !_theResult____h414071[0]) ? - _theResult____h414071 : - _theResult___snd__h422349 ; - assign _theResult___snd__h422349 = + assign _theResult___snd__h422319 = { _theResult____h414070[55:0], 1'd0 } ; + assign _theResult___snd__h422330 = + (!_theResult____h414070[56] && _theResult____h414070[55]) ? + _theResult___snd__h422332 : + _theResult___snd__h422342 ; + assign _theResult___snd__h422332 = { _theResult____h414070[54:0], 2'd0 } ; + assign _theResult___snd__h422342 = + (!_theResult____h414070[56] && !_theResult____h414070[55] && + !_theResult____h414070[54] && + !_theResult____h414070[53] && + !_theResult____h414070[52] && + !_theResult____h414070[51] && + !_theResult____h414070[50] && + !_theResult____h414070[49] && + !_theResult____h414070[48] && + !_theResult____h414070[47] && + !_theResult____h414070[46] && + !_theResult____h414070[45] && + !_theResult____h414070[44] && + !_theResult____h414070[43] && + !_theResult____h414070[42] && + !_theResult____h414070[41] && + !_theResult____h414070[40] && + !_theResult____h414070[39] && + !_theResult____h414070[38] && + !_theResult____h414070[37] && + !_theResult____h414070[36] && + !_theResult____h414070[35] && + !_theResult____h414070[34] && + !_theResult____h414070[33] && + !_theResult____h414070[32] && + !_theResult____h414070[31] && + !_theResult____h414070[30] && + !_theResult____h414070[29] && + !_theResult____h414070[28] && + !_theResult____h414070[27] && + !_theResult____h414070[26] && + !_theResult____h414070[25] && + !_theResult____h414070[24] && + !_theResult____h414070[23] && + !_theResult____h414070[22] && + !_theResult____h414070[21] && + !_theResult____h414070[20] && + !_theResult____h414070[19] && + !_theResult____h414070[18] && + !_theResult____h414070[17] && + !_theResult____h414070[16] && + !_theResult____h414070[15] && + !_theResult____h414070[14] && + !_theResult____h414070[13] && + !_theResult____h414070[12] && + !_theResult____h414070[11] && + !_theResult____h414070[10] && + !_theResult____h414070[9] && + !_theResult____h414070[8] && + !_theResult____h414070[7] && + !_theResult____h414070[6] && + !_theResult____h414070[5] && + !_theResult____h414070[4] && + !_theResult____h414070[3] && + !_theResult____h414070[2] && + !_theResult____h414070[1] && + !_theResult____h414070[0]) ? + _theResult____h414070 : + _theResult___snd__h422348 ; + assign _theResult___snd__h422348 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66[54:0], 2'd0 } ; - assign _theResult___snd__h422372 = - _theResult____h414071 << + assign _theResult___snd__h422371 = + _theResult____h414070 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 ; - assign _theResult___snd__h430940 = + assign _theResult___snd__h430939 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h430954 : - _theResult___snd__h413152 ; - assign _theResult___snd__h430954 = + _theResult___snd__h430953 : + _theResult___snd__h413151 ; + assign _theResult___snd__h430953 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h388832 : - _theResult___snd__h430960 ; - assign _theResult___snd__h430960 = + sfd__h388831 : + _theResult___snd__h430959 ; + assign _theResult___snd__h430959 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71[54:0], 2'd0 } ; - assign _theResult___snd__h430978 = - sfd__h388832 << + assign _theResult___snd__h430977 = + sfd__h388831 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360) ; - assign _theResult___snd__h450249 = { _theResult____h442129[55:0], 1'd0 } ; - assign _theResult___snd__h450260 = - (!_theResult____h442129[56] && _theResult____h442129[55]) ? - _theResult___snd__h450262 : - _theResult___snd__h450272 ; - assign _theResult___snd__h450262 = { _theResult____h442129[54:0], 2'd0 } ; - assign _theResult___snd__h450272 = - (!_theResult____h442129[56] && !_theResult____h442129[55] && - !_theResult____h442129[54] && - !_theResult____h442129[53] && - !_theResult____h442129[52] && - !_theResult____h442129[51] && - !_theResult____h442129[50] && - !_theResult____h442129[49] && - !_theResult____h442129[48] && - !_theResult____h442129[47] && - !_theResult____h442129[46] && - !_theResult____h442129[45] && - !_theResult____h442129[44] && - !_theResult____h442129[43] && - !_theResult____h442129[42] && - !_theResult____h442129[41] && - !_theResult____h442129[40] && - !_theResult____h442129[39] && - !_theResult____h442129[38] && - !_theResult____h442129[37] && - !_theResult____h442129[36] && - !_theResult____h442129[35] && - !_theResult____h442129[34] && - !_theResult____h442129[33] && - !_theResult____h442129[32] && - !_theResult____h442129[31] && - !_theResult____h442129[30] && - !_theResult____h442129[29] && - !_theResult____h442129[28] && - !_theResult____h442129[27] && - !_theResult____h442129[26] && - !_theResult____h442129[25] && - !_theResult____h442129[24] && - !_theResult____h442129[23] && - !_theResult____h442129[22] && - !_theResult____h442129[21] && - !_theResult____h442129[20] && - !_theResult____h442129[19] && - !_theResult____h442129[18] && - !_theResult____h442129[17] && - !_theResult____h442129[16] && - !_theResult____h442129[15] && - !_theResult____h442129[14] && - !_theResult____h442129[13] && - !_theResult____h442129[12] && - !_theResult____h442129[11] && - !_theResult____h442129[10] && - !_theResult____h442129[9] && - !_theResult____h442129[8] && - !_theResult____h442129[7] && - !_theResult____h442129[6] && - !_theResult____h442129[5] && - !_theResult____h442129[4] && - !_theResult____h442129[3] && - !_theResult____h442129[2] && - !_theResult____h442129[1] && - !_theResult____h442129[0]) ? - _theResult____h442129 : - _theResult___snd__h450278 ; - assign _theResult___snd__h450278 = + assign _theResult___snd__h450248 = { _theResult____h442128[55:0], 1'd0 } ; + assign _theResult___snd__h450259 = + (!_theResult____h442128[56] && _theResult____h442128[55]) ? + _theResult___snd__h450261 : + _theResult___snd__h450271 ; + assign _theResult___snd__h450261 = { _theResult____h442128[54:0], 2'd0 } ; + assign _theResult___snd__h450271 = + (!_theResult____h442128[56] && !_theResult____h442128[55] && + !_theResult____h442128[54] && + !_theResult____h442128[53] && + !_theResult____h442128[52] && + !_theResult____h442128[51] && + !_theResult____h442128[50] && + !_theResult____h442128[49] && + !_theResult____h442128[48] && + !_theResult____h442128[47] && + !_theResult____h442128[46] && + !_theResult____h442128[45] && + !_theResult____h442128[44] && + !_theResult____h442128[43] && + !_theResult____h442128[42] && + !_theResult____h442128[41] && + !_theResult____h442128[40] && + !_theResult____h442128[39] && + !_theResult____h442128[38] && + !_theResult____h442128[37] && + !_theResult____h442128[36] && + !_theResult____h442128[35] && + !_theResult____h442128[34] && + !_theResult____h442128[33] && + !_theResult____h442128[32] && + !_theResult____h442128[31] && + !_theResult____h442128[30] && + !_theResult____h442128[29] && + !_theResult____h442128[28] && + !_theResult____h442128[27] && + !_theResult____h442128[26] && + !_theResult____h442128[25] && + !_theResult____h442128[24] && + !_theResult____h442128[23] && + !_theResult____h442128[22] && + !_theResult____h442128[21] && + !_theResult____h442128[20] && + !_theResult____h442128[19] && + !_theResult____h442128[18] && + !_theResult____h442128[17] && + !_theResult____h442128[16] && + !_theResult____h442128[15] && + !_theResult____h442128[14] && + !_theResult____h442128[13] && + !_theResult____h442128[12] && + !_theResult____h442128[11] && + !_theResult____h442128[10] && + !_theResult____h442128[9] && + !_theResult____h442128[8] && + !_theResult____h442128[7] && + !_theResult____h442128[6] && + !_theResult____h442128[5] && + !_theResult____h442128[4] && + !_theResult____h442128[3] && + !_theResult____h442128[2] && + !_theResult____h442128[1] && + !_theResult____h442128[0]) ? + _theResult____h442128 : + _theResult___snd__h450277 ; + assign _theResult___snd__h450277 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91[54:0], 2'd0 } ; - assign _theResult___snd__h450301 = - _theResult____h442129 << + assign _theResult___snd__h450300 = + _theResult____h442128 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 ; - assign _theResult___snd__h458845 = + assign _theResult___snd__h458844 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h458854 : - _theResult___snd__h458847 ; - assign _theResult___snd__h458847 = + _theResult___snd__h458853 : + _theResult___snd__h458846 ; + assign _theResult___snd__h458846 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h458854 = + assign _theResult___snd__h458853 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h434527 : - _theResult___snd__h458860 ; - assign _theResult___snd__h458860 = + sfd__h434526 : + _theResult___snd__h458859 ; + assign _theResult___snd__h458859 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93[54:0], 2'd0 } ; - assign _theResult___snd__h458883 = - sfd__h434527 << + assign _theResult___snd__h458882 = + sfd__h434526 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 ; - assign _theResult___snd__h468015 = { _theResult____h459766[55:0], 1'd0 } ; - assign _theResult___snd__h468026 = - (!_theResult____h459766[56] && _theResult____h459766[55]) ? - _theResult___snd__h468028 : - _theResult___snd__h468038 ; - assign _theResult___snd__h468028 = { _theResult____h459766[54:0], 2'd0 } ; - assign _theResult___snd__h468038 = - (!_theResult____h459766[56] && !_theResult____h459766[55] && - !_theResult____h459766[54] && - !_theResult____h459766[53] && - !_theResult____h459766[52] && - !_theResult____h459766[51] && - !_theResult____h459766[50] && - !_theResult____h459766[49] && - !_theResult____h459766[48] && - !_theResult____h459766[47] && - !_theResult____h459766[46] && - !_theResult____h459766[45] && - !_theResult____h459766[44] && - !_theResult____h459766[43] && - !_theResult____h459766[42] && - !_theResult____h459766[41] && - !_theResult____h459766[40] && - !_theResult____h459766[39] && - !_theResult____h459766[38] && - !_theResult____h459766[37] && - !_theResult____h459766[36] && - !_theResult____h459766[35] && - !_theResult____h459766[34] && - !_theResult____h459766[33] && - !_theResult____h459766[32] && - !_theResult____h459766[31] && - !_theResult____h459766[30] && - !_theResult____h459766[29] && - !_theResult____h459766[28] && - !_theResult____h459766[27] && - !_theResult____h459766[26] && - !_theResult____h459766[25] && - !_theResult____h459766[24] && - !_theResult____h459766[23] && - !_theResult____h459766[22] && - !_theResult____h459766[21] && - !_theResult____h459766[20] && - !_theResult____h459766[19] && - !_theResult____h459766[18] && - !_theResult____h459766[17] && - !_theResult____h459766[16] && - !_theResult____h459766[15] && - !_theResult____h459766[14] && - !_theResult____h459766[13] && - !_theResult____h459766[12] && - !_theResult____h459766[11] && - !_theResult____h459766[10] && - !_theResult____h459766[9] && - !_theResult____h459766[8] && - !_theResult____h459766[7] && - !_theResult____h459766[6] && - !_theResult____h459766[5] && - !_theResult____h459766[4] && - !_theResult____h459766[3] && - !_theResult____h459766[2] && - !_theResult____h459766[1] && - !_theResult____h459766[0]) ? - _theResult____h459766 : - _theResult___snd__h468044 ; - assign _theResult___snd__h468044 = + assign _theResult___snd__h468014 = { _theResult____h459765[55:0], 1'd0 } ; + assign _theResult___snd__h468025 = + (!_theResult____h459765[56] && _theResult____h459765[55]) ? + _theResult___snd__h468027 : + _theResult___snd__h468037 ; + assign _theResult___snd__h468027 = { _theResult____h459765[54:0], 2'd0 } ; + assign _theResult___snd__h468037 = + (!_theResult____h459765[56] && !_theResult____h459765[55] && + !_theResult____h459765[54] && + !_theResult____h459765[53] && + !_theResult____h459765[52] && + !_theResult____h459765[51] && + !_theResult____h459765[50] && + !_theResult____h459765[49] && + !_theResult____h459765[48] && + !_theResult____h459765[47] && + !_theResult____h459765[46] && + !_theResult____h459765[45] && + !_theResult____h459765[44] && + !_theResult____h459765[43] && + !_theResult____h459765[42] && + !_theResult____h459765[41] && + !_theResult____h459765[40] && + !_theResult____h459765[39] && + !_theResult____h459765[38] && + !_theResult____h459765[37] && + !_theResult____h459765[36] && + !_theResult____h459765[35] && + !_theResult____h459765[34] && + !_theResult____h459765[33] && + !_theResult____h459765[32] && + !_theResult____h459765[31] && + !_theResult____h459765[30] && + !_theResult____h459765[29] && + !_theResult____h459765[28] && + !_theResult____h459765[27] && + !_theResult____h459765[26] && + !_theResult____h459765[25] && + !_theResult____h459765[24] && + !_theResult____h459765[23] && + !_theResult____h459765[22] && + !_theResult____h459765[21] && + !_theResult____h459765[20] && + !_theResult____h459765[19] && + !_theResult____h459765[18] && + !_theResult____h459765[17] && + !_theResult____h459765[16] && + !_theResult____h459765[15] && + !_theResult____h459765[14] && + !_theResult____h459765[13] && + !_theResult____h459765[12] && + !_theResult____h459765[11] && + !_theResult____h459765[10] && + !_theResult____h459765[9] && + !_theResult____h459765[8] && + !_theResult____h459765[7] && + !_theResult____h459765[6] && + !_theResult____h459765[5] && + !_theResult____h459765[4] && + !_theResult____h459765[3] && + !_theResult____h459765[2] && + !_theResult____h459765[1] && + !_theResult____h459765[0]) ? + _theResult____h459765 : + _theResult___snd__h468043 ; + assign _theResult___snd__h468043 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101[54:0], 2'd0 } ; - assign _theResult___snd__h468067 = - _theResult____h459766 << + assign _theResult___snd__h468066 = + _theResult____h459765 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 ; - assign _theResult___snd__h476635 = + assign _theResult___snd__h476634 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h476649 : - _theResult___snd__h458847 ; - assign _theResult___snd__h476649 = + _theResult___snd__h476648 : + _theResult___snd__h458846 ; + assign _theResult___snd__h476648 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h434527 : - _theResult___snd__h476655 ; - assign _theResult___snd__h476655 = + sfd__h434526 : + _theResult___snd__h476654 ; + assign _theResult___snd__h476654 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106[54:0], 2'd0 } ; - assign _theResult___snd__h476673 = - sfd__h434527 << + assign _theResult___snd__h476672 = + sfd__h434526 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752) ; - assign _theResult___snd__h506865 = - (f1_exp__h487526 == 8'd0) ? - _theResult___snd__h506874 : - _theResult___snd__h506867 ; - assign _theResult___snd__h506867 = { f1_sfd__h487527, 34'd0 } ; - assign _theResult___snd__h506874 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___snd__h506864 = + (f1_exp__h487525 == 8'd0) ? + _theResult___snd__h506873 : + _theResult___snd__h506866 ; + assign _theResult___snd__h506866 = { f1_sfd__h487526, 34'd0 } ; + assign _theResult___snd__h506873 = + (f1_exp__h487525 == 8'd0 && !f1_sfd__h487526[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h487888 : - _theResult___snd__h506880 ; - assign _theResult___snd__h506880 = + sfd__h487887 : + _theResult___snd__h506879 ; + assign _theResult___snd__h506879 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h506903 = - sfd__h487888 << + assign _theResult___snd__h506902 = + sfd__h487887 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 ; - assign _theResult___snd__h516502 = { _theResult____h508255[55:0], 1'd0 } ; - assign _theResult___snd__h516513 = - (!_theResult____h508255[56] && _theResult____h508255[55]) ? - _theResult___snd__h516515 : - _theResult___snd__h516525 ; - assign _theResult___snd__h516515 = { _theResult____h508255[54:0], 2'd0 } ; - assign _theResult___snd__h516525 = - (!_theResult____h508255[56] && !_theResult____h508255[55] && - !_theResult____h508255[54] && - !_theResult____h508255[53] && - !_theResult____h508255[52] && - !_theResult____h508255[51] && - !_theResult____h508255[50] && - !_theResult____h508255[49] && - !_theResult____h508255[48] && - !_theResult____h508255[47] && - !_theResult____h508255[46] && - !_theResult____h508255[45] && - !_theResult____h508255[44] && - !_theResult____h508255[43] && - !_theResult____h508255[42] && - !_theResult____h508255[41] && - !_theResult____h508255[40] && - !_theResult____h508255[39] && - !_theResult____h508255[38] && - !_theResult____h508255[37] && - !_theResult____h508255[36] && - !_theResult____h508255[35] && - !_theResult____h508255[34] && - !_theResult____h508255[33] && - !_theResult____h508255[32] && - !_theResult____h508255[31] && - !_theResult____h508255[30] && - !_theResult____h508255[29] && - !_theResult____h508255[28] && - !_theResult____h508255[27] && - !_theResult____h508255[26] && - !_theResult____h508255[25] && - !_theResult____h508255[24] && - !_theResult____h508255[23] && - !_theResult____h508255[22] && - !_theResult____h508255[21] && - !_theResult____h508255[20] && - !_theResult____h508255[19] && - !_theResult____h508255[18] && - !_theResult____h508255[17] && - !_theResult____h508255[16] && - !_theResult____h508255[15] && - !_theResult____h508255[14] && - !_theResult____h508255[13] && - !_theResult____h508255[12] && - !_theResult____h508255[11] && - !_theResult____h508255[10] && - !_theResult____h508255[9] && - !_theResult____h508255[8] && - !_theResult____h508255[7] && - !_theResult____h508255[6] && - !_theResult____h508255[5] && - !_theResult____h508255[4] && - !_theResult____h508255[3] && - !_theResult____h508255[2] && - !_theResult____h508255[1] && - !_theResult____h508255[0]) ? - _theResult____h508255 : - _theResult___snd__h516531 ; - assign _theResult___snd__h516531 = + assign _theResult___snd__h516501 = { _theResult____h508254[55:0], 1'd0 } ; + assign _theResult___snd__h516512 = + (!_theResult____h508254[56] && _theResult____h508254[55]) ? + _theResult___snd__h516514 : + _theResult___snd__h516524 ; + assign _theResult___snd__h516514 = { _theResult____h508254[54:0], 2'd0 } ; + assign _theResult___snd__h516524 = + (!_theResult____h508254[56] && !_theResult____h508254[55] && + !_theResult____h508254[54] && + !_theResult____h508254[53] && + !_theResult____h508254[52] && + !_theResult____h508254[51] && + !_theResult____h508254[50] && + !_theResult____h508254[49] && + !_theResult____h508254[48] && + !_theResult____h508254[47] && + !_theResult____h508254[46] && + !_theResult____h508254[45] && + !_theResult____h508254[44] && + !_theResult____h508254[43] && + !_theResult____h508254[42] && + !_theResult____h508254[41] && + !_theResult____h508254[40] && + !_theResult____h508254[39] && + !_theResult____h508254[38] && + !_theResult____h508254[37] && + !_theResult____h508254[36] && + !_theResult____h508254[35] && + !_theResult____h508254[34] && + !_theResult____h508254[33] && + !_theResult____h508254[32] && + !_theResult____h508254[31] && + !_theResult____h508254[30] && + !_theResult____h508254[29] && + !_theResult____h508254[28] && + !_theResult____h508254[27] && + !_theResult____h508254[26] && + !_theResult____h508254[25] && + !_theResult____h508254[24] && + !_theResult____h508254[23] && + !_theResult____h508254[22] && + !_theResult____h508254[21] && + !_theResult____h508254[20] && + !_theResult____h508254[19] && + !_theResult____h508254[18] && + !_theResult____h508254[17] && + !_theResult____h508254[16] && + !_theResult____h508254[15] && + !_theResult____h508254[14] && + !_theResult____h508254[13] && + !_theResult____h508254[12] && + !_theResult____h508254[11] && + !_theResult____h508254[10] && + !_theResult____h508254[9] && + !_theResult____h508254[8] && + !_theResult____h508254[7] && + !_theResult____h508254[6] && + !_theResult____h508254[5] && + !_theResult____h508254[4] && + !_theResult____h508254[3] && + !_theResult____h508254[2] && + !_theResult____h508254[1] && + !_theResult____h508254[0]) ? + _theResult____h508254 : + _theResult___snd__h516530 ; + assign _theResult___snd__h516530 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h516554 = - _theResult____h508255 << + assign _theResult___snd__h516553 = + _theResult____h508254 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 ; - assign _theResult___snd__h525270 = - (f1_exp__h487526 == 8'd0) ? - _theResult___snd__h525284 : - _theResult___snd__h506867 ; - assign _theResult___snd__h525284 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___snd__h525269 = + (f1_exp__h487525 == 8'd0) ? + _theResult___snd__h525283 : + _theResult___snd__h506866 ; + assign _theResult___snd__h525283 = + (f1_exp__h487525 == 8'd0 && !f1_sfd__h487526[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h487888 : - _theResult___snd__h525290 ; - assign _theResult___snd__h525290 = + sfd__h487887 : + _theResult___snd__h525289 ; + assign _theResult___snd__h525289 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h525308 = - sfd__h487888 << + assign _theResult___snd__h525307 = + sfd__h487887 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 ; - assign _theResult___snd__h545718 = - (f2_exp__h526520 == 8'd0) ? - _theResult___snd__h545727 : - _theResult___snd__h545720 ; - assign _theResult___snd__h545720 = { f2_sfd__h526521, 34'd0 } ; - assign _theResult___snd__h545727 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___snd__h545717 = + (f2_exp__h526519 == 8'd0) ? + _theResult___snd__h545726 : + _theResult___snd__h545719 ; + assign _theResult___snd__h545719 = { f2_sfd__h526520, 34'd0 } ; + assign _theResult___snd__h545726 = + (f2_exp__h526519 == 8'd0 && !f2_sfd__h526520[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h526882 : - _theResult___snd__h545733 ; - assign _theResult___snd__h545733 = + sfd__h526881 : + _theResult___snd__h545732 ; + assign _theResult___snd__h545732 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h545756 = - sfd__h526882 << + assign _theResult___snd__h545755 = + sfd__h526881 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 ; - assign _theResult___snd__h555355 = { _theResult____h547108[55:0], 1'd0 } ; - assign _theResult___snd__h555366 = - (!_theResult____h547108[56] && _theResult____h547108[55]) ? - _theResult___snd__h555368 : - _theResult___snd__h555378 ; - assign _theResult___snd__h555368 = { _theResult____h547108[54:0], 2'd0 } ; - assign _theResult___snd__h555378 = - (!_theResult____h547108[56] && !_theResult____h547108[55] && - !_theResult____h547108[54] && - !_theResult____h547108[53] && - !_theResult____h547108[52] && - !_theResult____h547108[51] && - !_theResult____h547108[50] && - !_theResult____h547108[49] && - !_theResult____h547108[48] && - !_theResult____h547108[47] && - !_theResult____h547108[46] && - !_theResult____h547108[45] && - !_theResult____h547108[44] && - !_theResult____h547108[43] && - !_theResult____h547108[42] && - !_theResult____h547108[41] && - !_theResult____h547108[40] && - !_theResult____h547108[39] && - !_theResult____h547108[38] && - !_theResult____h547108[37] && - !_theResult____h547108[36] && - !_theResult____h547108[35] && - !_theResult____h547108[34] && - !_theResult____h547108[33] && - !_theResult____h547108[32] && - !_theResult____h547108[31] && - !_theResult____h547108[30] && - !_theResult____h547108[29] && - !_theResult____h547108[28] && - !_theResult____h547108[27] && - !_theResult____h547108[26] && - !_theResult____h547108[25] && - !_theResult____h547108[24] && - !_theResult____h547108[23] && - !_theResult____h547108[22] && - !_theResult____h547108[21] && - !_theResult____h547108[20] && - !_theResult____h547108[19] && - !_theResult____h547108[18] && - !_theResult____h547108[17] && - !_theResult____h547108[16] && - !_theResult____h547108[15] && - !_theResult____h547108[14] && - !_theResult____h547108[13] && - !_theResult____h547108[12] && - !_theResult____h547108[11] && - !_theResult____h547108[10] && - !_theResult____h547108[9] && - !_theResult____h547108[8] && - !_theResult____h547108[7] && - !_theResult____h547108[6] && - !_theResult____h547108[5] && - !_theResult____h547108[4] && - !_theResult____h547108[3] && - !_theResult____h547108[2] && - !_theResult____h547108[1] && - !_theResult____h547108[0]) ? - _theResult____h547108 : - _theResult___snd__h555384 ; - assign _theResult___snd__h555384 = + assign _theResult___snd__h555354 = { _theResult____h547107[55:0], 1'd0 } ; + assign _theResult___snd__h555365 = + (!_theResult____h547107[56] && _theResult____h547107[55]) ? + _theResult___snd__h555367 : + _theResult___snd__h555377 ; + assign _theResult___snd__h555367 = { _theResult____h547107[54:0], 2'd0 } ; + assign _theResult___snd__h555377 = + (!_theResult____h547107[56] && !_theResult____h547107[55] && + !_theResult____h547107[54] && + !_theResult____h547107[53] && + !_theResult____h547107[52] && + !_theResult____h547107[51] && + !_theResult____h547107[50] && + !_theResult____h547107[49] && + !_theResult____h547107[48] && + !_theResult____h547107[47] && + !_theResult____h547107[46] && + !_theResult____h547107[45] && + !_theResult____h547107[44] && + !_theResult____h547107[43] && + !_theResult____h547107[42] && + !_theResult____h547107[41] && + !_theResult____h547107[40] && + !_theResult____h547107[39] && + !_theResult____h547107[38] && + !_theResult____h547107[37] && + !_theResult____h547107[36] && + !_theResult____h547107[35] && + !_theResult____h547107[34] && + !_theResult____h547107[33] && + !_theResult____h547107[32] && + !_theResult____h547107[31] && + !_theResult____h547107[30] && + !_theResult____h547107[29] && + !_theResult____h547107[28] && + !_theResult____h547107[27] && + !_theResult____h547107[26] && + !_theResult____h547107[25] && + !_theResult____h547107[24] && + !_theResult____h547107[23] && + !_theResult____h547107[22] && + !_theResult____h547107[21] && + !_theResult____h547107[20] && + !_theResult____h547107[19] && + !_theResult____h547107[18] && + !_theResult____h547107[17] && + !_theResult____h547107[16] && + !_theResult____h547107[15] && + !_theResult____h547107[14] && + !_theResult____h547107[13] && + !_theResult____h547107[12] && + !_theResult____h547107[11] && + !_theResult____h547107[10] && + !_theResult____h547107[9] && + !_theResult____h547107[8] && + !_theResult____h547107[7] && + !_theResult____h547107[6] && + !_theResult____h547107[5] && + !_theResult____h547107[4] && + !_theResult____h547107[3] && + !_theResult____h547107[2] && + !_theResult____h547107[1] && + !_theResult____h547107[0]) ? + _theResult____h547107 : + _theResult___snd__h555383 ; + assign _theResult___snd__h555383 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h555407 = - _theResult____h547108 << + assign _theResult___snd__h555406 = + _theResult____h547107 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 ; - assign _theResult___snd__h564123 = - (f2_exp__h526520 == 8'd0) ? - _theResult___snd__h564137 : - _theResult___snd__h545720 ; - assign _theResult___snd__h564137 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___snd__h564122 = + (f2_exp__h526519 == 8'd0) ? + _theResult___snd__h564136 : + _theResult___snd__h545719 ; + assign _theResult___snd__h564136 = + (f2_exp__h526519 == 8'd0 && !f2_sfd__h526520[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h526882 : - _theResult___snd__h564143 ; - assign _theResult___snd__h564143 = + sfd__h526881 : + _theResult___snd__h564142 ; + assign _theResult___snd__h564142 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h564161 = - sfd__h526882 << + assign _theResult___snd__h564160 = + sfd__h526881 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 ; - assign _theResult___snd__h585022 = - (f3_exp__h565824 == 8'd0) ? - _theResult___snd__h585031 : - _theResult___snd__h585024 ; - assign _theResult___snd__h585024 = { f3_sfd__h565825, 34'd0 } ; - assign _theResult___snd__h585031 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___snd__h585021 = + (f3_exp__h565823 == 8'd0) ? + _theResult___snd__h585030 : + _theResult___snd__h585023 ; + assign _theResult___snd__h585023 = { f3_sfd__h565824, 34'd0 } ; + assign _theResult___snd__h585030 = + (f3_exp__h565823 == 8'd0 && !f3_sfd__h565824[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h566186 : - _theResult___snd__h585037 ; - assign _theResult___snd__h585037 = + sfd__h566185 : + _theResult___snd__h585036 ; + assign _theResult___snd__h585036 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h585060 = - sfd__h566186 << + assign _theResult___snd__h585059 = + sfd__h566185 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 ; - assign _theResult___snd__h594659 = { _theResult____h586412[55:0], 1'd0 } ; - assign _theResult___snd__h594670 = - (!_theResult____h586412[56] && _theResult____h586412[55]) ? - _theResult___snd__h594672 : - _theResult___snd__h594682 ; - assign _theResult___snd__h594672 = { _theResult____h586412[54:0], 2'd0 } ; - assign _theResult___snd__h594682 = - (!_theResult____h586412[56] && !_theResult____h586412[55] && - !_theResult____h586412[54] && - !_theResult____h586412[53] && - !_theResult____h586412[52] && - !_theResult____h586412[51] && - !_theResult____h586412[50] && - !_theResult____h586412[49] && - !_theResult____h586412[48] && - !_theResult____h586412[47] && - !_theResult____h586412[46] && - !_theResult____h586412[45] && - !_theResult____h586412[44] && - !_theResult____h586412[43] && - !_theResult____h586412[42] && - !_theResult____h586412[41] && - !_theResult____h586412[40] && - !_theResult____h586412[39] && - !_theResult____h586412[38] && - !_theResult____h586412[37] && - !_theResult____h586412[36] && - !_theResult____h586412[35] && - !_theResult____h586412[34] && - !_theResult____h586412[33] && - !_theResult____h586412[32] && - !_theResult____h586412[31] && - !_theResult____h586412[30] && - !_theResult____h586412[29] && - !_theResult____h586412[28] && - !_theResult____h586412[27] && - !_theResult____h586412[26] && - !_theResult____h586412[25] && - !_theResult____h586412[24] && - !_theResult____h586412[23] && - !_theResult____h586412[22] && - !_theResult____h586412[21] && - !_theResult____h586412[20] && - !_theResult____h586412[19] && - !_theResult____h586412[18] && - !_theResult____h586412[17] && - !_theResult____h586412[16] && - !_theResult____h586412[15] && - !_theResult____h586412[14] && - !_theResult____h586412[13] && - !_theResult____h586412[12] && - !_theResult____h586412[11] && - !_theResult____h586412[10] && - !_theResult____h586412[9] && - !_theResult____h586412[8] && - !_theResult____h586412[7] && - !_theResult____h586412[6] && - !_theResult____h586412[5] && - !_theResult____h586412[4] && - !_theResult____h586412[3] && - !_theResult____h586412[2] && - !_theResult____h586412[1] && - !_theResult____h586412[0]) ? - _theResult____h586412 : - _theResult___snd__h594688 ; - assign _theResult___snd__h594688 = + assign _theResult___snd__h594658 = { _theResult____h586411[55:0], 1'd0 } ; + assign _theResult___snd__h594669 = + (!_theResult____h586411[56] && _theResult____h586411[55]) ? + _theResult___snd__h594671 : + _theResult___snd__h594681 ; + assign _theResult___snd__h594671 = { _theResult____h586411[54:0], 2'd0 } ; + assign _theResult___snd__h594681 = + (!_theResult____h586411[56] && !_theResult____h586411[55] && + !_theResult____h586411[54] && + !_theResult____h586411[53] && + !_theResult____h586411[52] && + !_theResult____h586411[51] && + !_theResult____h586411[50] && + !_theResult____h586411[49] && + !_theResult____h586411[48] && + !_theResult____h586411[47] && + !_theResult____h586411[46] && + !_theResult____h586411[45] && + !_theResult____h586411[44] && + !_theResult____h586411[43] && + !_theResult____h586411[42] && + !_theResult____h586411[41] && + !_theResult____h586411[40] && + !_theResult____h586411[39] && + !_theResult____h586411[38] && + !_theResult____h586411[37] && + !_theResult____h586411[36] && + !_theResult____h586411[35] && + !_theResult____h586411[34] && + !_theResult____h586411[33] && + !_theResult____h586411[32] && + !_theResult____h586411[31] && + !_theResult____h586411[30] && + !_theResult____h586411[29] && + !_theResult____h586411[28] && + !_theResult____h586411[27] && + !_theResult____h586411[26] && + !_theResult____h586411[25] && + !_theResult____h586411[24] && + !_theResult____h586411[23] && + !_theResult____h586411[22] && + !_theResult____h586411[21] && + !_theResult____h586411[20] && + !_theResult____h586411[19] && + !_theResult____h586411[18] && + !_theResult____h586411[17] && + !_theResult____h586411[16] && + !_theResult____h586411[15] && + !_theResult____h586411[14] && + !_theResult____h586411[13] && + !_theResult____h586411[12] && + !_theResult____h586411[11] && + !_theResult____h586411[10] && + !_theResult____h586411[9] && + !_theResult____h586411[8] && + !_theResult____h586411[7] && + !_theResult____h586411[6] && + !_theResult____h586411[5] && + !_theResult____h586411[4] && + !_theResult____h586411[3] && + !_theResult____h586411[2] && + !_theResult____h586411[1] && + !_theResult____h586411[0]) ? + _theResult____h586411 : + _theResult___snd__h594687 ; + assign _theResult___snd__h594687 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h594711 = - _theResult____h586412 << + assign _theResult___snd__h594710 = + _theResult____h586411 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 ; - assign _theResult___snd__h603427 = - (f3_exp__h565824 == 8'd0) ? - _theResult___snd__h603441 : - _theResult___snd__h585024 ; - assign _theResult___snd__h603441 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___snd__h603426 = + (f3_exp__h565823 == 8'd0) ? + _theResult___snd__h603440 : + _theResult___snd__h585023 ; + assign _theResult___snd__h603440 = + (f3_exp__h565823 == 8'd0 && !f3_sfd__h565824[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h566186 : - _theResult___snd__h603447 ; - assign _theResult___snd__h603447 = + sfd__h566185 : + _theResult___snd__h603446 ; + assign _theResult___snd__h603446 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h603465 = - sfd__h566186 << + assign _theResult___snd__h603464 = + sfd__h566185 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 ; - assign _theResult___snd__h608921 = - b__h608373[63] ? b___1__h608986 : b__h608373 ; - assign _theResult___snd_fst_exp__h368028 = + assign _theResult___snd__h608920 = + b__h608372[63] ? b___1__h608985 : b__h608372 ; + assign _theResult___snd_fst_exp__h368027 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_exp__h359443 : - _theResult___fst_exp__h368025 ; - assign _theResult___snd_fst_exp__h385848 = + _theResult___fst_exp__h359442 : + _theResult___fst_exp__h368024 ; + assign _theResult___snd_fst_exp__h385847 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_exp__h377209 : - _theResult___fst_exp__h385845 ; - assign _theResult___snd_fst_exp__h413725 = + _theResult___fst_exp__h377208 : + _theResult___fst_exp__h385844 ; + assign _theResult___snd_fst_exp__h413724 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_exp__h405140 : - _theResult___fst_exp__h413722 ; - assign _theResult___snd_fst_exp__h431545 = + _theResult___fst_exp__h405139 : + _theResult___fst_exp__h413721 ; + assign _theResult___snd_fst_exp__h431544 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_exp__h422906 : - _theResult___fst_exp__h431542 ; - assign _theResult___snd_fst_exp__h459420 = + _theResult___fst_exp__h422905 : + _theResult___fst_exp__h431541 ; + assign _theResult___snd_fst_exp__h459419 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_exp__h450835 : - _theResult___fst_exp__h459417 ; - assign _theResult___snd_fst_exp__h477240 = + _theResult___fst_exp__h450834 : + _theResult___fst_exp__h459416 ; + assign _theResult___snd_fst_exp__h477239 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_exp__h468601 : - _theResult___fst_exp__h477237 ; - assign _theResult___snd_fst_exp__h507675 = + _theResult___fst_exp__h468600 : + _theResult___fst_exp__h477236 ; + assign _theResult___snd_fst_exp__h507674 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 11'd0 : - _theResult___fst_exp__h507672 ; - assign _theResult___snd_fst_exp__h526110 = + _theResult___fst_exp__h507671 ; + assign _theResult___snd_fst_exp__h526109 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_exp__h517323 : - _theResult___fst_exp__h526107 ; - assign _theResult___snd_fst_exp__h546528 = + _theResult___fst_exp__h517322 : + _theResult___fst_exp__h526106 ; + assign _theResult___snd_fst_exp__h546527 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 11'd0 : - _theResult___fst_exp__h546525 ; - assign _theResult___snd_fst_exp__h564963 = + _theResult___fst_exp__h546524 ; + assign _theResult___snd_fst_exp__h564962 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_exp__h556176 : - _theResult___fst_exp__h564960 ; - assign _theResult___snd_fst_exp__h585832 = + _theResult___fst_exp__h556175 : + _theResult___fst_exp__h564959 ; + assign _theResult___snd_fst_exp__h585831 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 11'd0 : - _theResult___fst_exp__h585829 ; - assign _theResult___snd_fst_exp__h604267 = + _theResult___fst_exp__h585828 ; + assign _theResult___snd_fst_exp__h604266 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_exp__h595480 : - _theResult___fst_exp__h604264 ; - assign _theResult___snd_fst_sfd__h343080 = + _theResult___fst_exp__h595479 : + _theResult___fst_exp__h604263 ; + assign _theResult___snd_fst_sfd__h343079 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h368029 = + assign _theResult___snd_fst_sfd__h368028 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_sfd__h359444 : - _theResult___fst_sfd__h368026 ; - assign _theResult___snd_fst_sfd__h385849 = + _theResult___fst_sfd__h359443 : + _theResult___fst_sfd__h368025 ; + assign _theResult___snd_fst_sfd__h385848 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_sfd__h377210 : - _theResult___fst_sfd__h385846 ; - assign _theResult___snd_fst_sfd__h388782 = + _theResult___fst_sfd__h377209 : + _theResult___fst_sfd__h385845 ; + assign _theResult___snd_fst_sfd__h388781 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h413726 = + assign _theResult___snd_fst_sfd__h413725 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_sfd__h405141 : - _theResult___fst_sfd__h413723 ; - assign _theResult___snd_fst_sfd__h431546 = + _theResult___fst_sfd__h405140 : + _theResult___fst_sfd__h413722 ; + assign _theResult___snd_fst_sfd__h431545 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_sfd__h422907 : - _theResult___fst_sfd__h431543 ; - assign _theResult___snd_fst_sfd__h434477 = + _theResult___fst_sfd__h422906 : + _theResult___fst_sfd__h431542 ; + assign _theResult___snd_fst_sfd__h434476 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h459421 = + assign _theResult___snd_fst_sfd__h459420 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_sfd__h450836 : - _theResult___fst_sfd__h459418 ; - assign _theResult___snd_fst_sfd__h477241 = + _theResult___fst_sfd__h450835 : + _theResult___fst_sfd__h459417 ; + assign _theResult___snd_fst_sfd__h477240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_sfd__h468602 : - _theResult___fst_sfd__h477238 ; - assign _theResult___snd_fst_sfd__h487842 = - (f1_sfd__h487527 == 23'd0) ? + _theResult___fst_sfd__h468601 : + _theResult___fst_sfd__h477237 ; + assign _theResult___snd_fst_sfd__h487841 = + (f1_sfd__h487526 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h487590 ; - assign _theResult___snd_fst_sfd__h507676 = + out___1_sfd__h487589 ; + assign _theResult___snd_fst_sfd__h507675 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 52'd0 : - _theResult___fst_sfd__h507673 ; - assign _theResult___snd_fst_sfd__h526111 = + _theResult___fst_sfd__h507672 ; + assign _theResult___snd_fst_sfd__h526110 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_sfd__h517324 : - _theResult___fst_sfd__h526108 ; - assign _theResult___snd_fst_sfd__h526836 = - (f2_sfd__h526521 == 23'd0) ? + _theResult___fst_sfd__h517323 : + _theResult___fst_sfd__h526107 ; + assign _theResult___snd_fst_sfd__h526835 = + (f2_sfd__h526520 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h526584 ; - assign _theResult___snd_fst_sfd__h546529 = + out___1_sfd__h526583 ; + assign _theResult___snd_fst_sfd__h546528 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 52'd0 : - _theResult___fst_sfd__h546526 ; - assign _theResult___snd_fst_sfd__h564964 = + _theResult___fst_sfd__h546525 ; + assign _theResult___snd_fst_sfd__h564963 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_sfd__h556177 : - _theResult___fst_sfd__h564961 ; - assign _theResult___snd_fst_sfd__h566140 = - (f3_sfd__h565825 == 23'd0) ? + _theResult___fst_sfd__h556176 : + _theResult___fst_sfd__h564960 ; + assign _theResult___snd_fst_sfd__h566139 = + (f3_sfd__h565824 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h565888 ; - assign _theResult___snd_fst_sfd__h585833 = + out___1_sfd__h565887 ; + assign _theResult___snd_fst_sfd__h585832 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 52'd0 : - _theResult___fst_sfd__h585830 ; - assign _theResult___snd_fst_sfd__h604268 = + _theResult___fst_sfd__h585829 ; + assign _theResult___snd_fst_sfd__h604267 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_sfd__h595481 : - _theResult___fst_sfd__h604265 ; - assign a___1__h608534 = + _theResult___fst_sfd__h595480 : + _theResult___fst_sfd__h604264 ; + assign a___1__h608533 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 } ; - assign a___1__h608925 = 64'd0 - a__h608372 ; - assign a__h608372 = + assign a___1__h608924 = 64'd0 - a__h608371 ; + assign a__h608371 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h608534 : + a___1__h608533 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h608535 = + assign b___1__h608534 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h608986 = 64'd0 - b__h608373 ; - assign b__h608373 = + assign b___1__h608985 = 64'd0 - b__h608372 ; + assign b__h608372 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h608535 : + b___1__h608534 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h608520 = { {64{a__h608372[63]}}, a__h608372 } ; - assign b__h608596 = { {64{b__h608373[63]}}, b__h608373 } ; - assign b__h608697 = { 64'd0, a__h608372 } ; - assign b__h608709 = { 64'd0, b__h608373 } ; + assign b__h608519 = { {64{a__h608371[63]}}, a__h608371 } ; + assign b__h608595 = { {64{b__h608372[63]}}, b__h608372 } ; + assign b__h608696 = { 64'd0, a__h608371 } ; + assign b__h608708 = { 64'd0, b__h608372 } ; assign base__h710680 = { csrf_stvec_base_hi_reg, 2'b0 } ; assign base__h710700 = { csrf_mtvec_base_hi_reg, 2'b0 } ; assign cause_code__h707757 = @@ -27776,9 +27759,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565823 != 8'd255 || f3_sfd__h565824 == 23'd0) && + (f3_exp__h565823 != 8'd255 || f3_sfd__h565824 != 23'd0) && + (f3_exp__h565823 != 8'd0 || f3_sfd__h565824 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27786,9 +27769,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565823 != 8'd255 || f3_sfd__h565824 == 23'd0) && + (f3_exp__h565823 != 8'd255 || f3_sfd__h565824 != 23'd0) && + (f3_exp__h565823 != 8'd0 || f3_sfd__h565824 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27796,9 +27779,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565823 != 8'd255 || f3_sfd__h565824 == 23'd0) && + (f3_exp__h565823 != 8'd255 || f3_sfd__h565824 != 23'd0) && + (f3_exp__h565823 != 8'd0 || f3_sfd__h565824 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27806,9 +27789,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565823 != 8'd255 || f3_sfd__h565824 == 23'd0) && + (f3_exp__h565823 != 8'd255 || f3_sfd__h565824 != 23'd0) && + (f3_exp__h565823 != 8'd0 || f3_sfd__h565824 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27816,9 +27799,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565823 != 8'd255 || f3_sfd__h565824 == 23'd0) && + (f3_exp__h565823 != 8'd255 || f3_sfd__h565824 != 23'd0) && + (f3_exp__h565823 != 8'd0 || f3_sfd__h565824 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -27864,7 +27847,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h258434 ; + y__h258433 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 || @@ -28217,13 +28200,13 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_full ; assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14778 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__4451_BITS_257_TO_2_ETC___d14773 ; - assign csr_addr__h661836 = + assign csr_addr__h661834 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 : 12'hCFF ; @@ -28248,7 +28231,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 || csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 || - csr_addr__h661836 == 12'h8FF) ; + csr_addr__h661834 == 12'h8FF) ; assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13605 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -28280,90 +28263,90 @@ module mkCore(CLK, _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14629) ; assign csrf_prv_reg_read__2956_ULE_1___d14592 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 = - csrf_prv_reg < csr_addr__h661836[9:8] ; - assign data79261_BITS_31_TO_0__q2 = data__h479261[31:0] ; - assign data80193_BITS_31_TO_0__q6 = data__h480193[31:0] ; - assign data___1__h479773 = - { {32{data79261_BITS_31_TO_0__q2[31]}}, - data79261_BITS_31_TO_0__q2 } ; - assign data___1__h480705 = - { {32{data80193_BITS_31_TO_0__q6[31]}}, - data80193_BITS_31_TO_0__q6 } ; - assign data__h479261 = + csrf_prv_reg < csr_addr__h661834[9:8] ; + assign data79260_BITS_31_TO_0__q2 = data__h479260[31:0] ; + assign data80192_BITS_31_TO_0__q6 = data__h480192[31:0] ; + assign data___1__h479772 = + { {32{data79260_BITS_31_TO_0__q2[31]}}, + data79260_BITS_31_TO_0__q2 } ; + assign data___1__h480704 = + { {32{data80192_BITS_31_TO_0__q6[31]}}, + data80192_BITS_31_TO_0__q6 } ; + assign data__h479260 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h480193 = + assign data__h480192 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h479957 : - x_remainder__h479958 ; - assign din_inc___2_exp__h385879 = _theResult___fst_exp__h358846 + 8'd1 ; - assign din_inc___2_exp__h385903 = _theResult___fst_exp__h367502 + 8'd1 ; - assign din_inc___2_exp__h385933 = _theResult___fst_exp__h376612 + 8'd1 ; - assign din_inc___2_exp__h385957 = _theResult___fst_exp__h385297 + 8'd1 ; - assign din_inc___2_exp__h431576 = _theResult___fst_exp__h404543 + 8'd1 ; - assign din_inc___2_exp__h431600 = _theResult___fst_exp__h413199 + 8'd1 ; - assign din_inc___2_exp__h431630 = _theResult___fst_exp__h422309 + 8'd1 ; - assign din_inc___2_exp__h431654 = _theResult___fst_exp__h430994 + 8'd1 ; - assign din_inc___2_exp__h477271 = _theResult___fst_exp__h450238 + 8'd1 ; - assign din_inc___2_exp__h477295 = _theResult___fst_exp__h458894 + 8'd1 ; - assign din_inc___2_exp__h477325 = _theResult___fst_exp__h468004 + 8'd1 ; - assign din_inc___2_exp__h477349 = _theResult___fst_exp__h476689 + 8'd1 ; - assign din_inc___2_exp__h526164 = _theResult___fst_exp__h506914 + 11'd1 ; - assign din_inc___2_exp__h526199 = _theResult___fst_exp__h516491 + 11'd1 ; - assign din_inc___2_exp__h526225 = _theResult___fst_exp__h525324 + 11'd1 ; - assign din_inc___2_exp__h565017 = _theResult___fst_exp__h545767 + 11'd1 ; - assign din_inc___2_exp__h565052 = _theResult___fst_exp__h555344 + 11'd1 ; - assign din_inc___2_exp__h565078 = _theResult___fst_exp__h564177 + 11'd1 ; - assign din_inc___2_exp__h604321 = _theResult___fst_exp__h585071 + 11'd1 ; - assign din_inc___2_exp__h604356 = _theResult___fst_exp__h594648 + 11'd1 ; - assign din_inc___2_exp__h604382 = _theResult___fst_exp__h603481 + 11'd1 ; - assign enabled_ints___1__h658440 = pend_ints__h658025 & y__h658452 ; - assign enabled_ints__h658486 = - pend_ints__h658025 & - { r1__read_BITS_9_TO_0___h658462, csrf_mideleg_1_0_reg } ; - assign f1_exp87526_MINUS_127__q128 = f1_exp__h487526 - 8'd127 ; - assign f1_exp__h487526 = + x_quotient__h479956 : + x_remainder__h479957 ; + assign din_inc___2_exp__h385878 = _theResult___fst_exp__h358845 + 8'd1 ; + assign din_inc___2_exp__h385902 = _theResult___fst_exp__h367501 + 8'd1 ; + assign din_inc___2_exp__h385932 = _theResult___fst_exp__h376611 + 8'd1 ; + assign din_inc___2_exp__h385956 = _theResult___fst_exp__h385296 + 8'd1 ; + assign din_inc___2_exp__h431575 = _theResult___fst_exp__h404542 + 8'd1 ; + assign din_inc___2_exp__h431599 = _theResult___fst_exp__h413198 + 8'd1 ; + assign din_inc___2_exp__h431629 = _theResult___fst_exp__h422308 + 8'd1 ; + assign din_inc___2_exp__h431653 = _theResult___fst_exp__h430993 + 8'd1 ; + assign din_inc___2_exp__h477270 = _theResult___fst_exp__h450237 + 8'd1 ; + assign din_inc___2_exp__h477294 = _theResult___fst_exp__h458893 + 8'd1 ; + assign din_inc___2_exp__h477324 = _theResult___fst_exp__h468003 + 8'd1 ; + assign din_inc___2_exp__h477348 = _theResult___fst_exp__h476688 + 8'd1 ; + assign din_inc___2_exp__h526163 = _theResult___fst_exp__h506913 + 11'd1 ; + assign din_inc___2_exp__h526198 = _theResult___fst_exp__h516490 + 11'd1 ; + assign din_inc___2_exp__h526224 = _theResult___fst_exp__h525323 + 11'd1 ; + assign din_inc___2_exp__h565016 = _theResult___fst_exp__h545766 + 11'd1 ; + assign din_inc___2_exp__h565051 = _theResult___fst_exp__h555343 + 11'd1 ; + assign din_inc___2_exp__h565077 = _theResult___fst_exp__h564176 + 11'd1 ; + assign din_inc___2_exp__h604320 = _theResult___fst_exp__h585070 + 11'd1 ; + assign din_inc___2_exp__h604355 = _theResult___fst_exp__h594647 + 11'd1 ; + assign din_inc___2_exp__h604381 = _theResult___fst_exp__h603480 + 11'd1 ; + assign enabled_ints___1__h658438 = pend_ints__h658023 & y__h658450 ; + assign enabled_ints__h658484 = + pend_ints__h658023 & + { r1__read_BITS_9_TO_0___h658460, csrf_mideleg_1_0_reg } ; + assign f1_exp87525_MINUS_127__q128 = f1_exp__h487525 - 8'd127 ; + assign f1_exp__h487525 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h487527 = + assign f1_sfd__h487526 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp26520_MINUS_127__q168 = f2_exp__h526520 - 8'd127 ; - assign f2_exp__h526520 = + assign f2_exp26519_MINUS_127__q168 = f2_exp__h526519 - 8'd127 ; + assign f2_exp__h526519 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h526521 = + assign f2_sfd__h526520 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp65824_MINUS_127__q145 = f3_exp__h565824 - 8'd127 ; - assign f3_exp__h565824 = + assign f3_exp65823_MINUS_127__q145 = f3_exp__h565823 - 8'd127 ; + assign f3_exp__h565823 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h565825 = + assign f3_sfd__h565824 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign fallthrough_pc__h670385 = + assign fallthrough_pc__h670383 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h686131 = + assign fallthrough_pc__h686129 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; - assign fcsr_csr__read__h616233 = { 56'd0, x__h619373 } ; + assign fcsr_csr__read__h616232 = { 56'd0, x__h619372 } ; assign fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13536 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -28460,9 +28443,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h661837 != 5'd0 || - imm__h661838 != 32'd0) && - csr_addr__h661836[11:10] == 2'b11 ; + rs1__h661835 != 5'd0 || + imm__h661836 != 32'd0) && + csr_addr__h661834[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13836 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -28575,7 +28558,7 @@ module mkCore(CLK, IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13540 ; assign fetchStage_pipelines_1_first__2937_BIT_173_368_ETC___d13770 = { fetchStage$pipelines_1_first[173], - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 } ; + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 } ; assign fetchStage_pipelines_1_first__2937_BIT_68_3660_ETC___d14058 = fetchStage$pipelines_1_first[68] || checkForException___d13792[4] || @@ -28584,82 +28567,82 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14043 ; - assign fflags__h722582 = + assign fflags__h722584 = NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_fst__h722529 : + y_avValue_fst__h722531 : IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 ; - assign fflags_csr__read__h616208 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h616219 = { 61'd0, csrf_frm_reg } ; - assign guard__h350745 = - { IF_sfdin58840_BIT_33_THEN_2_ELSE_0__q22[1], - { sfdin__h358840[32:0], 23'd0 } != 56'd0 } ; - assign guard__h359454 = - { IF_theResult___snd67453_BIT_33_THEN_2_ELSE_0__q24[1], - { _theResult___snd__h367453[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368384 = - { IF_sfdin76606_BIT_33_THEN_2_ELSE_0__q32[1], - { sfdin__h376606[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368982 = x__h369084 != 57'd0 ; - assign guard__h377220 = - { IF_theResult___snd85243_BIT_33_THEN_2_ELSE_0__q37[1], - { _theResult___snd__h385243[32:0], 23'd0 } != 56'd0 } ; - assign guard__h396444 = - { IF_sfdin04537_BIT_33_THEN_2_ELSE_0__q57[1], - { sfdin__h404537[32:0], 23'd0 } != 56'd0 } ; - assign guard__h405151 = - { IF_theResult___snd13150_BIT_33_THEN_2_ELSE_0__q59[1], - { _theResult___snd__h413150[32:0], 23'd0 } != 56'd0 } ; - assign guard__h414081 = - { IF_sfdin22303_BIT_33_THEN_2_ELSE_0__q67[1], - { sfdin__h422303[32:0], 23'd0 } != 56'd0 } ; - assign guard__h414679 = x__h414781 != 57'd0 ; - assign guard__h422917 = - { IF_theResult___snd30940_BIT_33_THEN_2_ELSE_0__q72[1], - { _theResult___snd__h430940[32:0], 23'd0 } != 56'd0 } ; - assign guard__h442139 = - { IF_sfdin50232_BIT_33_THEN_2_ELSE_0__q92[1], - { sfdin__h450232[32:0], 23'd0 } != 56'd0 } ; - assign guard__h450846 = - { IF_theResult___snd58845_BIT_33_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h458845[32:0], 23'd0 } != 56'd0 } ; - assign guard__h459776 = - { IF_sfdin67998_BIT_33_THEN_2_ELSE_0__q102[1], - { sfdin__h467998[32:0], 23'd0 } != 56'd0 } ; - assign guard__h460374 = x__h460476 != 57'd0 ; - assign guard__h468612 = - { IF_theResult___snd76635_BIT_33_THEN_2_ELSE_0__q107[1], - { _theResult___snd__h476635[32:0], 23'd0 } != 56'd0 } ; - assign guard__h498953 = - { IF_theResult___snd06865_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h506865[3:0], 52'd0 } != 56'd0 } ; - assign guard__h508265 = - { IF_sfdin16485_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h516485[3:0], 52'd0 } != 56'd0 } ; - assign guard__h508863 = x__h508963 != 57'd0 ; - assign guard__h517334 = - { IF_theResult___snd25270_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h525270[3:0], 52'd0 } != 56'd0 } ; - assign guard__h537806 = - { IF_theResult___snd45718_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h545718[3:0], 52'd0 } != 56'd0 } ; - assign guard__h547118 = - { IF_sfdin55338_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h555338[3:0], 52'd0 } != 56'd0 } ; - assign guard__h547716 = x__h547816 != 57'd0 ; - assign guard__h556187 = - { IF_theResult___snd64123_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h564123[3:0], 52'd0 } != 56'd0 } ; - assign guard__h577110 = - { IF_theResult___snd85022_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h585022[3:0], 52'd0 } != 56'd0 } ; - assign guard__h586422 = - { IF_sfdin94642_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h594642[3:0], 52'd0 } != 56'd0 } ; - assign guard__h587020 = x__h587120 != 57'd0 ; - assign guard__h595491 = - { IF_theResult___snd03427_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h603427[3:0], 52'd0 } != 56'd0 } ; - assign idx__h689688 = + assign fflags_csr__read__h616207 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h616218 = { 61'd0, csrf_frm_reg } ; + assign guard__h350744 = + { IF_sfdin58839_BIT_33_THEN_2_ELSE_0__q22[1], + { sfdin__h358839[32:0], 23'd0 } != 56'd0 } ; + assign guard__h359453 = + { IF_theResult___snd67452_BIT_33_THEN_2_ELSE_0__q24[1], + { _theResult___snd__h367452[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368383 = + { IF_sfdin76605_BIT_33_THEN_2_ELSE_0__q32[1], + { sfdin__h376605[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368981 = x__h369083 != 57'd0 ; + assign guard__h377219 = + { IF_theResult___snd85242_BIT_33_THEN_2_ELSE_0__q37[1], + { _theResult___snd__h385242[32:0], 23'd0 } != 56'd0 } ; + assign guard__h396443 = + { IF_sfdin04536_BIT_33_THEN_2_ELSE_0__q57[1], + { sfdin__h404536[32:0], 23'd0 } != 56'd0 } ; + assign guard__h405150 = + { IF_theResult___snd13149_BIT_33_THEN_2_ELSE_0__q59[1], + { _theResult___snd__h413149[32:0], 23'd0 } != 56'd0 } ; + assign guard__h414080 = + { IF_sfdin22302_BIT_33_THEN_2_ELSE_0__q67[1], + { sfdin__h422302[32:0], 23'd0 } != 56'd0 } ; + assign guard__h414678 = x__h414780 != 57'd0 ; + assign guard__h422916 = + { IF_theResult___snd30939_BIT_33_THEN_2_ELSE_0__q72[1], + { _theResult___snd__h430939[32:0], 23'd0 } != 56'd0 } ; + assign guard__h442138 = + { IF_sfdin50231_BIT_33_THEN_2_ELSE_0__q92[1], + { sfdin__h450231[32:0], 23'd0 } != 56'd0 } ; + assign guard__h450845 = + { IF_theResult___snd58844_BIT_33_THEN_2_ELSE_0__q94[1], + { _theResult___snd__h458844[32:0], 23'd0 } != 56'd0 } ; + assign guard__h459775 = + { IF_sfdin67997_BIT_33_THEN_2_ELSE_0__q102[1], + { sfdin__h467997[32:0], 23'd0 } != 56'd0 } ; + assign guard__h460373 = x__h460475 != 57'd0 ; + assign guard__h468611 = + { IF_theResult___snd76634_BIT_33_THEN_2_ELSE_0__q107[1], + { _theResult___snd__h476634[32:0], 23'd0 } != 56'd0 } ; + assign guard__h498952 = + { IF_theResult___snd06864_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h506864[3:0], 52'd0 } != 56'd0 } ; + assign guard__h508264 = + { IF_sfdin16484_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h516484[3:0], 52'd0 } != 56'd0 } ; + assign guard__h508862 = x__h508962 != 57'd0 ; + assign guard__h517333 = + { IF_theResult___snd25269_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h525269[3:0], 52'd0 } != 56'd0 } ; + assign guard__h537805 = + { IF_theResult___snd45717_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h545717[3:0], 52'd0 } != 56'd0 } ; + assign guard__h547117 = + { IF_sfdin55337_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h555337[3:0], 52'd0 } != 56'd0 } ; + assign guard__h547715 = x__h547815 != 57'd0 ; + assign guard__h556186 = + { IF_theResult___snd64122_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h564122[3:0], 52'd0 } != 56'd0 } ; + assign guard__h577109 = + { IF_theResult___snd85021_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h585021[3:0], 52'd0 } != 56'd0 } ; + assign guard__h586421 = + { IF_sfdin94641_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h594641[3:0], 52'd0 } != 56'd0 } ; + assign guard__h587019 = x__h587119 != 57'd0 ; + assign guard__h595490 = + { IF_theResult___snd03426_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h603426[3:0], 52'd0 } != 56'd0 } ; + assign idx__h689686 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13837 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -28667,24 +28650,24 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13857) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3547__ETC___d13549 ; - assign imm__h661838 = + assign imm__h661836 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h674093 = + assign k__h674091 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3547__ETC___d13549 ; - assign mcause_csr__read__h617875 = - { r1__read__h620836, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h617620 = - { r1__read__h620823, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h617227 = - { r1__read__h620684, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h617322 = - { r1__read__h620701, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h617446 = { r1__read__h620725, 1'b0 } ; - assign mip_csr__read__h618108 = { r1__read__h620842, 1'b0 } ; + assign mcause_csr__read__h617874 = + { r1__read__h620835, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h617619 = + { r1__read__h620822, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h617226 = + { r1__read__h620683, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h617321 = + { r1__read__h620700, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h617445 = { r1__read__h620724, 1'b0 } ; + assign mip_csr__read__h618107 = { r1__read__h620841, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28761,40 +28744,40 @@ module mkCore(CLK, !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; assign msip__h75668 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h617079 = { r1__read__h620559, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h617528 = - { r1__read__h620818, csrf_mtvec_mode_low_reg } ; - assign n___1__h201749 = + assign mstatus_csr__read__h617078 = { r1__read__h620558, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h617527 = + { r1__read__h620817, csrf_mtvec_mode_low_reg } ; + assign n___1__h201748 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h200346[63:56], + x__h200345[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h200346[55:48], + x__h200345[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h200346[47:40], + x__h200345[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h200346[39:32], + x__h200345[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h200346[31:24], + x__h200345[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h200346[23:16], + x__h200345[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h200346[15:8], + x__h200345[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h200346[7:0] } ; - assign n__read__h618212 = + x__h200345[7:0] } ; + assign n__read__h618211 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h618403 = + assign n__read__h618402 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -28805,368 +28788,376 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h719386 = + assign n__read__h719387 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h301450 = + assign next_deqP___1__h301449 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h309446 = + assign next_deqP___1__h309445 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h315727 = + assign next_deqP___1__h315726 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h323581 = + assign next_deqP___1__h323580 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h333638 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h336863 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h718596 = + assign next_deqP___1__h333637 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h336862 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h718597 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954 ; - assign out___1_sfd__h487590 = { f1_sfd__h487527, 29'd0 } ; - assign out___1_sfd__h526584 = { f2_sfd__h526521, 29'd0 } ; - assign out___1_sfd__h565888 = { f3_sfd__h565825, 29'd0 } ; - assign out_exp__h359365 = - sfdin__h358840[34] ? - _theResult___exp__h359362 : - _theResult___fst_exp__h358846 ; - assign out_exp__h367947 = - _theResult___snd__h367453[34] ? - _theResult___exp__h367944 : - _theResult___fst_exp__h367502 ; - assign out_exp__h377131 = - sfdin__h376606[34] ? - _theResult___exp__h377128 : - _theResult___fst_exp__h376612 ; - assign out_exp__h385767 = - _theResult___snd__h385243[34] ? - _theResult___exp__h385764 : - _theResult___fst_exp__h385297 ; - assign out_exp__h405062 = - sfdin__h404537[34] ? - _theResult___exp__h405059 : - _theResult___fst_exp__h404543 ; - assign out_exp__h413644 = - _theResult___snd__h413150[34] ? - _theResult___exp__h413641 : - _theResult___fst_exp__h413199 ; - assign out_exp__h422828 = - sfdin__h422303[34] ? - _theResult___exp__h422825 : - _theResult___fst_exp__h422309 ; - assign out_exp__h431464 = - _theResult___snd__h430940[34] ? - _theResult___exp__h431461 : - _theResult___fst_exp__h430994 ; - assign out_exp__h450757 = - sfdin__h450232[34] ? - _theResult___exp__h450754 : - _theResult___fst_exp__h450238 ; - assign out_exp__h459339 = - _theResult___snd__h458845[34] ? - _theResult___exp__h459336 : - _theResult___fst_exp__h458894 ; - assign out_exp__h468523 = - sfdin__h467998[34] ? - _theResult___exp__h468520 : - _theResult___fst_exp__h468004 ; - assign out_exp__h477159 = - _theResult___snd__h476635[34] ? - _theResult___exp__h477156 : - _theResult___fst_exp__h476689 ; - assign out_exp__h507572 = - _theResult___snd__h506865[5] ? - _theResult___exp__h507569 : - _theResult___fst_exp__h506914 ; - assign out_exp__h517223 = - sfdin__h516485[5] ? - _theResult___exp__h517220 : - _theResult___fst_exp__h516491 ; - assign out_exp__h526007 = - _theResult___snd__h525270[5] ? - _theResult___exp__h526004 : - _theResult___fst_exp__h525324 ; - assign out_exp__h546425 = - _theResult___snd__h545718[5] ? - _theResult___exp__h546422 : - _theResult___fst_exp__h545767 ; - assign out_exp__h556076 = - sfdin__h555338[5] ? - _theResult___exp__h556073 : - _theResult___fst_exp__h555344 ; - assign out_exp__h564860 = - _theResult___snd__h564123[5] ? - _theResult___exp__h564857 : - _theResult___fst_exp__h564177 ; - assign out_exp__h585729 = - _theResult___snd__h585022[5] ? - _theResult___exp__h585726 : - _theResult___fst_exp__h585071 ; - assign out_exp__h595380 = - sfdin__h594642[5] ? - _theResult___exp__h595377 : - _theResult___fst_exp__h594648 ; - assign out_exp__h604164 = - _theResult___snd__h603427[5] ? - _theResult___exp__h604161 : - _theResult___fst_exp__h603481 ; - assign out_f_exp__h386143 = - (_theResult___exp__h385866 == 8'd255 && - _theResult___sfd__h385867 != 23'd0 || + assign out___1_sfd__h487589 = { f1_sfd__h487526, 29'd0 } ; + assign out___1_sfd__h526583 = { f2_sfd__h526520, 29'd0 } ; + assign out___1_sfd__h565887 = { f3_sfd__h565824, 29'd0 } ; + assign out_exp__h359364 = + sfdin__h358839[34] ? + _theResult___exp__h359361 : + _theResult___fst_exp__h358845 ; + assign out_exp__h367946 = + _theResult___snd__h367452[34] ? + _theResult___exp__h367943 : + _theResult___fst_exp__h367501 ; + assign out_exp__h377130 = + sfdin__h376605[34] ? + _theResult___exp__h377127 : + _theResult___fst_exp__h376611 ; + assign out_exp__h385766 = + _theResult___snd__h385242[34] ? + _theResult___exp__h385763 : + _theResult___fst_exp__h385296 ; + assign out_exp__h405061 = + sfdin__h404536[34] ? + _theResult___exp__h405058 : + _theResult___fst_exp__h404542 ; + assign out_exp__h413643 = + _theResult___snd__h413149[34] ? + _theResult___exp__h413640 : + _theResult___fst_exp__h413198 ; + assign out_exp__h422827 = + sfdin__h422302[34] ? + _theResult___exp__h422824 : + _theResult___fst_exp__h422308 ; + assign out_exp__h431463 = + _theResult___snd__h430939[34] ? + _theResult___exp__h431460 : + _theResult___fst_exp__h430993 ; + assign out_exp__h450756 = + sfdin__h450231[34] ? + _theResult___exp__h450753 : + _theResult___fst_exp__h450237 ; + assign out_exp__h459338 = + _theResult___snd__h458844[34] ? + _theResult___exp__h459335 : + _theResult___fst_exp__h458893 ; + assign out_exp__h468522 = + sfdin__h467997[34] ? + _theResult___exp__h468519 : + _theResult___fst_exp__h468003 ; + assign out_exp__h477158 = + _theResult___snd__h476634[34] ? + _theResult___exp__h477155 : + _theResult___fst_exp__h476688 ; + assign out_exp__h507571 = + _theResult___snd__h506864[5] ? + _theResult___exp__h507568 : + _theResult___fst_exp__h506913 ; + assign out_exp__h517222 = + sfdin__h516484[5] ? + _theResult___exp__h517219 : + _theResult___fst_exp__h516490 ; + assign out_exp__h526006 = + _theResult___snd__h525269[5] ? + _theResult___exp__h526003 : + _theResult___fst_exp__h525323 ; + assign out_exp__h546424 = + _theResult___snd__h545717[5] ? + _theResult___exp__h546421 : + _theResult___fst_exp__h545766 ; + assign out_exp__h556075 = + sfdin__h555337[5] ? + _theResult___exp__h556072 : + _theResult___fst_exp__h555343 ; + assign out_exp__h564859 = + _theResult___snd__h564122[5] ? + _theResult___exp__h564856 : + _theResult___fst_exp__h564176 ; + assign out_exp__h585728 = + _theResult___snd__h585021[5] ? + _theResult___exp__h585725 : + _theResult___fst_exp__h585070 ; + assign out_exp__h595379 = + sfdin__h594641[5] ? + _theResult___exp__h595376 : + _theResult___fst_exp__h594647 ; + assign out_exp__h604163 = + _theResult___snd__h603426[5] ? + _theResult___exp__h604160 : + _theResult___fst_exp__h603480 ; + assign out_f_exp__h386142 = + (_theResult___exp__h385865 == 8'd255 && + _theResult___sfd__h385866 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385857 ; - assign out_f_exp__h431840 = - (_theResult___exp__h431563 == 8'd255 && - _theResult___sfd__h431564 != 23'd0 || + _theResult___fst_exp__h385856 ; + assign out_f_exp__h431839 = + (_theResult___exp__h431562 == 8'd255 && + _theResult___sfd__h431563 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431554 ; - assign out_f_exp__h477535 = - (_theResult___exp__h477258 == 8'd255 && - _theResult___sfd__h477259 != 23'd0 || + _theResult___fst_exp__h431553 ; + assign out_f_exp__h477534 = + (_theResult___exp__h477257 == 8'd255 && + _theResult___sfd__h477258 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477249 ; - assign out_f_sfd__h386144 = - (_theResult___exp__h385866 == 8'd255 && - _theResult___sfd__h385867 != 23'd0) ? + _theResult___fst_exp__h477248 ; + assign out_f_sfd__h386143 = + (_theResult___exp__h385865 == 8'd255 && + _theResult___sfd__h385866 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h385867 ; - assign out_f_sfd__h431841 = - (_theResult___exp__h431563 == 8'd255 && - _theResult___sfd__h431564 != 23'd0) ? + _theResult___sfd__h385866 ; + assign out_f_sfd__h431840 = + (_theResult___exp__h431562 == 8'd255 && + _theResult___sfd__h431563 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h431564 ; - assign out_f_sfd__h477536 = - (_theResult___exp__h477258 == 8'd255 && - _theResult___sfd__h477259 != 23'd0) ? + _theResult___sfd__h431563 ; + assign out_f_sfd__h477535 = + (_theResult___exp__h477257 == 8'd255 && + _theResult___sfd__h477258 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h477259 ; - assign out_sfd__h359366 = - sfdin__h358840[34] ? - _theResult___sfd__h359363 : - sfdin__h358840[56:34] ; - assign out_sfd__h367948 = - _theResult___snd__h367453[34] ? - _theResult___sfd__h367945 : - _theResult___snd__h367453[56:34] ; - assign out_sfd__h377132 = - sfdin__h376606[34] ? - _theResult___sfd__h377129 : - sfdin__h376606[56:34] ; - assign out_sfd__h385768 = - _theResult___snd__h385243[34] ? - _theResult___sfd__h385765 : - _theResult___snd__h385243[56:34] ; - assign out_sfd__h405063 = - sfdin__h404537[34] ? - _theResult___sfd__h405060 : - sfdin__h404537[56:34] ; - assign out_sfd__h413645 = - _theResult___snd__h413150[34] ? - _theResult___sfd__h413642 : - _theResult___snd__h413150[56:34] ; - assign out_sfd__h422829 = - sfdin__h422303[34] ? - _theResult___sfd__h422826 : - sfdin__h422303[56:34] ; - assign out_sfd__h431465 = - _theResult___snd__h430940[34] ? - _theResult___sfd__h431462 : - _theResult___snd__h430940[56:34] ; - assign out_sfd__h450758 = - sfdin__h450232[34] ? - _theResult___sfd__h450755 : - sfdin__h450232[56:34] ; - assign out_sfd__h459340 = - _theResult___snd__h458845[34] ? - _theResult___sfd__h459337 : - _theResult___snd__h458845[56:34] ; - assign out_sfd__h468524 = - sfdin__h467998[34] ? - _theResult___sfd__h468521 : - sfdin__h467998[56:34] ; - assign out_sfd__h477160 = - _theResult___snd__h476635[34] ? - _theResult___sfd__h477157 : - _theResult___snd__h476635[56:34] ; - assign out_sfd__h507573 = - _theResult___snd__h506865[5] ? - _theResult___sfd__h507570 : - _theResult___snd__h506865[56:5] ; - assign out_sfd__h517224 = - sfdin__h516485[5] ? - _theResult___sfd__h517221 : - sfdin__h516485[56:5] ; - assign out_sfd__h526008 = - _theResult___snd__h525270[5] ? - _theResult___sfd__h526005 : - _theResult___snd__h525270[56:5] ; - assign out_sfd__h546426 = - _theResult___snd__h545718[5] ? - _theResult___sfd__h546423 : - _theResult___snd__h545718[56:5] ; - assign out_sfd__h556077 = - sfdin__h555338[5] ? - _theResult___sfd__h556074 : - sfdin__h555338[56:5] ; - assign out_sfd__h564861 = - _theResult___snd__h564123[5] ? - _theResult___sfd__h564858 : - _theResult___snd__h564123[56:5] ; - assign out_sfd__h585730 = - _theResult___snd__h585022[5] ? - _theResult___sfd__h585727 : - _theResult___snd__h585022[56:5] ; - assign out_sfd__h595381 = - sfdin__h594642[5] ? - _theResult___sfd__h595378 : - sfdin__h594642[56:5] ; - assign out_sfd__h604165 = - _theResult___snd__h603427[5] ? - _theResult___sfd__h604162 : - _theResult___snd__h603427[56:5] ; - assign pend_ints__h658025 = + _theResult___sfd__h477258 ; + assign out_sfd__h359365 = + sfdin__h358839[34] ? + _theResult___sfd__h359362 : + sfdin__h358839[56:34] ; + assign out_sfd__h367947 = + _theResult___snd__h367452[34] ? + _theResult___sfd__h367944 : + _theResult___snd__h367452[56:34] ; + assign out_sfd__h377131 = + sfdin__h376605[34] ? + _theResult___sfd__h377128 : + sfdin__h376605[56:34] ; + assign out_sfd__h385767 = + _theResult___snd__h385242[34] ? + _theResult___sfd__h385764 : + _theResult___snd__h385242[56:34] ; + assign out_sfd__h405062 = + sfdin__h404536[34] ? + _theResult___sfd__h405059 : + sfdin__h404536[56:34] ; + assign out_sfd__h413644 = + _theResult___snd__h413149[34] ? + _theResult___sfd__h413641 : + _theResult___snd__h413149[56:34] ; + assign out_sfd__h422828 = + sfdin__h422302[34] ? + _theResult___sfd__h422825 : + sfdin__h422302[56:34] ; + assign out_sfd__h431464 = + _theResult___snd__h430939[34] ? + _theResult___sfd__h431461 : + _theResult___snd__h430939[56:34] ; + assign out_sfd__h450757 = + sfdin__h450231[34] ? + _theResult___sfd__h450754 : + sfdin__h450231[56:34] ; + assign out_sfd__h459339 = + _theResult___snd__h458844[34] ? + _theResult___sfd__h459336 : + _theResult___snd__h458844[56:34] ; + assign out_sfd__h468523 = + sfdin__h467997[34] ? + _theResult___sfd__h468520 : + sfdin__h467997[56:34] ; + assign out_sfd__h477159 = + _theResult___snd__h476634[34] ? + _theResult___sfd__h477156 : + _theResult___snd__h476634[56:34] ; + assign out_sfd__h507572 = + _theResult___snd__h506864[5] ? + _theResult___sfd__h507569 : + _theResult___snd__h506864[56:5] ; + assign out_sfd__h517223 = + sfdin__h516484[5] ? + _theResult___sfd__h517220 : + sfdin__h516484[56:5] ; + assign out_sfd__h526007 = + _theResult___snd__h525269[5] ? + _theResult___sfd__h526004 : + _theResult___snd__h525269[56:5] ; + assign out_sfd__h546425 = + _theResult___snd__h545717[5] ? + _theResult___sfd__h546422 : + _theResult___snd__h545717[56:5] ; + assign out_sfd__h556076 = + sfdin__h555337[5] ? + _theResult___sfd__h556073 : + sfdin__h555337[56:5] ; + assign out_sfd__h564860 = + _theResult___snd__h564122[5] ? + _theResult___sfd__h564857 : + _theResult___snd__h564122[56:5] ; + assign out_sfd__h585729 = + _theResult___snd__h585021[5] ? + _theResult___sfd__h585726 : + _theResult___snd__h585021[56:5] ; + assign out_sfd__h595380 = + sfdin__h594641[5] ? + _theResult___sfd__h595377 : + sfdin__h594641[56:5] ; + assign out_sfd__h604164 = + _theResult___snd__h603426[5] ? + _theResult___sfd__h604161 : + _theResult___snd__h603426[56:5] ; + assign pend_ints__h658023 = { csrf_external_int_en_vec_3_read__1844_AND_csrf_ETC___d12967, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign prv__h724096 = csrf_prv_reg ; - assign prv__h724140 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h480780 = + assign prv__h724098 = csrf_prv_reg ; + assign prv__h724142 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h480779 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_12___h661706 = csrf_fs_reg ; - assign r1__read_BITS_9_TO_0___h658462 = + assign r1__read_BITS_13_TO_12___h661704 = csrf_fs_reg ; + assign r1__read_BITS_9_TO_0___h658460 = { csrf_mideleg_11_reg, 1'b0, csrf_mideleg_9_7_reg, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BIT_20___h662370 = csrf_tw_reg ; - assign r1__read__h619388 = { r1__read__h619390, csrf_ie_vec_1 } ; - assign r1__read__h619390 = { r1__read__h619392, 2'b0 } ; - assign r1__read__h619392 = { r1__read__h619394, csrf_prev_ie_vec_0 } ; - assign r1__read__h619394 = { r1__read__h619396, csrf_prev_ie_vec_1 } ; - assign r1__read__h619396 = { r1__read__h619398, 2'b0 } ; - assign r1__read__h619398 = { r1__read__h619400, csrf_spp_reg } ; - assign r1__read__h619400 = { r1__read__h619402, 4'b0 } ; - assign r1__read__h619402 = { r1__read__h619404, csrf_fs_reg } ; - assign r1__read__h619404 = { r1__read__h619406, 2'd0 } ; - assign r1__read__h619406 = { r1__read__h619408, 1'b0 } ; - assign r1__read__h619408 = { r1__read__h619410, csrf_sum_reg } ; - assign r1__read__h619410 = { r1__read__h619412, csrf_mxr_reg } ; - assign r1__read__h619412 = { r1__read__h619414, 12'b0 } ; - assign r1__read__h619414 = { r1__read__h619416, 2'b10 } ; - assign r1__read__h619416 = { r__h619420, 29'b0 } ; - assign r1__read__h619792 = - { r1__read__h619794, csrf_software_int_en_vec_1 } ; - assign r1__read__h619794 = { r1__read__h619796, 2'b0 } ; - assign r1__read__h619796 = { r1__read__h619798, 1'b0 } ; - assign r1__read__h619798 = { r1__read__h619800, csrf_timer_int_en_vec_1 } ; - assign r1__read__h619800 = { r1__read__h619802, 2'b0 } ; - assign r1__read__h619802 = { r1__read__h619804, 1'b0 } ; - assign r1__read__h619804 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h620302 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620307 = { r1__read__h620309, csrf_scounteren_tm_reg } ; - assign r1__read__h620309 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h620320 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h620326 = - { r1__read__h620328, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620328 = { r1__read__h620330, 2'b0 } ; - assign r1__read__h620330 = { r1__read__h620332, 1'b0 } ; - assign r1__read__h620332 = - { r1__read__h620334, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620334 = { r1__read__h620336, 2'b0 } ; - assign r1__read__h620336 = { r1__read__h620338, 1'b0 } ; - assign r1__read__h620338 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620536 = { vm_mode_reg__read__h620542, 16'd0 } ; - assign r1__read__h620559 = { r1__read__h620561, csrf_ie_vec_1 } ; - assign r1__read__h620561 = { r1__read__h620563, 1'b0 } ; - assign r1__read__h620563 = { r1__read__h620565, csrf_ie_vec_3 } ; - assign r1__read__h620565 = { r1__read__h620567, csrf_prev_ie_vec_0 } ; - assign r1__read__h620567 = { r1__read__h620569, csrf_prev_ie_vec_1 } ; - assign r1__read__h620569 = { r1__read__h620571, 1'b0 } ; - assign r1__read__h620571 = { r1__read__h620573, csrf_prev_ie_vec_3 } ; - assign r1__read__h620573 = { r1__read__h620575, csrf_spp_reg } ; - assign r1__read__h620575 = { r1__read__h620577, 2'b0 } ; - assign r1__read__h620577 = { r1__read__h620579, csrf_mpp_reg } ; - assign r1__read__h620579 = { r1__read__h620581, csrf_fs_reg } ; - assign r1__read__h620581 = { r1__read__h620583, 2'd0 } ; - assign r1__read__h620583 = { r1__read__h620585, csrf_mprv_reg } ; - assign r1__read__h620585 = { r1__read__h620587, csrf_sum_reg } ; - assign r1__read__h620587 = { r1__read__h620589, csrf_mxr_reg } ; - assign r1__read__h620589 = { r1__read__h620591, csrf_tvm_reg } ; - assign r1__read__h620591 = { r1__read__h620593, csrf_tw_reg } ; - assign r1__read__h620593 = { r1__read__h620595, csrf_tsr_reg } ; - assign r1__read__h620595 = { r1__read__h620597, 9'b0 } ; - assign r1__read__h620597 = { r1__read__h620599, 2'b10 } ; - assign r1__read__h620599 = { r1__read__h620601, 2'b10 } ; - assign r1__read__h620601 = { r__h619420, 27'b0 } ; - assign r1__read__h620684 = { r1__read__h620686, 1'b0 } ; - assign r1__read__h620686 = { r1__read__h620688, csrf_medeleg_13_11_reg } ; - assign r1__read__h620688 = { r1__read__h620690, 1'b0 } ; - assign r1__read__h620690 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h620701 = { r1__read__h620703, 1'b0 } ; - assign r1__read__h620703 = { r1__read__h620705, csrf_mideleg_5_3_reg } ; - assign r1__read__h620705 = { r1__read__h620707, 1'b0 } ; - assign r1__read__h620707 = { r1__read__h620709, csrf_mideleg_9_7_reg } ; - assign r1__read__h620709 = { r1__read__h620711, 1'b0 } ; - assign r1__read__h620711 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h620725 = - { r1__read__h620727, csrf_software_int_en_vec_1 } ; - assign r1__read__h620727 = { r1__read__h620729, 1'b0 } ; - assign r1__read__h620729 = - { r1__read__h620731, csrf_software_int_en_vec_3 } ; - assign r1__read__h620731 = { r1__read__h620733, 1'b0 } ; - assign r1__read__h620733 = { r1__read__h620735, csrf_timer_int_en_vec_1 } ; - assign r1__read__h620735 = { r1__read__h620737, 1'b0 } ; - assign r1__read__h620737 = { r1__read__h620739, csrf_timer_int_en_vec_3 } ; - assign r1__read__h620739 = { r1__read__h620741, 1'b0 } ; - assign r1__read__h620741 = - { r1__read__h620743, csrf_external_int_en_vec_1 } ; - assign r1__read__h620743 = { r1__read__h620745, 1'b0 } ; - assign r1__read__h620745 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h620818 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620823 = { r1__read__h620825, csrf_mcounteren_tm_reg } ; - assign r1__read__h620825 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h620836 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h620842 = - { r1__read__h620844, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620844 = { r1__read__h620846, 1'b0 } ; - assign r1__read__h620846 = - { r1__read__h620848, csrf_software_int_pend_vec_3 } ; - assign r1__read__h620848 = { r1__read__h620850, 1'b0 } ; - assign r1__read__h620850 = - { r1__read__h620852, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620852 = { r1__read__h620854, 1'b0 } ; - assign r1__read__h620854 = - { r1__read__h620856, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h620856 = { r1__read__h620858, 1'b0 } ; - assign r1__read__h620858 = - { r1__read__h620860, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620860 = { r1__read__h620862, 1'b0 } ; - assign r1__read__h620862 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h620939 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h487142 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h487143 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h480807 = + assign r1__read_BIT_20___h662368 = csrf_tw_reg ; + assign r1__read__h619387 = { r1__read__h619389, csrf_ie_vec_1 } ; + assign r1__read__h619389 = { r1__read__h619391, 2'b0 } ; + assign r1__read__h619391 = { r1__read__h619393, csrf_prev_ie_vec_0 } ; + assign r1__read__h619393 = { r1__read__h619395, csrf_prev_ie_vec_1 } ; + assign r1__read__h619395 = { r1__read__h619397, 2'b0 } ; + assign r1__read__h619397 = { r1__read__h619399, csrf_spp_reg } ; + assign r1__read__h619399 = { r1__read__h619401, 4'b0 } ; + assign r1__read__h619401 = { r1__read__h619403, csrf_fs_reg } ; + assign r1__read__h619403 = { r1__read__h619405, 2'd0 } ; + assign r1__read__h619405 = { r1__read__h619407, 1'b0 } ; + assign r1__read__h619407 = { r1__read__h619409, csrf_sum_reg } ; + assign r1__read__h619409 = { r1__read__h619411, csrf_mxr_reg } ; + assign r1__read__h619411 = { r1__read__h619413, 12'b0 } ; + assign r1__read__h619413 = { r1__read__h619415, 2'b10 } ; + assign r1__read__h619415 = { r__h619419, 29'b0 } ; + assign r1__read__h619791 = + { r1__read__h619793, csrf_software_int_en_vec_1 } ; + assign r1__read__h619793 = { r1__read__h619795, 2'b0 } ; + assign r1__read__h619795 = { r1__read__h619797, 1'b0 } ; + assign r1__read__h619797 = { r1__read__h619799, csrf_timer_int_en_vec_1 } ; + assign r1__read__h619799 = { r1__read__h619801, 2'b0 } ; + assign r1__read__h619801 = { r1__read__h619803, 1'b0 } ; + assign r1__read__h619803 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h620301 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620306 = { r1__read__h620308, csrf_scounteren_tm_reg } ; + assign r1__read__h620308 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h620319 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h620325 = + { r1__read__h620327, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620327 = { r1__read__h620329, 2'b0 } ; + assign r1__read__h620329 = { r1__read__h620331, 1'b0 } ; + assign r1__read__h620331 = + { r1__read__h620333, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620333 = { r1__read__h620335, 2'b0 } ; + assign r1__read__h620335 = { r1__read__h620337, 1'b0 } ; + assign r1__read__h620337 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620535 = { vm_mode_reg__read__h620541, 16'd0 } ; + assign r1__read__h620558 = { r1__read__h620560, csrf_ie_vec_1 } ; + assign r1__read__h620560 = { r1__read__h620562, 1'b0 } ; + assign r1__read__h620562 = { r1__read__h620564, csrf_ie_vec_3 } ; + assign r1__read__h620564 = { r1__read__h620566, csrf_prev_ie_vec_0 } ; + assign r1__read__h620566 = { r1__read__h620568, csrf_prev_ie_vec_1 } ; + assign r1__read__h620568 = { r1__read__h620570, 1'b0 } ; + assign r1__read__h620570 = { r1__read__h620572, csrf_prev_ie_vec_3 } ; + assign r1__read__h620572 = { r1__read__h620574, csrf_spp_reg } ; + assign r1__read__h620574 = { r1__read__h620576, 2'b0 } ; + assign r1__read__h620576 = { r1__read__h620578, csrf_mpp_reg } ; + assign r1__read__h620578 = { r1__read__h620580, csrf_fs_reg } ; + assign r1__read__h620580 = { r1__read__h620582, 2'd0 } ; + assign r1__read__h620582 = { r1__read__h620584, csrf_mprv_reg } ; + assign r1__read__h620584 = { r1__read__h620586, csrf_sum_reg } ; + assign r1__read__h620586 = { r1__read__h620588, csrf_mxr_reg } ; + assign r1__read__h620588 = { r1__read__h620590, csrf_tvm_reg } ; + assign r1__read__h620590 = { r1__read__h620592, csrf_tw_reg } ; + assign r1__read__h620592 = { r1__read__h620594, csrf_tsr_reg } ; + assign r1__read__h620594 = { r1__read__h620596, 9'b0 } ; + assign r1__read__h620596 = { r1__read__h620598, 2'b10 } ; + assign r1__read__h620598 = { r1__read__h620600, 2'b10 } ; + assign r1__read__h620600 = { r__h619419, 27'b0 } ; + assign r1__read__h620683 = { r1__read__h620685, 1'b0 } ; + assign r1__read__h620685 = { r1__read__h620687, csrf_medeleg_13_11_reg } ; + assign r1__read__h620687 = { r1__read__h620689, 1'b0 } ; + assign r1__read__h620689 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h620700 = { r1__read__h620702, 1'b0 } ; + assign r1__read__h620702 = { r1__read__h620704, csrf_mideleg_5_3_reg } ; + assign r1__read__h620704 = { r1__read__h620706, 1'b0 } ; + assign r1__read__h620706 = { r1__read__h620708, csrf_mideleg_9_7_reg } ; + assign r1__read__h620708 = { r1__read__h620710, 1'b0 } ; + assign r1__read__h620710 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h620724 = + { r1__read__h620726, csrf_software_int_en_vec_1 } ; + assign r1__read__h620726 = { r1__read__h620728, 1'b0 } ; + assign r1__read__h620728 = + { r1__read__h620730, csrf_software_int_en_vec_3 } ; + assign r1__read__h620730 = { r1__read__h620732, 1'b0 } ; + assign r1__read__h620732 = { r1__read__h620734, csrf_timer_int_en_vec_1 } ; + assign r1__read__h620734 = { r1__read__h620736, 1'b0 } ; + assign r1__read__h620736 = { r1__read__h620738, csrf_timer_int_en_vec_3 } ; + assign r1__read__h620738 = { r1__read__h620740, 1'b0 } ; + assign r1__read__h620740 = + { r1__read__h620742, csrf_external_int_en_vec_1 } ; + assign r1__read__h620742 = { r1__read__h620744, 1'b0 } ; + assign r1__read__h620744 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h620817 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620822 = { r1__read__h620824, csrf_mcounteren_tm_reg } ; + assign r1__read__h620824 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h620835 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h620841 = + { r1__read__h620843, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620843 = { r1__read__h620845, 1'b0 } ; + assign r1__read__h620845 = + { r1__read__h620847, csrf_software_int_pend_vec_3 } ; + assign r1__read__h620847 = { r1__read__h620849, 1'b0 } ; + assign r1__read__h620849 = + { r1__read__h620851, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620851 = { r1__read__h620853, 1'b0 } ; + assign r1__read__h620853 = + { r1__read__h620855, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h620855 = { r1__read__h620857, 1'b0 } ; + assign r1__read__h620857 = + { r1__read__h620859, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620859 = { r1__read__h620861, 1'b0 } ; + assign r1__read__h620861 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h620938 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h487141 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h487142 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h480806 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h619420 = csrf_fs_reg == 2'b11 ; - assign regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14022 = + assign r__h619419 = csrf_fs_reg == 2'b11 ; + assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407 = regRenamingTable$RDY_rename_0_getRename && - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14022 = + regRenamingTable$RDY_rename_0_getRename && + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || coreFix_memExe_rsMem$RDY_enq) ; assign regRenamingTable_RDY_rename_1_getRename__4078__ETC___d14096 = @@ -29306,12 +29297,12 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14371 && (fetchStage$pipelines_1_first[199:195] != 5'd14) != fetchStage$pipelines_1_first[160] ; - assign renaming_spec_bits__h689557 = + assign renaming_spec_bits__h689555 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h686255 : + y_avValue_snd_fst__h686253 : specTagManager$currentSpecBits ; - assign res_data__h342519 = { 32'hFFFFFFFF, x__h342534 } ; - assign res_data__h342524 = + assign res_data__h342518 = { 32'hFFFFFFFF, x__h342533 } ; + assign res_data__h342523 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -29324,8 +29315,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h388221 = { 32'hFFFFFFFF, x__h388236 } ; - assign res_data__h388226 = + assign res_data__h388220 = { 32'hFFFFFFFF, x__h388235 } ; + assign res_data__h388225 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -29338,8 +29329,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h433916 = { 32'hFFFFFFFF, x__h433931 } ; - assign res_data__h433921 = + assign res_data__h433915 = { 32'hFFFFFFFF, x__h433930 } ; + assign res_data__h433920 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -29352,7 +29343,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h342520 = + assign res_fflags__h342519 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -29420,7 +29411,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351 } ; - assign res_fflags__h388222 = + assign res_fflags__h388221 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -29488,7 +29479,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743 } ; - assign res_fflags__h433917 = + assign res_fflags__h433916 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -29556,45 +29547,37 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135 } ; - assign resp_addr__h296627 = + assign resp_addr__h296626 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h368987 = + assign result__h368986 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[0] | - guard__h368982 } ; - assign result__h414684 = + guard__h368981 } ; + assign result__h414683 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[0] | - guard__h414679 } ; - assign result__h460379 = + guard__h414678 } ; + assign result__h460378 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[0] | - guard__h460374 } ; - assign result__h508868 = + guard__h460373 } ; + assign result__h508867 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[0] | - guard__h508863 } ; - assign result__h547721 = + guard__h508862 } ; + assign result__h547720 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[0] | - guard__h547716 } ; - assign result__h587025 = + guard__h547715 } ; + assign result__h587024 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[0] | - guard__h587020 } ; - assign result__h653734 = w__h653729 & y__h653763 ; - assign result__h653785 = ~x__h653784 ; - assign rg_tdata1__read__h619063 = - { r1__read__h620939, csrf_rg_tdata1_data } ; - assign rob_RDY_enqPort_0_enq__2950_AND_regRenamingTab_ETC___d13407 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; + guard__h587019 } ; + assign result__h653732 = w__h653727 & y__h653761 ; + assign result__h653783 = ~x__h653782 ; + assign rg_tdata1__read__h619062 = + { r1__read__h620938, csrf_rg_tdata1_data } ; assign rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954 = rob$deqPort_0_deq_data[353:290] + 64'd4 ; assign rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13826 = @@ -29620,293 +29603,293 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13973) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q262 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h661837 = + assign rs1__h661835 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h616936 = { r1__read__h620536, csrf_ppn_reg } ; - assign sbIdx__h158517 = + assign satp_csr__read__h616935 = { r1__read__h620535, csrf_ppn_reg } ; + assign sbIdx__h158516 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h616733 = - { r1__read__h620320, csrf_scause_code_reg } ; - assign scounteren_csr__read__h616595 = - { r1__read__h620307, csrf_scounteren_cy_reg } ; - assign sfd__h343130 = { value__h351357, 3'd0 } ; - assign sfd__h358938 = + assign scause_csr__read__h616732 = + { r1__read__h620319, csrf_scause_code_reg } ; + assign scounteren_csr__read__h616594 = + { r1__read__h620306, csrf_scounteren_cy_reg } ; + assign sfd__h343129 = { value__h351356, 3'd0 } ; + assign sfd__h358937 = { 1'b0, - _theResult___fst_exp__h358846 != 8'd0, - sfdin__h358840[56:34] } + + _theResult___fst_exp__h358845 != 8'd0, + sfdin__h358839[56:34] } + 25'd1 ; - assign sfd__h367520 = + assign sfd__h367519 = { 1'b0, - _theResult___fst_exp__h367502 != 8'd0, - _theResult___snd__h367453[56:34] } + + _theResult___fst_exp__h367501 != 8'd0, + _theResult___snd__h367452[56:34] } + 25'd1 ; - assign sfd__h376704 = + assign sfd__h376703 = { 1'b0, - _theResult___fst_exp__h376612 != 8'd0, - sfdin__h376606[56:34] } + + _theResult___fst_exp__h376611 != 8'd0, + sfdin__h376605[56:34] } + 25'd1 ; - assign sfd__h385316 = + assign sfd__h385315 = { 1'b0, - _theResult___fst_exp__h385297 != 8'd0, - _theResult___snd__h385243[56:34] } + + _theResult___fst_exp__h385296 != 8'd0, + _theResult___snd__h385242[56:34] } + 25'd1 ; - assign sfd__h388832 = { value__h397054, 3'd0 } ; - assign sfd__h404635 = + assign sfd__h388831 = { value__h397053, 3'd0 } ; + assign sfd__h404634 = { 1'b0, - _theResult___fst_exp__h404543 != 8'd0, - sfdin__h404537[56:34] } + + _theResult___fst_exp__h404542 != 8'd0, + sfdin__h404536[56:34] } + 25'd1 ; - assign sfd__h413217 = + assign sfd__h413216 = { 1'b0, - _theResult___fst_exp__h413199 != 8'd0, - _theResult___snd__h413150[56:34] } + + _theResult___fst_exp__h413198 != 8'd0, + _theResult___snd__h413149[56:34] } + 25'd1 ; - assign sfd__h422401 = + assign sfd__h422400 = { 1'b0, - _theResult___fst_exp__h422309 != 8'd0, - sfdin__h422303[56:34] } + + _theResult___fst_exp__h422308 != 8'd0, + sfdin__h422302[56:34] } + 25'd1 ; - assign sfd__h431013 = + assign sfd__h431012 = { 1'b0, - _theResult___fst_exp__h430994 != 8'd0, - _theResult___snd__h430940[56:34] } + + _theResult___fst_exp__h430993 != 8'd0, + _theResult___snd__h430939[56:34] } + 25'd1 ; - assign sfd__h434527 = { value__h442749, 3'd0 } ; - assign sfd__h450330 = + assign sfd__h434526 = { value__h442748, 3'd0 } ; + assign sfd__h450329 = { 1'b0, - _theResult___fst_exp__h450238 != 8'd0, - sfdin__h450232[56:34] } + + _theResult___fst_exp__h450237 != 8'd0, + sfdin__h450231[56:34] } + 25'd1 ; - assign sfd__h458912 = + assign sfd__h458911 = { 1'b0, - _theResult___fst_exp__h458894 != 8'd0, - _theResult___snd__h458845[56:34] } + + _theResult___fst_exp__h458893 != 8'd0, + _theResult___snd__h458844[56:34] } + 25'd1 ; - assign sfd__h468096 = + assign sfd__h468095 = { 1'b0, - _theResult___fst_exp__h468004 != 8'd0, - sfdin__h467998[56:34] } + + _theResult___fst_exp__h468003 != 8'd0, + sfdin__h467997[56:34] } + 25'd1 ; - assign sfd__h476708 = + assign sfd__h476707 = { 1'b0, - _theResult___fst_exp__h476689 != 8'd0, - _theResult___snd__h476635[56:34] } + + _theResult___fst_exp__h476688 != 8'd0, + _theResult___snd__h476634[56:34] } + 25'd1 ; - assign sfd__h487888 = { value__h492471, 32'd0 } ; - assign sfd__h506932 = + assign sfd__h487887 = { value__h492470, 32'd0 } ; + assign sfd__h506931 = { 1'b0, - _theResult___fst_exp__h506914 != 11'd0, - _theResult___snd__h506865[56:5] } + + _theResult___fst_exp__h506913 != 11'd0, + _theResult___snd__h506864[56:5] } + 54'd1 ; - assign sfd__h516583 = + assign sfd__h516582 = { 1'b0, - _theResult___fst_exp__h516491 != 11'd0, - sfdin__h516485[56:5] } + + _theResult___fst_exp__h516490 != 11'd0, + sfdin__h516484[56:5] } + 54'd1 ; - assign sfd__h525343 = + assign sfd__h525342 = { 1'b0, - _theResult___fst_exp__h525324 != 11'd0, - _theResult___snd__h525270[56:5] } + + _theResult___fst_exp__h525323 != 11'd0, + _theResult___snd__h525269[56:5] } + 54'd1 ; - assign sfd__h526882 = { value__h531324, 32'd0 } ; - assign sfd__h545785 = + assign sfd__h526881 = { value__h531323, 32'd0 } ; + assign sfd__h545784 = { 1'b0, - _theResult___fst_exp__h545767 != 11'd0, - _theResult___snd__h545718[56:5] } + + _theResult___fst_exp__h545766 != 11'd0, + _theResult___snd__h545717[56:5] } + 54'd1 ; - assign sfd__h555436 = + assign sfd__h555435 = { 1'b0, - _theResult___fst_exp__h555344 != 11'd0, - sfdin__h555338[56:5] } + + _theResult___fst_exp__h555343 != 11'd0, + sfdin__h555337[56:5] } + 54'd1 ; - assign sfd__h564196 = + assign sfd__h564195 = { 1'b0, - _theResult___fst_exp__h564177 != 11'd0, - _theResult___snd__h564123[56:5] } + + _theResult___fst_exp__h564176 != 11'd0, + _theResult___snd__h564122[56:5] } + 54'd1 ; - assign sfd__h566186 = { value__h570628, 32'd0 } ; - assign sfd__h585089 = + assign sfd__h566185 = { value__h570627, 32'd0 } ; + assign sfd__h585088 = { 1'b0, - _theResult___fst_exp__h585071 != 11'd0, - _theResult___snd__h585022[56:5] } + + _theResult___fst_exp__h585070 != 11'd0, + _theResult___snd__h585021[56:5] } + 54'd1 ; - assign sfd__h594740 = + assign sfd__h594739 = { 1'b0, - _theResult___fst_exp__h594648 != 11'd0, - sfdin__h594642[56:5] } + + _theResult___fst_exp__h594647 != 11'd0, + sfdin__h594641[56:5] } + 54'd1 ; - assign sfd__h603500 = + assign sfd__h603499 = { 1'b0, - _theResult___fst_exp__h603481 != 11'd0, - _theResult___snd__h603427[56:5] } + + _theResult___fst_exp__h603480 != 11'd0, + _theResult___snd__h603426[56:5] } + 54'd1 ; - assign sfdin__h358840 = - _theResult____h350735[56] ? - _theResult___snd__h358857 : - _theResult___snd__h358868 ; - assign sfdin__h376606 = - _theResult____h368374[56] ? - _theResult___snd__h376623 : - _theResult___snd__h376634 ; - assign sfdin__h404537 = - _theResult____h396434[56] ? - _theResult___snd__h404554 : - _theResult___snd__h404565 ; - assign sfdin__h422303 = - _theResult____h414071[56] ? - _theResult___snd__h422320 : - _theResult___snd__h422331 ; - assign sfdin__h450232 = - _theResult____h442129[56] ? - _theResult___snd__h450249 : - _theResult___snd__h450260 ; - assign sfdin__h467998 = - _theResult____h459766[56] ? - _theResult___snd__h468015 : - _theResult___snd__h468026 ; - assign sfdin__h516485 = - _theResult____h508255[56] ? - _theResult___snd__h516502 : - _theResult___snd__h516513 ; - assign sfdin__h555338 = - _theResult____h547108[56] ? - _theResult___snd__h555355 : - _theResult___snd__h555366 ; - assign sfdin__h594642 = - _theResult____h586412[56] ? - _theResult___snd__h594659 : - _theResult___snd__h594670 ; - assign shiftData__h184742 = - coreFix_memExe_regToExeQ$first[75:12] << x__h184871 ; - assign sie_csr__read__h616499 = { r1__read__h619792, 1'b0 } ; - assign sip_csr__read__h616873 = { r1__read__h620326, 1'b0 } ; - assign spec_bits__h692684 = specTagManager$currentSpecBits | y__h692697 ; - assign sstatus_csr__read__h616429 = { r1__read__h619388, csrf_ie_vec_0 } ; - assign stvec_csr__read__h616542 = - { r1__read__h620302, csrf_stvec_mode_low_reg } ; + assign sfdin__h358839 = + _theResult____h350734[56] ? + _theResult___snd__h358856 : + _theResult___snd__h358867 ; + assign sfdin__h376605 = + _theResult____h368373[56] ? + _theResult___snd__h376622 : + _theResult___snd__h376633 ; + assign sfdin__h404536 = + _theResult____h396433[56] ? + _theResult___snd__h404553 : + _theResult___snd__h404564 ; + assign sfdin__h422302 = + _theResult____h414070[56] ? + _theResult___snd__h422319 : + _theResult___snd__h422330 ; + assign sfdin__h450231 = + _theResult____h442128[56] ? + _theResult___snd__h450248 : + _theResult___snd__h450259 ; + assign sfdin__h467997 = + _theResult____h459765[56] ? + _theResult___snd__h468014 : + _theResult___snd__h468025 ; + assign sfdin__h516484 = + _theResult____h508254[56] ? + _theResult___snd__h516501 : + _theResult___snd__h516512 ; + assign sfdin__h555337 = + _theResult____h547107[56] ? + _theResult___snd__h555354 : + _theResult___snd__h555365 ; + assign sfdin__h594641 = + _theResult____h586411[56] ? + _theResult___snd__h594658 : + _theResult___snd__h594669 ; + assign shiftData__h184741 = + coreFix_memExe_regToExeQ$first[75:12] << x__h184870 ; + assign sie_csr__read__h616498 = { r1__read__h619791, 1'b0 } ; + assign sip_csr__read__h616872 = { r1__read__h620325, 1'b0 } ; + assign spec_bits__h692682 = specTagManager$currentSpecBits | y__h692695 ; + assign sstatus_csr__read__h616428 = { r1__read__h619387, csrf_ie_vec_0 } ; + assign stvec_csr__read__h616541 = + { r1__read__h620301, csrf_stvec_mode_low_reg } ; assign upd__h3680 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; assign upd__h4997 = n__read__h6329 + 64'd1 ; - assign v__h300591 = + assign v__h300590 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127) ? - v__h300822 : + v__h300821 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h300822 = + assign v__h300821 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h303936 = + assign v__h303935 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234) ? - v__h304454 : + v__h304453 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h304454 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h314450 = + assign v__h304453 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h314449 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405) ? - v__h314681 : + v__h314680 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h314681 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h318326 = + assign v__h314680 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h318325 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501) ? - v__h318557 : + v__h318556 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h318557 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h332927 = + assign v__h318556 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h332926 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730) ? - v__h333158 : + v__h333157 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h333158 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h336152 = + assign v__h333157 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h336151 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824) ? - v__h336383 : + v__h336382 : coreFix_memExe_forwardQ_enqP ; - assign v__h336383 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h609619 = + assign v__h336382 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h609618 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h609629 : + v__h609628 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h609629 = + assign v__h609628 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h610687 = v__h609619 - 2'd1 ; - assign v__h614703 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615874 ; - assign v__h639702 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640721 ; - assign vaddr__h184737 = + assign v__h610686 = v__h609618 - 2'd1 ; + assign v__h614702 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615873 ; + assign v__h639700 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640719 ; + assign vaddr__h184736 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 } ; - assign value__h351357 = + assign value__h351356 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h397054 = + assign value__h397053 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h442749 = + assign value__h442748 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h492471 = { 1'b0, f1_exp__h487526 != 8'd0, f1_sfd__h487527 } ; - assign value__h531324 = { 1'b0, f2_exp__h526520 != 8'd0, f2_sfd__h526521 } ; - assign value__h570628 = { 1'b0, f3_exp__h565824 != 8'd0, f3_sfd__h565825 } ; - assign vm_mode_reg__read__h620542 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h653729 = + assign value__h492470 = { 1'b0, f1_exp__h487525 != 8'd0, f1_sfd__h487526 } ; + assign value__h531323 = { 1'b0, f2_exp__h526519 != 8'd0, f2_sfd__h526520 } ; + assign value__h570627 = { 1'b0, f3_exp__h565823 != 8'd0, f3_sfd__h565824 } ; + assign vm_mode_reg__read__h620541 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h653727 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h653785 : + result__h653783 : 12'd4095 ; - assign x__h155091 = + assign x__h155090 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h155097 = + assign x__h155096 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h158638 = { 3'd0, sbIdx__h158517 } ; - assign x__h158644 = + assign x__h158637 = { 3'd0, sbIdx__h158516 } ; + assign x__h158643 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h161454 = + assign x__h161453 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h161458 = + assign x__h161457 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h163306 = + assign x__h163305 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : @@ -29916,141 +29899,141 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; + assign x__h184648 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183776 ; assign x__h184649 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183777 ; - assign x__h184650 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184496 ; - assign x__h184871 = { vaddr__h184737[2:0], 3'b0 } ; - assign x__h196066 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184495 ; + assign x__h184870 = { vaddr__h184736[2:0], 3'b0 } ; + assign x__h196065 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h195303[63:32] : - curData__h195303[31:0] ; + curData__h195302[63:32] : + curData__h195302[31:0] ; assign x__h20469 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h291824 = + assign x__h291823 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h291836 = + assign x__h291835 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h293690 = + assign x__h293689 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h306801 = + assign x__h306800 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h342534 = - { (_theResult___exp__h385866 != 8'd255 || - _theResult___sfd__h385867 == 23'd0) && + assign x__h342533 = + { (_theResult___exp__h385865 != 8'd255 || + _theResult___sfd__h385866 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236, - out_f_exp__h386143, - out_f_sfd__h386144 } ; - assign x__h369084 = - sfd__h343130 << (x__h369117[11] ? 12'hAAA : x__h369117) ; - assign x__h369117 = + out_f_exp__h386142, + out_f_sfd__h386143 } ; + assign x__h369083 = + sfd__h343129 << (x__h369116[11] ? 12'hAAA : x__h369116) ; + assign x__h369116 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ; - assign x__h388236 = - { (_theResult___exp__h431563 != 8'd255 || - _theResult___sfd__h431564 == 23'd0) && + assign x__h388235 = + { (_theResult___exp__h431562 != 8'd255 || + _theResult___sfd__h431563 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628, - out_f_exp__h431840, - out_f_sfd__h431841 } ; - assign x__h414781 = - sfd__h388832 << (x__h414814[11] ? 12'hAAA : x__h414814) ; - assign x__h414814 = + out_f_exp__h431839, + out_f_sfd__h431840 } ; + assign x__h414780 = + sfd__h388831 << (x__h414813[11] ? 12'hAAA : x__h414813) ; + assign x__h414813 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ; - assign x__h433931 = - { (_theResult___exp__h477258 != 8'd255 || - _theResult___sfd__h477259 == 23'd0) && + assign x__h433930 = + { (_theResult___exp__h477257 != 8'd255 || + _theResult___sfd__h477258 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020, - out_f_exp__h477535, - out_f_sfd__h477536 } ; + out_f_exp__h477534, + out_f_sfd__h477535 } ; assign x__h45838 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h460476 = - sfd__h434527 << (x__h460509[11] ? 12'hAAA : x__h460509) ; - assign x__h460509 = + assign x__h460475 = + sfd__h434526 << (x__h460508[11] ? 12'hAAA : x__h460508) ; + assign x__h460508 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ; assign x__h48374 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; + assign x__h487047 = + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h484110 ; assign x__h487048 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h484111 ; + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484831 ; assign x__h487049 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484832 ; - assign x__h487050 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485547 ; - assign x__h508963 = sfd__h487888 << x__h508996 ; - assign x__h508996 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485546 ; + assign x__h508962 = sfd__h487887 << x__h508995 ; + assign x__h508995 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; - assign x__h547816 = sfd__h526882 << x__h547849 ; - assign x__h547849 = + assign x__h547815 = sfd__h526881 << x__h547848 ; + assign x__h547848 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; - assign x__h587120 = sfd__h566186 << x__h587153 ; - assign x__h587153 = + assign x__h587119 = sfd__h566185 << x__h587152 ; + assign x__h587152 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; - assign x__h608909 = + assign x__h608908 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h608920 : - a__h608372 ; - assign x__h608935 = a__h608372[63] ^ b__h608373[63] ; - assign x__h609549 = + _theResult___fst__h608919 : + a__h608371 ; + assign x__h608934 = a__h608371[63] ^ b__h608372[63] ; + assign x__h609548 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257 } ; - assign x__h619373 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h623642 = + assign x__h619372 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h623641 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h615931 : - v__h614703 ; - assign x__h623643 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621652 ; - assign x__h646272 = + rVal1__h615930 : + v__h614702 ; + assign x__h623642 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621651 ; + assign x__h646270 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h640776 : - v__h639702 ; - assign x__h646273 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644292 ; - assign x__h653733 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h653784 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h704087 = + rVal1__h640774 : + v__h639700 ; + assign x__h646271 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644290 ; + assign x__h653731 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h653782 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h704086 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; assign x__h710695 = { cause_code__h707757, 2'b0 } ; - assign x__h718765 = { 1'b0, csrf_spp_reg } ; - assign x__h722829 = + assign x__h718766 = { 1'b0, csrf_spp_reg } ; + assign x__h722831 = NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_snd_snd_snd_fst__h722652 : + y_avValue_snd_snd_snd_fst__h722654 : IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 ; assign x__h75783 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h318724 = + assign x_addr__h318723 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; @@ -30058,31 +30041,31 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h681438 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h697342 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h661521 = csrf_frm_reg ; - assign x_quotient__h479957 = + assign x_data_imm__h681436 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h697340 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h661519 = csrf_frm_reg ; + assign x_quotient__h479956 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h480780 : + q___1__h480779 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h616338 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h479958 = + assign x_reg_ifc__read__h616337 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h479957 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h480807 : + r___1__h480806 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h258434 = + assign y__h258433 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h626444 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; - assign y__h648781 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; - assign y__h653763 = ~x__h653733 ; - assign y__h658452 = + assign y__h626443 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; + assign y__h648779 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; + assign y__h653761 = ~x__h653731 ; + assign y__h658450 = { ~csrf_mideleg_11_reg, 1'd1, ~csrf_mideleg_9_7_reg, @@ -30090,52 +30073,52 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h692697 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h722605 = + assign y__h692695 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h722607 = NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_snd_snd_snd_snd_snd__h722658 : + y_avValue_snd_snd_snd_snd_snd__h722660 : IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 ; - assign y_avValue__h183777 = + assign y_avValue__h183776 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679 ; - assign y_avValue__h184496 = + assign y_avValue__h184495 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687 ; - assign y_avValue__h484111 = + assign y_avValue__h484110 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 ; - assign y_avValue__h484832 = + assign y_avValue__h484831 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 ; - assign y_avValue__h485547 = + assign y_avValue__h485546 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 ; - assign y_avValue__h615874 = + assign y_avValue__h615873 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11943 ; - assign y_avValue__h621652 = + assign y_avValue__h621651 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11952 ; - assign y_avValue__h640721 = + assign y_avValue__h640719 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12617 ; - assign y_avValue__h644292 = + assign y_avValue__h644290 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12626 ; - assign y_avValue_fst__h685981 = + assign y_avValue_fst__h685979 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h692684 : + spec_bits__h692682 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h721559 = + assign y_avValue_fst__h721561 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30149,10 +30132,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h722501 = + assign y_avValue_fst__h722503 = IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h722529 = + assign y_avValue_fst__h722531 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30165,7 +30148,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 : - y_avValue_fst__h722501 ; + y_avValue_fst__h722503 ; assign y_avValue_new_pc__h710461 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? base__h710680 + { 58'd0, x__h710695 } : @@ -30174,18 +30157,18 @@ module mkCore(CLK, (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? base__h710700 + { 58'd0, x__h710695 } : base__h710700 ; - assign y_avValue_snd_fst__h686255 = + assign y_avValue_snd_fst__h686253 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13533) ? - y_avValue_snd_fst__h686290 : + y_avValue_snd_fst__h686288 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h686290 = + assign y_avValue_snd_fst__h686288 = IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13593 ? - y_avValue_fst__h685981 : + y_avValue_fst__h685979 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h721993 = + assign y_avValue_snd_snd_snd_fst__h721995 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30199,7 +30182,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h722652 = + assign y_avValue_snd_snd_snd_fst__h722654 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30212,11 +30195,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 : - y_avValue_snd_snd_snd_fst__h722681 ; - assign y_avValue_snd_snd_snd_fst__h722681 = + y_avValue_snd_snd_snd_fst__h722683 ; + assign y_avValue_snd_snd_snd_fst__h722683 = IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h721999 = + assign y_avValue_snd_snd_snd_snd_snd__h722001 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30230,7 +30213,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h722658 = + assign y_avValue_snd_snd_snd_snd_snd__h722660 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30243,8 +30226,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 : - y_avValue_snd_snd_snd_snd_snd__h722687 ; - assign y_avValue_snd_snd_snd_snd_snd__h722687 = + y_avValue_snd_snd_snd_snd_snd__h722689 ; + assign y_avValue_snd_snd_snd_snd_snd__h722689 = IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -30263,28 +30246,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h200346 = + x__h200345 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -30300,28 +30283,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h290391 = + x__h290390 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -30331,10 +30314,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h294612 = + addr__h294611 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h294612 = + addr__h294611 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -30343,28 +30326,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h195303 = + curData__h195302 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -30387,265 +30370,265 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h296161 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h296160 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h296161 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h296160 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h616208 or - frm_csr__read__h616219 or - fcsr_csr__read__h616233 or - sstatus_csr__read__h616429 or - sie_csr__read__h616499 or - stvec_csr__read__h616542 or - scounteren_csr__read__h616595 or + fflags_csr__read__h616207 or + frm_csr__read__h616218 or + fcsr_csr__read__h616232 or + sstatus_csr__read__h616428 or + sie_csr__read__h616498 or + stvec_csr__read__h616541 or + scounteren_csr__read__h616594 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616733 or + scause_csr__read__h616732 or csrf_stval_csr or - sip_csr__read__h616873 or - satp_csr__read__h616936 or - mstatus_csr__read__h617079 or - medeleg_csr__read__h617227 or - mideleg_csr__read__h617322 or - mie_csr__read__h617446 or - mtvec_csr__read__h617528 or - mcounteren_csr__read__h617620 or + sip_csr__read__h616872 or + satp_csr__read__h616935 or + mstatus_csr__read__h617078 or + medeleg_csr__read__h617226 or + mideleg_csr__read__h617321 or + mie_csr__read__h617445 or + mtvec_csr__read__h617527 or + mcounteren_csr__read__h617619 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617875 or + mcause_csr__read__h617874 or csrf_mtval_csr or - mip_csr__read__h618108 or + mip_csr__read__h618107 or csrf_rg_tselect or - rg_tdata1__read__h619063 or + rg_tdata1__read__h619062 or csrf_rg_tdata2 or csrf_rg_tdata3 or - x_reg_ifc__read__h616338 or - n__read__h618212 or n__read__h618403 or csrf_time_reg) + x_reg_ifc__read__h616337 or + n__read__h618211 or n__read__h618402 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h615931 = fflags_csr__read__h616208; - 12'd2: rVal1__h615931 = frm_csr__read__h616219; - 12'd3: rVal1__h615931 = fcsr_csr__read__h616233; - 12'd256: rVal1__h615931 = sstatus_csr__read__h616429; - 12'd260: rVal1__h615931 = sie_csr__read__h616499; - 12'd261: rVal1__h615931 = stvec_csr__read__h616542; - 12'd262: rVal1__h615931 = scounteren_csr__read__h616595; - 12'd320: rVal1__h615931 = csrf_sscratch_csr; - 12'd321: rVal1__h615931 = csrf_sepc_csr; - 12'd322: rVal1__h615931 = scause_csr__read__h616733; - 12'd323: rVal1__h615931 = csrf_stval_csr; - 12'd324: rVal1__h615931 = sip_csr__read__h616873; - 12'd384: rVal1__h615931 = satp_csr__read__h616936; - 12'd768: rVal1__h615931 = mstatus_csr__read__h617079; - 12'd769: rVal1__h615931 = 64'h800000000014112D; - 12'd770: rVal1__h615931 = medeleg_csr__read__h617227; - 12'd771: rVal1__h615931 = mideleg_csr__read__h617322; - 12'd772: rVal1__h615931 = mie_csr__read__h617446; - 12'd773: rVal1__h615931 = mtvec_csr__read__h617528; - 12'd774: rVal1__h615931 = mcounteren_csr__read__h617620; - 12'd832: rVal1__h615931 = csrf_mscratch_csr; - 12'd833: rVal1__h615931 = csrf_mepc_csr; - 12'd834: rVal1__h615931 = mcause_csr__read__h617875; - 12'd835: rVal1__h615931 = csrf_mtval_csr; - 12'd836: rVal1__h615931 = mip_csr__read__h618108; - 12'd1952: rVal1__h615931 = csrf_rg_tselect; - 12'd1953: rVal1__h615931 = rg_tdata1__read__h619063; - 12'd1954: rVal1__h615931 = csrf_rg_tdata2; - 12'd1955: rVal1__h615931 = csrf_rg_tdata3; + 12'd1: rVal1__h615930 = fflags_csr__read__h616207; + 12'd2: rVal1__h615930 = frm_csr__read__h616218; + 12'd3: rVal1__h615930 = fcsr_csr__read__h616232; + 12'd256: rVal1__h615930 = sstatus_csr__read__h616428; + 12'd260: rVal1__h615930 = sie_csr__read__h616498; + 12'd261: rVal1__h615930 = stvec_csr__read__h616541; + 12'd262: rVal1__h615930 = scounteren_csr__read__h616594; + 12'd320: rVal1__h615930 = csrf_sscratch_csr; + 12'd321: rVal1__h615930 = csrf_sepc_csr; + 12'd322: rVal1__h615930 = scause_csr__read__h616732; + 12'd323: rVal1__h615930 = csrf_stval_csr; + 12'd324: rVal1__h615930 = sip_csr__read__h616872; + 12'd384: rVal1__h615930 = satp_csr__read__h616935; + 12'd768: rVal1__h615930 = mstatus_csr__read__h617078; + 12'd769: rVal1__h615930 = 64'h800000000014112D; + 12'd770: rVal1__h615930 = medeleg_csr__read__h617226; + 12'd771: rVal1__h615930 = mideleg_csr__read__h617321; + 12'd772: rVal1__h615930 = mie_csr__read__h617445; + 12'd773: rVal1__h615930 = mtvec_csr__read__h617527; + 12'd774: rVal1__h615930 = mcounteren_csr__read__h617619; + 12'd832: rVal1__h615930 = csrf_mscratch_csr; + 12'd833: rVal1__h615930 = csrf_mepc_csr; + 12'd834: rVal1__h615930 = mcause_csr__read__h617874; + 12'd835: rVal1__h615930 = csrf_mtval_csr; + 12'd836: rVal1__h615930 = mip_csr__read__h618107; + 12'd1952: rVal1__h615930 = csrf_rg_tselect; + 12'd1953: rVal1__h615930 = rg_tdata1__read__h619062; + 12'd1954: rVal1__h615930 = csrf_rg_tdata2; + 12'd1955: rVal1__h615930 = csrf_rg_tdata3; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h615931 = 64'd0; - 12'd2049: rVal1__h615931 = x_reg_ifc__read__h616338; - 12'd2816, 12'd3072: rVal1__h615931 = n__read__h618212; - 12'd2818, 12'd3074: rVal1__h615931 = n__read__h618403; - 12'd3073: rVal1__h615931 = csrf_time_reg; - default: rVal1__h615931 = 64'b0; + rVal1__h615930 = 64'd0; + 12'd2049: rVal1__h615930 = x_reg_ifc__read__h616337; + 12'd2816, 12'd3072: rVal1__h615930 = n__read__h618211; + 12'd2818, 12'd3074: rVal1__h615930 = n__read__h618402; + 12'd3073: rVal1__h615930 = csrf_time_reg; + default: rVal1__h615930 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h616208 or - frm_csr__read__h616219 or - fcsr_csr__read__h616233 or - sstatus_csr__read__h616429 or - sie_csr__read__h616499 or - stvec_csr__read__h616542 or - scounteren_csr__read__h616595 or + fflags_csr__read__h616207 or + frm_csr__read__h616218 or + fcsr_csr__read__h616232 or + sstatus_csr__read__h616428 or + sie_csr__read__h616498 or + stvec_csr__read__h616541 or + scounteren_csr__read__h616594 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616733 or + scause_csr__read__h616732 or csrf_stval_csr or - sip_csr__read__h616873 or - satp_csr__read__h616936 or - mstatus_csr__read__h617079 or - medeleg_csr__read__h617227 or - mideleg_csr__read__h617322 or - mie_csr__read__h617446 or - mtvec_csr__read__h617528 or - mcounteren_csr__read__h617620 or + sip_csr__read__h616872 or + satp_csr__read__h616935 or + mstatus_csr__read__h617078 or + medeleg_csr__read__h617226 or + mideleg_csr__read__h617321 or + mie_csr__read__h617445 or + mtvec_csr__read__h617527 or + mcounteren_csr__read__h617619 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617875 or + mcause_csr__read__h617874 or csrf_mtval_csr or - mip_csr__read__h618108 or + mip_csr__read__h618107 or csrf_rg_tselect or - rg_tdata1__read__h619063 or + rg_tdata1__read__h619062 or csrf_rg_tdata2 or csrf_rg_tdata3 or - x_reg_ifc__read__h616338 or - n__read__h618212 or n__read__h618403 or csrf_time_reg) + x_reg_ifc__read__h616337 or + n__read__h618211 or n__read__h618402 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h640776 = fflags_csr__read__h616208; - 12'd2: rVal1__h640776 = frm_csr__read__h616219; - 12'd3: rVal1__h640776 = fcsr_csr__read__h616233; - 12'd256: rVal1__h640776 = sstatus_csr__read__h616429; - 12'd260: rVal1__h640776 = sie_csr__read__h616499; - 12'd261: rVal1__h640776 = stvec_csr__read__h616542; - 12'd262: rVal1__h640776 = scounteren_csr__read__h616595; - 12'd320: rVal1__h640776 = csrf_sscratch_csr; - 12'd321: rVal1__h640776 = csrf_sepc_csr; - 12'd322: rVal1__h640776 = scause_csr__read__h616733; - 12'd323: rVal1__h640776 = csrf_stval_csr; - 12'd324: rVal1__h640776 = sip_csr__read__h616873; - 12'd384: rVal1__h640776 = satp_csr__read__h616936; - 12'd768: rVal1__h640776 = mstatus_csr__read__h617079; - 12'd769: rVal1__h640776 = 64'h800000000014112D; - 12'd770: rVal1__h640776 = medeleg_csr__read__h617227; - 12'd771: rVal1__h640776 = mideleg_csr__read__h617322; - 12'd772: rVal1__h640776 = mie_csr__read__h617446; - 12'd773: rVal1__h640776 = mtvec_csr__read__h617528; - 12'd774: rVal1__h640776 = mcounteren_csr__read__h617620; - 12'd832: rVal1__h640776 = csrf_mscratch_csr; - 12'd833: rVal1__h640776 = csrf_mepc_csr; - 12'd834: rVal1__h640776 = mcause_csr__read__h617875; - 12'd835: rVal1__h640776 = csrf_mtval_csr; - 12'd836: rVal1__h640776 = mip_csr__read__h618108; - 12'd1952: rVal1__h640776 = csrf_rg_tselect; - 12'd1953: rVal1__h640776 = rg_tdata1__read__h619063; - 12'd1954: rVal1__h640776 = csrf_rg_tdata2; - 12'd1955: rVal1__h640776 = csrf_rg_tdata3; + 12'd1: rVal1__h640774 = fflags_csr__read__h616207; + 12'd2: rVal1__h640774 = frm_csr__read__h616218; + 12'd3: rVal1__h640774 = fcsr_csr__read__h616232; + 12'd256: rVal1__h640774 = sstatus_csr__read__h616428; + 12'd260: rVal1__h640774 = sie_csr__read__h616498; + 12'd261: rVal1__h640774 = stvec_csr__read__h616541; + 12'd262: rVal1__h640774 = scounteren_csr__read__h616594; + 12'd320: rVal1__h640774 = csrf_sscratch_csr; + 12'd321: rVal1__h640774 = csrf_sepc_csr; + 12'd322: rVal1__h640774 = scause_csr__read__h616732; + 12'd323: rVal1__h640774 = csrf_stval_csr; + 12'd324: rVal1__h640774 = sip_csr__read__h616872; + 12'd384: rVal1__h640774 = satp_csr__read__h616935; + 12'd768: rVal1__h640774 = mstatus_csr__read__h617078; + 12'd769: rVal1__h640774 = 64'h800000000014112D; + 12'd770: rVal1__h640774 = medeleg_csr__read__h617226; + 12'd771: rVal1__h640774 = mideleg_csr__read__h617321; + 12'd772: rVal1__h640774 = mie_csr__read__h617445; + 12'd773: rVal1__h640774 = mtvec_csr__read__h617527; + 12'd774: rVal1__h640774 = mcounteren_csr__read__h617619; + 12'd832: rVal1__h640774 = csrf_mscratch_csr; + 12'd833: rVal1__h640774 = csrf_mepc_csr; + 12'd834: rVal1__h640774 = mcause_csr__read__h617874; + 12'd835: rVal1__h640774 = csrf_mtval_csr; + 12'd836: rVal1__h640774 = mip_csr__read__h618107; + 12'd1952: rVal1__h640774 = csrf_rg_tselect; + 12'd1953: rVal1__h640774 = rg_tdata1__read__h619062; + 12'd1954: rVal1__h640774 = csrf_rg_tdata2; + 12'd1955: rVal1__h640774 = csrf_rg_tdata3; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h640776 = 64'd0; - 12'd2049: rVal1__h640776 = x_reg_ifc__read__h616338; - 12'd2816, 12'd3072: rVal1__h640776 = n__read__h618212; - 12'd2818, 12'd3074: rVal1__h640776 = n__read__h618403; - 12'd3073: rVal1__h640776 = csrf_time_reg; - default: rVal1__h640776 = 64'b0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h396416 = 8'd255; - 3'd2: - _theResult___fst_exp__h396416 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h396416 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h396416 = 8'd254; - default: _theResult___fst_exp__h396416 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h350717 = 8'd255; - 3'd2: - _theResult___fst_exp__h350717 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd254 : - 8'd255; - 3'd3: - _theResult___fst_exp__h350717 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 8'd255 : - 8'd254; - 3'd4: _theResult___fst_exp__h350717 = 8'd254; - default: _theResult___fst_exp__h350717 = 8'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h350718 = 23'd0; - 3'd2: - _theResult___fst_sfd__h350718 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h350718 = - coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h350718 = 23'd8388607; - default: _theResult___fst_sfd__h350718 = 23'd0; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h396417 = 23'd0; - 3'd2: - _theResult___fst_sfd__h396417 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd8388607 : - 23'd0; - 3'd3: - _theResult___fst_sfd__h396417 = - coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - 23'd0 : - 23'd8388607; - 3'd4: _theResult___fst_sfd__h396417 = 23'd8388607; - default: _theResult___fst_sfd__h396417 = 23'd0; + rVal1__h640774 = 64'd0; + 12'd2049: rVal1__h640774 = x_reg_ifc__read__h616337; + 12'd2816, 12'd3072: rVal1__h640774 = n__read__h618211; + 12'd2818, 12'd3074: rVal1__h640774 = n__read__h618402; + 12'd3073: rVal1__h640774 = csrf_time_reg; + default: rVal1__h640774 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h442111 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h442110 = 8'd255; 3'd2: - _theResult___fst_exp__h442111 = + _theResult___fst_exp__h442110 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h442111 = + _theResult___fst_exp__h442110 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h442111 = 8'd254; - default: _theResult___fst_exp__h442111 = 8'd0; + 3'd4: _theResult___fst_exp__h442110 = 8'd254; + default: _theResult___fst_exp__h442110 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h350716 = 8'd255; + 3'd2: + _theResult___fst_exp__h350716 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h350716 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h350716 = 8'd254; + default: _theResult___fst_exp__h350716 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h350717 = 23'd0; + 3'd2: + _theResult___fst_sfd__h350717 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h350717 = + coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h350717 = 23'd8388607; + default: _theResult___fst_sfd__h350717 = 23'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_exp__h396415 = 8'd255; + 3'd2: + _theResult___fst_exp__h396415 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd254 : + 8'd255; + 3'd3: + _theResult___fst_exp__h396415 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 8'd255 : + 8'd254; + 3'd4: _theResult___fst_exp__h396415 = 8'd254; + default: _theResult___fst_exp__h396415 = 8'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0, 3'd1: _theResult___fst_sfd__h396416 = 23'd0; + 3'd2: + _theResult___fst_sfd__h396416 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd8388607 : + 23'd0; + 3'd3: + _theResult___fst_sfd__h396416 = + coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? + 23'd0 : + 23'd8388607; + 3'd4: _theResult___fst_sfd__h396416 = 23'd8388607; + default: _theResult___fst_sfd__h396416 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h442112 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h442111 = 23'd0; 3'd2: - _theResult___fst_sfd__h442112 = + _theResult___fst_sfd__h442111 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h442112 = + _theResult___fst_sfd__h442111 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h442112 = 23'd8388607; - default: _theResult___fst_sfd__h442112 = 23'd0; + 3'd4: _theResult___fst_sfd__h442111 = 23'd8388607; + default: _theResult___fst_sfd__h442111 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -31046,446 +31029,446 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359454 or - _theResult___fst_exp__h367502 or - out_exp__h367947 or _theResult___exp__h367944) + always@(guard__h359453 or + _theResult___fst_exp__h367501 or + out_exp__h367946 or _theResult___exp__h367943) begin - case (guard__h359454) + case (guard__h359453) 2'b0, 2'b01: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 = - _theResult___fst_exp__h367502; + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q25 = + _theResult___fst_exp__h367501; 2'b10: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 = - out_exp__h367947; + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q25 = + out_exp__h367946; 2'b11: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 = - _theResult___exp__h367944; + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q25 = + _theResult___exp__h367943; endcase end - always@(guard__h359454 or - _theResult___fst_exp__h367502 or _theResult___exp__h367944) + always@(guard__h359453 or + _theResult___fst_exp__h367501 or _theResult___exp__h367943) begin - case (guard__h359454) + case (guard__h359453) 2'b0: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26 = - _theResult___fst_exp__h367502; + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q26 = + _theResult___fst_exp__h367501; 2'b01, 2'b10, 2'b11: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26 = - _theResult___exp__h367944; + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q26 = + _theResult___exp__h367943; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 or - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26 or + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q25 or + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q26 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or - _theResult___fst_exp__h367502) + _theResult___fst_exp__h367501) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h368022 = - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25; + _theResult___fst_exp__h368021 = + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q25; 3'd1: - _theResult___fst_exp__h368022 = - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26; + _theResult___fst_exp__h368021 = + CASE_guard59453_0b0_theResult___fst_exp67501_0_ETC__q26; 3'd2: - _theResult___fst_exp__h368022 = + _theResult___fst_exp__h368021 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; 3'd3: - _theResult___fst_exp__h368022 = + _theResult___fst_exp__h368021 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; - 3'd4: _theResult___fst_exp__h368022 = _theResult___fst_exp__h367502; - default: _theResult___fst_exp__h368022 = 8'd0; + 3'd4: _theResult___fst_exp__h368021 = _theResult___fst_exp__h367501; + default: _theResult___fst_exp__h368021 = 8'd0; endcase end - always@(guard__h350745 or - _theResult___fst_exp__h358846 or - out_exp__h359365 or _theResult___exp__h359362) + always@(guard__h350744 or + _theResult___fst_exp__h358845 or + out_exp__h359364 or _theResult___exp__h359361) begin - case (guard__h350745) + case (guard__h350744) 2'b0, 2'b01: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 = - _theResult___fst_exp__h358846; + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q27 = + _theResult___fst_exp__h358845; 2'b10: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 = - out_exp__h359365; + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q27 = + out_exp__h359364; 2'b11: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 = - _theResult___exp__h359362; + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q27 = + _theResult___exp__h359361; endcase end - always@(guard__h350745 or - _theResult___fst_exp__h358846 or _theResult___exp__h359362) + always@(guard__h350744 or + _theResult___fst_exp__h358845 or _theResult___exp__h359361) begin - case (guard__h350745) + case (guard__h350744) 2'b0: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28 = - _theResult___fst_exp__h358846; + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q28 = + _theResult___fst_exp__h358845; 2'b01, 2'b10, 2'b11: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28 = - _theResult___exp__h359362; + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q28 = + _theResult___exp__h359361; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 or - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28 or + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q27 or + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q28 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 or - _theResult___fst_exp__h358846) + _theResult___fst_exp__h358845) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h359440 = - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27; + _theResult___fst_exp__h359439 = + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q27; 3'd1: - _theResult___fst_exp__h359440 = - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28; + _theResult___fst_exp__h359439 = + CASE_guard50744_0b0_theResult___fst_exp58845_0_ETC__q28; 3'd2: - _theResult___fst_exp__h359440 = + _theResult___fst_exp__h359439 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406; 3'd3: - _theResult___fst_exp__h359440 = + _theResult___fst_exp__h359439 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409; - 3'd4: _theResult___fst_exp__h359440 = _theResult___fst_exp__h358846; - default: _theResult___fst_exp__h359440 = 8'd0; + 3'd4: _theResult___fst_exp__h359439 = _theResult___fst_exp__h358845; + default: _theResult___fst_exp__h359439 = 8'd0; endcase end - always@(guard__h368384 or - _theResult___fst_exp__h376612 or - out_exp__h377131 or _theResult___exp__h377128) + always@(guard__h368383 or + _theResult___fst_exp__h376611 or + out_exp__h377130 or _theResult___exp__h377127) begin - case (guard__h368384) + case (guard__h368383) 2'b0, 2'b01: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 = - _theResult___fst_exp__h376612; + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q33 = + _theResult___fst_exp__h376611; 2'b10: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 = - out_exp__h377131; + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q33 = + out_exp__h377130; 2'b11: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 = - _theResult___exp__h377128; + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q33 = + _theResult___exp__h377127; endcase end - always@(guard__h368384 or - _theResult___fst_exp__h376612 or _theResult___exp__h377128) + always@(guard__h368383 or + _theResult___fst_exp__h376611 or _theResult___exp__h377127) begin - case (guard__h368384) + case (guard__h368383) 2'b0: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34 = - _theResult___fst_exp__h376612; + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q34 = + _theResult___fst_exp__h376611; 2'b01, 2'b10, 2'b11: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34 = - _theResult___exp__h377128; + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q34 = + _theResult___exp__h377127; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 or - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34 or + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q33 or + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q34 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 or - _theResult___fst_exp__h376612) + _theResult___fst_exp__h376611) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h377206 = - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33; + _theResult___fst_exp__h377205 = + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q33; 3'd1: - _theResult___fst_exp__h377206 = - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34; + _theResult___fst_exp__h377205 = + CASE_guard68383_0b0_theResult___fst_exp76611_0_ETC__q34; 3'd2: - _theResult___fst_exp__h377206 = + _theResult___fst_exp__h377205 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953; 3'd3: - _theResult___fst_exp__h377206 = + _theResult___fst_exp__h377205 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955; - 3'd4: _theResult___fst_exp__h377206 = _theResult___fst_exp__h376612; - default: _theResult___fst_exp__h377206 = 8'd0; + 3'd4: _theResult___fst_exp__h377205 = _theResult___fst_exp__h376611; + default: _theResult___fst_exp__h377205 = 8'd0; endcase end - always@(guard__h377220 or - _theResult___fst_exp__h385297 or - out_exp__h385767 or _theResult___exp__h385764) + always@(guard__h377219 or + _theResult___fst_exp__h385296 or + out_exp__h385766 or _theResult___exp__h385763) begin - case (guard__h377220) + case (guard__h377219) 2'b0, 2'b01: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 = - _theResult___fst_exp__h385297; + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q38 = + _theResult___fst_exp__h385296; 2'b10: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 = - out_exp__h385767; + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q38 = + out_exp__h385766; 2'b11: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 = - _theResult___exp__h385764; + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q38 = + _theResult___exp__h385763; endcase end - always@(guard__h377220 or - _theResult___fst_exp__h385297 or _theResult___exp__h385764) + always@(guard__h377219 or + _theResult___fst_exp__h385296 or _theResult___exp__h385763) begin - case (guard__h377220) + case (guard__h377219) 2'b0: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39 = - _theResult___fst_exp__h385297; + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q39 = + _theResult___fst_exp__h385296; 2'b01, 2'b10, 2'b11: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39 = - _theResult___exp__h385764; + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q39 = + _theResult___exp__h385763; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 or - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39 or + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q38 or + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q39 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___fst_exp__h385297) + _theResult___fst_exp__h385296) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h385842 = - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38; + _theResult___fst_exp__h385841 = + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q38; 3'd1: - _theResult___fst_exp__h385842 = - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39; + _theResult___fst_exp__h385841 = + CASE_guard77219_0b0_theResult___fst_exp85296_0_ETC__q39; 3'd2: - _theResult___fst_exp__h385842 = + _theResult___fst_exp__h385841 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_exp__h385842 = + _theResult___fst_exp__h385841 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_exp__h385842 = _theResult___fst_exp__h385297; - default: _theResult___fst_exp__h385842 = 8'd0; + 3'd4: _theResult___fst_exp__h385841 = _theResult___fst_exp__h385296; + default: _theResult___fst_exp__h385841 = 8'd0; endcase end - always@(guard__h359454 or - _theResult___snd__h367453 or - out_sfd__h367948 or _theResult___sfd__h367945) + always@(guard__h359453 or + _theResult___snd__h367452 or + out_sfd__h367947 or _theResult___sfd__h367944) begin - case (guard__h359454) + case (guard__h359453) 2'b0, 2'b01: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 = - _theResult___snd__h367453[56:34]; + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q40 = + _theResult___snd__h367452[56:34]; 2'b10: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 = - out_sfd__h367948; + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q40 = + out_sfd__h367947; 2'b11: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 = - _theResult___sfd__h367945; + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q40 = + _theResult___sfd__h367944; endcase end - always@(guard__h359454 or - _theResult___snd__h367453 or _theResult___sfd__h367945) + always@(guard__h359453 or + _theResult___snd__h367452 or _theResult___sfd__h367944) begin - case (guard__h359454) + case (guard__h359453) 2'b0: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41 = - _theResult___snd__h367453[56:34]; + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q41 = + _theResult___snd__h367452[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41 = - _theResult___sfd__h367945; + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q41 = + _theResult___sfd__h367944; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 or - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41 or + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q40 or + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q41 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or - _theResult___snd__h367453) + _theResult___snd__h367452) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h368023 = - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40; + _theResult___fst_sfd__h368022 = + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q40; 3'd1: - _theResult___fst_sfd__h368023 = - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41; + _theResult___fst_sfd__h368022 = + CASE_guard59453_0b0_theResult___snd67452_BITS__ETC__q41; 3'd2: - _theResult___fst_sfd__h368023 = + _theResult___fst_sfd__h368022 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; 3'd3: - _theResult___fst_sfd__h368023 = + _theResult___fst_sfd__h368022 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074; - 3'd4: _theResult___fst_sfd__h368023 = _theResult___snd__h367453[56:34]; - default: _theResult___fst_sfd__h368023 = 23'd0; + 3'd4: _theResult___fst_sfd__h368022 = _theResult___snd__h367452[56:34]; + default: _theResult___fst_sfd__h368022 = 23'd0; endcase end - always@(guard__h350745 or - sfdin__h358840 or out_sfd__h359366 or _theResult___sfd__h359363) + always@(guard__h350744 or + sfdin__h358839 or out_sfd__h359365 or _theResult___sfd__h359362) begin - case (guard__h350745) + case (guard__h350744) 2'b0, 2'b01: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 = - sfdin__h358840[56:34]; + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q42 = + sfdin__h358839[56:34]; 2'b10: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 = - out_sfd__h359366; + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q42 = + out_sfd__h359365; 2'b11: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h359363; + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h359362; endcase end - always@(guard__h350745 or sfdin__h358840 or _theResult___sfd__h359363) + always@(guard__h350744 or sfdin__h358839 or _theResult___sfd__h359362) begin - case (guard__h350745) + case (guard__h350744) 2'b0: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43 = - sfdin__h358840[56:34]; + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q43 = + sfdin__h358839[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h359363; + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h359362; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 or - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43 or + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q42 or + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q43 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or - sfdin__h358840) + sfdin__h358839) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h359441 = - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42; + _theResult___fst_sfd__h359440 = + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q42; 3'd1: - _theResult___fst_sfd__h359441 = - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43; + _theResult___fst_sfd__h359440 = + CASE_guard50744_0b0_sfdin58839_BITS_56_TO_34_0_ETC__q43; 3'd2: - _theResult___fst_sfd__h359441 = + _theResult___fst_sfd__h359440 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; 3'd3: - _theResult___fst_sfd__h359441 = + _theResult___fst_sfd__h359440 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; - 3'd4: _theResult___fst_sfd__h359441 = sfdin__h358840[56:34]; - default: _theResult___fst_sfd__h359441 = 23'd0; + 3'd4: _theResult___fst_sfd__h359440 = sfdin__h358839[56:34]; + default: _theResult___fst_sfd__h359440 = 23'd0; endcase end - always@(guard__h368384 or - sfdin__h376606 or out_sfd__h377132 or _theResult___sfd__h377129) + always@(guard__h368383 or + sfdin__h376605 or out_sfd__h377131 or _theResult___sfd__h377128) begin - case (guard__h368384) + case (guard__h368383) 2'b0, 2'b01: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 = - sfdin__h376606[56:34]; + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q44 = + sfdin__h376605[56:34]; 2'b10: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 = - out_sfd__h377132; + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q44 = + out_sfd__h377131; 2'b11: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h377129; + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h377128; endcase end - always@(guard__h368384 or sfdin__h376606 or _theResult___sfd__h377129) + always@(guard__h368383 or sfdin__h376605 or _theResult___sfd__h377128) begin - case (guard__h368384) + case (guard__h368383) 2'b0: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45 = - sfdin__h376606[56:34]; + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q45 = + sfdin__h376605[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45 = - _theResult___sfd__h377129; + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q45 = + _theResult___sfd__h377128; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 or - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45 or + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q44 or + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q45 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 or - sfdin__h376606) + sfdin__h376605) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h377207 = - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44; + _theResult___fst_sfd__h377206 = + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q44; 3'd1: - _theResult___fst_sfd__h377207 = - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45; + _theResult___fst_sfd__h377206 = + CASE_guard68383_0b0_sfdin76605_BITS_56_TO_34_0_ETC__q45; 3'd2: - _theResult___fst_sfd__h377207 = + _theResult___fst_sfd__h377206 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099; 3'd3: - _theResult___fst_sfd__h377207 = + _theResult___fst_sfd__h377206 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101; - 3'd4: _theResult___fst_sfd__h377207 = sfdin__h376606[56:34]; - default: _theResult___fst_sfd__h377207 = 23'd0; + 3'd4: _theResult___fst_sfd__h377206 = sfdin__h376605[56:34]; + default: _theResult___fst_sfd__h377206 = 23'd0; endcase end - always@(guard__h377220 or - _theResult___snd__h385243 or - out_sfd__h385768 or _theResult___sfd__h385765) + always@(guard__h377219 or + _theResult___snd__h385242 or + out_sfd__h385767 or _theResult___sfd__h385764) begin - case (guard__h377220) + case (guard__h377219) 2'b0, 2'b01: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 = - _theResult___snd__h385243[56:34]; + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q46 = + _theResult___snd__h385242[56:34]; 2'b10: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 = - out_sfd__h385768; + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q46 = + out_sfd__h385767; 2'b11: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 = - _theResult___sfd__h385765; + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q46 = + _theResult___sfd__h385764; endcase end - always@(guard__h377220 or - _theResult___snd__h385243 or _theResult___sfd__h385765) + always@(guard__h377219 or + _theResult___snd__h385242 or _theResult___sfd__h385764) begin - case (guard__h377220) + case (guard__h377219) 2'b0: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47 = - _theResult___snd__h385243[56:34]; + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q47 = + _theResult___snd__h385242[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47 = - _theResult___sfd__h385765; + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q47 = + _theResult___sfd__h385764; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 or - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47 or + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q46 or + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q47 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or - _theResult___snd__h385243) + _theResult___snd__h385242) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h385843 = - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46; + _theResult___fst_sfd__h385842 = + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q46; 3'd1: - _theResult___fst_sfd__h385843 = - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47; + _theResult___fst_sfd__h385842 = + CASE_guard77219_0b0_theResult___snd85242_BITS__ETC__q47; 3'd2: - _theResult___fst_sfd__h385843 = + _theResult___fst_sfd__h385842 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; 3'd3: - _theResult___fst_sfd__h385843 = + _theResult___fst_sfd__h385842 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; - 3'd4: _theResult___fst_sfd__h385843 = _theResult___snd__h385243[56:34]; - default: _theResult___fst_sfd__h385843 = 23'd0; + 3'd4: _theResult___fst_sfd__h385842 = _theResult___snd__h385242[56:34]; + default: _theResult___fst_sfd__h385842 = 23'd0; endcase end - always@(guard__h350745 or + always@(guard__h350744 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350745) + case (guard__h350744) 2'b0, 2'b01, 2'b10: - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard50744_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h350745 == 2'b11 && + CASE_guard50744_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h350744 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h350745) + CASE_guard50744_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h350744) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard50744_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - (guard__h350745 == 2'b0) ? + (guard__h350744 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h350745 == 2'b01 || guard__h350745 == 2'b10 || - guard__h350745 == 2'b11) && + (guard__h350744 == 2'b01 || guard__h350744 == 2'b10 || + guard__h350744 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = @@ -31496,34 +31479,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h350745 or + always@(guard__h350744 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350745) + case (guard__h350744) 2'b0, 2'b01, 2'b10: - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard50744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h350745 != 2'b11 || + CASE_guard50744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h350744 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h350745) + CASE_guard50744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h350744) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + CASE_guard50744_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - (guard__h350745 == 2'b0) ? + (guard__h350744 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h350745 != 2'b01 && guard__h350745 != 2'b10 && - guard__h350745 != 2'b11 || + guard__h350744 != 2'b01 && guard__h350744 != 2'b10 && + guard__h350744 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = @@ -31534,34 +31517,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359454 or + always@(guard__h359453 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359454) + case (guard__h359453) 2'b0, 2'b01, 2'b10: - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + CASE_guard59453_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = - guard__h359454 == 2'b11 && + CASE_guard59453_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + guard__h359453 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or - guard__h359454) + CASE_guard59453_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or + guard__h359453) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; + CASE_guard59453_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - (guard__h359454 == 2'b0) ? + (guard__h359453 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h359454 == 2'b01 || guard__h359454 == 2'b10 || - guard__h359454 == 2'b11) && + (guard__h359453 == 2'b01 || guard__h359453 == 2'b10 || + guard__h359453 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = @@ -31572,34 +31555,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359454 or + always@(guard__h359453 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359454) + case (guard__h359453) 2'b0, 2'b01, 2'b10: - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + CASE_guard59453_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = - guard__h359454 != 2'b11 || + CASE_guard59453_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + guard__h359453 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or - guard__h359454) + CASE_guard59453_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or + guard__h359453) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; + CASE_guard59453_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - (guard__h359454 == 2'b0) ? + (guard__h359453 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h359454 != 2'b01 && guard__h359454 != 2'b10 && - guard__h359454 != 2'b11 || + guard__h359453 != 2'b01 && guard__h359453 != 2'b10 && + guard__h359453 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = @@ -31610,34 +31593,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368384 or + always@(guard__h368383 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368384) + case (guard__h368383) 2'b0, 2'b01, 2'b10: - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h368384 == 2'b11 && + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h368383 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h368384) + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h368383) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - (guard__h368384 == 2'b0) ? + (guard__h368383 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h368384 == 2'b01 || guard__h368384 == 2'b10 || - guard__h368384 == 2'b11) && + (guard__h368383 == 2'b01 || guard__h368383 == 2'b10 || + guard__h368383 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = @@ -31648,34 +31631,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368384 or + always@(guard__h368383 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368384) + case (guard__h368383) 2'b0, 2'b01, 2'b10: - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h368384 != 2'b11 || + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h368383 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h368384) + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h368383) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - (guard__h368384 == 2'b0) ? + (guard__h368383 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h368384 != 2'b01 && guard__h368384 != 2'b10 && - guard__h368384 != 2'b11 || + guard__h368383 != 2'b01 && guard__h368383 != 2'b10 && + guard__h368383 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = @@ -31686,34 +31669,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h377220 or + always@(guard__h377219 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h377220) + case (guard__h377219) 2'b0, 2'b01, 2'b10: - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + CASE_guard77219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = - guard__h377220 == 2'b11 && + CASE_guard77219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + guard__h377219 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or - guard__h377220) + CASE_guard77219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or + guard__h377219) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; + CASE_guard77219_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - (guard__h377220 == 2'b0) ? + (guard__h377219 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h377220 == 2'b01 || guard__h377220 == 2'b10 || - guard__h377220 == 2'b11) && + (guard__h377219 == 2'b01 || guard__h377219 == 2'b10 || + guard__h377219 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = @@ -31724,34 +31707,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h377220 or + always@(guard__h377219 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h377220) + case (guard__h377219) 2'b0, 2'b01, 2'b10: - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + CASE_guard77219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = - guard__h377220 != 2'b11 || + CASE_guard77219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + guard__h377219 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or - guard__h377220) + CASE_guard77219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or + guard__h377219) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; + CASE_guard77219_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - (guard__h377220 == 2'b0) ? + (guard__h377219 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h377220 != 2'b01 && guard__h377220 != 2'b10 && - guard__h377220 != 2'b11 || + guard__h377219 != 2'b01 && guard__h377219 != 2'b10 && + guard__h377219 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = @@ -31775,446 +31758,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h405151 or - _theResult___fst_exp__h413199 or - out_exp__h413644 or _theResult___exp__h413641) + always@(guard__h405150 or + _theResult___fst_exp__h413198 or + out_exp__h413643 or _theResult___exp__h413640) begin - case (guard__h405151) + case (guard__h405150) 2'b0, 2'b01: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 = - _theResult___fst_exp__h413199; + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q60 = + _theResult___fst_exp__h413198; 2'b10: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 = - out_exp__h413644; + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q60 = + out_exp__h413643; 2'b11: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 = - _theResult___exp__h413641; + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q60 = + _theResult___exp__h413640; endcase end - always@(guard__h405151 or - _theResult___fst_exp__h413199 or _theResult___exp__h413641) + always@(guard__h405150 or + _theResult___fst_exp__h413198 or _theResult___exp__h413640) begin - case (guard__h405151) + case (guard__h405150) 2'b0: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61 = - _theResult___fst_exp__h413199; + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q61 = + _theResult___fst_exp__h413198; 2'b01, 2'b10, 2'b11: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61 = - _theResult___exp__h413641; + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q61 = + _theResult___exp__h413640; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 or - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61 or + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q60 or + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q61 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 or - _theResult___fst_exp__h413199) + _theResult___fst_exp__h413198) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h413719 = - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60; + _theResult___fst_exp__h413718 = + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q60; 3'd1: - _theResult___fst_exp__h413719 = - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61; + _theResult___fst_exp__h413718 = + CASE_guard05150_0b0_theResult___fst_exp13198_0_ETC__q61; 3'd2: - _theResult___fst_exp__h413719 = + _theResult___fst_exp__h413718 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020; 3'd3: - _theResult___fst_exp__h413719 = + _theResult___fst_exp__h413718 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022; - 3'd4: _theResult___fst_exp__h413719 = _theResult___fst_exp__h413199; - default: _theResult___fst_exp__h413719 = 8'd0; + 3'd4: _theResult___fst_exp__h413718 = _theResult___fst_exp__h413198; + default: _theResult___fst_exp__h413718 = 8'd0; endcase end - always@(guard__h396444 or - _theResult___fst_exp__h404543 or - out_exp__h405062 or _theResult___exp__h405059) + always@(guard__h396443 or + _theResult___fst_exp__h404542 or + out_exp__h405061 or _theResult___exp__h405058) begin - case (guard__h396444) + case (guard__h396443) 2'b0, 2'b01: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 = - _theResult___fst_exp__h404543; + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q62 = + _theResult___fst_exp__h404542; 2'b10: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 = - out_exp__h405062; + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q62 = + out_exp__h405061; 2'b11: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 = - _theResult___exp__h405059; + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q62 = + _theResult___exp__h405058; endcase end - always@(guard__h396444 or - _theResult___fst_exp__h404543 or _theResult___exp__h405059) + always@(guard__h396443 or + _theResult___fst_exp__h404542 or _theResult___exp__h405058) begin - case (guard__h396444) + case (guard__h396443) 2'b0: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63 = - _theResult___fst_exp__h404543; + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q63 = + _theResult___fst_exp__h404542; 2'b01, 2'b10, 2'b11: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63 = - _theResult___exp__h405059; + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q63 = + _theResult___exp__h405058; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 or - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63 or + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q62 or + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q63 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 or - _theResult___fst_exp__h404543) + _theResult___fst_exp__h404542) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h405137 = - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62; + _theResult___fst_exp__h405136 = + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q62; 3'd1: - _theResult___fst_exp__h405137 = - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63; + _theResult___fst_exp__h405136 = + CASE_guard96443_0b0_theResult___fst_exp04542_0_ETC__q63; 3'd2: - _theResult___fst_exp__h405137 = + _theResult___fst_exp__h405136 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798; 3'd3: - _theResult___fst_exp__h405137 = + _theResult___fst_exp__h405136 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801; - 3'd4: _theResult___fst_exp__h405137 = _theResult___fst_exp__h404543; - default: _theResult___fst_exp__h405137 = 8'd0; + 3'd4: _theResult___fst_exp__h405136 = _theResult___fst_exp__h404542; + default: _theResult___fst_exp__h405136 = 8'd0; endcase end - always@(guard__h414081 or - _theResult___fst_exp__h422309 or - out_exp__h422828 or _theResult___exp__h422825) + always@(guard__h414080 or + _theResult___fst_exp__h422308 or + out_exp__h422827 or _theResult___exp__h422824) begin - case (guard__h414081) + case (guard__h414080) 2'b0, 2'b01: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 = - _theResult___fst_exp__h422309; + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q68 = + _theResult___fst_exp__h422308; 2'b10: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 = - out_exp__h422828; + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q68 = + out_exp__h422827; 2'b11: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 = - _theResult___exp__h422825; + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q68 = + _theResult___exp__h422824; endcase end - always@(guard__h414081 or - _theResult___fst_exp__h422309 or _theResult___exp__h422825) + always@(guard__h414080 or + _theResult___fst_exp__h422308 or _theResult___exp__h422824) begin - case (guard__h414081) + case (guard__h414080) 2'b0: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69 = - _theResult___fst_exp__h422309; + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q69 = + _theResult___fst_exp__h422308; 2'b01, 2'b10, 2'b11: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69 = - _theResult___exp__h422825; + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q69 = + _theResult___exp__h422824; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 or - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69 or + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q68 or + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q69 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 or - _theResult___fst_exp__h422309) + _theResult___fst_exp__h422308) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h422903 = - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68; + _theResult___fst_exp__h422902 = + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q68; 3'd1: - _theResult___fst_exp__h422903 = - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69; + _theResult___fst_exp__h422902 = + CASE_guard14080_0b0_theResult___fst_exp22308_0_ETC__q69; 3'd2: - _theResult___fst_exp__h422903 = + _theResult___fst_exp__h422902 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345; 3'd3: - _theResult___fst_exp__h422903 = + _theResult___fst_exp__h422902 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347; - 3'd4: _theResult___fst_exp__h422903 = _theResult___fst_exp__h422309; - default: _theResult___fst_exp__h422903 = 8'd0; + 3'd4: _theResult___fst_exp__h422902 = _theResult___fst_exp__h422308; + default: _theResult___fst_exp__h422902 = 8'd0; endcase end - always@(guard__h422917 or - _theResult___fst_exp__h430994 or - out_exp__h431464 or _theResult___exp__h431461) + always@(guard__h422916 or + _theResult___fst_exp__h430993 or + out_exp__h431463 or _theResult___exp__h431460) begin - case (guard__h422917) + case (guard__h422916) 2'b0, 2'b01: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 = - _theResult___fst_exp__h430994; + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q73 = + _theResult___fst_exp__h430993; 2'b10: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 = - out_exp__h431464; + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q73 = + out_exp__h431463; 2'b11: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 = - _theResult___exp__h431461; + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q73 = + _theResult___exp__h431460; endcase end - always@(guard__h422917 or - _theResult___fst_exp__h430994 or _theResult___exp__h431461) + always@(guard__h422916 or + _theResult___fst_exp__h430993 or _theResult___exp__h431460) begin - case (guard__h422917) + case (guard__h422916) 2'b0: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74 = - _theResult___fst_exp__h430994; + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q74 = + _theResult___fst_exp__h430993; 2'b01, 2'b10, 2'b11: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74 = - _theResult___exp__h431461; + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q74 = + _theResult___exp__h431460; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 or - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74 or + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q73 or + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q74 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___fst_exp__h430994) + _theResult___fst_exp__h430993) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h431539 = - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73; + _theResult___fst_exp__h431538 = + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q73; 3'd1: - _theResult___fst_exp__h431539 = - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74; + _theResult___fst_exp__h431538 = + CASE_guard22916_0b0_theResult___fst_exp30993_0_ETC__q74; 3'd2: - _theResult___fst_exp__h431539 = + _theResult___fst_exp__h431538 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_exp__h431539 = + _theResult___fst_exp__h431538 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_exp__h431539 = _theResult___fst_exp__h430994; - default: _theResult___fst_exp__h431539 = 8'd0; + 3'd4: _theResult___fst_exp__h431538 = _theResult___fst_exp__h430993; + default: _theResult___fst_exp__h431538 = 8'd0; endcase end - always@(guard__h405151 or - _theResult___snd__h413150 or - out_sfd__h413645 or _theResult___sfd__h413642) + always@(guard__h405150 or + _theResult___snd__h413149 or + out_sfd__h413644 or _theResult___sfd__h413641) begin - case (guard__h405151) + case (guard__h405150) 2'b0, 2'b01: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 = - _theResult___snd__h413150[56:34]; + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q75 = + _theResult___snd__h413149[56:34]; 2'b10: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 = - out_sfd__h413645; + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q75 = + out_sfd__h413644; 2'b11: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 = - _theResult___sfd__h413642; + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q75 = + _theResult___sfd__h413641; endcase end - always@(guard__h405151 or - _theResult___snd__h413150 or _theResult___sfd__h413642) + always@(guard__h405150 or + _theResult___snd__h413149 or _theResult___sfd__h413641) begin - case (guard__h405151) + case (guard__h405150) 2'b0: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76 = - _theResult___snd__h413150[56:34]; + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q76 = + _theResult___snd__h413149[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76 = - _theResult___sfd__h413642; + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q76 = + _theResult___sfd__h413641; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 or - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76 or + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q75 or + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q76 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or - _theResult___snd__h413150) + _theResult___snd__h413149) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h413720 = - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75; + _theResult___fst_sfd__h413719 = + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q75; 3'd1: - _theResult___fst_sfd__h413720 = - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76; + _theResult___fst_sfd__h413719 = + CASE_guard05150_0b0_theResult___snd13149_BITS__ETC__q76; 3'd2: - _theResult___fst_sfd__h413720 = + _theResult___fst_sfd__h413719 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; 3'd3: - _theResult___fst_sfd__h413720 = + _theResult___fst_sfd__h413719 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466; - 3'd4: _theResult___fst_sfd__h413720 = _theResult___snd__h413150[56:34]; - default: _theResult___fst_sfd__h413720 = 23'd0; + 3'd4: _theResult___fst_sfd__h413719 = _theResult___snd__h413149[56:34]; + default: _theResult___fst_sfd__h413719 = 23'd0; endcase end - always@(guard__h396444 or - sfdin__h404537 or out_sfd__h405063 or _theResult___sfd__h405060) + always@(guard__h396443 or + sfdin__h404536 or out_sfd__h405062 or _theResult___sfd__h405059) begin - case (guard__h396444) + case (guard__h396443) 2'b0, 2'b01: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 = - sfdin__h404537[56:34]; + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q77 = + sfdin__h404536[56:34]; 2'b10: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 = - out_sfd__h405063; + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q77 = + out_sfd__h405062; 2'b11: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h405060; + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h405059; endcase end - always@(guard__h396444 or sfdin__h404537 or _theResult___sfd__h405060) + always@(guard__h396443 or sfdin__h404536 or _theResult___sfd__h405059) begin - case (guard__h396444) + case (guard__h396443) 2'b0: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78 = - sfdin__h404537[56:34]; + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q78 = + sfdin__h404536[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h405060; + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h405059; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 or - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78 or + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q77 or + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q78 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or - sfdin__h404537) + sfdin__h404536) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h405138 = - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h405137 = + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q77; 3'd1: - _theResult___fst_sfd__h405138 = - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h405137 = + CASE_guard96443_0b0_sfdin04536_BITS_56_TO_34_0_ETC__q78; 3'd2: - _theResult___fst_sfd__h405138 = + _theResult___fst_sfd__h405137 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; 3'd3: - _theResult___fst_sfd__h405138 = + _theResult___fst_sfd__h405137 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; - 3'd4: _theResult___fst_sfd__h405138 = sfdin__h404537[56:34]; - default: _theResult___fst_sfd__h405138 = 23'd0; + 3'd4: _theResult___fst_sfd__h405137 = sfdin__h404536[56:34]; + default: _theResult___fst_sfd__h405137 = 23'd0; endcase end - always@(guard__h414081 or - sfdin__h422303 or out_sfd__h422829 or _theResult___sfd__h422826) + always@(guard__h414080 or + sfdin__h422302 or out_sfd__h422828 or _theResult___sfd__h422825) begin - case (guard__h414081) + case (guard__h414080) 2'b0, 2'b01: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 = - sfdin__h422303[56:34]; + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q79 = + sfdin__h422302[56:34]; 2'b10: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 = - out_sfd__h422829; + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q79 = + out_sfd__h422828; 2'b11: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h422826; + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h422825; endcase end - always@(guard__h414081 or sfdin__h422303 or _theResult___sfd__h422826) + always@(guard__h414080 or sfdin__h422302 or _theResult___sfd__h422825) begin - case (guard__h414081) + case (guard__h414080) 2'b0: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80 = - sfdin__h422303[56:34]; + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q80 = + sfdin__h422302[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80 = - _theResult___sfd__h422826; + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q80 = + _theResult___sfd__h422825; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 or - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80 or + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q79 or + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q80 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 or - sfdin__h422303) + sfdin__h422302) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h422904 = - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h422903 = + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q79; 3'd1: - _theResult___fst_sfd__h422904 = - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80; + _theResult___fst_sfd__h422903 = + CASE_guard14080_0b0_sfdin22302_BITS_56_TO_34_0_ETC__q80; 3'd2: - _theResult___fst_sfd__h422904 = + _theResult___fst_sfd__h422903 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491; 3'd3: - _theResult___fst_sfd__h422904 = + _theResult___fst_sfd__h422903 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493; - 3'd4: _theResult___fst_sfd__h422904 = sfdin__h422303[56:34]; - default: _theResult___fst_sfd__h422904 = 23'd0; + 3'd4: _theResult___fst_sfd__h422903 = sfdin__h422302[56:34]; + default: _theResult___fst_sfd__h422903 = 23'd0; endcase end - always@(guard__h422917 or - _theResult___snd__h430940 or - out_sfd__h431465 or _theResult___sfd__h431462) + always@(guard__h422916 or + _theResult___snd__h430939 or + out_sfd__h431464 or _theResult___sfd__h431461) begin - case (guard__h422917) + case (guard__h422916) 2'b0, 2'b01: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 = - _theResult___snd__h430940[56:34]; + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q81 = + _theResult___snd__h430939[56:34]; 2'b10: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 = - out_sfd__h431465; + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q81 = + out_sfd__h431464; 2'b11: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 = - _theResult___sfd__h431462; + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q81 = + _theResult___sfd__h431461; endcase end - always@(guard__h422917 or - _theResult___snd__h430940 or _theResult___sfd__h431462) + always@(guard__h422916 or + _theResult___snd__h430939 or _theResult___sfd__h431461) begin - case (guard__h422917) + case (guard__h422916) 2'b0: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82 = - _theResult___snd__h430940[56:34]; + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q82 = + _theResult___snd__h430939[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82 = - _theResult___sfd__h431462; + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q82 = + _theResult___sfd__h431461; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 or - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82 or + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q81 or + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q82 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 or - _theResult___snd__h430940) + _theResult___snd__h430939) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h431540 = - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81; + _theResult___fst_sfd__h431539 = + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q81; 3'd1: - _theResult___fst_sfd__h431540 = - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82; + _theResult___fst_sfd__h431539 = + CASE_guard22916_0b0_theResult___snd30939_BITS__ETC__q82; 3'd2: - _theResult___fst_sfd__h431540 = + _theResult___fst_sfd__h431539 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510; 3'd3: - _theResult___fst_sfd__h431540 = + _theResult___fst_sfd__h431539 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512; - 3'd4: _theResult___fst_sfd__h431540 = _theResult___snd__h430940[56:34]; - default: _theResult___fst_sfd__h431540 = 23'd0; + 3'd4: _theResult___fst_sfd__h431539 = _theResult___snd__h430939[56:34]; + default: _theResult___fst_sfd__h431539 = 23'd0; endcase end - always@(guard__h396444 or + always@(guard__h396443 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396444) + case (guard__h396443) 2'b0, 2'b01, 2'b10: - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + CASE_guard96443_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = - guard__h396444 == 2'b11 && + CASE_guard96443_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + guard__h396443 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or - guard__h396444) + CASE_guard96443_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or + guard__h396443) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; + CASE_guard96443_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - (guard__h396444 == 2'b0) ? + (guard__h396443 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h396444 == 2'b01 || guard__h396444 == 2'b10 || - guard__h396444 == 2'b11) && + (guard__h396443 == 2'b01 || guard__h396443 == 2'b10 || + guard__h396443 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = @@ -32225,34 +32208,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h396444 or + always@(guard__h396443 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396444) + case (guard__h396443) 2'b0, 2'b01, 2'b10: - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = + CASE_guard96443_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = - guard__h396444 != 2'b11 || + CASE_guard96443_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = + guard__h396443 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or - guard__h396444) + CASE_guard96443_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or + guard__h396443) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84; + CASE_guard96443_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - (guard__h396444 == 2'b0) ? + (guard__h396443 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h396444 != 2'b01 && guard__h396444 != 2'b10 && - guard__h396444 != 2'b11 || + guard__h396443 != 2'b01 && guard__h396443 != 2'b10 && + guard__h396443 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = @@ -32263,34 +32246,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h405151 or + always@(guard__h405150 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h405151) + case (guard__h405150) 2'b0, 2'b01, 2'b10: - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + CASE_guard05150_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = - guard__h405151 == 2'b11 && + CASE_guard05150_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + guard__h405150 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or - guard__h405151) + CASE_guard05150_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or + guard__h405150) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85; + CASE_guard05150_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - (guard__h405151 == 2'b0) ? + (guard__h405150 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h405151 == 2'b01 || guard__h405151 == 2'b10 || - guard__h405151 == 2'b11) && + (guard__h405150 == 2'b01 || guard__h405150 == 2'b10 || + guard__h405150 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = @@ -32301,34 +32284,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h405151 or + always@(guard__h405150 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h405151) + case (guard__h405150) 2'b0, 2'b01, 2'b10: - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + CASE_guard05150_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = - guard__h405151 != 2'b11 || + CASE_guard05150_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + guard__h405150 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or - guard__h405151) + CASE_guard05150_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or + guard__h405150) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; + CASE_guard05150_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - (guard__h405151 == 2'b0) ? + (guard__h405150 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h405151 != 2'b01 && guard__h405151 != 2'b10 && - guard__h405151 != 2'b11 || + guard__h405150 != 2'b01 && guard__h405150 != 2'b10 && + guard__h405150 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = @@ -32339,34 +32322,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h414081 or + always@(guard__h414080 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h414081) + case (guard__h414080) 2'b0, 2'b01, 2'b10: - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + CASE_guard14080_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = - guard__h414081 == 2'b11 && + CASE_guard14080_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + guard__h414080 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or - guard__h414081) + CASE_guard14080_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or + guard__h414080) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; + CASE_guard14080_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - (guard__h414081 == 2'b0) ? + (guard__h414080 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h414081 == 2'b01 || guard__h414081 == 2'b10 || - guard__h414081 == 2'b11) && + (guard__h414080 == 2'b01 || guard__h414080 == 2'b10 || + guard__h414080 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = @@ -32377,34 +32360,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h414081 or + always@(guard__h414080 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h414081) + case (guard__h414080) 2'b0, 2'b01, 2'b10: - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = + CASE_guard14080_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = - guard__h414081 != 2'b11 || + CASE_guard14080_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = + guard__h414080 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or - guard__h414081) + CASE_guard14080_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or + guard__h414080) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; + CASE_guard14080_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - (guard__h414081 == 2'b0) ? + (guard__h414080 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h414081 != 2'b01 && guard__h414081 != 2'b10 && - guard__h414081 != 2'b11 || + guard__h414080 != 2'b01 && guard__h414080 != 2'b10 && + guard__h414080 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = @@ -32415,34 +32398,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422917 or + always@(guard__h422916 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422917) + case (guard__h422916) 2'b0, 2'b01, 2'b10: - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + CASE_guard22916_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = - guard__h422917 == 2'b11 && + CASE_guard22916_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + guard__h422916 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or - guard__h422917) + CASE_guard22916_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or + guard__h422916) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; + CASE_guard22916_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - (guard__h422917 == 2'b0) ? + (guard__h422916 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h422917 == 2'b01 || guard__h422917 == 2'b10 || - guard__h422917 == 2'b11) && + (guard__h422916 == 2'b01 || guard__h422916 == 2'b10 || + guard__h422916 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = @@ -32453,34 +32436,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422917 or + always@(guard__h422916 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422917) + case (guard__h422916) 2'b0, 2'b01, 2'b10: - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + CASE_guard22916_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = - guard__h422917 != 2'b11 || + CASE_guard22916_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + guard__h422916 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or - guard__h422917) + CASE_guard22916_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or + guard__h422916) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; + CASE_guard22916_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - (guard__h422917 == 2'b0) ? + (guard__h422916 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h422917 != 2'b01 && guard__h422917 != 2'b10 && - guard__h422917 != 2'b11 || + guard__h422916 != 2'b01 && guard__h422916 != 2'b10 && + guard__h422916 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = @@ -32517,446 +32500,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h450846 or - _theResult___fst_exp__h458894 or - out_exp__h459339 or _theResult___exp__h459336) + always@(guard__h450845 or + _theResult___fst_exp__h458893 or + out_exp__h459338 or _theResult___exp__h459335) begin - case (guard__h450846) + case (guard__h450845) 2'b0, 2'b01: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 = - _theResult___fst_exp__h458894; + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q95 = + _theResult___fst_exp__h458893; 2'b10: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 = - out_exp__h459339; + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q95 = + out_exp__h459338; 2'b11: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 = - _theResult___exp__h459336; + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q95 = + _theResult___exp__h459335; endcase end - always@(guard__h450846 or - _theResult___fst_exp__h458894 or _theResult___exp__h459336) + always@(guard__h450845 or + _theResult___fst_exp__h458893 or _theResult___exp__h459335) begin - case (guard__h450846) + case (guard__h450845) 2'b0: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96 = - _theResult___fst_exp__h458894; + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q96 = + _theResult___fst_exp__h458893; 2'b01, 2'b10, 2'b11: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96 = - _theResult___exp__h459336; + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q96 = + _theResult___exp__h459335; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 or - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96 or + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q95 or + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q96 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 or - _theResult___fst_exp__h458894) + _theResult___fst_exp__h458893) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h459414 = - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95; + _theResult___fst_exp__h459413 = + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q95; 3'd1: - _theResult___fst_exp__h459414 = - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96; + _theResult___fst_exp__h459413 = + CASE_guard50845_0b0_theResult___fst_exp58893_0_ETC__q96; 3'd2: - _theResult___fst_exp__h459414 = + _theResult___fst_exp__h459413 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412; 3'd3: - _theResult___fst_exp__h459414 = + _theResult___fst_exp__h459413 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414; - 3'd4: _theResult___fst_exp__h459414 = _theResult___fst_exp__h458894; - default: _theResult___fst_exp__h459414 = 8'd0; + 3'd4: _theResult___fst_exp__h459413 = _theResult___fst_exp__h458893; + default: _theResult___fst_exp__h459413 = 8'd0; endcase end - always@(guard__h442139 or - _theResult___fst_exp__h450238 or - out_exp__h450757 or _theResult___exp__h450754) + always@(guard__h442138 or + _theResult___fst_exp__h450237 or + out_exp__h450756 or _theResult___exp__h450753) begin - case (guard__h442139) + case (guard__h442138) 2'b0, 2'b01: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 = - _theResult___fst_exp__h450238; + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q97 = + _theResult___fst_exp__h450237; 2'b10: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 = - out_exp__h450757; + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q97 = + out_exp__h450756; 2'b11: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 = - _theResult___exp__h450754; + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q97 = + _theResult___exp__h450753; endcase end - always@(guard__h442139 or - _theResult___fst_exp__h450238 or _theResult___exp__h450754) + always@(guard__h442138 or + _theResult___fst_exp__h450237 or _theResult___exp__h450753) begin - case (guard__h442139) + case (guard__h442138) 2'b0: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98 = - _theResult___fst_exp__h450238; + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q98 = + _theResult___fst_exp__h450237; 2'b01, 2'b10, 2'b11: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98 = - _theResult___exp__h450754; + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q98 = + _theResult___exp__h450753; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 or - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98 or + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q97 or + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q98 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 or - _theResult___fst_exp__h450238) + _theResult___fst_exp__h450237) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h450832 = - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97; + _theResult___fst_exp__h450831 = + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q97; 3'd1: - _theResult___fst_exp__h450832 = - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98; + _theResult___fst_exp__h450831 = + CASE_guard42138_0b0_theResult___fst_exp50237_0_ETC__q98; 3'd2: - _theResult___fst_exp__h450832 = + _theResult___fst_exp__h450831 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190; 3'd3: - _theResult___fst_exp__h450832 = + _theResult___fst_exp__h450831 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193; - 3'd4: _theResult___fst_exp__h450832 = _theResult___fst_exp__h450238; - default: _theResult___fst_exp__h450832 = 8'd0; + 3'd4: _theResult___fst_exp__h450831 = _theResult___fst_exp__h450237; + default: _theResult___fst_exp__h450831 = 8'd0; endcase end - always@(guard__h459776 or - _theResult___fst_exp__h468004 or - out_exp__h468523 or _theResult___exp__h468520) + always@(guard__h459775 or + _theResult___fst_exp__h468003 or + out_exp__h468522 or _theResult___exp__h468519) begin - case (guard__h459776) + case (guard__h459775) 2'b0, 2'b01: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 = - _theResult___fst_exp__h468004; + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q103 = + _theResult___fst_exp__h468003; 2'b10: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 = - out_exp__h468523; + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q103 = + out_exp__h468522; 2'b11: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 = - _theResult___exp__h468520; + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q103 = + _theResult___exp__h468519; endcase end - always@(guard__h459776 or - _theResult___fst_exp__h468004 or _theResult___exp__h468520) + always@(guard__h459775 or + _theResult___fst_exp__h468003 or _theResult___exp__h468519) begin - case (guard__h459776) + case (guard__h459775) 2'b0: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104 = - _theResult___fst_exp__h468004; + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q104 = + _theResult___fst_exp__h468003; 2'b01, 2'b10, 2'b11: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104 = - _theResult___exp__h468520; + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q104 = + _theResult___exp__h468519; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 or - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104 or + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q103 or + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q104 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 or - _theResult___fst_exp__h468004) + _theResult___fst_exp__h468003) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h468598 = - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103; + _theResult___fst_exp__h468597 = + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q103; 3'd1: - _theResult___fst_exp__h468598 = - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104; + _theResult___fst_exp__h468597 = + CASE_guard59775_0b0_theResult___fst_exp68003_0_ETC__q104; 3'd2: - _theResult___fst_exp__h468598 = + _theResult___fst_exp__h468597 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737; 3'd3: - _theResult___fst_exp__h468598 = + _theResult___fst_exp__h468597 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739; - 3'd4: _theResult___fst_exp__h468598 = _theResult___fst_exp__h468004; - default: _theResult___fst_exp__h468598 = 8'd0; + 3'd4: _theResult___fst_exp__h468597 = _theResult___fst_exp__h468003; + default: _theResult___fst_exp__h468597 = 8'd0; endcase end - always@(guard__h468612 or - _theResult___fst_exp__h476689 or - out_exp__h477159 or _theResult___exp__h477156) + always@(guard__h468611 or + _theResult___fst_exp__h476688 or + out_exp__h477158 or _theResult___exp__h477155) begin - case (guard__h468612) + case (guard__h468611) 2'b0, 2'b01: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 = - _theResult___fst_exp__h476689; + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q108 = + _theResult___fst_exp__h476688; 2'b10: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 = - out_exp__h477159; + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q108 = + out_exp__h477158; 2'b11: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 = - _theResult___exp__h477156; + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q108 = + _theResult___exp__h477155; endcase end - always@(guard__h468612 or - _theResult___fst_exp__h476689 or _theResult___exp__h477156) + always@(guard__h468611 or + _theResult___fst_exp__h476688 or _theResult___exp__h477155) begin - case (guard__h468612) + case (guard__h468611) 2'b0: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109 = - _theResult___fst_exp__h476689; + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q109 = + _theResult___fst_exp__h476688; 2'b01, 2'b10, 2'b11: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109 = - _theResult___exp__h477156; + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q109 = + _theResult___exp__h477155; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 or - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109 or + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q108 or + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q109 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___fst_exp__h476689) + _theResult___fst_exp__h476688) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h477234 = - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108; + _theResult___fst_exp__h477233 = + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q108; 3'd1: - _theResult___fst_exp__h477234 = - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109; + _theResult___fst_exp__h477233 = + CASE_guard68611_0b0_theResult___fst_exp76688_0_ETC__q109; 3'd2: - _theResult___fst_exp__h477234 = + _theResult___fst_exp__h477233 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; 3'd3: - _theResult___fst_exp__h477234 = + _theResult___fst_exp__h477233 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_exp__h477234 = _theResult___fst_exp__h476689; - default: _theResult___fst_exp__h477234 = 8'd0; + 3'd4: _theResult___fst_exp__h477233 = _theResult___fst_exp__h476688; + default: _theResult___fst_exp__h477233 = 8'd0; endcase end - always@(guard__h450846 or - _theResult___snd__h458845 or - out_sfd__h459340 or _theResult___sfd__h459337) + always@(guard__h450845 or + _theResult___snd__h458844 or + out_sfd__h459339 or _theResult___sfd__h459336) begin - case (guard__h450846) + case (guard__h450845) 2'b0, 2'b01: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 = - _theResult___snd__h458845[56:34]; + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q110 = + _theResult___snd__h458844[56:34]; 2'b10: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 = - out_sfd__h459340; + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q110 = + out_sfd__h459339; 2'b11: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 = - _theResult___sfd__h459337; + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q110 = + _theResult___sfd__h459336; endcase end - always@(guard__h450846 or - _theResult___snd__h458845 or _theResult___sfd__h459337) + always@(guard__h450845 or + _theResult___snd__h458844 or _theResult___sfd__h459336) begin - case (guard__h450846) + case (guard__h450845) 2'b0: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111 = - _theResult___snd__h458845[56:34]; + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q111 = + _theResult___snd__h458844[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111 = - _theResult___sfd__h459337; + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q111 = + _theResult___sfd__h459336; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 or - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111 or + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q110 or + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q111 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 or - _theResult___snd__h458845) + _theResult___snd__h458844) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h459415 = - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110; + _theResult___fst_sfd__h459414 = + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q110; 3'd1: - _theResult___fst_sfd__h459415 = - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111; + _theResult___fst_sfd__h459414 = + CASE_guard50845_0b0_theResult___snd58844_BITS__ETC__q111; 3'd2: - _theResult___fst_sfd__h459415 = + _theResult___fst_sfd__h459414 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856; 3'd3: - _theResult___fst_sfd__h459415 = + _theResult___fst_sfd__h459414 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858; - 3'd4: _theResult___fst_sfd__h459415 = _theResult___snd__h458845[56:34]; - default: _theResult___fst_sfd__h459415 = 23'd0; + 3'd4: _theResult___fst_sfd__h459414 = _theResult___snd__h458844[56:34]; + default: _theResult___fst_sfd__h459414 = 23'd0; endcase end - always@(guard__h442139 or - sfdin__h450232 or out_sfd__h450758 or _theResult___sfd__h450755) + always@(guard__h442138 or + sfdin__h450231 or out_sfd__h450757 or _theResult___sfd__h450754) begin - case (guard__h442139) + case (guard__h442138) 2'b0, 2'b01: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 = - sfdin__h450232[56:34]; + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q112 = + sfdin__h450231[56:34]; 2'b10: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 = - out_sfd__h450758; + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q112 = + out_sfd__h450757; 2'b11: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h450755; + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h450754; endcase end - always@(guard__h442139 or sfdin__h450232 or _theResult___sfd__h450755) + always@(guard__h442138 or sfdin__h450231 or _theResult___sfd__h450754) begin - case (guard__h442139) + case (guard__h442138) 2'b0: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113 = - sfdin__h450232[56:34]; + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q113 = + sfdin__h450231[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h450755; + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h450754; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 or - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113 or + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q112 or + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q113 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 or - sfdin__h450232) + sfdin__h450231) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h450833 = - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h450832 = + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q112; 3'd1: - _theResult___fst_sfd__h450833 = - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h450832 = + CASE_guard42138_0b0_sfdin50231_BITS_56_TO_34_0_ETC__q113; 3'd2: - _theResult___fst_sfd__h450833 = + _theResult___fst_sfd__h450832 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837; 3'd3: - _theResult___fst_sfd__h450833 = + _theResult___fst_sfd__h450832 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839; - 3'd4: _theResult___fst_sfd__h450833 = sfdin__h450232[56:34]; - default: _theResult___fst_sfd__h450833 = 23'd0; + 3'd4: _theResult___fst_sfd__h450832 = sfdin__h450231[56:34]; + default: _theResult___fst_sfd__h450832 = 23'd0; endcase end - always@(guard__h459776 or - sfdin__h467998 or out_sfd__h468524 or _theResult___sfd__h468521) + always@(guard__h459775 or + sfdin__h467997 or out_sfd__h468523 or _theResult___sfd__h468520) begin - case (guard__h459776) + case (guard__h459775) 2'b0, 2'b01: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 = - sfdin__h467998[56:34]; + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q114 = + sfdin__h467997[56:34]; 2'b10: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 = - out_sfd__h468524; + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q114 = + out_sfd__h468523; 2'b11: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h468521; + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h468520; endcase end - always@(guard__h459776 or sfdin__h467998 or _theResult___sfd__h468521) + always@(guard__h459775 or sfdin__h467997 or _theResult___sfd__h468520) begin - case (guard__h459776) + case (guard__h459775) 2'b0: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115 = - sfdin__h467998[56:34]; + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q115 = + sfdin__h467997[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115 = - _theResult___sfd__h468521; + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q115 = + _theResult___sfd__h468520; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 or - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115 or + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q114 or + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q115 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 or - sfdin__h467998) + sfdin__h467997) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h468599 = - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h468598 = + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q114; 3'd1: - _theResult___fst_sfd__h468599 = - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115; + _theResult___fst_sfd__h468598 = + CASE_guard59775_0b0_sfdin67997_BITS_56_TO_34_0_ETC__q115; 3'd2: - _theResult___fst_sfd__h468599 = + _theResult___fst_sfd__h468598 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883; 3'd3: - _theResult___fst_sfd__h468599 = + _theResult___fst_sfd__h468598 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885; - 3'd4: _theResult___fst_sfd__h468599 = sfdin__h467998[56:34]; - default: _theResult___fst_sfd__h468599 = 23'd0; + 3'd4: _theResult___fst_sfd__h468598 = sfdin__h467997[56:34]; + default: _theResult___fst_sfd__h468598 = 23'd0; endcase end - always@(guard__h468612 or - _theResult___snd__h476635 or - out_sfd__h477160 or _theResult___sfd__h477157) + always@(guard__h468611 or + _theResult___snd__h476634 or + out_sfd__h477159 or _theResult___sfd__h477156) begin - case (guard__h468612) + case (guard__h468611) 2'b0, 2'b01: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 = - _theResult___snd__h476635[56:34]; + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q116 = + _theResult___snd__h476634[56:34]; 2'b10: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 = - out_sfd__h477160; + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q116 = + out_sfd__h477159; 2'b11: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 = - _theResult___sfd__h477157; + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q116 = + _theResult___sfd__h477156; endcase end - always@(guard__h468612 or - _theResult___snd__h476635 or _theResult___sfd__h477157) + always@(guard__h468611 or + _theResult___snd__h476634 or _theResult___sfd__h477156) begin - case (guard__h468612) + case (guard__h468611) 2'b0: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117 = - _theResult___snd__h476635[56:34]; + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q117 = + _theResult___snd__h476634[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117 = - _theResult___sfd__h477157; + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q117 = + _theResult___sfd__h477156; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 or - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117 or + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q116 or + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q117 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 or - _theResult___snd__h476635) + _theResult___snd__h476634) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h477235 = - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116; + _theResult___fst_sfd__h477234 = + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q116; 3'd1: - _theResult___fst_sfd__h477235 = - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117; + _theResult___fst_sfd__h477234 = + CASE_guard68611_0b0_theResult___snd76634_BITS__ETC__q117; 3'd2: - _theResult___fst_sfd__h477235 = + _theResult___fst_sfd__h477234 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902; 3'd3: - _theResult___fst_sfd__h477235 = + _theResult___fst_sfd__h477234 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904; - 3'd4: _theResult___fst_sfd__h477235 = _theResult___snd__h476635[56:34]; - default: _theResult___fst_sfd__h477235 = 23'd0; + 3'd4: _theResult___fst_sfd__h477234 = _theResult___snd__h476634[56:34]; + default: _theResult___fst_sfd__h477234 = 23'd0; endcase end - always@(guard__h442139 or + always@(guard__h442138 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h442139) + case (guard__h442138) 2'b0, 2'b01, 2'b10: - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + CASE_guard42138_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = - guard__h442139 == 2'b11 && + CASE_guard42138_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + guard__h442138 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or - guard__h442139) + CASE_guard42138_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or + guard__h442138) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; + CASE_guard42138_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - (guard__h442139 == 2'b0) ? + (guard__h442138 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h442139 == 2'b01 || guard__h442139 == 2'b10 || - guard__h442139 == 2'b11) && + (guard__h442138 == 2'b01 || guard__h442138 == 2'b10 || + guard__h442138 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = @@ -32967,72 +32950,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h442139 or + always@(guard__h450845 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h442139) + case (guard__h450845) 2'b0, 2'b01, 2'b10: - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 = - guard__h442139 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119 or - guard__h442139) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q119; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h442139 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h442139 != 2'b01 && guard__h442139 != 2'b10 && - guard__h442139 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h450846 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h450846) - 2'b0, 2'b01, 2'b10: - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = + CASE_guard50845_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 = - guard__h450846 == 2'b11 && + CASE_guard50845_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h450845 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or - guard__h450846) + CASE_guard50845_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h450845) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120; + CASE_guard50845_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - (guard__h450846 == 2'b0) ? + (guard__h450845 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h450846 == 2'b01 || guard__h450846 == 2'b10 || - guard__h450846 == 2'b11) && + (guard__h450845 == 2'b01 || guard__h450845 == 2'b10 || + guard__h450845 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = @@ -33043,34 +32988,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h450846 or + always@(guard__h442138 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h450846) + case (guard__h442138) 2'b0, 2'b01, 2'b10: - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + CASE_guard42138_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = - guard__h450846 != 2'b11 || + CASE_guard42138_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h442138 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or - guard__h450846) + CASE_guard42138_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h442138) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + CASE_guard42138_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + (guard__h442138 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h442138 != 2'b01 && guard__h442138 != 2'b10 && + guard__h442138 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h450845 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h450845) + 2'b0, 2'b01, 2'b10: + CASE_guard50845_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard50845_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + guard__h450845 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard50845_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or + guard__h450845) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; + CASE_guard50845_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - (guard__h450846 == 2'b0) ? + (guard__h450845 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h450846 != 2'b01 && guard__h450846 != 2'b10 && - guard__h450846 != 2'b11 || + guard__h450845 != 2'b01 && guard__h450845 != 2'b10 && + guard__h450845 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = @@ -33081,34 +33064,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459776 or + always@(guard__h459775 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459776) + case (guard__h459775) 2'b0, 2'b01, 2'b10: - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + CASE_guard59775_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = - guard__h459776 == 2'b11 && + CASE_guard59775_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + guard__h459775 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or - guard__h459776) + CASE_guard59775_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or + guard__h459775) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; + CASE_guard59775_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - (guard__h459776 == 2'b0) ? + (guard__h459775 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h459776 == 2'b01 || guard__h459776 == 2'b10 || - guard__h459776 == 2'b11) && + (guard__h459775 == 2'b01 || guard__h459775 == 2'b10 || + guard__h459775 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = @@ -33119,34 +33102,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459776 or + always@(guard__h459775 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459776) + case (guard__h459775) 2'b0, 2'b01, 2'b10: - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + CASE_guard59775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = - guard__h459776 != 2'b11 || + CASE_guard59775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + guard__h459775 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or - guard__h459776) + CASE_guard59775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or + guard__h459775) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; + CASE_guard59775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - (guard__h459776 == 2'b0) ? + (guard__h459775 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h459776 != 2'b01 && guard__h459776 != 2'b10 && - guard__h459776 != 2'b11 || + guard__h459775 != 2'b01 && guard__h459775 != 2'b10 && + guard__h459775 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = @@ -33157,34 +33140,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468612 or + always@(guard__h468611 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468612) + case (guard__h468611) 2'b0, 2'b01, 2'b10: - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + CASE_guard68611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = - guard__h468612 == 2'b11 && + CASE_guard68611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + guard__h468611 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or - guard__h468612) + CASE_guard68611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or + guard__h468611) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; + CASE_guard68611_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - (guard__h468612 == 2'b0) ? + (guard__h468611 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h468612 == 2'b01 || guard__h468612 == 2'b10 || - guard__h468612 == 2'b11) && + (guard__h468611 == 2'b01 || guard__h468611 == 2'b10 || + guard__h468611 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = @@ -33195,34 +33178,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468612 or + always@(guard__h468611 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468612) + case (guard__h468611) 2'b0, 2'b01, 2'b10: - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + CASE_guard68611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = - guard__h468612 != 2'b11 || + CASE_guard68611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + guard__h468611 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or - guard__h468612) + CASE_guard68611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or + guard__h468611) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; + CASE_guard68611_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - (guard__h468612 == 2'b0) ? + (guard__h468611 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h468612 != 2'b01 && guard__h468612 != 2'b10 && - guard__h468612 != 2'b11 || + guard__h468611 != 2'b01 && guard__h468611 != 2'b10 && + guard__h468611 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = @@ -33279,28 +33262,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h498953 or - _theResult___fst_exp__h506914 or _theResult___exp__h507569) + always@(guard__h498952 or + _theResult___fst_exp__h506913 or _theResult___exp__h507568) begin - case (guard__h498953) + case (guard__h498952) 2'b0: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135 = - _theResult___fst_exp__h506914; + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q135 = + _theResult___fst_exp__h506913; 2'b01, 2'b10, 2'b11: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135 = - _theResult___exp__h507569; + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q135 = + _theResult___exp__h507568; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h506914 or + _theResult___fst_exp__h506913 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 or - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135) + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - _theResult___fst_exp__h506914; + _theResult___fst_exp__h506913; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126; @@ -33309,44 +33292,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135; + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = 11'd0; endcase end - always@(guard__h498953 or - _theResult___fst_exp__h506914 or - out_exp__h507572 or _theResult___exp__h507569) + always@(guard__h498952 or + _theResult___fst_exp__h506913 or + out_exp__h507571 or _theResult___exp__h507568) begin - case (guard__h498953) + case (guard__h498952) 2'b0, 2'b01: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 = - _theResult___fst_exp__h506914; + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q136 = + _theResult___fst_exp__h506913; 2'b10: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 = - out_exp__h507572; + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q136 = + out_exp__h507571; 2'b11: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 = - _theResult___exp__h507569; + CASE_guard98952_0b0_theResult___fst_exp06913_0_ETC__q136 = + _theResult___exp__h507568; endcase end - always@(guard__h498953 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h498952 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h498953) + case (guard__h498952) 2'b0, 2'b01, 2'b10: - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard98952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h498953 == 2'b11 && + CASE_guard98952_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h498952 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498953) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498952) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33356,12 +33339,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h498953 == 2'b0) ? + (guard__h498952 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h498953 == 2'b01 || guard__h498953 == 2'b10 || - guard__h498953 == 2'b11) && + (guard__h498952 == 2'b01 || guard__h498952 == 2'b10 || + guard__h498952 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33372,23 +33355,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h508265 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h508264 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h508265) + case (guard__h508264) 2'b0, 2'b01, 2'b10: - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard08264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h508265 == 2'b11 && + CASE_guard08264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h508264 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h508265) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h508264) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33398,12 +33381,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h508265 == 2'b0) ? + (guard__h508264 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h508265 == 2'b01 || guard__h508265 == 2'b10 || - guard__h508265 == 2'b11) && + (guard__h508264 == 2'b01 || guard__h508264 == 2'b10 || + guard__h508264 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33414,23 +33397,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h517334 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h517333 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h517334) + case (guard__h517333) 2'b0, 2'b01, 2'b10: - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard17333_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h517334 == 2'b11 && + CASE_guard17333_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h517333 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h517334) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h517333) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33440,12 +33423,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h517334 == 2'b0) ? + (guard__h517333 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h517334 == 2'b01 || guard__h517334 == 2'b10 || - guard__h517334 == 2'b11) && + (guard__h517333 == 2'b01 || guard__h517333 == 2'b10 || + guard__h517333 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33456,28 +33439,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h577110 or - _theResult___fst_exp__h585071 or _theResult___exp__h585726) + always@(guard__h577109 or + _theResult___fst_exp__h585070 or _theResult___exp__h585725) begin - case (guard__h577110) + case (guard__h577109) 2'b0: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152 = - _theResult___fst_exp__h585071; + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q152 = + _theResult___fst_exp__h585070; 2'b01, 2'b10, 2'b11: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152 = - _theResult___exp__h585726; + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q152 = + _theResult___exp__h585725; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h585071 or + _theResult___fst_exp__h585070 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 or - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152) + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - _theResult___fst_exp__h585071; + _theResult___fst_exp__h585070; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841; @@ -33486,42 +33469,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152; + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = 11'd0; endcase end - always@(guard__h577110 or - _theResult___fst_exp__h585071 or - out_exp__h585729 or _theResult___exp__h585726) + always@(guard__h577109 or + _theResult___fst_exp__h585070 or + out_exp__h585728 or _theResult___exp__h585725) begin - case (guard__h577110) + case (guard__h577109) 2'b0, 2'b01: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 = - _theResult___fst_exp__h585071; + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q153 = + _theResult___fst_exp__h585070; 2'b10: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 = - out_exp__h585729; + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q153 = + out_exp__h585728; 2'b11: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 = - _theResult___exp__h585726; + CASE_guard77109_0b0_theResult___fst_exp85070_0_ETC__q153 = + _theResult___exp__h585725; endcase end - always@(guard__h577110 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577109 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577110) + case (guard__h577109) 2'b0, 2'b01, 2'b10: - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard77109_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h577110 == 2'b11 && + CASE_guard77109_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h577109 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577110) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577109) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33530,12 +33513,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h577110 == 2'b0) ? + (guard__h577109 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h577110 == 2'b01 || guard__h577110 == 2'b10 || - guard__h577110 == 2'b11) && + (guard__h577109 == 2'b01 || guard__h577109 == 2'b10 || + guard__h577109 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33546,21 +33529,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h586422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h586421 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h586422) + case (guard__h586421) 2'b0, 2'b01, 2'b10: - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard86421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h586422 == 2'b11 && + CASE_guard86421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h586421 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586422) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586421) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33569,12 +33552,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h586422 == 2'b0) ? + (guard__h586421 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h586422 == 2'b01 || guard__h586422 == 2'b10 || - guard__h586422 == 2'b11) && + (guard__h586421 == 2'b01 || guard__h586421 == 2'b10 || + guard__h586421 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33585,21 +33568,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595490 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595491) + case (guard__h595490) 2'b0, 2'b01, 2'b10: - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard95490_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h595491 == 2'b11 && + CASE_guard95490_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h595490 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595490) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33608,12 +33591,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h595491 == 2'b0) ? + (guard__h595490 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h595491 == 2'b01 || guard__h595491 == 2'b10 || - guard__h595491 == 2'b11) && + (guard__h595490 == 2'b01 || guard__h595490 == 2'b10 || + guard__h595490 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33624,21 +33607,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h586422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h586421 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h586422) + case (guard__h586421) 2'b0, 2'b01, 2'b10: - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard86421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h586422 != 2'b11 || + CASE_guard86421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h586421 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586422) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586421) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33647,12 +33630,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h586422 == 2'b0) ? + (guard__h586421 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h586422 != 2'b01 && guard__h586422 != 2'b10 && - guard__h586422 != 2'b11 || + guard__h586421 != 2'b01 && guard__h586421 != 2'b10 && + guard__h586421 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33663,21 +33646,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595490 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595491) + case (guard__h595490) 2'b0, 2'b01, 2'b10: - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard95490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h595491 != 2'b11 || + CASE_guard95490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h595490 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595490) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33686,12 +33669,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h595491 == 2'b0) ? + (guard__h595490 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595491 != 2'b01 && guard__h595491 != 2'b10 && - guard__h595491 != 2'b11 || + guard__h595490 != 2'b01 && guard__h595490 != 2'b10 && + guard__h595490 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33702,21 +33685,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h577110 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577109 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577110) + case (guard__h577109) 2'b0, 2'b01, 2'b10: - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard77109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h577110 != 2'b11 || + CASE_guard77109_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h577109 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577110) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577109) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33725,12 +33708,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h577110 == 2'b0) ? + (guard__h577109 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h577110 != 2'b01 && guard__h577110 != 2'b10 && - guard__h577110 != 2'b11 || + guard__h577109 != 2'b01 && guard__h577109 != 2'b10 && + guard__h577109 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33741,28 +33724,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h537806 or - _theResult___fst_exp__h545767 or _theResult___exp__h546422) + always@(guard__h537805 or + _theResult___fst_exp__h545766 or _theResult___exp__h546421) begin - case (guard__h537806) + case (guard__h537805) 2'b0: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175 = - _theResult___fst_exp__h545767; + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q175 = + _theResult___fst_exp__h545766; 2'b01, 2'b10, 2'b11: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175 = - _theResult___exp__h546422; + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q175 = + _theResult___exp__h546421; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h545767 or + _theResult___fst_exp__h545766 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 or - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175) + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - _theResult___fst_exp__h545767; + _theResult___fst_exp__h545766; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611; @@ -33771,49 +33754,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175; + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = 11'd0; endcase end - always@(guard__h537806 or - _theResult___fst_exp__h545767 or - out_exp__h546425 or _theResult___exp__h546422) + always@(guard__h537805 or + _theResult___fst_exp__h545766 or + out_exp__h546424 or _theResult___exp__h546421) begin - case (guard__h537806) + case (guard__h537805) 2'b0, 2'b01: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 = - _theResult___fst_exp__h545767; + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q176 = + _theResult___fst_exp__h545766; 2'b10: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 = - out_exp__h546425; + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q176 = + out_exp__h546424; 2'b11: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 = - _theResult___exp__h546422; + CASE_guard37805_0b0_theResult___fst_exp45766_0_ETC__q176 = + _theResult___exp__h546421; endcase end - always@(guard__h547118 or - _theResult___fst_exp__h555344 or _theResult___exp__h556073) + always@(guard__h547117 or + _theResult___fst_exp__h555343 or _theResult___exp__h556072) begin - case (guard__h547118) + case (guard__h547117) 2'b0: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177 = - _theResult___fst_exp__h555344; + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q177 = + _theResult___fst_exp__h555343; 2'b01, 2'b10, 2'b11: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177 = - _theResult___exp__h556073; + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q177 = + _theResult___exp__h556072; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h555344 or + _theResult___fst_exp__h555343 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 or - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177) + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - _theResult___fst_exp__h555344; + _theResult___fst_exp__h555343; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649; @@ -33822,49 +33805,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177; + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = 11'd0; endcase end - always@(guard__h547118 or - _theResult___fst_exp__h555344 or - out_exp__h556076 or _theResult___exp__h556073) + always@(guard__h547117 or + _theResult___fst_exp__h555343 or + out_exp__h556075 or _theResult___exp__h556072) begin - case (guard__h547118) + case (guard__h547117) 2'b0, 2'b01: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 = - _theResult___fst_exp__h555344; + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q178 = + _theResult___fst_exp__h555343; 2'b10: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 = - out_exp__h556076; + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q178 = + out_exp__h556075; 2'b11: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 = - _theResult___exp__h556073; + CASE_guard47117_0b0_theResult___fst_exp55343_0_ETC__q178 = + _theResult___exp__h556072; endcase end - always@(guard__h556187 or - _theResult___fst_exp__h564177 or _theResult___exp__h564857) + always@(guard__h556186 or + _theResult___fst_exp__h564176 or _theResult___exp__h564856) begin - case (guard__h556187) + case (guard__h556186) 2'b0: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179 = - _theResult___fst_exp__h564177; + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q179 = + _theResult___fst_exp__h564176; 2'b01, 2'b10, 2'b11: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179 = - _theResult___exp__h564857; + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q179 = + _theResult___exp__h564856; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h564177 or + _theResult___fst_exp__h564176 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 or - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179) + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - _theResult___fst_exp__h564177; + _theResult___fst_exp__h564176; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680; @@ -33873,49 +33856,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179; + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = 11'd0; endcase end - always@(guard__h556187 or - _theResult___fst_exp__h564177 or - out_exp__h564860 or _theResult___exp__h564857) + always@(guard__h556186 or + _theResult___fst_exp__h564176 or + out_exp__h564859 or _theResult___exp__h564856) begin - case (guard__h556187) + case (guard__h556186) 2'b0, 2'b01: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 = - _theResult___fst_exp__h564177; + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q180 = + _theResult___fst_exp__h564176; 2'b10: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 = - out_exp__h564860; + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q180 = + out_exp__h564859; 2'b11: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 = - _theResult___exp__h564857; + CASE_guard56186_0b0_theResult___fst_exp64176_0_ETC__q180 = + _theResult___exp__h564856; endcase end - always@(guard__h595491 or - _theResult___fst_exp__h603481 or _theResult___exp__h604161) + always@(guard__h595490 or + _theResult___fst_exp__h603480 or _theResult___exp__h604160) begin - case (guard__h595491) + case (guard__h595490) 2'b0: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181 = - _theResult___fst_exp__h603481; + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q181 = + _theResult___fst_exp__h603480; 2'b01, 2'b10, 2'b11: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181 = - _theResult___exp__h604161; + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q181 = + _theResult___exp__h604160; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h603481 or + _theResult___fst_exp__h603480 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 or - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181) + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - _theResult___fst_exp__h603481; + _theResult___fst_exp__h603480; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910; @@ -33924,49 +33907,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181; + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = 11'd0; endcase end - always@(guard__h595491 or - _theResult___fst_exp__h603481 or - out_exp__h604164 or _theResult___exp__h604161) + always@(guard__h595490 or + _theResult___fst_exp__h603480 or + out_exp__h604163 or _theResult___exp__h604160) begin - case (guard__h595491) + case (guard__h595490) 2'b0, 2'b01: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 = - _theResult___fst_exp__h603481; + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q182 = + _theResult___fst_exp__h603480; 2'b10: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 = - out_exp__h604164; + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q182 = + out_exp__h604163; 2'b11: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 = - _theResult___exp__h604161; + CASE_guard95490_0b0_theResult___fst_exp03480_0_ETC__q182 = + _theResult___exp__h604160; endcase end - always@(guard__h586422 or - _theResult___fst_exp__h594648 or _theResult___exp__h595377) + always@(guard__h586421 or + _theResult___fst_exp__h594647 or _theResult___exp__h595376) begin - case (guard__h586422) + case (guard__h586421) 2'b0: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183 = - _theResult___fst_exp__h594648; + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q183 = + _theResult___fst_exp__h594647; 2'b01, 2'b10, 2'b11: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183 = - _theResult___exp__h595377; + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q183 = + _theResult___exp__h595376; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h594648 or + _theResult___fst_exp__h594647 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 or - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183) + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - _theResult___fst_exp__h594648; + _theResult___fst_exp__h594647; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879; @@ -33975,44 +33958,44 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183; + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = 11'd0; endcase end - always@(guard__h586422 or - _theResult___fst_exp__h594648 or - out_exp__h595380 or _theResult___exp__h595377) + always@(guard__h586421 or + _theResult___fst_exp__h594647 or + out_exp__h595379 or _theResult___exp__h595376) begin - case (guard__h586422) + case (guard__h586421) 2'b0, 2'b01: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 = - _theResult___fst_exp__h594648; + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q184 = + _theResult___fst_exp__h594647; 2'b10: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 = - out_exp__h595380; + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q184 = + out_exp__h595379; 2'b11: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 = - _theResult___exp__h595377; + CASE_guard86421_0b0_theResult___fst_exp94647_0_ETC__q184 = + _theResult___exp__h595376; endcase end - always@(guard__h537806 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537805 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537806) + case (guard__h537805) 2'b0, 2'b01, 2'b10: - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard37805_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h537806 == 2'b11 && + CASE_guard37805_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h537805 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537806) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537805) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34022,12 +34005,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h537806 == 2'b0) ? + (guard__h537805 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h537806 == 2'b01 || guard__h537806 == 2'b10 || - guard__h537806 == 2'b11) && + (guard__h537805 == 2'b01 || guard__h537805 == 2'b10 || + guard__h537805 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34038,23 +34021,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547118 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547117 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547118) + case (guard__h547117) 2'b0, 2'b01, 2'b10: - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard47117_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h547118 == 2'b11 && + CASE_guard47117_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h547117 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547118) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547117) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34064,12 +34047,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h547118 == 2'b0) ? + (guard__h547117 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h547118 == 2'b01 || guard__h547118 == 2'b10 || - guard__h547118 == 2'b11) && + (guard__h547117 == 2'b01 || guard__h547117 == 2'b10 || + guard__h547117 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34080,23 +34063,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h556187 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h556186 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h556187) + case (guard__h556186) 2'b0, 2'b01, 2'b10: - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard56186_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h556187 == 2'b11 && + CASE_guard56186_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h556186 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556187) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556186) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34106,12 +34089,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h556187 == 2'b0) ? + (guard__h556186 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h556187 == 2'b01 || guard__h556187 == 2'b10 || - guard__h556187 == 2'b11) && + (guard__h556186 == 2'b01 || guard__h556186 == 2'b10 || + guard__h556186 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34122,23 +34105,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547118 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547117 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547118) + case (guard__h547117) 2'b0, 2'b01, 2'b10: - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard47117_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h547118 != 2'b11 || + CASE_guard47117_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h547117 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547118) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547117) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34148,12 +34131,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h547118 == 2'b0) ? + (guard__h547117 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h547118 != 2'b01 && guard__h547118 != 2'b10 && - guard__h547118 != 2'b11 || + guard__h547117 != 2'b01 && guard__h547117 != 2'b10 && + guard__h547117 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34164,23 +34147,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h556187 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h556186 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h556187) + case (guard__h556186) 2'b0, 2'b01, 2'b10: - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard56186_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h556187 != 2'b11 || + CASE_guard56186_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h556186 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556187) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556186) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34190,12 +34173,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h556187 == 2'b0) ? + (guard__h556186 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h556187 != 2'b01 && guard__h556187 != 2'b10 && - guard__h556187 != 2'b11 || + guard__h556186 != 2'b01 && guard__h556186 != 2'b10 && + guard__h556186 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34206,23 +34189,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537806 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537805 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537806) + case (guard__h537805) 2'b0, 2'b01, 2'b10: - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard37805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h537806 != 2'b11 || + CASE_guard37805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h537805 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537806) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537805) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34232,12 +34215,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h537806 == 2'b0) ? + (guard__h537805 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h537806 != 2'b01 && guard__h537806 != 2'b10 && - guard__h537806 != 2'b11 || + guard__h537805 != 2'b01 && guard__h537805 != 2'b10 && + guard__h537805 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34248,28 +34231,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537806 or - _theResult___snd__h545718 or _theResult___sfd__h546423) + always@(guard__h537805 or + _theResult___snd__h545717 or _theResult___sfd__h546422) begin - case (guard__h537806) + case (guard__h537805) 2'b0: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197 = - _theResult___snd__h545718[56:5]; + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q197 = + _theResult___snd__h545717[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197 = - _theResult___sfd__h546423; + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q197 = + _theResult___sfd__h546422; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h545718 or + _theResult___snd__h545717 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 or - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197) + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - _theResult___snd__h545718[56:5]; + _theResult___snd__h545717[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706; @@ -34278,48 +34261,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197; + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = 52'd0; endcase end - always@(guard__h537806 or - _theResult___snd__h545718 or - out_sfd__h546426 or _theResult___sfd__h546423) + always@(guard__h537805 or + _theResult___snd__h545717 or + out_sfd__h546425 or _theResult___sfd__h546422) begin - case (guard__h537806) + case (guard__h537805) 2'b0, 2'b01: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 = - _theResult___snd__h545718[56:5]; + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q198 = + _theResult___snd__h545717[56:5]; 2'b10: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 = - out_sfd__h546426; + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q198 = + out_sfd__h546425; 2'b11: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 = - _theResult___sfd__h546423; + CASE_guard37805_0b0_theResult___snd45717_BITS__ETC__q198 = + _theResult___sfd__h546422; endcase end - always@(guard__h547118 or sfdin__h555338 or _theResult___sfd__h556074) + always@(guard__h547117 or sfdin__h555337 or _theResult___sfd__h556073) begin - case (guard__h547118) + case (guard__h547117) 2'b0: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h555338[56:5]; + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q199 = + sfdin__h555337[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h556074; + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q199 = + _theResult___sfd__h556073; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h555338 or + sfdin__h555337 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 or - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199) + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - sfdin__h555338[56:5]; + sfdin__h555337[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732; @@ -34328,48 +34311,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199; + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = 52'd0; endcase end - always@(guard__h547118 or - sfdin__h555338 or out_sfd__h556077 or _theResult___sfd__h556074) + always@(guard__h547117 or + sfdin__h555337 or out_sfd__h556076 or _theResult___sfd__h556073) begin - case (guard__h547118) + case (guard__h547117) 2'b0, 2'b01: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h555338[56:5]; + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q200 = + sfdin__h555337[56:5]; 2'b10: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h556077; + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q200 = + out_sfd__h556076; 2'b11: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h556074; + CASE_guard47117_0b0_sfdin55337_BITS_56_TO_5_0b_ETC__q200 = + _theResult___sfd__h556073; endcase end - always@(guard__h556187 or - _theResult___snd__h564123 or _theResult___sfd__h564858) + always@(guard__h556186 or + _theResult___snd__h564122 or _theResult___sfd__h564857) begin - case (guard__h556187) + case (guard__h556186) 2'b0: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201 = - _theResult___snd__h564123[56:5]; + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q201 = + _theResult___snd__h564122[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201 = - _theResult___sfd__h564858; + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q201 = + _theResult___sfd__h564857; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h564123 or + _theResult___snd__h564122 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 or - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201) + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - _theResult___snd__h564123[56:5]; + _theResult___snd__h564122[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751; @@ -34378,49 +34361,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201; + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = 52'd0; endcase end - always@(guard__h556187 or - _theResult___snd__h564123 or - out_sfd__h564861 or _theResult___sfd__h564858) + always@(guard__h556186 or + _theResult___snd__h564122 or + out_sfd__h564860 or _theResult___sfd__h564857) begin - case (guard__h556187) + case (guard__h556186) 2'b0, 2'b01: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 = - _theResult___snd__h564123[56:5]; + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q202 = + _theResult___snd__h564122[56:5]; 2'b10: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 = - out_sfd__h564861; + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q202 = + out_sfd__h564860; 2'b11: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 = - _theResult___sfd__h564858; + CASE_guard56186_0b0_theResult___snd64122_BITS__ETC__q202 = + _theResult___sfd__h564857; endcase end - always@(guard__h508265 or - _theResult___fst_exp__h516491 or _theResult___exp__h517220) + always@(guard__h508264 or + _theResult___fst_exp__h516490 or _theResult___exp__h517219) begin - case (guard__h508265) + case (guard__h508264) 2'b0: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203 = - _theResult___fst_exp__h516491; + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q203 = + _theResult___fst_exp__h516490; 2'b01, 2'b10, 2'b11: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203 = - _theResult___exp__h517220; + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q203 = + _theResult___exp__h517219; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h516491 or + _theResult___fst_exp__h516490 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 or - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203) + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - _theResult___fst_exp__h516491; + _theResult___fst_exp__h516490; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169; @@ -34429,49 +34412,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203; + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = 11'd0; endcase end - always@(guard__h508265 or - _theResult___fst_exp__h516491 or - out_exp__h517223 or _theResult___exp__h517220) + always@(guard__h508264 or + _theResult___fst_exp__h516490 or + out_exp__h517222 or _theResult___exp__h517219) begin - case (guard__h508265) + case (guard__h508264) 2'b0, 2'b01: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 = - _theResult___fst_exp__h516491; + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q204 = + _theResult___fst_exp__h516490; 2'b10: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 = - out_exp__h517223; + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q204 = + out_exp__h517222; 2'b11: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 = - _theResult___exp__h517220; + CASE_guard08264_0b0_theResult___fst_exp16490_0_ETC__q204 = + _theResult___exp__h517219; endcase end - always@(guard__h517334 or - _theResult___fst_exp__h525324 or _theResult___exp__h526004) + always@(guard__h517333 or + _theResult___fst_exp__h525323 or _theResult___exp__h526003) begin - case (guard__h517334) + case (guard__h517333) 2'b0: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205 = - _theResult___fst_exp__h525324; + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q205 = + _theResult___fst_exp__h525323; 2'b01, 2'b10, 2'b11: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205 = - _theResult___exp__h526004; + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q205 = + _theResult___exp__h526003; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h525324 or + _theResult___fst_exp__h525323 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 or - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205) + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - _theResult___fst_exp__h525324; + _theResult___fst_exp__h525323; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200; @@ -34480,98 +34463,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205; + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = 11'd0; endcase end - always@(guard__h517334 or - _theResult___fst_exp__h525324 or - out_exp__h526007 or _theResult___exp__h526004) + always@(guard__h517333 or + _theResult___fst_exp__h525323 or + out_exp__h526006 or _theResult___exp__h526003) begin - case (guard__h517334) + case (guard__h517333) 2'b0, 2'b01: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 = - _theResult___fst_exp__h525324; + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q206 = + _theResult___fst_exp__h525323; 2'b10: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 = - out_exp__h526007; + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q206 = + out_exp__h526006; 2'b11: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 = - _theResult___exp__h526004; + CASE_guard17333_0b0_theResult___fst_exp25323_0_ETC__q206 = + _theResult___exp__h526003; endcase end - always@(guard__h508265 or sfdin__h516485 or _theResult___sfd__h517221) + always@(guard__h498952 or + _theResult___snd__h506864 or _theResult___sfd__h507569) begin - case (guard__h508265) + case (guard__h498952) 2'b0: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h516485[56:5]; + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q207 = + _theResult___snd__h506864[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h517221; + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q207 = + _theResult___sfd__h507569; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h516485 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q207) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - sfdin__h516485[56:5]; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q207; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - 52'd0; - endcase - end - always@(guard__h508265 or - sfdin__h516485 or out_sfd__h517224 or _theResult___sfd__h517221) - begin - case (guard__h508265) - 2'b0, 2'b01: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h516485[56:5]; - 2'b10: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h517224; - 2'b11: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h517221; - endcase - end - always@(guard__h498953 or - _theResult___snd__h506865 or _theResult___sfd__h507570) - begin - case (guard__h498953) - 2'b0: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q209 = - _theResult___snd__h506865[56:5]; - 2'b01, 2'b10, 2'b11: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q209 = - _theResult___sfd__h507570; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h506865 or + _theResult___snd__h506864 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 or - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q209) + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - _theResult___snd__h506865[56:5]; + _theResult___snd__h506864[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226; @@ -34580,49 +34514,98 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q209; + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = 52'd0; endcase end - always@(guard__h498953 or - _theResult___snd__h506865 or - out_sfd__h507573 or _theResult___sfd__h507570) + always@(guard__h498952 or + _theResult___snd__h506864 or + out_sfd__h507572 or _theResult___sfd__h507569) begin - case (guard__h498953) + case (guard__h498952) 2'b0, 2'b01: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q210 = - _theResult___snd__h506865[56:5]; + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q208 = + _theResult___snd__h506864[56:5]; 2'b10: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q210 = - out_sfd__h507573; + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q208 = + out_sfd__h507572; 2'b11: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q210 = - _theResult___sfd__h507570; + CASE_guard98952_0b0_theResult___snd06864_BITS__ETC__q208 = + _theResult___sfd__h507569; endcase end - always@(guard__h517334 or - _theResult___snd__h525270 or _theResult___sfd__h526005) + always@(guard__h508264 or sfdin__h516484 or _theResult___sfd__h517220) begin - case (guard__h517334) + case (guard__h508264) 2'b0: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211 = - _theResult___snd__h525270[56:5]; + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q209 = + sfdin__h516484[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211 = - _theResult___sfd__h526005; + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q209 = + _theResult___sfd__h517220; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h525270 or + sfdin__h516484 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q209) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + sfdin__h516484[56:5]; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q209; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = + 52'd0; + endcase + end + always@(guard__h508264 or + sfdin__h516484 or out_sfd__h517223 or _theResult___sfd__h517220) + begin + case (guard__h508264) + 2'b0, 2'b01: + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q210 = + sfdin__h516484[56:5]; + 2'b10: + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q210 = + out_sfd__h517223; + 2'b11: + CASE_guard08264_0b0_sfdin16484_BITS_56_TO_5_0b_ETC__q210 = + _theResult___sfd__h517220; + endcase + end + always@(guard__h517333 or + _theResult___snd__h525269 or _theResult___sfd__h526004) + begin + case (guard__h517333) + 2'b0: + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q211 = + _theResult___snd__h525269[56:5]; + 2'b01, 2'b10, 2'b11: + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q211 = + _theResult___sfd__h526004; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + _theResult___snd__h525269 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 or - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211) + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - _theResult___snd__h525270[56:5]; + _theResult___snd__h525269[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272; @@ -34631,49 +34614,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211; + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = 52'd0; endcase end - always@(guard__h517334 or - _theResult___snd__h525270 or - out_sfd__h526008 or _theResult___sfd__h526005) + always@(guard__h517333 or + _theResult___snd__h525269 or + out_sfd__h526007 or _theResult___sfd__h526004) begin - case (guard__h517334) + case (guard__h517333) 2'b0, 2'b01: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 = - _theResult___snd__h525270[56:5]; + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q212 = + _theResult___snd__h525269[56:5]; 2'b10: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 = - out_sfd__h526008; + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q212 = + out_sfd__h526007; 2'b11: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 = - _theResult___sfd__h526005; + CASE_guard17333_0b0_theResult___snd25269_BITS__ETC__q212 = + _theResult___sfd__h526004; endcase end - always@(guard__h577110 or - _theResult___snd__h585022 or _theResult___sfd__h585727) + always@(guard__h577109 or + _theResult___snd__h585021 or _theResult___sfd__h585726) begin - case (guard__h577110) + case (guard__h577109) 2'b0: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213 = - _theResult___snd__h585022[56:5]; + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q213 = + _theResult___snd__h585021[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213 = - _theResult___sfd__h585727; + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q213 = + _theResult___sfd__h585726; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h585022 or + _theResult___snd__h585021 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 or - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213) + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - _theResult___snd__h585022[56:5]; + _theResult___snd__h585021[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936; @@ -34682,48 +34665,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213; + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = 52'd0; endcase end - always@(guard__h577110 or - _theResult___snd__h585022 or - out_sfd__h585730 or _theResult___sfd__h585727) + always@(guard__h577109 or + _theResult___snd__h585021 or + out_sfd__h585729 or _theResult___sfd__h585726) begin - case (guard__h577110) + case (guard__h577109) 2'b0, 2'b01: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 = - _theResult___snd__h585022[56:5]; + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q214 = + _theResult___snd__h585021[56:5]; 2'b10: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 = - out_sfd__h585730; + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q214 = + out_sfd__h585729; 2'b11: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 = - _theResult___sfd__h585727; + CASE_guard77109_0b0_theResult___snd85021_BITS__ETC__q214 = + _theResult___sfd__h585726; endcase end - always@(guard__h586422 or sfdin__h594642 or _theResult___sfd__h595378) + always@(guard__h586421 or sfdin__h594641 or _theResult___sfd__h595377) begin - case (guard__h586422) + case (guard__h586421) 2'b0: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h594642[56:5]; + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h594641[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h595378; + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h595377; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h594642 or + sfdin__h594641 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 or - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215) + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - sfdin__h594642[56:5]; + sfdin__h594641[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962; @@ -34732,24 +34715,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215; + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = 52'd0; endcase end - always@(guard__h586422 or - sfdin__h594642 or out_sfd__h595381 or _theResult___sfd__h595378) + always@(guard__h586421 or + sfdin__h594641 or out_sfd__h595380 or _theResult___sfd__h595377) begin - case (guard__h586422) + case (guard__h586421) 2'b0, 2'b01: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h594642[56:5]; + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h594641[56:5]; 2'b10: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h595381; + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h595380; 2'b11: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h595378; + CASE_guard86421_0b0_sfdin94641_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h595377; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34784,28 +34767,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963; endcase end - always@(guard__h595491 or - _theResult___snd__h603427 or _theResult___sfd__h604162) + always@(guard__h595490 or + _theResult___snd__h603426 or _theResult___sfd__h604161) begin - case (guard__h595491) + case (guard__h595490) 2'b0: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217 = - _theResult___snd__h603427[56:5]; + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q217 = + _theResult___snd__h603426[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217 = - _theResult___sfd__h604162; + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q217 = + _theResult___sfd__h604161; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h603427 or + _theResult___snd__h603426 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 or - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217) + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - _theResult___snd__h603427[56:5]; + _theResult___snd__h603426[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981; @@ -34814,25 +34797,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217; + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = 52'd0; endcase end - always@(guard__h595491 or - _theResult___snd__h603427 or - out_sfd__h604165 or _theResult___sfd__h604162) + always@(guard__h595490 or + _theResult___snd__h603426 or + out_sfd__h604164 or _theResult___sfd__h604161) begin - case (guard__h595491) + case (guard__h595490) 2'b0, 2'b01: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 = - _theResult___snd__h603427[56:5]; + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q218 = + _theResult___snd__h603426[56:5]; 2'b10: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 = - out_sfd__h604165; + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q218 = + out_sfd__h604164; 2'b11: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 = - _theResult___sfd__h604162; + CASE_guard95490_0b0_theResult___snd03426_BITS__ETC__q218 = + _theResult___sfd__h604161; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -35156,10 +35139,10 @@ module mkCore(CLK, 4'd11; endcase end - always@(k__h674093 or + always@(k__h674091 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h674093) + case (k__h674091) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3543_co_ETC___d13553 = coreFix_aluExe_0_rsAlu$canEnq; @@ -35198,10 +35181,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13565; endcase end - always@(k__h674093 or + always@(k__h674091 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h674093) + case (k__h674091) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13586 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -35272,6 +35255,33 @@ module mkCore(CLK, endcase end always@(fetchStage$pipelines_1_first) + begin + case (fetchStage$pipelines_1_first[177:175]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = + fetchStage$pipelines_1_first[177:175]; + default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228 = 3'd7; + endcase + end + always@(fetchStage$pipelines_1_first or + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228) + begin + case (fetchStage$pipelines_1_first[194:192]) + 3'd0, 3'd1, 3'd2, 3'd3: + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686 = + fetchStage$pipelines_1_first[194:174]; + 3'd4: + IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686 = + { fetchStage$pipelines_1_first[194:192], + 9'h0AA, + fetchStage$pipelines_1_first[182:178], + CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, + fetchStage$pipelines_1_first[174] }; + default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686 = + 21'd1485482; + endcase + end + always@(fetchStage$pipelines_1_first) begin case (fetchStage$pipelines_1_first[172:161]) 12'd1, @@ -35314,47 +35324,20 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = + CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 = fetchStage$pipelines_1_first[172:161]; - default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 = + default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q229 = 12'd2303; endcase end - always@(fetchStage$pipelines_1_first) - begin - case (fetchStage$pipelines_1_first[177:175]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = - fetchStage$pipelines_1_first[177:175]; - default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = 3'd7; - endcase - end - always@(fetchStage$pipelines_1_first or - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229) - begin - case (fetchStage$pipelines_1_first[194:192]) - 3'd0, 3'd1, 3'd2, 3'd3: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686 = - fetchStage$pipelines_1_first[194:174]; - 3'd4: - IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686 = - { fetchStage$pipelines_1_first[194:192], - 9'h0AA, - fetchStage$pipelines_1_first[182:178], - CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229, - fetchStage$pipelines_1_first[174] }; - default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686 = - 21'd1485482; - endcase - end - always@(idx__h689688 or + always@(idx__h689686 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13837 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13843 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h689688) + case (idx__h689686) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13862 = fetchStage$pipelines_0_canDeq && @@ -35487,29 +35470,29 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13828; endcase end + always@(k__h674091 or + coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) + begin + case (k__h674091) + 1'd0: + CASE_k74091_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + coreFix_aluExe_0_rsAlu$RDY_enq; + 1'd1: + CASE_k74091_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + coreFix_aluExe_1_rsAlu$RDY_enq; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q232 = + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 = coreFix_memExe_lsq$RDY_enqSt; endcase end - always@(k__h674093 or - coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) - begin - case (k__h674093) - 1'd0: - CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = - coreFix_aluExe_0_rsAlu$RDY_enq; - 1'd1: - CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q233 = - coreFix_aluExe_1_rsAlu$RDY_enq; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13621 or @@ -35532,7 +35515,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13621 or - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14022 or + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14022 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3543_co_ETC___d13553 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14009 or @@ -35554,7 +35537,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13621 || - regRenamingTable_RDY_rename_0_getRename__3399__ETC___d14022; + regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14022; endcase end always@(fetchStage$pipelines_0_first or @@ -35598,14 +35581,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13565; endcase end - always@(idx__h689688 or + always@(idx__h689686 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14065 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14072 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h689688) + case (idx__h689686) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14076 = (!fetchStage$pipelines_0_canDeq || @@ -35744,10 +35727,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14219 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14219 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14216 = + coreFix_memExe_lsq$enqLdTag[4:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14216 = + coreFix_memExe_lsq$enqStTag[4:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -35755,10 +35738,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14216 = - coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14216 = - coreFix_memExe_lsq$enqStTag[4:0]; + IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14219 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14219 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_1_first or @@ -36514,28 +36497,6 @@ module mkCore(CLK, { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q264 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -36552,9 +36513,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q265 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 = 4'd15; endcase end @@ -38389,7 +38372,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[25]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 558, column 48\nmust be executed"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 578, column 48\nmust be executed"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[25]) @@ -38401,7 +38384,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && rob$deqPort_0_deq_data[11:0] != 12'd0) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 559, column 36\ncannot have spec bits"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 579, column 36\ncannot have spec bits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitTrap_flush && rob$deqPort_0_deq_data[11:0] != 12'd0) @@ -38413,7 +38396,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitKilledLd && rob$deqPort_0_deq_data[12]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 672, column 39\ncannot increment epoch before"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 695, column 39\ncannot increment epoch before"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitKilledLd && rob$deqPort_0_deq_data[12]) @@ -38425,7 +38408,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitKilledLd && !rob$deqPort_0_deq_data[25]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 673, column 48\nmust be executed"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 696, column 48\nmust be executed"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitKilledLd && !rob$deqPort_0_deq_data[25]) @@ -38437,7 +38420,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitKilledLd && rob$deqPort_0_deq_data[11:0] != 12'd0) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 674, column 36\ncannot have spec bits"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 697, column 36\ncannot have spec bits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitKilledLd && rob$deqPort_0_deq_data[11:0] != 12'd0) @@ -38571,7 +38554,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd13 && (rob$deqPort_0_deq_data[97:96] == 2'd0 || rob$deqPort_0_deq_data[97:96] == 2'd1)) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 712, column 33\nmust have csr data"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 736, column 33\nmust have csr data"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[257:253] == 5'd13 && @@ -38592,7 +38575,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && NOT_IF_rob_deqPort_0_deq_data__4451_BITS_97_TO_ETC___d14957) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 730, column 39\nppc must be pc + 4"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 754, column 39\nppc must be pc + 4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && NOT_IF_rob_deqPort_0_deq_data__4451_BITS_97_TO_ETC___d14957) @@ -38604,7 +38587,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && !rob$deqPort_0_deq_data[12]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 789, column 38\nmust have already incremented epoch"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 815, column 38\nmust have already incremented epoch"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && !rob$deqPort_0_deq_data[12]) @@ -38616,7 +38599,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && NOT_rob_deqPort_0_deq_data__4451_BITS_257_TO_2_ETC___d14967) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 790, column 54\nonly CSR has valid csr idx"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 816, column 54\nonly CSR has valid csr idx"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && NOT_rob_deqPort_0_deq_data__4451_BITS_257_TO_2_ETC___d14967) @@ -38630,7 +38613,7 @@ module mkCore(CLK, if (WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[31:27] != 5'd0 || rob$deqPort_0_deq_data[26])) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 791, column 60\ncannot dirty FPU"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 817, column 60\ncannot dirty FPU"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[31:27] != 5'd0 || @@ -38643,7 +38626,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[11:0] != 12'd0) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 792, column 36\ncannot have spec bits"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 818, column 36\ncannot have spec bits"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[11:0] != 12'd0) @@ -38655,7 +38638,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && !rob$deqPort_0_deq_data[168]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 793, column 37\nmust have claimed phy reg"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 819, column 37\nmust have claimed phy reg"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && !rob$deqPort_0_deq_data[168]) @@ -38761,7 +38744,7 @@ module mkCore(CLK, if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && !rob$deqPort_0_deq_data[168]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 912, column 49\nshould have renamed"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 941, column 49\nshould have renamed"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -38970,7 +38953,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] != 5'd19 && rob$deqPort_1_deq_data[257:253] != 5'd20 && !rob$deqPort_1_deq_data[168]) - $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 912, column 49\nshould have renamed"); + $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 941, column 49\nshould have renamed"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_1_canDeq && @@ -39077,21 +39060,21 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12101[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626444)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626443)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12101[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626444)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626443)) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 283, column 84\nCsr inst ppc = pc+4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12101[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626444)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626443)) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -39128,21 +39111,21 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12775[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648781)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648779)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12775[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648781)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648779)) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 283, column 84\nCsr inst ppc = pc+4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12775[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648781)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648779)) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -39938,15 +39921,15 @@ module mkCore(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609619 == 2'd0) + v__h609618 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609619 == 2'd0) + v__h609618 == 2'd0) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv\", line 172, column 38\ncredit underflow"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609619 == 2'd0) + v__h609618 == 2'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v index 1a5c468..adfb9e5 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkFabric_2x3.v @@ -3313,17 +3313,17 @@ module mkFabric_2x3(CLK, 8'd0 : x__h12203 ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; + { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, + fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = - { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, - fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_0$D_OUT[3:0], 66'd3, @@ -3734,23 +3734,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: @@ -3761,9 +3761,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && @@ -3862,23 +3862,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: @@ -3889,9 +3889,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v index 50edc66..1750dac 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v @@ -1997,9 +1997,9 @@ module mkProc(CLK, wire [511 : 0] IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1301, SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1451, new_cline__h135439; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1589, + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1588, SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1434; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1584, + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1583, SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1417; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1400; wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__70_BITS_14_ETC___d393; @@ -2139,8 +2139,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1271, IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1291, IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1307, - IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657, + IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656, IF_mmioPlatform_mtimecmp_0_48_ULE_IF_NOT_mmioP_ETC___d613, IF_mmioPlatform_reqFunc_28_BITS_5_TO_4_29_EQ_0_ETC___d445, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__83__ETC___d192, @@ -2155,8 +2155,8 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011, NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091, NOT_enqDst_1_0_dummy2_0_read__349_350_OR_NOT_e_ETC___d1365, - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707, + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d742, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d750, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d755, @@ -2177,8 +2177,8 @@ module mkProc(CLK, NOT_propDstIdx_1_0_dummy2_1_read__318_319_OR_I_ETC___d1362, NOT_propDstIdx_1_1_dummy2_1_read__336_337_OR_I_ETC___d1469, NOT_propDstIdx_1_dummy2_1_read__067_068_OR_IF__ETC___d1167, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522, mmioPlatform_cycle_39_ULT_99___d340, mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d323, @@ -3183,32 +3183,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3548,7 +3552,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3566,7 +3570,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3584,7 +3588,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3594,7 +3598,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3603,7 +3607,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3614,7 +3618,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3623,7 +3627,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -3631,7 +3635,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -3655,7 +3659,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3672,15 +3676,15 @@ module mkProc(CLK, // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -3914,7 +3918,7 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1589, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1588, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? new_dword__h90069 : @@ -4315,10 +4319,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674, + IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4332,8 +4336,8 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr @@ -5183,7 +5187,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5213,11 +5217,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5434,15 +5438,6 @@ module mkProc(CLK, assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ; // remaining internal signals - module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], - mmioPlatform_reqBE_BIT_4___h29827 && - mmioPlatform_reqBE_BIT_0___h29867, - 2'd0 }), - .amoExec_current_data(x__h37121), - .amoExec_in_data(mmioPlatform_reqData__h48527), - .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29827 && - !mmioPlatform_reqBE_BIT_0___h29867), - .amoExec(x__h31851)); module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], mmioPlatform_reqBE_BIT_4___h29827 && mmioPlatform_reqBE_BIT_0___h29867, @@ -5452,6 +5447,15 @@ module mkProc(CLK, .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29827 && !mmioPlatform_reqBE_BIT_0___h29867), .amoExec(x__h34761)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], + mmioPlatform_reqBE_BIT_4___h29827 && + mmioPlatform_reqBE_BIT_0___h29867, + 2'd0 }), + .amoExec_current_data(x__h37121), + .amoExec_in_data(mmioPlatform_reqData__h48527), + .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29827 && + !mmioPlatform_reqBE_BIT_0___h29867), + .amoExec(x__h31851)); module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0], mmioPlatform_reqBE_BIT_4___h29827 && mmioPlatform_reqBE_BIT_0___h29867, @@ -5565,7 +5569,7 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1286, IF_enqDst_1_0_lat_1_whas__263_THEN_enqDst_1_0__ETC___d1309 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1584 = + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1583 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? new_dword__h90069 : @@ -5582,8 +5586,8 @@ module mkProc(CLK, 3'd4) ? new_dword__h90069 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1589 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1584, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1588 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1583, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? new_dword__h90069 : @@ -5592,11 +5596,11 @@ module mkProc(CLK, 3'd2) ? new_dword__h90069 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_curReq_23_BITS_2_TO_0_73_EQ_0x_ETC___d821 = @@ -5836,14 +5840,14 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__318_AND__ETC___d1359 || IF_NOT_propDstIdx_1_0_dummy2_1_read__318_319_O_ETC___d1363) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656 ; assign NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d742 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && @@ -6026,9 +6030,9 @@ module mkProc(CLK, assign line_addr__h102528 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 = line_addr__h102528 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 = + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 = line_addr__h102442 == llc_mem_server_rg_cacheline_cache_addr ; assign mask__h90065 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? @@ -6409,19 +6413,6 @@ module mkProc(CLK, 3'd7: dword__h94378 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end - always@(llc$dma_respLd_first) - begin - case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h132665 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h132665 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h132665 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h132665 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h132665 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h132665 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h132665 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h132665 = llc$dma_respLd_first[516:453]; - endcase - end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) @@ -6435,6 +6426,19 @@ module mkProc(CLK, 3'd7: data64__h148576 = llc$to_mem_toM_first[511:448]; endcase end + always@(llc$dma_respLd_first) + begin + case (llc$dma_respLd_first[2:0]) + 3'd0: ld_data__h132665 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h132665 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h132665 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h132665 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h132665 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h132665 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h132665 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h132665 = llc$dma_respLd_first[516:453]; + endcase + end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) @@ -9363,7 +9367,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9377,7 +9381,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) begin v__h135136 = $stime; #0; @@ -9385,63 +9389,63 @@ module mkProc(CLK, v__h135130 = v__h135136 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h135130, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9517,119 +9521,119 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && @@ -10857,139 +10861,139 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", mem_req_wr_addr_awaddr__h148661); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", data64__h148576); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", strb8__h148577); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11076,103 +11080,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", mem_req_rd_addr_araddr__h134737); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) begin v__h161444 = $stime; #0; @@ -11180,41 +11184,41 @@ module mkProc(CLK, v__h161438 = v__h161444 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", v__h161438, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index 362411c..6a3db30 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -90,6 +90,7 @@ interface CsrFile; Bool init_for_way0, Bit #(5) old_fflags, Data old_mstatus); + method Data getMIP; `endif // The WARL transform performed during CSRRx writes to a CSR @@ -898,6 +899,10 @@ module mkCsrFile #(Data hartid)(CsrFile); return tuple2 (new_fflags, new_mstatus); endmethod + + method Data getMIP; + return mip_csr; + endmethod `endif method Data warl_xform (CSR csr, Data x); diff --git a/src_Core/Core/Trace_Data2.bsv b/src_Core/Core/Trace_Data2.bsv index d34d63d..f273ec2 100644 --- a/src_Core/Core/Trace_Data2.bsv +++ b/src_Core/Core/Trace_Data2.bsv @@ -24,7 +24,13 @@ import ReorderBuffer :: *; // add to the critical path or scheduling requirements of CommitStage. typedef struct { - Bit #(64) serial_num; // TV message serial number + // TV message serial number + Bit #(64) serial_num; + + // For asynchronous CSR updates (e.g., MIP change on external interrupt) + Maybe #(Tuple2 #(Bit #(12), Data)) maybe_csr_upd; + + // Remaining fields relevant only if maybe_csr_upd is Invalid Addr pc; Bit #(32) orig_inst; // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b) IType iType; diff --git a/src_Core/Core/Trace_Data2_to_Trace_Data.bsv b/src_Core/Core/Trace_Data2_to_Trace_Data.bsv index c2ae9b8..db93548 100644 --- a/src_Core/Core/Trace_Data2_to_Trace_Data.bsv +++ b/src_Core/Core/Trace_Data2_to_Trace_Data.bsv @@ -76,6 +76,9 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC); if (serial_num == 0) td = mkTrace_RESET; + else if (td2.maybe_csr_upd matches tagged Valid { .csr_addr, .csr_value }) + td = mkTrace_CSR_WRITE (csr_addr, csr_value); + else if (isValid (td2.trap)) td = mkTrace_TRAP (td2.tvec, isize, diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index 279a009..8c60a0a 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -183,6 +183,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); function Action fa_to_TV (Integer way, Bit #(64) serial_num, + Maybe #(Tuple2 #(Bit #(12), Data)) maybe_csr_upd, ToReorderBuffer deq_data, Bit #(5) fflags, Data mstatus, @@ -192,6 +193,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); let tval = (m_trap_updates matches tagged Valid .tu ? tu.tval : deq_data.tval); let upd_pc = (m_ret_updates matches tagged Valid .ru ? ru.new_pc : deq_data.pc); let x = Trace_Data2 {serial_num: serial_num, + maybe_csr_upd: maybe_csr_upd, pc: upd_pc, orig_inst: deq_data.orig_inst, iType: deq_data.iType, @@ -230,10 +232,28 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); rule rl_send_tv_reset (rg_just_after_reset); Bit #(64) serial_num = 0; - fa_to_TV (way0, serial_num, no_deq_data, no_fflags, no_mstatus, no_trap_updates, no_ret_updates); + fa_to_TV (way0, serial_num, + tagged Invalid, + no_deq_data, no_fflags, no_mstatus, no_trap_updates, no_ret_updates); rg_just_after_reset <= False; rg_serial_num <= 1; endrule + + Reg #(Data) rg_old_mip_csr_val <- mkReg (0); + + Data new_mip_csr_val = inIfc.csrfIfc.getMIP; + + Bool send_mip_csr_change_to_tv = (new_mip_csr_val != rg_old_mip_csr_val); + + rule rl_send_mip_csr_change_to_tv ((! rg_just_after_reset) && send_mip_csr_change_to_tv); + fa_to_TV (way0, rg_serial_num, + tagged Valid (tuple2 (pack (CSRmip), new_mip_csr_val)), + no_deq_data, no_fflags, no_mstatus, no_trap_updates, no_ret_updates); + rg_old_mip_csr_val <= new_mip_csr_val; + rg_serial_num <= rg_serial_num + 1; + endrule +`else + Bool send_mip_csr_change_to_tv = False; `endif // func units @@ -560,10 +580,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); endrule rule doCommitTrap_handle( + commitTrap matches tagged Valid .trap `ifdef INCLUDE_GDB_CONTROL - (rg_run_state == RUN_STATE_RUNNING) &&& + &&& (rg_run_state == RUN_STATE_RUNNING) `endif - commitTrap matches tagged Valid .trap); + &&& (! send_mip_csr_change_to_tv)); // reset commitTrap commitTrap <= Invalid; @@ -624,7 +645,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); inIfc.redirectPc(trap_updates.new_pc); `ifdef INCLUDE_TANDEM_VERIF - fa_to_TV (way0, rg_serial_num, x, no_fflags, no_mstatus, tagged Valid trap_updates, no_ret_updates); + fa_to_TV (way0, rg_serial_num, + tagged Invalid, + x, no_fflags, no_mstatus, tagged Valid trap_updates, no_ret_updates); `endif rg_serial_num <= rg_serial_num + 1; @@ -683,7 +706,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); !isValid(rob.deqPort[0].deq_data.trap) && !isValid(rob.deqPort[0].deq_data.ldKilled) && rob.deqPort[0].deq_data.rob_inst_state == Executed && - isSystem(rob.deqPort[0].deq_data.iType) + isSystem(rob.deqPort[0].deq_data.iType) && + (! send_mip_csr_change_to_tv) ); rob.deqPort[0].deq; let x = rob.deqPort[0].deq_data; @@ -748,7 +772,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); inIfc.redirectPc(next_pc); `ifdef INCLUDE_TANDEM_VERIF - fa_to_TV (way0, rg_serial_num, x, no_fflags, no_mstatus, no_trap_updates, m_ret_updates); + fa_to_TV (way0, rg_serial_num, + tagged Invalid, + x, no_fflags, no_mstatus, no_trap_updates, m_ret_updates); `endif rg_serial_num <= rg_serial_num + 1; @@ -832,7 +858,8 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); !isValid(rob.deqPort[0].deq_data.trap) && !isValid(rob.deqPort[0].deq_data.ldKilled) && rob.deqPort[0].deq_data.rob_inst_state == Executed && - !isSystem(rob.deqPort[0].deq_data.iType) + !isSystem(rob.deqPort[0].deq_data.iType) && + (! send_mip_csr_change_to_tv) ); // stop superscalar commit after we // 1. see a trap or system inst or killed Ld @@ -897,7 +924,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); Bool is_fmv_x_dw = ((x.orig_inst & 32'b_1111110_11111_00000_111_00000_1111111) == 32'b_1110000_00000_00000_000_00000_1010011); - fa_to_TV (i, rg_serial_num + instret, x, + fa_to_TV (i, rg_serial_num + instret, + tagged Invalid, + x, (is_fmv_x_dw ? 5'b0 : po_fflags), po_mstatus, no_trap_updates, no_ret_updates); diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 07e8558..4a78ad7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -98,9 +98,9 @@ // RDY_hart0_csr_mem_server_request_put O 1 reg // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg -// v_to_TV_0_get O 785 +// v_to_TV_0_get O 862 // RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 785 +// v_to_TV_1_get O 862 // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset @@ -668,16 +668,16 @@ module mkCore(CLK, // actionvalue method v_to_TV_0_get input EN_v_to_TV_0_get; - output [784 : 0] v_to_TV_0_get; + output [861 : 0] v_to_TV_0_get; output RDY_v_to_TV_0_get; // actionvalue method v_to_TV_1_get input EN_v_to_TV_1_get; - output [784 : 0] v_to_TV_1_get; + output [861 : 0] v_to_TV_1_get; output RDY_v_to_TV_1_get; // signals for module outputs - wire [784 : 0] v_to_TV_0_get, v_to_TV_1_get; + wire [861 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first; wire [162 : 0] deadlock_commitInstStuck_get, deadlock_commitUserInstStuck_get; @@ -845,6 +845,11 @@ module mkCore(CLK, wire commitStage_rg_just_after_reset$D_IN, commitStage_rg_just_after_reset$EN; + // register commitStage_rg_old_mip_csr_val + reg [63 : 0] commitStage_rg_old_mip_csr_val; + wire [63 : 0] commitStage_rg_old_mip_csr_val$D_IN; + wire commitStage_rg_old_mip_csr_val$EN; + // register commitStage_rg_run_state reg commitStage_rg_run_state; wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN; @@ -3747,8 +3752,8 @@ module mkCore(CLK, specTagManager$specUpdate_incorrectSpeculation_kill_all; // ports of submodule v_f_to_TV_0 - reg [784 : 0] v_f_to_TV_0$D_IN; - wire [784 : 0] v_f_to_TV_0$D_OUT; + reg [861 : 0] v_f_to_TV_0$D_IN; + wire [861 : 0] v_f_to_TV_0$D_OUT; wire v_f_to_TV_0$CLR, v_f_to_TV_0$DEQ, v_f_to_TV_0$EMPTY_N, @@ -3756,7 +3761,7 @@ module mkCore(CLK, v_f_to_TV_0$FULL_N; // ports of submodule v_f_to_TV_1 - wire [784 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT; + wire [861 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT; wire v_f_to_TV_1$CLR, v_f_to_TV_1$DEQ, v_f_to_TV_1$EMPTY_N, @@ -3772,6 +3777,7 @@ module mkCore(CLK, CAN_FIRE_RL_commitStage_doSetLSQAtCommit, CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1, CAN_FIRE_RL_commitStage_notifyLSQCommit, + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv, CAN_FIRE_RL_commitStage_rl_send_tv_reset, CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu, CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu, @@ -4008,6 +4014,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doSetLSQAtCommit, WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1, WILL_FIRE_RL_commitStage_notifyLSQCommit, + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv, WILL_FIRE_RL_commitStage_rl_send_tv_reset, WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu, WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu, @@ -4244,9 +4251,10 @@ module mkCore(CLK, reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1, MUX_coreFix_memExe_lsq$respLd_1__VAL_2; reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3; - wire [784 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1, + wire [861 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1, MUX_v_f_to_TV_0$enq_1__VAL_2, - MUX_v_f_to_TV_0$enq_1__VAL_4; + MUX_v_f_to_TV_0$enq_1__VAL_4, + MUX_v_f_to_TV_0$enq_1__VAL_5; wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3, @@ -4324,7 +4332,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3, @@ -4339,6 +4347,7 @@ module mkCore(CLK, MUX_csrf_prv_reg$write_1__VAL_1; wire MUX_commitStage_rg_run_state$write_1__SEL_1, MUX_commitStage_rg_serial_num$write_1__SEL_1, + MUX_commitStage_rg_serial_num$write_1__SEL_2, MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3, MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1, @@ -4455,7 +4464,7 @@ module mkCore(CLK, MUX_csrf_stvec_base_hi_reg$write_1__SEL_1, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, - MUX_flush_reservation$write_1__SEL_2, + MUX_flush_reservation$write_1__SEL_1, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -4471,7 +4480,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, MUX_rg_core_run_state$write_1__SEL_4, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5, MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5, MUX_sbAggr$setReady_4_put_1__SEL_1, @@ -4479,7 +4488,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_started$write_1__SEL_1, MUX_v_f_to_TV_0$enq_1__SEL_2; // remaining internal signals @@ -4490,52 +4498,52 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875, - addr__h290066, - curData__h192915, - data_out__h736609, - data_warl_xformed__h721446, - rVal1__h609049, - rVal1__h633777, - trap_val__h709502, - x__h197125, - x__h722034; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + addr__h290067, + curData__h192916, + data_out__h737644, + data_warl_xformed__h722429, + rVal1__h609051, + rVal1__h633779, + trap_val__h710482, + x__h197126, + x__h723033; + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217, - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218, - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219, - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220, - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205, - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206, - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207, - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208, - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209, - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210, - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221, - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222, - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223, - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224, - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225, - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226, - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215, - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216, + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217, + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218, + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219, + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220, + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205, + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206, + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209, + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210, + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221, + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222, + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223, + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224, + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225, + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226, + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215, + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4547,50 +4555,50 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82, - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83, - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86, - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87, - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88, - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89, - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119, - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120, - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49, - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50, - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117, - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118, - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47, - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48, - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121, - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122, - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51, - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52, - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124, - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125, - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53, - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54, - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84, - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85, - _theResult___fst_sfd__h346067, - _theResult___fst_sfd__h354790, - _theResult___fst_sfd__h363372, - _theResult___fst_sfd__h372556, - _theResult___fst_sfd__h381192, - _theResult___fst_sfd__h391766, - _theResult___fst_sfd__h400487, - _theResult___fst_sfd__h409069, - _theResult___fst_sfd__h418253, - _theResult___fst_sfd__h426889, - _theResult___fst_sfd__h437461, - _theResult___fst_sfd__h446182, - _theResult___fst_sfd__h454764, - _theResult___fst_sfd__h463948, - _theResult___fst_sfd__h472584; + reg [22 : 0] CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82, + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83, + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86, + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87, + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88, + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89, + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119, + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120, + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49, + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50, + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117, + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118, + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47, + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48, + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121, + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122, + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51, + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52, + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123, + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124, + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53, + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54, + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84, + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85, + _theResult___fst_sfd__h346068, + _theResult___fst_sfd__h354791, + _theResult___fst_sfd__h363373, + _theResult___fst_sfd__h372557, + _theResult___fst_sfd__h381193, + _theResult___fst_sfd__h391767, + _theResult___fst_sfd__h400488, + _theResult___fst_sfd__h409070, + _theResult___fst_sfd__h418254, + _theResult___fst_sfd__h426890, + _theResult___fst_sfd__h437462, + _theResult___fst_sfd__h446183, + _theResult___fst_sfd__h454765, + _theResult___fst_sfd__h463949, + _theResult___fst_sfd__h472585; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294, @@ -4598,40 +4606,40 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407; - reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277, + reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255, + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211, - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212, - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213, - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214, - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183, - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184, - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185, - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186, - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187, - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188, - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160, - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161, - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189, - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190, - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191, - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192, - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143, - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144, + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211, + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212, + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213, + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214, + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183, + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184, + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185, + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186, + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187, + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188, + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160, + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161, + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189, + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190, + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191, + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192, + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143, + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573, @@ -4641,62 +4649,62 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803; - reg [7 : 0] CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67, - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68, - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75, - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76, - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80, - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81, - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104, - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105, - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34, - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35, - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102, - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103, - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32, - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33, - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110, - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111, - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40, - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41, - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115, - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116, - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45, - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46, - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69, - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70, + reg [7 : 0] CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67, + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68, + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75, + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76, + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80, + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81, + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104, + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105, + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34, + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35, + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102, + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103, + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32, + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33, + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110, + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111, + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40, + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41, + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115, + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116, + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45, + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46, + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69, + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h346066, - _theResult___fst_exp__h354789, - _theResult___fst_exp__h363371, - _theResult___fst_exp__h372555, - _theResult___fst_exp__h381191, - _theResult___fst_exp__h391765, - _theResult___fst_exp__h400486, - _theResult___fst_exp__h409068, - _theResult___fst_exp__h418252, - _theResult___fst_exp__h426888, - _theResult___fst_exp__h437460, - _theResult___fst_exp__h446181, - _theResult___fst_exp__h454763, - _theResult___fst_exp__h463947, - _theResult___fst_exp__h472583; + _theResult___fst_exp__h346067, + _theResult___fst_exp__h354790, + _theResult___fst_exp__h363372, + _theResult___fst_exp__h372556, + _theResult___fst_exp__h381192, + _theResult___fst_exp__h391766, + _theResult___fst_exp__h400487, + _theResult___fst_exp__h409069, + _theResult___fst_exp__h418253, + _theResult___fst_exp__h426889, + _theResult___fst_exp__h437461, + _theResult___fst_exp__h446182, + _theResult___fst_exp__h454764, + _theResult___fst_exp__h463948, + _theResult___fst_exp__h472584; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274, - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973; + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983; reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14128, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14261; reg [3 : 0] CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234, - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278, - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279, + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250, + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20, CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, @@ -4704,30 +4712,30 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262, - i__h708478, - i__h708638; + i__h709458, + i__h709618; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717, - x__h285845, - x__h291615; - reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265, + x__h285846, + x__h291616; + reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, + CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8, CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4; @@ -4746,58 +4754,58 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244, - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241, CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463, @@ -4869,23 +4877,24 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057; - wire [457 : 0] IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070; + wire [463 : 0] commitStage_f_rob_data_first__4755_BIT_167_485_ETC___d14927; + wire [457 : 0] rob_deqPort_0_deq_data__4339_BITS_161_TO_98_43_ETC___d15292; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; - wire [393 : 0] IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281; + wire [393 : 0] IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16052; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; wire [68 : 0] execFpuSimple___d11056; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627, - IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501; + IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448, @@ -4917,167 +4926,167 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180, - _theResult___fst__h603369, - _theResult___snd__h603370, - a___1__h603088, - a___1__h603374, - a__h602947, + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191, + _theResult___fst__h603370, + _theResult___snd__h603371, + a___1__h603089, + a___1__h603375, + a__h602948, amoExec___d880, - b___1__h603089, - b___1__h603419, - b__h602948, - base__h711423, - base__h711443, - commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438, - data___1__h475007, - data___1__h475815, - data__h475281, - fcsr_csr__read__h609375, - fflags_csr__read__h609350, - frm_csr__read__h609361, - mcause_csr__read__h611017, - mcounteren_csr__read__h610762, - medeleg_csr__read__h610369, - mideleg_csr__read__h610464, - mie_csr__read__h610588, - mip_csr__read__h611250, - mstatus_csr__read__h610221, - mtvec_csr__read__h610670, - n___1__h198528, - n__h194453, - n__read__h611354, - n__read__h611545, + b___1__h603090, + b___1__h603420, + b__h602949, + base__h712403, + base__h712423, + commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450, + data___1__h475008, + data___1__h475816, + data__h475282, + fcsr_csr__read__h609377, + fflags_csr__read__h609352, + frm_csr__read__h609363, + mcause_csr__read__h611019, + mcounteren_csr__read__h610764, + medeleg_csr__read__h610371, + mideleg_csr__read__h610466, + mie_csr__read__h610590, + mip_csr__read__h611252, + mstatus_csr__read__h610223, + mtvec_csr__read__h610672, + n___1__h198529, + n__h194454, + n__read__h611356, + n__read__h611547, n__read__h6759, - n__read__h725937, - next_pc__h721469, - pc__h711407, - q___1__h475880, - rVal1__h481760, - rVal2__h481761, - r___1__h475906, - res_data__h337868, - res_data__h337873, - res_data__h383570, - res_data__h383575, - res_data__h429265, - res_data__h429270, - resp_addr__h291970, - rg_tdata1__read__h612205, + n__read__h726937, + next_pc__h722452, + pc__h712387, + q___1__h475881, + rVal1__h481761, + rVal2__h481762, + r___1__h475907, + res_data__h337869, + res_data__h337874, + res_data__h383571, + res_data__h383576, + res_data__h429266, + res_data__h429271, + resp_addr__h291971, + rg_tdata1__read__h612207, robdeqPort_0_deq_data_BITS_95_TO_32__q245, - satp_csr__read__h610078, - scause_csr__read__h609875, - scounteren_csr__read__h609737, - shiftData__h181566, - sie_csr__read__h609641, - sip_csr__read__h610015, - sstatus_csr__read__h609571, - stvec_csr__read__h609684, - trap_val__h708464, + satp_csr__read__h610080, + scause_csr__read__h609877, + scounteren_csr__read__h609739, + shiftData__h181567, + sie_csr__read__h609643, + sip_csr__read__h610017, + sstatus_csr__read__h609573, + stvec_csr__read__h609686, + trap_val__h709444, upd__h3993, upd__h5310, upd__h6873, - upd__h726048, - v__h607933, - v__h632816, - x__h153730, - x__h157277, - x__h160091, - x__h161939, - x__h181475, + upd__h727048, + v__h607935, + v__h632818, + x__h153731, + x__h157278, + x__h160092, + x__h161940, x__h181476, - x__h18384, - x__h183901, - x__h20922, - x__h287290, - x__h289144, - x__h46291, - x__h481669, + x__h181477, + x__h18385, + x__h183902, + x__h20923, + x__h287291, + x__h289145, + x__h46292, x__h481670, x__h481671, - x__h48827, - x__h617230, - x__h617231, - x__h639739, - x__h639740, - x__h701397, - x__h713649, - x__h713841, - x__h725432, - x__h728883, - x__h732011, - x_addr__h314073, - x_quotient__h475195, - x_reg_ifc__read__h609480, - x_remainder__h475196, - y__h729714, - y__h732518, - y_avValue__h180563, - y_avValue__h181169, - y_avValue__h478805, - y_avValue__h479413, - y_avValue__h480015, - y_avValue__h608839, - y_avValue__h615055, - y_avValue__h633569, - y_avValue__h637574, - y_avValue_new_pc__h711199, - y_avValue_new_pc__h711385, - y_avValue_snd_snd_snd_snd_snd_fst__h729737, - y_avValue_snd_snd_snd_snd_snd_fst__h732579, - y_avValue_snd_snd_snd_snd_snd_fst__h732615, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993; + x__h481672, + x__h48828, + x__h617232, + x__h617233, + x__h639741, + x__h639742, + x__h702377, + x__h714645, + x__h714837, + x__h726431, + x__h729900, + x__h733045, + x_addr__h314074, + x_quotient__h475196, + x_reg_ifc__read__h609482, + x_remainder__h475197, + y__h730732, + y__h733553, + y_avValue__h180564, + y_avValue__h181170, + y_avValue__h478806, + y_avValue__h479414, + y_avValue__h480016, + y_avValue__h608841, + y_avValue__h615057, + y_avValue__h633571, + y_avValue__h637576, + y_avValue_new_pc__h712179, + y_avValue_new_pc__h712365, + y_avValue_snd_snd_snd_snd_snd_fst__h730755, + y_avValue_snd_snd_snd_snd_snd_fst__h733614, + y_avValue_snd_snd_snd_snd_snd_fst__h733650, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882, - IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909, - r1__read__h613048, - r1__read__h613452, - r1__read__h613962, - r1__read__h613967, - r1__read__h613986, - r1__read__h614219, - r1__read__h614385, - r1__read__h614478, - r1__read__h614483, - r1__read__h614502; - wire [61 : 0] r1__read__h613050, + IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920, + r1__read__h613050, r1__read__h613454, + r1__read__h613964, r1__read__h613969, r1__read__h613988, r1__read__h614221, - r1__read__h614361, r1__read__h614387, + r1__read__h614480, r1__read__h614485, r1__read__h614504; - wire [60 : 0] r1__read__h614223, + wire [61 : 0] r1__read__h613052, + r1__read__h613456, + r1__read__h613971, + r1__read__h613990, + r1__read__h614223, r1__read__h614363, r1__read__h614389, + r1__read__h614487, r1__read__h614506; - wire [59 : 0] r1__read__h613052, - r1__read__h613456, - r1__read__h613980, - r1__read__h613990, - r1__read__h614225, + wire [60 : 0] r1__read__h614225, + r1__read__h614365, r1__read__h614391, - r1__read__h614496, r1__read__h614508; - wire [58 : 0] r1__read__h613054, + wire [59 : 0] r1__read__h613054, r1__read__h613458, + r1__read__h613982, r1__read__h613992, r1__read__h614227, r1__read__h614393, + r1__read__h614498, r1__read__h614510; - wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550, - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012, - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, - r1__read__h613056, + wire [58 : 0] r1__read__h613056, r1__read__h613460, r1__read__h613994, r1__read__h614229, - r1__read__h614365, r1__read__h614395, - r1__read__h614512, - y__h254802; + r1__read__h614512; + wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550, + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012, + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, + r1__read__h613058, + r1__read__h613462, + r1__read__h613996, + r1__read__h614231, + r1__read__h614367, + r1__read__h614397, + r1__read__h614514, + y__h254803; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98, @@ -5105,187 +5114,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342, - _theResult____h346084, - _theResult____h363723, - _theResult____h391783, - _theResult____h409420, - _theResult____h437478, - _theResult____h455115, - _theResult____h502868, - _theResult____h541721, - _theResult____h581025, - _theResult___snd__h354206, - _theResult___snd__h354217, - _theResult___snd__h354219, - _theResult___snd__h354229, - _theResult___snd__h354235, - _theResult___snd__h354258, - _theResult___snd__h362802, - _theResult___snd__h362804, - _theResult___snd__h362811, - _theResult___snd__h362817, - _theResult___snd__h362840, - _theResult___snd__h371972, - _theResult___snd__h371983, - _theResult___snd__h371985, - _theResult___snd__h371995, - _theResult___snd__h372001, - _theResult___snd__h372024, - _theResult___snd__h380592, - _theResult___snd__h380606, - _theResult___snd__h380612, - _theResult___snd__h380630, - _theResult___snd__h399903, - _theResult___snd__h399914, - _theResult___snd__h399916, - _theResult___snd__h399926, - _theResult___snd__h399932, - _theResult___snd__h399955, - _theResult___snd__h408499, - _theResult___snd__h408501, - _theResult___snd__h408508, - _theResult___snd__h408514, - _theResult___snd__h408537, - _theResult___snd__h417669, - _theResult___snd__h417680, - _theResult___snd__h417682, - _theResult___snd__h417692, - _theResult___snd__h417698, - _theResult___snd__h417721, - _theResult___snd__h426289, - _theResult___snd__h426303, - _theResult___snd__h426309, - _theResult___snd__h426327, - _theResult___snd__h445598, - _theResult___snd__h445609, - _theResult___snd__h445611, - _theResult___snd__h445621, - _theResult___snd__h445627, - _theResult___snd__h445650, - _theResult___snd__h454194, - _theResult___snd__h454196, - _theResult___snd__h454203, - _theResult___snd__h454209, - _theResult___snd__h454232, - _theResult___snd__h463364, - _theResult___snd__h463375, - _theResult___snd__h463377, - _theResult___snd__h463387, - _theResult___snd__h463393, - _theResult___snd__h463416, - _theResult___snd__h471984, - _theResult___snd__h471998, - _theResult___snd__h472004, - _theResult___snd__h472022, - _theResult___snd__h501478, - _theResult___snd__h501480, - _theResult___snd__h501487, - _theResult___snd__h501493, - _theResult___snd__h501516, - _theResult___snd__h511115, - _theResult___snd__h511126, - _theResult___snd__h511128, - _theResult___snd__h511138, - _theResult___snd__h511144, - _theResult___snd__h511167, - _theResult___snd__h519883, - _theResult___snd__h519897, - _theResult___snd__h519903, - _theResult___snd__h519921, - _theResult___snd__h540331, - _theResult___snd__h540333, - _theResult___snd__h540340, - _theResult___snd__h540346, - _theResult___snd__h540369, - _theResult___snd__h549968, - _theResult___snd__h549979, - _theResult___snd__h549981, - _theResult___snd__h549991, - _theResult___snd__h549997, - _theResult___snd__h550020, - _theResult___snd__h558736, - _theResult___snd__h558750, - _theResult___snd__h558756, - _theResult___snd__h558774, - _theResult___snd__h579635, - _theResult___snd__h579637, - _theResult___snd__h579644, - _theResult___snd__h579650, - _theResult___snd__h579673, - _theResult___snd__h589272, - _theResult___snd__h589283, - _theResult___snd__h589285, - _theResult___snd__h589295, - _theResult___snd__h589301, - _theResult___snd__h589324, - _theResult___snd__h598040, - _theResult___snd__h598054, - _theResult___snd__h598060, - _theResult___snd__h598078, - r1__read__h614231, - r1__read__h614367, - r1__read__h614397, - r1__read__h614514, - result__h364336, - result__h410033, - result__h455728, - result__h503481, - result__h542334, - result__h581638, - sfd__h338479, - sfd__h384181, - sfd__h429876, - sfd__h482501, - sfd__h521495, - sfd__h560799, - sfdin__h354189, - sfdin__h371955, - sfdin__h399886, - sfdin__h417652, - sfdin__h445581, - sfdin__h463347, - sfdin__h511098, - sfdin__h549951, - sfdin__h589255, - x__h364433, - x__h410130, - x__h455825, - x__h503576, - x__h542429, - x__h581733; - wire [55 : 0] r1__read__h613058, - r1__read__h613462, - r1__read__h613996, + _theResult____h346085, + _theResult____h363724, + _theResult____h391784, + _theResult____h409421, + _theResult____h437479, + _theResult____h455116, + _theResult____h502869, + _theResult____h541722, + _theResult____h581026, + _theResult___snd__h354207, + _theResult___snd__h354218, + _theResult___snd__h354220, + _theResult___snd__h354230, + _theResult___snd__h354236, + _theResult___snd__h354259, + _theResult___snd__h362803, + _theResult___snd__h362805, + _theResult___snd__h362812, + _theResult___snd__h362818, + _theResult___snd__h362841, + _theResult___snd__h371973, + _theResult___snd__h371984, + _theResult___snd__h371986, + _theResult___snd__h371996, + _theResult___snd__h372002, + _theResult___snd__h372025, + _theResult___snd__h380593, + _theResult___snd__h380607, + _theResult___snd__h380613, + _theResult___snd__h380631, + _theResult___snd__h399904, + _theResult___snd__h399915, + _theResult___snd__h399917, + _theResult___snd__h399927, + _theResult___snd__h399933, + _theResult___snd__h399956, + _theResult___snd__h408500, + _theResult___snd__h408502, + _theResult___snd__h408509, + _theResult___snd__h408515, + _theResult___snd__h408538, + _theResult___snd__h417670, + _theResult___snd__h417681, + _theResult___snd__h417683, + _theResult___snd__h417693, + _theResult___snd__h417699, + _theResult___snd__h417722, + _theResult___snd__h426290, + _theResult___snd__h426304, + _theResult___snd__h426310, + _theResult___snd__h426328, + _theResult___snd__h445599, + _theResult___snd__h445610, + _theResult___snd__h445612, + _theResult___snd__h445622, + _theResult___snd__h445628, + _theResult___snd__h445651, + _theResult___snd__h454195, + _theResult___snd__h454197, + _theResult___snd__h454204, + _theResult___snd__h454210, + _theResult___snd__h454233, + _theResult___snd__h463365, + _theResult___snd__h463376, + _theResult___snd__h463378, + _theResult___snd__h463388, + _theResult___snd__h463394, + _theResult___snd__h463417, + _theResult___snd__h471985, + _theResult___snd__h471999, + _theResult___snd__h472005, + _theResult___snd__h472023, + _theResult___snd__h501479, + _theResult___snd__h501481, + _theResult___snd__h501488, + _theResult___snd__h501494, + _theResult___snd__h501517, + _theResult___snd__h511116, + _theResult___snd__h511127, + _theResult___snd__h511129, + _theResult___snd__h511139, + _theResult___snd__h511145, + _theResult___snd__h511168, + _theResult___snd__h519884, + _theResult___snd__h519898, + _theResult___snd__h519904, + _theResult___snd__h519922, + _theResult___snd__h540332, + _theResult___snd__h540334, + _theResult___snd__h540341, + _theResult___snd__h540347, + _theResult___snd__h540370, + _theResult___snd__h549969, + _theResult___snd__h549980, + _theResult___snd__h549982, + _theResult___snd__h549992, + _theResult___snd__h549998, + _theResult___snd__h550021, + _theResult___snd__h558737, + _theResult___snd__h558751, + _theResult___snd__h558757, + _theResult___snd__h558775, + _theResult___snd__h579636, + _theResult___snd__h579638, + _theResult___snd__h579645, + _theResult___snd__h579651, + _theResult___snd__h579674, + _theResult___snd__h589273, + _theResult___snd__h589284, + _theResult___snd__h589286, + _theResult___snd__h589296, + _theResult___snd__h589302, + _theResult___snd__h589325, + _theResult___snd__h598041, + _theResult___snd__h598055, + _theResult___snd__h598061, + _theResult___snd__h598079, r1__read__h614233, + r1__read__h614369, r1__read__h614399, - r1__read__h614516; - wire [54 : 0] r1__read__h613060, + r1__read__h614516, + result__h364337, + result__h410034, + result__h455729, + result__h503482, + result__h542335, + result__h581639, + sfd__h338480, + sfd__h384182, + sfd__h429877, + sfd__h482502, + sfd__h521496, + sfd__h560800, + sfdin__h354190, + sfdin__h371956, + sfdin__h399887, + sfdin__h417653, + sfdin__h445582, + sfdin__h463348, + sfdin__h511099, + sfdin__h549952, + sfdin__h589256, + x__h364434, + x__h410131, + x__h455826, + x__h503577, + x__h542430, + x__h581734; + wire [55 : 0] r1__read__h613060, r1__read__h613464, r1__read__h613998, r1__read__h614235, r1__read__h614401, r1__read__h614518; - wire [53 : 0] r1__read__h614344, - r1__read__h614369, + wire [54 : 0] r1__read__h613062, + r1__read__h613466, + r1__read__h614000, + r1__read__h614237, r1__read__h614403, - r1__read__h614520, - sfd__h501545, - sfd__h511196, - sfd__h519956, - sfd__h540398, - sfd__h550049, - sfd__h558809, - sfd__h579702, - sfd__h589353, - sfd__h598113, - value__h346706, - value__h392403, - value__h438098; - wire [52 : 0] r1__read__h614237, - r1__read__h614346, + r1__read__h614520; + wire [53 : 0] r1__read__h614346, r1__read__h614371, r1__read__h614405, - r1__read__h614522; + r1__read__h614522, + sfd__h501546, + sfd__h511197, + sfd__h519957, + sfd__h540399, + sfd__h550050, + sfd__h558810, + sfd__h579703, + sfd__h589354, + sfd__h598114, + value__h346707, + value__h392404, + value__h438099; + wire [52 : 0] r1__read__h614239, + r1__read__h614348, + r1__read__h614373, + r1__read__h614407, + r1__read__h614524; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140, @@ -5307,111 +5316,111 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881, - _theResult___fst_sfd__h486455, - _theResult___fst_sfd__h502283, - _theResult___fst_sfd__h502286, - _theResult___fst_sfd__h511934, - _theResult___fst_sfd__h511937, - _theResult___fst_sfd__h520718, - _theResult___fst_sfd__h520721, - _theResult___fst_sfd__h520730, - _theResult___fst_sfd__h520736, - _theResult___fst_sfd__h525308, - _theResult___fst_sfd__h541136, - _theResult___fst_sfd__h541139, - _theResult___fst_sfd__h550787, - _theResult___fst_sfd__h550790, - _theResult___fst_sfd__h559571, - _theResult___fst_sfd__h559574, - _theResult___fst_sfd__h559583, - _theResult___fst_sfd__h559589, - _theResult___fst_sfd__h564612, - _theResult___fst_sfd__h580440, - _theResult___fst_sfd__h580443, - _theResult___fst_sfd__h590091, - _theResult___fst_sfd__h590094, - _theResult___fst_sfd__h598875, - _theResult___fst_sfd__h598878, - _theResult___fst_sfd__h598887, - _theResult___fst_sfd__h598893, - _theResult___sfd__h502183, - _theResult___sfd__h511834, - _theResult___sfd__h520618, - _theResult___sfd__h541036, - _theResult___sfd__h550687, - _theResult___sfd__h559471, - _theResult___sfd__h580340, - _theResult___sfd__h589991, - _theResult___sfd__h598775, - _theResult___snd_fst_sfd__h482455, - _theResult___snd_fst_sfd__h502289, - _theResult___snd_fst_sfd__h520724, - _theResult___snd_fst_sfd__h521449, - _theResult___snd_fst_sfd__h541142, - _theResult___snd_fst_sfd__h559577, - _theResult___snd_fst_sfd__h560753, - _theResult___snd_fst_sfd__h580446, - _theResult___snd_fst_sfd__h598881, - out___1_sfd__h482203, - out___1_sfd__h521197, - out___1_sfd__h560501, - out_sfd__h502186, - out_sfd__h511837, - out_sfd__h520621, - out_sfd__h541039, - out_sfd__h550690, - out_sfd__h559474, - out_sfd__h580343, - out_sfd__h589994, - out_sfd__h598778; - wire [50 : 0] r1__read__h613062, r1__read__h614239; - wire [49 : 0] r1__read__h614348; - wire [48 : 0] r1__read_BITS_62_TO_14___h728903, - r1__read__h613064, - r1__read__h614350; - wire [46 : 0] r1__read__h613066, r1__read__h614243; - wire [45 : 0] r1__read__h613068, r1__read__h614245; - wire [44 : 0] r1__read__h613070, r1__read__h614247; - wire [43 : 0] r1__read__h613072, r1__read__h614249; - wire [42 : 0] r1__read__h614251; - wire [41 : 0] r1__read__h614253; - wire [40 : 0] r1__read__h614255; + _theResult___fst_sfd__h486456, + _theResult___fst_sfd__h502284, + _theResult___fst_sfd__h502287, + _theResult___fst_sfd__h511935, + _theResult___fst_sfd__h511938, + _theResult___fst_sfd__h520719, + _theResult___fst_sfd__h520722, + _theResult___fst_sfd__h520731, + _theResult___fst_sfd__h520737, + _theResult___fst_sfd__h525309, + _theResult___fst_sfd__h541137, + _theResult___fst_sfd__h541140, + _theResult___fst_sfd__h550788, + _theResult___fst_sfd__h550791, + _theResult___fst_sfd__h559572, + _theResult___fst_sfd__h559575, + _theResult___fst_sfd__h559584, + _theResult___fst_sfd__h559590, + _theResult___fst_sfd__h564613, + _theResult___fst_sfd__h580441, + _theResult___fst_sfd__h580444, + _theResult___fst_sfd__h590092, + _theResult___fst_sfd__h590095, + _theResult___fst_sfd__h598876, + _theResult___fst_sfd__h598879, + _theResult___fst_sfd__h598888, + _theResult___fst_sfd__h598894, + _theResult___sfd__h502184, + _theResult___sfd__h511835, + _theResult___sfd__h520619, + _theResult___sfd__h541037, + _theResult___sfd__h550688, + _theResult___sfd__h559472, + _theResult___sfd__h580341, + _theResult___sfd__h589992, + _theResult___sfd__h598776, + _theResult___snd_fst_sfd__h482456, + _theResult___snd_fst_sfd__h502290, + _theResult___snd_fst_sfd__h520725, + _theResult___snd_fst_sfd__h521450, + _theResult___snd_fst_sfd__h541143, + _theResult___snd_fst_sfd__h559578, + _theResult___snd_fst_sfd__h560754, + _theResult___snd_fst_sfd__h580447, + _theResult___snd_fst_sfd__h598882, + out___1_sfd__h482204, + out___1_sfd__h521198, + out___1_sfd__h560502, + out_sfd__h502187, + out_sfd__h511838, + out_sfd__h520622, + out_sfd__h541040, + out_sfd__h550691, + out_sfd__h559475, + out_sfd__h580344, + out_sfd__h589995, + out_sfd__h598779; + wire [50 : 0] r1__read__h613064, r1__read__h614241; + wire [49 : 0] r1__read__h614350; + wire [48 : 0] r1__read_BITS_62_TO_14___h729920, + r1__read__h613066, + r1__read__h614352; + wire [46 : 0] r1__read__h613068, r1__read__h614245; + wire [45 : 0] r1__read__h613070, r1__read__h614247; + wire [44 : 0] r1__read__h613072, r1__read__h614249; + wire [43 : 0] r1__read__h613074, r1__read__h614251; + wire [42 : 0] r1__read__h614253; + wire [41 : 0] r1__read__h614255; + wire [40 : 0] r1__read__h614257; wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14134, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data75281_BITS_31_TO_0__q14, - imm__h655327, - r1__read__h613074, - r1__read__h614257, - x__h193678, - x__h337883, - x__h383585, - x__h429280, - x__h76236, - x_data__h66085, - x_data_imm__h676655, - x_data_imm__h692709; - wire [29 : 0] r1__read__h613076, r1__read__h614259; - wire [27 : 0] r1__read__h614261; + data75282_BITS_31_TO_0__q13, + imm__h655329, + r1__read__h613076, + r1__read__h614259, + x__h193679, + x__h337884, + x__h383586, + x__h429281, + x__h76237, + x_data__h66086, + x_data_imm__h676657, + x_data_imm__h692711; + wire [29 : 0] r1__read__h613078, r1__read__h614261; + wire [27 : 0] r1__read__h614263; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14166, - sfd__h354287, - sfd__h362869, - sfd__h372053, - sfd__h380665, - sfd__h399984, - sfd__h408566, - sfd__h417750, - sfd__h426362, - sfd__h445679, - sfd__h454261, - sfd__h463445, - sfd__h472057, - value__h487084, - value__h525937, - value__h565241; + sfd__h354288, + sfd__h362870, + sfd__h372054, + sfd__h380666, + sfd__h399985, + sfd__h408567, + sfd__h417751, + sfd__h426363, + sfd__h445680, + sfd__h454262, + sfd__h463446, + sfd__h472058, + value__h487085, + value__h525938, + value__h565242; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349, @@ -5436,77 +5445,77 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808, - _theResult___fst_sfd__h354793, - _theResult___fst_sfd__h363375, - _theResult___fst_sfd__h372559, - _theResult___fst_sfd__h381195, - _theResult___fst_sfd__h381204, - _theResult___fst_sfd__h381210, - _theResult___fst_sfd__h400490, - _theResult___fst_sfd__h409072, - _theResult___fst_sfd__h418256, - _theResult___fst_sfd__h426892, - _theResult___fst_sfd__h426901, - _theResult___fst_sfd__h426907, - _theResult___fst_sfd__h446185, - _theResult___fst_sfd__h454767, - _theResult___fst_sfd__h463951, - _theResult___fst_sfd__h472587, - _theResult___fst_sfd__h472596, - _theResult___fst_sfd__h472602, - _theResult___sfd__h354712, - _theResult___sfd__h363294, - _theResult___sfd__h372478, - _theResult___sfd__h381114, - _theResult___sfd__h381216, - _theResult___sfd__h400409, - _theResult___sfd__h408991, - _theResult___sfd__h418175, - _theResult___sfd__h426811, - _theResult___sfd__h426913, - _theResult___sfd__h446104, - _theResult___sfd__h454686, - _theResult___sfd__h463870, - _theResult___sfd__h472506, - _theResult___sfd__h472608, - _theResult___snd_fst_sfd__h338429, - _theResult___snd_fst_sfd__h363378, - _theResult___snd_fst_sfd__h381198, - _theResult___snd_fst_sfd__h384131, - _theResult___snd_fst_sfd__h409075, - _theResult___snd_fst_sfd__h426895, - _theResult___snd_fst_sfd__h429826, - _theResult___snd_fst_sfd__h454770, - _theResult___snd_fst_sfd__h472590, - f1_sfd__h482140, - f2_sfd__h521134, - f3_sfd__h560438, - out_f_sfd__h381493, - out_f_sfd__h427190, - out_f_sfd__h472885, - out_sfd__h354715, - out_sfd__h363297, - out_sfd__h372481, - out_sfd__h381117, - out_sfd__h400412, - out_sfd__h408994, - out_sfd__h418178, - out_sfd__h426814, - out_sfd__h446107, - out_sfd__h454689, - out_sfd__h463873, - out_sfd__h472509; - wire [19 : 0] r1__read__h614196; + _theResult___fst_sfd__h354794, + _theResult___fst_sfd__h363376, + _theResult___fst_sfd__h372560, + _theResult___fst_sfd__h381196, + _theResult___fst_sfd__h381205, + _theResult___fst_sfd__h381211, + _theResult___fst_sfd__h400491, + _theResult___fst_sfd__h409073, + _theResult___fst_sfd__h418257, + _theResult___fst_sfd__h426893, + _theResult___fst_sfd__h426902, + _theResult___fst_sfd__h426908, + _theResult___fst_sfd__h446186, + _theResult___fst_sfd__h454768, + _theResult___fst_sfd__h463952, + _theResult___fst_sfd__h472588, + _theResult___fst_sfd__h472597, + _theResult___fst_sfd__h472603, + _theResult___sfd__h354713, + _theResult___sfd__h363295, + _theResult___sfd__h372479, + _theResult___sfd__h381115, + _theResult___sfd__h381217, + _theResult___sfd__h400410, + _theResult___sfd__h408992, + _theResult___sfd__h418176, + _theResult___sfd__h426812, + _theResult___sfd__h426914, + _theResult___sfd__h446105, + _theResult___sfd__h454687, + _theResult___sfd__h463871, + _theResult___sfd__h472507, + _theResult___sfd__h472609, + _theResult___snd_fst_sfd__h338430, + _theResult___snd_fst_sfd__h363379, + _theResult___snd_fst_sfd__h381199, + _theResult___snd_fst_sfd__h384132, + _theResult___snd_fst_sfd__h409076, + _theResult___snd_fst_sfd__h426896, + _theResult___snd_fst_sfd__h429827, + _theResult___snd_fst_sfd__h454771, + _theResult___snd_fst_sfd__h472591, + f1_sfd__h482141, + f2_sfd__h521135, + f3_sfd__h560439, + out_f_sfd__h381494, + out_f_sfd__h427191, + out_f_sfd__h472886, + out_sfd__h354716, + out_sfd__h363298, + out_sfd__h372482, + out_sfd__h381118, + out_sfd__h400413, + out_sfd__h408995, + out_sfd__h418179, + out_sfd__h426815, + out_sfd__h446108, + out_sfd__h454690, + out_sfd__h463874, + out_sfd__h472510; + wire [19 : 0] r1__read__h614198; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824, - _theResult____h651116, - enabled_ints___1__h651641, - enabled_ints__h651687, - pend_ints__h651114, - y__h651653; - wire [13 : 0] r1__read_BITS_13_TO_0___h651663; - wire [12 : 0] IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271, + _theResult____h651118, + enabled_ints___1__h651643, + enabled_ints__h651689, + pend_ints__h651116, + y__h651655; + wire [13 : 0] r1__read_BITS_13_TO_0___h651665; + wire [12 : 0] IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15282, fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494; + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661, @@ -5536,25 +5545,25 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338, - csr_addr__h655325, - renaming_spec_bits__h685237, - result__h646693, - result__h646744, - spec_bits__h688396, - w__h646688, - x__h364466, - x__h410163, - x__h455858, - x__h503609, - x__h542462, - x__h581766, - x__h646692, - x__h646743, - y__h646722, - y__h688409, - y_avValue_fst__h681569, - y_avValue_fst__h681598, - y_avValue_fst__h681632; + csr_addr__h655327, + renaming_spec_bits__h685239, + result__h646695, + result__h646746, + spec_bits__h688398, + w__h646690, + x__h364467, + x__h410164, + x__h455859, + x__h503610, + x__h542463, + x__h581767, + x__h646694, + x__h646745, + y__h646724, + y__h688411, + y_avValue_fst__h681571, + y_avValue_fst__h681600, + y_avValue_fst__h681634; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056, @@ -5576,102 +5585,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h502182, - _theResult___exp__h511833, - _theResult___exp__h520617, - _theResult___exp__h541035, - _theResult___exp__h550686, - _theResult___exp__h559470, - _theResult___exp__h580339, - _theResult___exp__h589990, - _theResult___exp__h598774, - _theResult___fst_exp__h486454, - _theResult___fst_exp__h501518, - _theResult___fst_exp__h501524, - _theResult___fst_exp__h501527, - _theResult___fst_exp__h502282, - _theResult___fst_exp__h502285, - _theResult___fst_exp__h511104, - _theResult___fst_exp__h511169, - _theResult___fst_exp__h511175, - _theResult___fst_exp__h511178, - _theResult___fst_exp__h511933, - _theResult___fst_exp__h511936, - _theResult___fst_exp__h519889, - _theResult___fst_exp__h519928, - _theResult___fst_exp__h519934, - _theResult___fst_exp__h519937, - _theResult___fst_exp__h520717, - _theResult___fst_exp__h520720, - _theResult___fst_exp__h520729, - _theResult___fst_exp__h520732, - _theResult___fst_exp__h525307, - _theResult___fst_exp__h540371, - _theResult___fst_exp__h540377, - _theResult___fst_exp__h540380, - _theResult___fst_exp__h541135, - _theResult___fst_exp__h541138, - _theResult___fst_exp__h549957, - _theResult___fst_exp__h550022, - _theResult___fst_exp__h550028, - _theResult___fst_exp__h550031, - _theResult___fst_exp__h550786, - _theResult___fst_exp__h550789, - _theResult___fst_exp__h558742, - _theResult___fst_exp__h558781, - _theResult___fst_exp__h558787, - _theResult___fst_exp__h558790, - _theResult___fst_exp__h559570, - _theResult___fst_exp__h559573, - _theResult___fst_exp__h559582, - _theResult___fst_exp__h559585, - _theResult___fst_exp__h564611, - _theResult___fst_exp__h579675, - _theResult___fst_exp__h579681, - _theResult___fst_exp__h579684, - _theResult___fst_exp__h580439, - _theResult___fst_exp__h580442, - _theResult___fst_exp__h589261, - _theResult___fst_exp__h589326, - _theResult___fst_exp__h589332, - _theResult___fst_exp__h589335, - _theResult___fst_exp__h590090, - _theResult___fst_exp__h590093, - _theResult___fst_exp__h598046, - _theResult___fst_exp__h598085, - _theResult___fst_exp__h598091, - _theResult___fst_exp__h598094, - _theResult___fst_exp__h598874, - _theResult___fst_exp__h598877, - _theResult___fst_exp__h598886, - _theResult___fst_exp__h598889, - _theResult___snd_fst_exp__h502288, - _theResult___snd_fst_exp__h520723, - _theResult___snd_fst_exp__h541141, - _theResult___snd_fst_exp__h559576, - _theResult___snd_fst_exp__h580445, - _theResult___snd_fst_exp__h598880, + _theResult___exp__h502183, + _theResult___exp__h511834, + _theResult___exp__h520618, + _theResult___exp__h541036, + _theResult___exp__h550687, + _theResult___exp__h559471, + _theResult___exp__h580340, + _theResult___exp__h589991, + _theResult___exp__h598775, + _theResult___fst_exp__h486455, + _theResult___fst_exp__h501519, + _theResult___fst_exp__h501525, + _theResult___fst_exp__h501528, + _theResult___fst_exp__h502283, + _theResult___fst_exp__h502286, + _theResult___fst_exp__h511105, + _theResult___fst_exp__h511170, + _theResult___fst_exp__h511176, + _theResult___fst_exp__h511179, + _theResult___fst_exp__h511934, + _theResult___fst_exp__h511937, + _theResult___fst_exp__h519890, + _theResult___fst_exp__h519929, + _theResult___fst_exp__h519935, + _theResult___fst_exp__h519938, + _theResult___fst_exp__h520718, + _theResult___fst_exp__h520721, + _theResult___fst_exp__h520730, + _theResult___fst_exp__h520733, + _theResult___fst_exp__h525308, + _theResult___fst_exp__h540372, + _theResult___fst_exp__h540378, + _theResult___fst_exp__h540381, + _theResult___fst_exp__h541136, + _theResult___fst_exp__h541139, + _theResult___fst_exp__h549958, + _theResult___fst_exp__h550023, + _theResult___fst_exp__h550029, + _theResult___fst_exp__h550032, + _theResult___fst_exp__h550787, + _theResult___fst_exp__h550790, + _theResult___fst_exp__h558743, + _theResult___fst_exp__h558782, + _theResult___fst_exp__h558788, + _theResult___fst_exp__h558791, + _theResult___fst_exp__h559571, + _theResult___fst_exp__h559574, + _theResult___fst_exp__h559583, + _theResult___fst_exp__h559586, + _theResult___fst_exp__h564612, + _theResult___fst_exp__h579676, + _theResult___fst_exp__h579682, + _theResult___fst_exp__h579685, + _theResult___fst_exp__h580440, + _theResult___fst_exp__h580443, + _theResult___fst_exp__h589262, + _theResult___fst_exp__h589327, + _theResult___fst_exp__h589333, + _theResult___fst_exp__h589336, + _theResult___fst_exp__h590091, + _theResult___fst_exp__h590094, + _theResult___fst_exp__h598047, + _theResult___fst_exp__h598086, + _theResult___fst_exp__h598092, + _theResult___fst_exp__h598095, + _theResult___fst_exp__h598875, + _theResult___fst_exp__h598878, + _theResult___fst_exp__h598887, + _theResult___fst_exp__h598890, + _theResult___snd_fst_exp__h502289, + _theResult___snd_fst_exp__h520724, + _theResult___snd_fst_exp__h541142, + _theResult___snd_fst_exp__h559577, + _theResult___snd_fst_exp__h580446, + _theResult___snd_fst_exp__h598881, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106, - din_inc___2_exp__h520777, - din_inc___2_exp__h520812, - din_inc___2_exp__h520838, - din_inc___2_exp__h559630, - din_inc___2_exp__h559665, - din_inc___2_exp__h559691, - din_inc___2_exp__h598934, - din_inc___2_exp__h598969, - din_inc___2_exp__h598995, - out_exp__h502185, - out_exp__h511836, - out_exp__h520620, - out_exp__h541038, - out_exp__h550689, - out_exp__h559473, - out_exp__h580342, - out_exp__h589993, - out_exp__h598777; + din_inc___2_exp__h520778, + din_inc___2_exp__h520813, + din_inc___2_exp__h520839, + din_inc___2_exp__h559631, + din_inc___2_exp__h559666, + din_inc___2_exp__h559692, + din_inc___2_exp__h598935, + din_inc___2_exp__h598970, + din_inc___2_exp__h598996, + out_exp__h502186, + out_exp__h511837, + out_exp__h520621, + out_exp__h541039, + out_exp__h550690, + out_exp__h559474, + out_exp__h580343, + out_exp__h589994, + out_exp__h598778; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656; @@ -5702,124 +5711,124 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112, - _theResult___exp__h354711, - _theResult___exp__h363293, - _theResult___exp__h372477, - _theResult___exp__h381113, - _theResult___exp__h381215, - _theResult___exp__h400408, - _theResult___exp__h408990, - _theResult___exp__h418174, - _theResult___exp__h426810, - _theResult___exp__h426912, - _theResult___exp__h446103, - _theResult___exp__h454685, - _theResult___exp__h463869, - _theResult___exp__h472505, - _theResult___exp__h472607, - _theResult___fst_exp__h354195, - _theResult___fst_exp__h354260, - _theResult___fst_exp__h354266, - _theResult___fst_exp__h354269, - _theResult___fst_exp__h354792, - _theResult___fst_exp__h362842, - _theResult___fst_exp__h362848, - _theResult___fst_exp__h362851, - _theResult___fst_exp__h363374, - _theResult___fst_exp__h371961, - _theResult___fst_exp__h372026, - _theResult___fst_exp__h372032, - _theResult___fst_exp__h372035, - _theResult___fst_exp__h372558, - _theResult___fst_exp__h380598, - _theResult___fst_exp__h380637, - _theResult___fst_exp__h380643, - _theResult___fst_exp__h380646, - _theResult___fst_exp__h381194, - _theResult___fst_exp__h381203, - _theResult___fst_exp__h381206, - _theResult___fst_exp__h399892, - _theResult___fst_exp__h399957, - _theResult___fst_exp__h399963, - _theResult___fst_exp__h399966, - _theResult___fst_exp__h400489, - _theResult___fst_exp__h408539, - _theResult___fst_exp__h408545, - _theResult___fst_exp__h408548, - _theResult___fst_exp__h409071, - _theResult___fst_exp__h417658, - _theResult___fst_exp__h417723, - _theResult___fst_exp__h417729, - _theResult___fst_exp__h417732, - _theResult___fst_exp__h418255, - _theResult___fst_exp__h426295, - _theResult___fst_exp__h426334, - _theResult___fst_exp__h426340, - _theResult___fst_exp__h426343, - _theResult___fst_exp__h426891, - _theResult___fst_exp__h426900, - _theResult___fst_exp__h426903, - _theResult___fst_exp__h445587, - _theResult___fst_exp__h445652, - _theResult___fst_exp__h445658, - _theResult___fst_exp__h445661, - _theResult___fst_exp__h446184, - _theResult___fst_exp__h454234, - _theResult___fst_exp__h454240, - _theResult___fst_exp__h454243, - _theResult___fst_exp__h454766, - _theResult___fst_exp__h463353, - _theResult___fst_exp__h463418, - _theResult___fst_exp__h463424, - _theResult___fst_exp__h463427, - _theResult___fst_exp__h463950, - _theResult___fst_exp__h471990, - _theResult___fst_exp__h472029, - _theResult___fst_exp__h472035, - _theResult___fst_exp__h472038, - _theResult___fst_exp__h472586, - _theResult___fst_exp__h472595, - _theResult___fst_exp__h472598, - _theResult___snd_fst_exp__h363377, - _theResult___snd_fst_exp__h381197, - _theResult___snd_fst_exp__h409074, - _theResult___snd_fst_exp__h426894, - _theResult___snd_fst_exp__h454769, - _theResult___snd_fst_exp__h472589, - din_inc___2_exp__h381228, - din_inc___2_exp__h381252, - din_inc___2_exp__h381282, - din_inc___2_exp__h381306, - din_inc___2_exp__h426925, - din_inc___2_exp__h426949, - din_inc___2_exp__h426979, - din_inc___2_exp__h427003, - din_inc___2_exp__h472620, - din_inc___2_exp__h472644, - din_inc___2_exp__h472674, - din_inc___2_exp__h472698, - f1_exp82139_MINUS_127__q136, - f1_exp__h482139, - f2_exp21133_MINUS_127__q176, - f2_exp__h521133, - f3_exp60437_MINUS_127__q153, - f3_exp__h560437, - out_exp__h354714, - out_exp__h363296, - out_exp__h372480, - out_exp__h381116, - out_exp__h400411, - out_exp__h408993, - out_exp__h418177, - out_exp__h426813, - out_exp__h446106, - out_exp__h454688, - out_exp__h463872, - out_exp__h472508, - out_f_exp__h381492, - out_f_exp__h427189, - out_f_exp__h472884, - x__h613033; + _theResult___exp__h354712, + _theResult___exp__h363294, + _theResult___exp__h372478, + _theResult___exp__h381114, + _theResult___exp__h381216, + _theResult___exp__h400409, + _theResult___exp__h408991, + _theResult___exp__h418175, + _theResult___exp__h426811, + _theResult___exp__h426913, + _theResult___exp__h446104, + _theResult___exp__h454686, + _theResult___exp__h463870, + _theResult___exp__h472506, + _theResult___exp__h472608, + _theResult___fst_exp__h354196, + _theResult___fst_exp__h354261, + _theResult___fst_exp__h354267, + _theResult___fst_exp__h354270, + _theResult___fst_exp__h354793, + _theResult___fst_exp__h362843, + _theResult___fst_exp__h362849, + _theResult___fst_exp__h362852, + _theResult___fst_exp__h363375, + _theResult___fst_exp__h371962, + _theResult___fst_exp__h372027, + _theResult___fst_exp__h372033, + _theResult___fst_exp__h372036, + _theResult___fst_exp__h372559, + _theResult___fst_exp__h380599, + _theResult___fst_exp__h380638, + _theResult___fst_exp__h380644, + _theResult___fst_exp__h380647, + _theResult___fst_exp__h381195, + _theResult___fst_exp__h381204, + _theResult___fst_exp__h381207, + _theResult___fst_exp__h399893, + _theResult___fst_exp__h399958, + _theResult___fst_exp__h399964, + _theResult___fst_exp__h399967, + _theResult___fst_exp__h400490, + _theResult___fst_exp__h408540, + _theResult___fst_exp__h408546, + _theResult___fst_exp__h408549, + _theResult___fst_exp__h409072, + _theResult___fst_exp__h417659, + _theResult___fst_exp__h417724, + _theResult___fst_exp__h417730, + _theResult___fst_exp__h417733, + _theResult___fst_exp__h418256, + _theResult___fst_exp__h426296, + _theResult___fst_exp__h426335, + _theResult___fst_exp__h426341, + _theResult___fst_exp__h426344, + _theResult___fst_exp__h426892, + _theResult___fst_exp__h426901, + _theResult___fst_exp__h426904, + _theResult___fst_exp__h445588, + _theResult___fst_exp__h445653, + _theResult___fst_exp__h445659, + _theResult___fst_exp__h445662, + _theResult___fst_exp__h446185, + _theResult___fst_exp__h454235, + _theResult___fst_exp__h454241, + _theResult___fst_exp__h454244, + _theResult___fst_exp__h454767, + _theResult___fst_exp__h463354, + _theResult___fst_exp__h463419, + _theResult___fst_exp__h463425, + _theResult___fst_exp__h463428, + _theResult___fst_exp__h463951, + _theResult___fst_exp__h471991, + _theResult___fst_exp__h472030, + _theResult___fst_exp__h472036, + _theResult___fst_exp__h472039, + _theResult___fst_exp__h472587, + _theResult___fst_exp__h472596, + _theResult___fst_exp__h472599, + _theResult___snd_fst_exp__h363378, + _theResult___snd_fst_exp__h381198, + _theResult___snd_fst_exp__h409075, + _theResult___snd_fst_exp__h426895, + _theResult___snd_fst_exp__h454770, + _theResult___snd_fst_exp__h472590, + din_inc___2_exp__h381229, + din_inc___2_exp__h381253, + din_inc___2_exp__h381283, + din_inc___2_exp__h381307, + din_inc___2_exp__h426926, + din_inc___2_exp__h426950, + din_inc___2_exp__h426980, + din_inc___2_exp__h427004, + din_inc___2_exp__h472621, + din_inc___2_exp__h472645, + din_inc___2_exp__h472675, + din_inc___2_exp__h472699, + f1_exp82140_MINUS_127__q136, + f1_exp__h482140, + f2_exp21134_MINUS_127__q176, + f2_exp__h521134, + f3_exp60438_MINUS_127__q153, + f3_exp__h560438, + out_exp__h354715, + out_exp__h363297, + out_exp__h372481, + out_exp__h381117, + out_exp__h400412, + out_exp__h408994, + out_exp__h418178, + out_exp__h426814, + out_exp__h446107, + out_exp__h454689, + out_exp__h463873, + out_exp__h472509, + out_f_exp__h381493, + out_f_exp__h427190, + out_f_exp__h472885, + x__h613035; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031, @@ -5839,11 +5848,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083, - x__h181698, - x__h711438; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16096, + x__h181699, + x__h712418; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651, + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953, @@ -5861,25 +5870,25 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965, checkForException___d13008, checkForException___d13698, - fflags__h727255, - fflags__h729891, - fflags__h732495, - old_fflags__h731983, - po_fflags__h727241, - po_fflags__h729877, - r1__read__h614599, - res_fflags__h337869, - res_fflags__h383571, - res_fflags__h429266, - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, - rs1__h655326, - x__h153724, - x__h157271, - x__h160087, - x__h287278, - y_avValue_fst__h729252, - y_avValue_fst__h732400, - y_avValue_fst__h732432; + fflags__h728257, + fflags__h730910, + fflags__h733530, + old_fflags__h733017, + po_fflags__h728242, + po_fflags__h730895, + r1__read__h614601, + res_fflags__h337870, + res_fflags__h383572, + res_fflags__h429267, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, + rs1__h655328, + x__h153725, + x__h157272, + x__h160088, + x__h287279, + y_avValue_fst__h730270, + y_avValue_fst__h733435, + y_avValue_fst__h733467; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855, @@ -5906,77 +5915,77 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h708463, - vm_mode_reg__read__h614202; + cause_code__h709443, + vm_mode_reg__read__h614204; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h296520, - dcsr_cause__h707982, - next_deqP___1__h296799, - v__h295940, - v__h296171, - x__h302150, - x_decodeInfo_frm__h655010; + _theResult_____2__h296521, + dcsr_cause__h708962, + next_deqP___1__h296800, + v__h295941, + v__h296172, + x__h302151, + x_decodeInfo_frm__h655012; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670, - IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74, - IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99, - IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29, - IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109, - IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39, - IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156, - IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64, - IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135, - IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66, - IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79, - IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101, - IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31, - IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114, - IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44, - IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159, - guard__h346094, - guard__h354803, - guard__h363733, - guard__h372569, - guard__h391793, - guard__h400500, - guard__h409430, - guard__h418266, - guard__h437488, - guard__h446195, - guard__h455125, - guard__h463961, - guard__h493566, - guard__h502878, - guard__h511947, - guard__h532419, - guard__h541731, - guard__h550800, - guard__h571723, - guard__h581035, - guard__h590104, - prv__h734164, - prv__h734208, - r1__read_BITS_13_TO_12___h655195, - sbIdx__h157150, - v__h603882, - v__h603892, - v__h604527, - x__h721573, - x__h732759, - x_prv__h711506, - x_prv__h722029, - y_avValue_snd_snd_snd_fst__h729727, - y_avValue_snd_snd_snd_fst__h732569, - y_avValue_snd_snd_snd_fst__h732605; + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683, + IF_sfdin11099_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin17653_BIT_33_THEN_2_ELSE_0__q74, + IF_sfdin45582_BIT_33_THEN_2_ELSE_0__q99, + IF_sfdin49952_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin54190_BIT_33_THEN_2_ELSE_0__q29, + IF_sfdin63348_BIT_33_THEN_2_ELSE_0__q109, + IF_sfdin71956_BIT_33_THEN_2_ELSE_0__q39, + IF_sfdin89256_BIT_4_THEN_2_ELSE_0__q156, + IF_sfdin99887_BIT_33_THEN_2_ELSE_0__q64, + IF_theResult___snd01479_BIT_4_THEN_2_ELSE_0__q135, + IF_theResult___snd08500_BIT_33_THEN_2_ELSE_0__q66, + IF_theResult___snd19884_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd26290_BIT_33_THEN_2_ELSE_0__q79, + IF_theResult___snd40332_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd54195_BIT_33_THEN_2_ELSE_0__q101, + IF_theResult___snd58737_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd62803_BIT_33_THEN_2_ELSE_0__q31, + IF_theResult___snd71985_BIT_33_THEN_2_ELSE_0__q114, + IF_theResult___snd79636_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd80593_BIT_33_THEN_2_ELSE_0__q44, + IF_theResult___snd98041_BIT_4_THEN_2_ELSE_0__q159, + guard__h346095, + guard__h354804, + guard__h363734, + guard__h372570, + guard__h391794, + guard__h400501, + guard__h409431, + guard__h418267, + guard__h437489, + guard__h446196, + guard__h455126, + guard__h463962, + guard__h493567, + guard__h502879, + guard__h511948, + guard__h532420, + guard__h541732, + guard__h550801, + guard__h571724, + guard__h581036, + guard__h590105, + prv__h735199, + prv__h735243, + r1__read_BITS_13_TO_12___h655197, + sbIdx__h157151, + v__h603883, + v__h603893, + v__h604528, + x__h722556, + x__h733794, + x_prv__h712487, + x_prv__h723013, + y_avValue_snd_snd_snd_fst__h730745, + y_avValue_snd_snd_snd_fst__h733604, + y_avValue_snd_snd_snd_fst__h733640; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461, @@ -6056,7 +6065,7 @@ module mkCore(CLK, IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13916, IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13831, IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13915, - IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661, + IF_NOT_rob_deqPort_1_deq_data__5322_BIT_25_532_ETC___d15674, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900, @@ -6179,7 +6188,7 @@ module mkCore(CLK, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662, + IF_rob_deqPort_1_canDeq__5319_THEN_IF_NOT_rob__ETC___d15675, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613, @@ -6189,25 +6198,27 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13422, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725, - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667, + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286, NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484, - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614, - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621, - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684, - NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995, + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14624, + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14631, + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695, + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005, + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15016, + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15368, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257, NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369, @@ -6263,7 +6274,7 @@ module mkCore(CLK, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723, - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731, + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13527, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13814, @@ -6315,10 +6326,10 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13736, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13878, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13896, - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345, - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645, - NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983, - NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342, + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_RDY_ETC___d15356, + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658, + NOT_rob_deqPort_0_deq_data__4339_BITS_329_TO_3_ETC___d14993, + NOT_rob_deqPort_1_deq_data__5322_BIT_25_5323_5_ETC___d15353, NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14007, NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14074, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132, @@ -6357,8 +6368,9 @@ module mkCore(CLK, _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928, _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829, _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14020, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687, + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184, @@ -6384,7 +6396,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo20, + _dfoo22, _dfoo24, _dfoo26, _dfoo32, @@ -6413,12 +6425,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h304516, - _theResult_____2__h310510, - _theResult_____2__h318364, - _theResult_____2__h328708, - _theResult_____2__h331933, - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644, + _theResult_____2__h304517, + _theResult_____2__h310511, + _theResult_____2__h318365, + _theResult_____2__h328709, + _theResult_____2__h331934, + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244, coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218, @@ -6517,18 +6529,18 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574, - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646, + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14656, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791, - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707, - csrf_prv_reg_read__2787_ULE_1___d14685, + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718, + csrf_prv_reg_read__2787_ULE_1___d14696, csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040, csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13876, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13894, - f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880, + f_csr_rsps_i_notFull__5790_AND_f_csr_reqs_firs_ETC___d15893, fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14018, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100, @@ -6553,14 +6565,14 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13835, fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13973, fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13985, - guard__h364331, - guard__h410028, - guard__h455723, - guard__h503476, - guard__h542329, - guard__h581633, - idx__h685368, - k__h669623, + guard__h364332, + guard__h410029, + guard__h455724, + guard__h503477, + guard__h542330, + guard__h581634, + idx__h685370, + k__h669625, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6573,14 +6585,15 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14094, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h76121, - next_deqP___1__h304795, - next_deqP___1__h311076, - next_deqP___1__h318930, - next_deqP___1__h328987, - next_deqP___1__h332212, - r1__read_BIT_20___h655891, - regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941, + msip__h76122, + next_deqP___1__h304796, + next_deqP___1__h311077, + next_deqP___1__h318931, + next_deqP___1__h328988, + next_deqP___1__h332213, + r1__read_BIT_20___h655893, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941, regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022, regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429, regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479, @@ -6603,26 +6616,24 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13799, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920, - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716, - rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988, - rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309, + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15729, + rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, - tsr_val__h725552, - tvm_val__h725554, - v__h299285, - v__h299803, - v__h309799, - v__h310030, - v__h313675, - v__h313906, - v__h328276, - v__h328507, - v__h331501, - v__h331732, - value_BIT_23___h494224, - x__h603383; + tsr_val__h726551, + tvm_val__h726553, + v__h299286, + v__h299804, + v__h309800, + v__h310031, + v__h313676, + v__h313907, + v__h328277, + v__h328508, + v__h331502, + v__h331733, + x__h603384; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6660,10 +6671,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6681,9 +6692,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16096 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -6970,7 +6981,7 @@ module mkCore(CLK, // actionvalue method v_to_TV_0_get assign v_to_TV_0_get = - { v_f_to_TV_0$D_OUT[784:476], + { v_f_to_TV_0$D_OUT[861:476], CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, v_f_to_TV_0$D_OUT[463:462], v_f_to_TV_0$D_OUT[462] ? @@ -6985,7 +6996,7 @@ module mkCore(CLK, // actionvalue method v_to_TV_1_get assign v_to_TV_1_get = - { v_f_to_TV_1$D_OUT[784:476], + { v_f_to_TV_1$D_OUT[861:476], CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, v_f_to_TV_1$D_OUT[463:462], v_f_to_TV_1$D_OUT[462] ? @@ -9790,7 +9801,7 @@ module mkCore(CLK, .RDY_isFull_ehrPort0()); // submodule v_f_to_TV_0 - FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N), .CLK(CLK), .D_IN(v_f_to_TV_0$D_IN), .ENQ(v_f_to_TV_0$ENQ), @@ -9801,7 +9812,7 @@ module mkCore(CLK, .EMPTY_N(v_f_to_TV_0$EMPTY_N)); // submodule v_f_to_TV_1 - FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N), .CLK(CLK), .D_IN(v_f_to_TV_1$D_IN), .ENQ(v_f_to_TV_1$ENQ), @@ -9817,32 +9828,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && - l2Tlb$RDY_toChildren_rsToC_deq && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && + l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9854,16 +9865,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9884,7 +9895,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716 && + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15729 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9981,7 +9992,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880 && + f_csr_rsps_i_notFull__5790_AND_f_csr_reqs_firs_ETC___d15893 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10001,9 +10012,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -10295,7 +10306,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && commitStage_f_rob_data$FULL_N && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && @@ -10311,12 +10322,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10336,14 +10347,22 @@ module mkCore(CLK, assign WILL_FIRE_RL_commitStage_rl_send_tv_reset = CAN_FIRE_RL_commitStage_rl_send_tv_reset ; + // rule RL_commitStage_rl_send_mip_csr_change_to_tv + assign CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = + v_f_to_TV_0$FULL_N && !commitStage_rg_just_after_reset && + !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; + assign WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; + // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = commitStage_f_rob_data$EMPTY_N && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621 && - (commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646) && + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14631 && + (commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14656) && + commitStage_commitTrap[165] && !commitStage_rg_run_state && - commitStage_commitTrap[165] ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = CAN_FIRE_RL_commitStage_doCommitTrap_handle && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10355,8 +10374,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10370,12 +10389,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10392,17 +10411,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988 && - NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 && - (rob$deqPort_0_deq_data[329:325] == 5'd0 || - rob$deqPort_0_deq_data[329:325] == 5'd21 || - rob$deqPort_0_deq_data[329:325] == 5'd17 || - rob$deqPort_0_deq_data[329:325] == 5'd18 || - rob$deqPort_0_deq_data[329:325] == 5'd13 || - rob$deqPort_0_deq_data[329:325] == 5'd16 || - rob$deqPort_0_deq_data[329:325] == 5'd15 || - rob$deqPort_0_deq_data[329:325] == 5'd19 || - rob$deqPort_0_deq_data[329:325] == 5'd20) ; + rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998 && + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15016 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10436,17 +10446,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345 && - NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 && - rob$deqPort_0_deq_data[329:325] != 5'd0 && - rob$deqPort_0_deq_data[329:325] != 5'd21 && - rob$deqPort_0_deq_data[329:325] != 5'd17 && - rob$deqPort_0_deq_data[329:325] != 5'd18 && - rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[329:325] != 5'd16 && - rob$deqPort_0_deq_data[329:325] != 5'd15 && - rob$deqPort_0_deq_data[329:325] != 5'd19 && - rob$deqPort_0_deq_data[329:325] != 5'd20 ; + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_RDY_ETC___d15356 && + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15368 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -10465,12 +10466,12 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10497,12 +10498,12 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10595,8 +10596,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10607,8 +10608,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10620,8 +10621,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10649,6 +10650,8 @@ module mkCore(CLK, rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10660,7 +10663,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10672,8 +10675,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10686,8 +10690,9 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10701,8 +10706,9 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10714,11 +10720,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10726,16 +10727,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -10759,8 +10760,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10857,8 +10858,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10875,8 +10876,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10898,8 +10899,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10911,12 +10912,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10944,12 +10945,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -11062,8 +11063,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -11123,16 +11124,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush && + commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -11140,7 +11141,9 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_debug_resume = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -11158,8 +11161,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11172,7 +11175,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -11203,7 +11206,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -11279,10 +11282,6 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon = 1'd1 ; - // rule RL_coreFix_memExe_memRespLdQ_canonicalize - assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; - // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; @@ -11299,6 +11298,10 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ; + // rule RL_coreFix_memExe_memRespLdQ_canonicalize + assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; + // rule RL_coreFix_memExe_memRespLdQ_clearReq_canon assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ; @@ -11391,8 +11394,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11412,9 +11415,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11426,8 +11429,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11513,10 +11516,13 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ; + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 ; + assign MUX_commitStage_rg_serial_num$write_1__SEL_2 = + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || + WILL_FIRE_RL_commitStage_doCommitSystemInst ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -11525,7 +11531,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11708,9 +11715,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd9 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11718,9 +11725,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd16 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11729,20 +11736,20 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29 ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd0 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11751,22 +11758,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd0 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11778,9 +11785,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11790,21 +11797,21 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11818,7 +11825,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11826,7 +11833,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11840,7 +11847,7 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; @@ -11850,7 +11857,7 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11873,12 +11880,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd41 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11904,7 +11911,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11915,7 +11922,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11935,7 +11942,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11953,7 +11960,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 && NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205 && IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 ; - assign MUX_flush_reservation$write_1__SEL_2 = + assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -11988,7 +11995,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ; assign MUX_rg_core_run_state$write_1__SEL_4 = WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -12010,9 +12017,6 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[89] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ; - assign MUX_started$write_1__SEL_1 = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -12023,15 +12027,27 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h701397, - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, + x__h702377, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h732518 ; + commitStage_rg_serial_num + y__h733553 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h669623 == 1'd0 && + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + (k__h669625 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12052,22 +12068,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -12155,7 +12159,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, @@ -12169,10 +12173,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h285845 } ; + x__h285846 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h287290, + x__h287291, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12180,7 +12184,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h290066, + addr__h290067, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12193,12 +12197,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h153724, x__h153730, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h153725, x__h153731, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h157271, x__h157277, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h157272, x__h157278, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h160087, - x__h160091, + { x__h160088, + x__h160092, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -12209,7 +12213,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161939, + x__h161940, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -12222,7 +12226,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h291970, + resp_addr__h291971, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -12230,8 +12234,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h734208, - prv__h734208 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h735243, + prv__h735243 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12308,7 +12312,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h197125 } ; + x__h197126 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12343,8 +12347,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h192915 : - { {32{x__h193678[31]}}, x__h193678 } } ; + curData__h192916 : + { {32{x__h193679[31]}}, x__h193679 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12377,9 +12381,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h732495 ; + csrf_fflags_reg | fflags__h733530 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ; @@ -12387,10 +12391,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 or + always@(IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973) + case (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13]; @@ -12405,55 +12409,55 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h725937 + 64'd1 ; + n__read__h726937 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h725937 + { 62'd0, x__h732759 } ; + n__read__h726937 + { 62'd0, x__h733794 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd8 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h721573 : + x__h722556 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h707982, + dcsr_cause__h708962, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12463,13 +12467,13 @@ module mkCore(CLK, amoExec___d880[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h736609 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h737644 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12478,12 +12482,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h721469 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h722452 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h721469; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h722452; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12495,7 +12499,7 @@ module mkCore(CLK, assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274, + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, mmio_dataReqQ_data_0[71:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, @@ -12518,24 +12522,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h337873 : - res_data__h337868 ; + res_data__h337874 : + res_data__h337869 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h383575 : - res_data__h383570 ; + res_data__h383576 : + res_data__h383571 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h429270 : - res_data__h429265 ; + res_data__h429271 : + res_data__h429266 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h475007 : + data___1__h475008 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h475815 : - data__h475281 ; + data___1__h475816 : + data__h475282 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -12595,54 +12599,57 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h337869 ; + res_fflags__h337870 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h383571 ; + res_fflags__h383572 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h429266 ; + res_fflags__h429267 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, commitStage_f_rob_data$D_OUT[425:181], - CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277, - commitStage_f_rob_data$D_OUT[167:166], - commitStage_f_rob_data$D_OUT[166] ? - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 : - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279, - IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916 } ; + CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, + commitStage_f_rob_data_first__4755_BIT_167_485_ETC___d14927 } ; assign MUX_v_f_to_TV_0$enq_1__VAL_2 = { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494, + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501, - fflags__h727255, + IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512, + fflags__h728257, rob$deqPort_0_deq_data[26], - x__h728883, + x__h729900, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, - x__h722034, + 13'd4932, + mip_csr__read__h611252, + 721'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign MUX_v_f_to_TV_0$enq_1__VAL_5 = + { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, + x__h723033, rob$deqPort_0_deq_data[361:182], - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494, + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, - rob$deqPort_0_deq_data[161:98], - IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281 } ; + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, + rob_deqPort_0_deq_data__4339_BITS_161_TO_98_43_ETC___d15292 } ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12932,18 +12939,23 @@ module mkCore(CLK, assign commitStage_rg_just_after_reset$EN = CAN_FIRE_RL_commitStage_rl_send_tv_reset ; + // register commitStage_rg_old_mip_csr_val + assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h611252 ; + assign commitStage_rg_old_mip_csr_val$EN = + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; + // register commitStage_rg_run_state assign commitStage_rg_run_state$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serial_num always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_commitStage_rg_serial_num$write_1__VAL_1 or - WILL_FIRE_RL_commitStage_doCommitSystemInst or + MUX_commitStage_rg_serial_num$write_1__SEL_2 or WILL_FIRE_RL_commitStage_doCommitNormalInst or MUX_commitStage_rg_serial_num$write_1__VAL_3 or WILL_FIRE_RL_commitStage_rl_send_tv_reset) @@ -12952,7 +12964,7 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_1; - WILL_FIRE_RL_commitStage_doCommitSystemInst: + MUX_commitStage_rg_serial_num$write_1__SEL_2: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_1; WILL_FIRE_RL_commitStage_doCommitNormalInst: @@ -12966,7 +12978,8 @@ module mkCore(CLK, end assign commitStage_rg_serial_num$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst || WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -12990,8 +13003,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h604527 : - v__h603882 ; + v__h604528 : + v__h603883 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -13013,7 +13026,9 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd0 && @@ -13023,9 +13038,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd1 && @@ -13035,7 +13048,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd2 && @@ -13045,7 +13058,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd3 && @@ -13055,7 +13068,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd4 && @@ -13065,7 +13078,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd5 && @@ -13075,7 +13088,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd6 && @@ -13085,7 +13098,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7 && @@ -13098,7 +13111,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h296520 ; + _theResult_____2__h296521 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -13120,7 +13133,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h295940 ; + v__h295941 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -13166,7 +13179,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - _theResult_____2__h304516 ; + _theResult_____2__h304517 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -13184,7 +13197,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - v__h299285 ; + v__h299286 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13284,7 +13297,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - _theResult_____2__h310510 ; + _theResult_____2__h310511 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13302,7 +13315,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - v__h309799 ; + v__h309800 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13323,7 +13336,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h314073, + { x_addr__h314074, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13353,7 +13366,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - _theResult_____2__h318364 ; + _theResult_____2__h318365 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13371,7 +13384,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - v__h313675 ; + v__h313676 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13448,7 +13461,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - _theResult_____2__h331933 ; + _theResult_____2__h331934 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13466,7 +13479,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - v__h331501 ; + v__h331502 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13509,7 +13522,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - _theResult_____2__h328708 ; + _theResult_____2__h328709 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13527,7 +13540,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - v__h328276 ; + v__h328277 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13707,7 +13720,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13756,7 +13769,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29 || EN_setMEIP ; @@ -13778,12 +13791,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd0 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13796,9 +13809,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13820,7 +13833,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13853,13 +13866,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -13875,24 +13888,24 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h708463 or + cause_code__h709443 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h708463; + csrf_mcause_code_reg$D_IN = cause_code__h709443; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -13901,11 +13914,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -13928,11 +13941,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -13945,7 +13958,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -13958,7 +13971,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -13971,7 +13984,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -13988,7 +14001,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd20 ; // register csrf_medeleg_15_reg @@ -14001,7 +14014,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -14014,7 +14027,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd20 ; // register csrf_mepc_csr @@ -14037,11 +14050,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd26 ; // register csrf_mideleg_11_reg @@ -14054,7 +14067,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -14067,7 +14080,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -14080,7 +14093,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -14093,7 +14106,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -14118,12 +14131,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -14135,7 +14148,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_mscratch_csr @@ -14148,19 +14161,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd25 ; // register csrf_mtval_csr always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h708464 or + trap_val__h709444 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h708464; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h709444; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14170,11 +14183,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -14187,7 +14200,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14200,7 +14213,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd23 ; // register csrf_mxr_reg @@ -14224,7 +14237,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14253,13 +14266,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -14276,34 +14289,34 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h711506 or + x_prv__h712487 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h711506; + csrf_prv_reg$D_IN = x_prv__h712487; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -14323,12 +14336,12 @@ module mkCore(CLK, endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40 ; // register csrf_rg_dpc @@ -14347,12 +14360,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd41 ; // register csrf_rg_dscratch0 @@ -14365,7 +14378,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd42 ; // register csrf_rg_dscratch1 @@ -14378,7 +14391,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd43 ; // register csrf_rg_tdata1_data @@ -14391,7 +14404,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd37 ; // register csrf_rg_tdata1_dmode @@ -14404,7 +14417,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd37 ; // register csrf_rg_tdata2 @@ -14417,7 +14430,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd38 ; // register csrf_rg_tdata3 @@ -14430,7 +14443,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd39 ; // register csrf_rg_tselect @@ -14443,20 +14456,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd36 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h708463 or + cause_code__h709443 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h708463; + csrf_scause_code_reg$D_IN = cause_code__h709443; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14465,11 +14478,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14492,11 +14505,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14509,7 +14522,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14522,7 +14535,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14535,7 +14548,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd11 ; // register csrf_sepc_csr @@ -14558,11 +14571,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14590,7 +14603,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14634,7 +14647,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29 ; // register csrf_spp_reg @@ -14651,13 +14664,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14669,7 +14682,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd12 ; // register csrf_stats_module_doStats @@ -14680,12 +14693,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h708464 or + trap_val__h709444 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h708464; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h709444; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14695,11 +14708,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14712,7 +14725,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14725,7 +14738,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd10 ; // register csrf_sum_reg @@ -14768,7 +14781,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14802,7 +14815,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_tvm_reg @@ -14815,7 +14828,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_tw_reg @@ -14828,7 +14841,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -14841,28 +14854,28 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -14870,11 +14883,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[329:325] == 5'd16 || rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14883,7 +14896,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46291, + { x__h46292, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14895,7 +14908,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48827 } ; + x__h48828 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -14988,7 +15001,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18384, + { x__h18385, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15000,7 +15013,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20922 } ; + x__h20923 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -15084,7 +15097,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h66085 } ; + x_data__h66086 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -15207,18 +15220,18 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data assign commitStage_f_rob_data$D_IN = { rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494, + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[168:167], - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501, + IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512, rob$deqPort_0_deq_data[31:0] } ; assign commitStage_f_rob_data$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_flush ; @@ -15327,8 +15340,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h639739, - x__h639740, + x__h639741, + x__h639742, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -15466,9 +15479,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -15618,8 +15631,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h617230, - x__h617231, + x__h617232, + x__h617233, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -15661,7 +15674,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h669623 == 1'd1 && + (k__h669625 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -15682,7 +15695,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16161,19 +16174,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h603369 : - a__h602947 ; + _theResult___fst__h603370 : + a__h602948 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h602948 == 64'd0, - a__h602947, + { b__h602949 == 64'd0, + a__h602948, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h603383, - a__h602947[63], + x__h603384, + a__h602948[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h603370 : - b__h602948 ; + _theResult___snd__h603371 : + b__h602949 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -16234,20 +16247,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602947 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602948 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602948 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602949 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h602947 ; + a__h602948 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h602948 ; + b__h602949 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h602947 ; + a__h602948 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h602948 ; + b__h602949 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -16276,9 +16289,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h481669, x__h481670, x__h481671, + x__h481672, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -16330,7 +16343,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16484,8 +16497,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h287278, - x__h287290, + { x__h287279, + x__h287291, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797, @@ -16496,13 +16509,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828, - x__h289144, + x__h289145, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h285845 ; + x__h285846 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -16725,7 +16738,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN = 1'd1 ; assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN = - MUX_flush_reservation$write_1__SEL_2 ; + MUX_flush_reservation$write_1__SEL_1 ; // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = @@ -17296,7 +17309,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685237 ; + renaming_spec_bits__h685239 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? @@ -17316,7 +17329,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685237 ; + renaming_spec_bits__h685239 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17396,7 +17409,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h181566 ; + shiftData__h181567 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17496,8 +17509,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h181475, x__h181476, + x__h181477, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -17761,7 +17774,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17989,7 +18002,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -18003,7 +18016,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -18021,7 +18034,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -18032,7 +18045,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -18209,7 +18222,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h711407 or + pc__h712387 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18223,7 +18236,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h711407; + fetchStage$redirect_pc = pc__h712387; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18322,14 +18335,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18643,7 +18656,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h685237 ; + renaming_spec_bits__h685239 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -18915,7 +18928,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, 7'd32, - renaming_spec_bits__h685237 } ; + renaming_spec_bits__h685239 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18925,24 +18938,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -19231,16 +19244,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -19533,8 +19546,10 @@ module mkCore(CLK, MUX_v_f_to_TV_0$enq_1__SEL_2 or MUX_v_f_to_TV_0$enq_1__VAL_2 or WILL_FIRE_RL_commitStage_rl_send_tv_reset or + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv or + MUX_v_f_to_TV_0$enq_1__VAL_4 or WILL_FIRE_RL_commitStage_doCommitSystemInst or - MUX_v_f_to_TV_0$enq_1__VAL_4) + MUX_v_f_to_TV_0$enq_1__VAL_5) begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: @@ -19543,35 +19558,39 @@ module mkCore(CLK, v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_2; WILL_FIRE_RL_commitStage_rl_send_tv_reset: v_f_to_TV_0$D_IN = - 785'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_commitStage_doCommitSystemInst: + 862'h000000000000000015555555555555555554AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv: v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_4; + WILL_FIRE_RL_commitStage_doCommitSystemInst: + v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_5; default: v_f_to_TV_0$D_IN = - 785'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 862'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign v_f_to_TV_0$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq || WILL_FIRE_RL_commitStage_rl_send_tv_reset || + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst ; assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ; assign v_f_to_TV_0$CLR = 1'b0 ; // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438, + { commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450, + 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_1_deq_data[425:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, 6'd10, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, rob$deqPort_1_deq_data[95:32], - fflags__h729891, + fflags__h730910, rob$deqPort_1_deq_data[26], - x__h732011, + x__h733045, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19593,33 +19612,21 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h192915), + .amoExec_current_data(curData__h192916), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h194453)); + .amoExec(n__h194454)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h76121 }), - .amoExec_in_data({ 32'd0, x__h76236 }), + msip__h76122 }), + .amoExec_in_data({ 32'd0, x__h76237 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d880)); - module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228, - { coreFix_aluExe_0_regToExeQ$first[395], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229, - coreFix_aluExe_0_regToExeQ$first[382], - coreFix_aluExe_0_regToExeQ$first[381:350] } }), - .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), - .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), - .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), - .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), - .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12617)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, { coreFix_aluExe_1_regToExeQ$first[395], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, coreFix_aluExe_1_regToExeQ$first[382], coreFix_aluExe_1_regToExeQ$first[381:350] } }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]), @@ -19628,12 +19635,24 @@ module mkCore(CLK, .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), .basicExec(basicExec___d11943)); + module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, + { coreFix_aluExe_0_regToExeQ$first[395], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, + coreFix_aluExe_0_regToExeQ$first[382], + coreFix_aluExe_0_regToExeQ$first[381:350] } }), + .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), + .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), + .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), + .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), + .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), + .basicExec(basicExec___d12617)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 }, fetchStage$pipelines_0_first[160], - x_data_imm__h676655 } }), + x_data_imm__h676657 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19642,13 +19661,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655010, - r1__read_BITS_13_TO_12___h655195 != + .checkForException_csrState({ x_decodeInfo_frm__h655012, + r1__read_BITS_13_TO_12___h655197 != 2'd0, - { prv__h734164, - tvm_val__h725554, - { r1__read_BIT_20___h655891, - tsr_val__h725552, + { prv__h735199, + tvm_val__h726553, + { r1__read_BIT_20___h655893, + tsr_val__h726551, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19663,7 +19682,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, { fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, fetchStage$pipelines_1_first[160], - x_data_imm__h692709 } }), + x_data_imm__h692711 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19672,13 +19691,13 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655010, - r1__read_BITS_13_TO_12___h655195 != + .checkForException_csrState({ x_decodeInfo_frm__h655012, + r1__read_BITS_13_TO_12___h655197 != 2'd0, - { prv__h734164, - tvm_val__h725554, - { r1__read_BIT_20___h655891, - tsr_val__h725552, + { prv__h735199, + tvm_val__h726553, + { r1__read_BIT_20___h655893, + tsr_val__h726551, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19690,1198 +19709,1198 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13698)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h481760), - .execFpuSimple_rVal2(rVal2__h481761), + .execFpuSimple_rVal1(rVal1__h481761), + .execFpuSimple_rVal2(rVal2__h481762), .execFpuSimple(execFpuSimple___d11056)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 ? - _theResult___snd__h354258 : - _theResult____h346084 ; + _theResult___snd__h354259 : + _theResult____h346085 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 ? - _theResult___snd__h399955 : - _theResult____h391783 ; + _theResult___snd__h399956 : + _theResult____h391784 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 ? - _theResult___snd__h445650 : - _theResult____h437478 ; + _theResult___snd__h445651 : + _theResult____h437479 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 ? - _theResult___snd__h511167 : - _theResult____h502868 ; + _theResult___snd__h511168 : + _theResult____h502869 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 ? - _theResult___snd__h589324 : - _theResult____h581025 ; + _theResult___snd__h589325 : + _theResult____h581026 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 ? - _theResult___snd__h550020 : - _theResult____h541721 ; + _theResult___snd__h550021 : + _theResult____h541722 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 ? - _theResult___snd__h463416 : - _theResult____h455115 ; + _theResult___snd__h463417 : + _theResult____h455116 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 ? - _theResult___snd__h372024 : - _theResult____h363723 ; + _theResult___snd__h372025 : + _theResult____h363724 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 ? - _theResult___snd__h417721 : - _theResult____h409420 ; + _theResult___snd__h417722 : + _theResult____h409421 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 ? - _theResult___snd__h501516 : + _theResult___snd__h501517 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 ? - _theResult___snd__h501516 : - _theResult___snd__h519921 ; + _theResult___snd__h501517 : + _theResult___snd__h519922 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 ? - _theResult___snd__h579673 : + _theResult___snd__h579674 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 ? - _theResult___snd__h579673 : - _theResult___snd__h598078 ; + _theResult___snd__h579674 : + _theResult___snd__h598079 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 ? - _theResult___snd__h540369 : + _theResult___snd__h540370 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 ? - _theResult___snd__h540369 : - _theResult___snd__h558774 ; + _theResult___snd__h540370 : + _theResult___snd__h558775 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 ? - _theResult___snd__h454232 : + _theResult___snd__h454233 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 ? - _theResult___snd__h454232 : - _theResult___snd__h472022 ; + _theResult___snd__h454233 : + _theResult___snd__h472023 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 ? - _theResult___snd__h362840 : + _theResult___snd__h362841 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 ? - _theResult___snd__h362840 : - _theResult___snd__h380630 ; + _theResult___snd__h362841 : + _theResult___snd__h380631 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 ? - _theResult___snd__h408537 : + _theResult___snd__h408538 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 ? - _theResult___snd__h408537 : - _theResult___snd__h426327 ; + _theResult___snd__h408538 : + _theResult___snd__h426328 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354195 == 8'd255) ? + ((_theResult___fst_exp__h354196 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054) : - ((_theResult___fst_exp__h362851 == 8'd255) ? + ((_theResult___fst_exp__h362852 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354195 == 8'd255) ? + ((_theResult___fst_exp__h354196 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110) : - ((_theResult___fst_exp__h362851 == 8'd255) ? + ((_theResult___fst_exp__h362852 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399892 == 8'd255) ? + ((_theResult___fst_exp__h399893 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446) : - ((_theResult___fst_exp__h408548 == 8'd255) ? + ((_theResult___fst_exp__h408549 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399892 == 8'd255) ? + ((_theResult___fst_exp__h399893 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502) : - ((_theResult___fst_exp__h408548 == 8'd255) ? + ((_theResult___fst_exp__h408549 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445587 == 8'd255) ? + ((_theResult___fst_exp__h445588 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838) : - ((_theResult___fst_exp__h454243 == 8'd255) ? + ((_theResult___fst_exp__h454244 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445587 == 8'd255) ? + ((_theResult___fst_exp__h445588 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894) : - ((_theResult___fst_exp__h454243 == 8'd255) ? + ((_theResult___fst_exp__h454244 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 = - (_theResult____h346084[56] ? + (_theResult____h346085[56] ? 6'd0 : - (_theResult____h346084[55] ? + (_theResult____h346085[55] ? 6'd1 : - (_theResult____h346084[54] ? + (_theResult____h346085[54] ? 6'd2 : - (_theResult____h346084[53] ? + (_theResult____h346085[53] ? 6'd3 : - (_theResult____h346084[52] ? + (_theResult____h346085[52] ? 6'd4 : - (_theResult____h346084[51] ? + (_theResult____h346085[51] ? 6'd5 : - (_theResult____h346084[50] ? + (_theResult____h346085[50] ? 6'd6 : - (_theResult____h346084[49] ? + (_theResult____h346085[49] ? 6'd7 : - (_theResult____h346084[48] ? + (_theResult____h346085[48] ? 6'd8 : - (_theResult____h346084[47] ? + (_theResult____h346085[47] ? 6'd9 : - (_theResult____h346084[46] ? + (_theResult____h346085[46] ? 6'd10 : - (_theResult____h346084[45] ? + (_theResult____h346085[45] ? 6'd11 : - (_theResult____h346084[44] ? + (_theResult____h346085[44] ? 6'd12 : - (_theResult____h346084[43] ? + (_theResult____h346085[43] ? 6'd13 : - (_theResult____h346084[42] ? + (_theResult____h346085[42] ? 6'd14 : - (_theResult____h346084[41] ? + (_theResult____h346085[41] ? 6'd15 : - (_theResult____h346084[40] ? + (_theResult____h346085[40] ? 6'd16 : - (_theResult____h346084[39] ? + (_theResult____h346085[39] ? 6'd17 : - (_theResult____h346084[38] ? + (_theResult____h346085[38] ? 6'd18 : - (_theResult____h346084[37] ? + (_theResult____h346085[37] ? 6'd19 : - (_theResult____h346084[36] ? + (_theResult____h346085[36] ? 6'd20 : - (_theResult____h346084[35] ? + (_theResult____h346085[35] ? 6'd21 : - (_theResult____h346084[34] ? + (_theResult____h346085[34] ? 6'd22 : - (_theResult____h346084[33] ? + (_theResult____h346085[33] ? 6'd23 : - (_theResult____h346084[32] ? + (_theResult____h346085[32] ? 6'd24 : - (_theResult____h346084[31] ? + (_theResult____h346085[31] ? 6'd25 : - (_theResult____h346084[30] ? + (_theResult____h346085[30] ? 6'd26 : - (_theResult____h346084[29] ? + (_theResult____h346085[29] ? 6'd27 : - (_theResult____h346084[28] ? + (_theResult____h346085[28] ? 6'd28 : - (_theResult____h346084[27] ? + (_theResult____h346085[27] ? 6'd29 : - (_theResult____h346084[26] ? + (_theResult____h346085[26] ? 6'd30 : - (_theResult____h346084[25] ? + (_theResult____h346085[25] ? 6'd31 : - (_theResult____h346084[24] ? + (_theResult____h346085[24] ? 6'd32 : - (_theResult____h346084[23] ? + (_theResult____h346085[23] ? 6'd33 : - (_theResult____h346084[22] ? + (_theResult____h346085[22] ? 6'd34 : - (_theResult____h346084[21] ? + (_theResult____h346085[21] ? 6'd35 : - (_theResult____h346084[20] ? + (_theResult____h346085[20] ? 6'd36 : - (_theResult____h346084[19] ? + (_theResult____h346085[19] ? 6'd37 : - (_theResult____h346084[18] ? + (_theResult____h346085[18] ? 6'd38 : - (_theResult____h346084[17] ? + (_theResult____h346085[17] ? 6'd39 : - (_theResult____h346084[16] ? + (_theResult____h346085[16] ? 6'd40 : - (_theResult____h346084[15] ? + (_theResult____h346085[15] ? 6'd41 : - (_theResult____h346084[14] ? + (_theResult____h346085[14] ? 6'd42 : - (_theResult____h346084[13] ? + (_theResult____h346085[13] ? 6'd43 : - (_theResult____h346084[12] ? + (_theResult____h346085[12] ? 6'd44 : - (_theResult____h346084[11] ? + (_theResult____h346085[11] ? 6'd45 : - (_theResult____h346084[10] ? + (_theResult____h346085[10] ? 6'd46 : - (_theResult____h346084[9] ? + (_theResult____h346085[9] ? 6'd47 : - (_theResult____h346084[8] ? + (_theResult____h346085[8] ? 6'd48 : - (_theResult____h346084[7] ? + (_theResult____h346085[7] ? 6'd49 : - (_theResult____h346084[6] ? + (_theResult____h346085[6] ? 6'd50 : - (_theResult____h346084[5] ? + (_theResult____h346085[5] ? 6'd51 : - (_theResult____h346084[4] ? + (_theResult____h346085[4] ? 6'd52 : - (_theResult____h346084[3] ? + (_theResult____h346085[3] ? 6'd53 : - (_theResult____h346084[2] ? + (_theResult____h346085[2] ? 6'd54 : - (_theResult____h346084[1] ? + (_theResult____h346085[1] ? 6'd55 : - (_theResult____h346084[0] ? + (_theResult____h346085[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 = - (_theResult____h391783[56] ? + (_theResult____h391784[56] ? 6'd0 : - (_theResult____h391783[55] ? + (_theResult____h391784[55] ? 6'd1 : - (_theResult____h391783[54] ? + (_theResult____h391784[54] ? 6'd2 : - (_theResult____h391783[53] ? + (_theResult____h391784[53] ? 6'd3 : - (_theResult____h391783[52] ? + (_theResult____h391784[52] ? 6'd4 : - (_theResult____h391783[51] ? + (_theResult____h391784[51] ? 6'd5 : - (_theResult____h391783[50] ? + (_theResult____h391784[50] ? 6'd6 : - (_theResult____h391783[49] ? + (_theResult____h391784[49] ? 6'd7 : - (_theResult____h391783[48] ? + (_theResult____h391784[48] ? 6'd8 : - (_theResult____h391783[47] ? + (_theResult____h391784[47] ? 6'd9 : - (_theResult____h391783[46] ? + (_theResult____h391784[46] ? 6'd10 : - (_theResult____h391783[45] ? + (_theResult____h391784[45] ? 6'd11 : - (_theResult____h391783[44] ? + (_theResult____h391784[44] ? 6'd12 : - (_theResult____h391783[43] ? + (_theResult____h391784[43] ? 6'd13 : - (_theResult____h391783[42] ? + (_theResult____h391784[42] ? 6'd14 : - (_theResult____h391783[41] ? + (_theResult____h391784[41] ? 6'd15 : - (_theResult____h391783[40] ? + (_theResult____h391784[40] ? 6'd16 : - (_theResult____h391783[39] ? + (_theResult____h391784[39] ? 6'd17 : - (_theResult____h391783[38] ? + (_theResult____h391784[38] ? 6'd18 : - (_theResult____h391783[37] ? + (_theResult____h391784[37] ? 6'd19 : - (_theResult____h391783[36] ? + (_theResult____h391784[36] ? 6'd20 : - (_theResult____h391783[35] ? + (_theResult____h391784[35] ? 6'd21 : - (_theResult____h391783[34] ? + (_theResult____h391784[34] ? 6'd22 : - (_theResult____h391783[33] ? + (_theResult____h391784[33] ? 6'd23 : - (_theResult____h391783[32] ? + (_theResult____h391784[32] ? 6'd24 : - (_theResult____h391783[31] ? + (_theResult____h391784[31] ? 6'd25 : - (_theResult____h391783[30] ? + (_theResult____h391784[30] ? 6'd26 : - (_theResult____h391783[29] ? + (_theResult____h391784[29] ? 6'd27 : - (_theResult____h391783[28] ? + (_theResult____h391784[28] ? 6'd28 : - (_theResult____h391783[27] ? + (_theResult____h391784[27] ? 6'd29 : - (_theResult____h391783[26] ? + (_theResult____h391784[26] ? 6'd30 : - (_theResult____h391783[25] ? + (_theResult____h391784[25] ? 6'd31 : - (_theResult____h391783[24] ? + (_theResult____h391784[24] ? 6'd32 : - (_theResult____h391783[23] ? + (_theResult____h391784[23] ? 6'd33 : - (_theResult____h391783[22] ? + (_theResult____h391784[22] ? 6'd34 : - (_theResult____h391783[21] ? + (_theResult____h391784[21] ? 6'd35 : - (_theResult____h391783[20] ? + (_theResult____h391784[20] ? 6'd36 : - (_theResult____h391783[19] ? + (_theResult____h391784[19] ? 6'd37 : - (_theResult____h391783[18] ? + (_theResult____h391784[18] ? 6'd38 : - (_theResult____h391783[17] ? + (_theResult____h391784[17] ? 6'd39 : - (_theResult____h391783[16] ? + (_theResult____h391784[16] ? 6'd40 : - (_theResult____h391783[15] ? + (_theResult____h391784[15] ? 6'd41 : - (_theResult____h391783[14] ? + (_theResult____h391784[14] ? 6'd42 : - (_theResult____h391783[13] ? + (_theResult____h391784[13] ? 6'd43 : - (_theResult____h391783[12] ? + (_theResult____h391784[12] ? 6'd44 : - (_theResult____h391783[11] ? + (_theResult____h391784[11] ? 6'd45 : - (_theResult____h391783[10] ? + (_theResult____h391784[10] ? 6'd46 : - (_theResult____h391783[9] ? + (_theResult____h391784[9] ? 6'd47 : - (_theResult____h391783[8] ? + (_theResult____h391784[8] ? 6'd48 : - (_theResult____h391783[7] ? + (_theResult____h391784[7] ? 6'd49 : - (_theResult____h391783[6] ? + (_theResult____h391784[6] ? 6'd50 : - (_theResult____h391783[5] ? + (_theResult____h391784[5] ? 6'd51 : - (_theResult____h391783[4] ? + (_theResult____h391784[4] ? 6'd52 : - (_theResult____h391783[3] ? + (_theResult____h391784[3] ? 6'd53 : - (_theResult____h391783[2] ? + (_theResult____h391784[2] ? 6'd54 : - (_theResult____h391783[1] ? + (_theResult____h391784[1] ? 6'd55 : - (_theResult____h391783[0] ? + (_theResult____h391784[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 = - (_theResult____h437478[56] ? + (_theResult____h437479[56] ? 6'd0 : - (_theResult____h437478[55] ? + (_theResult____h437479[55] ? 6'd1 : - (_theResult____h437478[54] ? + (_theResult____h437479[54] ? 6'd2 : - (_theResult____h437478[53] ? + (_theResult____h437479[53] ? 6'd3 : - (_theResult____h437478[52] ? + (_theResult____h437479[52] ? 6'd4 : - (_theResult____h437478[51] ? + (_theResult____h437479[51] ? 6'd5 : - (_theResult____h437478[50] ? + (_theResult____h437479[50] ? 6'd6 : - (_theResult____h437478[49] ? + (_theResult____h437479[49] ? 6'd7 : - (_theResult____h437478[48] ? + (_theResult____h437479[48] ? 6'd8 : - (_theResult____h437478[47] ? + (_theResult____h437479[47] ? 6'd9 : - (_theResult____h437478[46] ? + (_theResult____h437479[46] ? 6'd10 : - (_theResult____h437478[45] ? + (_theResult____h437479[45] ? 6'd11 : - (_theResult____h437478[44] ? + (_theResult____h437479[44] ? 6'd12 : - (_theResult____h437478[43] ? + (_theResult____h437479[43] ? 6'd13 : - (_theResult____h437478[42] ? + (_theResult____h437479[42] ? 6'd14 : - (_theResult____h437478[41] ? + (_theResult____h437479[41] ? 6'd15 : - (_theResult____h437478[40] ? + (_theResult____h437479[40] ? 6'd16 : - (_theResult____h437478[39] ? + (_theResult____h437479[39] ? 6'd17 : - (_theResult____h437478[38] ? + (_theResult____h437479[38] ? 6'd18 : - (_theResult____h437478[37] ? + (_theResult____h437479[37] ? 6'd19 : - (_theResult____h437478[36] ? + (_theResult____h437479[36] ? 6'd20 : - (_theResult____h437478[35] ? + (_theResult____h437479[35] ? 6'd21 : - (_theResult____h437478[34] ? + (_theResult____h437479[34] ? 6'd22 : - (_theResult____h437478[33] ? + (_theResult____h437479[33] ? 6'd23 : - (_theResult____h437478[32] ? + (_theResult____h437479[32] ? 6'd24 : - (_theResult____h437478[31] ? + (_theResult____h437479[31] ? 6'd25 : - (_theResult____h437478[30] ? + (_theResult____h437479[30] ? 6'd26 : - (_theResult____h437478[29] ? + (_theResult____h437479[29] ? 6'd27 : - (_theResult____h437478[28] ? + (_theResult____h437479[28] ? 6'd28 : - (_theResult____h437478[27] ? + (_theResult____h437479[27] ? 6'd29 : - (_theResult____h437478[26] ? + (_theResult____h437479[26] ? 6'd30 : - (_theResult____h437478[25] ? + (_theResult____h437479[25] ? 6'd31 : - (_theResult____h437478[24] ? + (_theResult____h437479[24] ? 6'd32 : - (_theResult____h437478[23] ? + (_theResult____h437479[23] ? 6'd33 : - (_theResult____h437478[22] ? + (_theResult____h437479[22] ? 6'd34 : - (_theResult____h437478[21] ? + (_theResult____h437479[21] ? 6'd35 : - (_theResult____h437478[20] ? + (_theResult____h437479[20] ? 6'd36 : - (_theResult____h437478[19] ? + (_theResult____h437479[19] ? 6'd37 : - (_theResult____h437478[18] ? + (_theResult____h437479[18] ? 6'd38 : - (_theResult____h437478[17] ? + (_theResult____h437479[17] ? 6'd39 : - (_theResult____h437478[16] ? + (_theResult____h437479[16] ? 6'd40 : - (_theResult____h437478[15] ? + (_theResult____h437479[15] ? 6'd41 : - (_theResult____h437478[14] ? + (_theResult____h437479[14] ? 6'd42 : - (_theResult____h437478[13] ? + (_theResult____h437479[13] ? 6'd43 : - (_theResult____h437478[12] ? + (_theResult____h437479[12] ? 6'd44 : - (_theResult____h437478[11] ? + (_theResult____h437479[11] ? 6'd45 : - (_theResult____h437478[10] ? + (_theResult____h437479[10] ? 6'd46 : - (_theResult____h437478[9] ? + (_theResult____h437479[9] ? 6'd47 : - (_theResult____h437478[8] ? + (_theResult____h437479[8] ? 6'd48 : - (_theResult____h437478[7] ? + (_theResult____h437479[7] ? 6'd49 : - (_theResult____h437478[6] ? + (_theResult____h437479[6] ? 6'd50 : - (_theResult____h437478[5] ? + (_theResult____h437479[5] ? 6'd51 : - (_theResult____h437478[4] ? + (_theResult____h437479[4] ? 6'd52 : - (_theResult____h437478[3] ? + (_theResult____h437479[3] ? 6'd53 : - (_theResult____h437478[2] ? + (_theResult____h437479[2] ? 6'd54 : - (_theResult____h437478[1] ? + (_theResult____h437479[1] ? 6'd55 : - (_theResult____h437478[0] ? + (_theResult____h437479[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 = - (_theResult____h541721[56] ? + (_theResult____h541722[56] ? 6'd0 : - (_theResult____h541721[55] ? + (_theResult____h541722[55] ? 6'd1 : - (_theResult____h541721[54] ? + (_theResult____h541722[54] ? 6'd2 : - (_theResult____h541721[53] ? + (_theResult____h541722[53] ? 6'd3 : - (_theResult____h541721[52] ? + (_theResult____h541722[52] ? 6'd4 : - (_theResult____h541721[51] ? + (_theResult____h541722[51] ? 6'd5 : - (_theResult____h541721[50] ? + (_theResult____h541722[50] ? 6'd6 : - (_theResult____h541721[49] ? + (_theResult____h541722[49] ? 6'd7 : - (_theResult____h541721[48] ? + (_theResult____h541722[48] ? 6'd8 : - (_theResult____h541721[47] ? + (_theResult____h541722[47] ? 6'd9 : - (_theResult____h541721[46] ? + (_theResult____h541722[46] ? 6'd10 : - (_theResult____h541721[45] ? + (_theResult____h541722[45] ? 6'd11 : - (_theResult____h541721[44] ? + (_theResult____h541722[44] ? 6'd12 : - (_theResult____h541721[43] ? + (_theResult____h541722[43] ? 6'd13 : - (_theResult____h541721[42] ? + (_theResult____h541722[42] ? 6'd14 : - (_theResult____h541721[41] ? + (_theResult____h541722[41] ? 6'd15 : - (_theResult____h541721[40] ? + (_theResult____h541722[40] ? 6'd16 : - (_theResult____h541721[39] ? + (_theResult____h541722[39] ? 6'd17 : - (_theResult____h541721[38] ? + (_theResult____h541722[38] ? 6'd18 : - (_theResult____h541721[37] ? + (_theResult____h541722[37] ? 6'd19 : - (_theResult____h541721[36] ? + (_theResult____h541722[36] ? 6'd20 : - (_theResult____h541721[35] ? + (_theResult____h541722[35] ? 6'd21 : - (_theResult____h541721[34] ? + (_theResult____h541722[34] ? 6'd22 : - (_theResult____h541721[33] ? + (_theResult____h541722[33] ? 6'd23 : - (_theResult____h541721[32] ? + (_theResult____h541722[32] ? 6'd24 : - (_theResult____h541721[31] ? + (_theResult____h541722[31] ? 6'd25 : - (_theResult____h541721[30] ? + (_theResult____h541722[30] ? 6'd26 : - (_theResult____h541721[29] ? + (_theResult____h541722[29] ? 6'd27 : - (_theResult____h541721[28] ? + (_theResult____h541722[28] ? 6'd28 : - (_theResult____h541721[27] ? + (_theResult____h541722[27] ? 6'd29 : - (_theResult____h541721[26] ? + (_theResult____h541722[26] ? 6'd30 : - (_theResult____h541721[25] ? + (_theResult____h541722[25] ? 6'd31 : - (_theResult____h541721[24] ? + (_theResult____h541722[24] ? 6'd32 : - (_theResult____h541721[23] ? + (_theResult____h541722[23] ? 6'd33 : - (_theResult____h541721[22] ? + (_theResult____h541722[22] ? 6'd34 : - (_theResult____h541721[21] ? + (_theResult____h541722[21] ? 6'd35 : - (_theResult____h541721[20] ? + (_theResult____h541722[20] ? 6'd36 : - (_theResult____h541721[19] ? + (_theResult____h541722[19] ? 6'd37 : - (_theResult____h541721[18] ? + (_theResult____h541722[18] ? 6'd38 : - (_theResult____h541721[17] ? + (_theResult____h541722[17] ? 6'd39 : - (_theResult____h541721[16] ? + (_theResult____h541722[16] ? 6'd40 : - (_theResult____h541721[15] ? + (_theResult____h541722[15] ? 6'd41 : - (_theResult____h541721[14] ? + (_theResult____h541722[14] ? 6'd42 : - (_theResult____h541721[13] ? + (_theResult____h541722[13] ? 6'd43 : - (_theResult____h541721[12] ? + (_theResult____h541722[12] ? 6'd44 : - (_theResult____h541721[11] ? + (_theResult____h541722[11] ? 6'd45 : - (_theResult____h541721[10] ? + (_theResult____h541722[10] ? 6'd46 : - (_theResult____h541721[9] ? + (_theResult____h541722[9] ? 6'd47 : - (_theResult____h541721[8] ? + (_theResult____h541722[8] ? 6'd48 : - (_theResult____h541721[7] ? + (_theResult____h541722[7] ? 6'd49 : - (_theResult____h541721[6] ? + (_theResult____h541722[6] ? 6'd50 : - (_theResult____h541721[5] ? + (_theResult____h541722[5] ? 6'd51 : - (_theResult____h541721[4] ? + (_theResult____h541722[4] ? 6'd52 : - (_theResult____h541721[3] ? + (_theResult____h541722[3] ? 6'd53 : - (_theResult____h541721[2] ? + (_theResult____h541722[2] ? 6'd54 : - (_theResult____h541721[1] ? + (_theResult____h541722[1] ? 6'd55 : - (_theResult____h541721[0] ? + (_theResult____h541722[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 = - (_theResult____h502868[56] ? + (_theResult____h502869[56] ? 6'd0 : - (_theResult____h502868[55] ? + (_theResult____h502869[55] ? 6'd1 : - (_theResult____h502868[54] ? + (_theResult____h502869[54] ? 6'd2 : - (_theResult____h502868[53] ? + (_theResult____h502869[53] ? 6'd3 : - (_theResult____h502868[52] ? + (_theResult____h502869[52] ? 6'd4 : - (_theResult____h502868[51] ? + (_theResult____h502869[51] ? 6'd5 : - (_theResult____h502868[50] ? + (_theResult____h502869[50] ? 6'd6 : - (_theResult____h502868[49] ? + (_theResult____h502869[49] ? 6'd7 : - (_theResult____h502868[48] ? + (_theResult____h502869[48] ? 6'd8 : - (_theResult____h502868[47] ? + (_theResult____h502869[47] ? 6'd9 : - (_theResult____h502868[46] ? + (_theResult____h502869[46] ? 6'd10 : - (_theResult____h502868[45] ? + (_theResult____h502869[45] ? 6'd11 : - (_theResult____h502868[44] ? + (_theResult____h502869[44] ? 6'd12 : - (_theResult____h502868[43] ? + (_theResult____h502869[43] ? 6'd13 : - (_theResult____h502868[42] ? + (_theResult____h502869[42] ? 6'd14 : - (_theResult____h502868[41] ? + (_theResult____h502869[41] ? 6'd15 : - (_theResult____h502868[40] ? + (_theResult____h502869[40] ? 6'd16 : - (_theResult____h502868[39] ? + (_theResult____h502869[39] ? 6'd17 : - (_theResult____h502868[38] ? + (_theResult____h502869[38] ? 6'd18 : - (_theResult____h502868[37] ? + (_theResult____h502869[37] ? 6'd19 : - (_theResult____h502868[36] ? + (_theResult____h502869[36] ? 6'd20 : - (_theResult____h502868[35] ? + (_theResult____h502869[35] ? 6'd21 : - (_theResult____h502868[34] ? + (_theResult____h502869[34] ? 6'd22 : - (_theResult____h502868[33] ? + (_theResult____h502869[33] ? 6'd23 : - (_theResult____h502868[32] ? + (_theResult____h502869[32] ? 6'd24 : - (_theResult____h502868[31] ? + (_theResult____h502869[31] ? 6'd25 : - (_theResult____h502868[30] ? + (_theResult____h502869[30] ? 6'd26 : - (_theResult____h502868[29] ? + (_theResult____h502869[29] ? 6'd27 : - (_theResult____h502868[28] ? + (_theResult____h502869[28] ? 6'd28 : - (_theResult____h502868[27] ? + (_theResult____h502869[27] ? 6'd29 : - (_theResult____h502868[26] ? + (_theResult____h502869[26] ? 6'd30 : - (_theResult____h502868[25] ? + (_theResult____h502869[25] ? 6'd31 : - (_theResult____h502868[24] ? + (_theResult____h502869[24] ? 6'd32 : - (_theResult____h502868[23] ? + (_theResult____h502869[23] ? 6'd33 : - (_theResult____h502868[22] ? + (_theResult____h502869[22] ? 6'd34 : - (_theResult____h502868[21] ? + (_theResult____h502869[21] ? 6'd35 : - (_theResult____h502868[20] ? + (_theResult____h502869[20] ? 6'd36 : - (_theResult____h502868[19] ? + (_theResult____h502869[19] ? 6'd37 : - (_theResult____h502868[18] ? + (_theResult____h502869[18] ? 6'd38 : - (_theResult____h502868[17] ? + (_theResult____h502869[17] ? 6'd39 : - (_theResult____h502868[16] ? + (_theResult____h502869[16] ? 6'd40 : - (_theResult____h502868[15] ? + (_theResult____h502869[15] ? 6'd41 : - (_theResult____h502868[14] ? + (_theResult____h502869[14] ? 6'd42 : - (_theResult____h502868[13] ? + (_theResult____h502869[13] ? 6'd43 : - (_theResult____h502868[12] ? + (_theResult____h502869[12] ? 6'd44 : - (_theResult____h502868[11] ? + (_theResult____h502869[11] ? 6'd45 : - (_theResult____h502868[10] ? + (_theResult____h502869[10] ? 6'd46 : - (_theResult____h502868[9] ? + (_theResult____h502869[9] ? 6'd47 : - (_theResult____h502868[8] ? + (_theResult____h502869[8] ? 6'd48 : - (_theResult____h502868[7] ? + (_theResult____h502869[7] ? 6'd49 : - (_theResult____h502868[6] ? + (_theResult____h502869[6] ? 6'd50 : - (_theResult____h502868[5] ? + (_theResult____h502869[5] ? 6'd51 : - (_theResult____h502868[4] ? + (_theResult____h502869[4] ? 6'd52 : - (_theResult____h502868[3] ? + (_theResult____h502869[3] ? 6'd53 : - (_theResult____h502868[2] ? + (_theResult____h502869[2] ? 6'd54 : - (_theResult____h502868[1] ? + (_theResult____h502869[1] ? 6'd55 : - (_theResult____h502868[0] ? + (_theResult____h502869[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 = - (_theResult____h581025[56] ? + (_theResult____h581026[56] ? 6'd0 : - (_theResult____h581025[55] ? + (_theResult____h581026[55] ? 6'd1 : - (_theResult____h581025[54] ? + (_theResult____h581026[54] ? 6'd2 : - (_theResult____h581025[53] ? + (_theResult____h581026[53] ? 6'd3 : - (_theResult____h581025[52] ? + (_theResult____h581026[52] ? 6'd4 : - (_theResult____h581025[51] ? + (_theResult____h581026[51] ? 6'd5 : - (_theResult____h581025[50] ? + (_theResult____h581026[50] ? 6'd6 : - (_theResult____h581025[49] ? + (_theResult____h581026[49] ? 6'd7 : - (_theResult____h581025[48] ? + (_theResult____h581026[48] ? 6'd8 : - (_theResult____h581025[47] ? + (_theResult____h581026[47] ? 6'd9 : - (_theResult____h581025[46] ? + (_theResult____h581026[46] ? 6'd10 : - (_theResult____h581025[45] ? + (_theResult____h581026[45] ? 6'd11 : - (_theResult____h581025[44] ? + (_theResult____h581026[44] ? 6'd12 : - (_theResult____h581025[43] ? + (_theResult____h581026[43] ? 6'd13 : - (_theResult____h581025[42] ? + (_theResult____h581026[42] ? 6'd14 : - (_theResult____h581025[41] ? + (_theResult____h581026[41] ? 6'd15 : - (_theResult____h581025[40] ? + (_theResult____h581026[40] ? 6'd16 : - (_theResult____h581025[39] ? + (_theResult____h581026[39] ? 6'd17 : - (_theResult____h581025[38] ? + (_theResult____h581026[38] ? 6'd18 : - (_theResult____h581025[37] ? + (_theResult____h581026[37] ? 6'd19 : - (_theResult____h581025[36] ? + (_theResult____h581026[36] ? 6'd20 : - (_theResult____h581025[35] ? + (_theResult____h581026[35] ? 6'd21 : - (_theResult____h581025[34] ? + (_theResult____h581026[34] ? 6'd22 : - (_theResult____h581025[33] ? + (_theResult____h581026[33] ? 6'd23 : - (_theResult____h581025[32] ? + (_theResult____h581026[32] ? 6'd24 : - (_theResult____h581025[31] ? + (_theResult____h581026[31] ? 6'd25 : - (_theResult____h581025[30] ? + (_theResult____h581026[30] ? 6'd26 : - (_theResult____h581025[29] ? + (_theResult____h581026[29] ? 6'd27 : - (_theResult____h581025[28] ? + (_theResult____h581026[28] ? 6'd28 : - (_theResult____h581025[27] ? + (_theResult____h581026[27] ? 6'd29 : - (_theResult____h581025[26] ? + (_theResult____h581026[26] ? 6'd30 : - (_theResult____h581025[25] ? + (_theResult____h581026[25] ? 6'd31 : - (_theResult____h581025[24] ? + (_theResult____h581026[24] ? 6'd32 : - (_theResult____h581025[23] ? + (_theResult____h581026[23] ? 6'd33 : - (_theResult____h581025[22] ? + (_theResult____h581026[22] ? 6'd34 : - (_theResult____h581025[21] ? + (_theResult____h581026[21] ? 6'd35 : - (_theResult____h581025[20] ? + (_theResult____h581026[20] ? 6'd36 : - (_theResult____h581025[19] ? + (_theResult____h581026[19] ? 6'd37 : - (_theResult____h581025[18] ? + (_theResult____h581026[18] ? 6'd38 : - (_theResult____h581025[17] ? + (_theResult____h581026[17] ? 6'd39 : - (_theResult____h581025[16] ? + (_theResult____h581026[16] ? 6'd40 : - (_theResult____h581025[15] ? + (_theResult____h581026[15] ? 6'd41 : - (_theResult____h581025[14] ? + (_theResult____h581026[14] ? 6'd42 : - (_theResult____h581025[13] ? + (_theResult____h581026[13] ? 6'd43 : - (_theResult____h581025[12] ? + (_theResult____h581026[12] ? 6'd44 : - (_theResult____h581025[11] ? + (_theResult____h581026[11] ? 6'd45 : - (_theResult____h581025[10] ? + (_theResult____h581026[10] ? 6'd46 : - (_theResult____h581025[9] ? + (_theResult____h581026[9] ? 6'd47 : - (_theResult____h581025[8] ? + (_theResult____h581026[8] ? 6'd48 : - (_theResult____h581025[7] ? + (_theResult____h581026[7] ? 6'd49 : - (_theResult____h581025[6] ? + (_theResult____h581026[6] ? 6'd50 : - (_theResult____h581025[5] ? + (_theResult____h581026[5] ? 6'd51 : - (_theResult____h581025[4] ? + (_theResult____h581026[4] ? 6'd52 : - (_theResult____h581025[3] ? + (_theResult____h581026[3] ? 6'd53 : - (_theResult____h581025[2] ? + (_theResult____h581026[2] ? 6'd54 : - (_theResult____h581025[1] ? + (_theResult____h581026[1] ? 6'd55 : - (_theResult____h581025[0] ? + (_theResult____h581026[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 = - (_theResult____h363723[56] ? + (_theResult____h363724[56] ? 6'd0 : - (_theResult____h363723[55] ? + (_theResult____h363724[55] ? 6'd1 : - (_theResult____h363723[54] ? + (_theResult____h363724[54] ? 6'd2 : - (_theResult____h363723[53] ? + (_theResult____h363724[53] ? 6'd3 : - (_theResult____h363723[52] ? + (_theResult____h363724[52] ? 6'd4 : - (_theResult____h363723[51] ? + (_theResult____h363724[51] ? 6'd5 : - (_theResult____h363723[50] ? + (_theResult____h363724[50] ? 6'd6 : - (_theResult____h363723[49] ? + (_theResult____h363724[49] ? 6'd7 : - (_theResult____h363723[48] ? + (_theResult____h363724[48] ? 6'd8 : - (_theResult____h363723[47] ? + (_theResult____h363724[47] ? 6'd9 : - (_theResult____h363723[46] ? + (_theResult____h363724[46] ? 6'd10 : - (_theResult____h363723[45] ? + (_theResult____h363724[45] ? 6'd11 : - (_theResult____h363723[44] ? + (_theResult____h363724[44] ? 6'd12 : - (_theResult____h363723[43] ? + (_theResult____h363724[43] ? 6'd13 : - (_theResult____h363723[42] ? + (_theResult____h363724[42] ? 6'd14 : - (_theResult____h363723[41] ? + (_theResult____h363724[41] ? 6'd15 : - (_theResult____h363723[40] ? + (_theResult____h363724[40] ? 6'd16 : - (_theResult____h363723[39] ? + (_theResult____h363724[39] ? 6'd17 : - (_theResult____h363723[38] ? + (_theResult____h363724[38] ? 6'd18 : - (_theResult____h363723[37] ? + (_theResult____h363724[37] ? 6'd19 : - (_theResult____h363723[36] ? + (_theResult____h363724[36] ? 6'd20 : - (_theResult____h363723[35] ? + (_theResult____h363724[35] ? 6'd21 : - (_theResult____h363723[34] ? + (_theResult____h363724[34] ? 6'd22 : - (_theResult____h363723[33] ? + (_theResult____h363724[33] ? 6'd23 : - (_theResult____h363723[32] ? + (_theResult____h363724[32] ? 6'd24 : - (_theResult____h363723[31] ? + (_theResult____h363724[31] ? 6'd25 : - (_theResult____h363723[30] ? + (_theResult____h363724[30] ? 6'd26 : - (_theResult____h363723[29] ? + (_theResult____h363724[29] ? 6'd27 : - (_theResult____h363723[28] ? + (_theResult____h363724[28] ? 6'd28 : - (_theResult____h363723[27] ? + (_theResult____h363724[27] ? 6'd29 : - (_theResult____h363723[26] ? + (_theResult____h363724[26] ? 6'd30 : - (_theResult____h363723[25] ? + (_theResult____h363724[25] ? 6'd31 : - (_theResult____h363723[24] ? + (_theResult____h363724[24] ? 6'd32 : - (_theResult____h363723[23] ? + (_theResult____h363724[23] ? 6'd33 : - (_theResult____h363723[22] ? + (_theResult____h363724[22] ? 6'd34 : - (_theResult____h363723[21] ? + (_theResult____h363724[21] ? 6'd35 : - (_theResult____h363723[20] ? + (_theResult____h363724[20] ? 6'd36 : - (_theResult____h363723[19] ? + (_theResult____h363724[19] ? 6'd37 : - (_theResult____h363723[18] ? + (_theResult____h363724[18] ? 6'd38 : - (_theResult____h363723[17] ? + (_theResult____h363724[17] ? 6'd39 : - (_theResult____h363723[16] ? + (_theResult____h363724[16] ? 6'd40 : - (_theResult____h363723[15] ? + (_theResult____h363724[15] ? 6'd41 : - (_theResult____h363723[14] ? + (_theResult____h363724[14] ? 6'd42 : - (_theResult____h363723[13] ? + (_theResult____h363724[13] ? 6'd43 : - (_theResult____h363723[12] ? + (_theResult____h363724[12] ? 6'd44 : - (_theResult____h363723[11] ? + (_theResult____h363724[11] ? 6'd45 : - (_theResult____h363723[10] ? + (_theResult____h363724[10] ? 6'd46 : - (_theResult____h363723[9] ? + (_theResult____h363724[9] ? 6'd47 : - (_theResult____h363723[8] ? + (_theResult____h363724[8] ? 6'd48 : - (_theResult____h363723[7] ? + (_theResult____h363724[7] ? 6'd49 : - (_theResult____h363723[6] ? + (_theResult____h363724[6] ? 6'd50 : - (_theResult____h363723[5] ? + (_theResult____h363724[5] ? 6'd51 : - (_theResult____h363723[4] ? + (_theResult____h363724[4] ? 6'd52 : - (_theResult____h363723[3] ? + (_theResult____h363724[3] ? 6'd53 : - (_theResult____h363723[2] ? + (_theResult____h363724[2] ? 6'd54 : - (_theResult____h363723[1] ? + (_theResult____h363724[1] ? 6'd55 : - (_theResult____h363723[0] ? + (_theResult____h363724[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 = - (_theResult____h409420[56] ? + (_theResult____h409421[56] ? 6'd0 : - (_theResult____h409420[55] ? + (_theResult____h409421[55] ? 6'd1 : - (_theResult____h409420[54] ? + (_theResult____h409421[54] ? 6'd2 : - (_theResult____h409420[53] ? + (_theResult____h409421[53] ? 6'd3 : - (_theResult____h409420[52] ? + (_theResult____h409421[52] ? 6'd4 : - (_theResult____h409420[51] ? + (_theResult____h409421[51] ? 6'd5 : - (_theResult____h409420[50] ? + (_theResult____h409421[50] ? 6'd6 : - (_theResult____h409420[49] ? + (_theResult____h409421[49] ? 6'd7 : - (_theResult____h409420[48] ? + (_theResult____h409421[48] ? 6'd8 : - (_theResult____h409420[47] ? + (_theResult____h409421[47] ? 6'd9 : - (_theResult____h409420[46] ? + (_theResult____h409421[46] ? 6'd10 : - (_theResult____h409420[45] ? + (_theResult____h409421[45] ? 6'd11 : - (_theResult____h409420[44] ? + (_theResult____h409421[44] ? 6'd12 : - (_theResult____h409420[43] ? + (_theResult____h409421[43] ? 6'd13 : - (_theResult____h409420[42] ? + (_theResult____h409421[42] ? 6'd14 : - (_theResult____h409420[41] ? + (_theResult____h409421[41] ? 6'd15 : - (_theResult____h409420[40] ? + (_theResult____h409421[40] ? 6'd16 : - (_theResult____h409420[39] ? + (_theResult____h409421[39] ? 6'd17 : - (_theResult____h409420[38] ? + (_theResult____h409421[38] ? 6'd18 : - (_theResult____h409420[37] ? + (_theResult____h409421[37] ? 6'd19 : - (_theResult____h409420[36] ? + (_theResult____h409421[36] ? 6'd20 : - (_theResult____h409420[35] ? + (_theResult____h409421[35] ? 6'd21 : - (_theResult____h409420[34] ? + (_theResult____h409421[34] ? 6'd22 : - (_theResult____h409420[33] ? + (_theResult____h409421[33] ? 6'd23 : - (_theResult____h409420[32] ? + (_theResult____h409421[32] ? 6'd24 : - (_theResult____h409420[31] ? + (_theResult____h409421[31] ? 6'd25 : - (_theResult____h409420[30] ? + (_theResult____h409421[30] ? 6'd26 : - (_theResult____h409420[29] ? + (_theResult____h409421[29] ? 6'd27 : - (_theResult____h409420[28] ? + (_theResult____h409421[28] ? 6'd28 : - (_theResult____h409420[27] ? + (_theResult____h409421[27] ? 6'd29 : - (_theResult____h409420[26] ? + (_theResult____h409421[26] ? 6'd30 : - (_theResult____h409420[25] ? + (_theResult____h409421[25] ? 6'd31 : - (_theResult____h409420[24] ? + (_theResult____h409421[24] ? 6'd32 : - (_theResult____h409420[23] ? + (_theResult____h409421[23] ? 6'd33 : - (_theResult____h409420[22] ? + (_theResult____h409421[22] ? 6'd34 : - (_theResult____h409420[21] ? + (_theResult____h409421[21] ? 6'd35 : - (_theResult____h409420[20] ? + (_theResult____h409421[20] ? 6'd36 : - (_theResult____h409420[19] ? + (_theResult____h409421[19] ? 6'd37 : - (_theResult____h409420[18] ? + (_theResult____h409421[18] ? 6'd38 : - (_theResult____h409420[17] ? + (_theResult____h409421[17] ? 6'd39 : - (_theResult____h409420[16] ? + (_theResult____h409421[16] ? 6'd40 : - (_theResult____h409420[15] ? + (_theResult____h409421[15] ? 6'd41 : - (_theResult____h409420[14] ? + (_theResult____h409421[14] ? 6'd42 : - (_theResult____h409420[13] ? + (_theResult____h409421[13] ? 6'd43 : - (_theResult____h409420[12] ? + (_theResult____h409421[12] ? 6'd44 : - (_theResult____h409420[11] ? + (_theResult____h409421[11] ? 6'd45 : - (_theResult____h409420[10] ? + (_theResult____h409421[10] ? 6'd46 : - (_theResult____h409420[9] ? + (_theResult____h409421[9] ? 6'd47 : - (_theResult____h409420[8] ? + (_theResult____h409421[8] ? 6'd48 : - (_theResult____h409420[7] ? + (_theResult____h409421[7] ? 6'd49 : - (_theResult____h409420[6] ? + (_theResult____h409421[6] ? 6'd50 : - (_theResult____h409420[5] ? + (_theResult____h409421[5] ? 6'd51 : - (_theResult____h409420[4] ? + (_theResult____h409421[4] ? 6'd52 : - (_theResult____h409420[3] ? + (_theResult____h409421[3] ? 6'd53 : - (_theResult____h409420[2] ? + (_theResult____h409421[2] ? 6'd54 : - (_theResult____h409420[1] ? + (_theResult____h409421[1] ? 6'd55 : - (_theResult____h409420[0] ? + (_theResult____h409421[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 = - (_theResult____h455115[56] ? + (_theResult____h455116[56] ? 6'd0 : - (_theResult____h455115[55] ? + (_theResult____h455116[55] ? 6'd1 : - (_theResult____h455115[54] ? + (_theResult____h455116[54] ? 6'd2 : - (_theResult____h455115[53] ? + (_theResult____h455116[53] ? 6'd3 : - (_theResult____h455115[52] ? + (_theResult____h455116[52] ? 6'd4 : - (_theResult____h455115[51] ? + (_theResult____h455116[51] ? 6'd5 : - (_theResult____h455115[50] ? + (_theResult____h455116[50] ? 6'd6 : - (_theResult____h455115[49] ? + (_theResult____h455116[49] ? 6'd7 : - (_theResult____h455115[48] ? + (_theResult____h455116[48] ? 6'd8 : - (_theResult____h455115[47] ? + (_theResult____h455116[47] ? 6'd9 : - (_theResult____h455115[46] ? + (_theResult____h455116[46] ? 6'd10 : - (_theResult____h455115[45] ? + (_theResult____h455116[45] ? 6'd11 : - (_theResult____h455115[44] ? + (_theResult____h455116[44] ? 6'd12 : - (_theResult____h455115[43] ? + (_theResult____h455116[43] ? 6'd13 : - (_theResult____h455115[42] ? + (_theResult____h455116[42] ? 6'd14 : - (_theResult____h455115[41] ? + (_theResult____h455116[41] ? 6'd15 : - (_theResult____h455115[40] ? + (_theResult____h455116[40] ? 6'd16 : - (_theResult____h455115[39] ? + (_theResult____h455116[39] ? 6'd17 : - (_theResult____h455115[38] ? + (_theResult____h455116[38] ? 6'd18 : - (_theResult____h455115[37] ? + (_theResult____h455116[37] ? 6'd19 : - (_theResult____h455115[36] ? + (_theResult____h455116[36] ? 6'd20 : - (_theResult____h455115[35] ? + (_theResult____h455116[35] ? 6'd21 : - (_theResult____h455115[34] ? + (_theResult____h455116[34] ? 6'd22 : - (_theResult____h455115[33] ? + (_theResult____h455116[33] ? 6'd23 : - (_theResult____h455115[32] ? + (_theResult____h455116[32] ? 6'd24 : - (_theResult____h455115[31] ? + (_theResult____h455116[31] ? 6'd25 : - (_theResult____h455115[30] ? + (_theResult____h455116[30] ? 6'd26 : - (_theResult____h455115[29] ? + (_theResult____h455116[29] ? 6'd27 : - (_theResult____h455115[28] ? + (_theResult____h455116[28] ? 6'd28 : - (_theResult____h455115[27] ? + (_theResult____h455116[27] ? 6'd29 : - (_theResult____h455115[26] ? + (_theResult____h455116[26] ? 6'd30 : - (_theResult____h455115[25] ? + (_theResult____h455116[25] ? 6'd31 : - (_theResult____h455115[24] ? + (_theResult____h455116[24] ? 6'd32 : - (_theResult____h455115[23] ? + (_theResult____h455116[23] ? 6'd33 : - (_theResult____h455115[22] ? + (_theResult____h455116[22] ? 6'd34 : - (_theResult____h455115[21] ? + (_theResult____h455116[21] ? 6'd35 : - (_theResult____h455115[20] ? + (_theResult____h455116[20] ? 6'd36 : - (_theResult____h455115[19] ? + (_theResult____h455116[19] ? 6'd37 : - (_theResult____h455115[18] ? + (_theResult____h455116[18] ? 6'd38 : - (_theResult____h455115[17] ? + (_theResult____h455116[17] ? 6'd39 : - (_theResult____h455115[16] ? + (_theResult____h455116[16] ? 6'd40 : - (_theResult____h455115[15] ? + (_theResult____h455116[15] ? 6'd41 : - (_theResult____h455115[14] ? + (_theResult____h455116[14] ? 6'd42 : - (_theResult____h455115[13] ? + (_theResult____h455116[13] ? 6'd43 : - (_theResult____h455115[12] ? + (_theResult____h455116[12] ? 6'd44 : - (_theResult____h455115[11] ? + (_theResult____h455116[11] ? 6'd45 : - (_theResult____h455115[10] ? + (_theResult____h455116[10] ? 6'd46 : - (_theResult____h455115[9] ? + (_theResult____h455116[9] ? 6'd47 : - (_theResult____h455115[8] ? + (_theResult____h455116[8] ? 6'd48 : - (_theResult____h455115[7] ? + (_theResult____h455116[7] ? 6'd49 : - (_theResult____h455115[6] ? + (_theResult____h455116[6] ? 6'd50 : - (_theResult____h455115[5] ? + (_theResult____h455116[5] ? 6'd51 : - (_theResult____h455115[4] ? + (_theResult____h455116[4] ? 6'd52 : - (_theResult____h455115[3] ? + (_theResult____h455116[3] ? 6'd53 : - (_theResult____h455115[2] ? + (_theResult____h455116[2] ? 6'd54 : - (_theResult____h455115[1] ? + (_theResult____h455116[1] ? 6'd55 : - (_theResult____h455115[0] ? + (_theResult____h455116[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 = - (_theResult___fst_exp__h549957 == 11'd2047) ? + (_theResult___fst_exp__h549958 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20889,10 +20908,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = - (_theResult___fst_exp__h549957 == 11'd2047) ? + (_theResult___fst_exp__h549958 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20900,10 +20919,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 = - (_theResult___fst_exp__h511104 == 11'd2047) ? + (_theResult___fst_exp__h511105 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20911,10 +20930,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 = - (_theResult___fst_exp__h589261 == 11'd2047) ? + (_theResult___fst_exp__h589262 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20922,10 +20941,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = - (_theResult___fst_exp__h589261 == 11'd2047) ? + (_theResult___fst_exp__h589262 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20933,538 +20952,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 = - (guard__h346094 == 2'b0 || + (guard__h346095 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h354195 : - _theResult___exp__h354711 ; + _theResult___fst_exp__h354196 : + _theResult___exp__h354712 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 = - (guard__h346094 == 2'b0) ? - _theResult___fst_exp__h354195 : + (guard__h346095 == 2'b0) ? + _theResult___fst_exp__h354196 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h354711 : - _theResult___fst_exp__h354195) ; + _theResult___exp__h354712 : + _theResult___fst_exp__h354196) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 = - (guard__h346094 == 2'b0 || + (guard__h346095 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h354189[56:34] : - _theResult___sfd__h354712 ; + sfdin__h354190[56:34] : + _theResult___sfd__h354713 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 = - (guard__h346094 == 2'b0) ? - sfdin__h354189[56:34] : + (guard__h346095 == 2'b0) ? + sfdin__h354190[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h354712 : - sfdin__h354189[56:34]) ; + _theResult___sfd__h354713 : + sfdin__h354190[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 = - (guard__h391793 == 2'b0 || + (guard__h391794 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h399892 : - _theResult___exp__h400408 ; + _theResult___fst_exp__h399893 : + _theResult___exp__h400409 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 = - (guard__h391793 == 2'b0) ? - _theResult___fst_exp__h399892 : + (guard__h391794 == 2'b0) ? + _theResult___fst_exp__h399893 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h400408 : - _theResult___fst_exp__h399892) ; + _theResult___exp__h400409 : + _theResult___fst_exp__h399893) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 = - (guard__h391793 == 2'b0 || + (guard__h391794 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h399886[56:34] : - _theResult___sfd__h400409 ; + sfdin__h399887[56:34] : + _theResult___sfd__h400410 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 = - (guard__h391793 == 2'b0) ? - sfdin__h399886[56:34] : + (guard__h391794 == 2'b0) ? + sfdin__h399887[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h400409 : - sfdin__h399886[56:34]) ; + _theResult___sfd__h400410 : + sfdin__h399887[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 = - (guard__h437488 == 2'b0 || + (guard__h437489 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h445587 : - _theResult___exp__h446103 ; + _theResult___fst_exp__h445588 : + _theResult___exp__h446104 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 = - (guard__h437488 == 2'b0) ? - _theResult___fst_exp__h445587 : + (guard__h437489 == 2'b0) ? + _theResult___fst_exp__h445588 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h446103 : - _theResult___fst_exp__h445587) ; + _theResult___exp__h446104 : + _theResult___fst_exp__h445588) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 = - (guard__h437488 == 2'b0 || + (guard__h437489 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h445581[56:34] : - _theResult___sfd__h446104 ; + sfdin__h445582[56:34] : + _theResult___sfd__h446105 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 = - (guard__h437488 == 2'b0) ? - sfdin__h445581[56:34] : + (guard__h437489 == 2'b0) ? + sfdin__h445582[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h446104 : - sfdin__h445581[56:34]) ; + _theResult___sfd__h446105 : + sfdin__h445582[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 = - (guard__h541731 == 2'b0 || + (guard__h541732 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h549957 : - _theResult___exp__h550686 ; + _theResult___fst_exp__h549958 : + _theResult___exp__h550687 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 = - (guard__h541731 == 2'b0) ? - _theResult___fst_exp__h549957 : + (guard__h541732 == 2'b0) ? + _theResult___fst_exp__h549958 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h550686 : - _theResult___fst_exp__h549957) ; + _theResult___exp__h550687 : + _theResult___fst_exp__h549958) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 = - (guard__h541731 == 2'b0 || + (guard__h541732 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h549951[56:5] : - _theResult___sfd__h550687 ; + sfdin__h549952[56:5] : + _theResult___sfd__h550688 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 = - (guard__h541731 == 2'b0) ? - sfdin__h549951[56:5] : + (guard__h541732 == 2'b0) ? + sfdin__h549952[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h550687 : - sfdin__h549951[56:5]) ; + _theResult___sfd__h550688 : + sfdin__h549952[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 = - (guard__h502878 == 2'b0 || + (guard__h502879 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h511104 : - _theResult___exp__h511833 ; + _theResult___fst_exp__h511105 : + _theResult___exp__h511834 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 = - (guard__h502878 == 2'b0) ? - _theResult___fst_exp__h511104 : + (guard__h502879 == 2'b0) ? + _theResult___fst_exp__h511105 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h511833 : - _theResult___fst_exp__h511104) ; + _theResult___exp__h511834 : + _theResult___fst_exp__h511105) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 = - (guard__h502878 == 2'b0 || + (guard__h502879 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h511098[56:5] : - _theResult___sfd__h511834 ; + sfdin__h511099[56:5] : + _theResult___sfd__h511835 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 = - (guard__h502878 == 2'b0) ? - sfdin__h511098[56:5] : + (guard__h502879 == 2'b0) ? + sfdin__h511099[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h511834 : - sfdin__h511098[56:5]) ; + _theResult___sfd__h511835 : + sfdin__h511099[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 = - (guard__h581035 == 2'b0 || + (guard__h581036 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h589261 : - _theResult___exp__h589990 ; + _theResult___fst_exp__h589262 : + _theResult___exp__h589991 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 = - (guard__h581035 == 2'b0) ? - _theResult___fst_exp__h589261 : + (guard__h581036 == 2'b0) ? + _theResult___fst_exp__h589262 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h589990 : - _theResult___fst_exp__h589261) ; + _theResult___exp__h589991 : + _theResult___fst_exp__h589262) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 = - (guard__h581035 == 2'b0 || + (guard__h581036 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h589255[56:5] : - _theResult___sfd__h589991 ; + sfdin__h589256[56:5] : + _theResult___sfd__h589992 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 = - (guard__h581035 == 2'b0) ? - sfdin__h589255[56:5] : + (guard__h581036 == 2'b0) ? + sfdin__h589256[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h589991 : - sfdin__h589255[56:5]) ; + _theResult___sfd__h589992 : + sfdin__h589256[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 = - (guard__h363733 == 2'b0 || + (guard__h363734 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h371961 : - _theResult___exp__h372477 ; + _theResult___fst_exp__h371962 : + _theResult___exp__h372478 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 = - (guard__h363733 == 2'b0) ? - _theResult___fst_exp__h371961 : + (guard__h363734 == 2'b0) ? + _theResult___fst_exp__h371962 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h372477 : - _theResult___fst_exp__h371961) ; + _theResult___exp__h372478 : + _theResult___fst_exp__h371962) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 = - (guard__h363733 == 2'b0 || + (guard__h363734 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h371955[56:34] : - _theResult___sfd__h372478 ; + sfdin__h371956[56:34] : + _theResult___sfd__h372479 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 = - (guard__h363733 == 2'b0) ? - sfdin__h371955[56:34] : + (guard__h363734 == 2'b0) ? + sfdin__h371956[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h372478 : - sfdin__h371955[56:34]) ; + _theResult___sfd__h372479 : + sfdin__h371956[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 = - (guard__h409430 == 2'b0 || + (guard__h409431 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h417658 : - _theResult___exp__h418174 ; + _theResult___fst_exp__h417659 : + _theResult___exp__h418175 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 = - (guard__h409430 == 2'b0) ? - _theResult___fst_exp__h417658 : + (guard__h409431 == 2'b0) ? + _theResult___fst_exp__h417659 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h418174 : - _theResult___fst_exp__h417658) ; + _theResult___exp__h418175 : + _theResult___fst_exp__h417659) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 = - (guard__h409430 == 2'b0 || + (guard__h409431 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h417652[56:34] : - _theResult___sfd__h418175 ; + sfdin__h417653[56:34] : + _theResult___sfd__h418176 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 = - (guard__h409430 == 2'b0) ? - sfdin__h417652[56:34] : + (guard__h409431 == 2'b0) ? + sfdin__h417653[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h418175 : - sfdin__h417652[56:34]) ; + _theResult___sfd__h418176 : + sfdin__h417653[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 = - (guard__h455125 == 2'b0 || + (guard__h455126 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h463353 : - _theResult___exp__h463869 ; + _theResult___fst_exp__h463354 : + _theResult___exp__h463870 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 = - (guard__h455125 == 2'b0) ? - _theResult___fst_exp__h463353 : + (guard__h455126 == 2'b0) ? + _theResult___fst_exp__h463354 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h463869 : - _theResult___fst_exp__h463353) ; + _theResult___exp__h463870 : + _theResult___fst_exp__h463354) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 = - (guard__h455125 == 2'b0 || + (guard__h455126 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h463347[56:34] : - _theResult___sfd__h463870 ; + sfdin__h463348[56:34] : + _theResult___sfd__h463871 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 = - (guard__h455125 == 2'b0) ? - sfdin__h463347[56:34] : + (guard__h455126 == 2'b0) ? + sfdin__h463348[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h463870 : - sfdin__h463347[56:34]) ; + _theResult___sfd__h463871 : + sfdin__h463348[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 = - (guard__h532419 == 2'b0 || + (guard__h532420 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h540380 : - _theResult___exp__h541035 ; + _theResult___fst_exp__h540381 : + _theResult___exp__h541036 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 = - (guard__h532419 == 2'b0) ? - _theResult___fst_exp__h540380 : + (guard__h532420 == 2'b0) ? + _theResult___fst_exp__h540381 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h541035 : - _theResult___fst_exp__h540380) ; + _theResult___exp__h541036 : + _theResult___fst_exp__h540381) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 = - (guard__h550800 == 2'b0 || + (guard__h550801 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h558790 : - _theResult___exp__h559470 ; + _theResult___fst_exp__h558791 : + _theResult___exp__h559471 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 = - (guard__h550800 == 2'b0) ? - _theResult___fst_exp__h558790 : + (guard__h550801 == 2'b0) ? + _theResult___fst_exp__h558791 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h559470 : - _theResult___fst_exp__h558790) ; + _theResult___exp__h559471 : + _theResult___fst_exp__h558791) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 = - (guard__h532419 == 2'b0 || + (guard__h532420 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h540331[56:5] : - _theResult___sfd__h541036 ; + _theResult___snd__h540332[56:5] : + _theResult___sfd__h541037 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 = - (guard__h532419 == 2'b0) ? - _theResult___snd__h540331[56:5] : + (guard__h532420 == 2'b0) ? + _theResult___snd__h540332[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h541036 : - _theResult___snd__h540331[56:5]) ; + _theResult___sfd__h541037 : + _theResult___snd__h540332[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 = - (guard__h550800 == 2'b0 || + (guard__h550801 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h558736[56:5] : - _theResult___sfd__h559471 ; + _theResult___snd__h558737[56:5] : + _theResult___sfd__h559472 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 = - (guard__h550800 == 2'b0) ? - _theResult___snd__h558736[56:5] : + (guard__h550801 == 2'b0) ? + _theResult___snd__h558737[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h559471 : - _theResult___snd__h558736[56:5]) ; + _theResult___sfd__h559472 : + _theResult___snd__h558737[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 = - (guard__h493566 == 2'b0 || + (guard__h493567 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h501527 : - _theResult___exp__h502182 ; + _theResult___fst_exp__h501528 : + _theResult___exp__h502183 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 = - (guard__h493566 == 2'b0) ? - _theResult___fst_exp__h501527 : + (guard__h493567 == 2'b0) ? + _theResult___fst_exp__h501528 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h502182 : - _theResult___fst_exp__h501527) ; + _theResult___exp__h502183 : + _theResult___fst_exp__h501528) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 = - (guard__h511947 == 2'b0 || + (guard__h511948 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h519937 : - _theResult___exp__h520617 ; + _theResult___fst_exp__h519938 : + _theResult___exp__h520618 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 = - (guard__h511947 == 2'b0) ? - _theResult___fst_exp__h519937 : + (guard__h511948 == 2'b0) ? + _theResult___fst_exp__h519938 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h520617 : - _theResult___fst_exp__h519937) ; + _theResult___exp__h520618 : + _theResult___fst_exp__h519938) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 = - (guard__h493566 == 2'b0 || + (guard__h493567 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h501478[56:5] : - _theResult___sfd__h502183 ; + _theResult___snd__h501479[56:5] : + _theResult___sfd__h502184 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 = - (guard__h493566 == 2'b0) ? - _theResult___snd__h501478[56:5] : + (guard__h493567 == 2'b0) ? + _theResult___snd__h501479[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h502183 : - _theResult___snd__h501478[56:5]) ; + _theResult___sfd__h502184 : + _theResult___snd__h501479[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 = - (guard__h511947 == 2'b0 || + (guard__h511948 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h519883[56:5] : - _theResult___sfd__h520618 ; + _theResult___snd__h519884[56:5] : + _theResult___sfd__h520619 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 = - (guard__h511947 == 2'b0) ? - _theResult___snd__h519883[56:5] : + (guard__h511948 == 2'b0) ? + _theResult___snd__h519884[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h520618 : - _theResult___snd__h519883[56:5]) ; + _theResult___sfd__h520619 : + _theResult___snd__h519884[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 = - (guard__h571723 == 2'b0 || + (guard__h571724 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h579684 : - _theResult___exp__h580339 ; + _theResult___fst_exp__h579685 : + _theResult___exp__h580340 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 = - (guard__h571723 == 2'b0) ? - _theResult___fst_exp__h579684 : + (guard__h571724 == 2'b0) ? + _theResult___fst_exp__h579685 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h580339 : - _theResult___fst_exp__h579684) ; + _theResult___exp__h580340 : + _theResult___fst_exp__h579685) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 = - (guard__h590104 == 2'b0 || + (guard__h590105 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h598094 : - _theResult___exp__h598774 ; + _theResult___fst_exp__h598095 : + _theResult___exp__h598775 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 = - (guard__h590104 == 2'b0) ? - _theResult___fst_exp__h598094 : + (guard__h590105 == 2'b0) ? + _theResult___fst_exp__h598095 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h598774 : - _theResult___fst_exp__h598094) ; + _theResult___exp__h598775 : + _theResult___fst_exp__h598095) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 = - (guard__h571723 == 2'b0 || + (guard__h571724 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h579635[56:5] : - _theResult___sfd__h580340 ; + _theResult___snd__h579636[56:5] : + _theResult___sfd__h580341 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 = - (guard__h571723 == 2'b0) ? - _theResult___snd__h579635[56:5] : + (guard__h571724 == 2'b0) ? + _theResult___snd__h579636[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h580340 : - _theResult___snd__h579635[56:5]) ; + _theResult___sfd__h580341 : + _theResult___snd__h579636[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 = - (guard__h590104 == 2'b0 || + (guard__h590105 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h598040[56:5] : - _theResult___sfd__h598775 ; + _theResult___snd__h598041[56:5] : + _theResult___sfd__h598776 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 = - (guard__h590104 == 2'b0) ? - _theResult___snd__h598040[56:5] : + (guard__h590105 == 2'b0) ? + _theResult___snd__h598041[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h598775 : - _theResult___snd__h598040[56:5]) ; + _theResult___sfd__h598776 : + _theResult___snd__h598041[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 = - (guard__h354803 == 2'b0 || + (guard__h354804 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h362851 : - _theResult___exp__h363293 ; + _theResult___fst_exp__h362852 : + _theResult___exp__h363294 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 = - (guard__h354803 == 2'b0) ? - _theResult___fst_exp__h362851 : + (guard__h354804 == 2'b0) ? + _theResult___fst_exp__h362852 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h363293 : - _theResult___fst_exp__h362851) ; + _theResult___exp__h363294 : + _theResult___fst_exp__h362852) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 = - (guard__h372569 == 2'b0 || + (guard__h372570 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h380646 : - _theResult___exp__h381113 ; + _theResult___fst_exp__h380647 : + _theResult___exp__h381114 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 = - (guard__h372569 == 2'b0) ? - _theResult___fst_exp__h380646 : + (guard__h372570 == 2'b0) ? + _theResult___fst_exp__h380647 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h381113 : - _theResult___fst_exp__h380646) ; + _theResult___exp__h381114 : + _theResult___fst_exp__h380647) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 = - (guard__h354803 == 2'b0 || + (guard__h354804 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h362802[56:34] : - _theResult___sfd__h363294 ; + _theResult___snd__h362803[56:34] : + _theResult___sfd__h363295 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 = - (guard__h354803 == 2'b0) ? - _theResult___snd__h362802[56:34] : + (guard__h354804 == 2'b0) ? + _theResult___snd__h362803[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h363294 : - _theResult___snd__h362802[56:34]) ; + _theResult___sfd__h363295 : + _theResult___snd__h362803[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h372569 == 2'b0 || + (guard__h372570 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h380592[56:34] : - _theResult___sfd__h381114 ; + _theResult___snd__h380593[56:34] : + _theResult___sfd__h381115 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h372569 == 2'b0) ? - _theResult___snd__h380592[56:34] : + (guard__h372570 == 2'b0) ? + _theResult___snd__h380593[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h381114 : - _theResult___snd__h380592[56:34]) ; + _theResult___sfd__h381115 : + _theResult___snd__h380593[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 = - (guard__h400500 == 2'b0 || + (guard__h400501 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h408548 : - _theResult___exp__h408990 ; + _theResult___fst_exp__h408549 : + _theResult___exp__h408991 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 = - (guard__h400500 == 2'b0) ? - _theResult___fst_exp__h408548 : + (guard__h400501 == 2'b0) ? + _theResult___fst_exp__h408549 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h408990 : - _theResult___fst_exp__h408548) ; + _theResult___exp__h408991 : + _theResult___fst_exp__h408549) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 = - (guard__h418266 == 2'b0 || + (guard__h418267 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h426343 : - _theResult___exp__h426810 ; + _theResult___fst_exp__h426344 : + _theResult___exp__h426811 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 = - (guard__h418266 == 2'b0) ? - _theResult___fst_exp__h426343 : + (guard__h418267 == 2'b0) ? + _theResult___fst_exp__h426344 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h426810 : - _theResult___fst_exp__h426343) ; + _theResult___exp__h426811 : + _theResult___fst_exp__h426344) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 = - (guard__h400500 == 2'b0 || + (guard__h400501 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h408499[56:34] : - _theResult___sfd__h408991 ; + _theResult___snd__h408500[56:34] : + _theResult___sfd__h408992 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 = - (guard__h400500 == 2'b0) ? - _theResult___snd__h408499[56:34] : + (guard__h400501 == 2'b0) ? + _theResult___snd__h408500[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h408991 : - _theResult___snd__h408499[56:34]) ; + _theResult___sfd__h408992 : + _theResult___snd__h408500[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h418266 == 2'b0 || + (guard__h418267 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h426289[56:34] : - _theResult___sfd__h426811 ; + _theResult___snd__h426290[56:34] : + _theResult___sfd__h426812 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h418266 == 2'b0) ? - _theResult___snd__h426289[56:34] : + (guard__h418267 == 2'b0) ? + _theResult___snd__h426290[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h426811 : - _theResult___snd__h426289[56:34]) ; + _theResult___sfd__h426812 : + _theResult___snd__h426290[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 = - (guard__h446195 == 2'b0 || + (guard__h446196 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h454243 : - _theResult___exp__h454685 ; + _theResult___fst_exp__h454244 : + _theResult___exp__h454686 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 = - (guard__h446195 == 2'b0) ? - _theResult___fst_exp__h454243 : + (guard__h446196 == 2'b0) ? + _theResult___fst_exp__h454244 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h454685 : - _theResult___fst_exp__h454243) ; + _theResult___exp__h454686 : + _theResult___fst_exp__h454244) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 = - (guard__h463961 == 2'b0 || + (guard__h463962 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h472038 : - _theResult___exp__h472505 ; + _theResult___fst_exp__h472039 : + _theResult___exp__h472506 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 = - (guard__h463961 == 2'b0) ? - _theResult___fst_exp__h472038 : + (guard__h463962 == 2'b0) ? + _theResult___fst_exp__h472039 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h472505 : - _theResult___fst_exp__h472038) ; + _theResult___exp__h472506 : + _theResult___fst_exp__h472039) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 = - (guard__h446195 == 2'b0 || + (guard__h446196 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h454194[56:34] : - _theResult___sfd__h454686 ; + _theResult___snd__h454195[56:34] : + _theResult___sfd__h454687 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 = - (guard__h446195 == 2'b0) ? - _theResult___snd__h454194[56:34] : + (guard__h446196 == 2'b0) ? + _theResult___snd__h454195[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h454686 : - _theResult___snd__h454194[56:34]) ; + _theResult___sfd__h454687 : + _theResult___snd__h454195[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h463961 == 2'b0 || + (guard__h463962 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h471984[56:34] : - _theResult___sfd__h472506 ; + _theResult___snd__h471985[56:34] : + _theResult___sfd__h472507 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h463961 == 2'b0) ? - _theResult___snd__h471984[56:34] : + (guard__h463962 == 2'b0) ? + _theResult___snd__h471985[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h472506 : - _theResult___snd__h471984[56:34]) ; + _theResult___sfd__h472507 : + _theResult___snd__h471985[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470 = - (_theResult___fst_exp__h558790 == 11'd2047) ? + (_theResult___fst_exp__h558791 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21472,10 +21491,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676 = - (_theResult___fst_exp__h540380 == 11'd2047) ? + (_theResult___fst_exp__h540381 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21483,10 +21502,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = - (_theResult___fst_exp__h558790 == 11'd2047) ? + (_theResult___fst_exp__h558791 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21494,10 +21513,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = - (_theResult___fst_exp__h519937 == 11'd2047) ? + (_theResult___fst_exp__h519938 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21505,10 +21524,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 = - (_theResult___fst_exp__h598094 == 11'd2047) ? + (_theResult___fst_exp__h598095 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21516,10 +21535,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907 = - (_theResult___fst_exp__h579684 == 11'd2047) ? + (_theResult___fst_exp__h579685 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21527,10 +21546,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 = - (_theResult___fst_exp__h598094 == 11'd2047) ? + (_theResult___fst_exp__h598095 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21538,14 +21557,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 = - (_theResult____h651116 == 16'd0 && + (_theResult____h651118 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h651687 : - _theResult____h651116 ; + enabled_ints__h651689 : + _theResult____h651118 ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || @@ -21607,77 +21626,77 @@ module mkCore(CLK, checkForException___d13698[4] || csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 = - ((f2_exp__h521133 == 8'd0) ? - (f2_sfd__h521134[22] ? + ((f2_exp__h521134 == 8'd0) ? + (f2_sfd__h521135[22] ? 6'd2 : - (f2_sfd__h521134[21] ? + (f2_sfd__h521135[21] ? 6'd3 : - (f2_sfd__h521134[20] ? + (f2_sfd__h521135[20] ? 6'd4 : - (f2_sfd__h521134[19] ? + (f2_sfd__h521135[19] ? 6'd5 : - (f2_sfd__h521134[18] ? + (f2_sfd__h521135[18] ? 6'd6 : - (f2_sfd__h521134[17] ? + (f2_sfd__h521135[17] ? 6'd7 : - (f2_sfd__h521134[16] ? + (f2_sfd__h521135[16] ? 6'd8 : - (f2_sfd__h521134[15] ? + (f2_sfd__h521135[15] ? 6'd9 : - (f2_sfd__h521134[14] ? + (f2_sfd__h521135[14] ? 6'd10 : - (f2_sfd__h521134[13] ? + (f2_sfd__h521135[13] ? 6'd11 : - (f2_sfd__h521134[12] ? + (f2_sfd__h521135[12] ? 6'd12 : - (f2_sfd__h521134[11] ? + (f2_sfd__h521135[11] ? 6'd13 : - (f2_sfd__h521134[10] ? + (f2_sfd__h521135[10] ? 6'd14 : - (f2_sfd__h521134[9] ? + (f2_sfd__h521135[9] ? 6'd15 : - (f2_sfd__h521134[8] ? + (f2_sfd__h521135[8] ? 6'd16 : - (f2_sfd__h521134[7] ? + (f2_sfd__h521135[7] ? 6'd17 : - (f2_sfd__h521134[6] ? + (f2_sfd__h521135[6] ? 6'd18 : - (f2_sfd__h521134[5] ? + (f2_sfd__h521135[5] ? 6'd19 : - (f2_sfd__h521134[4] ? + (f2_sfd__h521135[4] ? 6'd20 : - (f2_sfd__h521134[3] ? + (f2_sfd__h521135[3] ? 6'd21 : - (f2_sfd__h521134[2] ? + (f2_sfd__h521135[2] ? 6'd22 : - (f2_sfd__h521134[1] ? + (f2_sfd__h521135[1] ? 6'd23 : - (f2_sfd__h521134[0] ? + (f2_sfd__h521135[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474 = - (f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0 || - (f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) && - f2_sfd__h521134 == 23'd0) ? + (f2_exp__h521134 == 8'd255 && f2_sfd__h521135 != 23'd0 || + (f2_exp__h521134 == 8'd255 || f2_exp__h521134 == 8'd0) && + f2_sfd__h521135 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h521133 == 8'd0) ? + ((f2_exp__h521134 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 = - (f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0) ? - _theResult___snd_fst_sfd__h521449 : - _theResult___fst_sfd__h559589 ; + (f2_exp__h521134 == 8'd255 && f2_sfd__h521135 != 23'd0) ? + _theResult___snd_fst_sfd__h521450 : + _theResult___fst_sfd__h559590 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 = - { (f2_exp__h521133 == 8'd255) ? + { (f2_exp__h521134 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h559585, + _theResult___fst_exp__h559586, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21687,15 +21706,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 = - (f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0 || - (f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) && - f2_sfd__h521134 == 23'd0) ? + (f2_exp__h521134 == 8'd255 && f2_sfd__h521135 != 23'd0 || + (f2_exp__h521134 == 8'd255 || f2_exp__h521134 == 8'd0) && + f2_sfd__h521135 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[4] : @@ -21703,7 +21722,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[4] : @@ -21711,7 +21730,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[4] : @@ -21719,7 +21738,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[3] : @@ -21727,7 +21746,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[3] : @@ -21735,7 +21754,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[3] : @@ -21743,211 +21762,211 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 = - ((f1_exp__h482139 == 8'd0) ? - (f1_sfd__h482140[22] ? + ((f1_exp__h482140 == 8'd0) ? + (f1_sfd__h482141[22] ? 6'd2 : - (f1_sfd__h482140[21] ? + (f1_sfd__h482141[21] ? 6'd3 : - (f1_sfd__h482140[20] ? + (f1_sfd__h482141[20] ? 6'd4 : - (f1_sfd__h482140[19] ? + (f1_sfd__h482141[19] ? 6'd5 : - (f1_sfd__h482140[18] ? + (f1_sfd__h482141[18] ? 6'd6 : - (f1_sfd__h482140[17] ? + (f1_sfd__h482141[17] ? 6'd7 : - (f1_sfd__h482140[16] ? + (f1_sfd__h482141[16] ? 6'd8 : - (f1_sfd__h482140[15] ? + (f1_sfd__h482141[15] ? 6'd9 : - (f1_sfd__h482140[14] ? + (f1_sfd__h482141[14] ? 6'd10 : - (f1_sfd__h482140[13] ? + (f1_sfd__h482141[13] ? 6'd11 : - (f1_sfd__h482140[12] ? + (f1_sfd__h482141[12] ? 6'd12 : - (f1_sfd__h482140[11] ? + (f1_sfd__h482141[11] ? 6'd13 : - (f1_sfd__h482140[10] ? + (f1_sfd__h482141[10] ? 6'd14 : - (f1_sfd__h482140[9] ? + (f1_sfd__h482141[9] ? 6'd15 : - (f1_sfd__h482140[8] ? + (f1_sfd__h482141[8] ? 6'd16 : - (f1_sfd__h482140[7] ? + (f1_sfd__h482141[7] ? 6'd17 : - (f1_sfd__h482140[6] ? + (f1_sfd__h482141[6] ? 6'd18 : - (f1_sfd__h482140[5] ? + (f1_sfd__h482141[5] ? 6'd19 : - (f1_sfd__h482140[4] ? + (f1_sfd__h482141[4] ? 6'd20 : - (f1_sfd__h482140[3] ? + (f1_sfd__h482141[3] ? 6'd21 : - (f1_sfd__h482140[2] ? + (f1_sfd__h482141[2] ? 6'd22 : - (f1_sfd__h482140[1] ? + (f1_sfd__h482141[1] ? 6'd23 : - (f1_sfd__h482140[0] ? + (f1_sfd__h482141[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989 = - (f1_exp__h482139 == 8'd255 && f1_sfd__h482140 != 23'd0 || - (f1_exp__h482139 == 8'd255 || f1_exp__h482139 == 8'd0) && - f1_sfd__h482140 == 23'd0) ? + (f1_exp__h482140 == 8'd255 && f1_sfd__h482141 != 23'd0 || + (f1_exp__h482140 == 8'd255 || f1_exp__h482140 == 8'd0) && + f1_sfd__h482141 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h482139 == 8'd0) ? + ((f1_exp__h482140 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 = - (f1_exp__h482139 == 8'd255 && f1_sfd__h482140 != 23'd0) ? - _theResult___snd_fst_sfd__h482455 : - _theResult___fst_sfd__h520736 ; + (f1_exp__h482140 == 8'd255 && f1_sfd__h482141 != 23'd0) ? + _theResult___snd_fst_sfd__h482456 : + _theResult___fst_sfd__h520737 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989, - (f1_exp__h482139 == 8'd255) ? + (f1_exp__h482140 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h520732, + _theResult___fst_exp__h520733, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 = - ((f3_exp__h560437 == 8'd0) ? - (f3_sfd__h560438[22] ? + ((f3_exp__h560438 == 8'd0) ? + (f3_sfd__h560439[22] ? 6'd2 : - (f3_sfd__h560438[21] ? + (f3_sfd__h560439[21] ? 6'd3 : - (f3_sfd__h560438[20] ? + (f3_sfd__h560439[20] ? 6'd4 : - (f3_sfd__h560438[19] ? + (f3_sfd__h560439[19] ? 6'd5 : - (f3_sfd__h560438[18] ? + (f3_sfd__h560439[18] ? 6'd6 : - (f3_sfd__h560438[17] ? + (f3_sfd__h560439[17] ? 6'd7 : - (f3_sfd__h560438[16] ? + (f3_sfd__h560439[16] ? 6'd8 : - (f3_sfd__h560438[15] ? + (f3_sfd__h560439[15] ? 6'd9 : - (f3_sfd__h560438[14] ? + (f3_sfd__h560439[14] ? 6'd10 : - (f3_sfd__h560438[13] ? + (f3_sfd__h560439[13] ? 6'd11 : - (f3_sfd__h560438[12] ? + (f3_sfd__h560439[12] ? 6'd12 : - (f3_sfd__h560438[11] ? + (f3_sfd__h560439[11] ? 6'd13 : - (f3_sfd__h560438[10] ? + (f3_sfd__h560439[10] ? 6'd14 : - (f3_sfd__h560438[9] ? + (f3_sfd__h560439[9] ? 6'd15 : - (f3_sfd__h560438[8] ? + (f3_sfd__h560439[8] ? 6'd16 : - (f3_sfd__h560438[7] ? + (f3_sfd__h560439[7] ? 6'd17 : - (f3_sfd__h560438[6] ? + (f3_sfd__h560439[6] ? 6'd18 : - (f3_sfd__h560438[5] ? + (f3_sfd__h560439[5] ? 6'd19 : - (f3_sfd__h560438[4] ? + (f3_sfd__h560439[4] ? 6'd20 : - (f3_sfd__h560438[3] ? + (f3_sfd__h560439[3] ? 6'd21 : - (f3_sfd__h560438[2] ? + (f3_sfd__h560439[2] ? 6'd22 : - (f3_sfd__h560438[1] ? + (f3_sfd__h560439[1] ? 6'd23 : - (f3_sfd__h560438[0] ? + (f3_sfd__h560439[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704 = - (f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0 || - (f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) && - f3_sfd__h560438 == 23'd0) ? + (f3_exp__h560438 == 8'd255 && f3_sfd__h560439 != 23'd0 || + (f3_exp__h560438 == 8'd255 || f3_exp__h560438 == 8'd0) && + f3_sfd__h560439 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h560437 == 8'd0) ? + ((f3_exp__h560438 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 = - (f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0) ? - _theResult___snd_fst_sfd__h560753 : - _theResult___fst_sfd__h598893 ; + (f3_exp__h560438 == 8'd255 && f3_sfd__h560439 != 23'd0) ? + _theResult___snd_fst_sfd__h560754 : + _theResult___fst_sfd__h598894 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 = - { (f3_exp__h560437 == 8'd255) ? + { (f3_exp__h560438 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h598889, + _theResult___fst_exp__h598890, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21957,9 +21976,9 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938 = - (f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0 || - (f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) && - f3_sfd__h560438 == 23'd0) ? + (f3_exp__h560438 == 8'd255 && f3_sfd__h560439 != 23'd0 || + (f3_exp__h560438 == 8'd255 || f3_exp__h560438 == 8'd0) && + f3_sfd__h560439 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22168,7 +22187,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || - _theResult___fst_exp__h540380 == 11'd2047) ? + _theResult___fst_exp__h540381 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22176,12 +22195,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || - _theResult___fst_exp__h501527 == 11'd2047) ? + _theResult___fst_exp__h501528 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -22189,12 +22208,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || - _theResult___fst_exp__h579684 == 11'd2047) ? + _theResult___fst_exp__h579685 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22202,7 +22221,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? @@ -22687,25 +22706,7 @@ module mkCore(CLK, 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281 = - { (rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[97:96] == 2'd0) ? - { 2'd0, rob$deqPort_0_deq_data[95:32] } : - ((rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[97:96] == 2'd1) ? - { 2'd1, rob$deqPort_0_deq_data[95:32] } : - { 2'd2, - (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h721446 : - rob$deqPort_0_deq_data[95:32] }), - 5'h0A, - rob$deqPort_0_deq_data[26], - 64'hAAAAAAAAAAAAAAAA, - x_prv__h722029, - 64'hAAAAAAAAAAAAAAAA, - x__h725432, - 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661 = + assign IF_NOT_rob_deqPort_1_deq_data__5322_BIT_25_532_ETC___d15674 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -22744,48 +22745,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[2] : - _theResult___fst_exp__h520720 == 11'd2047 && - _theResult___fst_sfd__h520721 == 52'd0 ; + _theResult___fst_exp__h520721 == 11'd2047 && + _theResult___fst_sfd__h520722 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[2] : - _theResult___fst_exp__h559573 == 11'd2047 && - _theResult___fst_sfd__h559574 == 52'd0 ; + _theResult___fst_exp__h559574 == 11'd2047 && + _theResult___fst_sfd__h559575 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[2] : - _theResult___fst_exp__h598877 == 11'd2047 && - _theResult___fst_sfd__h598878 == 52'd0 ; + _theResult___fst_exp__h598878 == 11'd2047 && + _theResult___fst_sfd__h598879 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[1] : - _theResult___fst_exp__h519937 == 11'd0 && - guard__h511947 != 2'b0 ; + _theResult___fst_exp__h519938 == 11'd0 && + guard__h511948 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[1] : - _theResult___fst_exp__h558790 == 11'd0 && - guard__h550800 != 2'b0 ; + _theResult___fst_exp__h558791 == 11'd0 && + guard__h550801 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[1] : - _theResult___fst_exp__h598094 == 11'd0 && - guard__h590104 != 2'b0 ; + _theResult___fst_exp__h598095 == 11'd0 && + guard__h590105 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[0] : - _theResult___fst_exp__h519937 != 11'd2047 && - guard__h511947 != 2'b0 ; + _theResult___fst_exp__h519938 != 11'd2047 && + guard__h511948 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[0] : - _theResult___fst_exp__h558790 != 11'd2047 && - guard__h550800 != 2'b0 ; + _theResult___fst_exp__h558791 != 11'd2047 && + guard__h550801 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[0] : - _theResult___fst_exp__h598094 != 11'd2047 && - guard__h590104 != 2'b0 ; + _theResult___fst_exp__h598095 != 11'd2047 && + guard__h590105 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -22831,35 +22832,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371961 == 8'd255) ? + ((_theResult___fst_exp__h371962 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084) : - ((_theResult___fst_exp__h380646 == 8'd255) ? + ((_theResult___fst_exp__h380647 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371961 == 8'd255) ? + ((_theResult___fst_exp__h371962 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127) : - ((_theResult___fst_exp__h380646 == 8'd255) ? + ((_theResult___fst_exp__h380647 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[2] : - _theResult___fst_exp__h381194 == 8'd255 && - _theResult___fst_sfd__h381195 == 23'd0 ; + _theResult___fst_exp__h381195 == 8'd255 && + _theResult___fst_sfd__h381196 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[1] : - _theResult___fst_exp__h380646 == 8'd0 && - guard__h372569 != 2'b0 ; + _theResult___fst_exp__h380647 == 8'd0 && + guard__h372570 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[0] : - _theResult___fst_exp__h380646 != 8'd255 && - guard__h372569 != 2'b0 ; + _theResult___fst_exp__h380647 != 8'd255 && + guard__h372570 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? @@ -22869,35 +22870,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417658 == 8'd255) ? + ((_theResult___fst_exp__h417659 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476) : - ((_theResult___fst_exp__h426343 == 8'd255) ? + ((_theResult___fst_exp__h426344 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417658 == 8'd255) ? + ((_theResult___fst_exp__h417659 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519) : - ((_theResult___fst_exp__h426343 == 8'd255) ? + ((_theResult___fst_exp__h426344 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[2] : - _theResult___fst_exp__h426891 == 8'd255 && - _theResult___fst_sfd__h426892 == 23'd0 ; + _theResult___fst_exp__h426892 == 8'd255 && + _theResult___fst_sfd__h426893 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[1] : - _theResult___fst_exp__h426343 == 8'd0 && - guard__h418266 != 2'b0 ; + _theResult___fst_exp__h426344 == 8'd0 && + guard__h418267 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[0] : - _theResult___fst_exp__h426343 != 8'd255 && - guard__h418266 != 2'b0 ; + _theResult___fst_exp__h426344 != 8'd255 && + guard__h418267 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? @@ -22907,50 +22908,49 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463353 == 8'd255) ? + ((_theResult___fst_exp__h463354 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868) : - ((_theResult___fst_exp__h472038 == 8'd255) ? + ((_theResult___fst_exp__h472039 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463353 == 8'd255) ? + ((_theResult___fst_exp__h463354 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911) : - ((_theResult___fst_exp__h472038 == 8'd255) ? + ((_theResult___fst_exp__h472039 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[2] : - _theResult___fst_exp__h472586 == 8'd255 && - _theResult___fst_sfd__h472587 == 23'd0 ; + _theResult___fst_exp__h472587 == 8'd255 && + _theResult___fst_sfd__h472588 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[1] : - _theResult___fst_exp__h472038 == 8'd0 && - guard__h463961 != 2'b0 ; + _theResult___fst_exp__h472039 == 8'd0 && + guard__h463962 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[0] : - _theResult___fst_exp__h472038 != 8'd255 && - guard__h463961 != 2'b0 ; + _theResult___fst_exp__h472039 != 8'd255 && + guard__h463962 != 2'b0 ; assign IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 = checkForException___d13008[4] ? CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916 = - { trap_val__h708464, - CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257, + assign IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926 = + { CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, commitStage_f_rob_data$D_OUT[95:32], 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h711506, - pc__h711407, - x__h713649, - x__h713841, + x_prv__h712487, + pc__h712387, + x__h714645, + x__h714837, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -23608,8 +23608,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h646693 : - w__h646688 ; + result__h646695 : + w__h646690 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23631,39 +23631,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23716,7 +23716,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h197125 : + x__h197126 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ? 64'd0 : 64'd1) ; @@ -23728,7 +23728,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 = - _theResult_____2__h296520 == v__h295940 ; + _theResult_____2__h296521 == v__h295941 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23737,7 +23737,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 = - _theResult_____2__h304516 == v__h299285 ; + _theResult_____2__h304517 == v__h299286 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23766,14 +23766,14 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h302150 } ; + x__h302151 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 = - !MUX_flush_reservation$write_1__SEL_2 && + !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 = - MUX_flush_reservation$write_1__SEL_2 ? + MUX_flush_reservation$write_1__SEL_1 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -23864,35 +23864,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -23920,7 +23920,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 = - _theResult_____2__h310510 == v__h309799 ; + _theResult_____2__h310511 == v__h309800 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23929,7 +23929,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 = - _theResult_____2__h318364 == v__h313675 ; + _theResult_____2__h318365 == v__h313676 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24081,7 +24081,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 = - _theResult_____2__h331933 == v__h331501 ; + _theResult_____2__h331934 == v__h331502 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -24130,7 +24130,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 = - _theResult_____2__h328708 == v__h328276 ; + _theResult_____2__h328709 == v__h328277 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -24162,10 +24162,10 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h726048 : + upd__h727048 : csrf_minstret_ehr_data_rl ; - assign IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909 = - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ? + assign IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 = + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? { 43'd8192, csrf_mxr_reg, csrf_sum_reg, @@ -24230,8 +24230,8 @@ module mkCore(CLK, assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13954 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 || rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; @@ -24247,8 +24247,8 @@ module mkCore(CLK, IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13833 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14068 || rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && regRenamingTable$RDY_rename_1_getRename && + regRenamingTable$RDY_rename_1_claimRename && fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && @@ -24288,17 +24288,17 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 = - rob$deqPort_0_canDeq ? y_avValue_fst__h729252 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 = + assign IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 = + rob$deqPort_0_canDeq ? y_avValue_fst__h730270 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h729727 : + y_avValue_snd_snd_snd_fst__h730745 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180 = + assign IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? csrf_sepc_csr : csrf_mepc_csr ; - assign IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271 = + assign IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15282 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? { csrf_mpp_reg, 3'd0, @@ -24318,55 +24318,55 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501 = - { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256, + assign IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512 = + { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, rob$deqPort_0_deq_data[95:32] } ; - assign IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662 = + assign IF_rob_deqPort_1_canDeq__5319_THEN_IF_NOT_rob__ETC___d15675 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661 : + IF_NOT_rob_deqPort_1_deq_data__5322_BIT_25_532_ETC___d15674 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h511098[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74 = - sfdin__h417652[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99 = - sfdin__h445581[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h549951[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29 = - sfdin__h354189[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109 = - sfdin__h463347[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39 = - sfdin__h371955[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h589255[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64 = - sfdin__h399886[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h501478[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66 = - _theResult___snd__h408499[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h519883[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79 = - _theResult___snd__h426289[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h540331[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101 = - _theResult___snd__h454194[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h558736[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31 = - _theResult___snd__h362802[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114 = - _theResult___snd__h471984[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h579635[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44 = - _theResult___snd__h380592[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h598040[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin11099_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h511099[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin17653_BIT_33_THEN_2_ELSE_0__q74 = + sfdin__h417653[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin45582_BIT_33_THEN_2_ELSE_0__q99 = + sfdin__h445582[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin49952_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h549952[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin54190_BIT_33_THEN_2_ELSE_0__q29 = + sfdin__h354190[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin63348_BIT_33_THEN_2_ELSE_0__q109 = + sfdin__h463348[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin71956_BIT_33_THEN_2_ELSE_0__q39 = + sfdin__h371956[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin89256_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h589256[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin99887_BIT_33_THEN_2_ELSE_0__q64 = + sfdin__h399887[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd01479_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h501479[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd08500_BIT_33_THEN_2_ELSE_0__q66 = + _theResult___snd__h408500[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd19884_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h519884[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd26290_BIT_33_THEN_2_ELSE_0__q79 = + _theResult___snd__h426290[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd40332_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h540332[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd54195_BIT_33_THEN_2_ELSE_0__q101 = + _theResult___snd__h454195[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58737_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h558737[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd62803_BIT_33_THEN_2_ELSE_0__q31 = + _theResult___snd__h362803[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd71985_BIT_33_THEN_2_ELSE_0__q114 = + _theResult___snd__h471985[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd79636_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h579636[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd80593_BIT_33_THEN_2_ELSE_0__q44 = + _theResult___snd__h380593[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98041_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h598041[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? @@ -24457,138 +24457,138 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] && !checkForException___d13698[4] && NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 = - (fflags__h732495 & csrf_fflags_reg) != fflags__h732495 || + assign NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 = + (fflags__h733530 & csrf_fflags_reg) != fflags__h733530 || csrf_fs_reg != 2'b11 && - (IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662 || - fflags__h732495 != 5'd0) ; + (IF_rob_deqPort_1_canDeq__5319_THEN_IF_NOT_rob__ETC___d15675 || + fflags__h733530 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 = - !f2_sfd__h521134[21] && !f2_sfd__h521134[20] && - !f2_sfd__h521134[19] && - !f2_sfd__h521134[18] && - !f2_sfd__h521134[17] && - !f2_sfd__h521134[16] && - !f2_sfd__h521134[15] && - !f2_sfd__h521134[14] && - !f2_sfd__h521134[13] && - !f2_sfd__h521134[12] && - !f2_sfd__h521134[11] && - !f2_sfd__h521134[10] && - !f2_sfd__h521134[9] && - !f2_sfd__h521134[8] && - !f2_sfd__h521134[7] && - !f2_sfd__h521134[6] && - !f2_sfd__h521134[5] && - !f2_sfd__h521134[4] && - !f2_sfd__h521134[3] && - !f2_sfd__h521134[2] && - !f2_sfd__h521134[1] && - !f2_sfd__h521134[0] ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + !f2_sfd__h521135[21] && !f2_sfd__h521135[20] && + !f2_sfd__h521135[19] && + !f2_sfd__h521135[18] && + !f2_sfd__h521135[17] && + !f2_sfd__h521135[16] && + !f2_sfd__h521135[15] && + !f2_sfd__h521135[14] && + !f2_sfd__h521135[13] && + !f2_sfd__h521135[12] && + !f2_sfd__h521135[11] && + !f2_sfd__h521135[10] && + !f2_sfd__h521135[9] && + !f2_sfd__h521135[8] && + !f2_sfd__h521135[7] && + !f2_sfd__h521135[6] && + !f2_sfd__h521135[5] && + !f2_sfd__h521135[4] && + !f2_sfd__h521135[3] && + !f2_sfd__h521135[2] && + !f2_sfd__h521135[1] && + !f2_sfd__h521135[0] ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 = - !f1_sfd__h482140[21] && !f1_sfd__h482140[20] && - !f1_sfd__h482140[19] && - !f1_sfd__h482140[18] && - !f1_sfd__h482140[17] && - !f1_sfd__h482140[16] && - !f1_sfd__h482140[15] && - !f1_sfd__h482140[14] && - !f1_sfd__h482140[13] && - !f1_sfd__h482140[12] && - !f1_sfd__h482140[11] && - !f1_sfd__h482140[10] && - !f1_sfd__h482140[9] && - !f1_sfd__h482140[8] && - !f1_sfd__h482140[7] && - !f1_sfd__h482140[6] && - !f1_sfd__h482140[5] && - !f1_sfd__h482140[4] && - !f1_sfd__h482140[3] && - !f1_sfd__h482140[2] && - !f1_sfd__h482140[1] && - !f1_sfd__h482140[0] ; + !f1_sfd__h482141[21] && !f1_sfd__h482141[20] && + !f1_sfd__h482141[19] && + !f1_sfd__h482141[18] && + !f1_sfd__h482141[17] && + !f1_sfd__h482141[16] && + !f1_sfd__h482141[15] && + !f1_sfd__h482141[14] && + !f1_sfd__h482141[13] && + !f1_sfd__h482141[12] && + !f1_sfd__h482141[11] && + !f1_sfd__h482141[10] && + !f1_sfd__h482141[9] && + !f1_sfd__h482141[8] && + !f1_sfd__h482141[7] && + !f1_sfd__h482141[6] && + !f1_sfd__h482141[5] && + !f1_sfd__h482141[4] && + !f1_sfd__h482141[3] && + !f1_sfd__h482141[2] && + !f1_sfd__h482141[1] && + !f1_sfd__h482141[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 = - !f3_sfd__h560438[21] && !f3_sfd__h560438[20] && - !f3_sfd__h560438[19] && - !f3_sfd__h560438[18] && - !f3_sfd__h560438[17] && - !f3_sfd__h560438[16] && - !f3_sfd__h560438[15] && - !f3_sfd__h560438[14] && - !f3_sfd__h560438[13] && - !f3_sfd__h560438[12] && - !f3_sfd__h560438[11] && - !f3_sfd__h560438[10] && - !f3_sfd__h560438[9] && - !f3_sfd__h560438[8] && - !f3_sfd__h560438[7] && - !f3_sfd__h560438[6] && - !f3_sfd__h560438[5] && - !f3_sfd__h560438[4] && - !f3_sfd__h560438[3] && - !f3_sfd__h560438[2] && - !f3_sfd__h560438[1] && - !f3_sfd__h560438[0] ; + !f3_sfd__h560439[21] && !f3_sfd__h560439[20] && + !f3_sfd__h560439[19] && + !f3_sfd__h560439[18] && + !f3_sfd__h560439[17] && + !f3_sfd__h560439[16] && + !f3_sfd__h560439[15] && + !f3_sfd__h560439[14] && + !f3_sfd__h560439[13] && + !f3_sfd__h560439[12] && + !f3_sfd__h560439[11] && + !f3_sfd__h560439[10] && + !f3_sfd__h560439[9] && + !f3_sfd__h560439[8] && + !f3_sfd__h560439[7] && + !f3_sfd__h560439[6] && + !f3_sfd__h560439[5] && + !f3_sfd__h560439[4] && + !f3_sfd__h560439[3] && + !f3_sfd__h560439[2] && + !f3_sfd__h560439[1] && + !f3_sfd__h560439[0] ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 ; - assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614 = + assign NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14624 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] == 4'd0 || commitStage_commitTrap[35:32] == 4'd1 || @@ -24601,13 +24601,13 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd11) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; - assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621 = - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614 || + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + assign NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14631 = + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14624 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 = + assign NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd14) && (!commitStage_commitTrap[36] || @@ -24623,12 +24623,36 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd14) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; - assign NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 = + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + assign NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; + assign NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15016 = + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005 && + (rob$deqPort_0_deq_data[329:325] == 5'd0 || + rob$deqPort_0_deq_data[329:325] == 5'd21 || + rob$deqPort_0_deq_data[329:325] == 5'd17 || + rob$deqPort_0_deq_data[329:325] == 5'd18 || + rob$deqPort_0_deq_data[329:325] == 5'd13 || + rob$deqPort_0_deq_data[329:325] == 5'd16 || + rob$deqPort_0_deq_data[329:325] == 5'd15 || + rob$deqPort_0_deq_data[329:325] == 5'd19 || + rob$deqPort_0_deq_data[329:325] == 5'd20) && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; + assign NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15368 = + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005 && + rob$deqPort_0_deq_data[329:325] != 5'd0 && + rob$deqPort_0_deq_data[329:325] != 5'd21 && + rob$deqPort_0_deq_data[329:325] != 5'd17 && + rob$deqPort_0_deq_data[329:325] != 5'd18 && + rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[329:325] != 5'd16 && + rob$deqPort_0_deq_data[329:325] != 5'd15 && + rob$deqPort_0_deq_data[329:325] != 5'd19 && + rob$deqPort_0_deq_data[329:325] != 5'd20 && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) && @@ -25133,7 +25157,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 && !csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 && - csr_addr__h655325 != 12'h8FF) ; + csr_addr__h655327 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -25158,11 +25182,11 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 = - !csrf_prv_reg_read__2787_ULE_1___d14685 || + assign NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 = + !csrf_prv_reg_read__2787_ULE_1___d14696 || (commitStage_commitTrap[36] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705) ; + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716) ; assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13527 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || @@ -25258,9 +25282,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h655326 == 5'd0 && - imm__h655327 == 32'd0 || - csr_addr__h655325[11:10] != 2'b11 ; + rs1__h655328 == 5'd0 && + imm__h655329 == 32'd0 || + csr_addr__h655327[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && @@ -25371,12 +25395,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -25513,14 +25537,14 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13894 ; - assign NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345 = + assign NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_RDY_ETC___d15356 = (!rob$deqPort_0_canDeq || rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342) ; - assign NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 = + NOT_rob_deqPort_1_deq_data__5322_BIT_25_5323_5_ETC___d15353) ; + assign NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25534,15 +25558,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983 = + assign NOT_rob_deqPort_0_deq_data__4339_BITS_329_TO_3_ETC___d14993 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342 = + assign NOT_rob_deqPort_1_deq_data__5322_BIT_25_5323_5_ETC___d15353 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -25581,33 +25605,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - x__h291615 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 } ; + x__h291616 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16096 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16052 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16052, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = - { {4{f2_exp21133_MINUS_127__q176[7]}}, - f2_exp21133_MINUS_127__q176 } ; + { {4{f2_exp21134_MINUS_127__q176[7]}}, + f2_exp21134_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^ 12'h800) <= @@ -25617,8 +25641,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 = - { {4{f1_exp82139_MINUS_127__q136[7]}}, - f1_exp82139_MINUS_127__q136 } ; + { {4{f1_exp82140_MINUS_127__q136[7]}}, + f1_exp82140_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^ 12'h800) <= @@ -25628,8 +25652,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 = - { {4{f3_exp60437_MINUS_127__q153[7]}}, - f3_exp60437_MINUS_127__q153 } ; + { {4{f3_exp60438_MINUS_127__q153[7]}}, + f3_exp60438_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^ 12'h800) <= @@ -25714,15 +25738,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169 = { 3'd0, - _theResult___fst_exp__h354195 == 8'd0 && - (sfdin__h354189[56:34] == 23'd0 || guard__h346094 != 2'b0), + _theResult___fst_exp__h354196 == 8'd0 && + (sfdin__h354190[56:34] == 23'd0 || guard__h346095 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h354792 == 8'd255 && - _theResult___fst_sfd__h354793 == 23'd0, + _theResult___fst_exp__h354793 == 8'd255 && + _theResult___fst_sfd__h354794 == 23'd0, 1'd0, - _theResult___fst_exp__h354195 != 8'd255 && - guard__h346094 != 2'b0 } ; + _theResult___fst_exp__h354196 != 8'd255 && + guard__h346095 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ^ @@ -25730,15 +25754,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561 = { 3'd0, - _theResult___fst_exp__h399892 == 8'd0 && - (sfdin__h399886[56:34] == 23'd0 || guard__h391793 != 2'b0), + _theResult___fst_exp__h399893 == 8'd0 && + (sfdin__h399887[56:34] == 23'd0 || guard__h391794 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h400489 == 8'd255 && - _theResult___fst_sfd__h400490 == 23'd0, + _theResult___fst_exp__h400490 == 8'd255 && + _theResult___fst_sfd__h400491 == 23'd0, 1'd0, - _theResult___fst_exp__h399892 != 8'd255 && - guard__h391793 != 2'b0 } ; + _theResult___fst_exp__h399893 != 8'd255 && + guard__h391794 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ^ @@ -25746,15 +25770,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953 = { 3'd0, - _theResult___fst_exp__h445587 == 8'd0 && - (sfdin__h445581[56:34] == 23'd0 || guard__h437488 != 2'b0), + _theResult___fst_exp__h445588 == 8'd0 && + (sfdin__h445582[56:34] == 23'd0 || guard__h437489 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h446184 == 8'd255 && - _theResult___fst_sfd__h446185 == 23'd0, + _theResult___fst_exp__h446185 == 8'd255 && + _theResult___fst_sfd__h446186 == 23'd0, 1'd0, - _theResult___fst_exp__h445587 != 8'd255 && - guard__h437488 != 2'b0 } ; + _theResult___fst_exp__h445588 != 8'd255 && + guard__h437489 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ^ @@ -25762,37 +25786,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758 = { 3'd0, - _theResult___fst_exp__h511104 == 11'd0 && - (sfdin__h511098[56:5] == 52'd0 || guard__h502878 != 2'b0), + _theResult___fst_exp__h511105 == 11'd0 && + (sfdin__h511099[56:5] == 52'd0 || guard__h502879 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h511936 == 11'd2047 && - _theResult___fst_sfd__h511937 == 52'd0, + _theResult___fst_exp__h511937 == 11'd2047 && + _theResult___fst_sfd__h511938 == 52'd0, 1'd0, - _theResult___fst_exp__h511104 != 11'd2047 && - guard__h502878 != 2'b0 } ; + _theResult___fst_exp__h511105 != 11'd2047 && + guard__h502879 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799 = { 3'd0, - _theResult___fst_exp__h549957 == 11'd0 && - (sfdin__h549951[56:5] == 52'd0 || guard__h541731 != 2'b0), + _theResult___fst_exp__h549958 == 11'd0 && + (sfdin__h549952[56:5] == 52'd0 || guard__h541732 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h550789 == 11'd2047 && - _theResult___fst_sfd__h550790 == 52'd0, + _theResult___fst_exp__h550790 == 11'd2047 && + _theResult___fst_sfd__h550791 == 52'd0, 1'd0, - _theResult___fst_exp__h549957 != 11'd2047 && - guard__h541731 != 2'b0 } ; + _theResult___fst_exp__h549958 != 11'd2047 && + guard__h541732 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843 = { 3'd0, - _theResult___fst_exp__h589261 == 11'd0 && - (sfdin__h589255[56:5] == 52'd0 || guard__h581035 != 2'b0), + _theResult___fst_exp__h589262 == 11'd0 && + (sfdin__h589256[56:5] == 52'd0 || guard__h581036 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h590093 == 11'd2047 && - _theResult___fst_sfd__h590094 == 52'd0, + _theResult___fst_exp__h590094 == 11'd2047 && + _theResult___fst_sfd__h590095 == 52'd0, 1'd0, - _theResult___fst_exp__h589261 != 11'd2047 && - guard__h581035 != 2'b0 } ; + _theResult___fst_exp__h589262 != 11'd2047 && + guard__h581036 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ^ @@ -25810,15 +25834,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198 = { 3'd0, - _theResult___fst_exp__h371961 == 8'd0 && - (sfdin__h371955[56:34] == 23'd0 || guard__h363733 != 2'b0), + _theResult___fst_exp__h371962 == 8'd0 && + (sfdin__h371956[56:34] == 23'd0 || guard__h363734 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h372558 == 8'd255 && - _theResult___fst_sfd__h372559 == 23'd0, + _theResult___fst_exp__h372559 == 8'd255 && + _theResult___fst_sfd__h372560 == 23'd0, 1'd0, - _theResult___fst_exp__h371961 != 8'd255 && - guard__h363733 != 2'b0 } ; + _theResult___fst_exp__h371962 != 8'd255 && + guard__h363734 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ^ @@ -25826,15 +25850,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590 = { 3'd0, - _theResult___fst_exp__h417658 == 8'd0 && - (sfdin__h417652[56:34] == 23'd0 || guard__h409430 != 2'b0), + _theResult___fst_exp__h417659 == 8'd0 && + (sfdin__h417653[56:34] == 23'd0 || guard__h409431 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h418255 == 8'd255 && - _theResult___fst_sfd__h418256 == 23'd0, + _theResult___fst_exp__h418256 == 8'd255 && + _theResult___fst_sfd__h418257 == 23'd0, 1'd0, - _theResult___fst_exp__h417658 != 8'd255 && - guard__h409430 != 2'b0 } ; + _theResult___fst_exp__h417659 != 8'd255 && + guard__h409431 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ^ @@ -25842,15 +25866,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982 = { 3'd0, - _theResult___fst_exp__h463353 == 8'd0 && - (sfdin__h463347[56:34] == 23'd0 || guard__h455125 != 2'b0), + _theResult___fst_exp__h463354 == 8'd0 && + (sfdin__h463348[56:34] == 23'd0 || guard__h455126 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h463950 == 8'd255 && - _theResult___fst_sfd__h463951 == 23'd0, + _theResult___fst_exp__h463951 == 8'd255 && + _theResult___fst_sfd__h463952 == 23'd0, 1'd0, - _theResult___fst_exp__h463353 != 8'd255 && - guard__h455125 != 2'b0 } ; + _theResult___fst_exp__h463354 != 8'd255 && + guard__h455126 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^ @@ -25864,37 +25888,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741 = { 3'd0, - _theResult___fst_exp__h501527 == 11'd0 && - guard__h493566 != 2'b0, + _theResult___fst_exp__h501528 == 11'd0 && + guard__h493567 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h502285 == 11'd2047 && - _theResult___fst_sfd__h502286 == 52'd0, + _theResult___fst_exp__h502286 == 11'd2047 && + _theResult___fst_sfd__h502287 == 52'd0, 1'd0, - _theResult___fst_exp__h501527 != 11'd2047 && - guard__h493566 != 2'b0 } ; + _theResult___fst_exp__h501528 != 11'd2047 && + guard__h493567 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782 = { 3'd0, - _theResult___fst_exp__h540380 == 11'd0 && - guard__h532419 != 2'b0, + _theResult___fst_exp__h540381 == 11'd0 && + guard__h532420 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h541138 == 11'd2047 && - _theResult___fst_sfd__h541139 == 52'd0, + _theResult___fst_exp__h541139 == 11'd2047 && + _theResult___fst_sfd__h541140 == 52'd0, 1'd0, - _theResult___fst_exp__h540380 != 11'd2047 && - guard__h532419 != 2'b0 } ; + _theResult___fst_exp__h540381 != 11'd2047 && + guard__h532420 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826 = { 3'd0, - _theResult___fst_exp__h579684 == 11'd0 && - guard__h571723 != 2'b0, + _theResult___fst_exp__h579685 == 11'd0 && + guard__h571724 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h580442 == 11'd2047 && - _theResult___fst_sfd__h580443 == 52'd0, + _theResult___fst_exp__h580443 == 11'd2047 && + _theResult___fst_sfd__h580444 == 52'd0, 1'd0, - _theResult___fst_exp__h579684 != 11'd2047 && - guard__h571723 != 2'b0 } ; + _theResult___fst_exp__h579685 != 11'd2047 && + guard__h571724 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^ @@ -25930,15 +25954,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181 = { 3'd0, - _theResult___fst_exp__h362851 == 8'd0 && - guard__h354803 != 2'b0, + _theResult___fst_exp__h362852 == 8'd0 && + guard__h354804 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h363374 == 8'd255 && - _theResult___fst_sfd__h363375 == 23'd0, + _theResult___fst_exp__h363375 == 8'd255 && + _theResult___fst_sfd__h363376 == 23'd0, 1'd0, - _theResult___fst_exp__h362851 != 8'd255 && - guard__h354803 != 2'b0 } ; + _theResult___fst_exp__h362852 != 8'd255 && + guard__h354804 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^ @@ -25952,15 +25976,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573 = { 3'd0, - _theResult___fst_exp__h408548 == 8'd0 && - guard__h400500 != 2'b0, + _theResult___fst_exp__h408549 == 8'd0 && + guard__h400501 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h409071 == 8'd255 && - _theResult___fst_sfd__h409072 == 23'd0, + _theResult___fst_exp__h409072 == 8'd255 && + _theResult___fst_sfd__h409073 == 23'd0, 1'd0, - _theResult___fst_exp__h408548 != 8'd255 && - guard__h400500 != 2'b0 } ; + _theResult___fst_exp__h408549 != 8'd255 && + guard__h400501 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^ @@ -25974,15 +25998,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965 = { 3'd0, - _theResult___fst_exp__h454243 == 8'd0 && - guard__h446195 != 2'b0, + _theResult___fst_exp__h454244 == 8'd0 && + guard__h446196 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h454766 == 8'd255 && - _theResult___fst_sfd__h454767 == 23'd0, + _theResult___fst_exp__h454767 == 8'd255 && + _theResult___fst_sfd__h454768 == 23'd0, 1'd0, - _theResult___fst_exp__h454243 != 8'd255 && - guard__h446195 != 2'b0 } ; + _theResult___fst_exp__h454244 != 8'd255 && + guard__h446196 != 2'b0 } ; assign _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798 = { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, @@ -25996,7 +26020,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -26010,33 +26034,35 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138 = - sfd__h521495 >> + sfd__h521496 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653 = - sfd__h482501 >> + sfd__h482502 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368 = - sfd__h560799 >> + sfd__h560800 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558 = - sfd__h338479 >> + sfd__h338480 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950 = - sfd__h384181 >> + sfd__h384182 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342 = - sfd__h429876 >> + sfd__h429877 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705 = - medeleg_csr__read__h610369[i__h708478] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 = - mideleg_csr__read__h610464[i__h708638] ; + assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 = + mip_csr__read__h611252 == commitStage_rg_old_mip_csr_val ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716 = + medeleg_csr__read__h610371[i__h709458] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 = + mideleg_csr__read__h610466[i__h709618] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 = 12'd3074 - { 6'd0, @@ -26442,51 +26468,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 = 12'd3970 - { 7'd0, - f2_sfd__h521134[22] ? + f2_sfd__h521135[22] ? 5'd0 : - (f2_sfd__h521134[21] ? + (f2_sfd__h521135[21] ? 5'd1 : - (f2_sfd__h521134[20] ? + (f2_sfd__h521135[20] ? 5'd2 : - (f2_sfd__h521134[19] ? + (f2_sfd__h521135[19] ? 5'd3 : - (f2_sfd__h521134[18] ? + (f2_sfd__h521135[18] ? 5'd4 : - (f2_sfd__h521134[17] ? + (f2_sfd__h521135[17] ? 5'd5 : - (f2_sfd__h521134[16] ? + (f2_sfd__h521135[16] ? 5'd6 : - (f2_sfd__h521134[15] ? + (f2_sfd__h521135[15] ? 5'd7 : - (f2_sfd__h521134[14] ? + (f2_sfd__h521135[14] ? 5'd8 : - (f2_sfd__h521134[13] ? + (f2_sfd__h521135[13] ? 5'd9 : - (f2_sfd__h521134[12] ? + (f2_sfd__h521135[12] ? 5'd10 : - (f2_sfd__h521134[11] ? + (f2_sfd__h521135[11] ? 5'd11 : - (f2_sfd__h521134[10] ? + (f2_sfd__h521135[10] ? 5'd12 : - (f2_sfd__h521134[9] ? + (f2_sfd__h521135[9] ? 5'd13 : - (f2_sfd__h521134[8] ? + (f2_sfd__h521135[8] ? 5'd14 : - (f2_sfd__h521134[7] ? + (f2_sfd__h521135[7] ? 5'd15 : - (f2_sfd__h521134[6] ? + (f2_sfd__h521135[6] ? 5'd16 : - (f2_sfd__h521134[5] ? + (f2_sfd__h521135[5] ? 5'd17 : - (f2_sfd__h521134[4] ? + (f2_sfd__h521135[4] ? 5'd18 : - (f2_sfd__h521134[3] ? + (f2_sfd__h521135[3] ? 5'd19 : - (f2_sfd__h521134[2] ? + (f2_sfd__h521135[2] ? 5'd20 : - (f2_sfd__h521134[1] ? + (f2_sfd__h521135[1] ? 5'd21 : - (f2_sfd__h521134[0] ? + (f2_sfd__h521135[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 = @@ -26500,51 +26526,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 = 12'd3970 - { 7'd0, - f1_sfd__h482140[22] ? + f1_sfd__h482141[22] ? 5'd0 : - (f1_sfd__h482140[21] ? + (f1_sfd__h482141[21] ? 5'd1 : - (f1_sfd__h482140[20] ? + (f1_sfd__h482141[20] ? 5'd2 : - (f1_sfd__h482140[19] ? + (f1_sfd__h482141[19] ? 5'd3 : - (f1_sfd__h482140[18] ? + (f1_sfd__h482141[18] ? 5'd4 : - (f1_sfd__h482140[17] ? + (f1_sfd__h482141[17] ? 5'd5 : - (f1_sfd__h482140[16] ? + (f1_sfd__h482141[16] ? 5'd6 : - (f1_sfd__h482140[15] ? + (f1_sfd__h482141[15] ? 5'd7 : - (f1_sfd__h482140[14] ? + (f1_sfd__h482141[14] ? 5'd8 : - (f1_sfd__h482140[13] ? + (f1_sfd__h482141[13] ? 5'd9 : - (f1_sfd__h482140[12] ? + (f1_sfd__h482141[12] ? 5'd10 : - (f1_sfd__h482140[11] ? + (f1_sfd__h482141[11] ? 5'd11 : - (f1_sfd__h482140[10] ? + (f1_sfd__h482141[10] ? 5'd12 : - (f1_sfd__h482140[9] ? + (f1_sfd__h482141[9] ? 5'd13 : - (f1_sfd__h482140[8] ? + (f1_sfd__h482141[8] ? 5'd14 : - (f1_sfd__h482140[7] ? + (f1_sfd__h482141[7] ? 5'd15 : - (f1_sfd__h482140[6] ? + (f1_sfd__h482141[6] ? 5'd16 : - (f1_sfd__h482140[5] ? + (f1_sfd__h482141[5] ? 5'd17 : - (f1_sfd__h482140[4] ? + (f1_sfd__h482141[4] ? 5'd18 : - (f1_sfd__h482140[3] ? + (f1_sfd__h482141[3] ? 5'd19 : - (f1_sfd__h482140[2] ? + (f1_sfd__h482141[2] ? 5'd20 : - (f1_sfd__h482140[1] ? + (f1_sfd__h482141[1] ? 5'd21 : - (f1_sfd__h482140[0] ? + (f1_sfd__h482141[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 = @@ -26558,51 +26584,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 = 12'd3970 - { 7'd0, - f3_sfd__h560438[22] ? + f3_sfd__h560439[22] ? 5'd0 : - (f3_sfd__h560438[21] ? + (f3_sfd__h560439[21] ? 5'd1 : - (f3_sfd__h560438[20] ? + (f3_sfd__h560439[20] ? 5'd2 : - (f3_sfd__h560438[19] ? + (f3_sfd__h560439[19] ? 5'd3 : - (f3_sfd__h560438[18] ? + (f3_sfd__h560439[18] ? 5'd4 : - (f3_sfd__h560438[17] ? + (f3_sfd__h560439[17] ? 5'd5 : - (f3_sfd__h560438[16] ? + (f3_sfd__h560439[16] ? 5'd6 : - (f3_sfd__h560438[15] ? + (f3_sfd__h560439[15] ? 5'd7 : - (f3_sfd__h560438[14] ? + (f3_sfd__h560439[14] ? 5'd8 : - (f3_sfd__h560438[13] ? + (f3_sfd__h560439[13] ? 5'd9 : - (f3_sfd__h560438[12] ? + (f3_sfd__h560439[12] ? 5'd10 : - (f3_sfd__h560438[11] ? + (f3_sfd__h560439[11] ? 5'd11 : - (f3_sfd__h560438[10] ? + (f3_sfd__h560439[10] ? 5'd12 : - (f3_sfd__h560438[9] ? + (f3_sfd__h560439[9] ? 5'd13 : - (f3_sfd__h560438[8] ? + (f3_sfd__h560439[8] ? 5'd14 : - (f3_sfd__h560438[7] ? + (f3_sfd__h560439[7] ? 5'd15 : - (f3_sfd__h560438[6] ? + (f3_sfd__h560439[6] ? 5'd16 : - (f3_sfd__h560438[5] ? + (f3_sfd__h560439[5] ? 5'd17 : - (f3_sfd__h560438[4] ? + (f3_sfd__h560439[4] ? 5'd18 : - (f3_sfd__h560438[3] ? + (f3_sfd__h560439[3] ? 5'd19 : - (f3_sfd__h560438[2] ? + (f3_sfd__h560439[2] ? 5'd20 : - (f3_sfd__h560438[1] ? + (f3_sfd__h560439[1] ? 5'd21 : - (f3_sfd__h560438[0] ? + (f3_sfd__h560439[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 = @@ -26631,14 +26657,14 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h669623 == 1'd1 && + k__h669625 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == 1'd1 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208 ; assign _dfoo18 = - k__h669623 == 1'd0 && + k__h669625 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == @@ -26653,25 +26679,25 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo20 = - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ; + assign _dfoo22 = + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 ; assign _dfoo24 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo32 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) || rob$deqPort_0_deq_data[329:325] == 5'd19 ; assign _dfoo7 = @@ -26755,1421 +26781,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h296520 = + assign _theResult_____2__h296521 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046) ? - next_deqP___1__h296799 : + next_deqP___1__h296800 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h304516 = + assign _theResult_____2__h304517 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153) ? - next_deqP___1__h304795 : + next_deqP___1__h304796 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h310510 = + assign _theResult_____2__h310511 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324) ? - next_deqP___1__h311076 : + next_deqP___1__h311077 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h318364 = + assign _theResult_____2__h318365 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420) ? - next_deqP___1__h318930 : + next_deqP___1__h318931 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h328708 = + assign _theResult_____2__h328709 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649) ? - next_deqP___1__h328987 : + next_deqP___1__h328988 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h331933 = + assign _theResult_____2__h331934 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743) ? - next_deqP___1__h332212 : + next_deqP___1__h332213 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h346084 = - (value__h346706 == 54'd0) ? sfd__h338479 : 57'd1 ; - assign _theResult____h363723 = + assign _theResult____h346085 = + (value__h346707 == 54'd0) ? sfd__h338480 : 57'd1 ; + assign _theResult____h363724 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ^ 12'h800) < 12'd2105) ? - result__h364336 : - _theResult____h346084 ; - assign _theResult____h391783 = - (value__h392403 == 54'd0) ? sfd__h384181 : 57'd1 ; - assign _theResult____h409420 = + result__h364337 : + _theResult____h346085 ; + assign _theResult____h391784 = + (value__h392404 == 54'd0) ? sfd__h384182 : 57'd1 ; + assign _theResult____h409421 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ^ 12'h800) < 12'd2105) ? - result__h410033 : - _theResult____h391783 ; - assign _theResult____h437478 = - (value__h438098 == 54'd0) ? sfd__h429876 : 57'd1 ; - assign _theResult____h455115 = + result__h410034 : + _theResult____h391784 ; + assign _theResult____h437479 = + (value__h438099 == 54'd0) ? sfd__h429877 : 57'd1 ; + assign _theResult____h455116 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ^ 12'h800) < 12'd2105) ? - result__h455728 : - _theResult____h437478 ; - assign _theResult____h502868 = + result__h455729 : + _theResult____h437479 ; + assign _theResult____h502869 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ^ 12'h800) < 12'd2105) ? - result__h503481 : - ((value__h487084 == 25'd0) ? sfd__h482501 : 57'd1) ; - assign _theResult____h541721 = + result__h503482 : + ((value__h487085 == 25'd0) ? sfd__h482502 : 57'd1) ; + assign _theResult____h541722 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ^ 12'h800) < 12'd2105) ? - result__h542334 : - ((value__h525937 == 25'd0) ? sfd__h521495 : 57'd1) ; - assign _theResult____h581025 = + result__h542335 : + ((value__h525938 == 25'd0) ? sfd__h521496 : 57'd1) ; + assign _theResult____h581026 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ^ 12'h800) < 12'd2105) ? - result__h581638 : - ((value__h565241 == 25'd0) ? sfd__h560799 : 57'd1) ; - assign _theResult____h651116 = + result__h581639 : + ((value__h565242 == 25'd0) ? sfd__h560800 : 57'd1) ; + assign _theResult____h651118 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h651641 : + enabled_ints___1__h651643 : 16'd0 ; - assign _theResult___exp__h354711 = - sfd__h354287[24] ? - ((_theResult___fst_exp__h354195 == 8'd254) ? + assign _theResult___exp__h354712 = + sfd__h354288[24] ? + ((_theResult___fst_exp__h354196 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381228) : - ((_theResult___fst_exp__h354195 == 8'd0 && - sfd__h354287[24:23] == 2'b01) ? + din_inc___2_exp__h381229) : + ((_theResult___fst_exp__h354196 == 8'd0 && + sfd__h354288[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h354195) ; - assign _theResult___exp__h363293 = - sfd__h362869[24] ? - ((_theResult___fst_exp__h362851 == 8'd254) ? + _theResult___fst_exp__h354196) ; + assign _theResult___exp__h363294 = + sfd__h362870[24] ? + ((_theResult___fst_exp__h362852 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381252) : - ((_theResult___fst_exp__h362851 == 8'd0 && - sfd__h362869[24:23] == 2'b01) ? + din_inc___2_exp__h381253) : + ((_theResult___fst_exp__h362852 == 8'd0 && + sfd__h362870[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h362851) ; - assign _theResult___exp__h372477 = - sfd__h372053[24] ? - ((_theResult___fst_exp__h371961 == 8'd254) ? + _theResult___fst_exp__h362852) ; + assign _theResult___exp__h372478 = + sfd__h372054[24] ? + ((_theResult___fst_exp__h371962 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381282) : - ((_theResult___fst_exp__h371961 == 8'd0 && - sfd__h372053[24:23] == 2'b01) ? + din_inc___2_exp__h381283) : + ((_theResult___fst_exp__h371962 == 8'd0 && + sfd__h372054[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h371961) ; - assign _theResult___exp__h381113 = - sfd__h380665[24] ? - ((_theResult___fst_exp__h380646 == 8'd254) ? + _theResult___fst_exp__h371962) ; + assign _theResult___exp__h381114 = + sfd__h380666[24] ? + ((_theResult___fst_exp__h380647 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381306) : - ((_theResult___fst_exp__h380646 == 8'd0 && - sfd__h380665[24:23] == 2'b01) ? + din_inc___2_exp__h381307) : + ((_theResult___fst_exp__h380647 == 8'd0 && + sfd__h380666[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h380646) ; - assign _theResult___exp__h381215 = + _theResult___fst_exp__h380647) ; + assign _theResult___exp__h381216 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381206 ; - assign _theResult___exp__h400408 = - sfd__h399984[24] ? - ((_theResult___fst_exp__h399892 == 8'd254) ? + _theResult___fst_exp__h381207 ; + assign _theResult___exp__h400409 = + sfd__h399985[24] ? + ((_theResult___fst_exp__h399893 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426925) : - ((_theResult___fst_exp__h399892 == 8'd0 && - sfd__h399984[24:23] == 2'b01) ? + din_inc___2_exp__h426926) : + ((_theResult___fst_exp__h399893 == 8'd0 && + sfd__h399985[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h399892) ; - assign _theResult___exp__h408990 = - sfd__h408566[24] ? - ((_theResult___fst_exp__h408548 == 8'd254) ? + _theResult___fst_exp__h399893) ; + assign _theResult___exp__h408991 = + sfd__h408567[24] ? + ((_theResult___fst_exp__h408549 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426949) : - ((_theResult___fst_exp__h408548 == 8'd0 && - sfd__h408566[24:23] == 2'b01) ? + din_inc___2_exp__h426950) : + ((_theResult___fst_exp__h408549 == 8'd0 && + sfd__h408567[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h408548) ; - assign _theResult___exp__h418174 = - sfd__h417750[24] ? - ((_theResult___fst_exp__h417658 == 8'd254) ? + _theResult___fst_exp__h408549) ; + assign _theResult___exp__h418175 = + sfd__h417751[24] ? + ((_theResult___fst_exp__h417659 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426979) : - ((_theResult___fst_exp__h417658 == 8'd0 && - sfd__h417750[24:23] == 2'b01) ? + din_inc___2_exp__h426980) : + ((_theResult___fst_exp__h417659 == 8'd0 && + sfd__h417751[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h417658) ; - assign _theResult___exp__h426810 = - sfd__h426362[24] ? - ((_theResult___fst_exp__h426343 == 8'd254) ? + _theResult___fst_exp__h417659) ; + assign _theResult___exp__h426811 = + sfd__h426363[24] ? + ((_theResult___fst_exp__h426344 == 8'd254) ? 8'd255 : - din_inc___2_exp__h427003) : - ((_theResult___fst_exp__h426343 == 8'd0 && - sfd__h426362[24:23] == 2'b01) ? + din_inc___2_exp__h427004) : + ((_theResult___fst_exp__h426344 == 8'd0 && + sfd__h426363[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h426343) ; - assign _theResult___exp__h426912 = + _theResult___fst_exp__h426344) ; + assign _theResult___exp__h426913 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426903 ; - assign _theResult___exp__h446103 = - sfd__h445679[24] ? - ((_theResult___fst_exp__h445587 == 8'd254) ? + _theResult___fst_exp__h426904 ; + assign _theResult___exp__h446104 = + sfd__h445680[24] ? + ((_theResult___fst_exp__h445588 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472620) : - ((_theResult___fst_exp__h445587 == 8'd0 && - sfd__h445679[24:23] == 2'b01) ? + din_inc___2_exp__h472621) : + ((_theResult___fst_exp__h445588 == 8'd0 && + sfd__h445680[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h445587) ; - assign _theResult___exp__h454685 = - sfd__h454261[24] ? - ((_theResult___fst_exp__h454243 == 8'd254) ? + _theResult___fst_exp__h445588) ; + assign _theResult___exp__h454686 = + sfd__h454262[24] ? + ((_theResult___fst_exp__h454244 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472644) : - ((_theResult___fst_exp__h454243 == 8'd0 && - sfd__h454261[24:23] == 2'b01) ? + din_inc___2_exp__h472645) : + ((_theResult___fst_exp__h454244 == 8'd0 && + sfd__h454262[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h454243) ; - assign _theResult___exp__h463869 = - sfd__h463445[24] ? - ((_theResult___fst_exp__h463353 == 8'd254) ? + _theResult___fst_exp__h454244) ; + assign _theResult___exp__h463870 = + sfd__h463446[24] ? + ((_theResult___fst_exp__h463354 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472674) : - ((_theResult___fst_exp__h463353 == 8'd0 && - sfd__h463445[24:23] == 2'b01) ? + din_inc___2_exp__h472675) : + ((_theResult___fst_exp__h463354 == 8'd0 && + sfd__h463446[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h463353) ; - assign _theResult___exp__h472505 = - sfd__h472057[24] ? - ((_theResult___fst_exp__h472038 == 8'd254) ? + _theResult___fst_exp__h463354) ; + assign _theResult___exp__h472506 = + sfd__h472058[24] ? + ((_theResult___fst_exp__h472039 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472698) : - ((_theResult___fst_exp__h472038 == 8'd0 && - sfd__h472057[24:23] == 2'b01) ? + din_inc___2_exp__h472699) : + ((_theResult___fst_exp__h472039 == 8'd0 && + sfd__h472058[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h472038) ; - assign _theResult___exp__h472607 = + _theResult___fst_exp__h472039) ; + assign _theResult___exp__h472608 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472598 ; - assign _theResult___exp__h502182 = - sfd__h501545[53] ? - ((_theResult___fst_exp__h501527 == 11'd2046) ? + _theResult___fst_exp__h472599 ; + assign _theResult___exp__h502183 = + sfd__h501546[53] ? + ((_theResult___fst_exp__h501528 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520777) : - ((_theResult___fst_exp__h501527 == 11'd0 && - sfd__h501545[53:52] == 2'b01) ? + din_inc___2_exp__h520778) : + ((_theResult___fst_exp__h501528 == 11'd0 && + sfd__h501546[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h501527) ; - assign _theResult___exp__h511833 = - sfd__h511196[53] ? - ((_theResult___fst_exp__h511104 == 11'd2046) ? + _theResult___fst_exp__h501528) ; + assign _theResult___exp__h511834 = + sfd__h511197[53] ? + ((_theResult___fst_exp__h511105 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520812) : - ((_theResult___fst_exp__h511104 == 11'd0 && - sfd__h511196[53:52] == 2'b01) ? + din_inc___2_exp__h520813) : + ((_theResult___fst_exp__h511105 == 11'd0 && + sfd__h511197[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h511104) ; - assign _theResult___exp__h520617 = - sfd__h519956[53] ? - ((_theResult___fst_exp__h519937 == 11'd2046) ? + _theResult___fst_exp__h511105) ; + assign _theResult___exp__h520618 = + sfd__h519957[53] ? + ((_theResult___fst_exp__h519938 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520838) : - ((_theResult___fst_exp__h519937 == 11'd0 && - sfd__h519956[53:52] == 2'b01) ? + din_inc___2_exp__h520839) : + ((_theResult___fst_exp__h519938 == 11'd0 && + sfd__h519957[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h519937) ; - assign _theResult___exp__h541035 = - sfd__h540398[53] ? - ((_theResult___fst_exp__h540380 == 11'd2046) ? + _theResult___fst_exp__h519938) ; + assign _theResult___exp__h541036 = + sfd__h540399[53] ? + ((_theResult___fst_exp__h540381 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559630) : - ((_theResult___fst_exp__h540380 == 11'd0 && - sfd__h540398[53:52] == 2'b01) ? + din_inc___2_exp__h559631) : + ((_theResult___fst_exp__h540381 == 11'd0 && + sfd__h540399[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h540380) ; - assign _theResult___exp__h550686 = - sfd__h550049[53] ? - ((_theResult___fst_exp__h549957 == 11'd2046) ? + _theResult___fst_exp__h540381) ; + assign _theResult___exp__h550687 = + sfd__h550050[53] ? + ((_theResult___fst_exp__h549958 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559665) : - ((_theResult___fst_exp__h549957 == 11'd0 && - sfd__h550049[53:52] == 2'b01) ? + din_inc___2_exp__h559666) : + ((_theResult___fst_exp__h549958 == 11'd0 && + sfd__h550050[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h549957) ; - assign _theResult___exp__h559470 = - sfd__h558809[53] ? - ((_theResult___fst_exp__h558790 == 11'd2046) ? + _theResult___fst_exp__h549958) ; + assign _theResult___exp__h559471 = + sfd__h558810[53] ? + ((_theResult___fst_exp__h558791 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559691) : - ((_theResult___fst_exp__h558790 == 11'd0 && - sfd__h558809[53:52] == 2'b01) ? + din_inc___2_exp__h559692) : + ((_theResult___fst_exp__h558791 == 11'd0 && + sfd__h558810[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h558790) ; - assign _theResult___exp__h580339 = - sfd__h579702[53] ? - ((_theResult___fst_exp__h579684 == 11'd2046) ? + _theResult___fst_exp__h558791) ; + assign _theResult___exp__h580340 = + sfd__h579703[53] ? + ((_theResult___fst_exp__h579685 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598934) : - ((_theResult___fst_exp__h579684 == 11'd0 && - sfd__h579702[53:52] == 2'b01) ? + din_inc___2_exp__h598935) : + ((_theResult___fst_exp__h579685 == 11'd0 && + sfd__h579703[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h579684) ; - assign _theResult___exp__h589990 = - sfd__h589353[53] ? - ((_theResult___fst_exp__h589261 == 11'd2046) ? + _theResult___fst_exp__h579685) ; + assign _theResult___exp__h589991 = + sfd__h589354[53] ? + ((_theResult___fst_exp__h589262 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598969) : - ((_theResult___fst_exp__h589261 == 11'd0 && - sfd__h589353[53:52] == 2'b01) ? + din_inc___2_exp__h598970) : + ((_theResult___fst_exp__h589262 == 11'd0 && + sfd__h589354[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h589261) ; - assign _theResult___exp__h598774 = - sfd__h598113[53] ? - ((_theResult___fst_exp__h598094 == 11'd2046) ? + _theResult___fst_exp__h589262) ; + assign _theResult___exp__h598775 = + sfd__h598114[53] ? + ((_theResult___fst_exp__h598095 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598995) : - ((_theResult___fst_exp__h598094 == 11'd0 && - sfd__h598113[53:52] == 2'b01) ? + din_inc___2_exp__h598996) : + ((_theResult___fst_exp__h598095 == 11'd0 && + sfd__h598114[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h598094) ; - assign _theResult___fst__h603369 = - a__h602947[63] ? a___1__h603374 : a__h602947 ; - assign _theResult___fst_exp__h354195 = - _theResult____h346084[56] ? + _theResult___fst_exp__h598095) ; + assign _theResult___fst__h603370 = + a__h602948[63] ? a___1__h603375 : a__h602948 ; + assign _theResult___fst_exp__h354196 = + _theResult____h346085[56] ? 8'd2 : - _theResult___fst_exp__h354269 ; - assign _theResult___fst_exp__h354260 = + _theResult___fst_exp__h354270 ; + assign _theResult___fst_exp__h354261 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ; - assign _theResult___fst_exp__h354266 = - (!_theResult____h346084[56] && !_theResult____h346084[55] && - !_theResult____h346084[54] && - !_theResult____h346084[53] && - !_theResult____h346084[52] && - !_theResult____h346084[51] && - !_theResult____h346084[50] && - !_theResult____h346084[49] && - !_theResult____h346084[48] && - !_theResult____h346084[47] && - !_theResult____h346084[46] && - !_theResult____h346084[45] && - !_theResult____h346084[44] && - !_theResult____h346084[43] && - !_theResult____h346084[42] && - !_theResult____h346084[41] && - !_theResult____h346084[40] && - !_theResult____h346084[39] && - !_theResult____h346084[38] && - !_theResult____h346084[37] && - !_theResult____h346084[36] && - !_theResult____h346084[35] && - !_theResult____h346084[34] && - !_theResult____h346084[33] && - !_theResult____h346084[32] && - !_theResult____h346084[31] && - !_theResult____h346084[30] && - !_theResult____h346084[29] && - !_theResult____h346084[28] && - !_theResult____h346084[27] && - !_theResult____h346084[26] && - !_theResult____h346084[25] && - !_theResult____h346084[24] && - !_theResult____h346084[23] && - !_theResult____h346084[22] && - !_theResult____h346084[21] && - !_theResult____h346084[20] && - !_theResult____h346084[19] && - !_theResult____h346084[18] && - !_theResult____h346084[17] && - !_theResult____h346084[16] && - !_theResult____h346084[15] && - !_theResult____h346084[14] && - !_theResult____h346084[13] && - !_theResult____h346084[12] && - !_theResult____h346084[11] && - !_theResult____h346084[10] && - !_theResult____h346084[9] && - !_theResult____h346084[8] && - !_theResult____h346084[7] && - !_theResult____h346084[6] && - !_theResult____h346084[5] && - !_theResult____h346084[4] && - !_theResult____h346084[3] && - !_theResult____h346084[2] && - !_theResult____h346084[1] && - !_theResult____h346084[0] || + assign _theResult___fst_exp__h354267 = + (!_theResult____h346085[56] && !_theResult____h346085[55] && + !_theResult____h346085[54] && + !_theResult____h346085[53] && + !_theResult____h346085[52] && + !_theResult____h346085[51] && + !_theResult____h346085[50] && + !_theResult____h346085[49] && + !_theResult____h346085[48] && + !_theResult____h346085[47] && + !_theResult____h346085[46] && + !_theResult____h346085[45] && + !_theResult____h346085[44] && + !_theResult____h346085[43] && + !_theResult____h346085[42] && + !_theResult____h346085[41] && + !_theResult____h346085[40] && + !_theResult____h346085[39] && + !_theResult____h346085[38] && + !_theResult____h346085[37] && + !_theResult____h346085[36] && + !_theResult____h346085[35] && + !_theResult____h346085[34] && + !_theResult____h346085[33] && + !_theResult____h346085[32] && + !_theResult____h346085[31] && + !_theResult____h346085[30] && + !_theResult____h346085[29] && + !_theResult____h346085[28] && + !_theResult____h346085[27] && + !_theResult____h346085[26] && + !_theResult____h346085[25] && + !_theResult____h346085[24] && + !_theResult____h346085[23] && + !_theResult____h346085[22] && + !_theResult____h346085[21] && + !_theResult____h346085[20] && + !_theResult____h346085[19] && + !_theResult____h346085[18] && + !_theResult____h346085[17] && + !_theResult____h346085[16] && + !_theResult____h346085[15] && + !_theResult____h346085[14] && + !_theResult____h346085[13] && + !_theResult____h346085[12] && + !_theResult____h346085[11] && + !_theResult____h346085[10] && + !_theResult____h346085[9] && + !_theResult____h346085[8] && + !_theResult____h346085[7] && + !_theResult____h346085[6] && + !_theResult____h346085[5] && + !_theResult____h346085[4] && + !_theResult____h346085[3] && + !_theResult____h346085[2] && + !_theResult____h346085[1] && + !_theResult____h346085[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249) ? 8'd0 : - _theResult___fst_exp__h354260 ; - assign _theResult___fst_exp__h354269 = - (!_theResult____h346084[56] && _theResult____h346084[55]) ? + _theResult___fst_exp__h354261 ; + assign _theResult___fst_exp__h354270 = + (!_theResult____h346085[56] && _theResult____h346085[55]) ? 8'd1 : - _theResult___fst_exp__h354266 ; - assign _theResult___fst_exp__h354792 = - (_theResult___fst_exp__h354195 == 8'd255) ? - _theResult___fst_exp__h354195 : - _theResult___fst_exp__h354789 ; - assign _theResult___fst_exp__h362842 = + _theResult___fst_exp__h354267 ; + assign _theResult___fst_exp__h354793 = + (_theResult___fst_exp__h354196 == 8'd255) ? + _theResult___fst_exp__h354196 : + _theResult___fst_exp__h354790 ; + assign _theResult___fst_exp__h362843 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h362848 = + assign _theResult___fst_exp__h362849 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480) ? 8'd0 : - _theResult___fst_exp__h362842 ; - assign _theResult___fst_exp__h362851 = + _theResult___fst_exp__h362843 ; + assign _theResult___fst_exp__h362852 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h362848 : + _theResult___fst_exp__h362849 : 8'd129 ; - assign _theResult___fst_exp__h363374 = - (_theResult___fst_exp__h362851 == 8'd255) ? - _theResult___fst_exp__h362851 : - _theResult___fst_exp__h363371 ; - assign _theResult___fst_exp__h371961 = - _theResult____h363723[56] ? + assign _theResult___fst_exp__h363375 = + (_theResult___fst_exp__h362852 == 8'd255) ? + _theResult___fst_exp__h362852 : + _theResult___fst_exp__h363372 ; + assign _theResult___fst_exp__h371962 = + _theResult____h363724[56] ? 8'd2 : - _theResult___fst_exp__h372035 ; - assign _theResult___fst_exp__h372026 = + _theResult___fst_exp__h372036 ; + assign _theResult___fst_exp__h372027 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ; - assign _theResult___fst_exp__h372032 = - (!_theResult____h363723[56] && !_theResult____h363723[55] && - !_theResult____h363723[54] && - !_theResult____h363723[53] && - !_theResult____h363723[52] && - !_theResult____h363723[51] && - !_theResult____h363723[50] && - !_theResult____h363723[49] && - !_theResult____h363723[48] && - !_theResult____h363723[47] && - !_theResult____h363723[46] && - !_theResult____h363723[45] && - !_theResult____h363723[44] && - !_theResult____h363723[43] && - !_theResult____h363723[42] && - !_theResult____h363723[41] && - !_theResult____h363723[40] && - !_theResult____h363723[39] && - !_theResult____h363723[38] && - !_theResult____h363723[37] && - !_theResult____h363723[36] && - !_theResult____h363723[35] && - !_theResult____h363723[34] && - !_theResult____h363723[33] && - !_theResult____h363723[32] && - !_theResult____h363723[31] && - !_theResult____h363723[30] && - !_theResult____h363723[29] && - !_theResult____h363723[28] && - !_theResult____h363723[27] && - !_theResult____h363723[26] && - !_theResult____h363723[25] && - !_theResult____h363723[24] && - !_theResult____h363723[23] && - !_theResult____h363723[22] && - !_theResult____h363723[21] && - !_theResult____h363723[20] && - !_theResult____h363723[19] && - !_theResult____h363723[18] && - !_theResult____h363723[17] && - !_theResult____h363723[16] && - !_theResult____h363723[15] && - !_theResult____h363723[14] && - !_theResult____h363723[13] && - !_theResult____h363723[12] && - !_theResult____h363723[11] && - !_theResult____h363723[10] && - !_theResult____h363723[9] && - !_theResult____h363723[8] && - !_theResult____h363723[7] && - !_theResult____h363723[6] && - !_theResult____h363723[5] && - !_theResult____h363723[4] && - !_theResult____h363723[3] && - !_theResult____h363723[2] && - !_theResult____h363723[1] && - !_theResult____h363723[0] || + assign _theResult___fst_exp__h372033 = + (!_theResult____h363724[56] && !_theResult____h363724[55] && + !_theResult____h363724[54] && + !_theResult____h363724[53] && + !_theResult____h363724[52] && + !_theResult____h363724[51] && + !_theResult____h363724[50] && + !_theResult____h363724[49] && + !_theResult____h363724[48] && + !_theResult____h363724[47] && + !_theResult____h363724[46] && + !_theResult____h363724[45] && + !_theResult____h363724[44] && + !_theResult____h363724[43] && + !_theResult____h363724[42] && + !_theResult____h363724[41] && + !_theResult____h363724[40] && + !_theResult____h363724[39] && + !_theResult____h363724[38] && + !_theResult____h363724[37] && + !_theResult____h363724[36] && + !_theResult____h363724[35] && + !_theResult____h363724[34] && + !_theResult____h363724[33] && + !_theResult____h363724[32] && + !_theResult____h363724[31] && + !_theResult____h363724[30] && + !_theResult____h363724[29] && + !_theResult____h363724[28] && + !_theResult____h363724[27] && + !_theResult____h363724[26] && + !_theResult____h363724[25] && + !_theResult____h363724[24] && + !_theResult____h363724[23] && + !_theResult____h363724[22] && + !_theResult____h363724[21] && + !_theResult____h363724[20] && + !_theResult____h363724[19] && + !_theResult____h363724[18] && + !_theResult____h363724[17] && + !_theResult____h363724[16] && + !_theResult____h363724[15] && + !_theResult____h363724[14] && + !_theResult____h363724[13] && + !_theResult____h363724[12] && + !_theResult____h363724[11] && + !_theResult____h363724[10] && + !_theResult____h363724[9] && + !_theResult____h363724[8] && + !_theResult____h363724[7] && + !_theResult____h363724[6] && + !_theResult____h363724[5] && + !_theResult____h363724[4] && + !_theResult____h363724[3] && + !_theResult____h363724[2] && + !_theResult____h363724[1] && + !_theResult____h363724[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800) ? 8'd0 : - _theResult___fst_exp__h372026 ; - assign _theResult___fst_exp__h372035 = - (!_theResult____h363723[56] && _theResult____h363723[55]) ? + _theResult___fst_exp__h372027 ; + assign _theResult___fst_exp__h372036 = + (!_theResult____h363724[56] && _theResult____h363724[55]) ? 8'd1 : - _theResult___fst_exp__h372032 ; - assign _theResult___fst_exp__h372558 = - (_theResult___fst_exp__h371961 == 8'd255) ? - _theResult___fst_exp__h371961 : - _theResult___fst_exp__h372555 ; - assign _theResult___fst_exp__h380598 = + _theResult___fst_exp__h372033 ; + assign _theResult___fst_exp__h372559 = + (_theResult___fst_exp__h371962 == 8'd255) ? + _theResult___fst_exp__h371962 : + _theResult___fst_exp__h372556 ; + assign _theResult___fst_exp__h380599 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ; - assign _theResult___fst_exp__h380637 = + assign _theResult___fst_exp__h380638 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h380643 = + assign _theResult___fst_exp__h380644 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873) ? 8'd0 : - _theResult___fst_exp__h380637 ; - assign _theResult___fst_exp__h380646 = + _theResult___fst_exp__h380638 ; + assign _theResult___fst_exp__h380647 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h380643 : - _theResult___fst_exp__h380598 ; - assign _theResult___fst_exp__h381194 = - (_theResult___fst_exp__h380646 == 8'd255) ? - _theResult___fst_exp__h380646 : - _theResult___fst_exp__h381191 ; - assign _theResult___fst_exp__h381203 = + _theResult___fst_exp__h380644 : + _theResult___fst_exp__h380599 ; + assign _theResult___fst_exp__h381195 = + (_theResult___fst_exp__h380647 == 8'd255) ? + _theResult___fst_exp__h380647 : + _theResult___fst_exp__h381192 ; + assign _theResult___fst_exp__h381204 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_exp__h363377 : - _theResult___fst_exp__h346066) : + _theResult___snd_fst_exp__h363378 : + _theResult___fst_exp__h346067) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_exp__h381197 : - _theResult___fst_exp__h346066) ; - assign _theResult___fst_exp__h381206 = + _theResult___snd_fst_exp__h381198 : + _theResult___fst_exp__h346067) ; + assign _theResult___fst_exp__h381207 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h381203 ; - assign _theResult___fst_exp__h399892 = - _theResult____h391783[56] ? + _theResult___fst_exp__h381204 ; + assign _theResult___fst_exp__h399893 = + _theResult____h391784[56] ? 8'd2 : - _theResult___fst_exp__h399966 ; - assign _theResult___fst_exp__h399957 = + _theResult___fst_exp__h399967 ; + assign _theResult___fst_exp__h399958 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ; - assign _theResult___fst_exp__h399963 = - (!_theResult____h391783[56] && !_theResult____h391783[55] && - !_theResult____h391783[54] && - !_theResult____h391783[53] && - !_theResult____h391783[52] && - !_theResult____h391783[51] && - !_theResult____h391783[50] && - !_theResult____h391783[49] && - !_theResult____h391783[48] && - !_theResult____h391783[47] && - !_theResult____h391783[46] && - !_theResult____h391783[45] && - !_theResult____h391783[44] && - !_theResult____h391783[43] && - !_theResult____h391783[42] && - !_theResult____h391783[41] && - !_theResult____h391783[40] && - !_theResult____h391783[39] && - !_theResult____h391783[38] && - !_theResult____h391783[37] && - !_theResult____h391783[36] && - !_theResult____h391783[35] && - !_theResult____h391783[34] && - !_theResult____h391783[33] && - !_theResult____h391783[32] && - !_theResult____h391783[31] && - !_theResult____h391783[30] && - !_theResult____h391783[29] && - !_theResult____h391783[28] && - !_theResult____h391783[27] && - !_theResult____h391783[26] && - !_theResult____h391783[25] && - !_theResult____h391783[24] && - !_theResult____h391783[23] && - !_theResult____h391783[22] && - !_theResult____h391783[21] && - !_theResult____h391783[20] && - !_theResult____h391783[19] && - !_theResult____h391783[18] && - !_theResult____h391783[17] && - !_theResult____h391783[16] && - !_theResult____h391783[15] && - !_theResult____h391783[14] && - !_theResult____h391783[13] && - !_theResult____h391783[12] && - !_theResult____h391783[11] && - !_theResult____h391783[10] && - !_theResult____h391783[9] && - !_theResult____h391783[8] && - !_theResult____h391783[7] && - !_theResult____h391783[6] && - !_theResult____h391783[5] && - !_theResult____h391783[4] && - !_theResult____h391783[3] && - !_theResult____h391783[2] && - !_theResult____h391783[1] && - !_theResult____h391783[0] || + assign _theResult___fst_exp__h399964 = + (!_theResult____h391784[56] && !_theResult____h391784[55] && + !_theResult____h391784[54] && + !_theResult____h391784[53] && + !_theResult____h391784[52] && + !_theResult____h391784[51] && + !_theResult____h391784[50] && + !_theResult____h391784[49] && + !_theResult____h391784[48] && + !_theResult____h391784[47] && + !_theResult____h391784[46] && + !_theResult____h391784[45] && + !_theResult____h391784[44] && + !_theResult____h391784[43] && + !_theResult____h391784[42] && + !_theResult____h391784[41] && + !_theResult____h391784[40] && + !_theResult____h391784[39] && + !_theResult____h391784[38] && + !_theResult____h391784[37] && + !_theResult____h391784[36] && + !_theResult____h391784[35] && + !_theResult____h391784[34] && + !_theResult____h391784[33] && + !_theResult____h391784[32] && + !_theResult____h391784[31] && + !_theResult____h391784[30] && + !_theResult____h391784[29] && + !_theResult____h391784[28] && + !_theResult____h391784[27] && + !_theResult____h391784[26] && + !_theResult____h391784[25] && + !_theResult____h391784[24] && + !_theResult____h391784[23] && + !_theResult____h391784[22] && + !_theResult____h391784[21] && + !_theResult____h391784[20] && + !_theResult____h391784[19] && + !_theResult____h391784[18] && + !_theResult____h391784[17] && + !_theResult____h391784[16] && + !_theResult____h391784[15] && + !_theResult____h391784[14] && + !_theResult____h391784[13] && + !_theResult____h391784[12] && + !_theResult____h391784[11] && + !_theResult____h391784[10] && + !_theResult____h391784[9] && + !_theResult____h391784[8] && + !_theResult____h391784[7] && + !_theResult____h391784[6] && + !_theResult____h391784[5] && + !_theResult____h391784[4] && + !_theResult____h391784[3] && + !_theResult____h391784[2] && + !_theResult____h391784[1] && + !_theResult____h391784[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641) ? 8'd0 : - _theResult___fst_exp__h399957 ; - assign _theResult___fst_exp__h399966 = - (!_theResult____h391783[56] && _theResult____h391783[55]) ? + _theResult___fst_exp__h399958 ; + assign _theResult___fst_exp__h399967 = + (!_theResult____h391784[56] && _theResult____h391784[55]) ? 8'd1 : - _theResult___fst_exp__h399963 ; - assign _theResult___fst_exp__h400489 = - (_theResult___fst_exp__h399892 == 8'd255) ? - _theResult___fst_exp__h399892 : - _theResult___fst_exp__h400486 ; - assign _theResult___fst_exp__h408539 = + _theResult___fst_exp__h399964 ; + assign _theResult___fst_exp__h400490 = + (_theResult___fst_exp__h399893 == 8'd255) ? + _theResult___fst_exp__h399893 : + _theResult___fst_exp__h400487 ; + assign _theResult___fst_exp__h408540 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h408545 = + assign _theResult___fst_exp__h408546 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872) ? 8'd0 : - _theResult___fst_exp__h408539 ; - assign _theResult___fst_exp__h408548 = + _theResult___fst_exp__h408540 ; + assign _theResult___fst_exp__h408549 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h408545 : + _theResult___fst_exp__h408546 : 8'd129 ; - assign _theResult___fst_exp__h409071 = - (_theResult___fst_exp__h408548 == 8'd255) ? - _theResult___fst_exp__h408548 : - _theResult___fst_exp__h409068 ; - assign _theResult___fst_exp__h417658 = - _theResult____h409420[56] ? + assign _theResult___fst_exp__h409072 = + (_theResult___fst_exp__h408549 == 8'd255) ? + _theResult___fst_exp__h408549 : + _theResult___fst_exp__h409069 ; + assign _theResult___fst_exp__h417659 = + _theResult____h409421[56] ? 8'd2 : - _theResult___fst_exp__h417732 ; - assign _theResult___fst_exp__h417723 = + _theResult___fst_exp__h417733 ; + assign _theResult___fst_exp__h417724 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ; - assign _theResult___fst_exp__h417729 = - (!_theResult____h409420[56] && !_theResult____h409420[55] && - !_theResult____h409420[54] && - !_theResult____h409420[53] && - !_theResult____h409420[52] && - !_theResult____h409420[51] && - !_theResult____h409420[50] && - !_theResult____h409420[49] && - !_theResult____h409420[48] && - !_theResult____h409420[47] && - !_theResult____h409420[46] && - !_theResult____h409420[45] && - !_theResult____h409420[44] && - !_theResult____h409420[43] && - !_theResult____h409420[42] && - !_theResult____h409420[41] && - !_theResult____h409420[40] && - !_theResult____h409420[39] && - !_theResult____h409420[38] && - !_theResult____h409420[37] && - !_theResult____h409420[36] && - !_theResult____h409420[35] && - !_theResult____h409420[34] && - !_theResult____h409420[33] && - !_theResult____h409420[32] && - !_theResult____h409420[31] && - !_theResult____h409420[30] && - !_theResult____h409420[29] && - !_theResult____h409420[28] && - !_theResult____h409420[27] && - !_theResult____h409420[26] && - !_theResult____h409420[25] && - !_theResult____h409420[24] && - !_theResult____h409420[23] && - !_theResult____h409420[22] && - !_theResult____h409420[21] && - !_theResult____h409420[20] && - !_theResult____h409420[19] && - !_theResult____h409420[18] && - !_theResult____h409420[17] && - !_theResult____h409420[16] && - !_theResult____h409420[15] && - !_theResult____h409420[14] && - !_theResult____h409420[13] && - !_theResult____h409420[12] && - !_theResult____h409420[11] && - !_theResult____h409420[10] && - !_theResult____h409420[9] && - !_theResult____h409420[8] && - !_theResult____h409420[7] && - !_theResult____h409420[6] && - !_theResult____h409420[5] && - !_theResult____h409420[4] && - !_theResult____h409420[3] && - !_theResult____h409420[2] && - !_theResult____h409420[1] && - !_theResult____h409420[0] || + assign _theResult___fst_exp__h417730 = + (!_theResult____h409421[56] && !_theResult____h409421[55] && + !_theResult____h409421[54] && + !_theResult____h409421[53] && + !_theResult____h409421[52] && + !_theResult____h409421[51] && + !_theResult____h409421[50] && + !_theResult____h409421[49] && + !_theResult____h409421[48] && + !_theResult____h409421[47] && + !_theResult____h409421[46] && + !_theResult____h409421[45] && + !_theResult____h409421[44] && + !_theResult____h409421[43] && + !_theResult____h409421[42] && + !_theResult____h409421[41] && + !_theResult____h409421[40] && + !_theResult____h409421[39] && + !_theResult____h409421[38] && + !_theResult____h409421[37] && + !_theResult____h409421[36] && + !_theResult____h409421[35] && + !_theResult____h409421[34] && + !_theResult____h409421[33] && + !_theResult____h409421[32] && + !_theResult____h409421[31] && + !_theResult____h409421[30] && + !_theResult____h409421[29] && + !_theResult____h409421[28] && + !_theResult____h409421[27] && + !_theResult____h409421[26] && + !_theResult____h409421[25] && + !_theResult____h409421[24] && + !_theResult____h409421[23] && + !_theResult____h409421[22] && + !_theResult____h409421[21] && + !_theResult____h409421[20] && + !_theResult____h409421[19] && + !_theResult____h409421[18] && + !_theResult____h409421[17] && + !_theResult____h409421[16] && + !_theResult____h409421[15] && + !_theResult____h409421[14] && + !_theResult____h409421[13] && + !_theResult____h409421[12] && + !_theResult____h409421[11] && + !_theResult____h409421[10] && + !_theResult____h409421[9] && + !_theResult____h409421[8] && + !_theResult____h409421[7] && + !_theResult____h409421[6] && + !_theResult____h409421[5] && + !_theResult____h409421[4] && + !_theResult____h409421[3] && + !_theResult____h409421[2] && + !_theResult____h409421[1] && + !_theResult____h409421[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192) ? 8'd0 : - _theResult___fst_exp__h417723 ; - assign _theResult___fst_exp__h417732 = - (!_theResult____h409420[56] && _theResult____h409420[55]) ? + _theResult___fst_exp__h417724 ; + assign _theResult___fst_exp__h417733 = + (!_theResult____h409421[56] && _theResult____h409421[55]) ? 8'd1 : - _theResult___fst_exp__h417729 ; - assign _theResult___fst_exp__h418255 = - (_theResult___fst_exp__h417658 == 8'd255) ? - _theResult___fst_exp__h417658 : - _theResult___fst_exp__h418252 ; - assign _theResult___fst_exp__h426295 = + _theResult___fst_exp__h417730 ; + assign _theResult___fst_exp__h418256 = + (_theResult___fst_exp__h417659 == 8'd255) ? + _theResult___fst_exp__h417659 : + _theResult___fst_exp__h418253 ; + assign _theResult___fst_exp__h426296 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ; - assign _theResult___fst_exp__h426334 = + assign _theResult___fst_exp__h426335 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h426340 = + assign _theResult___fst_exp__h426341 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265) ? 8'd0 : - _theResult___fst_exp__h426334 ; - assign _theResult___fst_exp__h426343 = + _theResult___fst_exp__h426335 ; + assign _theResult___fst_exp__h426344 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h426340 : - _theResult___fst_exp__h426295 ; - assign _theResult___fst_exp__h426891 = - (_theResult___fst_exp__h426343 == 8'd255) ? - _theResult___fst_exp__h426343 : - _theResult___fst_exp__h426888 ; - assign _theResult___fst_exp__h426900 = + _theResult___fst_exp__h426341 : + _theResult___fst_exp__h426296 ; + assign _theResult___fst_exp__h426892 = + (_theResult___fst_exp__h426344 == 8'd255) ? + _theResult___fst_exp__h426344 : + _theResult___fst_exp__h426889 ; + assign _theResult___fst_exp__h426901 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_exp__h409074 : - _theResult___fst_exp__h391765) : + _theResult___snd_fst_exp__h409075 : + _theResult___fst_exp__h391766) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_exp__h426894 : - _theResult___fst_exp__h391765) ; - assign _theResult___fst_exp__h426903 = + _theResult___snd_fst_exp__h426895 : + _theResult___fst_exp__h391766) ; + assign _theResult___fst_exp__h426904 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h426900 ; - assign _theResult___fst_exp__h445587 = - _theResult____h437478[56] ? + _theResult___fst_exp__h426901 ; + assign _theResult___fst_exp__h445588 = + _theResult____h437479[56] ? 8'd2 : - _theResult___fst_exp__h445661 ; - assign _theResult___fst_exp__h445652 = + _theResult___fst_exp__h445662 ; + assign _theResult___fst_exp__h445653 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ; - assign _theResult___fst_exp__h445658 = - (!_theResult____h437478[56] && !_theResult____h437478[55] && - !_theResult____h437478[54] && - !_theResult____h437478[53] && - !_theResult____h437478[52] && - !_theResult____h437478[51] && - !_theResult____h437478[50] && - !_theResult____h437478[49] && - !_theResult____h437478[48] && - !_theResult____h437478[47] && - !_theResult____h437478[46] && - !_theResult____h437478[45] && - !_theResult____h437478[44] && - !_theResult____h437478[43] && - !_theResult____h437478[42] && - !_theResult____h437478[41] && - !_theResult____h437478[40] && - !_theResult____h437478[39] && - !_theResult____h437478[38] && - !_theResult____h437478[37] && - !_theResult____h437478[36] && - !_theResult____h437478[35] && - !_theResult____h437478[34] && - !_theResult____h437478[33] && - !_theResult____h437478[32] && - !_theResult____h437478[31] && - !_theResult____h437478[30] && - !_theResult____h437478[29] && - !_theResult____h437478[28] && - !_theResult____h437478[27] && - !_theResult____h437478[26] && - !_theResult____h437478[25] && - !_theResult____h437478[24] && - !_theResult____h437478[23] && - !_theResult____h437478[22] && - !_theResult____h437478[21] && - !_theResult____h437478[20] && - !_theResult____h437478[19] && - !_theResult____h437478[18] && - !_theResult____h437478[17] && - !_theResult____h437478[16] && - !_theResult____h437478[15] && - !_theResult____h437478[14] && - !_theResult____h437478[13] && - !_theResult____h437478[12] && - !_theResult____h437478[11] && - !_theResult____h437478[10] && - !_theResult____h437478[9] && - !_theResult____h437478[8] && - !_theResult____h437478[7] && - !_theResult____h437478[6] && - !_theResult____h437478[5] && - !_theResult____h437478[4] && - !_theResult____h437478[3] && - !_theResult____h437478[2] && - !_theResult____h437478[1] && - !_theResult____h437478[0] || + assign _theResult___fst_exp__h445659 = + (!_theResult____h437479[56] && !_theResult____h437479[55] && + !_theResult____h437479[54] && + !_theResult____h437479[53] && + !_theResult____h437479[52] && + !_theResult____h437479[51] && + !_theResult____h437479[50] && + !_theResult____h437479[49] && + !_theResult____h437479[48] && + !_theResult____h437479[47] && + !_theResult____h437479[46] && + !_theResult____h437479[45] && + !_theResult____h437479[44] && + !_theResult____h437479[43] && + !_theResult____h437479[42] && + !_theResult____h437479[41] && + !_theResult____h437479[40] && + !_theResult____h437479[39] && + !_theResult____h437479[38] && + !_theResult____h437479[37] && + !_theResult____h437479[36] && + !_theResult____h437479[35] && + !_theResult____h437479[34] && + !_theResult____h437479[33] && + !_theResult____h437479[32] && + !_theResult____h437479[31] && + !_theResult____h437479[30] && + !_theResult____h437479[29] && + !_theResult____h437479[28] && + !_theResult____h437479[27] && + !_theResult____h437479[26] && + !_theResult____h437479[25] && + !_theResult____h437479[24] && + !_theResult____h437479[23] && + !_theResult____h437479[22] && + !_theResult____h437479[21] && + !_theResult____h437479[20] && + !_theResult____h437479[19] && + !_theResult____h437479[18] && + !_theResult____h437479[17] && + !_theResult____h437479[16] && + !_theResult____h437479[15] && + !_theResult____h437479[14] && + !_theResult____h437479[13] && + !_theResult____h437479[12] && + !_theResult____h437479[11] && + !_theResult____h437479[10] && + !_theResult____h437479[9] && + !_theResult____h437479[8] && + !_theResult____h437479[7] && + !_theResult____h437479[6] && + !_theResult____h437479[5] && + !_theResult____h437479[4] && + !_theResult____h437479[3] && + !_theResult____h437479[2] && + !_theResult____h437479[1] && + !_theResult____h437479[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033) ? 8'd0 : - _theResult___fst_exp__h445652 ; - assign _theResult___fst_exp__h445661 = - (!_theResult____h437478[56] && _theResult____h437478[55]) ? + _theResult___fst_exp__h445653 ; + assign _theResult___fst_exp__h445662 = + (!_theResult____h437479[56] && _theResult____h437479[55]) ? 8'd1 : - _theResult___fst_exp__h445658 ; - assign _theResult___fst_exp__h446184 = - (_theResult___fst_exp__h445587 == 8'd255) ? - _theResult___fst_exp__h445587 : - _theResult___fst_exp__h446181 ; - assign _theResult___fst_exp__h454234 = + _theResult___fst_exp__h445659 ; + assign _theResult___fst_exp__h446185 = + (_theResult___fst_exp__h445588 == 8'd255) ? + _theResult___fst_exp__h445588 : + _theResult___fst_exp__h446182 ; + assign _theResult___fst_exp__h454235 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h454240 = + assign _theResult___fst_exp__h454241 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264) ? 8'd0 : - _theResult___fst_exp__h454234 ; - assign _theResult___fst_exp__h454243 = + _theResult___fst_exp__h454235 ; + assign _theResult___fst_exp__h454244 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h454240 : + _theResult___fst_exp__h454241 : 8'd129 ; - assign _theResult___fst_exp__h454766 = - (_theResult___fst_exp__h454243 == 8'd255) ? - _theResult___fst_exp__h454243 : - _theResult___fst_exp__h454763 ; - assign _theResult___fst_exp__h463353 = - _theResult____h455115[56] ? + assign _theResult___fst_exp__h454767 = + (_theResult___fst_exp__h454244 == 8'd255) ? + _theResult___fst_exp__h454244 : + _theResult___fst_exp__h454764 ; + assign _theResult___fst_exp__h463354 = + _theResult____h455116[56] ? 8'd2 : - _theResult___fst_exp__h463427 ; - assign _theResult___fst_exp__h463418 = + _theResult___fst_exp__h463428 ; + assign _theResult___fst_exp__h463419 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ; - assign _theResult___fst_exp__h463424 = - (!_theResult____h455115[56] && !_theResult____h455115[55] && - !_theResult____h455115[54] && - !_theResult____h455115[53] && - !_theResult____h455115[52] && - !_theResult____h455115[51] && - !_theResult____h455115[50] && - !_theResult____h455115[49] && - !_theResult____h455115[48] && - !_theResult____h455115[47] && - !_theResult____h455115[46] && - !_theResult____h455115[45] && - !_theResult____h455115[44] && - !_theResult____h455115[43] && - !_theResult____h455115[42] && - !_theResult____h455115[41] && - !_theResult____h455115[40] && - !_theResult____h455115[39] && - !_theResult____h455115[38] && - !_theResult____h455115[37] && - !_theResult____h455115[36] && - !_theResult____h455115[35] && - !_theResult____h455115[34] && - !_theResult____h455115[33] && - !_theResult____h455115[32] && - !_theResult____h455115[31] && - !_theResult____h455115[30] && - !_theResult____h455115[29] && - !_theResult____h455115[28] && - !_theResult____h455115[27] && - !_theResult____h455115[26] && - !_theResult____h455115[25] && - !_theResult____h455115[24] && - !_theResult____h455115[23] && - !_theResult____h455115[22] && - !_theResult____h455115[21] && - !_theResult____h455115[20] && - !_theResult____h455115[19] && - !_theResult____h455115[18] && - !_theResult____h455115[17] && - !_theResult____h455115[16] && - !_theResult____h455115[15] && - !_theResult____h455115[14] && - !_theResult____h455115[13] && - !_theResult____h455115[12] && - !_theResult____h455115[11] && - !_theResult____h455115[10] && - !_theResult____h455115[9] && - !_theResult____h455115[8] && - !_theResult____h455115[7] && - !_theResult____h455115[6] && - !_theResult____h455115[5] && - !_theResult____h455115[4] && - !_theResult____h455115[3] && - !_theResult____h455115[2] && - !_theResult____h455115[1] && - !_theResult____h455115[0] || + assign _theResult___fst_exp__h463425 = + (!_theResult____h455116[56] && !_theResult____h455116[55] && + !_theResult____h455116[54] && + !_theResult____h455116[53] && + !_theResult____h455116[52] && + !_theResult____h455116[51] && + !_theResult____h455116[50] && + !_theResult____h455116[49] && + !_theResult____h455116[48] && + !_theResult____h455116[47] && + !_theResult____h455116[46] && + !_theResult____h455116[45] && + !_theResult____h455116[44] && + !_theResult____h455116[43] && + !_theResult____h455116[42] && + !_theResult____h455116[41] && + !_theResult____h455116[40] && + !_theResult____h455116[39] && + !_theResult____h455116[38] && + !_theResult____h455116[37] && + !_theResult____h455116[36] && + !_theResult____h455116[35] && + !_theResult____h455116[34] && + !_theResult____h455116[33] && + !_theResult____h455116[32] && + !_theResult____h455116[31] && + !_theResult____h455116[30] && + !_theResult____h455116[29] && + !_theResult____h455116[28] && + !_theResult____h455116[27] && + !_theResult____h455116[26] && + !_theResult____h455116[25] && + !_theResult____h455116[24] && + !_theResult____h455116[23] && + !_theResult____h455116[22] && + !_theResult____h455116[21] && + !_theResult____h455116[20] && + !_theResult____h455116[19] && + !_theResult____h455116[18] && + !_theResult____h455116[17] && + !_theResult____h455116[16] && + !_theResult____h455116[15] && + !_theResult____h455116[14] && + !_theResult____h455116[13] && + !_theResult____h455116[12] && + !_theResult____h455116[11] && + !_theResult____h455116[10] && + !_theResult____h455116[9] && + !_theResult____h455116[8] && + !_theResult____h455116[7] && + !_theResult____h455116[6] && + !_theResult____h455116[5] && + !_theResult____h455116[4] && + !_theResult____h455116[3] && + !_theResult____h455116[2] && + !_theResult____h455116[1] && + !_theResult____h455116[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584) ? 8'd0 : - _theResult___fst_exp__h463418 ; - assign _theResult___fst_exp__h463427 = - (!_theResult____h455115[56] && _theResult____h455115[55]) ? + _theResult___fst_exp__h463419 ; + assign _theResult___fst_exp__h463428 = + (!_theResult____h455116[56] && _theResult____h455116[55]) ? 8'd1 : - _theResult___fst_exp__h463424 ; - assign _theResult___fst_exp__h463950 = - (_theResult___fst_exp__h463353 == 8'd255) ? - _theResult___fst_exp__h463353 : - _theResult___fst_exp__h463947 ; - assign _theResult___fst_exp__h471990 = + _theResult___fst_exp__h463425 ; + assign _theResult___fst_exp__h463951 = + (_theResult___fst_exp__h463354 == 8'd255) ? + _theResult___fst_exp__h463354 : + _theResult___fst_exp__h463948 ; + assign _theResult___fst_exp__h471991 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ; - assign _theResult___fst_exp__h472029 = + assign _theResult___fst_exp__h472030 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h472035 = + assign _theResult___fst_exp__h472036 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657) ? 8'd0 : - _theResult___fst_exp__h472029 ; - assign _theResult___fst_exp__h472038 = + _theResult___fst_exp__h472030 ; + assign _theResult___fst_exp__h472039 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h472035 : - _theResult___fst_exp__h471990 ; - assign _theResult___fst_exp__h472586 = - (_theResult___fst_exp__h472038 == 8'd255) ? - _theResult___fst_exp__h472038 : - _theResult___fst_exp__h472583 ; - assign _theResult___fst_exp__h472595 = + _theResult___fst_exp__h472036 : + _theResult___fst_exp__h471991 ; + assign _theResult___fst_exp__h472587 = + (_theResult___fst_exp__h472039 == 8'd255) ? + _theResult___fst_exp__h472039 : + _theResult___fst_exp__h472584 ; + assign _theResult___fst_exp__h472596 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_exp__h454769 : - _theResult___fst_exp__h437460) : + _theResult___snd_fst_exp__h454770 : + _theResult___fst_exp__h437461) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_exp__h472589 : - _theResult___fst_exp__h437460) ; - assign _theResult___fst_exp__h472598 = + _theResult___snd_fst_exp__h472590 : + _theResult___fst_exp__h437461) ; + assign _theResult___fst_exp__h472599 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h472595 ; - assign _theResult___fst_exp__h486454 = + _theResult___fst_exp__h472596 ; + assign _theResult___fst_exp__h486455 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_exp__h501518 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; + assign _theResult___fst_exp__h501519 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h501524 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___fst_exp__h501525 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585) ? 11'd0 : - _theResult___fst_exp__h501518 ; - assign _theResult___fst_exp__h501527 = - (f1_exp__h482139 == 8'd0) ? - _theResult___fst_exp__h501524 : + _theResult___fst_exp__h501519 ; + assign _theResult___fst_exp__h501528 = + (f1_exp__h482140 == 8'd0) ? + _theResult___fst_exp__h501525 : 11'd897 ; - assign _theResult___fst_exp__h502282 = + assign _theResult___fst_exp__h502283 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 : + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 ; - assign _theResult___fst_exp__h502285 = - (_theResult___fst_exp__h501527 == 11'd2047) ? - _theResult___fst_exp__h501527 : - _theResult___fst_exp__h502282 ; - assign _theResult___fst_exp__h511104 = - _theResult____h502868[56] ? + assign _theResult___fst_exp__h502286 = + (_theResult___fst_exp__h501528 == 11'd2047) ? + _theResult___fst_exp__h501528 : + _theResult___fst_exp__h502283 ; + assign _theResult___fst_exp__h511105 = + _theResult____h502869[56] ? 11'd2 : - _theResult___fst_exp__h511178 ; - assign _theResult___fst_exp__h511169 = + _theResult___fst_exp__h511179 ; + assign _theResult___fst_exp__h511170 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ; - assign _theResult___fst_exp__h511175 = - (!_theResult____h502868[56] && !_theResult____h502868[55] && - !_theResult____h502868[54] && - !_theResult____h502868[53] && - !_theResult____h502868[52] && - !_theResult____h502868[51] && - !_theResult____h502868[50] && - !_theResult____h502868[49] && - !_theResult____h502868[48] && - !_theResult____h502868[47] && - !_theResult____h502868[46] && - !_theResult____h502868[45] && - !_theResult____h502868[44] && - !_theResult____h502868[43] && - !_theResult____h502868[42] && - !_theResult____h502868[41] && - !_theResult____h502868[40] && - !_theResult____h502868[39] && - !_theResult____h502868[38] && - !_theResult____h502868[37] && - !_theResult____h502868[36] && - !_theResult____h502868[35] && - !_theResult____h502868[34] && - !_theResult____h502868[33] && - !_theResult____h502868[32] && - !_theResult____h502868[31] && - !_theResult____h502868[30] && - !_theResult____h502868[29] && - !_theResult____h502868[28] && - !_theResult____h502868[27] && - !_theResult____h502868[26] && - !_theResult____h502868[25] && - !_theResult____h502868[24] && - !_theResult____h502868[23] && - !_theResult____h502868[22] && - !_theResult____h502868[21] && - !_theResult____h502868[20] && - !_theResult____h502868[19] && - !_theResult____h502868[18] && - !_theResult____h502868[17] && - !_theResult____h502868[16] && - !_theResult____h502868[15] && - !_theResult____h502868[14] && - !_theResult____h502868[13] && - !_theResult____h502868[12] && - !_theResult____h502868[11] && - !_theResult____h502868[10] && - !_theResult____h502868[9] && - !_theResult____h502868[8] && - !_theResult____h502868[7] && - !_theResult____h502868[6] && - !_theResult____h502868[5] && - !_theResult____h502868[4] && - !_theResult____h502868[3] && - !_theResult____h502868[2] && - !_theResult____h502868[1] && - !_theResult____h502868[0] || + assign _theResult___fst_exp__h511176 = + (!_theResult____h502869[56] && !_theResult____h502869[55] && + !_theResult____h502869[54] && + !_theResult____h502869[53] && + !_theResult____h502869[52] && + !_theResult____h502869[51] && + !_theResult____h502869[50] && + !_theResult____h502869[49] && + !_theResult____h502869[48] && + !_theResult____h502869[47] && + !_theResult____h502869[46] && + !_theResult____h502869[45] && + !_theResult____h502869[44] && + !_theResult____h502869[43] && + !_theResult____h502869[42] && + !_theResult____h502869[41] && + !_theResult____h502869[40] && + !_theResult____h502869[39] && + !_theResult____h502869[38] && + !_theResult____h502869[37] && + !_theResult____h502869[36] && + !_theResult____h502869[35] && + !_theResult____h502869[34] && + !_theResult____h502869[33] && + !_theResult____h502869[32] && + !_theResult____h502869[31] && + !_theResult____h502869[30] && + !_theResult____h502869[29] && + !_theResult____h502869[28] && + !_theResult____h502869[27] && + !_theResult____h502869[26] && + !_theResult____h502869[25] && + !_theResult____h502869[24] && + !_theResult____h502869[23] && + !_theResult____h502869[22] && + !_theResult____h502869[21] && + !_theResult____h502869[20] && + !_theResult____h502869[19] && + !_theResult____h502869[18] && + !_theResult____h502869[17] && + !_theResult____h502869[16] && + !_theResult____h502869[15] && + !_theResult____h502869[14] && + !_theResult____h502869[13] && + !_theResult____h502869[12] && + !_theResult____h502869[11] && + !_theResult____h502869[10] && + !_theResult____h502869[9] && + !_theResult____h502869[8] && + !_theResult____h502869[7] && + !_theResult____h502869[6] && + !_theResult____h502869[5] && + !_theResult____h502869[4] && + !_theResult____h502869[3] && + !_theResult____h502869[2] && + !_theResult____h502869[1] && + !_theResult____h502869[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897) ? 11'd0 : - _theResult___fst_exp__h511169 ; - assign _theResult___fst_exp__h511178 = - (!_theResult____h502868[56] && _theResult____h502868[55]) ? + _theResult___fst_exp__h511170 ; + assign _theResult___fst_exp__h511179 = + (!_theResult____h502869[56] && _theResult____h502869[55]) ? 11'd1 : - _theResult___fst_exp__h511175 ; - assign _theResult___fst_exp__h511933 = + _theResult___fst_exp__h511176 ; + assign _theResult___fst_exp__h511934 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 : + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 ; - assign _theResult___fst_exp__h511936 = - (_theResult___fst_exp__h511104 == 11'd2047) ? - _theResult___fst_exp__h511104 : - _theResult___fst_exp__h511933 ; - assign _theResult___fst_exp__h519889 = + assign _theResult___fst_exp__h511937 = + (_theResult___fst_exp__h511105 == 11'd2047) ? + _theResult___fst_exp__h511105 : + _theResult___fst_exp__h511934 ; + assign _theResult___fst_exp__h519890 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h519928 = + assign _theResult___fst_exp__h519929 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h519934 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___fst_exp__h519935 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947) ? 11'd0 : - _theResult___fst_exp__h519928 ; - assign _theResult___fst_exp__h519937 = - (f1_exp__h482139 == 8'd0) ? - _theResult___fst_exp__h519934 : - _theResult___fst_exp__h519889 ; - assign _theResult___fst_exp__h520717 = + _theResult___fst_exp__h519929 ; + assign _theResult___fst_exp__h519938 = + (f1_exp__h482140 == 8'd0) ? + _theResult___fst_exp__h519935 : + _theResult___fst_exp__h519890 ; + assign _theResult___fst_exp__h520718 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 : + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 ; - assign _theResult___fst_exp__h520720 = - (_theResult___fst_exp__h519937 == 11'd2047) ? - _theResult___fst_exp__h519937 : - _theResult___fst_exp__h520717 ; - assign _theResult___fst_exp__h520729 = - (f1_exp__h482139 == 8'd0) ? + assign _theResult___fst_exp__h520721 = + (_theResult___fst_exp__h519938 == 11'd2047) ? + _theResult___fst_exp__h519938 : + _theResult___fst_exp__h520718 ; + assign _theResult___fst_exp__h520730 = + (f1_exp__h482140 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_exp__h502288 : - _theResult___fst_exp__h486454) : + _theResult___snd_fst_exp__h502289 : + _theResult___fst_exp__h486455) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_exp__h520723 : - _theResult___fst_exp__h486454) ; - assign _theResult___fst_exp__h520732 = - (f1_exp__h482139 == 8'd0 && f1_sfd__h482140 == 23'd0) ? + _theResult___snd_fst_exp__h520724 : + _theResult___fst_exp__h486455) ; + assign _theResult___fst_exp__h520733 = + (f1_exp__h482140 == 8'd0 && f1_sfd__h482141 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h520729 ; - assign _theResult___fst_exp__h525307 = + _theResult___fst_exp__h520730 ; + assign _theResult___fst_exp__h525308 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 ; - assign _theResult___fst_exp__h540371 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + assign _theResult___fst_exp__h540372 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h540377 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___fst_exp__h540378 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085) ? 11'd0 : - _theResult___fst_exp__h540371 ; - assign _theResult___fst_exp__h540380 = - (f2_exp__h521133 == 8'd0) ? - _theResult___fst_exp__h540377 : + _theResult___fst_exp__h540372 ; + assign _theResult___fst_exp__h540381 = + (f2_exp__h521134 == 8'd0) ? + _theResult___fst_exp__h540378 : 11'd897 ; - assign _theResult___fst_exp__h541135 = + assign _theResult___fst_exp__h541136 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 : + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 ; - assign _theResult___fst_exp__h541138 = - (_theResult___fst_exp__h540380 == 11'd2047) ? - _theResult___fst_exp__h540380 : - _theResult___fst_exp__h541135 ; - assign _theResult___fst_exp__h549957 = - _theResult____h541721[56] ? + assign _theResult___fst_exp__h541139 = + (_theResult___fst_exp__h540381 == 11'd2047) ? + _theResult___fst_exp__h540381 : + _theResult___fst_exp__h541136 ; + assign _theResult___fst_exp__h549958 = + _theResult____h541722[56] ? 11'd2 : - _theResult___fst_exp__h550031 ; - assign _theResult___fst_exp__h550022 = + _theResult___fst_exp__h550032 ; + assign _theResult___fst_exp__h550023 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ; - assign _theResult___fst_exp__h550028 = - (!_theResult____h541721[56] && !_theResult____h541721[55] && - !_theResult____h541721[54] && - !_theResult____h541721[53] && - !_theResult____h541721[52] && - !_theResult____h541721[51] && - !_theResult____h541721[50] && - !_theResult____h541721[49] && - !_theResult____h541721[48] && - !_theResult____h541721[47] && - !_theResult____h541721[46] && - !_theResult____h541721[45] && - !_theResult____h541721[44] && - !_theResult____h541721[43] && - !_theResult____h541721[42] && - !_theResult____h541721[41] && - !_theResult____h541721[40] && - !_theResult____h541721[39] && - !_theResult____h541721[38] && - !_theResult____h541721[37] && - !_theResult____h541721[36] && - !_theResult____h541721[35] && - !_theResult____h541721[34] && - !_theResult____h541721[33] && - !_theResult____h541721[32] && - !_theResult____h541721[31] && - !_theResult____h541721[30] && - !_theResult____h541721[29] && - !_theResult____h541721[28] && - !_theResult____h541721[27] && - !_theResult____h541721[26] && - !_theResult____h541721[25] && - !_theResult____h541721[24] && - !_theResult____h541721[23] && - !_theResult____h541721[22] && - !_theResult____h541721[21] && - !_theResult____h541721[20] && - !_theResult____h541721[19] && - !_theResult____h541721[18] && - !_theResult____h541721[17] && - !_theResult____h541721[16] && - !_theResult____h541721[15] && - !_theResult____h541721[14] && - !_theResult____h541721[13] && - !_theResult____h541721[12] && - !_theResult____h541721[11] && - !_theResult____h541721[10] && - !_theResult____h541721[9] && - !_theResult____h541721[8] && - !_theResult____h541721[7] && - !_theResult____h541721[6] && - !_theResult____h541721[5] && - !_theResult____h541721[4] && - !_theResult____h541721[3] && - !_theResult____h541721[2] && - !_theResult____h541721[1] && - !_theResult____h541721[0] || + assign _theResult___fst_exp__h550029 = + (!_theResult____h541722[56] && !_theResult____h541722[55] && + !_theResult____h541722[54] && + !_theResult____h541722[53] && + !_theResult____h541722[52] && + !_theResult____h541722[51] && + !_theResult____h541722[50] && + !_theResult____h541722[49] && + !_theResult____h541722[48] && + !_theResult____h541722[47] && + !_theResult____h541722[46] && + !_theResult____h541722[45] && + !_theResult____h541722[44] && + !_theResult____h541722[43] && + !_theResult____h541722[42] && + !_theResult____h541722[41] && + !_theResult____h541722[40] && + !_theResult____h541722[39] && + !_theResult____h541722[38] && + !_theResult____h541722[37] && + !_theResult____h541722[36] && + !_theResult____h541722[35] && + !_theResult____h541722[34] && + !_theResult____h541722[33] && + !_theResult____h541722[32] && + !_theResult____h541722[31] && + !_theResult____h541722[30] && + !_theResult____h541722[29] && + !_theResult____h541722[28] && + !_theResult____h541722[27] && + !_theResult____h541722[26] && + !_theResult____h541722[25] && + !_theResult____h541722[24] && + !_theResult____h541722[23] && + !_theResult____h541722[22] && + !_theResult____h541722[21] && + !_theResult____h541722[20] && + !_theResult____h541722[19] && + !_theResult____h541722[18] && + !_theResult____h541722[17] && + !_theResult____h541722[16] && + !_theResult____h541722[15] && + !_theResult____h541722[14] && + !_theResult____h541722[13] && + !_theResult____h541722[12] && + !_theResult____h541722[11] && + !_theResult____h541722[10] && + !_theResult____h541722[9] && + !_theResult____h541722[8] && + !_theResult____h541722[7] && + !_theResult____h541722[6] && + !_theResult____h541722[5] && + !_theResult____h541722[4] && + !_theResult____h541722[3] && + !_theResult____h541722[2] && + !_theResult____h541722[1] && + !_theResult____h541722[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382) ? 11'd0 : - _theResult___fst_exp__h550022 ; - assign _theResult___fst_exp__h550031 = - (!_theResult____h541721[56] && _theResult____h541721[55]) ? + _theResult___fst_exp__h550023 ; + assign _theResult___fst_exp__h550032 = + (!_theResult____h541722[56] && _theResult____h541722[55]) ? 11'd1 : - _theResult___fst_exp__h550028 ; - assign _theResult___fst_exp__h550786 = + _theResult___fst_exp__h550029 ; + assign _theResult___fst_exp__h550787 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 : + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 ; - assign _theResult___fst_exp__h550789 = - (_theResult___fst_exp__h549957 == 11'd2047) ? - _theResult___fst_exp__h549957 : - _theResult___fst_exp__h550786 ; - assign _theResult___fst_exp__h558742 = + assign _theResult___fst_exp__h550790 = + (_theResult___fst_exp__h549958 == 11'd2047) ? + _theResult___fst_exp__h549958 : + _theResult___fst_exp__h550787 ; + assign _theResult___fst_exp__h558743 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h558781 = + assign _theResult___fst_exp__h558782 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h558787 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___fst_exp__h558788 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432) ? 11'd0 : - _theResult___fst_exp__h558781 ; - assign _theResult___fst_exp__h558790 = - (f2_exp__h521133 == 8'd0) ? - _theResult___fst_exp__h558787 : - _theResult___fst_exp__h558742 ; - assign _theResult___fst_exp__h559570 = + _theResult___fst_exp__h558782 ; + assign _theResult___fst_exp__h558791 = + (f2_exp__h521134 == 8'd0) ? + _theResult___fst_exp__h558788 : + _theResult___fst_exp__h558743 ; + assign _theResult___fst_exp__h559571 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 : + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ; - assign _theResult___fst_exp__h559573 = - (_theResult___fst_exp__h558790 == 11'd2047) ? - _theResult___fst_exp__h558790 : - _theResult___fst_exp__h559570 ; - assign _theResult___fst_exp__h559582 = - (f2_exp__h521133 == 8'd0) ? + assign _theResult___fst_exp__h559574 = + (_theResult___fst_exp__h558791 == 11'd2047) ? + _theResult___fst_exp__h558791 : + _theResult___fst_exp__h559571 ; + assign _theResult___fst_exp__h559583 = + (f2_exp__h521134 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_exp__h541141 : - _theResult___fst_exp__h525307) : + _theResult___snd_fst_exp__h541142 : + _theResult___fst_exp__h525308) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_exp__h559576 : - _theResult___fst_exp__h525307) ; - assign _theResult___fst_exp__h559585 = - (f2_exp__h521133 == 8'd0 && f2_sfd__h521134 == 23'd0) ? + _theResult___snd_fst_exp__h559577 : + _theResult___fst_exp__h525308) ; + assign _theResult___fst_exp__h559586 = + (f2_exp__h521134 == 8'd0 && f2_sfd__h521135 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h559582 ; - assign _theResult___fst_exp__h564611 = + _theResult___fst_exp__h559583 ; + assign _theResult___fst_exp__h564612 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_exp__h579675 = + assign _theResult___fst_exp__h579676 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h579681 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___fst_exp__h579682 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315) ? 11'd0 : - _theResult___fst_exp__h579675 ; - assign _theResult___fst_exp__h579684 = - (f3_exp__h560437 == 8'd0) ? - _theResult___fst_exp__h579681 : + _theResult___fst_exp__h579676 ; + assign _theResult___fst_exp__h579685 = + (f3_exp__h560438 == 8'd0) ? + _theResult___fst_exp__h579682 : 11'd897 ; - assign _theResult___fst_exp__h580439 = + assign _theResult___fst_exp__h580440 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 : + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 ; - assign _theResult___fst_exp__h580442 = - (_theResult___fst_exp__h579684 == 11'd2047) ? - _theResult___fst_exp__h579684 : - _theResult___fst_exp__h580439 ; - assign _theResult___fst_exp__h589261 = - _theResult____h581025[56] ? + assign _theResult___fst_exp__h580443 = + (_theResult___fst_exp__h579685 == 11'd2047) ? + _theResult___fst_exp__h579685 : + _theResult___fst_exp__h580440 ; + assign _theResult___fst_exp__h589262 = + _theResult____h581026[56] ? 11'd2 : - _theResult___fst_exp__h589335 ; - assign _theResult___fst_exp__h589326 = + _theResult___fst_exp__h589336 ; + assign _theResult___fst_exp__h589327 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ; - assign _theResult___fst_exp__h589332 = - (!_theResult____h581025[56] && !_theResult____h581025[55] && - !_theResult____h581025[54] && - !_theResult____h581025[53] && - !_theResult____h581025[52] && - !_theResult____h581025[51] && - !_theResult____h581025[50] && - !_theResult____h581025[49] && - !_theResult____h581025[48] && - !_theResult____h581025[47] && - !_theResult____h581025[46] && - !_theResult____h581025[45] && - !_theResult____h581025[44] && - !_theResult____h581025[43] && - !_theResult____h581025[42] && - !_theResult____h581025[41] && - !_theResult____h581025[40] && - !_theResult____h581025[39] && - !_theResult____h581025[38] && - !_theResult____h581025[37] && - !_theResult____h581025[36] && - !_theResult____h581025[35] && - !_theResult____h581025[34] && - !_theResult____h581025[33] && - !_theResult____h581025[32] && - !_theResult____h581025[31] && - !_theResult____h581025[30] && - !_theResult____h581025[29] && - !_theResult____h581025[28] && - !_theResult____h581025[27] && - !_theResult____h581025[26] && - !_theResult____h581025[25] && - !_theResult____h581025[24] && - !_theResult____h581025[23] && - !_theResult____h581025[22] && - !_theResult____h581025[21] && - !_theResult____h581025[20] && - !_theResult____h581025[19] && - !_theResult____h581025[18] && - !_theResult____h581025[17] && - !_theResult____h581025[16] && - !_theResult____h581025[15] && - !_theResult____h581025[14] && - !_theResult____h581025[13] && - !_theResult____h581025[12] && - !_theResult____h581025[11] && - !_theResult____h581025[10] && - !_theResult____h581025[9] && - !_theResult____h581025[8] && - !_theResult____h581025[7] && - !_theResult____h581025[6] && - !_theResult____h581025[5] && - !_theResult____h581025[4] && - !_theResult____h581025[3] && - !_theResult____h581025[2] && - !_theResult____h581025[1] && - !_theResult____h581025[0] || + assign _theResult___fst_exp__h589333 = + (!_theResult____h581026[56] && !_theResult____h581026[55] && + !_theResult____h581026[54] && + !_theResult____h581026[53] && + !_theResult____h581026[52] && + !_theResult____h581026[51] && + !_theResult____h581026[50] && + !_theResult____h581026[49] && + !_theResult____h581026[48] && + !_theResult____h581026[47] && + !_theResult____h581026[46] && + !_theResult____h581026[45] && + !_theResult____h581026[44] && + !_theResult____h581026[43] && + !_theResult____h581026[42] && + !_theResult____h581026[41] && + !_theResult____h581026[40] && + !_theResult____h581026[39] && + !_theResult____h581026[38] && + !_theResult____h581026[37] && + !_theResult____h581026[36] && + !_theResult____h581026[35] && + !_theResult____h581026[34] && + !_theResult____h581026[33] && + !_theResult____h581026[32] && + !_theResult____h581026[31] && + !_theResult____h581026[30] && + !_theResult____h581026[29] && + !_theResult____h581026[28] && + !_theResult____h581026[27] && + !_theResult____h581026[26] && + !_theResult____h581026[25] && + !_theResult____h581026[24] && + !_theResult____h581026[23] && + !_theResult____h581026[22] && + !_theResult____h581026[21] && + !_theResult____h581026[20] && + !_theResult____h581026[19] && + !_theResult____h581026[18] && + !_theResult____h581026[17] && + !_theResult____h581026[16] && + !_theResult____h581026[15] && + !_theResult____h581026[14] && + !_theResult____h581026[13] && + !_theResult____h581026[12] && + !_theResult____h581026[11] && + !_theResult____h581026[10] && + !_theResult____h581026[9] && + !_theResult____h581026[8] && + !_theResult____h581026[7] && + !_theResult____h581026[6] && + !_theResult____h581026[5] && + !_theResult____h581026[4] && + !_theResult____h581026[3] && + !_theResult____h581026[2] && + !_theResult____h581026[1] && + !_theResult____h581026[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612) ? 11'd0 : - _theResult___fst_exp__h589326 ; - assign _theResult___fst_exp__h589335 = - (!_theResult____h581025[56] && _theResult____h581025[55]) ? + _theResult___fst_exp__h589327 ; + assign _theResult___fst_exp__h589336 = + (!_theResult____h581026[56] && _theResult____h581026[55]) ? 11'd1 : - _theResult___fst_exp__h589332 ; - assign _theResult___fst_exp__h590090 = + _theResult___fst_exp__h589333 ; + assign _theResult___fst_exp__h590091 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 : + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ; - assign _theResult___fst_exp__h590093 = - (_theResult___fst_exp__h589261 == 11'd2047) ? - _theResult___fst_exp__h589261 : - _theResult___fst_exp__h590090 ; - assign _theResult___fst_exp__h598046 = + assign _theResult___fst_exp__h590094 = + (_theResult___fst_exp__h589262 == 11'd2047) ? + _theResult___fst_exp__h589262 : + _theResult___fst_exp__h590091 ; + assign _theResult___fst_exp__h598047 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h598085 = + assign _theResult___fst_exp__h598086 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h598091 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___fst_exp__h598092 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662) ? 11'd0 : - _theResult___fst_exp__h598085 ; - assign _theResult___fst_exp__h598094 = - (f3_exp__h560437 == 8'd0) ? - _theResult___fst_exp__h598091 : - _theResult___fst_exp__h598046 ; - assign _theResult___fst_exp__h598874 = + _theResult___fst_exp__h598086 ; + assign _theResult___fst_exp__h598095 = + (f3_exp__h560438 == 8'd0) ? + _theResult___fst_exp__h598092 : + _theResult___fst_exp__h598047 ; + assign _theResult___fst_exp__h598875 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 : + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; - assign _theResult___fst_exp__h598877 = - (_theResult___fst_exp__h598094 == 11'd2047) ? - _theResult___fst_exp__h598094 : - _theResult___fst_exp__h598874 ; - assign _theResult___fst_exp__h598886 = - (f3_exp__h560437 == 8'd0) ? + assign _theResult___fst_exp__h598878 = + (_theResult___fst_exp__h598095 == 11'd2047) ? + _theResult___fst_exp__h598095 : + _theResult___fst_exp__h598875 ; + assign _theResult___fst_exp__h598887 = + (f3_exp__h560438 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_exp__h580445 : - _theResult___fst_exp__h564611) : + _theResult___snd_fst_exp__h580446 : + _theResult___fst_exp__h564612) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_exp__h598880 : - _theResult___fst_exp__h564611) ; - assign _theResult___fst_exp__h598889 = - (f3_exp__h560437 == 8'd0 && f3_sfd__h560438 == 23'd0) ? + _theResult___snd_fst_exp__h598881 : + _theResult___fst_exp__h564612) ; + assign _theResult___fst_exp__h598890 = + (f3_exp__h560438 == 8'd0 && f3_sfd__h560439 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h598886 ; - assign _theResult___fst_sfd__h354793 = - (_theResult___fst_exp__h354195 == 8'd255) ? - sfdin__h354189[56:34] : - _theResult___fst_sfd__h354790 ; - assign _theResult___fst_sfd__h363375 = - (_theResult___fst_exp__h362851 == 8'd255) ? - _theResult___snd__h362802[56:34] : - _theResult___fst_sfd__h363372 ; - assign _theResult___fst_sfd__h372559 = - (_theResult___fst_exp__h371961 == 8'd255) ? - sfdin__h371955[56:34] : - _theResult___fst_sfd__h372556 ; - assign _theResult___fst_sfd__h381195 = - (_theResult___fst_exp__h380646 == 8'd255) ? - _theResult___snd__h380592[56:34] : - _theResult___fst_sfd__h381192 ; - assign _theResult___fst_sfd__h381204 = + _theResult___fst_exp__h598887 ; + assign _theResult___fst_sfd__h354794 = + (_theResult___fst_exp__h354196 == 8'd255) ? + sfdin__h354190[56:34] : + _theResult___fst_sfd__h354791 ; + assign _theResult___fst_sfd__h363376 = + (_theResult___fst_exp__h362852 == 8'd255) ? + _theResult___snd__h362803[56:34] : + _theResult___fst_sfd__h363373 ; + assign _theResult___fst_sfd__h372560 = + (_theResult___fst_exp__h371962 == 8'd255) ? + sfdin__h371956[56:34] : + _theResult___fst_sfd__h372557 ; + assign _theResult___fst_sfd__h381196 = + (_theResult___fst_exp__h380647 == 8'd255) ? + _theResult___snd__h380593[56:34] : + _theResult___fst_sfd__h381193 ; + assign _theResult___fst_sfd__h381205 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_sfd__h363378 : - _theResult___fst_sfd__h346067) : + _theResult___snd_fst_sfd__h363379 : + _theResult___fst_sfd__h346068) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_sfd__h381198 : - _theResult___fst_sfd__h346067) ; - assign _theResult___fst_sfd__h381210 = + _theResult___snd_fst_sfd__h381199 : + _theResult___fst_sfd__h346068) ; + assign _theResult___fst_sfd__h381211 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -28177,33 +28203,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h381204 ; - assign _theResult___fst_sfd__h400490 = - (_theResult___fst_exp__h399892 == 8'd255) ? - sfdin__h399886[56:34] : - _theResult___fst_sfd__h400487 ; - assign _theResult___fst_sfd__h409072 = - (_theResult___fst_exp__h408548 == 8'd255) ? - _theResult___snd__h408499[56:34] : - _theResult___fst_sfd__h409069 ; - assign _theResult___fst_sfd__h418256 = - (_theResult___fst_exp__h417658 == 8'd255) ? - sfdin__h417652[56:34] : - _theResult___fst_sfd__h418253 ; - assign _theResult___fst_sfd__h426892 = - (_theResult___fst_exp__h426343 == 8'd255) ? - _theResult___snd__h426289[56:34] : - _theResult___fst_sfd__h426889 ; - assign _theResult___fst_sfd__h426901 = + _theResult___fst_sfd__h381205 ; + assign _theResult___fst_sfd__h400491 = + (_theResult___fst_exp__h399893 == 8'd255) ? + sfdin__h399887[56:34] : + _theResult___fst_sfd__h400488 ; + assign _theResult___fst_sfd__h409073 = + (_theResult___fst_exp__h408549 == 8'd255) ? + _theResult___snd__h408500[56:34] : + _theResult___fst_sfd__h409070 ; + assign _theResult___fst_sfd__h418257 = + (_theResult___fst_exp__h417659 == 8'd255) ? + sfdin__h417653[56:34] : + _theResult___fst_sfd__h418254 ; + assign _theResult___fst_sfd__h426893 = + (_theResult___fst_exp__h426344 == 8'd255) ? + _theResult___snd__h426290[56:34] : + _theResult___fst_sfd__h426890 ; + assign _theResult___fst_sfd__h426902 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_sfd__h409075 : - _theResult___fst_sfd__h391766) : + _theResult___snd_fst_sfd__h409076 : + _theResult___fst_sfd__h391767) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_sfd__h426895 : - _theResult___fst_sfd__h391766) ; - assign _theResult___fst_sfd__h426907 = + _theResult___snd_fst_sfd__h426896 : + _theResult___fst_sfd__h391767) ; + assign _theResult___fst_sfd__h426908 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -28211,33 +28237,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h426901 ; - assign _theResult___fst_sfd__h446185 = - (_theResult___fst_exp__h445587 == 8'd255) ? - sfdin__h445581[56:34] : - _theResult___fst_sfd__h446182 ; - assign _theResult___fst_sfd__h454767 = - (_theResult___fst_exp__h454243 == 8'd255) ? - _theResult___snd__h454194[56:34] : - _theResult___fst_sfd__h454764 ; - assign _theResult___fst_sfd__h463951 = - (_theResult___fst_exp__h463353 == 8'd255) ? - sfdin__h463347[56:34] : - _theResult___fst_sfd__h463948 ; - assign _theResult___fst_sfd__h472587 = - (_theResult___fst_exp__h472038 == 8'd255) ? - _theResult___snd__h471984[56:34] : - _theResult___fst_sfd__h472584 ; - assign _theResult___fst_sfd__h472596 = + _theResult___fst_sfd__h426902 ; + assign _theResult___fst_sfd__h446186 = + (_theResult___fst_exp__h445588 == 8'd255) ? + sfdin__h445582[56:34] : + _theResult___fst_sfd__h446183 ; + assign _theResult___fst_sfd__h454768 = + (_theResult___fst_exp__h454244 == 8'd255) ? + _theResult___snd__h454195[56:34] : + _theResult___fst_sfd__h454765 ; + assign _theResult___fst_sfd__h463952 = + (_theResult___fst_exp__h463354 == 8'd255) ? + sfdin__h463348[56:34] : + _theResult___fst_sfd__h463949 ; + assign _theResult___fst_sfd__h472588 = + (_theResult___fst_exp__h472039 == 8'd255) ? + _theResult___snd__h471985[56:34] : + _theResult___fst_sfd__h472585 ; + assign _theResult___fst_sfd__h472597 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_sfd__h454770 : - _theResult___fst_sfd__h437461) : + _theResult___snd_fst_sfd__h454771 : + _theResult___fst_sfd__h437462) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_sfd__h472590 : - _theResult___fst_sfd__h437461) ; - assign _theResult___fst_sfd__h472602 = + _theResult___snd_fst_sfd__h472591 : + _theResult___fst_sfd__h437462) ; + assign _theResult___fst_sfd__h472603 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -28245,1309 +28271,1309 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h472596 ; - assign _theResult___fst_sfd__h486455 = + _theResult___fst_sfd__h472597 ; + assign _theResult___fst_sfd__h486456 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_sfd__h502283 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; + assign _theResult___fst_sfd__h502284 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 : + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; - assign _theResult___fst_sfd__h502286 = - (_theResult___fst_exp__h501527 == 11'd2047) ? - _theResult___snd__h501478[56:5] : - _theResult___fst_sfd__h502283 ; - assign _theResult___fst_sfd__h511934 = + assign _theResult___fst_sfd__h502287 = + (_theResult___fst_exp__h501528 == 11'd2047) ? + _theResult___snd__h501479[56:5] : + _theResult___fst_sfd__h502284 ; + assign _theResult___fst_sfd__h511935 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; - assign _theResult___fst_sfd__h511937 = - (_theResult___fst_exp__h511104 == 11'd2047) ? - sfdin__h511098[56:5] : - _theResult___fst_sfd__h511934 ; - assign _theResult___fst_sfd__h520718 = + assign _theResult___fst_sfd__h511938 = + (_theResult___fst_exp__h511105 == 11'd2047) ? + sfdin__h511099[56:5] : + _theResult___fst_sfd__h511935 ; + assign _theResult___fst_sfd__h520719 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 : + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; - assign _theResult___fst_sfd__h520721 = - (_theResult___fst_exp__h519937 == 11'd2047) ? - _theResult___snd__h519883[56:5] : - _theResult___fst_sfd__h520718 ; - assign _theResult___fst_sfd__h520730 = - (f1_exp__h482139 == 8'd0) ? + assign _theResult___fst_sfd__h520722 = + (_theResult___fst_exp__h519938 == 11'd2047) ? + _theResult___snd__h519884[56:5] : + _theResult___fst_sfd__h520719 ; + assign _theResult___fst_sfd__h520731 = + (f1_exp__h482140 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_sfd__h502289 : - _theResult___fst_sfd__h486455) : + _theResult___snd_fst_sfd__h502290 : + _theResult___fst_sfd__h486456) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_sfd__h520724 : - _theResult___fst_sfd__h486455) ; - assign _theResult___fst_sfd__h520736 = - ((f1_exp__h482139 == 8'd255 || f1_exp__h482139 == 8'd0) && - f1_sfd__h482140 == 23'd0) ? + _theResult___snd_fst_sfd__h520725 : + _theResult___fst_sfd__h486456) ; + assign _theResult___fst_sfd__h520737 = + ((f1_exp__h482140 == 8'd255 || f1_exp__h482140 == 8'd0) && + f1_sfd__h482141 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h520730 ; - assign _theResult___fst_sfd__h525308 = + _theResult___fst_sfd__h520731 ; + assign _theResult___fst_sfd__h525309 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_sfd__h541136 = + assign _theResult___fst_sfd__h541137 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 : + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 ; - assign _theResult___fst_sfd__h541139 = - (_theResult___fst_exp__h540380 == 11'd2047) ? - _theResult___snd__h540331[56:5] : - _theResult___fst_sfd__h541136 ; - assign _theResult___fst_sfd__h550787 = + assign _theResult___fst_sfd__h541140 = + (_theResult___fst_exp__h540381 == 11'd2047) ? + _theResult___snd__h540332[56:5] : + _theResult___fst_sfd__h541137 ; + assign _theResult___fst_sfd__h550788 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; - assign _theResult___fst_sfd__h550790 = - (_theResult___fst_exp__h549957 == 11'd2047) ? - sfdin__h549951[56:5] : - _theResult___fst_sfd__h550787 ; - assign _theResult___fst_sfd__h559571 = + assign _theResult___fst_sfd__h550791 = + (_theResult___fst_exp__h549958 == 11'd2047) ? + sfdin__h549952[56:5] : + _theResult___fst_sfd__h550788 ; + assign _theResult___fst_sfd__h559572 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 : + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; - assign _theResult___fst_sfd__h559574 = - (_theResult___fst_exp__h558790 == 11'd2047) ? - _theResult___snd__h558736[56:5] : - _theResult___fst_sfd__h559571 ; - assign _theResult___fst_sfd__h559583 = - (f2_exp__h521133 == 8'd0) ? + assign _theResult___fst_sfd__h559575 = + (_theResult___fst_exp__h558791 == 11'd2047) ? + _theResult___snd__h558737[56:5] : + _theResult___fst_sfd__h559572 ; + assign _theResult___fst_sfd__h559584 = + (f2_exp__h521134 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_sfd__h541142 : - _theResult___fst_sfd__h525308) : + _theResult___snd_fst_sfd__h541143 : + _theResult___fst_sfd__h525309) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_sfd__h559577 : - _theResult___fst_sfd__h525308) ; - assign _theResult___fst_sfd__h559589 = - ((f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) && - f2_sfd__h521134 == 23'd0) ? + _theResult___snd_fst_sfd__h559578 : + _theResult___fst_sfd__h525309) ; + assign _theResult___fst_sfd__h559590 = + ((f2_exp__h521134 == 8'd255 || f2_exp__h521134 == 8'd0) && + f2_sfd__h521135 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h559583 ; - assign _theResult___fst_sfd__h564612 = + _theResult___fst_sfd__h559584 ; + assign _theResult___fst_sfd__h564613 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_sfd__h580440 = + assign _theResult___fst_sfd__h580441 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 : + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 ; - assign _theResult___fst_sfd__h580443 = - (_theResult___fst_exp__h579684 == 11'd2047) ? - _theResult___snd__h579635[56:5] : - _theResult___fst_sfd__h580440 ; - assign _theResult___fst_sfd__h590091 = + assign _theResult___fst_sfd__h580444 = + (_theResult___fst_exp__h579685 == 11'd2047) ? + _theResult___snd__h579636[56:5] : + _theResult___fst_sfd__h580441 ; + assign _theResult___fst_sfd__h590092 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 ; - assign _theResult___fst_sfd__h590094 = - (_theResult___fst_exp__h589261 == 11'd2047) ? - sfdin__h589255[56:5] : - _theResult___fst_sfd__h590091 ; - assign _theResult___fst_sfd__h598875 = + assign _theResult___fst_sfd__h590095 = + (_theResult___fst_exp__h589262 == 11'd2047) ? + sfdin__h589256[56:5] : + _theResult___fst_sfd__h590092 ; + assign _theResult___fst_sfd__h598876 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 : + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 ; - assign _theResult___fst_sfd__h598878 = - (_theResult___fst_exp__h598094 == 11'd2047) ? - _theResult___snd__h598040[56:5] : - _theResult___fst_sfd__h598875 ; - assign _theResult___fst_sfd__h598887 = - (f3_exp__h560437 == 8'd0) ? + assign _theResult___fst_sfd__h598879 = + (_theResult___fst_exp__h598095 == 11'd2047) ? + _theResult___snd__h598041[56:5] : + _theResult___fst_sfd__h598876 ; + assign _theResult___fst_sfd__h598888 = + (f3_exp__h560438 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_sfd__h580446 : - _theResult___fst_sfd__h564612) : + _theResult___snd_fst_sfd__h580447 : + _theResult___fst_sfd__h564613) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_sfd__h598881 : - _theResult___fst_sfd__h564612) ; - assign _theResult___fst_sfd__h598893 = - ((f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) && - f3_sfd__h560438 == 23'd0) ? + _theResult___snd_fst_sfd__h598882 : + _theResult___fst_sfd__h564613) ; + assign _theResult___fst_sfd__h598894 = + ((f3_exp__h560438 == 8'd255 || f3_exp__h560438 == 8'd0) && + f3_sfd__h560439 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h598887 ; - assign _theResult___sfd__h354712 = - sfd__h354287[24] ? - ((_theResult___fst_exp__h354195 == 8'd254) ? + _theResult___fst_sfd__h598888 ; + assign _theResult___sfd__h354713 = + sfd__h354288[24] ? + ((_theResult___fst_exp__h354196 == 8'd254) ? 23'd0 : - sfd__h354287[23:1]) : - sfd__h354287[22:0] ; - assign _theResult___sfd__h363294 = - sfd__h362869[24] ? - ((_theResult___fst_exp__h362851 == 8'd254) ? + sfd__h354288[23:1]) : + sfd__h354288[22:0] ; + assign _theResult___sfd__h363295 = + sfd__h362870[24] ? + ((_theResult___fst_exp__h362852 == 8'd254) ? 23'd0 : - sfd__h362869[23:1]) : - sfd__h362869[22:0] ; - assign _theResult___sfd__h372478 = - sfd__h372053[24] ? - ((_theResult___fst_exp__h371961 == 8'd254) ? + sfd__h362870[23:1]) : + sfd__h362870[22:0] ; + assign _theResult___sfd__h372479 = + sfd__h372054[24] ? + ((_theResult___fst_exp__h371962 == 8'd254) ? 23'd0 : - sfd__h372053[23:1]) : - sfd__h372053[22:0] ; - assign _theResult___sfd__h381114 = - sfd__h380665[24] ? - ((_theResult___fst_exp__h380646 == 8'd254) ? + sfd__h372054[23:1]) : + sfd__h372054[22:0] ; + assign _theResult___sfd__h381115 = + sfd__h380666[24] ? + ((_theResult___fst_exp__h380647 == 8'd254) ? 23'd0 : - sfd__h380665[23:1]) : - sfd__h380665[22:0] ; - assign _theResult___sfd__h381216 = + sfd__h380666[23:1]) : + sfd__h380666[22:0] ; + assign _theResult___sfd__h381217 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h338429 : - _theResult___fst_sfd__h381210 ; - assign _theResult___sfd__h400409 = - sfd__h399984[24] ? - ((_theResult___fst_exp__h399892 == 8'd254) ? + _theResult___snd_fst_sfd__h338430 : + _theResult___fst_sfd__h381211 ; + assign _theResult___sfd__h400410 = + sfd__h399985[24] ? + ((_theResult___fst_exp__h399893 == 8'd254) ? 23'd0 : - sfd__h399984[23:1]) : - sfd__h399984[22:0] ; - assign _theResult___sfd__h408991 = - sfd__h408566[24] ? - ((_theResult___fst_exp__h408548 == 8'd254) ? + sfd__h399985[23:1]) : + sfd__h399985[22:0] ; + assign _theResult___sfd__h408992 = + sfd__h408567[24] ? + ((_theResult___fst_exp__h408549 == 8'd254) ? 23'd0 : - sfd__h408566[23:1]) : - sfd__h408566[22:0] ; - assign _theResult___sfd__h418175 = - sfd__h417750[24] ? - ((_theResult___fst_exp__h417658 == 8'd254) ? + sfd__h408567[23:1]) : + sfd__h408567[22:0] ; + assign _theResult___sfd__h418176 = + sfd__h417751[24] ? + ((_theResult___fst_exp__h417659 == 8'd254) ? 23'd0 : - sfd__h417750[23:1]) : - sfd__h417750[22:0] ; - assign _theResult___sfd__h426811 = - sfd__h426362[24] ? - ((_theResult___fst_exp__h426343 == 8'd254) ? + sfd__h417751[23:1]) : + sfd__h417751[22:0] ; + assign _theResult___sfd__h426812 = + sfd__h426363[24] ? + ((_theResult___fst_exp__h426344 == 8'd254) ? 23'd0 : - sfd__h426362[23:1]) : - sfd__h426362[22:0] ; - assign _theResult___sfd__h426913 = + sfd__h426363[23:1]) : + sfd__h426363[22:0] ; + assign _theResult___sfd__h426914 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h384131 : - _theResult___fst_sfd__h426907 ; - assign _theResult___sfd__h446104 = - sfd__h445679[24] ? - ((_theResult___fst_exp__h445587 == 8'd254) ? + _theResult___snd_fst_sfd__h384132 : + _theResult___fst_sfd__h426908 ; + assign _theResult___sfd__h446105 = + sfd__h445680[24] ? + ((_theResult___fst_exp__h445588 == 8'd254) ? 23'd0 : - sfd__h445679[23:1]) : - sfd__h445679[22:0] ; - assign _theResult___sfd__h454686 = - sfd__h454261[24] ? - ((_theResult___fst_exp__h454243 == 8'd254) ? + sfd__h445680[23:1]) : + sfd__h445680[22:0] ; + assign _theResult___sfd__h454687 = + sfd__h454262[24] ? + ((_theResult___fst_exp__h454244 == 8'd254) ? 23'd0 : - sfd__h454261[23:1]) : - sfd__h454261[22:0] ; - assign _theResult___sfd__h463870 = - sfd__h463445[24] ? - ((_theResult___fst_exp__h463353 == 8'd254) ? + sfd__h454262[23:1]) : + sfd__h454262[22:0] ; + assign _theResult___sfd__h463871 = + sfd__h463446[24] ? + ((_theResult___fst_exp__h463354 == 8'd254) ? 23'd0 : - sfd__h463445[23:1]) : - sfd__h463445[22:0] ; - assign _theResult___sfd__h472506 = - sfd__h472057[24] ? - ((_theResult___fst_exp__h472038 == 8'd254) ? + sfd__h463446[23:1]) : + sfd__h463446[22:0] ; + assign _theResult___sfd__h472507 = + sfd__h472058[24] ? + ((_theResult___fst_exp__h472039 == 8'd254) ? 23'd0 : - sfd__h472057[23:1]) : - sfd__h472057[22:0] ; - assign _theResult___sfd__h472608 = + sfd__h472058[23:1]) : + sfd__h472058[22:0] ; + assign _theResult___sfd__h472609 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h429826 : - _theResult___fst_sfd__h472602 ; - assign _theResult___sfd__h502183 = - sfd__h501545[53] ? - ((_theResult___fst_exp__h501527 == 11'd2046) ? + _theResult___snd_fst_sfd__h429827 : + _theResult___fst_sfd__h472603 ; + assign _theResult___sfd__h502184 = + sfd__h501546[53] ? + ((_theResult___fst_exp__h501528 == 11'd2046) ? 52'd0 : - sfd__h501545[52:1]) : - sfd__h501545[51:0] ; - assign _theResult___sfd__h511834 = - sfd__h511196[53] ? - ((_theResult___fst_exp__h511104 == 11'd2046) ? + sfd__h501546[52:1]) : + sfd__h501546[51:0] ; + assign _theResult___sfd__h511835 = + sfd__h511197[53] ? + ((_theResult___fst_exp__h511105 == 11'd2046) ? 52'd0 : - sfd__h511196[52:1]) : - sfd__h511196[51:0] ; - assign _theResult___sfd__h520618 = - sfd__h519956[53] ? - ((_theResult___fst_exp__h519937 == 11'd2046) ? + sfd__h511197[52:1]) : + sfd__h511197[51:0] ; + assign _theResult___sfd__h520619 = + sfd__h519957[53] ? + ((_theResult___fst_exp__h519938 == 11'd2046) ? 52'd0 : - sfd__h519956[52:1]) : - sfd__h519956[51:0] ; - assign _theResult___sfd__h541036 = - sfd__h540398[53] ? - ((_theResult___fst_exp__h540380 == 11'd2046) ? + sfd__h519957[52:1]) : + sfd__h519957[51:0] ; + assign _theResult___sfd__h541037 = + sfd__h540399[53] ? + ((_theResult___fst_exp__h540381 == 11'd2046) ? 52'd0 : - sfd__h540398[52:1]) : - sfd__h540398[51:0] ; - assign _theResult___sfd__h550687 = - sfd__h550049[53] ? - ((_theResult___fst_exp__h549957 == 11'd2046) ? + sfd__h540399[52:1]) : + sfd__h540399[51:0] ; + assign _theResult___sfd__h550688 = + sfd__h550050[53] ? + ((_theResult___fst_exp__h549958 == 11'd2046) ? 52'd0 : - sfd__h550049[52:1]) : - sfd__h550049[51:0] ; - assign _theResult___sfd__h559471 = - sfd__h558809[53] ? - ((_theResult___fst_exp__h558790 == 11'd2046) ? + sfd__h550050[52:1]) : + sfd__h550050[51:0] ; + assign _theResult___sfd__h559472 = + sfd__h558810[53] ? + ((_theResult___fst_exp__h558791 == 11'd2046) ? 52'd0 : - sfd__h558809[52:1]) : - sfd__h558809[51:0] ; - assign _theResult___sfd__h580340 = - sfd__h579702[53] ? - ((_theResult___fst_exp__h579684 == 11'd2046) ? + sfd__h558810[52:1]) : + sfd__h558810[51:0] ; + assign _theResult___sfd__h580341 = + sfd__h579703[53] ? + ((_theResult___fst_exp__h579685 == 11'd2046) ? 52'd0 : - sfd__h579702[52:1]) : - sfd__h579702[51:0] ; - assign _theResult___sfd__h589991 = - sfd__h589353[53] ? - ((_theResult___fst_exp__h589261 == 11'd2046) ? + sfd__h579703[52:1]) : + sfd__h579703[51:0] ; + assign _theResult___sfd__h589992 = + sfd__h589354[53] ? + ((_theResult___fst_exp__h589262 == 11'd2046) ? 52'd0 : - sfd__h589353[52:1]) : - sfd__h589353[51:0] ; - assign _theResult___sfd__h598775 = - sfd__h598113[53] ? - ((_theResult___fst_exp__h598094 == 11'd2046) ? + sfd__h589354[52:1]) : + sfd__h589354[51:0] ; + assign _theResult___sfd__h598776 = + sfd__h598114[53] ? + ((_theResult___fst_exp__h598095 == 11'd2046) ? 52'd0 : - sfd__h598113[52:1]) : - sfd__h598113[51:0] ; - assign _theResult___snd__h354206 = { _theResult____h346084[55:0], 1'd0 } ; - assign _theResult___snd__h354217 = - (!_theResult____h346084[56] && _theResult____h346084[55]) ? - _theResult___snd__h354219 : - _theResult___snd__h354229 ; - assign _theResult___snd__h354219 = { _theResult____h346084[54:0], 2'd0 } ; - assign _theResult___snd__h354229 = - (!_theResult____h346084[56] && !_theResult____h346084[55] && - !_theResult____h346084[54] && - !_theResult____h346084[53] && - !_theResult____h346084[52] && - !_theResult____h346084[51] && - !_theResult____h346084[50] && - !_theResult____h346084[49] && - !_theResult____h346084[48] && - !_theResult____h346084[47] && - !_theResult____h346084[46] && - !_theResult____h346084[45] && - !_theResult____h346084[44] && - !_theResult____h346084[43] && - !_theResult____h346084[42] && - !_theResult____h346084[41] && - !_theResult____h346084[40] && - !_theResult____h346084[39] && - !_theResult____h346084[38] && - !_theResult____h346084[37] && - !_theResult____h346084[36] && - !_theResult____h346084[35] && - !_theResult____h346084[34] && - !_theResult____h346084[33] && - !_theResult____h346084[32] && - !_theResult____h346084[31] && - !_theResult____h346084[30] && - !_theResult____h346084[29] && - !_theResult____h346084[28] && - !_theResult____h346084[27] && - !_theResult____h346084[26] && - !_theResult____h346084[25] && - !_theResult____h346084[24] && - !_theResult____h346084[23] && - !_theResult____h346084[22] && - !_theResult____h346084[21] && - !_theResult____h346084[20] && - !_theResult____h346084[19] && - !_theResult____h346084[18] && - !_theResult____h346084[17] && - !_theResult____h346084[16] && - !_theResult____h346084[15] && - !_theResult____h346084[14] && - !_theResult____h346084[13] && - !_theResult____h346084[12] && - !_theResult____h346084[11] && - !_theResult____h346084[10] && - !_theResult____h346084[9] && - !_theResult____h346084[8] && - !_theResult____h346084[7] && - !_theResult____h346084[6] && - !_theResult____h346084[5] && - !_theResult____h346084[4] && - !_theResult____h346084[3] && - !_theResult____h346084[2] && - !_theResult____h346084[1] && - !_theResult____h346084[0]) ? - _theResult____h346084 : - _theResult___snd__h354235 ; - assign _theResult___snd__h354235 = + sfd__h598114[52:1]) : + sfd__h598114[51:0] ; + assign _theResult___snd__h354207 = { _theResult____h346085[55:0], 1'd0 } ; + assign _theResult___snd__h354218 = + (!_theResult____h346085[56] && _theResult____h346085[55]) ? + _theResult___snd__h354220 : + _theResult___snd__h354230 ; + assign _theResult___snd__h354220 = { _theResult____h346085[54:0], 2'd0 } ; + assign _theResult___snd__h354230 = + (!_theResult____h346085[56] && !_theResult____h346085[55] && + !_theResult____h346085[54] && + !_theResult____h346085[53] && + !_theResult____h346085[52] && + !_theResult____h346085[51] && + !_theResult____h346085[50] && + !_theResult____h346085[49] && + !_theResult____h346085[48] && + !_theResult____h346085[47] && + !_theResult____h346085[46] && + !_theResult____h346085[45] && + !_theResult____h346085[44] && + !_theResult____h346085[43] && + !_theResult____h346085[42] && + !_theResult____h346085[41] && + !_theResult____h346085[40] && + !_theResult____h346085[39] && + !_theResult____h346085[38] && + !_theResult____h346085[37] && + !_theResult____h346085[36] && + !_theResult____h346085[35] && + !_theResult____h346085[34] && + !_theResult____h346085[33] && + !_theResult____h346085[32] && + !_theResult____h346085[31] && + !_theResult____h346085[30] && + !_theResult____h346085[29] && + !_theResult____h346085[28] && + !_theResult____h346085[27] && + !_theResult____h346085[26] && + !_theResult____h346085[25] && + !_theResult____h346085[24] && + !_theResult____h346085[23] && + !_theResult____h346085[22] && + !_theResult____h346085[21] && + !_theResult____h346085[20] && + !_theResult____h346085[19] && + !_theResult____h346085[18] && + !_theResult____h346085[17] && + !_theResult____h346085[16] && + !_theResult____h346085[15] && + !_theResult____h346085[14] && + !_theResult____h346085[13] && + !_theResult____h346085[12] && + !_theResult____h346085[11] && + !_theResult____h346085[10] && + !_theResult____h346085[9] && + !_theResult____h346085[8] && + !_theResult____h346085[7] && + !_theResult____h346085[6] && + !_theResult____h346085[5] && + !_theResult____h346085[4] && + !_theResult____h346085[3] && + !_theResult____h346085[2] && + !_theResult____h346085[1] && + !_theResult____h346085[0]) ? + _theResult____h346085 : + _theResult___snd__h354236 ; + assign _theResult___snd__h354236 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0], 2'd0 } ; - assign _theResult___snd__h354258 = - _theResult____h346084 << + assign _theResult___snd__h354259 = + _theResult____h346085 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 ; - assign _theResult___snd__h362802 = + assign _theResult___snd__h362803 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h362811 : - _theResult___snd__h362804 ; - assign _theResult___snd__h362804 = + _theResult___snd__h362812 : + _theResult___snd__h362805 ; + assign _theResult___snd__h362805 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h362811 = + assign _theResult___snd__h362812 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338479 : - _theResult___snd__h362817 ; - assign _theResult___snd__h362817 = + sfd__h338480 : + _theResult___snd__h362818 ; + assign _theResult___snd__h362818 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h362840 = - sfd__h338479 << + assign _theResult___snd__h362841 = + sfd__h338480 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 ; - assign _theResult___snd__h371972 = { _theResult____h363723[55:0], 1'd0 } ; - assign _theResult___snd__h371983 = - (!_theResult____h363723[56] && _theResult____h363723[55]) ? - _theResult___snd__h371985 : - _theResult___snd__h371995 ; - assign _theResult___snd__h371985 = { _theResult____h363723[54:0], 2'd0 } ; - assign _theResult___snd__h371995 = - (!_theResult____h363723[56] && !_theResult____h363723[55] && - !_theResult____h363723[54] && - !_theResult____h363723[53] && - !_theResult____h363723[52] && - !_theResult____h363723[51] && - !_theResult____h363723[50] && - !_theResult____h363723[49] && - !_theResult____h363723[48] && - !_theResult____h363723[47] && - !_theResult____h363723[46] && - !_theResult____h363723[45] && - !_theResult____h363723[44] && - !_theResult____h363723[43] && - !_theResult____h363723[42] && - !_theResult____h363723[41] && - !_theResult____h363723[40] && - !_theResult____h363723[39] && - !_theResult____h363723[38] && - !_theResult____h363723[37] && - !_theResult____h363723[36] && - !_theResult____h363723[35] && - !_theResult____h363723[34] && - !_theResult____h363723[33] && - !_theResult____h363723[32] && - !_theResult____h363723[31] && - !_theResult____h363723[30] && - !_theResult____h363723[29] && - !_theResult____h363723[28] && - !_theResult____h363723[27] && - !_theResult____h363723[26] && - !_theResult____h363723[25] && - !_theResult____h363723[24] && - !_theResult____h363723[23] && - !_theResult____h363723[22] && - !_theResult____h363723[21] && - !_theResult____h363723[20] && - !_theResult____h363723[19] && - !_theResult____h363723[18] && - !_theResult____h363723[17] && - !_theResult____h363723[16] && - !_theResult____h363723[15] && - !_theResult____h363723[14] && - !_theResult____h363723[13] && - !_theResult____h363723[12] && - !_theResult____h363723[11] && - !_theResult____h363723[10] && - !_theResult____h363723[9] && - !_theResult____h363723[8] && - !_theResult____h363723[7] && - !_theResult____h363723[6] && - !_theResult____h363723[5] && - !_theResult____h363723[4] && - !_theResult____h363723[3] && - !_theResult____h363723[2] && - !_theResult____h363723[1] && - !_theResult____h363723[0]) ? - _theResult____h363723 : - _theResult___snd__h372001 ; - assign _theResult___snd__h372001 = + assign _theResult___snd__h371973 = { _theResult____h363724[55:0], 1'd0 } ; + assign _theResult___snd__h371984 = + (!_theResult____h363724[56] && _theResult____h363724[55]) ? + _theResult___snd__h371986 : + _theResult___snd__h371996 ; + assign _theResult___snd__h371986 = { _theResult____h363724[54:0], 2'd0 } ; + assign _theResult___snd__h371996 = + (!_theResult____h363724[56] && !_theResult____h363724[55] && + !_theResult____h363724[54] && + !_theResult____h363724[53] && + !_theResult____h363724[52] && + !_theResult____h363724[51] && + !_theResult____h363724[50] && + !_theResult____h363724[49] && + !_theResult____h363724[48] && + !_theResult____h363724[47] && + !_theResult____h363724[46] && + !_theResult____h363724[45] && + !_theResult____h363724[44] && + !_theResult____h363724[43] && + !_theResult____h363724[42] && + !_theResult____h363724[41] && + !_theResult____h363724[40] && + !_theResult____h363724[39] && + !_theResult____h363724[38] && + !_theResult____h363724[37] && + !_theResult____h363724[36] && + !_theResult____h363724[35] && + !_theResult____h363724[34] && + !_theResult____h363724[33] && + !_theResult____h363724[32] && + !_theResult____h363724[31] && + !_theResult____h363724[30] && + !_theResult____h363724[29] && + !_theResult____h363724[28] && + !_theResult____h363724[27] && + !_theResult____h363724[26] && + !_theResult____h363724[25] && + !_theResult____h363724[24] && + !_theResult____h363724[23] && + !_theResult____h363724[22] && + !_theResult____h363724[21] && + !_theResult____h363724[20] && + !_theResult____h363724[19] && + !_theResult____h363724[18] && + !_theResult____h363724[17] && + !_theResult____h363724[16] && + !_theResult____h363724[15] && + !_theResult____h363724[14] && + !_theResult____h363724[13] && + !_theResult____h363724[12] && + !_theResult____h363724[11] && + !_theResult____h363724[10] && + !_theResult____h363724[9] && + !_theResult____h363724[8] && + !_theResult____h363724[7] && + !_theResult____h363724[6] && + !_theResult____h363724[5] && + !_theResult____h363724[4] && + !_theResult____h363724[3] && + !_theResult____h363724[2] && + !_theResult____h363724[1] && + !_theResult____h363724[0]) ? + _theResult____h363724 : + _theResult___snd__h372002 ; + assign _theResult___snd__h372002 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0], 2'd0 } ; - assign _theResult___snd__h372024 = - _theResult____h363723 << + assign _theResult___snd__h372025 = + _theResult____h363724 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 ; - assign _theResult___snd__h380592 = + assign _theResult___snd__h380593 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h380606 : - _theResult___snd__h362804 ; - assign _theResult___snd__h380606 = + _theResult___snd__h380607 : + _theResult___snd__h362805 ; + assign _theResult___snd__h380607 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338479 : - _theResult___snd__h380612 ; - assign _theResult___snd__h380612 = + sfd__h338480 : + _theResult___snd__h380613 ; + assign _theResult___snd__h380613 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0], 2'd0 } ; - assign _theResult___snd__h380630 = - sfd__h338479 << + assign _theResult___snd__h380631 = + sfd__h338480 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872) ; - assign _theResult___snd__h399903 = { _theResult____h391783[55:0], 1'd0 } ; - assign _theResult___snd__h399914 = - (!_theResult____h391783[56] && _theResult____h391783[55]) ? - _theResult___snd__h399916 : - _theResult___snd__h399926 ; - assign _theResult___snd__h399916 = { _theResult____h391783[54:0], 2'd0 } ; - assign _theResult___snd__h399926 = - (!_theResult____h391783[56] && !_theResult____h391783[55] && - !_theResult____h391783[54] && - !_theResult____h391783[53] && - !_theResult____h391783[52] && - !_theResult____h391783[51] && - !_theResult____h391783[50] && - !_theResult____h391783[49] && - !_theResult____h391783[48] && - !_theResult____h391783[47] && - !_theResult____h391783[46] && - !_theResult____h391783[45] && - !_theResult____h391783[44] && - !_theResult____h391783[43] && - !_theResult____h391783[42] && - !_theResult____h391783[41] && - !_theResult____h391783[40] && - !_theResult____h391783[39] && - !_theResult____h391783[38] && - !_theResult____h391783[37] && - !_theResult____h391783[36] && - !_theResult____h391783[35] && - !_theResult____h391783[34] && - !_theResult____h391783[33] && - !_theResult____h391783[32] && - !_theResult____h391783[31] && - !_theResult____h391783[30] && - !_theResult____h391783[29] && - !_theResult____h391783[28] && - !_theResult____h391783[27] && - !_theResult____h391783[26] && - !_theResult____h391783[25] && - !_theResult____h391783[24] && - !_theResult____h391783[23] && - !_theResult____h391783[22] && - !_theResult____h391783[21] && - !_theResult____h391783[20] && - !_theResult____h391783[19] && - !_theResult____h391783[18] && - !_theResult____h391783[17] && - !_theResult____h391783[16] && - !_theResult____h391783[15] && - !_theResult____h391783[14] && - !_theResult____h391783[13] && - !_theResult____h391783[12] && - !_theResult____h391783[11] && - !_theResult____h391783[10] && - !_theResult____h391783[9] && - !_theResult____h391783[8] && - !_theResult____h391783[7] && - !_theResult____h391783[6] && - !_theResult____h391783[5] && - !_theResult____h391783[4] && - !_theResult____h391783[3] && - !_theResult____h391783[2] && - !_theResult____h391783[1] && - !_theResult____h391783[0]) ? - _theResult____h391783 : - _theResult___snd__h399932 ; - assign _theResult___snd__h399932 = + assign _theResult___snd__h399904 = { _theResult____h391784[55:0], 1'd0 } ; + assign _theResult___snd__h399915 = + (!_theResult____h391784[56] && _theResult____h391784[55]) ? + _theResult___snd__h399917 : + _theResult___snd__h399927 ; + assign _theResult___snd__h399917 = { _theResult____h391784[54:0], 2'd0 } ; + assign _theResult___snd__h399927 = + (!_theResult____h391784[56] && !_theResult____h391784[55] && + !_theResult____h391784[54] && + !_theResult____h391784[53] && + !_theResult____h391784[52] && + !_theResult____h391784[51] && + !_theResult____h391784[50] && + !_theResult____h391784[49] && + !_theResult____h391784[48] && + !_theResult____h391784[47] && + !_theResult____h391784[46] && + !_theResult____h391784[45] && + !_theResult____h391784[44] && + !_theResult____h391784[43] && + !_theResult____h391784[42] && + !_theResult____h391784[41] && + !_theResult____h391784[40] && + !_theResult____h391784[39] && + !_theResult____h391784[38] && + !_theResult____h391784[37] && + !_theResult____h391784[36] && + !_theResult____h391784[35] && + !_theResult____h391784[34] && + !_theResult____h391784[33] && + !_theResult____h391784[32] && + !_theResult____h391784[31] && + !_theResult____h391784[30] && + !_theResult____h391784[29] && + !_theResult____h391784[28] && + !_theResult____h391784[27] && + !_theResult____h391784[26] && + !_theResult____h391784[25] && + !_theResult____h391784[24] && + !_theResult____h391784[23] && + !_theResult____h391784[22] && + !_theResult____h391784[21] && + !_theResult____h391784[20] && + !_theResult____h391784[19] && + !_theResult____h391784[18] && + !_theResult____h391784[17] && + !_theResult____h391784[16] && + !_theResult____h391784[15] && + !_theResult____h391784[14] && + !_theResult____h391784[13] && + !_theResult____h391784[12] && + !_theResult____h391784[11] && + !_theResult____h391784[10] && + !_theResult____h391784[9] && + !_theResult____h391784[8] && + !_theResult____h391784[7] && + !_theResult____h391784[6] && + !_theResult____h391784[5] && + !_theResult____h391784[4] && + !_theResult____h391784[3] && + !_theResult____h391784[2] && + !_theResult____h391784[1] && + !_theResult____h391784[0]) ? + _theResult____h391784 : + _theResult___snd__h399933 ; + assign _theResult___snd__h399933 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0], 2'd0 } ; - assign _theResult___snd__h399955 = - _theResult____h391783 << + assign _theResult___snd__h399956 = + _theResult____h391784 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 ; - assign _theResult___snd__h408499 = + assign _theResult___snd__h408500 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h408508 : - _theResult___snd__h408501 ; - assign _theResult___snd__h408501 = + _theResult___snd__h408509 : + _theResult___snd__h408502 ; + assign _theResult___snd__h408502 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h408508 = + assign _theResult___snd__h408509 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384181 : - _theResult___snd__h408514 ; - assign _theResult___snd__h408514 = + sfd__h384182 : + _theResult___snd__h408515 ; + assign _theResult___snd__h408515 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h408537 = - sfd__h384181 << + assign _theResult___snd__h408538 = + sfd__h384182 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 ; - assign _theResult___snd__h417669 = { _theResult____h409420[55:0], 1'd0 } ; - assign _theResult___snd__h417680 = - (!_theResult____h409420[56] && _theResult____h409420[55]) ? - _theResult___snd__h417682 : - _theResult___snd__h417692 ; - assign _theResult___snd__h417682 = { _theResult____h409420[54:0], 2'd0 } ; - assign _theResult___snd__h417692 = - (!_theResult____h409420[56] && !_theResult____h409420[55] && - !_theResult____h409420[54] && - !_theResult____h409420[53] && - !_theResult____h409420[52] && - !_theResult____h409420[51] && - !_theResult____h409420[50] && - !_theResult____h409420[49] && - !_theResult____h409420[48] && - !_theResult____h409420[47] && - !_theResult____h409420[46] && - !_theResult____h409420[45] && - !_theResult____h409420[44] && - !_theResult____h409420[43] && - !_theResult____h409420[42] && - !_theResult____h409420[41] && - !_theResult____h409420[40] && - !_theResult____h409420[39] && - !_theResult____h409420[38] && - !_theResult____h409420[37] && - !_theResult____h409420[36] && - !_theResult____h409420[35] && - !_theResult____h409420[34] && - !_theResult____h409420[33] && - !_theResult____h409420[32] && - !_theResult____h409420[31] && - !_theResult____h409420[30] && - !_theResult____h409420[29] && - !_theResult____h409420[28] && - !_theResult____h409420[27] && - !_theResult____h409420[26] && - !_theResult____h409420[25] && - !_theResult____h409420[24] && - !_theResult____h409420[23] && - !_theResult____h409420[22] && - !_theResult____h409420[21] && - !_theResult____h409420[20] && - !_theResult____h409420[19] && - !_theResult____h409420[18] && - !_theResult____h409420[17] && - !_theResult____h409420[16] && - !_theResult____h409420[15] && - !_theResult____h409420[14] && - !_theResult____h409420[13] && - !_theResult____h409420[12] && - !_theResult____h409420[11] && - !_theResult____h409420[10] && - !_theResult____h409420[9] && - !_theResult____h409420[8] && - !_theResult____h409420[7] && - !_theResult____h409420[6] && - !_theResult____h409420[5] && - !_theResult____h409420[4] && - !_theResult____h409420[3] && - !_theResult____h409420[2] && - !_theResult____h409420[1] && - !_theResult____h409420[0]) ? - _theResult____h409420 : - _theResult___snd__h417698 ; - assign _theResult___snd__h417698 = + assign _theResult___snd__h417670 = { _theResult____h409421[55:0], 1'd0 } ; + assign _theResult___snd__h417681 = + (!_theResult____h409421[56] && _theResult____h409421[55]) ? + _theResult___snd__h417683 : + _theResult___snd__h417693 ; + assign _theResult___snd__h417683 = { _theResult____h409421[54:0], 2'd0 } ; + assign _theResult___snd__h417693 = + (!_theResult____h409421[56] && !_theResult____h409421[55] && + !_theResult____h409421[54] && + !_theResult____h409421[53] && + !_theResult____h409421[52] && + !_theResult____h409421[51] && + !_theResult____h409421[50] && + !_theResult____h409421[49] && + !_theResult____h409421[48] && + !_theResult____h409421[47] && + !_theResult____h409421[46] && + !_theResult____h409421[45] && + !_theResult____h409421[44] && + !_theResult____h409421[43] && + !_theResult____h409421[42] && + !_theResult____h409421[41] && + !_theResult____h409421[40] && + !_theResult____h409421[39] && + !_theResult____h409421[38] && + !_theResult____h409421[37] && + !_theResult____h409421[36] && + !_theResult____h409421[35] && + !_theResult____h409421[34] && + !_theResult____h409421[33] && + !_theResult____h409421[32] && + !_theResult____h409421[31] && + !_theResult____h409421[30] && + !_theResult____h409421[29] && + !_theResult____h409421[28] && + !_theResult____h409421[27] && + !_theResult____h409421[26] && + !_theResult____h409421[25] && + !_theResult____h409421[24] && + !_theResult____h409421[23] && + !_theResult____h409421[22] && + !_theResult____h409421[21] && + !_theResult____h409421[20] && + !_theResult____h409421[19] && + !_theResult____h409421[18] && + !_theResult____h409421[17] && + !_theResult____h409421[16] && + !_theResult____h409421[15] && + !_theResult____h409421[14] && + !_theResult____h409421[13] && + !_theResult____h409421[12] && + !_theResult____h409421[11] && + !_theResult____h409421[10] && + !_theResult____h409421[9] && + !_theResult____h409421[8] && + !_theResult____h409421[7] && + !_theResult____h409421[6] && + !_theResult____h409421[5] && + !_theResult____h409421[4] && + !_theResult____h409421[3] && + !_theResult____h409421[2] && + !_theResult____h409421[1] && + !_theResult____h409421[0]) ? + _theResult____h409421 : + _theResult___snd__h417699 ; + assign _theResult___snd__h417699 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0], 2'd0 } ; - assign _theResult___snd__h417721 = - _theResult____h409420 << + assign _theResult___snd__h417722 = + _theResult____h409421 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 ; - assign _theResult___snd__h426289 = + assign _theResult___snd__h426290 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h426303 : - _theResult___snd__h408501 ; - assign _theResult___snd__h426303 = + _theResult___snd__h426304 : + _theResult___snd__h408502 ; + assign _theResult___snd__h426304 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384181 : - _theResult___snd__h426309 ; - assign _theResult___snd__h426309 = + sfd__h384182 : + _theResult___snd__h426310 ; + assign _theResult___snd__h426310 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0], 2'd0 } ; - assign _theResult___snd__h426327 = - sfd__h384181 << + assign _theResult___snd__h426328 = + sfd__h384182 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264) ; - assign _theResult___snd__h445598 = { _theResult____h437478[55:0], 1'd0 } ; - assign _theResult___snd__h445609 = - (!_theResult____h437478[56] && _theResult____h437478[55]) ? - _theResult___snd__h445611 : - _theResult___snd__h445621 ; - assign _theResult___snd__h445611 = { _theResult____h437478[54:0], 2'd0 } ; - assign _theResult___snd__h445621 = - (!_theResult____h437478[56] && !_theResult____h437478[55] && - !_theResult____h437478[54] && - !_theResult____h437478[53] && - !_theResult____h437478[52] && - !_theResult____h437478[51] && - !_theResult____h437478[50] && - !_theResult____h437478[49] && - !_theResult____h437478[48] && - !_theResult____h437478[47] && - !_theResult____h437478[46] && - !_theResult____h437478[45] && - !_theResult____h437478[44] && - !_theResult____h437478[43] && - !_theResult____h437478[42] && - !_theResult____h437478[41] && - !_theResult____h437478[40] && - !_theResult____h437478[39] && - !_theResult____h437478[38] && - !_theResult____h437478[37] && - !_theResult____h437478[36] && - !_theResult____h437478[35] && - !_theResult____h437478[34] && - !_theResult____h437478[33] && - !_theResult____h437478[32] && - !_theResult____h437478[31] && - !_theResult____h437478[30] && - !_theResult____h437478[29] && - !_theResult____h437478[28] && - !_theResult____h437478[27] && - !_theResult____h437478[26] && - !_theResult____h437478[25] && - !_theResult____h437478[24] && - !_theResult____h437478[23] && - !_theResult____h437478[22] && - !_theResult____h437478[21] && - !_theResult____h437478[20] && - !_theResult____h437478[19] && - !_theResult____h437478[18] && - !_theResult____h437478[17] && - !_theResult____h437478[16] && - !_theResult____h437478[15] && - !_theResult____h437478[14] && - !_theResult____h437478[13] && - !_theResult____h437478[12] && - !_theResult____h437478[11] && - !_theResult____h437478[10] && - !_theResult____h437478[9] && - !_theResult____h437478[8] && - !_theResult____h437478[7] && - !_theResult____h437478[6] && - !_theResult____h437478[5] && - !_theResult____h437478[4] && - !_theResult____h437478[3] && - !_theResult____h437478[2] && - !_theResult____h437478[1] && - !_theResult____h437478[0]) ? - _theResult____h437478 : - _theResult___snd__h445627 ; - assign _theResult___snd__h445627 = + assign _theResult___snd__h445599 = { _theResult____h437479[55:0], 1'd0 } ; + assign _theResult___snd__h445610 = + (!_theResult____h437479[56] && _theResult____h437479[55]) ? + _theResult___snd__h445612 : + _theResult___snd__h445622 ; + assign _theResult___snd__h445612 = { _theResult____h437479[54:0], 2'd0 } ; + assign _theResult___snd__h445622 = + (!_theResult____h437479[56] && !_theResult____h437479[55] && + !_theResult____h437479[54] && + !_theResult____h437479[53] && + !_theResult____h437479[52] && + !_theResult____h437479[51] && + !_theResult____h437479[50] && + !_theResult____h437479[49] && + !_theResult____h437479[48] && + !_theResult____h437479[47] && + !_theResult____h437479[46] && + !_theResult____h437479[45] && + !_theResult____h437479[44] && + !_theResult____h437479[43] && + !_theResult____h437479[42] && + !_theResult____h437479[41] && + !_theResult____h437479[40] && + !_theResult____h437479[39] && + !_theResult____h437479[38] && + !_theResult____h437479[37] && + !_theResult____h437479[36] && + !_theResult____h437479[35] && + !_theResult____h437479[34] && + !_theResult____h437479[33] && + !_theResult____h437479[32] && + !_theResult____h437479[31] && + !_theResult____h437479[30] && + !_theResult____h437479[29] && + !_theResult____h437479[28] && + !_theResult____h437479[27] && + !_theResult____h437479[26] && + !_theResult____h437479[25] && + !_theResult____h437479[24] && + !_theResult____h437479[23] && + !_theResult____h437479[22] && + !_theResult____h437479[21] && + !_theResult____h437479[20] && + !_theResult____h437479[19] && + !_theResult____h437479[18] && + !_theResult____h437479[17] && + !_theResult____h437479[16] && + !_theResult____h437479[15] && + !_theResult____h437479[14] && + !_theResult____h437479[13] && + !_theResult____h437479[12] && + !_theResult____h437479[11] && + !_theResult____h437479[10] && + !_theResult____h437479[9] && + !_theResult____h437479[8] && + !_theResult____h437479[7] && + !_theResult____h437479[6] && + !_theResult____h437479[5] && + !_theResult____h437479[4] && + !_theResult____h437479[3] && + !_theResult____h437479[2] && + !_theResult____h437479[1] && + !_theResult____h437479[0]) ? + _theResult____h437479 : + _theResult___snd__h445628 ; + assign _theResult___snd__h445628 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0], 2'd0 } ; - assign _theResult___snd__h445650 = - _theResult____h437478 << + assign _theResult___snd__h445651 = + _theResult____h437479 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 ; - assign _theResult___snd__h454194 = + assign _theResult___snd__h454195 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h454203 : - _theResult___snd__h454196 ; - assign _theResult___snd__h454196 = + _theResult___snd__h454204 : + _theResult___snd__h454197 ; + assign _theResult___snd__h454197 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h454203 = + assign _theResult___snd__h454204 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429876 : - _theResult___snd__h454209 ; - assign _theResult___snd__h454209 = + sfd__h429877 : + _theResult___snd__h454210 ; + assign _theResult___snd__h454210 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h454232 = - sfd__h429876 << + assign _theResult___snd__h454233 = + sfd__h429877 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 ; - assign _theResult___snd__h463364 = { _theResult____h455115[55:0], 1'd0 } ; - assign _theResult___snd__h463375 = - (!_theResult____h455115[56] && _theResult____h455115[55]) ? - _theResult___snd__h463377 : - _theResult___snd__h463387 ; - assign _theResult___snd__h463377 = { _theResult____h455115[54:0], 2'd0 } ; - assign _theResult___snd__h463387 = - (!_theResult____h455115[56] && !_theResult____h455115[55] && - !_theResult____h455115[54] && - !_theResult____h455115[53] && - !_theResult____h455115[52] && - !_theResult____h455115[51] && - !_theResult____h455115[50] && - !_theResult____h455115[49] && - !_theResult____h455115[48] && - !_theResult____h455115[47] && - !_theResult____h455115[46] && - !_theResult____h455115[45] && - !_theResult____h455115[44] && - !_theResult____h455115[43] && - !_theResult____h455115[42] && - !_theResult____h455115[41] && - !_theResult____h455115[40] && - !_theResult____h455115[39] && - !_theResult____h455115[38] && - !_theResult____h455115[37] && - !_theResult____h455115[36] && - !_theResult____h455115[35] && - !_theResult____h455115[34] && - !_theResult____h455115[33] && - !_theResult____h455115[32] && - !_theResult____h455115[31] && - !_theResult____h455115[30] && - !_theResult____h455115[29] && - !_theResult____h455115[28] && - !_theResult____h455115[27] && - !_theResult____h455115[26] && - !_theResult____h455115[25] && - !_theResult____h455115[24] && - !_theResult____h455115[23] && - !_theResult____h455115[22] && - !_theResult____h455115[21] && - !_theResult____h455115[20] && - !_theResult____h455115[19] && - !_theResult____h455115[18] && - !_theResult____h455115[17] && - !_theResult____h455115[16] && - !_theResult____h455115[15] && - !_theResult____h455115[14] && - !_theResult____h455115[13] && - !_theResult____h455115[12] && - !_theResult____h455115[11] && - !_theResult____h455115[10] && - !_theResult____h455115[9] && - !_theResult____h455115[8] && - !_theResult____h455115[7] && - !_theResult____h455115[6] && - !_theResult____h455115[5] && - !_theResult____h455115[4] && - !_theResult____h455115[3] && - !_theResult____h455115[2] && - !_theResult____h455115[1] && - !_theResult____h455115[0]) ? - _theResult____h455115 : - _theResult___snd__h463393 ; - assign _theResult___snd__h463393 = + assign _theResult___snd__h463365 = { _theResult____h455116[55:0], 1'd0 } ; + assign _theResult___snd__h463376 = + (!_theResult____h455116[56] && _theResult____h455116[55]) ? + _theResult___snd__h463378 : + _theResult___snd__h463388 ; + assign _theResult___snd__h463378 = { _theResult____h455116[54:0], 2'd0 } ; + assign _theResult___snd__h463388 = + (!_theResult____h455116[56] && !_theResult____h455116[55] && + !_theResult____h455116[54] && + !_theResult____h455116[53] && + !_theResult____h455116[52] && + !_theResult____h455116[51] && + !_theResult____h455116[50] && + !_theResult____h455116[49] && + !_theResult____h455116[48] && + !_theResult____h455116[47] && + !_theResult____h455116[46] && + !_theResult____h455116[45] && + !_theResult____h455116[44] && + !_theResult____h455116[43] && + !_theResult____h455116[42] && + !_theResult____h455116[41] && + !_theResult____h455116[40] && + !_theResult____h455116[39] && + !_theResult____h455116[38] && + !_theResult____h455116[37] && + !_theResult____h455116[36] && + !_theResult____h455116[35] && + !_theResult____h455116[34] && + !_theResult____h455116[33] && + !_theResult____h455116[32] && + !_theResult____h455116[31] && + !_theResult____h455116[30] && + !_theResult____h455116[29] && + !_theResult____h455116[28] && + !_theResult____h455116[27] && + !_theResult____h455116[26] && + !_theResult____h455116[25] && + !_theResult____h455116[24] && + !_theResult____h455116[23] && + !_theResult____h455116[22] && + !_theResult____h455116[21] && + !_theResult____h455116[20] && + !_theResult____h455116[19] && + !_theResult____h455116[18] && + !_theResult____h455116[17] && + !_theResult____h455116[16] && + !_theResult____h455116[15] && + !_theResult____h455116[14] && + !_theResult____h455116[13] && + !_theResult____h455116[12] && + !_theResult____h455116[11] && + !_theResult____h455116[10] && + !_theResult____h455116[9] && + !_theResult____h455116[8] && + !_theResult____h455116[7] && + !_theResult____h455116[6] && + !_theResult____h455116[5] && + !_theResult____h455116[4] && + !_theResult____h455116[3] && + !_theResult____h455116[2] && + !_theResult____h455116[1] && + !_theResult____h455116[0]) ? + _theResult____h455116 : + _theResult___snd__h463394 ; + assign _theResult___snd__h463394 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0], 2'd0 } ; - assign _theResult___snd__h463416 = - _theResult____h455115 << + assign _theResult___snd__h463417 = + _theResult____h455116 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 ; - assign _theResult___snd__h471984 = + assign _theResult___snd__h471985 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h471998 : - _theResult___snd__h454196 ; - assign _theResult___snd__h471998 = + _theResult___snd__h471999 : + _theResult___snd__h454197 ; + assign _theResult___snd__h471999 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429876 : - _theResult___snd__h472004 ; - assign _theResult___snd__h472004 = + sfd__h429877 : + _theResult___snd__h472005 ; + assign _theResult___snd__h472005 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0], 2'd0 } ; - assign _theResult___snd__h472022 = - sfd__h429876 << + assign _theResult___snd__h472023 = + sfd__h429877 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656) ; - assign _theResult___snd__h501478 = - (f1_exp__h482139 == 8'd0) ? - _theResult___snd__h501487 : - _theResult___snd__h501480 ; - assign _theResult___snd__h501480 = { f1_sfd__h482140, 34'd0 } ; - assign _theResult___snd__h501487 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___snd__h501479 = + (f1_exp__h482140 == 8'd0) ? + _theResult___snd__h501488 : + _theResult___snd__h501481 ; + assign _theResult___snd__h501481 = { f1_sfd__h482141, 34'd0 } ; + assign _theResult___snd__h501488 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482501 : - _theResult___snd__h501493 ; - assign _theResult___snd__h501493 = + sfd__h482502 : + _theResult___snd__h501494 ; + assign _theResult___snd__h501494 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h501516 = - sfd__h482501 << + assign _theResult___snd__h501517 = + sfd__h482502 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 ; - assign _theResult___snd__h511115 = { _theResult____h502868[55:0], 1'd0 } ; - assign _theResult___snd__h511126 = - (!_theResult____h502868[56] && _theResult____h502868[55]) ? - _theResult___snd__h511128 : - _theResult___snd__h511138 ; - assign _theResult___snd__h511128 = { _theResult____h502868[54:0], 2'd0 } ; - assign _theResult___snd__h511138 = - (!_theResult____h502868[56] && !_theResult____h502868[55] && - !_theResult____h502868[54] && - !_theResult____h502868[53] && - !_theResult____h502868[52] && - !_theResult____h502868[51] && - !_theResult____h502868[50] && - !_theResult____h502868[49] && - !_theResult____h502868[48] && - !_theResult____h502868[47] && - !_theResult____h502868[46] && - !_theResult____h502868[45] && - !_theResult____h502868[44] && - !_theResult____h502868[43] && - !_theResult____h502868[42] && - !_theResult____h502868[41] && - !_theResult____h502868[40] && - !_theResult____h502868[39] && - !_theResult____h502868[38] && - !_theResult____h502868[37] && - !_theResult____h502868[36] && - !_theResult____h502868[35] && - !_theResult____h502868[34] && - !_theResult____h502868[33] && - !_theResult____h502868[32] && - !_theResult____h502868[31] && - !_theResult____h502868[30] && - !_theResult____h502868[29] && - !_theResult____h502868[28] && - !_theResult____h502868[27] && - !_theResult____h502868[26] && - !_theResult____h502868[25] && - !_theResult____h502868[24] && - !_theResult____h502868[23] && - !_theResult____h502868[22] && - !_theResult____h502868[21] && - !_theResult____h502868[20] && - !_theResult____h502868[19] && - !_theResult____h502868[18] && - !_theResult____h502868[17] && - !_theResult____h502868[16] && - !_theResult____h502868[15] && - !_theResult____h502868[14] && - !_theResult____h502868[13] && - !_theResult____h502868[12] && - !_theResult____h502868[11] && - !_theResult____h502868[10] && - !_theResult____h502868[9] && - !_theResult____h502868[8] && - !_theResult____h502868[7] && - !_theResult____h502868[6] && - !_theResult____h502868[5] && - !_theResult____h502868[4] && - !_theResult____h502868[3] && - !_theResult____h502868[2] && - !_theResult____h502868[1] && - !_theResult____h502868[0]) ? - _theResult____h502868 : - _theResult___snd__h511144 ; - assign _theResult___snd__h511144 = + assign _theResult___snd__h511116 = { _theResult____h502869[55:0], 1'd0 } ; + assign _theResult___snd__h511127 = + (!_theResult____h502869[56] && _theResult____h502869[55]) ? + _theResult___snd__h511129 : + _theResult___snd__h511139 ; + assign _theResult___snd__h511129 = { _theResult____h502869[54:0], 2'd0 } ; + assign _theResult___snd__h511139 = + (!_theResult____h502869[56] && !_theResult____h502869[55] && + !_theResult____h502869[54] && + !_theResult____h502869[53] && + !_theResult____h502869[52] && + !_theResult____h502869[51] && + !_theResult____h502869[50] && + !_theResult____h502869[49] && + !_theResult____h502869[48] && + !_theResult____h502869[47] && + !_theResult____h502869[46] && + !_theResult____h502869[45] && + !_theResult____h502869[44] && + !_theResult____h502869[43] && + !_theResult____h502869[42] && + !_theResult____h502869[41] && + !_theResult____h502869[40] && + !_theResult____h502869[39] && + !_theResult____h502869[38] && + !_theResult____h502869[37] && + !_theResult____h502869[36] && + !_theResult____h502869[35] && + !_theResult____h502869[34] && + !_theResult____h502869[33] && + !_theResult____h502869[32] && + !_theResult____h502869[31] && + !_theResult____h502869[30] && + !_theResult____h502869[29] && + !_theResult____h502869[28] && + !_theResult____h502869[27] && + !_theResult____h502869[26] && + !_theResult____h502869[25] && + !_theResult____h502869[24] && + !_theResult____h502869[23] && + !_theResult____h502869[22] && + !_theResult____h502869[21] && + !_theResult____h502869[20] && + !_theResult____h502869[19] && + !_theResult____h502869[18] && + !_theResult____h502869[17] && + !_theResult____h502869[16] && + !_theResult____h502869[15] && + !_theResult____h502869[14] && + !_theResult____h502869[13] && + !_theResult____h502869[12] && + !_theResult____h502869[11] && + !_theResult____h502869[10] && + !_theResult____h502869[9] && + !_theResult____h502869[8] && + !_theResult____h502869[7] && + !_theResult____h502869[6] && + !_theResult____h502869[5] && + !_theResult____h502869[4] && + !_theResult____h502869[3] && + !_theResult____h502869[2] && + !_theResult____h502869[1] && + !_theResult____h502869[0]) ? + _theResult____h502869 : + _theResult___snd__h511145 ; + assign _theResult___snd__h511145 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h511167 = - _theResult____h502868 << + assign _theResult___snd__h511168 = + _theResult____h502869 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 ; - assign _theResult___snd__h519883 = - (f1_exp__h482139 == 8'd0) ? - _theResult___snd__h519897 : - _theResult___snd__h501480 ; - assign _theResult___snd__h519897 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___snd__h519884 = + (f1_exp__h482140 == 8'd0) ? + _theResult___snd__h519898 : + _theResult___snd__h501481 ; + assign _theResult___snd__h519898 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482501 : - _theResult___snd__h519903 ; - assign _theResult___snd__h519903 = + sfd__h482502 : + _theResult___snd__h519904 ; + assign _theResult___snd__h519904 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h519921 = - sfd__h482501 << + assign _theResult___snd__h519922 = + sfd__h482502 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ; - assign _theResult___snd__h540331 = - (f2_exp__h521133 == 8'd0) ? - _theResult___snd__h540340 : - _theResult___snd__h540333 ; - assign _theResult___snd__h540333 = { f2_sfd__h521134, 34'd0 } ; - assign _theResult___snd__h540340 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___snd__h540332 = + (f2_exp__h521134 == 8'd0) ? + _theResult___snd__h540341 : + _theResult___snd__h540334 ; + assign _theResult___snd__h540334 = { f2_sfd__h521135, 34'd0 } ; + assign _theResult___snd__h540341 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521495 : - _theResult___snd__h540346 ; - assign _theResult___snd__h540346 = + sfd__h521496 : + _theResult___snd__h540347 ; + assign _theResult___snd__h540347 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h540369 = - sfd__h521495 << + assign _theResult___snd__h540370 = + sfd__h521496 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 ; - assign _theResult___snd__h549968 = { _theResult____h541721[55:0], 1'd0 } ; - assign _theResult___snd__h549979 = - (!_theResult____h541721[56] && _theResult____h541721[55]) ? - _theResult___snd__h549981 : - _theResult___snd__h549991 ; - assign _theResult___snd__h549981 = { _theResult____h541721[54:0], 2'd0 } ; - assign _theResult___snd__h549991 = - (!_theResult____h541721[56] && !_theResult____h541721[55] && - !_theResult____h541721[54] && - !_theResult____h541721[53] && - !_theResult____h541721[52] && - !_theResult____h541721[51] && - !_theResult____h541721[50] && - !_theResult____h541721[49] && - !_theResult____h541721[48] && - !_theResult____h541721[47] && - !_theResult____h541721[46] && - !_theResult____h541721[45] && - !_theResult____h541721[44] && - !_theResult____h541721[43] && - !_theResult____h541721[42] && - !_theResult____h541721[41] && - !_theResult____h541721[40] && - !_theResult____h541721[39] && - !_theResult____h541721[38] && - !_theResult____h541721[37] && - !_theResult____h541721[36] && - !_theResult____h541721[35] && - !_theResult____h541721[34] && - !_theResult____h541721[33] && - !_theResult____h541721[32] && - !_theResult____h541721[31] && - !_theResult____h541721[30] && - !_theResult____h541721[29] && - !_theResult____h541721[28] && - !_theResult____h541721[27] && - !_theResult____h541721[26] && - !_theResult____h541721[25] && - !_theResult____h541721[24] && - !_theResult____h541721[23] && - !_theResult____h541721[22] && - !_theResult____h541721[21] && - !_theResult____h541721[20] && - !_theResult____h541721[19] && - !_theResult____h541721[18] && - !_theResult____h541721[17] && - !_theResult____h541721[16] && - !_theResult____h541721[15] && - !_theResult____h541721[14] && - !_theResult____h541721[13] && - !_theResult____h541721[12] && - !_theResult____h541721[11] && - !_theResult____h541721[10] && - !_theResult____h541721[9] && - !_theResult____h541721[8] && - !_theResult____h541721[7] && - !_theResult____h541721[6] && - !_theResult____h541721[5] && - !_theResult____h541721[4] && - !_theResult____h541721[3] && - !_theResult____h541721[2] && - !_theResult____h541721[1] && - !_theResult____h541721[0]) ? - _theResult____h541721 : - _theResult___snd__h549997 ; - assign _theResult___snd__h549997 = + assign _theResult___snd__h549969 = { _theResult____h541722[55:0], 1'd0 } ; + assign _theResult___snd__h549980 = + (!_theResult____h541722[56] && _theResult____h541722[55]) ? + _theResult___snd__h549982 : + _theResult___snd__h549992 ; + assign _theResult___snd__h549982 = { _theResult____h541722[54:0], 2'd0 } ; + assign _theResult___snd__h549992 = + (!_theResult____h541722[56] && !_theResult____h541722[55] && + !_theResult____h541722[54] && + !_theResult____h541722[53] && + !_theResult____h541722[52] && + !_theResult____h541722[51] && + !_theResult____h541722[50] && + !_theResult____h541722[49] && + !_theResult____h541722[48] && + !_theResult____h541722[47] && + !_theResult____h541722[46] && + !_theResult____h541722[45] && + !_theResult____h541722[44] && + !_theResult____h541722[43] && + !_theResult____h541722[42] && + !_theResult____h541722[41] && + !_theResult____h541722[40] && + !_theResult____h541722[39] && + !_theResult____h541722[38] && + !_theResult____h541722[37] && + !_theResult____h541722[36] && + !_theResult____h541722[35] && + !_theResult____h541722[34] && + !_theResult____h541722[33] && + !_theResult____h541722[32] && + !_theResult____h541722[31] && + !_theResult____h541722[30] && + !_theResult____h541722[29] && + !_theResult____h541722[28] && + !_theResult____h541722[27] && + !_theResult____h541722[26] && + !_theResult____h541722[25] && + !_theResult____h541722[24] && + !_theResult____h541722[23] && + !_theResult____h541722[22] && + !_theResult____h541722[21] && + !_theResult____h541722[20] && + !_theResult____h541722[19] && + !_theResult____h541722[18] && + !_theResult____h541722[17] && + !_theResult____h541722[16] && + !_theResult____h541722[15] && + !_theResult____h541722[14] && + !_theResult____h541722[13] && + !_theResult____h541722[12] && + !_theResult____h541722[11] && + !_theResult____h541722[10] && + !_theResult____h541722[9] && + !_theResult____h541722[8] && + !_theResult____h541722[7] && + !_theResult____h541722[6] && + !_theResult____h541722[5] && + !_theResult____h541722[4] && + !_theResult____h541722[3] && + !_theResult____h541722[2] && + !_theResult____h541722[1] && + !_theResult____h541722[0]) ? + _theResult____h541722 : + _theResult___snd__h549998 ; + assign _theResult___snd__h549998 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h550020 = - _theResult____h541721 << + assign _theResult___snd__h550021 = + _theResult____h541722 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 ; - assign _theResult___snd__h558736 = - (f2_exp__h521133 == 8'd0) ? - _theResult___snd__h558750 : - _theResult___snd__h540333 ; - assign _theResult___snd__h558750 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___snd__h558737 = + (f2_exp__h521134 == 8'd0) ? + _theResult___snd__h558751 : + _theResult___snd__h540334 ; + assign _theResult___snd__h558751 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521495 : - _theResult___snd__h558756 ; - assign _theResult___snd__h558756 = + sfd__h521496 : + _theResult___snd__h558757 ; + assign _theResult___snd__h558757 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h558774 = - sfd__h521495 << + assign _theResult___snd__h558775 = + sfd__h521496 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ; - assign _theResult___snd__h579635 = - (f3_exp__h560437 == 8'd0) ? - _theResult___snd__h579644 : - _theResult___snd__h579637 ; - assign _theResult___snd__h579637 = { f3_sfd__h560438, 34'd0 } ; - assign _theResult___snd__h579644 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___snd__h579636 = + (f3_exp__h560438 == 8'd0) ? + _theResult___snd__h579645 : + _theResult___snd__h579638 ; + assign _theResult___snd__h579638 = { f3_sfd__h560439, 34'd0 } ; + assign _theResult___snd__h579645 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560799 : - _theResult___snd__h579650 ; - assign _theResult___snd__h579650 = + sfd__h560800 : + _theResult___snd__h579651 ; + assign _theResult___snd__h579651 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h579673 = - sfd__h560799 << + assign _theResult___snd__h579674 = + sfd__h560800 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 ; - assign _theResult___snd__h589272 = { _theResult____h581025[55:0], 1'd0 } ; - assign _theResult___snd__h589283 = - (!_theResult____h581025[56] && _theResult____h581025[55]) ? - _theResult___snd__h589285 : - _theResult___snd__h589295 ; - assign _theResult___snd__h589285 = { _theResult____h581025[54:0], 2'd0 } ; - assign _theResult___snd__h589295 = - (!_theResult____h581025[56] && !_theResult____h581025[55] && - !_theResult____h581025[54] && - !_theResult____h581025[53] && - !_theResult____h581025[52] && - !_theResult____h581025[51] && - !_theResult____h581025[50] && - !_theResult____h581025[49] && - !_theResult____h581025[48] && - !_theResult____h581025[47] && - !_theResult____h581025[46] && - !_theResult____h581025[45] && - !_theResult____h581025[44] && - !_theResult____h581025[43] && - !_theResult____h581025[42] && - !_theResult____h581025[41] && - !_theResult____h581025[40] && - !_theResult____h581025[39] && - !_theResult____h581025[38] && - !_theResult____h581025[37] && - !_theResult____h581025[36] && - !_theResult____h581025[35] && - !_theResult____h581025[34] && - !_theResult____h581025[33] && - !_theResult____h581025[32] && - !_theResult____h581025[31] && - !_theResult____h581025[30] && - !_theResult____h581025[29] && - !_theResult____h581025[28] && - !_theResult____h581025[27] && - !_theResult____h581025[26] && - !_theResult____h581025[25] && - !_theResult____h581025[24] && - !_theResult____h581025[23] && - !_theResult____h581025[22] && - !_theResult____h581025[21] && - !_theResult____h581025[20] && - !_theResult____h581025[19] && - !_theResult____h581025[18] && - !_theResult____h581025[17] && - !_theResult____h581025[16] && - !_theResult____h581025[15] && - !_theResult____h581025[14] && - !_theResult____h581025[13] && - !_theResult____h581025[12] && - !_theResult____h581025[11] && - !_theResult____h581025[10] && - !_theResult____h581025[9] && - !_theResult____h581025[8] && - !_theResult____h581025[7] && - !_theResult____h581025[6] && - !_theResult____h581025[5] && - !_theResult____h581025[4] && - !_theResult____h581025[3] && - !_theResult____h581025[2] && - !_theResult____h581025[1] && - !_theResult____h581025[0]) ? - _theResult____h581025 : - _theResult___snd__h589301 ; - assign _theResult___snd__h589301 = + assign _theResult___snd__h589273 = { _theResult____h581026[55:0], 1'd0 } ; + assign _theResult___snd__h589284 = + (!_theResult____h581026[56] && _theResult____h581026[55]) ? + _theResult___snd__h589286 : + _theResult___snd__h589296 ; + assign _theResult___snd__h589286 = { _theResult____h581026[54:0], 2'd0 } ; + assign _theResult___snd__h589296 = + (!_theResult____h581026[56] && !_theResult____h581026[55] && + !_theResult____h581026[54] && + !_theResult____h581026[53] && + !_theResult____h581026[52] && + !_theResult____h581026[51] && + !_theResult____h581026[50] && + !_theResult____h581026[49] && + !_theResult____h581026[48] && + !_theResult____h581026[47] && + !_theResult____h581026[46] && + !_theResult____h581026[45] && + !_theResult____h581026[44] && + !_theResult____h581026[43] && + !_theResult____h581026[42] && + !_theResult____h581026[41] && + !_theResult____h581026[40] && + !_theResult____h581026[39] && + !_theResult____h581026[38] && + !_theResult____h581026[37] && + !_theResult____h581026[36] && + !_theResult____h581026[35] && + !_theResult____h581026[34] && + !_theResult____h581026[33] && + !_theResult____h581026[32] && + !_theResult____h581026[31] && + !_theResult____h581026[30] && + !_theResult____h581026[29] && + !_theResult____h581026[28] && + !_theResult____h581026[27] && + !_theResult____h581026[26] && + !_theResult____h581026[25] && + !_theResult____h581026[24] && + !_theResult____h581026[23] && + !_theResult____h581026[22] && + !_theResult____h581026[21] && + !_theResult____h581026[20] && + !_theResult____h581026[19] && + !_theResult____h581026[18] && + !_theResult____h581026[17] && + !_theResult____h581026[16] && + !_theResult____h581026[15] && + !_theResult____h581026[14] && + !_theResult____h581026[13] && + !_theResult____h581026[12] && + !_theResult____h581026[11] && + !_theResult____h581026[10] && + !_theResult____h581026[9] && + !_theResult____h581026[8] && + !_theResult____h581026[7] && + !_theResult____h581026[6] && + !_theResult____h581026[5] && + !_theResult____h581026[4] && + !_theResult____h581026[3] && + !_theResult____h581026[2] && + !_theResult____h581026[1] && + !_theResult____h581026[0]) ? + _theResult____h581026 : + _theResult___snd__h589302 ; + assign _theResult___snd__h589302 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h589324 = - _theResult____h581025 << + assign _theResult___snd__h589325 = + _theResult____h581026 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 ; - assign _theResult___snd__h598040 = - (f3_exp__h560437 == 8'd0) ? - _theResult___snd__h598054 : - _theResult___snd__h579637 ; - assign _theResult___snd__h598054 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___snd__h598041 = + (f3_exp__h560438 == 8'd0) ? + _theResult___snd__h598055 : + _theResult___snd__h579638 ; + assign _theResult___snd__h598055 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560799 : - _theResult___snd__h598060 ; - assign _theResult___snd__h598060 = + sfd__h560800 : + _theResult___snd__h598061 ; + assign _theResult___snd__h598061 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h598078 = - sfd__h560799 << + assign _theResult___snd__h598079 = + sfd__h560800 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ; - assign _theResult___snd__h603370 = - b__h602948[63] ? b___1__h603419 : b__h602948 ; - assign _theResult___snd_fst_exp__h363377 = + assign _theResult___snd__h603371 = + b__h602949[63] ? b___1__h603420 : b__h602949 ; + assign _theResult___snd_fst_exp__h363378 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_exp__h354792 : - _theResult___fst_exp__h363374 ; - assign _theResult___snd_fst_exp__h381197 = + _theResult___fst_exp__h354793 : + _theResult___fst_exp__h363375 ; + assign _theResult___snd_fst_exp__h381198 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_exp__h372558 : - _theResult___fst_exp__h381194 ; - assign _theResult___snd_fst_exp__h409074 = + _theResult___fst_exp__h372559 : + _theResult___fst_exp__h381195 ; + assign _theResult___snd_fst_exp__h409075 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_exp__h400489 : - _theResult___fst_exp__h409071 ; - assign _theResult___snd_fst_exp__h426894 = + _theResult___fst_exp__h400490 : + _theResult___fst_exp__h409072 ; + assign _theResult___snd_fst_exp__h426895 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_exp__h418255 : - _theResult___fst_exp__h426891 ; - assign _theResult___snd_fst_exp__h454769 = + _theResult___fst_exp__h418256 : + _theResult___fst_exp__h426892 ; + assign _theResult___snd_fst_exp__h454770 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_exp__h446184 : - _theResult___fst_exp__h454766 ; - assign _theResult___snd_fst_exp__h472589 = + _theResult___fst_exp__h446185 : + _theResult___fst_exp__h454767 ; + assign _theResult___snd_fst_exp__h472590 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_exp__h463950 : - _theResult___fst_exp__h472586 ; - assign _theResult___snd_fst_exp__h502288 = + _theResult___fst_exp__h463951 : + _theResult___fst_exp__h472587 ; + assign _theResult___snd_fst_exp__h502289 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 11'd0 : - _theResult___fst_exp__h502285 ; - assign _theResult___snd_fst_exp__h520723 = + _theResult___fst_exp__h502286 ; + assign _theResult___snd_fst_exp__h520724 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_exp__h511936 : - _theResult___fst_exp__h520720 ; - assign _theResult___snd_fst_exp__h541141 = + _theResult___fst_exp__h511937 : + _theResult___fst_exp__h520721 ; + assign _theResult___snd_fst_exp__h541142 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 11'd0 : - _theResult___fst_exp__h541138 ; - assign _theResult___snd_fst_exp__h559576 = + _theResult___fst_exp__h541139 ; + assign _theResult___snd_fst_exp__h559577 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_exp__h550789 : - _theResult___fst_exp__h559573 ; - assign _theResult___snd_fst_exp__h580445 = + _theResult___fst_exp__h550790 : + _theResult___fst_exp__h559574 ; + assign _theResult___snd_fst_exp__h580446 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 11'd0 : - _theResult___fst_exp__h580442 ; - assign _theResult___snd_fst_exp__h598880 = + _theResult___fst_exp__h580443 ; + assign _theResult___snd_fst_exp__h598881 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_exp__h590093 : - _theResult___fst_exp__h598877 ; - assign _theResult___snd_fst_sfd__h338429 = + _theResult___fst_exp__h590094 : + _theResult___fst_exp__h598878 ; + assign _theResult___snd_fst_sfd__h338430 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h363378 = + assign _theResult___snd_fst_sfd__h363379 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_sfd__h354793 : - _theResult___fst_sfd__h363375 ; - assign _theResult___snd_fst_sfd__h381198 = + _theResult___fst_sfd__h354794 : + _theResult___fst_sfd__h363376 ; + assign _theResult___snd_fst_sfd__h381199 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_sfd__h372559 : - _theResult___fst_sfd__h381195 ; - assign _theResult___snd_fst_sfd__h384131 = + _theResult___fst_sfd__h372560 : + _theResult___fst_sfd__h381196 ; + assign _theResult___snd_fst_sfd__h384132 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h409075 = + assign _theResult___snd_fst_sfd__h409076 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_sfd__h400490 : - _theResult___fst_sfd__h409072 ; - assign _theResult___snd_fst_sfd__h426895 = + _theResult___fst_sfd__h400491 : + _theResult___fst_sfd__h409073 ; + assign _theResult___snd_fst_sfd__h426896 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_sfd__h418256 : - _theResult___fst_sfd__h426892 ; - assign _theResult___snd_fst_sfd__h429826 = + _theResult___fst_sfd__h418257 : + _theResult___fst_sfd__h426893 ; + assign _theResult___snd_fst_sfd__h429827 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h454770 = + assign _theResult___snd_fst_sfd__h454771 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_sfd__h446185 : - _theResult___fst_sfd__h454767 ; - assign _theResult___snd_fst_sfd__h472590 = + _theResult___fst_sfd__h446186 : + _theResult___fst_sfd__h454768 ; + assign _theResult___snd_fst_sfd__h472591 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_sfd__h463951 : - _theResult___fst_sfd__h472587 ; - assign _theResult___snd_fst_sfd__h482455 = - (f1_sfd__h482140 == 23'd0) ? + _theResult___fst_sfd__h463952 : + _theResult___fst_sfd__h472588 ; + assign _theResult___snd_fst_sfd__h482456 = + (f1_sfd__h482141 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h482203 ; - assign _theResult___snd_fst_sfd__h502289 = + out___1_sfd__h482204 ; + assign _theResult___snd_fst_sfd__h502290 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 52'd0 : - _theResult___fst_sfd__h502286 ; - assign _theResult___snd_fst_sfd__h520724 = + _theResult___fst_sfd__h502287 ; + assign _theResult___snd_fst_sfd__h520725 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_sfd__h511937 : - _theResult___fst_sfd__h520721 ; - assign _theResult___snd_fst_sfd__h521449 = - (f2_sfd__h521134 == 23'd0) ? + _theResult___fst_sfd__h511938 : + _theResult___fst_sfd__h520722 ; + assign _theResult___snd_fst_sfd__h521450 = + (f2_sfd__h521135 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h521197 ; - assign _theResult___snd_fst_sfd__h541142 = + out___1_sfd__h521198 ; + assign _theResult___snd_fst_sfd__h541143 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 52'd0 : - _theResult___fst_sfd__h541139 ; - assign _theResult___snd_fst_sfd__h559577 = + _theResult___fst_sfd__h541140 ; + assign _theResult___snd_fst_sfd__h559578 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_sfd__h550790 : - _theResult___fst_sfd__h559574 ; - assign _theResult___snd_fst_sfd__h560753 = - (f3_sfd__h560438 == 23'd0) ? + _theResult___fst_sfd__h550791 : + _theResult___fst_sfd__h559575 ; + assign _theResult___snd_fst_sfd__h560754 = + (f3_sfd__h560439 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h560501 ; - assign _theResult___snd_fst_sfd__h580446 = + out___1_sfd__h560502 ; + assign _theResult___snd_fst_sfd__h580447 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 52'd0 : - _theResult___fst_sfd__h580443 ; - assign _theResult___snd_fst_sfd__h598881 = + _theResult___fst_sfd__h580444 ; + assign _theResult___snd_fst_sfd__h598882 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_sfd__h590094 : - _theResult___fst_sfd__h598878 ; - assign a___1__h603088 = + _theResult___fst_sfd__h590095 : + _theResult___fst_sfd__h598879 ; + assign a___1__h603089 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ; - assign a___1__h603374 = 64'd0 - a__h602947 ; - assign a__h602947 = + assign a___1__h603375 = 64'd0 - a__h602948 ; + assign a__h602948 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h603088 : + a___1__h603089 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h603089 = + assign b___1__h603090 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h603419 = 64'd0 - b__h602948 ; - assign b__h602948 = + assign b___1__h603420 = 64'd0 - b__h602949 ; + assign b__h602949 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h603089 : + b___1__h603090 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h711423 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h711443 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h708463 = - commitStage_commitTrap[36] ? i__h708638 : i__h708478 ; - assign commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 = + assign base__h712403 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h712423 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h709443 = + commitStage_commitTrap[36] ? i__h709618 : i__h709458 ; + assign commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && commitStage_commitTrap[35:32] != 4'd1 && @@ -29560,9 +29586,16 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd11 || !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 ; - assign commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438 = - commitStage_rg_serial_num + y__h729714 ; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; + assign commitStage_f_rob_data_first__4755_BIT_167_485_ETC___d14927 = + { commitStage_f_rob_data$D_OUT[167:166], + commitStage_f_rob_data$D_OUT[166] ? + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, + trap_val__h709444, + IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926 } ; + assign commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450 = + commitStage_rg_serial_num + y__h730732 ; assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29710,9 +29743,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29720,9 +29753,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29730,9 +29763,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29740,9 +29773,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29750,9 +29783,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -29792,7 +29825,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h254802 ; + y__h254803 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 || @@ -30010,15 +30043,15 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_deqReq_rl) && coreFix_memExe_forwardQ_full ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706 = - { coreFix_memExe_lsq$getOrigBE << x__h183901[2:0], - x__h183901, + { coreFix_memExe_lsq$getOrigBE << x__h183902[2:0], + x__h183902, coreFix_memExe_regToExeQ$first[75:12], coreFix_memExe_lsq$getOrigBE, coreFix_memExe_lsq$getOrigBE[7] ? - x__h183901[2:0] != 3'd0 : + x__h183902[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - x__h183901[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && x__h183901[0]) } ; + x__h183902[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && x__h183902[0]) } ; assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 = coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 || @@ -30090,12 +30123,12 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646 = + assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14656 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign csr_addr__h655325 = + assign csr_addr__h655327 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 : 12'hCFF ; @@ -30111,7 +30144,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 || csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 || - csr_addr__h655325 == 12'h8FF) ; + csr_addr__h655327 == 12'h8FF) ; assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -30136,31 +30169,31 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 = - csrf_prv_reg_read__2787_ULE_1___d14685 && + assign csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 = + csrf_prv_reg_read__2787_ULE_1___d14696 && (commitStage_commitTrap[36] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705) ; - assign csrf_prv_reg_read__2787_ULE_1___d14685 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716) ; + assign csrf_prv_reg_read__2787_ULE_1___d14696 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 = - csrf_prv_reg < csr_addr__h655325[9:8] ; + csrf_prv_reg < csr_addr__h655327[9:8] ; assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435 ; - assign data75281_BITS_31_TO_0__q14 = data__h475281[31:0] ; - assign data___1__h475007 = + assign data75282_BITS_31_TO_0__q13 = data__h475282[31:0] ; + assign data___1__h475008 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; - assign data___1__h475815 = - { {32{data75281_BITS_31_TO_0__q14[31]}}, - data75281_BITS_31_TO_0__q14 } ; - assign data__h475281 = + assign data___1__h475816 = + { {32{data75282_BITS_31_TO_0__q13[31]}}, + data75282_BITS_31_TO_0__q13 } ; + assign data__h475282 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h475195 : - x_remainder__h475196 ; - assign dcsr_cause__h707982 = + x_quotient__h475196 : + x_remainder__h475197 ; + assign dcsr_cause__h708962 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30177,31 +30210,31 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h381228 = _theResult___fst_exp__h354195 + 8'd1 ; - assign din_inc___2_exp__h381252 = _theResult___fst_exp__h362851 + 8'd1 ; - assign din_inc___2_exp__h381282 = _theResult___fst_exp__h371961 + 8'd1 ; - assign din_inc___2_exp__h381306 = _theResult___fst_exp__h380646 + 8'd1 ; - assign din_inc___2_exp__h426925 = _theResult___fst_exp__h399892 + 8'd1 ; - assign din_inc___2_exp__h426949 = _theResult___fst_exp__h408548 + 8'd1 ; - assign din_inc___2_exp__h426979 = _theResult___fst_exp__h417658 + 8'd1 ; - assign din_inc___2_exp__h427003 = _theResult___fst_exp__h426343 + 8'd1 ; - assign din_inc___2_exp__h472620 = _theResult___fst_exp__h445587 + 8'd1 ; - assign din_inc___2_exp__h472644 = _theResult___fst_exp__h454243 + 8'd1 ; - assign din_inc___2_exp__h472674 = _theResult___fst_exp__h463353 + 8'd1 ; - assign din_inc___2_exp__h472698 = _theResult___fst_exp__h472038 + 8'd1 ; - assign din_inc___2_exp__h520777 = _theResult___fst_exp__h501527 + 11'd1 ; - assign din_inc___2_exp__h520812 = _theResult___fst_exp__h511104 + 11'd1 ; - assign din_inc___2_exp__h520838 = _theResult___fst_exp__h519937 + 11'd1 ; - assign din_inc___2_exp__h559630 = _theResult___fst_exp__h540380 + 11'd1 ; - assign din_inc___2_exp__h559665 = _theResult___fst_exp__h549957 + 11'd1 ; - assign din_inc___2_exp__h559691 = _theResult___fst_exp__h558790 + 11'd1 ; - assign din_inc___2_exp__h598934 = _theResult___fst_exp__h579684 + 11'd1 ; - assign din_inc___2_exp__h598969 = _theResult___fst_exp__h589261 + 11'd1 ; - assign din_inc___2_exp__h598995 = _theResult___fst_exp__h598094 + 11'd1 ; - assign enabled_ints___1__h651641 = pend_ints__h651114 & y__h651653 ; - assign enabled_ints__h651687 = - pend_ints__h651114 & - { r1__read_BITS_13_TO_0___h651663, csrf_mideleg_1_0_reg } ; + assign din_inc___2_exp__h381229 = _theResult___fst_exp__h354196 + 8'd1 ; + assign din_inc___2_exp__h381253 = _theResult___fst_exp__h362852 + 8'd1 ; + assign din_inc___2_exp__h381283 = _theResult___fst_exp__h371962 + 8'd1 ; + assign din_inc___2_exp__h381307 = _theResult___fst_exp__h380647 + 8'd1 ; + assign din_inc___2_exp__h426926 = _theResult___fst_exp__h399893 + 8'd1 ; + assign din_inc___2_exp__h426950 = _theResult___fst_exp__h408549 + 8'd1 ; + assign din_inc___2_exp__h426980 = _theResult___fst_exp__h417659 + 8'd1 ; + assign din_inc___2_exp__h427004 = _theResult___fst_exp__h426344 + 8'd1 ; + assign din_inc___2_exp__h472621 = _theResult___fst_exp__h445588 + 8'd1 ; + assign din_inc___2_exp__h472645 = _theResult___fst_exp__h454244 + 8'd1 ; + assign din_inc___2_exp__h472675 = _theResult___fst_exp__h463354 + 8'd1 ; + assign din_inc___2_exp__h472699 = _theResult___fst_exp__h472039 + 8'd1 ; + assign din_inc___2_exp__h520778 = _theResult___fst_exp__h501528 + 11'd1 ; + assign din_inc___2_exp__h520813 = _theResult___fst_exp__h511105 + 11'd1 ; + assign din_inc___2_exp__h520839 = _theResult___fst_exp__h519938 + 11'd1 ; + assign din_inc___2_exp__h559631 = _theResult___fst_exp__h540381 + 11'd1 ; + assign din_inc___2_exp__h559666 = _theResult___fst_exp__h549958 + 11'd1 ; + assign din_inc___2_exp__h559692 = _theResult___fst_exp__h558791 + 11'd1 ; + assign din_inc___2_exp__h598935 = _theResult___fst_exp__h579685 + 11'd1 ; + assign din_inc___2_exp__h598970 = _theResult___fst_exp__h589262 + 11'd1 ; + assign din_inc___2_exp__h598996 = _theResult___fst_exp__h598095 + 11'd1 ; + assign enabled_ints___1__h651643 = pend_ints__h651116 & y__h651655 ; + assign enabled_ints__h651689 = + pend_ints__h651116 & + { r1__read_BITS_13_TO_0___h651665, csrf_mideleg_1_0_reg } ; assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || @@ -30223,44 +30256,44 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 && IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890) ; - assign f1_exp82139_MINUS_127__q136 = f1_exp__h482139 - 8'd127 ; - assign f1_exp__h482139 = + assign f1_exp82140_MINUS_127__q136 = f1_exp__h482140 - 8'd127 ; + assign f1_exp__h482140 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h482140 = + assign f1_sfd__h482141 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp21133_MINUS_127__q176 = f2_exp__h521133 - 8'd127 ; - assign f2_exp__h521133 = + assign f2_exp21134_MINUS_127__q176 = f2_exp__h521134 - 8'd127 ; + assign f2_exp__h521134 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h521134 = + assign f2_sfd__h521135 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp60437_MINUS_127__q153 = f3_exp__h560437 - 8'd127 ; - assign f3_exp__h560437 = + assign f3_exp60438_MINUS_127__q153 = f3_exp__h560438 - 8'd127 ; + assign f3_exp__h560438 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h560438 = + assign f3_sfd__h560439 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880 = + assign f_csr_rsps_i_notFull__5790_AND_f_csr_reqs_firs_ETC___d15893 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h609375 = { 56'd0, x__h613033 } ; + assign fcsr_csr__read__h609377 = { 56'd0, x__h613035 } ; assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || @@ -30341,9 +30374,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h655326 != 5'd0 || - imm__h655327 != 32'd0) && - csr_addr__h655325[11:10] == 2'b11 ; + rs1__h655328 != 5'd0 || + imm__h655329 != 32'd0) && + csr_addr__h655327[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -30450,7 +30483,7 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h727255 = + assign fflags__h728257 = ({ rob$deqPort_0_deq_data[361:356], 1'd0, rob$deqPort_0_deq_data[354:350], @@ -30460,8 +30493,8 @@ module mkCore(CLK, rob$deqPort_0_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h727241 ; - assign fflags__h729891 = + po_fflags__h728242 ; + assign fflags__h730910 = ({ rob$deqPort_1_deq_data[361:356], 1'd0, rob$deqPort_1_deq_data[354:350], @@ -30471,105 +30504,105 @@ module mkCore(CLK, rob$deqPort_1_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h729877 ; - assign fflags__h732495 = - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ? - y_avValue_fst__h732432 : - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 ; - assign fflags_csr__read__h609350 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h609361 = { 61'd0, csrf_frm_reg } ; - assign guard__h346094 = - { IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29[1], - { sfdin__h354189[32:0], 23'd0 } != 56'd0 } ; - assign guard__h354803 = - { IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31[1], - { _theResult___snd__h362802[32:0], 23'd0 } != 56'd0 } ; - assign guard__h363733 = - { IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39[1], - { sfdin__h371955[32:0], 23'd0 } != 56'd0 } ; - assign guard__h364331 = x__h364433 != 57'd0 ; - assign guard__h372569 = - { IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44[1], - { _theResult___snd__h380592[32:0], 23'd0 } != 56'd0 } ; - assign guard__h391793 = - { IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64[1], - { sfdin__h399886[32:0], 23'd0 } != 56'd0 } ; - assign guard__h400500 = - { IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66[1], - { _theResult___snd__h408499[32:0], 23'd0 } != 56'd0 } ; - assign guard__h409430 = - { IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74[1], - { sfdin__h417652[32:0], 23'd0 } != 56'd0 } ; - assign guard__h410028 = x__h410130 != 57'd0 ; - assign guard__h418266 = - { IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79[1], - { _theResult___snd__h426289[32:0], 23'd0 } != 56'd0 } ; - assign guard__h437488 = - { IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99[1], - { sfdin__h445581[32:0], 23'd0 } != 56'd0 } ; - assign guard__h446195 = - { IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h454194[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455125 = - { IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109[1], - { sfdin__h463347[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455723 = x__h455825 != 57'd0 ; - assign guard__h463961 = - { IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114[1], - { _theResult___snd__h471984[32:0], 23'd0 } != 56'd0 } ; - assign guard__h493566 = - { IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h501478[3:0], 52'd0 } != 56'd0 } ; - assign guard__h502878 = - { IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h511098[3:0], 52'd0 } != 56'd0 } ; - assign guard__h503476 = x__h503576 != 57'd0 ; - assign guard__h511947 = - { IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h519883[3:0], 52'd0 } != 56'd0 } ; - assign guard__h532419 = - { IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h540331[3:0], 52'd0 } != 56'd0 } ; - assign guard__h541731 = - { IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h549951[3:0], 52'd0 } != 56'd0 } ; - assign guard__h542329 = x__h542429 != 57'd0 ; - assign guard__h550800 = - { IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h558736[3:0], 52'd0 } != 56'd0 } ; - assign guard__h571723 = - { IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h579635[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581035 = - { IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h589255[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581633 = x__h581733 != 57'd0 ; - assign guard__h590104 = - { IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h598040[3:0], 52'd0 } != 56'd0 } ; - assign idx__h685368 = + po_fflags__h730895 ; + assign fflags__h733530 = + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 ? + y_avValue_fst__h733467 : + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 ; + assign fflags_csr__read__h609352 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h609363 = { 61'd0, csrf_frm_reg } ; + assign guard__h346095 = + { IF_sfdin54190_BIT_33_THEN_2_ELSE_0__q29[1], + { sfdin__h354190[32:0], 23'd0 } != 56'd0 } ; + assign guard__h354804 = + { IF_theResult___snd62803_BIT_33_THEN_2_ELSE_0__q31[1], + { _theResult___snd__h362803[32:0], 23'd0 } != 56'd0 } ; + assign guard__h363734 = + { IF_sfdin71956_BIT_33_THEN_2_ELSE_0__q39[1], + { sfdin__h371956[32:0], 23'd0 } != 56'd0 } ; + assign guard__h364332 = x__h364434 != 57'd0 ; + assign guard__h372570 = + { IF_theResult___snd80593_BIT_33_THEN_2_ELSE_0__q44[1], + { _theResult___snd__h380593[32:0], 23'd0 } != 56'd0 } ; + assign guard__h391794 = + { IF_sfdin99887_BIT_33_THEN_2_ELSE_0__q64[1], + { sfdin__h399887[32:0], 23'd0 } != 56'd0 } ; + assign guard__h400501 = + { IF_theResult___snd08500_BIT_33_THEN_2_ELSE_0__q66[1], + { _theResult___snd__h408500[32:0], 23'd0 } != 56'd0 } ; + assign guard__h409431 = + { IF_sfdin17653_BIT_33_THEN_2_ELSE_0__q74[1], + { sfdin__h417653[32:0], 23'd0 } != 56'd0 } ; + assign guard__h410029 = x__h410131 != 57'd0 ; + assign guard__h418267 = + { IF_theResult___snd26290_BIT_33_THEN_2_ELSE_0__q79[1], + { _theResult___snd__h426290[32:0], 23'd0 } != 56'd0 } ; + assign guard__h437489 = + { IF_sfdin45582_BIT_33_THEN_2_ELSE_0__q99[1], + { sfdin__h445582[32:0], 23'd0 } != 56'd0 } ; + assign guard__h446196 = + { IF_theResult___snd54195_BIT_33_THEN_2_ELSE_0__q101[1], + { _theResult___snd__h454195[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455126 = + { IF_sfdin63348_BIT_33_THEN_2_ELSE_0__q109[1], + { sfdin__h463348[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455724 = x__h455826 != 57'd0 ; + assign guard__h463962 = + { IF_theResult___snd71985_BIT_33_THEN_2_ELSE_0__q114[1], + { _theResult___snd__h471985[32:0], 23'd0 } != 56'd0 } ; + assign guard__h493567 = + { IF_theResult___snd01479_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h501479[3:0], 52'd0 } != 56'd0 } ; + assign guard__h502879 = + { IF_sfdin11099_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h511099[3:0], 52'd0 } != 56'd0 } ; + assign guard__h503477 = x__h503577 != 57'd0 ; + assign guard__h511948 = + { IF_theResult___snd19884_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h519884[3:0], 52'd0 } != 56'd0 } ; + assign guard__h532420 = + { IF_theResult___snd40332_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h540332[3:0], 52'd0 } != 56'd0 } ; + assign guard__h541732 = + { IF_sfdin49952_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h549952[3:0], 52'd0 } != 56'd0 } ; + assign guard__h542330 = x__h542430 != 57'd0 ; + assign guard__h550801 = + { IF_theResult___snd58737_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h558737[3:0], 52'd0 } != 56'd0 } ; + assign guard__h571724 = + { IF_theResult___snd79636_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h579636[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581036 = + { IF_sfdin89256_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h589256[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581634 = x__h581734 != 57'd0 ; + assign guard__h590105 = + { IF_theResult___snd98041_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h598041[3:0], 52'd0 } != 56'd0 } ; + assign idx__h685370 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 || !coreFix_aluExe_0_rsAlu$canEnq || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770 ; - assign imm__h655327 = + assign imm__h655329 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h669623 = + assign k__h669625 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ; - assign mcause_csr__read__h611017 = - { r1__read__h614496, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h610762 = - { r1__read__h614483, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h610369 = - { r1__read__h614344, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h610464 = - { r1__read__h614361, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h610588 = { r1__read__h614385, 1'b0 } ; - assign mip_csr__read__h611250 = { r1__read__h614502, 1'b0 } ; + assign mcause_csr__read__h611019 = + { r1__read__h614498, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h610764 = + { r1__read__h614485, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h610371 = + { r1__read__h614346, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h610466 = + { r1__read__h614363, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h610590 = { r1__read__h614387, 1'b0 } ; + assign mip_csr__read__h611252 = { r1__read__h614504, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30653,41 +30686,41 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h76121 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h610221 = { r1__read__h614219, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h610670 = - { r1__read__h614478, csrf_mtvec_mode_low_reg } ; - assign n___1__h198528 = + assign msip__h76122 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h610223 = { r1__read__h614221, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h610672 = + { r1__read__h614480, csrf_mtvec_mode_low_reg } ; + assign n___1__h198529 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h197125[63:56], + x__h197126[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h197125[55:48], + x__h197126[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h197125[47:40], + x__h197126[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h197125[39:32], + x__h197126[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h197125[31:24], + x__h197126[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h197125[23:16], + x__h197126[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h197125[15:8], + x__h197126[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h197125[7:0] } ; - assign n__read__h611354 = + x__h197126[7:0] } ; + assign n__read__h611356 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h611545 = + assign n__read__h611547 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -30698,257 +30731,257 @@ module mkCore(CLK, upd__h6873 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h725937 = + assign n__read__h726937 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h296799 = + assign next_deqP___1__h296800 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h304795 = + assign next_deqP___1__h304796 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h311076 = + assign next_deqP___1__h311077 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h318930 = + assign next_deqP___1__h318931 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h328987 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h332212 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h721469 = + assign next_deqP___1__h328988 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h332213 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h722452 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign old_fflags__h731983 = + assign old_fflags__h733017 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; - assign out___1_sfd__h482203 = { f1_sfd__h482140, 29'd0 } ; - assign out___1_sfd__h521197 = { f2_sfd__h521134, 29'd0 } ; - assign out___1_sfd__h560501 = { f3_sfd__h560438, 29'd0 } ; - assign out_exp__h354714 = - sfdin__h354189[34] ? - _theResult___exp__h354711 : - _theResult___fst_exp__h354195 ; - assign out_exp__h363296 = - _theResult___snd__h362802[34] ? - _theResult___exp__h363293 : - _theResult___fst_exp__h362851 ; - assign out_exp__h372480 = - sfdin__h371955[34] ? - _theResult___exp__h372477 : - _theResult___fst_exp__h371961 ; - assign out_exp__h381116 = - _theResult___snd__h380592[34] ? - _theResult___exp__h381113 : - _theResult___fst_exp__h380646 ; - assign out_exp__h400411 = - sfdin__h399886[34] ? - _theResult___exp__h400408 : - _theResult___fst_exp__h399892 ; - assign out_exp__h408993 = - _theResult___snd__h408499[34] ? - _theResult___exp__h408990 : - _theResult___fst_exp__h408548 ; - assign out_exp__h418177 = - sfdin__h417652[34] ? - _theResult___exp__h418174 : - _theResult___fst_exp__h417658 ; - assign out_exp__h426813 = - _theResult___snd__h426289[34] ? - _theResult___exp__h426810 : - _theResult___fst_exp__h426343 ; - assign out_exp__h446106 = - sfdin__h445581[34] ? - _theResult___exp__h446103 : - _theResult___fst_exp__h445587 ; - assign out_exp__h454688 = - _theResult___snd__h454194[34] ? - _theResult___exp__h454685 : - _theResult___fst_exp__h454243 ; - assign out_exp__h463872 = - sfdin__h463347[34] ? - _theResult___exp__h463869 : - _theResult___fst_exp__h463353 ; - assign out_exp__h472508 = - _theResult___snd__h471984[34] ? - _theResult___exp__h472505 : - _theResult___fst_exp__h472038 ; - assign out_exp__h502185 = - _theResult___snd__h501478[5] ? - _theResult___exp__h502182 : - _theResult___fst_exp__h501527 ; - assign out_exp__h511836 = - sfdin__h511098[5] ? - _theResult___exp__h511833 : - _theResult___fst_exp__h511104 ; - assign out_exp__h520620 = - _theResult___snd__h519883[5] ? - _theResult___exp__h520617 : - _theResult___fst_exp__h519937 ; - assign out_exp__h541038 = - _theResult___snd__h540331[5] ? - _theResult___exp__h541035 : - _theResult___fst_exp__h540380 ; - assign out_exp__h550689 = - sfdin__h549951[5] ? - _theResult___exp__h550686 : - _theResult___fst_exp__h549957 ; - assign out_exp__h559473 = - _theResult___snd__h558736[5] ? - _theResult___exp__h559470 : - _theResult___fst_exp__h558790 ; - assign out_exp__h580342 = - _theResult___snd__h579635[5] ? - _theResult___exp__h580339 : - _theResult___fst_exp__h579684 ; - assign out_exp__h589993 = - sfdin__h589255[5] ? - _theResult___exp__h589990 : - _theResult___fst_exp__h589261 ; - assign out_exp__h598777 = - _theResult___snd__h598040[5] ? - _theResult___exp__h598774 : - _theResult___fst_exp__h598094 ; - assign out_f_exp__h381492 = - (_theResult___exp__h381215 == 8'd255 && - _theResult___sfd__h381216 != 23'd0 || + assign out___1_sfd__h482204 = { f1_sfd__h482141, 29'd0 } ; + assign out___1_sfd__h521198 = { f2_sfd__h521135, 29'd0 } ; + assign out___1_sfd__h560502 = { f3_sfd__h560439, 29'd0 } ; + assign out_exp__h354715 = + sfdin__h354190[34] ? + _theResult___exp__h354712 : + _theResult___fst_exp__h354196 ; + assign out_exp__h363297 = + _theResult___snd__h362803[34] ? + _theResult___exp__h363294 : + _theResult___fst_exp__h362852 ; + assign out_exp__h372481 = + sfdin__h371956[34] ? + _theResult___exp__h372478 : + _theResult___fst_exp__h371962 ; + assign out_exp__h381117 = + _theResult___snd__h380593[34] ? + _theResult___exp__h381114 : + _theResult___fst_exp__h380647 ; + assign out_exp__h400412 = + sfdin__h399887[34] ? + _theResult___exp__h400409 : + _theResult___fst_exp__h399893 ; + assign out_exp__h408994 = + _theResult___snd__h408500[34] ? + _theResult___exp__h408991 : + _theResult___fst_exp__h408549 ; + assign out_exp__h418178 = + sfdin__h417653[34] ? + _theResult___exp__h418175 : + _theResult___fst_exp__h417659 ; + assign out_exp__h426814 = + _theResult___snd__h426290[34] ? + _theResult___exp__h426811 : + _theResult___fst_exp__h426344 ; + assign out_exp__h446107 = + sfdin__h445582[34] ? + _theResult___exp__h446104 : + _theResult___fst_exp__h445588 ; + assign out_exp__h454689 = + _theResult___snd__h454195[34] ? + _theResult___exp__h454686 : + _theResult___fst_exp__h454244 ; + assign out_exp__h463873 = + sfdin__h463348[34] ? + _theResult___exp__h463870 : + _theResult___fst_exp__h463354 ; + assign out_exp__h472509 = + _theResult___snd__h471985[34] ? + _theResult___exp__h472506 : + _theResult___fst_exp__h472039 ; + assign out_exp__h502186 = + _theResult___snd__h501479[5] ? + _theResult___exp__h502183 : + _theResult___fst_exp__h501528 ; + assign out_exp__h511837 = + sfdin__h511099[5] ? + _theResult___exp__h511834 : + _theResult___fst_exp__h511105 ; + assign out_exp__h520621 = + _theResult___snd__h519884[5] ? + _theResult___exp__h520618 : + _theResult___fst_exp__h519938 ; + assign out_exp__h541039 = + _theResult___snd__h540332[5] ? + _theResult___exp__h541036 : + _theResult___fst_exp__h540381 ; + assign out_exp__h550690 = + sfdin__h549952[5] ? + _theResult___exp__h550687 : + _theResult___fst_exp__h549958 ; + assign out_exp__h559474 = + _theResult___snd__h558737[5] ? + _theResult___exp__h559471 : + _theResult___fst_exp__h558791 ; + assign out_exp__h580343 = + _theResult___snd__h579636[5] ? + _theResult___exp__h580340 : + _theResult___fst_exp__h579685 ; + assign out_exp__h589994 = + sfdin__h589256[5] ? + _theResult___exp__h589991 : + _theResult___fst_exp__h589262 ; + assign out_exp__h598778 = + _theResult___snd__h598041[5] ? + _theResult___exp__h598775 : + _theResult___fst_exp__h598095 ; + assign out_f_exp__h381493 = + (_theResult___exp__h381216 == 8'd255 && + _theResult___sfd__h381217 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381206 ; - assign out_f_exp__h427189 = - (_theResult___exp__h426912 == 8'd255 && - _theResult___sfd__h426913 != 23'd0 || + _theResult___fst_exp__h381207 ; + assign out_f_exp__h427190 = + (_theResult___exp__h426913 == 8'd255 && + _theResult___sfd__h426914 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426903 ; - assign out_f_exp__h472884 = - (_theResult___exp__h472607 == 8'd255 && - _theResult___sfd__h472608 != 23'd0 || + _theResult___fst_exp__h426904 ; + assign out_f_exp__h472885 = + (_theResult___exp__h472608 == 8'd255 && + _theResult___sfd__h472609 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472598 ; - assign out_f_sfd__h381493 = - (_theResult___exp__h381215 == 8'd255 && - _theResult___sfd__h381216 != 23'd0) ? + _theResult___fst_exp__h472599 ; + assign out_f_sfd__h381494 = + (_theResult___exp__h381216 == 8'd255 && + _theResult___sfd__h381217 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h381216 ; - assign out_f_sfd__h427190 = - (_theResult___exp__h426912 == 8'd255 && - _theResult___sfd__h426913 != 23'd0) ? + _theResult___sfd__h381217 ; + assign out_f_sfd__h427191 = + (_theResult___exp__h426913 == 8'd255 && + _theResult___sfd__h426914 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h426913 ; - assign out_f_sfd__h472885 = - (_theResult___exp__h472607 == 8'd255 && - _theResult___sfd__h472608 != 23'd0) ? + _theResult___sfd__h426914 ; + assign out_f_sfd__h472886 = + (_theResult___exp__h472608 == 8'd255 && + _theResult___sfd__h472609 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h472608 ; - assign out_sfd__h354715 = - sfdin__h354189[34] ? - _theResult___sfd__h354712 : - sfdin__h354189[56:34] ; - assign out_sfd__h363297 = - _theResult___snd__h362802[34] ? - _theResult___sfd__h363294 : - _theResult___snd__h362802[56:34] ; - assign out_sfd__h372481 = - sfdin__h371955[34] ? - _theResult___sfd__h372478 : - sfdin__h371955[56:34] ; - assign out_sfd__h381117 = - _theResult___snd__h380592[34] ? - _theResult___sfd__h381114 : - _theResult___snd__h380592[56:34] ; - assign out_sfd__h400412 = - sfdin__h399886[34] ? - _theResult___sfd__h400409 : - sfdin__h399886[56:34] ; - assign out_sfd__h408994 = - _theResult___snd__h408499[34] ? - _theResult___sfd__h408991 : - _theResult___snd__h408499[56:34] ; - assign out_sfd__h418178 = - sfdin__h417652[34] ? - _theResult___sfd__h418175 : - sfdin__h417652[56:34] ; - assign out_sfd__h426814 = - _theResult___snd__h426289[34] ? - _theResult___sfd__h426811 : - _theResult___snd__h426289[56:34] ; - assign out_sfd__h446107 = - sfdin__h445581[34] ? - _theResult___sfd__h446104 : - sfdin__h445581[56:34] ; - assign out_sfd__h454689 = - _theResult___snd__h454194[34] ? - _theResult___sfd__h454686 : - _theResult___snd__h454194[56:34] ; - assign out_sfd__h463873 = - sfdin__h463347[34] ? - _theResult___sfd__h463870 : - sfdin__h463347[56:34] ; - assign out_sfd__h472509 = - _theResult___snd__h471984[34] ? - _theResult___sfd__h472506 : - _theResult___snd__h471984[56:34] ; - assign out_sfd__h502186 = - _theResult___snd__h501478[5] ? - _theResult___sfd__h502183 : - _theResult___snd__h501478[56:5] ; - assign out_sfd__h511837 = - sfdin__h511098[5] ? - _theResult___sfd__h511834 : - sfdin__h511098[56:5] ; - assign out_sfd__h520621 = - _theResult___snd__h519883[5] ? - _theResult___sfd__h520618 : - _theResult___snd__h519883[56:5] ; - assign out_sfd__h541039 = - _theResult___snd__h540331[5] ? - _theResult___sfd__h541036 : - _theResult___snd__h540331[56:5] ; - assign out_sfd__h550690 = - sfdin__h549951[5] ? - _theResult___sfd__h550687 : - sfdin__h549951[56:5] ; - assign out_sfd__h559474 = - _theResult___snd__h558736[5] ? - _theResult___sfd__h559471 : - _theResult___snd__h558736[56:5] ; - assign out_sfd__h580343 = - _theResult___snd__h579635[5] ? - _theResult___sfd__h580340 : - _theResult___snd__h579635[56:5] ; - assign out_sfd__h589994 = - sfdin__h589255[5] ? - _theResult___sfd__h589991 : - sfdin__h589255[56:5] ; - assign out_sfd__h598778 = - _theResult___snd__h598040[5] ? - _theResult___sfd__h598775 : - _theResult___snd__h598040[56:5] ; - assign pc__h711407 = - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ? - y_avValue_new_pc__h711199 : - y_avValue_new_pc__h711385 ; - assign pend_ints__h651114 = + _theResult___sfd__h472609 ; + assign out_sfd__h354716 = + sfdin__h354190[34] ? + _theResult___sfd__h354713 : + sfdin__h354190[56:34] ; + assign out_sfd__h363298 = + _theResult___snd__h362803[34] ? + _theResult___sfd__h363295 : + _theResult___snd__h362803[56:34] ; + assign out_sfd__h372482 = + sfdin__h371956[34] ? + _theResult___sfd__h372479 : + sfdin__h371956[56:34] ; + assign out_sfd__h381118 = + _theResult___snd__h380593[34] ? + _theResult___sfd__h381115 : + _theResult___snd__h380593[56:34] ; + assign out_sfd__h400413 = + sfdin__h399887[34] ? + _theResult___sfd__h400410 : + sfdin__h399887[56:34] ; + assign out_sfd__h408995 = + _theResult___snd__h408500[34] ? + _theResult___sfd__h408992 : + _theResult___snd__h408500[56:34] ; + assign out_sfd__h418179 = + sfdin__h417653[34] ? + _theResult___sfd__h418176 : + sfdin__h417653[56:34] ; + assign out_sfd__h426815 = + _theResult___snd__h426290[34] ? + _theResult___sfd__h426812 : + _theResult___snd__h426290[56:34] ; + assign out_sfd__h446108 = + sfdin__h445582[34] ? + _theResult___sfd__h446105 : + sfdin__h445582[56:34] ; + assign out_sfd__h454690 = + _theResult___snd__h454195[34] ? + _theResult___sfd__h454687 : + _theResult___snd__h454195[56:34] ; + assign out_sfd__h463874 = + sfdin__h463348[34] ? + _theResult___sfd__h463871 : + sfdin__h463348[56:34] ; + assign out_sfd__h472510 = + _theResult___snd__h471985[34] ? + _theResult___sfd__h472507 : + _theResult___snd__h471985[56:34] ; + assign out_sfd__h502187 = + _theResult___snd__h501479[5] ? + _theResult___sfd__h502184 : + _theResult___snd__h501479[56:5] ; + assign out_sfd__h511838 = + sfdin__h511099[5] ? + _theResult___sfd__h511835 : + sfdin__h511099[56:5] ; + assign out_sfd__h520622 = + _theResult___snd__h519884[5] ? + _theResult___sfd__h520619 : + _theResult___snd__h519884[56:5] ; + assign out_sfd__h541040 = + _theResult___snd__h540332[5] ? + _theResult___sfd__h541037 : + _theResult___snd__h540332[56:5] ; + assign out_sfd__h550691 = + sfdin__h549952[5] ? + _theResult___sfd__h550688 : + sfdin__h549952[56:5] ; + assign out_sfd__h559475 = + _theResult___snd__h558737[5] ? + _theResult___sfd__h559472 : + _theResult___snd__h558737[56:5] ; + assign out_sfd__h580344 = + _theResult___snd__h579636[5] ? + _theResult___sfd__h580341 : + _theResult___snd__h579636[56:5] ; + assign out_sfd__h589995 = + sfdin__h589256[5] ? + _theResult___sfd__h589992 : + sfdin__h589256[56:5] ; + assign out_sfd__h598779 = + _theResult___snd__h598041[5] ? + _theResult___sfd__h598776 : + _theResult___snd__h598041[56:5] ; + assign pc__h712387 = + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? + y_avValue_new_pc__h712179 : + y_avValue_new_pc__h712365 ; + assign pend_ints__h651116 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h727241 = old_fflags__h731983 ; - assign po_fflags__h729877 = - old_fflags__h731983 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h734164 = csrf_prv_reg ; - assign prv__h734208 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h475880 = + assign po_fflags__h728242 = old_fflags__h733017 ; + assign po_fflags__h730895 = + old_fflags__h733017 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h735199 = csrf_prv_reg ; + assign prv__h735243 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h475881 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h651663 = + assign r1__read_BITS_13_TO_0___h651665 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -30956,119 +30989,127 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h655195 = csrf_fs_reg ; - assign r1__read_BITS_62_TO_14___h728903 = { r1__read__h614243, 2'd0 } ; - assign r1__read_BIT_20___h655891 = csrf_tw_reg ; - assign r1__read__h613048 = { r1__read__h613050, csrf_ie_vec_1 } ; - assign r1__read__h613050 = { r1__read__h613052, 2'b0 } ; - assign r1__read__h613052 = { r1__read__h613054, csrf_prev_ie_vec_0 } ; - assign r1__read__h613054 = { r1__read__h613056, csrf_prev_ie_vec_1 } ; - assign r1__read__h613056 = { r1__read__h613058, 2'b0 } ; - assign r1__read__h613058 = { r1__read__h613060, csrf_spp_reg } ; - assign r1__read__h613060 = { r1__read__h613062, 4'b0 } ; - assign r1__read__h613062 = { r1__read__h613064, csrf_fs_reg } ; - assign r1__read__h613064 = { r1__read__h613066, 2'd0 } ; - assign r1__read__h613066 = { r1__read__h613068, 1'b0 } ; - assign r1__read__h613068 = { r1__read__h613070, csrf_sum_reg } ; - assign r1__read__h613070 = { r1__read__h613072, csrf_mxr_reg } ; - assign r1__read__h613072 = { r1__read__h613074, 12'b0 } ; - assign r1__read__h613074 = { r1__read__h613076, 2'b10 } ; - assign r1__read__h613076 = { csrf_fs_reg == 2'b11, 29'b0 } ; - assign r1__read__h613452 = - { r1__read__h613454, csrf_software_int_en_vec_1 } ; - assign r1__read__h613454 = { r1__read__h613456, 2'b0 } ; - assign r1__read__h613456 = { r1__read__h613458, 1'b0 } ; - assign r1__read__h613458 = { r1__read__h613460, csrf_timer_int_en_vec_1 } ; - assign r1__read__h613460 = { r1__read__h613462, 2'b0 } ; - assign r1__read__h613462 = { r1__read__h613464, 1'b0 } ; - assign r1__read__h613464 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h613962 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h613967 = { r1__read__h613969, csrf_scounteren_tm_reg } ; - assign r1__read__h613969 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h613980 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h613986 = - { r1__read__h613988, csrf_software_int_pend_vec_1 } ; - assign r1__read__h613988 = { r1__read__h613990, 2'b0 } ; - assign r1__read__h613990 = { r1__read__h613992, 1'b0 } ; - assign r1__read__h613992 = - { r1__read__h613994, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h613994 = { r1__read__h613996, 2'b0 } ; - assign r1__read__h613996 = { r1__read__h613998, 1'b0 } ; - assign r1__read__h613998 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614196 = { vm_mode_reg__read__h614202, 16'd0 } ; - assign r1__read__h614219 = { r1__read__h614221, csrf_ie_vec_1 } ; - assign r1__read__h614221 = { r1__read__h614223, 1'b0 } ; - assign r1__read__h614223 = { r1__read__h614225, csrf_ie_vec_3 } ; - assign r1__read__h614225 = { r1__read__h614227, csrf_prev_ie_vec_0 } ; - assign r1__read__h614227 = { r1__read__h614229, csrf_prev_ie_vec_1 } ; - assign r1__read__h614229 = { r1__read__h614231, 1'b0 } ; - assign r1__read__h614231 = { r1__read__h614233, csrf_prev_ie_vec_3 } ; - assign r1__read__h614233 = { r1__read__h614235, csrf_spp_reg } ; - assign r1__read__h614235 = { r1__read__h614237, 2'b0 } ; - assign r1__read__h614237 = { r1__read__h614239, csrf_mpp_reg } ; - assign r1__read__h614239 = - { r1__read_BITS_62_TO_14___h728903, csrf_fs_reg } ; - assign r1__read__h614243 = { r1__read__h614245, csrf_mprv_reg } ; - assign r1__read__h614245 = { r1__read__h614247, csrf_sum_reg } ; - assign r1__read__h614247 = { r1__read__h614249, csrf_mxr_reg } ; - assign r1__read__h614249 = { r1__read__h614251, csrf_tvm_reg } ; - assign r1__read__h614251 = { r1__read__h614253, csrf_tw_reg } ; - assign r1__read__h614253 = { r1__read__h614255, csrf_tsr_reg } ; - assign r1__read__h614255 = { r1__read__h614257, 9'b0 } ; - assign r1__read__h614257 = { r1__read__h614259, 2'b10 } ; + assign r1__read_BITS_13_TO_12___h655197 = csrf_fs_reg ; + assign r1__read_BITS_62_TO_14___h729920 = { r1__read__h614245, 2'd0 } ; + assign r1__read_BIT_20___h655893 = csrf_tw_reg ; + assign r1__read__h613050 = { r1__read__h613052, csrf_ie_vec_1 } ; + assign r1__read__h613052 = { r1__read__h613054, 2'b0 } ; + assign r1__read__h613054 = { r1__read__h613056, csrf_prev_ie_vec_0 } ; + assign r1__read__h613056 = { r1__read__h613058, csrf_prev_ie_vec_1 } ; + assign r1__read__h613058 = { r1__read__h613060, 2'b0 } ; + assign r1__read__h613060 = { r1__read__h613062, csrf_spp_reg } ; + assign r1__read__h613062 = { r1__read__h613064, 4'b0 } ; + assign r1__read__h613064 = { r1__read__h613066, csrf_fs_reg } ; + assign r1__read__h613066 = { r1__read__h613068, 2'd0 } ; + assign r1__read__h613068 = { r1__read__h613070, 1'b0 } ; + assign r1__read__h613070 = { r1__read__h613072, csrf_sum_reg } ; + assign r1__read__h613072 = { r1__read__h613074, csrf_mxr_reg } ; + assign r1__read__h613074 = { r1__read__h613076, 12'b0 } ; + assign r1__read__h613076 = { r1__read__h613078, 2'b10 } ; + assign r1__read__h613078 = { csrf_fs_reg == 2'b11, 29'b0 } ; + assign r1__read__h613454 = + { r1__read__h613456, csrf_software_int_en_vec_1 } ; + assign r1__read__h613456 = { r1__read__h613458, 2'b0 } ; + assign r1__read__h613458 = { r1__read__h613460, 1'b0 } ; + assign r1__read__h613460 = { r1__read__h613462, csrf_timer_int_en_vec_1 } ; + assign r1__read__h613462 = { r1__read__h613464, 2'b0 } ; + assign r1__read__h613464 = { r1__read__h613466, 1'b0 } ; + assign r1__read__h613466 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h613964 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h613969 = { r1__read__h613971, csrf_scounteren_tm_reg } ; + assign r1__read__h613971 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h613982 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h613988 = + { r1__read__h613990, csrf_software_int_pend_vec_1 } ; + assign r1__read__h613990 = { r1__read__h613992, 2'b0 } ; + assign r1__read__h613992 = { r1__read__h613994, 1'b0 } ; + assign r1__read__h613994 = + { r1__read__h613996, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h613996 = { r1__read__h613998, 2'b0 } ; + assign r1__read__h613998 = { r1__read__h614000, 1'b0 } ; + assign r1__read__h614000 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614198 = { vm_mode_reg__read__h614204, 16'd0 } ; + assign r1__read__h614221 = { r1__read__h614223, csrf_ie_vec_1 } ; + assign r1__read__h614223 = { r1__read__h614225, 1'b0 } ; + assign r1__read__h614225 = { r1__read__h614227, csrf_ie_vec_3 } ; + assign r1__read__h614227 = { r1__read__h614229, csrf_prev_ie_vec_0 } ; + assign r1__read__h614229 = { r1__read__h614231, csrf_prev_ie_vec_1 } ; + assign r1__read__h614231 = { r1__read__h614233, 1'b0 } ; + assign r1__read__h614233 = { r1__read__h614235, csrf_prev_ie_vec_3 } ; + assign r1__read__h614235 = { r1__read__h614237, csrf_spp_reg } ; + assign r1__read__h614237 = { r1__read__h614239, 2'b0 } ; + assign r1__read__h614239 = { r1__read__h614241, csrf_mpp_reg } ; + assign r1__read__h614241 = + { r1__read_BITS_62_TO_14___h729920, csrf_fs_reg } ; + assign r1__read__h614245 = { r1__read__h614247, csrf_mprv_reg } ; + assign r1__read__h614247 = { r1__read__h614249, csrf_sum_reg } ; + assign r1__read__h614249 = { r1__read__h614251, csrf_mxr_reg } ; + assign r1__read__h614251 = { r1__read__h614253, csrf_tvm_reg } ; + assign r1__read__h614253 = { r1__read__h614255, csrf_tw_reg } ; + assign r1__read__h614255 = { r1__read__h614257, csrf_tsr_reg } ; + assign r1__read__h614257 = { r1__read__h614259, 9'b0 } ; assign r1__read__h614259 = { r1__read__h614261, 2'b10 } ; - assign r1__read__h614261 = { csrf_fs_reg == 2'b11, 27'b0 } ; - assign r1__read__h614344 = { r1__read__h614346, 1'b0 } ; - assign r1__read__h614346 = { r1__read__h614348, csrf_medeleg_13_11_reg } ; - assign r1__read__h614348 = { r1__read__h614350, 1'b0 } ; - assign r1__read__h614350 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h614361 = { r1__read__h614363, 1'b0 } ; - assign r1__read__h614363 = { r1__read__h614365, csrf_mideleg_5_3_reg } ; - assign r1__read__h614365 = { r1__read__h614367, 1'b0 } ; - assign r1__read__h614367 = { r1__read__h614369, csrf_mideleg_9_7_reg } ; - assign r1__read__h614369 = { r1__read__h614371, 1'b0 } ; - assign r1__read__h614371 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h614385 = - { r1__read__h614387, csrf_software_int_en_vec_1 } ; - assign r1__read__h614387 = { r1__read__h614389, 1'b0 } ; - assign r1__read__h614389 = - { r1__read__h614391, csrf_software_int_en_vec_3 } ; - assign r1__read__h614391 = { r1__read__h614393, 1'b0 } ; - assign r1__read__h614393 = { r1__read__h614395, csrf_timer_int_en_vec_1 } ; - assign r1__read__h614395 = { r1__read__h614397, 1'b0 } ; - assign r1__read__h614397 = { r1__read__h614399, csrf_timer_int_en_vec_3 } ; - assign r1__read__h614399 = { r1__read__h614401, 1'b0 } ; - assign r1__read__h614401 = - { r1__read__h614403, csrf_external_int_en_vec_1 } ; - assign r1__read__h614403 = { r1__read__h614405, 1'b0 } ; - assign r1__read__h614405 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h614478 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h614483 = { r1__read__h614485, csrf_mcounteren_tm_reg } ; - assign r1__read__h614485 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h614496 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h614502 = - { r1__read__h614504, csrf_software_int_pend_vec_1 } ; - assign r1__read__h614504 = { r1__read__h614506, 1'b0 } ; - assign r1__read__h614506 = - { r1__read__h614508, csrf_software_int_pend_vec_3 } ; - assign r1__read__h614508 = { r1__read__h614510, 1'b0 } ; - assign r1__read__h614510 = - { r1__read__h614512, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h614512 = { r1__read__h614514, 1'b0 } ; - assign r1__read__h614514 = - { r1__read__h614516, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h614516 = { r1__read__h614518, 1'b0 } ; - assign r1__read__h614518 = - { r1__read__h614520, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614520 = { r1__read__h614522, 1'b0 } ; - assign r1__read__h614522 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h614599 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h481760 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h481761 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h475906 = + assign r1__read__h614261 = { r1__read__h614263, 2'b10 } ; + assign r1__read__h614263 = { csrf_fs_reg == 2'b11, 27'b0 } ; + assign r1__read__h614346 = { r1__read__h614348, 1'b0 } ; + assign r1__read__h614348 = { r1__read__h614350, csrf_medeleg_13_11_reg } ; + assign r1__read__h614350 = { r1__read__h614352, 1'b0 } ; + assign r1__read__h614352 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h614363 = { r1__read__h614365, 1'b0 } ; + assign r1__read__h614365 = { r1__read__h614367, csrf_mideleg_5_3_reg } ; + assign r1__read__h614367 = { r1__read__h614369, 1'b0 } ; + assign r1__read__h614369 = { r1__read__h614371, csrf_mideleg_9_7_reg } ; + assign r1__read__h614371 = { r1__read__h614373, 1'b0 } ; + assign r1__read__h614373 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h614387 = + { r1__read__h614389, csrf_software_int_en_vec_1 } ; + assign r1__read__h614389 = { r1__read__h614391, 1'b0 } ; + assign r1__read__h614391 = + { r1__read__h614393, csrf_software_int_en_vec_3 } ; + assign r1__read__h614393 = { r1__read__h614395, 1'b0 } ; + assign r1__read__h614395 = { r1__read__h614397, csrf_timer_int_en_vec_1 } ; + assign r1__read__h614397 = { r1__read__h614399, 1'b0 } ; + assign r1__read__h614399 = { r1__read__h614401, csrf_timer_int_en_vec_3 } ; + assign r1__read__h614401 = { r1__read__h614403, 1'b0 } ; + assign r1__read__h614403 = + { r1__read__h614405, csrf_external_int_en_vec_1 } ; + assign r1__read__h614405 = { r1__read__h614407, 1'b0 } ; + assign r1__read__h614407 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h614480 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h614485 = { r1__read__h614487, csrf_mcounteren_tm_reg } ; + assign r1__read__h614487 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h614498 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h614504 = + { r1__read__h614506, csrf_software_int_pend_vec_1 } ; + assign r1__read__h614506 = { r1__read__h614508, 1'b0 } ; + assign r1__read__h614508 = + { r1__read__h614510, csrf_software_int_pend_vec_3 } ; + assign r1__read__h614510 = { r1__read__h614512, 1'b0 } ; + assign r1__read__h614512 = + { r1__read__h614514, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h614514 = { r1__read__h614516, 1'b0 } ; + assign r1__read__h614516 = + { r1__read__h614518, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h614518 = { r1__read__h614520, 1'b0 } ; + assign r1__read__h614520 = + { r1__read__h614522, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614522 = { r1__read__h614524, 1'b0 } ; + assign r1__read__h614524 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h614601 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h481761 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h481762 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h475907 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941 = + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || @@ -31278,12 +31319,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h685237 = + assign renaming_spec_bits__h685239 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h681632 : + y_avValue_fst__h681634 : specTagManager$currentSpecBits ; - assign res_data__h337868 = { 32'hFFFFFFFF, x__h337883 } ; - assign res_data__h337873 = + assign res_data__h337869 = { 32'hFFFFFFFF, x__h337884 } ; + assign res_data__h337874 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -31296,8 +31337,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h383570 = { 32'hFFFFFFFF, x__h383585 } ; - assign res_data__h383575 = + assign res_data__h383571 = { 32'hFFFFFFFF, x__h383586 } ; + assign res_data__h383576 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -31310,8 +31351,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h429265 = { 32'hFFFFFFFF, x__h429280 } ; - assign res_data__h429270 = + assign res_data__h429266 = { 32'hFFFFFFFF, x__h429281 } ; + assign res_data__h429271 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -31324,7 +31365,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h337869 = + assign res_fflags__h337870 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -31392,7 +31433,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 } ; - assign res_fflags__h383571 = + assign res_fflags__h383572 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -31460,7 +31501,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 } ; - assign res_fflags__h429266 = + assign res_fflags__h429267 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31528,74 +31569,85 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 } ; - assign resp_addr__h291970 = + assign resp_addr__h291971 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h364336 = + assign result__h364337 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[0] | - guard__h364331 } ; - assign result__h410033 = + guard__h364332 } ; + assign result__h410034 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[0] | - guard__h410028 } ; - assign result__h455728 = + guard__h410029 } ; + assign result__h455729 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[0] | - guard__h455723 } ; - assign result__h503481 = + guard__h455724 } ; + assign result__h503482 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[0] | - guard__h503476 } ; - assign result__h542334 = + guard__h503477 } ; + assign result__h542335 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[0] | - guard__h542329 } ; - assign result__h581638 = + guard__h542330 } ; + assign result__h581639 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[0] | - guard__h581633 } ; - assign result__h646693 = w__h646688 & y__h646722 ; - assign result__h646744 = ~x__h646743 ; - assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716 = + guard__h581634 } ; + assign result__h646695 = w__h646690 & y__h646724 ; + assign result__h646746 = ~x__h646745 ; + assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15729 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h612205 = - { r1__read__h614599, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988 = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + assign rg_tdata1__read__h612207 = + { r1__read__h614601, csrf_rg_tdata1_data } ; + assign rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998 = + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983 ; - assign rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393 = + NOT_rob_deqPort_0_deq_data__4339_BITS_329_TO_3_ETC___d14993 ; + assign rob_deqPort_0_deq_data__4339_BITS_161_TO_98_43_ETC___d15292 = + { rob$deqPort_0_deq_data[161:98], + (rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[97:96] == 2'd0) ? + { 2'd0, rob$deqPort_0_deq_data[95:32] } : + ((rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[97:96] == 2'd1) ? + { 2'd1, rob$deqPort_0_deq_data[95:32] } : + { 2'd2, + (rob$deqPort_0_deq_data[329:325] == 5'd13) ? + data_warl_xformed__h722429 : + rob$deqPort_0_deq_data[95:32] }), + 5'h0A, + rob$deqPort_0_deq_data[26], + 64'hAAAAAAAAAAAAAAAA, + x_prv__h723013, + 64'hAAAAAAAAAAAAAAAA, + x__h726431, + 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 } ; - assign rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494 = + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; + assign rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505 = { rob$deqPort_0_deq_data[181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 } ; + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h655326 = + assign rs1__h655328 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h610078 = { r1__read__h614196, csrf_ppn_reg } ; + assign satp_csr__read__h610080 = { r1__read__h614198, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 && @@ -31615,175 +31667,175 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 && IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629) ; - assign sbIdx__h157150 = + assign sbIdx__h157151 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h609875 = - { r1__read__h613980, csrf_scause_code_reg } ; - assign scounteren_csr__read__h609737 = - { r1__read__h613967, csrf_scounteren_cy_reg } ; - assign sfd__h338479 = { value__h346706, 3'd0 } ; - assign sfd__h354287 = + assign scause_csr__read__h609877 = + { r1__read__h613982, csrf_scause_code_reg } ; + assign scounteren_csr__read__h609739 = + { r1__read__h613969, csrf_scounteren_cy_reg } ; + assign sfd__h338480 = { value__h346707, 3'd0 } ; + assign sfd__h354288 = { 1'b0, - _theResult___fst_exp__h354195 != 8'd0, - sfdin__h354189[56:34] } + + _theResult___fst_exp__h354196 != 8'd0, + sfdin__h354190[56:34] } + 25'd1 ; - assign sfd__h362869 = + assign sfd__h362870 = { 1'b0, - _theResult___fst_exp__h362851 != 8'd0, - _theResult___snd__h362802[56:34] } + + _theResult___fst_exp__h362852 != 8'd0, + _theResult___snd__h362803[56:34] } + 25'd1 ; - assign sfd__h372053 = + assign sfd__h372054 = { 1'b0, - _theResult___fst_exp__h371961 != 8'd0, - sfdin__h371955[56:34] } + + _theResult___fst_exp__h371962 != 8'd0, + sfdin__h371956[56:34] } + 25'd1 ; - assign sfd__h380665 = + assign sfd__h380666 = { 1'b0, - _theResult___fst_exp__h380646 != 8'd0, - _theResult___snd__h380592[56:34] } + + _theResult___fst_exp__h380647 != 8'd0, + _theResult___snd__h380593[56:34] } + 25'd1 ; - assign sfd__h384181 = { value__h392403, 3'd0 } ; - assign sfd__h399984 = + assign sfd__h384182 = { value__h392404, 3'd0 } ; + assign sfd__h399985 = { 1'b0, - _theResult___fst_exp__h399892 != 8'd0, - sfdin__h399886[56:34] } + + _theResult___fst_exp__h399893 != 8'd0, + sfdin__h399887[56:34] } + 25'd1 ; - assign sfd__h408566 = + assign sfd__h408567 = { 1'b0, - _theResult___fst_exp__h408548 != 8'd0, - _theResult___snd__h408499[56:34] } + + _theResult___fst_exp__h408549 != 8'd0, + _theResult___snd__h408500[56:34] } + 25'd1 ; - assign sfd__h417750 = + assign sfd__h417751 = { 1'b0, - _theResult___fst_exp__h417658 != 8'd0, - sfdin__h417652[56:34] } + + _theResult___fst_exp__h417659 != 8'd0, + sfdin__h417653[56:34] } + 25'd1 ; - assign sfd__h426362 = + assign sfd__h426363 = { 1'b0, - _theResult___fst_exp__h426343 != 8'd0, - _theResult___snd__h426289[56:34] } + + _theResult___fst_exp__h426344 != 8'd0, + _theResult___snd__h426290[56:34] } + 25'd1 ; - assign sfd__h429876 = { value__h438098, 3'd0 } ; - assign sfd__h445679 = + assign sfd__h429877 = { value__h438099, 3'd0 } ; + assign sfd__h445680 = { 1'b0, - _theResult___fst_exp__h445587 != 8'd0, - sfdin__h445581[56:34] } + + _theResult___fst_exp__h445588 != 8'd0, + sfdin__h445582[56:34] } + 25'd1 ; - assign sfd__h454261 = + assign sfd__h454262 = { 1'b0, - _theResult___fst_exp__h454243 != 8'd0, - _theResult___snd__h454194[56:34] } + + _theResult___fst_exp__h454244 != 8'd0, + _theResult___snd__h454195[56:34] } + 25'd1 ; - assign sfd__h463445 = + assign sfd__h463446 = { 1'b0, - _theResult___fst_exp__h463353 != 8'd0, - sfdin__h463347[56:34] } + + _theResult___fst_exp__h463354 != 8'd0, + sfdin__h463348[56:34] } + 25'd1 ; - assign sfd__h472057 = + assign sfd__h472058 = { 1'b0, - _theResult___fst_exp__h472038 != 8'd0, - _theResult___snd__h471984[56:34] } + + _theResult___fst_exp__h472039 != 8'd0, + _theResult___snd__h471985[56:34] } + 25'd1 ; - assign sfd__h482501 = { value__h487084, 32'd0 } ; - assign sfd__h501545 = + assign sfd__h482502 = { value__h487085, 32'd0 } ; + assign sfd__h501546 = { 1'b0, - _theResult___fst_exp__h501527 != 11'd0, - _theResult___snd__h501478[56:5] } + + _theResult___fst_exp__h501528 != 11'd0, + _theResult___snd__h501479[56:5] } + 54'd1 ; - assign sfd__h511196 = + assign sfd__h511197 = { 1'b0, - _theResult___fst_exp__h511104 != 11'd0, - sfdin__h511098[56:5] } + + _theResult___fst_exp__h511105 != 11'd0, + sfdin__h511099[56:5] } + 54'd1 ; - assign sfd__h519956 = + assign sfd__h519957 = { 1'b0, - _theResult___fst_exp__h519937 != 11'd0, - _theResult___snd__h519883[56:5] } + + _theResult___fst_exp__h519938 != 11'd0, + _theResult___snd__h519884[56:5] } + 54'd1 ; - assign sfd__h521495 = { value__h525937, 32'd0 } ; - assign sfd__h540398 = + assign sfd__h521496 = { value__h525938, 32'd0 } ; + assign sfd__h540399 = { 1'b0, - _theResult___fst_exp__h540380 != 11'd0, - _theResult___snd__h540331[56:5] } + + _theResult___fst_exp__h540381 != 11'd0, + _theResult___snd__h540332[56:5] } + 54'd1 ; - assign sfd__h550049 = + assign sfd__h550050 = { 1'b0, - _theResult___fst_exp__h549957 != 11'd0, - sfdin__h549951[56:5] } + + _theResult___fst_exp__h549958 != 11'd0, + sfdin__h549952[56:5] } + 54'd1 ; - assign sfd__h558809 = + assign sfd__h558810 = { 1'b0, - _theResult___fst_exp__h558790 != 11'd0, - _theResult___snd__h558736[56:5] } + + _theResult___fst_exp__h558791 != 11'd0, + _theResult___snd__h558737[56:5] } + 54'd1 ; - assign sfd__h560799 = { value__h565241, 32'd0 } ; - assign sfd__h579702 = + assign sfd__h560800 = { value__h565242, 32'd0 } ; + assign sfd__h579703 = { 1'b0, - _theResult___fst_exp__h579684 != 11'd0, - _theResult___snd__h579635[56:5] } + + _theResult___fst_exp__h579685 != 11'd0, + _theResult___snd__h579636[56:5] } + 54'd1 ; - assign sfd__h589353 = + assign sfd__h589354 = { 1'b0, - _theResult___fst_exp__h589261 != 11'd0, - sfdin__h589255[56:5] } + + _theResult___fst_exp__h589262 != 11'd0, + sfdin__h589256[56:5] } + 54'd1 ; - assign sfd__h598113 = + assign sfd__h598114 = { 1'b0, - _theResult___fst_exp__h598094 != 11'd0, - _theResult___snd__h598040[56:5] } + + _theResult___fst_exp__h598095 != 11'd0, + _theResult___snd__h598041[56:5] } + 54'd1 ; - assign sfdin__h354189 = - _theResult____h346084[56] ? - _theResult___snd__h354206 : - _theResult___snd__h354217 ; - assign sfdin__h371955 = - _theResult____h363723[56] ? - _theResult___snd__h371972 : - _theResult___snd__h371983 ; - assign sfdin__h399886 = - _theResult____h391783[56] ? - _theResult___snd__h399903 : - _theResult___snd__h399914 ; - assign sfdin__h417652 = - _theResult____h409420[56] ? - _theResult___snd__h417669 : - _theResult___snd__h417680 ; - assign sfdin__h445581 = - _theResult____h437478[56] ? - _theResult___snd__h445598 : - _theResult___snd__h445609 ; - assign sfdin__h463347 = - _theResult____h455115[56] ? - _theResult___snd__h463364 : - _theResult___snd__h463375 ; - assign sfdin__h511098 = - _theResult____h502868[56] ? - _theResult___snd__h511115 : - _theResult___snd__h511126 ; - assign sfdin__h549951 = - _theResult____h541721[56] ? - _theResult___snd__h549968 : - _theResult___snd__h549979 ; - assign sfdin__h589255 = - _theResult____h581025[56] ? - _theResult___snd__h589272 : - _theResult___snd__h589283 ; - assign shiftData__h181566 = - coreFix_memExe_regToExeQ$first[75:12] << x__h181698 ; - assign sie_csr__read__h609641 = { r1__read__h613452, 1'b0 } ; - assign sip_csr__read__h610015 = { r1__read__h613986, 1'b0 } ; - assign spec_bits__h688396 = specTagManager$currentSpecBits | y__h688409 ; - assign sstatus_csr__read__h609571 = { r1__read__h613048, csrf_ie_vec_0 } ; - assign stvec_csr__read__h609684 = - { r1__read__h613962, csrf_stvec_mode_low_reg } ; - assign trap_val__h708464 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h709502 ; - assign tsr_val__h725552 = csrf_tsr_reg ; - assign tvm_val__h725554 = csrf_tvm_reg ; + assign sfdin__h354190 = + _theResult____h346085[56] ? + _theResult___snd__h354207 : + _theResult___snd__h354218 ; + assign sfdin__h371956 = + _theResult____h363724[56] ? + _theResult___snd__h371973 : + _theResult___snd__h371984 ; + assign sfdin__h399887 = + _theResult____h391784[56] ? + _theResult___snd__h399904 : + _theResult___snd__h399915 ; + assign sfdin__h417653 = + _theResult____h409421[56] ? + _theResult___snd__h417670 : + _theResult___snd__h417681 ; + assign sfdin__h445582 = + _theResult____h437479[56] ? + _theResult___snd__h445599 : + _theResult___snd__h445610 ; + assign sfdin__h463348 = + _theResult____h455116[56] ? + _theResult___snd__h463365 : + _theResult___snd__h463376 ; + assign sfdin__h511099 = + _theResult____h502869[56] ? + _theResult___snd__h511116 : + _theResult___snd__h511127 ; + assign sfdin__h549952 = + _theResult____h541722[56] ? + _theResult___snd__h549969 : + _theResult___snd__h549980 ; + assign sfdin__h589256 = + _theResult____h581026[56] ? + _theResult___snd__h589273 : + _theResult___snd__h589284 ; + assign shiftData__h181567 = + coreFix_memExe_regToExeQ$first[75:12] << x__h181699 ; + assign sie_csr__read__h609643 = { r1__read__h613454, 1'b0 } ; + assign sip_csr__read__h610017 = { r1__read__h613988, 1'b0 } ; + assign spec_bits__h688398 = specTagManager$currentSpecBits | y__h688411 ; + assign sstatus_csr__read__h609573 = { r1__read__h613050, csrf_ie_vec_0 } ; + assign stvec_csr__read__h609686 = + { r1__read__h613964, csrf_stvec_mode_low_reg } ; + assign trap_val__h709444 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h710482 ; + assign tsr_val__h726551 = csrf_tsr_reg ; + assign tvm_val__h726553 = csrf_tvm_reg ; assign upd__h3993 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : @@ -31793,255 +31845,254 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h726048 = + assign upd__h727048 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h295940 = + assign v__h295941 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031) ? - v__h296171 : + v__h296172 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h296171 = + assign v__h296172 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h299285 = + assign v__h299286 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138) ? - v__h299803 : + v__h299804 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h299803 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h309799 = + assign v__h299804 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h309800 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309) ? - v__h310030 : + v__h310031 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h310030 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h313675 = + assign v__h310031 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h313676 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405) ? - v__h313906 : + v__h313907 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h313906 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h328276 = + assign v__h313907 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h328277 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634) ? - v__h328507 : + v__h328508 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h328507 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h331501 = + assign v__h328508 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h331502 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728) ? - v__h331732 : + v__h331733 : coreFix_memExe_forwardQ_enqP ; - assign v__h331732 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h603882 = + assign v__h331733 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h603883 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h603892 : + v__h603893 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h603892 = + assign v__h603893 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h604527 = v__h603882 - 2'd1 ; - assign v__h607933 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608839 ; - assign v__h632816 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633569 ; - assign value_BIT_23___h494224 = f1_exp__h482139 != 8'd0 ; - assign value__h346706 = + assign v__h604528 = v__h603883 - 2'd1 ; + assign v__h607935 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608841 ; + assign v__h632818 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633571 ; + assign value__h346707 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h392403 = + assign value__h392404 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h438098 = + assign value__h438099 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h487084 = { 1'b0, value_BIT_23___h494224, f1_sfd__h482140 } ; - assign value__h525937 = { 1'b0, f2_exp__h521133 != 8'd0, f2_sfd__h521134 } ; - assign value__h565241 = { 1'b0, f3_exp__h560437 != 8'd0, f3_sfd__h560438 } ; - assign vm_mode_reg__read__h614202 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h646688 = + assign value__h487085 = { 1'b0, f1_exp__h482140 != 8'd0, f1_sfd__h482141 } ; + assign value__h525938 = { 1'b0, f2_exp__h521134 != 8'd0, f2_sfd__h521135 } ; + assign value__h565242 = { 1'b0, f3_exp__h560438 != 8'd0, f3_sfd__h560439 } ; + assign vm_mode_reg__read__h614204 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h646690 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h646744 : + result__h646746 : 12'd4095 ; - assign x__h153724 = + assign x__h153725 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h153730 = + assign x__h153731 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h157271 = { 3'd0, sbIdx__h157150 } ; - assign x__h157277 = + assign x__h157272 = { 3'd0, sbIdx__h157151 } ; + assign x__h157278 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h160087 = + assign x__h160088 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h160091 = + assign x__h160092 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161939 = + assign x__h161940 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h181475 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180563 ; assign x__h181476 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181169 ; - assign x__h181698 = { x__h183901[2:0], 3'b0 } ; - assign x__h18384 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180564 ; + assign x__h181477 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181170 ; + assign x__h181699 = { x__h183902[2:0], 3'b0 } ; + assign x__h18385 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h183901 = + assign x__h183902 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ; - assign x__h193678 = + assign x__h193679 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h192915[63:32] : - curData__h192915[31:0] ; - assign x__h20922 = + curData__h192916[63:32] : + curData__h192916[31:0] ; + assign x__h20923 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h287278 = + assign x__h287279 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h287290 = + assign x__h287291 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h289144 = + assign x__h289145 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h302150 = + assign x__h302151 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h337883 = - { (_theResult___exp__h381215 != 8'd255 || - _theResult___sfd__h381216 == 23'd0) && + assign x__h337884 = + { (_theResult___exp__h381216 != 8'd255 || + _theResult___sfd__h381217 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140, - out_f_exp__h381492, - out_f_sfd__h381493 } ; - assign x__h364433 = - sfd__h338479 << (x__h364466[11] ? 12'hAAA : x__h364466) ; - assign x__h364466 = + out_f_exp__h381493, + out_f_sfd__h381494 } ; + assign x__h364434 = + sfd__h338480 << (x__h364467[11] ? 12'hAAA : x__h364467) ; + assign x__h364467 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ; - assign x__h383585 = - { (_theResult___exp__h426912 != 8'd255 || - _theResult___sfd__h426913 == 23'd0) && + assign x__h383586 = + { (_theResult___exp__h426913 != 8'd255 || + _theResult___sfd__h426914 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532, - out_f_exp__h427189, - out_f_sfd__h427190 } ; - assign x__h410130 = - sfd__h384181 << (x__h410163[11] ? 12'hAAA : x__h410163) ; - assign x__h410163 = + out_f_exp__h427190, + out_f_sfd__h427191 } ; + assign x__h410131 = + sfd__h384182 << (x__h410164[11] ? 12'hAAA : x__h410164) ; + assign x__h410164 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ; - assign x__h429280 = - { (_theResult___exp__h472607 != 8'd255 || - _theResult___sfd__h472608 == 23'd0) && + assign x__h429281 = + { (_theResult___exp__h472608 != 8'd255 || + _theResult___sfd__h472609 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924, - out_f_exp__h472884, - out_f_sfd__h472885 } ; - assign x__h455825 = - sfd__h429876 << (x__h455858[11] ? 12'hAAA : x__h455858) ; - assign x__h455858 = + out_f_exp__h472885, + out_f_sfd__h472886 } ; + assign x__h455826 = + sfd__h429877 << (x__h455859[11] ? 12'hAAA : x__h455859) ; + assign x__h455859 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ; - assign x__h46291 = + assign x__h46292 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h481669 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478805 ; assign x__h481670 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479413 ; + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478806 ; assign x__h481671 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480015 ; - assign x__h48827 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479414 ; + assign x__h481672 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480016 ; + assign x__h48828 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h503576 = sfd__h482501 << x__h503609 ; - assign x__h503609 = + assign x__h503577 = sfd__h482502 << x__h503610 ; + assign x__h503610 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; - assign x__h542429 = sfd__h521495 << x__h542462 ; - assign x__h542462 = + assign x__h542430 = sfd__h521496 << x__h542463 ; + assign x__h542463 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; - assign x__h581733 = sfd__h560799 << x__h581766 ; - assign x__h581766 = + assign x__h581734 = sfd__h560800 << x__h581767 ; + assign x__h581767 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; - assign x__h603383 = a__h602947[63] ^ b__h602948[63] ; - assign x__h613033 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h617230 = + assign x__h603384 = a__h602948[63] ^ b__h602949[63] ; + assign x__h613035 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h617232 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h609049 : - v__h607933 ; - assign x__h617231 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615055 ; - assign x__h639739 = + rVal1__h609051 : + v__h607935 ; + assign x__h617233 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615057 ; + assign x__h639741 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h633777 : - v__h632816 ; - assign x__h639740 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637574 ; - assign x__h646692 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h646743 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h701397 = + rVal1__h633779 : + v__h632818 ; + assign x__h639742 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637576 ; + assign x__h646694 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h646745 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h702377 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h711438 = { cause_code__h708463, 2'b0 } ; - assign x__h713649 = + assign x__h712418 = { cause_code__h709443, 2'b0 } ; + assign x__h714645 = { csrf_fs_reg == 2'b11, - IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909 } ; - assign x__h713841 = - { commitStage_commitTrap[36], 59'b0, cause_code__h708463 } ; - assign x__h721573 = { 1'b0, csrf_spp_reg } ; - assign x__h725432 = + IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 } ; + assign x__h714837 = + { commitStage_commitTrap[36], 59'b0, cause_code__h709443 } ; + assign x__h722556 = { 1'b0, csrf_spp_reg } ; + assign x__h726431 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32052,9 +32103,9 @@ module mkCore(CLK, csrf_mprv_reg, 2'd0, csrf_fs_reg, - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271 } ; - assign x__h728883 = - { r1__read_BITS_62_TO_14___h728903, + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15282 } ; + assign x__h729900 = + { r1__read_BITS_62_TO_14___h729920, 2'b11, csrf_mpp_reg, 2'b0, @@ -32067,54 +32118,54 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h732011 = - { y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993[63:15], + assign x__h733045 = + { y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027[63:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993[12:0] } ; - assign x__h732759 = - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ? - y_avValue_snd_snd_snd_fst__h732569 : - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 ; - assign x__h76236 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h314073 = + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027[12:0] } ; + assign x__h733794 = + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 ? + y_avValue_snd_snd_snd_fst__h733604 : + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 ; + assign x__h76237 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h314074 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h66085 = + assign x_data__h66086 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h676655 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h692709 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h655010 = csrf_frm_reg ; - assign x_prv__h711506 = - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ? + assign x_data_imm__h676657 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h692711 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h655012 = csrf_frm_reg ; + assign x_prv__h712487 = + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? 2'd1 : 2'd3 ; - assign x_prv__h722029 = + assign x_prv__h723013 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h721573 : + x__h722556 : csrf_mpp_reg ; - assign x_quotient__h475195 = + assign x_quotient__h475196 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h475880 : + q___1__h475881 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h609480 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h475196 = + assign x_reg_ifc__read__h609482 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h475197 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h475906 : + r___1__h475907 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h254802 = + assign y__h254803 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h646722 = ~x__h646692 ; - assign y__h651653 = + assign y__h646724 = ~x__h646694 ; + assign y__h651655 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -32123,66 +32174,66 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h688409 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h729714 = + assign y__h688411 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h730732 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h729737 : + y_avValue_snd_snd_snd_snd_snd_fst__h730755 : 64'd0 ; - assign y__h732518 = - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ? - y_avValue_snd_snd_snd_snd_snd_fst__h732579 : - y__h729714 ; - assign y_avValue__h180563 = + assign y__h733553 = + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 ? + y_avValue_snd_snd_snd_snd_snd_fst__h733614 : + y__h730732 ; + assign y_avValue__h180564 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 ; - assign y_avValue__h181169 = + assign y_avValue__h181170 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 ; - assign y_avValue__h478805 = + assign y_avValue__h478806 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 ; - assign y_avValue__h479413 = + assign y_avValue__h479414 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 ; - assign y_avValue__h480015 = + assign y_avValue__h480016 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 ; - assign y_avValue__h608839 = + assign y_avValue__h608841 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 ; - assign y_avValue__h615055 = + assign y_avValue__h615057 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 ; - assign y_avValue__h633569 = + assign y_avValue__h633571 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 ; - assign y_avValue__h637574 = + assign y_avValue__h637576 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ; - assign y_avValue_fst__h681569 = + assign y_avValue_fst__h681571 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h688396 : + spec_bits__h688398 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681598 = + assign y_avValue_fst__h681600 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ? - y_avValue_fst__h681569 : + y_avValue_fst__h681571 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681632 = + assign y_avValue_fst__h681634 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429) ? - y_avValue_fst__h681598 : + y_avValue_fst__h681600 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h729252 = + assign y_avValue_fst__h730270 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32196,10 +32247,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h732400 = - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 | + assign y_avValue_fst__h733435 = + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h732432 = + assign y_avValue_fst__h733467 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32211,17 +32262,17 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 : - y_avValue_fst__h732400 ; - assign y_avValue_new_pc__h711199 = + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 : + y_avValue_fst__h733435 ; + assign y_avValue_new_pc__h712179 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h711423 + { 58'd0, x__h711438 } : - base__h711423 ; - assign y_avValue_new_pc__h711385 = + base__h712403 + { 58'd0, x__h712418 } : + base__h712403 ; + assign y_avValue_new_pc__h712365 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h711443 + { 58'd0, x__h711438 } : - base__h711443 ; - assign y_avValue_snd_snd_snd_fst__h729727 = + base__h712423 + { 58'd0, x__h712418 } : + base__h712423 ; + assign y_avValue_snd_snd_snd_fst__h730745 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32235,7 +32286,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h732569 = + assign y_avValue_snd_snd_snd_fst__h733604 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32247,12 +32298,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 : - y_avValue_snd_snd_snd_fst__h732605 ; - assign y_avValue_snd_snd_snd_fst__h732605 = - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 + + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 : + y_avValue_snd_snd_snd_fst__h733640 ; + assign y_avValue_snd_snd_snd_fst__h733640 = + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h729737 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h730755 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32266,7 +32317,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h732579 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h733614 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32278,10 +32329,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h729714 : - y_avValue_snd_snd_snd_snd_snd_fst__h732615 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h732615 = y__h729714 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993 = x__h728883 ; + y__h730732 : + y_avValue_snd_snd_snd_snd_snd_fst__h733650 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h733650 = y__h730732 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027 = x__h729900 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32482,28 +32533,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -32519,28 +32570,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -32550,10 +32601,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h290066 = + addr__h290067 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h290066 = + addr__h290067 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -32562,37 +32613,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h709502 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h709502 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h709502 = + 4'd0, 4'd3: trap_val__h710482 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h710482 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h710482 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -32606,425 +32657,425 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h291615 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h291616 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h291615 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h291616 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h609350 or - frm_csr__read__h609361 or - fcsr_csr__read__h609375 or - sstatus_csr__read__h609571 or - sie_csr__read__h609641 or - stvec_csr__read__h609684 or - scounteren_csr__read__h609737 or + fflags_csr__read__h609352 or + frm_csr__read__h609363 or + fcsr_csr__read__h609377 or + sstatus_csr__read__h609573 or + sie_csr__read__h609643 or + stvec_csr__read__h609686 or + scounteren_csr__read__h609739 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609875 or + scause_csr__read__h609877 or csrf_stval_csr or - sip_csr__read__h610015 or - satp_csr__read__h610078 or - mstatus_csr__read__h610221 or - medeleg_csr__read__h610369 or - mideleg_csr__read__h610464 or - mie_csr__read__h610588 or - mtvec_csr__read__h610670 or - mcounteren_csr__read__h610762 or + sip_csr__read__h610017 or + satp_csr__read__h610080 or + mstatus_csr__read__h610223 or + medeleg_csr__read__h610371 or + mideleg_csr__read__h610466 or + mie_csr__read__h610590 or + mtvec_csr__read__h610672 or + mcounteren_csr__read__h610764 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611017 or + mcause_csr__read__h611019 or csrf_mtval_csr or - mip_csr__read__h611250 or + mip_csr__read__h611252 or csrf_rg_tselect or - rg_tdata1__read__h612205 or + rg_tdata1__read__h612207 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609480 or - n__read__h611354 or n__read__h611545 or csrf_time_reg) + x_reg_ifc__read__h609482 or + n__read__h611356 or n__read__h611547 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h736609 = fflags_csr__read__h609350; - 12'd2: data_out__h736609 = frm_csr__read__h609361; - 12'd3: data_out__h736609 = fcsr_csr__read__h609375; - 12'd256: data_out__h736609 = sstatus_csr__read__h609571; - 12'd260: data_out__h736609 = sie_csr__read__h609641; - 12'd261: data_out__h736609 = stvec_csr__read__h609684; - 12'd262: data_out__h736609 = scounteren_csr__read__h609737; - 12'd320: data_out__h736609 = csrf_sscratch_csr; - 12'd321: data_out__h736609 = csrf_sepc_csr; - 12'd322: data_out__h736609 = scause_csr__read__h609875; - 12'd323: data_out__h736609 = csrf_stval_csr; - 12'd324: data_out__h736609 = sip_csr__read__h610015; - 12'd384: data_out__h736609 = satp_csr__read__h610078; - 12'd768: data_out__h736609 = mstatus_csr__read__h610221; - 12'd769: data_out__h736609 = 64'h800000000014112D; - 12'd770: data_out__h736609 = medeleg_csr__read__h610369; - 12'd771: data_out__h736609 = mideleg_csr__read__h610464; - 12'd772: data_out__h736609 = mie_csr__read__h610588; - 12'd773: data_out__h736609 = mtvec_csr__read__h610670; - 12'd774: data_out__h736609 = mcounteren_csr__read__h610762; - 12'd832: data_out__h736609 = csrf_mscratch_csr; - 12'd833: data_out__h736609 = csrf_mepc_csr; - 12'd834: data_out__h736609 = mcause_csr__read__h611017; - 12'd835: data_out__h736609 = csrf_mtval_csr; - 12'd836: data_out__h736609 = mip_csr__read__h611250; - 12'd1952: data_out__h736609 = csrf_rg_tselect; - 12'd1953: data_out__h736609 = rg_tdata1__read__h612205; - 12'd1954: data_out__h736609 = csrf_rg_tdata2; - 12'd1955: data_out__h736609 = csrf_rg_tdata3; - 12'd1968: data_out__h736609 = csrf_rg_dcsr; - 12'd1969: data_out__h736609 = csrf_rg_dpc; - 12'd1970: data_out__h736609 = csrf_rg_dscratch0; - 12'd1971: data_out__h736609 = csrf_rg_dscratch1; + 12'd1: data_out__h737644 = fflags_csr__read__h609352; + 12'd2: data_out__h737644 = frm_csr__read__h609363; + 12'd3: data_out__h737644 = fcsr_csr__read__h609377; + 12'd256: data_out__h737644 = sstatus_csr__read__h609573; + 12'd260: data_out__h737644 = sie_csr__read__h609643; + 12'd261: data_out__h737644 = stvec_csr__read__h609686; + 12'd262: data_out__h737644 = scounteren_csr__read__h609739; + 12'd320: data_out__h737644 = csrf_sscratch_csr; + 12'd321: data_out__h737644 = csrf_sepc_csr; + 12'd322: data_out__h737644 = scause_csr__read__h609877; + 12'd323: data_out__h737644 = csrf_stval_csr; + 12'd324: data_out__h737644 = sip_csr__read__h610017; + 12'd384: data_out__h737644 = satp_csr__read__h610080; + 12'd768: data_out__h737644 = mstatus_csr__read__h610223; + 12'd769: data_out__h737644 = 64'h800000000014112D; + 12'd770: data_out__h737644 = medeleg_csr__read__h610371; + 12'd771: data_out__h737644 = mideleg_csr__read__h610466; + 12'd772: data_out__h737644 = mie_csr__read__h610590; + 12'd773: data_out__h737644 = mtvec_csr__read__h610672; + 12'd774: data_out__h737644 = mcounteren_csr__read__h610764; + 12'd832: data_out__h737644 = csrf_mscratch_csr; + 12'd833: data_out__h737644 = csrf_mepc_csr; + 12'd834: data_out__h737644 = mcause_csr__read__h611019; + 12'd835: data_out__h737644 = csrf_mtval_csr; + 12'd836: data_out__h737644 = mip_csr__read__h611252; + 12'd1952: data_out__h737644 = csrf_rg_tselect; + 12'd1953: data_out__h737644 = rg_tdata1__read__h612207; + 12'd1954: data_out__h737644 = csrf_rg_tdata2; + 12'd1955: data_out__h737644 = csrf_rg_tdata3; + 12'd1968: data_out__h737644 = csrf_rg_dcsr; + 12'd1969: data_out__h737644 = csrf_rg_dpc; + 12'd1970: data_out__h737644 = csrf_rg_dscratch0; + 12'd1971: data_out__h737644 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h736609 = 64'd0; - 12'd2049: data_out__h736609 = x_reg_ifc__read__h609480; - 12'd2816, 12'd3072: data_out__h736609 = n__read__h611354; - 12'd2818, 12'd3074: data_out__h736609 = n__read__h611545; - 12'd3073: data_out__h736609 = csrf_time_reg; - default: data_out__h736609 = 64'b0; + data_out__h737644 = 64'd0; + 12'd2049: data_out__h737644 = x_reg_ifc__read__h609482; + 12'd2816, 12'd3072: data_out__h737644 = n__read__h611356; + 12'd2818, 12'd3074: data_out__h737644 = n__read__h611547; + 12'd3073: data_out__h737644 = csrf_time_reg; + default: data_out__h737644 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h609350 or - frm_csr__read__h609361 or - fcsr_csr__read__h609375 or - sstatus_csr__read__h609571 or - sie_csr__read__h609641 or - stvec_csr__read__h609684 or - scounteren_csr__read__h609737 or + fflags_csr__read__h609352 or + frm_csr__read__h609363 or + fcsr_csr__read__h609377 or + sstatus_csr__read__h609573 or + sie_csr__read__h609643 or + stvec_csr__read__h609686 or + scounteren_csr__read__h609739 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609875 or + scause_csr__read__h609877 or csrf_stval_csr or - sip_csr__read__h610015 or - satp_csr__read__h610078 or - mstatus_csr__read__h610221 or - medeleg_csr__read__h610369 or - mideleg_csr__read__h610464 or - mie_csr__read__h610588 or - mtvec_csr__read__h610670 or - mcounteren_csr__read__h610762 or + sip_csr__read__h610017 or + satp_csr__read__h610080 or + mstatus_csr__read__h610223 or + medeleg_csr__read__h610371 or + mideleg_csr__read__h610466 or + mie_csr__read__h610590 or + mtvec_csr__read__h610672 or + mcounteren_csr__read__h610764 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611017 or + mcause_csr__read__h611019 or csrf_mtval_csr or - mip_csr__read__h611250 or + mip_csr__read__h611252 or csrf_rg_tselect or - rg_tdata1__read__h612205 or + rg_tdata1__read__h612207 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609480 or - n__read__h611354 or n__read__h611545 or csrf_time_reg) + x_reg_ifc__read__h609482 or + n__read__h611356 or n__read__h611547 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h609049 = fflags_csr__read__h609350; - 12'd2: rVal1__h609049 = frm_csr__read__h609361; - 12'd3: rVal1__h609049 = fcsr_csr__read__h609375; - 12'd256: rVal1__h609049 = sstatus_csr__read__h609571; - 12'd260: rVal1__h609049 = sie_csr__read__h609641; - 12'd261: rVal1__h609049 = stvec_csr__read__h609684; - 12'd262: rVal1__h609049 = scounteren_csr__read__h609737; - 12'd320: rVal1__h609049 = csrf_sscratch_csr; - 12'd321: rVal1__h609049 = csrf_sepc_csr; - 12'd322: rVal1__h609049 = scause_csr__read__h609875; - 12'd323: rVal1__h609049 = csrf_stval_csr; - 12'd324: rVal1__h609049 = sip_csr__read__h610015; - 12'd384: rVal1__h609049 = satp_csr__read__h610078; - 12'd768: rVal1__h609049 = mstatus_csr__read__h610221; - 12'd769: rVal1__h609049 = 64'h800000000014112D; - 12'd770: rVal1__h609049 = medeleg_csr__read__h610369; - 12'd771: rVal1__h609049 = mideleg_csr__read__h610464; - 12'd772: rVal1__h609049 = mie_csr__read__h610588; - 12'd773: rVal1__h609049 = mtvec_csr__read__h610670; - 12'd774: rVal1__h609049 = mcounteren_csr__read__h610762; - 12'd832: rVal1__h609049 = csrf_mscratch_csr; - 12'd833: rVal1__h609049 = csrf_mepc_csr; - 12'd834: rVal1__h609049 = mcause_csr__read__h611017; - 12'd835: rVal1__h609049 = csrf_mtval_csr; - 12'd836: rVal1__h609049 = mip_csr__read__h611250; - 12'd1952: rVal1__h609049 = csrf_rg_tselect; - 12'd1953: rVal1__h609049 = rg_tdata1__read__h612205; - 12'd1954: rVal1__h609049 = csrf_rg_tdata2; - 12'd1955: rVal1__h609049 = csrf_rg_tdata3; - 12'd1968: rVal1__h609049 = csrf_rg_dcsr; - 12'd1969: rVal1__h609049 = csrf_rg_dpc; - 12'd1970: rVal1__h609049 = csrf_rg_dscratch0; - 12'd1971: rVal1__h609049 = csrf_rg_dscratch1; + 12'd1: rVal1__h609051 = fflags_csr__read__h609352; + 12'd2: rVal1__h609051 = frm_csr__read__h609363; + 12'd3: rVal1__h609051 = fcsr_csr__read__h609377; + 12'd256: rVal1__h609051 = sstatus_csr__read__h609573; + 12'd260: rVal1__h609051 = sie_csr__read__h609643; + 12'd261: rVal1__h609051 = stvec_csr__read__h609686; + 12'd262: rVal1__h609051 = scounteren_csr__read__h609739; + 12'd320: rVal1__h609051 = csrf_sscratch_csr; + 12'd321: rVal1__h609051 = csrf_sepc_csr; + 12'd322: rVal1__h609051 = scause_csr__read__h609877; + 12'd323: rVal1__h609051 = csrf_stval_csr; + 12'd324: rVal1__h609051 = sip_csr__read__h610017; + 12'd384: rVal1__h609051 = satp_csr__read__h610080; + 12'd768: rVal1__h609051 = mstatus_csr__read__h610223; + 12'd769: rVal1__h609051 = 64'h800000000014112D; + 12'd770: rVal1__h609051 = medeleg_csr__read__h610371; + 12'd771: rVal1__h609051 = mideleg_csr__read__h610466; + 12'd772: rVal1__h609051 = mie_csr__read__h610590; + 12'd773: rVal1__h609051 = mtvec_csr__read__h610672; + 12'd774: rVal1__h609051 = mcounteren_csr__read__h610764; + 12'd832: rVal1__h609051 = csrf_mscratch_csr; + 12'd833: rVal1__h609051 = csrf_mepc_csr; + 12'd834: rVal1__h609051 = mcause_csr__read__h611019; + 12'd835: rVal1__h609051 = csrf_mtval_csr; + 12'd836: rVal1__h609051 = mip_csr__read__h611252; + 12'd1952: rVal1__h609051 = csrf_rg_tselect; + 12'd1953: rVal1__h609051 = rg_tdata1__read__h612207; + 12'd1954: rVal1__h609051 = csrf_rg_tdata2; + 12'd1955: rVal1__h609051 = csrf_rg_tdata3; + 12'd1968: rVal1__h609051 = csrf_rg_dcsr; + 12'd1969: rVal1__h609051 = csrf_rg_dpc; + 12'd1970: rVal1__h609051 = csrf_rg_dscratch0; + 12'd1971: rVal1__h609051 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h609049 = 64'd0; - 12'd2049: rVal1__h609049 = x_reg_ifc__read__h609480; - 12'd2816, 12'd3072: rVal1__h609049 = n__read__h611354; - 12'd2818, 12'd3074: rVal1__h609049 = n__read__h611545; - 12'd3073: rVal1__h609049 = csrf_time_reg; - default: rVal1__h609049 = 64'b0; + rVal1__h609051 = 64'd0; + 12'd2049: rVal1__h609051 = x_reg_ifc__read__h609482; + 12'd2816, 12'd3072: rVal1__h609051 = n__read__h611356; + 12'd2818, 12'd3074: rVal1__h609051 = n__read__h611547; + 12'd3073: rVal1__h609051 = csrf_time_reg; + default: rVal1__h609051 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h609350 or - frm_csr__read__h609361 or - fcsr_csr__read__h609375 or - sstatus_csr__read__h609571 or - sie_csr__read__h609641 or - stvec_csr__read__h609684 or - scounteren_csr__read__h609737 or + fflags_csr__read__h609352 or + frm_csr__read__h609363 or + fcsr_csr__read__h609377 or + sstatus_csr__read__h609573 or + sie_csr__read__h609643 or + stvec_csr__read__h609686 or + scounteren_csr__read__h609739 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609875 or + scause_csr__read__h609877 or csrf_stval_csr or - sip_csr__read__h610015 or - satp_csr__read__h610078 or - mstatus_csr__read__h610221 or - medeleg_csr__read__h610369 or - mideleg_csr__read__h610464 or - mie_csr__read__h610588 or - mtvec_csr__read__h610670 or - mcounteren_csr__read__h610762 or + sip_csr__read__h610017 or + satp_csr__read__h610080 or + mstatus_csr__read__h610223 or + medeleg_csr__read__h610371 or + mideleg_csr__read__h610466 or + mie_csr__read__h610590 or + mtvec_csr__read__h610672 or + mcounteren_csr__read__h610764 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611017 or + mcause_csr__read__h611019 or csrf_mtval_csr or - mip_csr__read__h611250 or + mip_csr__read__h611252 or csrf_rg_tselect or - rg_tdata1__read__h612205 or + rg_tdata1__read__h612207 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609480 or - n__read__h611354 or n__read__h611545 or csrf_time_reg) + x_reg_ifc__read__h609482 or + n__read__h611356 or n__read__h611547 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h633777 = fflags_csr__read__h609350; - 12'd2: rVal1__h633777 = frm_csr__read__h609361; - 12'd3: rVal1__h633777 = fcsr_csr__read__h609375; - 12'd256: rVal1__h633777 = sstatus_csr__read__h609571; - 12'd260: rVal1__h633777 = sie_csr__read__h609641; - 12'd261: rVal1__h633777 = stvec_csr__read__h609684; - 12'd262: rVal1__h633777 = scounteren_csr__read__h609737; - 12'd320: rVal1__h633777 = csrf_sscratch_csr; - 12'd321: rVal1__h633777 = csrf_sepc_csr; - 12'd322: rVal1__h633777 = scause_csr__read__h609875; - 12'd323: rVal1__h633777 = csrf_stval_csr; - 12'd324: rVal1__h633777 = sip_csr__read__h610015; - 12'd384: rVal1__h633777 = satp_csr__read__h610078; - 12'd768: rVal1__h633777 = mstatus_csr__read__h610221; - 12'd769: rVal1__h633777 = 64'h800000000014112D; - 12'd770: rVal1__h633777 = medeleg_csr__read__h610369; - 12'd771: rVal1__h633777 = mideleg_csr__read__h610464; - 12'd772: rVal1__h633777 = mie_csr__read__h610588; - 12'd773: rVal1__h633777 = mtvec_csr__read__h610670; - 12'd774: rVal1__h633777 = mcounteren_csr__read__h610762; - 12'd832: rVal1__h633777 = csrf_mscratch_csr; - 12'd833: rVal1__h633777 = csrf_mepc_csr; - 12'd834: rVal1__h633777 = mcause_csr__read__h611017; - 12'd835: rVal1__h633777 = csrf_mtval_csr; - 12'd836: rVal1__h633777 = mip_csr__read__h611250; - 12'd1952: rVal1__h633777 = csrf_rg_tselect; - 12'd1953: rVal1__h633777 = rg_tdata1__read__h612205; - 12'd1954: rVal1__h633777 = csrf_rg_tdata2; - 12'd1955: rVal1__h633777 = csrf_rg_tdata3; - 12'd1968: rVal1__h633777 = csrf_rg_dcsr; - 12'd1969: rVal1__h633777 = csrf_rg_dpc; - 12'd1970: rVal1__h633777 = csrf_rg_dscratch0; - 12'd1971: rVal1__h633777 = csrf_rg_dscratch1; + 12'd1: rVal1__h633779 = fflags_csr__read__h609352; + 12'd2: rVal1__h633779 = frm_csr__read__h609363; + 12'd3: rVal1__h633779 = fcsr_csr__read__h609377; + 12'd256: rVal1__h633779 = sstatus_csr__read__h609573; + 12'd260: rVal1__h633779 = sie_csr__read__h609643; + 12'd261: rVal1__h633779 = stvec_csr__read__h609686; + 12'd262: rVal1__h633779 = scounteren_csr__read__h609739; + 12'd320: rVal1__h633779 = csrf_sscratch_csr; + 12'd321: rVal1__h633779 = csrf_sepc_csr; + 12'd322: rVal1__h633779 = scause_csr__read__h609877; + 12'd323: rVal1__h633779 = csrf_stval_csr; + 12'd324: rVal1__h633779 = sip_csr__read__h610017; + 12'd384: rVal1__h633779 = satp_csr__read__h610080; + 12'd768: rVal1__h633779 = mstatus_csr__read__h610223; + 12'd769: rVal1__h633779 = 64'h800000000014112D; + 12'd770: rVal1__h633779 = medeleg_csr__read__h610371; + 12'd771: rVal1__h633779 = mideleg_csr__read__h610466; + 12'd772: rVal1__h633779 = mie_csr__read__h610590; + 12'd773: rVal1__h633779 = mtvec_csr__read__h610672; + 12'd774: rVal1__h633779 = mcounteren_csr__read__h610764; + 12'd832: rVal1__h633779 = csrf_mscratch_csr; + 12'd833: rVal1__h633779 = csrf_mepc_csr; + 12'd834: rVal1__h633779 = mcause_csr__read__h611019; + 12'd835: rVal1__h633779 = csrf_mtval_csr; + 12'd836: rVal1__h633779 = mip_csr__read__h611252; + 12'd1952: rVal1__h633779 = csrf_rg_tselect; + 12'd1953: rVal1__h633779 = rg_tdata1__read__h612207; + 12'd1954: rVal1__h633779 = csrf_rg_tdata2; + 12'd1955: rVal1__h633779 = csrf_rg_tdata3; + 12'd1968: rVal1__h633779 = csrf_rg_dcsr; + 12'd1969: rVal1__h633779 = csrf_rg_dpc; + 12'd1970: rVal1__h633779 = csrf_rg_dscratch0; + 12'd1971: rVal1__h633779 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h633777 = 64'd0; - 12'd2049: rVal1__h633777 = x_reg_ifc__read__h609480; - 12'd2816, 12'd3072: rVal1__h633777 = n__read__h611354; - 12'd2818, 12'd3074: rVal1__h633777 = n__read__h611545; - 12'd3073: rVal1__h633777 = csrf_time_reg; - default: rVal1__h633777 = 64'b0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd0; + rVal1__h633779 = 64'd0; + 12'd2049: rVal1__h633779 = x_reg_ifc__read__h609482; + 12'd2816, 12'd3072: rVal1__h633779 = n__read__h611356; + 12'd2818, 12'd3074: rVal1__h633779 = n__read__h611547; + 12'd3073: rVal1__h633779 = csrf_time_reg; + default: rVal1__h633779 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h346066 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h346067 = 8'd255; 3'd2: - _theResult___fst_exp__h346066 = + _theResult___fst_exp__h346067 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h346066 = + _theResult___fst_exp__h346067 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h346066 = 8'd254; - default: _theResult___fst_exp__h346066 = 8'd0; + 3'd4: _theResult___fst_exp__h346067 = 8'd254; + default: _theResult___fst_exp__h346067 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h346067 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h346068 = 23'd0; 3'd2: - _theResult___fst_sfd__h346067 = + _theResult___fst_sfd__h346068 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h346067 = + _theResult___fst_sfd__h346068 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h346067 = 23'd8388607; - default: _theResult___fst_sfd__h346067 = 23'd0; + 3'd4: _theResult___fst_sfd__h346068 = 23'd8388607; + default: _theResult___fst_sfd__h346068 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h391765 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h391766 = 8'd255; 3'd2: - _theResult___fst_exp__h391765 = + _theResult___fst_exp__h391766 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h391765 = + _theResult___fst_exp__h391766 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h391765 = 8'd254; - default: _theResult___fst_exp__h391765 = 8'd0; + 3'd4: _theResult___fst_exp__h391766 = 8'd254; + default: _theResult___fst_exp__h391766 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h391766 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h391767 = 23'd0; 3'd2: - _theResult___fst_sfd__h391766 = + _theResult___fst_sfd__h391767 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h391766 = + _theResult___fst_sfd__h391767 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h391766 = 23'd8388607; - default: _theResult___fst_sfd__h391766 = 23'd0; + 3'd4: _theResult___fst_sfd__h391767 = 23'd8388607; + default: _theResult___fst_sfd__h391767 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h437460 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h437461 = 8'd255; 3'd2: - _theResult___fst_exp__h437460 = + _theResult___fst_exp__h437461 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h437460 = + _theResult___fst_exp__h437461 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h437460 = 8'd254; - default: _theResult___fst_exp__h437460 = 8'd0; + 3'd4: _theResult___fst_exp__h437461 = 8'd254; + default: _theResult___fst_exp__h437461 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h437461 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h437462 = 23'd0; 3'd2: - _theResult___fst_sfd__h437461 = + _theResult___fst_sfd__h437462 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h437461 = + _theResult___fst_sfd__h437462 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h437461 = 23'd8388607; - default: _theResult___fst_sfd__h437461 = 23'd0; + 3'd4: _theResult___fst_sfd__h437462 = 23'd8388607; + default: _theResult___fst_sfd__h437462 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33110,16 +33161,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h708478 = commitStage_commitTrap[35:32]; - default: i__h708478 = 4'd15; + i__h709458 = commitStage_commitTrap[35:32]; + default: i__h709458 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h708638 = commitStage_commitTrap[35:32]; - default: i__h708638 = 4'd15; + i__h709618 = commitStage_commitTrap[35:32]; + default: i__h709618 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -33180,17 +33231,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[31:0]; - 1'd1: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[63:32]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:18]) 2'd0: @@ -33208,6 +33248,17 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19]) + 1'd0: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[31:0]; + 1'd1: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[63:32]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33347,446 +33398,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h354803 or - _theResult___fst_exp__h362851 or - out_exp__h363296 or _theResult___exp__h363293) + always@(guard__h354804 or + _theResult___fst_exp__h362852 or + out_exp__h363297 or _theResult___exp__h363294) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 = - _theResult___fst_exp__h362851; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 = + _theResult___fst_exp__h362852; 2'b10: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 = - out_exp__h363296; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 = + out_exp__h363297; 2'b11: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 = - _theResult___exp__h363293; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 = + _theResult___exp__h363294; endcase end - always@(guard__h354803 or - _theResult___fst_exp__h362851 or _theResult___exp__h363293) + always@(guard__h354804 or + _theResult___fst_exp__h362852 or _theResult___exp__h363294) begin - case (guard__h354803) + case (guard__h354804) 2'b0: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 = - _theResult___fst_exp__h362851; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33 = + _theResult___fst_exp__h362852; 2'b01, 2'b10, 2'b11: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 = - _theResult___exp__h363293; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33 = + _theResult___exp__h363294; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 or - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 or + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 or + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 or - _theResult___fst_exp__h362851) + _theResult___fst_exp__h362852) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h363371 = - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32; + _theResult___fst_exp__h363372 = + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32; 3'd1: - _theResult___fst_exp__h363371 = - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33; + _theResult___fst_exp__h363372 = + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33; 3'd2: - _theResult___fst_exp__h363371 = + _theResult___fst_exp__h363372 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532; 3'd3: - _theResult___fst_exp__h363371 = + _theResult___fst_exp__h363372 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534; - 3'd4: _theResult___fst_exp__h363371 = _theResult___fst_exp__h362851; - default: _theResult___fst_exp__h363371 = 8'd0; + 3'd4: _theResult___fst_exp__h363372 = _theResult___fst_exp__h362852; + default: _theResult___fst_exp__h363372 = 8'd0; endcase end - always@(guard__h346094 or - _theResult___fst_exp__h354195 or - out_exp__h354714 or _theResult___exp__h354711) + always@(guard__h346095 or + _theResult___fst_exp__h354196 or + out_exp__h354715 or _theResult___exp__h354712) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 = - _theResult___fst_exp__h354195; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 = + _theResult___fst_exp__h354196; 2'b10: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 = - out_exp__h354714; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 = + out_exp__h354715; 2'b11: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 = - _theResult___exp__h354711; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 = + _theResult___exp__h354712; endcase end - always@(guard__h346094 or - _theResult___fst_exp__h354195 or _theResult___exp__h354711) + always@(guard__h346095 or + _theResult___fst_exp__h354196 or _theResult___exp__h354712) begin - case (guard__h346094) + case (guard__h346095) 2'b0: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 = - _theResult___fst_exp__h354195; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35 = + _theResult___fst_exp__h354196; 2'b01, 2'b10, 2'b11: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 = - _theResult___exp__h354711; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35 = + _theResult___exp__h354712; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 or - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 or + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 or + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 or - _theResult___fst_exp__h354195) + _theResult___fst_exp__h354196) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h354789 = - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34; + _theResult___fst_exp__h354790 = + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34; 3'd1: - _theResult___fst_exp__h354789 = - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35; + _theResult___fst_exp__h354790 = + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35; 3'd2: - _theResult___fst_exp__h354789 = + _theResult___fst_exp__h354790 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310; 3'd3: - _theResult___fst_exp__h354789 = + _theResult___fst_exp__h354790 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313; - 3'd4: _theResult___fst_exp__h354789 = _theResult___fst_exp__h354195; - default: _theResult___fst_exp__h354789 = 8'd0; + 3'd4: _theResult___fst_exp__h354790 = _theResult___fst_exp__h354196; + default: _theResult___fst_exp__h354790 = 8'd0; endcase end - always@(guard__h363733 or - _theResult___fst_exp__h371961 or - out_exp__h372480 or _theResult___exp__h372477) + always@(guard__h363734 or + _theResult___fst_exp__h371962 or + out_exp__h372481 or _theResult___exp__h372478) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 = - _theResult___fst_exp__h371961; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 = + _theResult___fst_exp__h371962; 2'b10: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 = - out_exp__h372480; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 = + out_exp__h372481; 2'b11: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 = - _theResult___exp__h372477; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 = + _theResult___exp__h372478; endcase end - always@(guard__h363733 or - _theResult___fst_exp__h371961 or _theResult___exp__h372477) + always@(guard__h363734 or + _theResult___fst_exp__h371962 or _theResult___exp__h372478) begin - case (guard__h363733) + case (guard__h363734) 2'b0: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 = - _theResult___fst_exp__h371961; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41 = + _theResult___fst_exp__h371962; 2'b01, 2'b10, 2'b11: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 = - _theResult___exp__h372477; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41 = + _theResult___exp__h372478; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 or - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 or + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 or + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 or - _theResult___fst_exp__h371961) + _theResult___fst_exp__h371962) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h372555 = - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40; + _theResult___fst_exp__h372556 = + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40; 3'd1: - _theResult___fst_exp__h372555 = - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41; + _theResult___fst_exp__h372556 = + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41; 3'd2: - _theResult___fst_exp__h372555 = + _theResult___fst_exp__h372556 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857; 3'd3: - _theResult___fst_exp__h372555 = + _theResult___fst_exp__h372556 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859; - 3'd4: _theResult___fst_exp__h372555 = _theResult___fst_exp__h371961; - default: _theResult___fst_exp__h372555 = 8'd0; + 3'd4: _theResult___fst_exp__h372556 = _theResult___fst_exp__h371962; + default: _theResult___fst_exp__h372556 = 8'd0; endcase end - always@(guard__h372569 or - _theResult___fst_exp__h380646 or - out_exp__h381116 or _theResult___exp__h381113) + always@(guard__h372570 or + _theResult___fst_exp__h380647 or + out_exp__h381117 or _theResult___exp__h381114) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 = - _theResult___fst_exp__h380646; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 = + _theResult___fst_exp__h380647; 2'b10: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 = - out_exp__h381116; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 = + out_exp__h381117; 2'b11: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 = - _theResult___exp__h381113; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 = + _theResult___exp__h381114; endcase end - always@(guard__h372569 or - _theResult___fst_exp__h380646 or _theResult___exp__h381113) + always@(guard__h372570 or + _theResult___fst_exp__h380647 or _theResult___exp__h381114) begin - case (guard__h372569) + case (guard__h372570) 2'b0: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 = - _theResult___fst_exp__h380646; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46 = + _theResult___fst_exp__h380647; 2'b01, 2'b10, 2'b11: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 = - _theResult___exp__h381113; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46 = + _theResult___exp__h381114; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 or - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 or + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 or + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 or - _theResult___fst_exp__h380646) + _theResult___fst_exp__h380647) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h381191 = - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45; + _theResult___fst_exp__h381192 = + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45; 3'd1: - _theResult___fst_exp__h381191 = - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46; + _theResult___fst_exp__h381192 = + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46; 3'd2: - _theResult___fst_exp__h381191 = + _theResult___fst_exp__h381192 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926; 3'd3: - _theResult___fst_exp__h381191 = + _theResult___fst_exp__h381192 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928; - 3'd4: _theResult___fst_exp__h381191 = _theResult___fst_exp__h380646; - default: _theResult___fst_exp__h381191 = 8'd0; + 3'd4: _theResult___fst_exp__h381192 = _theResult___fst_exp__h380647; + default: _theResult___fst_exp__h381192 = 8'd0; endcase end - always@(guard__h354803 or - _theResult___snd__h362802 or - out_sfd__h363297 or _theResult___sfd__h363294) + always@(guard__h354804 or + _theResult___snd__h362803 or + out_sfd__h363298 or _theResult___sfd__h363295) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 = - _theResult___snd__h362802[56:34]; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 = + _theResult___snd__h362803[56:34]; 2'b10: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 = - out_sfd__h363297; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 = + out_sfd__h363298; 2'b11: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 = - _theResult___sfd__h363294; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 = + _theResult___sfd__h363295; endcase end - always@(guard__h354803 or - _theResult___snd__h362802 or _theResult___sfd__h363294) + always@(guard__h354804 or + _theResult___snd__h362803 or _theResult___sfd__h363295) begin - case (guard__h354803) + case (guard__h354804) 2'b0: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 = - _theResult___snd__h362802[56:34]; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48 = + _theResult___snd__h362803[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 = - _theResult___sfd__h363294; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48 = + _theResult___sfd__h363295; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 or - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 or + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 or + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or - _theResult___snd__h362802) + _theResult___snd__h362803) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h363372 = - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47; + _theResult___fst_sfd__h363373 = + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47; 3'd1: - _theResult___fst_sfd__h363372 = - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48; + _theResult___fst_sfd__h363373 = + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48; 3'd2: - _theResult___fst_sfd__h363372 = + _theResult___fst_sfd__h363373 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; 3'd3: - _theResult___fst_sfd__h363372 = + _theResult___fst_sfd__h363373 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978; - 3'd4: _theResult___fst_sfd__h363372 = _theResult___snd__h362802[56:34]; - default: _theResult___fst_sfd__h363372 = 23'd0; + 3'd4: _theResult___fst_sfd__h363373 = _theResult___snd__h362803[56:34]; + default: _theResult___fst_sfd__h363373 = 23'd0; endcase end - always@(guard__h346094 or - sfdin__h354189 or out_sfd__h354715 or _theResult___sfd__h354712) + always@(guard__h346095 or + sfdin__h354190 or out_sfd__h354716 or _theResult___sfd__h354713) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 = - sfdin__h354189[56:34]; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354190[56:34]; 2'b10: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 = - out_sfd__h354715; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354716; 2'b11: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 = - _theResult___sfd__h354712; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354713; endcase end - always@(guard__h346094 or sfdin__h354189 or _theResult___sfd__h354712) + always@(guard__h346095 or sfdin__h354190 or _theResult___sfd__h354713) begin - case (guard__h346094) + case (guard__h346095) 2'b0: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 = - sfdin__h354189[56:34]; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354190[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h354712; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354713; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 or - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 or + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354189) + sfdin__h354190) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h354790 = - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49; + _theResult___fst_sfd__h354791 = + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49; 3'd1: - _theResult___fst_sfd__h354790 = - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h354791 = + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50; 3'd2: - _theResult___fst_sfd__h354790 = + _theResult___fst_sfd__h354791 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; 3'd3: - _theResult___fst_sfd__h354790 = + _theResult___fst_sfd__h354791 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354790 = sfdin__h354189[56:34]; - default: _theResult___fst_sfd__h354790 = 23'd0; + 3'd4: _theResult___fst_sfd__h354791 = sfdin__h354190[56:34]; + default: _theResult___fst_sfd__h354791 = 23'd0; endcase end - always@(guard__h363733 or - sfdin__h371955 or out_sfd__h372481 or _theResult___sfd__h372478) + always@(guard__h363734 or + sfdin__h371956 or out_sfd__h372482 or _theResult___sfd__h372479) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 = - sfdin__h371955[56:34]; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 = + sfdin__h371956[56:34]; 2'b10: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 = - out_sfd__h372481; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 = + out_sfd__h372482; 2'b11: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h372478; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h372479; endcase end - always@(guard__h363733 or sfdin__h371955 or _theResult___sfd__h372478) + always@(guard__h363734 or sfdin__h371956 or _theResult___sfd__h372479) begin - case (guard__h363733) + case (guard__h363734) 2'b0: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 = - sfdin__h371955[56:34]; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52 = + sfdin__h371956[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h372478; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h372479; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 or - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 or + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 or + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 or - sfdin__h371955) + sfdin__h371956) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h372556 = - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h372557 = + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51; 3'd1: - _theResult___fst_sfd__h372556 = - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h372557 = + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52; 3'd2: - _theResult___fst_sfd__h372556 = + _theResult___fst_sfd__h372557 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003; 3'd3: - _theResult___fst_sfd__h372556 = + _theResult___fst_sfd__h372557 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005; - 3'd4: _theResult___fst_sfd__h372556 = sfdin__h371955[56:34]; - default: _theResult___fst_sfd__h372556 = 23'd0; + 3'd4: _theResult___fst_sfd__h372557 = sfdin__h371956[56:34]; + default: _theResult___fst_sfd__h372557 = 23'd0; endcase end - always@(guard__h372569 or - _theResult___snd__h380592 or - out_sfd__h381117 or _theResult___sfd__h381114) + always@(guard__h372570 or + _theResult___snd__h380593 or + out_sfd__h381118 or _theResult___sfd__h381115) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 = - _theResult___snd__h380592[56:34]; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 = + _theResult___snd__h380593[56:34]; 2'b10: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 = - out_sfd__h381117; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 = + out_sfd__h381118; 2'b11: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 = - _theResult___sfd__h381114; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 = + _theResult___sfd__h381115; endcase end - always@(guard__h372569 or - _theResult___snd__h380592 or _theResult___sfd__h381114) + always@(guard__h372570 or + _theResult___snd__h380593 or _theResult___sfd__h381115) begin - case (guard__h372569) + case (guard__h372570) 2'b0: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 = - _theResult___snd__h380592[56:34]; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54 = + _theResult___snd__h380593[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 = - _theResult___sfd__h381114; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54 = + _theResult___sfd__h381115; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 or - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 or + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 or + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___snd__h380592) + _theResult___snd__h380593) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h381192 = - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53; + _theResult___fst_sfd__h381193 = + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53; 3'd1: - _theResult___fst_sfd__h381192 = - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54; + _theResult___fst_sfd__h381193 = + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54; 3'd2: - _theResult___fst_sfd__h381192 = + _theResult___fst_sfd__h381193 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_sfd__h381192 = + _theResult___fst_sfd__h381193 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_sfd__h381192 = _theResult___snd__h380592[56:34]; - default: _theResult___fst_sfd__h381192 = 23'd0; + 3'd4: _theResult___fst_sfd__h381193 = _theResult___snd__h380593[56:34]; + default: _theResult___fst_sfd__h381193 = 23'd0; endcase end - always@(guard__h346094 or + always@(guard__h346095 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01, 2'b10: - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = - guard__h346094 == 2'b11 && + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + guard__h346095 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or - guard__h346094) + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or + guard__h346095) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - (guard__h346094 == 2'b0) ? + (guard__h346095 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h346094 == 2'b01 || guard__h346094 == 2'b10 || - guard__h346094 == 2'b11) && + (guard__h346095 == 2'b01 || guard__h346095 == 2'b10 || + guard__h346095 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = @@ -33797,34 +33848,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h346094 or + always@(guard__h346095 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01, 2'b10: - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - guard__h346094 != 2'b11 || + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + guard__h346095 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or - guard__h346094) + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or + guard__h346095) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - (guard__h346094 == 2'b0) ? + (guard__h346095 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h346094 != 2'b01 && guard__h346094 != 2'b10 && - guard__h346094 != 2'b11 || + guard__h346095 != 2'b01 && guard__h346095 != 2'b10 && + guard__h346095 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = @@ -33835,34 +33886,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354803 or + always@(guard__h354804 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01, 2'b10: - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = - guard__h354803 == 2'b11 && + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354804 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or - guard__h354803) + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354804) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354803 == 2'b0) ? + (guard__h354804 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354803 == 2'b01 || guard__h354803 == 2'b10 || - guard__h354803 == 2'b11) && + (guard__h354804 == 2'b01 || guard__h354804 == 2'b10 || + guard__h354804 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = @@ -33873,34 +33924,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354803 or + always@(guard__h354804 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01, 2'b10: - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = - guard__h354803 != 2'b11 || + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + guard__h354804 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or - guard__h354803) + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or + guard__h354804) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - (guard__h354803 == 2'b0) ? + (guard__h354804 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h354803 != 2'b01 && guard__h354803 != 2'b10 && - guard__h354803 != 2'b11 || + guard__h354804 != 2'b01 && guard__h354804 != 2'b10 && + guard__h354804 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = @@ -33911,34 +33962,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363733 or + always@(guard__h363734 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01, 2'b10: - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = - guard__h363733 == 2'b11 && + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + guard__h363734 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or - guard__h363733) + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or + guard__h363734) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - (guard__h363733 == 2'b0) ? + (guard__h363734 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h363733 == 2'b01 || guard__h363733 == 2'b10 || - guard__h363733 == 2'b11) && + (guard__h363734 == 2'b01 || guard__h363734 == 2'b10 || + guard__h363734 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = @@ -33949,34 +34000,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363733 or + always@(guard__h363734 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01, 2'b10: - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = - guard__h363733 != 2'b11 || + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + guard__h363734 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or - guard__h363733) + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or + guard__h363734) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - (guard__h363733 == 2'b0) ? + (guard__h363734 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h363733 != 2'b01 && guard__h363733 != 2'b10 && - guard__h363733 != 2'b11 || + guard__h363734 != 2'b01 && guard__h363734 != 2'b10 && + guard__h363734 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = @@ -33987,34 +34038,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372569 or + always@(guard__h372570 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01, 2'b10: - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - guard__h372569 == 2'b11 && + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + guard__h372570 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or - guard__h372569) + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or + guard__h372570) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - (guard__h372569 == 2'b0) ? + (guard__h372570 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h372569 == 2'b01 || guard__h372569 == 2'b10 || - guard__h372569 == 2'b11) && + (guard__h372570 == 2'b01 || guard__h372570 == 2'b10 || + guard__h372570 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = @@ -34025,34 +34076,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372569 or + always@(guard__h372570 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01, 2'b10: - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = - guard__h372569 != 2'b11 || + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + guard__h372570 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or - guard__h372569) + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or + guard__h372570) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - (guard__h372569 == 2'b0) ? + (guard__h372570 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h372569 != 2'b01 && guard__h372569 != 2'b10 && - guard__h372569 != 2'b11 || + guard__h372570 != 2'b01 && guard__h372570 != 2'b10 && + guard__h372570 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = @@ -34089,446 +34140,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h400500 or - _theResult___fst_exp__h408548 or - out_exp__h408993 or _theResult___exp__h408990) + always@(guard__h400501 or + _theResult___fst_exp__h408549 or + out_exp__h408994 or _theResult___exp__h408991) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 = - _theResult___fst_exp__h408548; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 = + _theResult___fst_exp__h408549; 2'b10: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 = - out_exp__h408993; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 = + out_exp__h408994; 2'b11: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 = - _theResult___exp__h408990; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 = + _theResult___exp__h408991; endcase end - always@(guard__h400500 or - _theResult___fst_exp__h408548 or _theResult___exp__h408990) + always@(guard__h400501 or + _theResult___fst_exp__h408549 or _theResult___exp__h408991) begin - case (guard__h400500) + case (guard__h400501) 2'b0: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 = - _theResult___fst_exp__h408548; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68 = + _theResult___fst_exp__h408549; 2'b01, 2'b10, 2'b11: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 = - _theResult___exp__h408990; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68 = + _theResult___exp__h408991; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 or - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 or + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 or + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 or - _theResult___fst_exp__h408548) + _theResult___fst_exp__h408549) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h409068 = - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67; + _theResult___fst_exp__h409069 = + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67; 3'd1: - _theResult___fst_exp__h409068 = - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68; + _theResult___fst_exp__h409069 = + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68; 3'd2: - _theResult___fst_exp__h409068 = + _theResult___fst_exp__h409069 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924; 3'd3: - _theResult___fst_exp__h409068 = + _theResult___fst_exp__h409069 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926; - 3'd4: _theResult___fst_exp__h409068 = _theResult___fst_exp__h408548; - default: _theResult___fst_exp__h409068 = 8'd0; + 3'd4: _theResult___fst_exp__h409069 = _theResult___fst_exp__h408549; + default: _theResult___fst_exp__h409069 = 8'd0; endcase end - always@(guard__h391793 or - _theResult___fst_exp__h399892 or - out_exp__h400411 or _theResult___exp__h400408) + always@(guard__h391794 or + _theResult___fst_exp__h399893 or + out_exp__h400412 or _theResult___exp__h400409) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 = - _theResult___fst_exp__h399892; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 = + _theResult___fst_exp__h399893; 2'b10: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 = - out_exp__h400411; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 = + out_exp__h400412; 2'b11: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 = - _theResult___exp__h400408; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 = + _theResult___exp__h400409; endcase end - always@(guard__h391793 or - _theResult___fst_exp__h399892 or _theResult___exp__h400408) + always@(guard__h391794 or + _theResult___fst_exp__h399893 or _theResult___exp__h400409) begin - case (guard__h391793) + case (guard__h391794) 2'b0: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 = - _theResult___fst_exp__h399892; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70 = + _theResult___fst_exp__h399893; 2'b01, 2'b10, 2'b11: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 = - _theResult___exp__h400408; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70 = + _theResult___exp__h400409; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 or - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 or + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 or + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 or - _theResult___fst_exp__h399892) + _theResult___fst_exp__h399893) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h400486 = - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69; + _theResult___fst_exp__h400487 = + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69; 3'd1: - _theResult___fst_exp__h400486 = - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70; + _theResult___fst_exp__h400487 = + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70; 3'd2: - _theResult___fst_exp__h400486 = + _theResult___fst_exp__h400487 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702; 3'd3: - _theResult___fst_exp__h400486 = + _theResult___fst_exp__h400487 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705; - 3'd4: _theResult___fst_exp__h400486 = _theResult___fst_exp__h399892; - default: _theResult___fst_exp__h400486 = 8'd0; + 3'd4: _theResult___fst_exp__h400487 = _theResult___fst_exp__h399893; + default: _theResult___fst_exp__h400487 = 8'd0; endcase end - always@(guard__h409430 or - _theResult___fst_exp__h417658 or - out_exp__h418177 or _theResult___exp__h418174) + always@(guard__h409431 or + _theResult___fst_exp__h417659 or + out_exp__h418178 or _theResult___exp__h418175) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 = - _theResult___fst_exp__h417658; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 = + _theResult___fst_exp__h417659; 2'b10: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 = - out_exp__h418177; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 = + out_exp__h418178; 2'b11: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 = - _theResult___exp__h418174; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 = + _theResult___exp__h418175; endcase end - always@(guard__h409430 or - _theResult___fst_exp__h417658 or _theResult___exp__h418174) + always@(guard__h409431 or + _theResult___fst_exp__h417659 or _theResult___exp__h418175) begin - case (guard__h409430) + case (guard__h409431) 2'b0: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 = - _theResult___fst_exp__h417658; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76 = + _theResult___fst_exp__h417659; 2'b01, 2'b10, 2'b11: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 = - _theResult___exp__h418174; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76 = + _theResult___exp__h418175; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 or - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 or + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 or + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 or - _theResult___fst_exp__h417658) + _theResult___fst_exp__h417659) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h418252 = - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75; + _theResult___fst_exp__h418253 = + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75; 3'd1: - _theResult___fst_exp__h418252 = - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76; + _theResult___fst_exp__h418253 = + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76; 3'd2: - _theResult___fst_exp__h418252 = + _theResult___fst_exp__h418253 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249; 3'd3: - _theResult___fst_exp__h418252 = + _theResult___fst_exp__h418253 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251; - 3'd4: _theResult___fst_exp__h418252 = _theResult___fst_exp__h417658; - default: _theResult___fst_exp__h418252 = 8'd0; + 3'd4: _theResult___fst_exp__h418253 = _theResult___fst_exp__h417659; + default: _theResult___fst_exp__h418253 = 8'd0; endcase end - always@(guard__h418266 or - _theResult___fst_exp__h426343 or - out_exp__h426813 or _theResult___exp__h426810) + always@(guard__h418267 or + _theResult___fst_exp__h426344 or + out_exp__h426814 or _theResult___exp__h426811) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 = - _theResult___fst_exp__h426343; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 = + _theResult___fst_exp__h426344; 2'b10: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 = - out_exp__h426813; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 = + out_exp__h426814; 2'b11: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 = - _theResult___exp__h426810; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 = + _theResult___exp__h426811; endcase end - always@(guard__h418266 or - _theResult___fst_exp__h426343 or _theResult___exp__h426810) + always@(guard__h418267 or + _theResult___fst_exp__h426344 or _theResult___exp__h426811) begin - case (guard__h418266) + case (guard__h418267) 2'b0: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 = - _theResult___fst_exp__h426343; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81 = + _theResult___fst_exp__h426344; 2'b01, 2'b10, 2'b11: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 = - _theResult___exp__h426810; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81 = + _theResult___exp__h426811; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 or - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 or + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 or + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 or - _theResult___fst_exp__h426343) + _theResult___fst_exp__h426344) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h426888 = - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80; + _theResult___fst_exp__h426889 = + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80; 3'd1: - _theResult___fst_exp__h426888 = - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81; + _theResult___fst_exp__h426889 = + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81; 3'd2: - _theResult___fst_exp__h426888 = + _theResult___fst_exp__h426889 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318; 3'd3: - _theResult___fst_exp__h426888 = + _theResult___fst_exp__h426889 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320; - 3'd4: _theResult___fst_exp__h426888 = _theResult___fst_exp__h426343; - default: _theResult___fst_exp__h426888 = 8'd0; + 3'd4: _theResult___fst_exp__h426889 = _theResult___fst_exp__h426344; + default: _theResult___fst_exp__h426889 = 8'd0; endcase end - always@(guard__h400500 or - _theResult___snd__h408499 or - out_sfd__h408994 or _theResult___sfd__h408991) + always@(guard__h400501 or + _theResult___snd__h408500 or + out_sfd__h408995 or _theResult___sfd__h408992) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 = - _theResult___snd__h408499[56:34]; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 = + _theResult___snd__h408500[56:34]; 2'b10: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 = - out_sfd__h408994; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 = + out_sfd__h408995; 2'b11: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 = - _theResult___sfd__h408991; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 = + _theResult___sfd__h408992; endcase end - always@(guard__h400500 or - _theResult___snd__h408499 or _theResult___sfd__h408991) + always@(guard__h400501 or + _theResult___snd__h408500 or _theResult___sfd__h408992) begin - case (guard__h400500) + case (guard__h400501) 2'b0: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 = - _theResult___snd__h408499[56:34]; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83 = + _theResult___snd__h408500[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 = - _theResult___sfd__h408991; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83 = + _theResult___sfd__h408992; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 or - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 or + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 or + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or - _theResult___snd__h408499) + _theResult___snd__h408500) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h409069 = - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82; + _theResult___fst_sfd__h409070 = + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82; 3'd1: - _theResult___fst_sfd__h409069 = - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83; + _theResult___fst_sfd__h409070 = + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83; 3'd2: - _theResult___fst_sfd__h409069 = + _theResult___fst_sfd__h409070 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; 3'd3: - _theResult___fst_sfd__h409069 = + _theResult___fst_sfd__h409070 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370; - 3'd4: _theResult___fst_sfd__h409069 = _theResult___snd__h408499[56:34]; - default: _theResult___fst_sfd__h409069 = 23'd0; + 3'd4: _theResult___fst_sfd__h409070 = _theResult___snd__h408500[56:34]; + default: _theResult___fst_sfd__h409070 = 23'd0; endcase end - always@(guard__h391793 or - sfdin__h399886 or out_sfd__h400412 or _theResult___sfd__h400409) + always@(guard__h391794 or + sfdin__h399887 or out_sfd__h400413 or _theResult___sfd__h400410) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 = - sfdin__h399886[56:34]; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399887[56:34]; 2'b10: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 = - out_sfd__h400412; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400413; 2'b11: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 = - _theResult___sfd__h400409; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400410; endcase end - always@(guard__h391793 or sfdin__h399886 or _theResult___sfd__h400409) + always@(guard__h391794 or sfdin__h399887 or _theResult___sfd__h400410) begin - case (guard__h391793) + case (guard__h391794) 2'b0: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 = - sfdin__h399886[56:34]; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399887[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 = - _theResult___sfd__h400409; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400410; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 or - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 or + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399886) + sfdin__h399887) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h400487 = - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84; + _theResult___fst_sfd__h400488 = + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84; 3'd1: - _theResult___fst_sfd__h400487 = - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85; + _theResult___fst_sfd__h400488 = + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85; 3'd2: - _theResult___fst_sfd__h400487 = + _theResult___fst_sfd__h400488 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; 3'd3: - _theResult___fst_sfd__h400487 = + _theResult___fst_sfd__h400488 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400487 = sfdin__h399886[56:34]; - default: _theResult___fst_sfd__h400487 = 23'd0; + 3'd4: _theResult___fst_sfd__h400488 = sfdin__h399887[56:34]; + default: _theResult___fst_sfd__h400488 = 23'd0; endcase end - always@(guard__h409430 or - sfdin__h417652 or out_sfd__h418178 or _theResult___sfd__h418175) + always@(guard__h409431 or + sfdin__h417653 or out_sfd__h418179 or _theResult___sfd__h418176) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 = - sfdin__h417652[56:34]; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 = + sfdin__h417653[56:34]; 2'b10: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 = - out_sfd__h418178; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 = + out_sfd__h418179; 2'b11: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h418175; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h418176; endcase end - always@(guard__h409430 or sfdin__h417652 or _theResult___sfd__h418175) + always@(guard__h409431 or sfdin__h417653 or _theResult___sfd__h418176) begin - case (guard__h409430) + case (guard__h409431) 2'b0: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 = - sfdin__h417652[56:34]; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87 = + sfdin__h417653[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h418175; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h418176; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 or - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 or + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 or + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 or - sfdin__h417652) + sfdin__h417653) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h418253 = - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h418254 = + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86; 3'd1: - _theResult___fst_sfd__h418253 = - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h418254 = + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87; 3'd2: - _theResult___fst_sfd__h418253 = + _theResult___fst_sfd__h418254 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395; 3'd3: - _theResult___fst_sfd__h418253 = + _theResult___fst_sfd__h418254 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397; - 3'd4: _theResult___fst_sfd__h418253 = sfdin__h417652[56:34]; - default: _theResult___fst_sfd__h418253 = 23'd0; + 3'd4: _theResult___fst_sfd__h418254 = sfdin__h417653[56:34]; + default: _theResult___fst_sfd__h418254 = 23'd0; endcase end - always@(guard__h418266 or - _theResult___snd__h426289 or - out_sfd__h426814 or _theResult___sfd__h426811) + always@(guard__h418267 or + _theResult___snd__h426290 or + out_sfd__h426815 or _theResult___sfd__h426812) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 = - _theResult___snd__h426289[56:34]; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 = + _theResult___snd__h426290[56:34]; 2'b10: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 = - out_sfd__h426814; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 = + out_sfd__h426815; 2'b11: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 = - _theResult___sfd__h426811; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 = + _theResult___sfd__h426812; endcase end - always@(guard__h418266 or - _theResult___snd__h426289 or _theResult___sfd__h426811) + always@(guard__h418267 or + _theResult___snd__h426290 or _theResult___sfd__h426812) begin - case (guard__h418266) + case (guard__h418267) 2'b0: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 = - _theResult___snd__h426289[56:34]; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89 = + _theResult___snd__h426290[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 = - _theResult___sfd__h426811; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89 = + _theResult___sfd__h426812; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 or - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 or + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 or + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___snd__h426289) + _theResult___snd__h426290) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h426889 = - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88; + _theResult___fst_sfd__h426890 = + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88; 3'd1: - _theResult___fst_sfd__h426889 = - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89; + _theResult___fst_sfd__h426890 = + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89; 3'd2: - _theResult___fst_sfd__h426889 = + _theResult___fst_sfd__h426890 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_sfd__h426889 = + _theResult___fst_sfd__h426890 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_sfd__h426889 = _theResult___snd__h426289[56:34]; - default: _theResult___fst_sfd__h426889 = 23'd0; + 3'd4: _theResult___fst_sfd__h426890 = _theResult___snd__h426290[56:34]; + default: _theResult___fst_sfd__h426890 = 23'd0; endcase end - always@(guard__h391793 or + always@(guard__h391794 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01, 2'b10: - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = - guard__h391793 == 2'b11 && + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + guard__h391794 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or - guard__h391793) + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or + guard__h391794) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - (guard__h391793 == 2'b0) ? + (guard__h391794 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h391793 == 2'b01 || guard__h391793 == 2'b10 || - guard__h391793 == 2'b11) && + (guard__h391794 == 2'b01 || guard__h391794 == 2'b10 || + guard__h391794 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = @@ -34539,34 +34590,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h391793 or + always@(guard__h391794 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01, 2'b10: - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = - guard__h391793 != 2'b11 || + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + guard__h391794 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or - guard__h391793) + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or + guard__h391794) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - (guard__h391793 == 2'b0) ? + (guard__h391794 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h391793 != 2'b01 && guard__h391793 != 2'b10 && - guard__h391793 != 2'b11 || + guard__h391794 != 2'b01 && guard__h391794 != 2'b10 && + guard__h391794 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = @@ -34577,34 +34628,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400500 or + always@(guard__h400501 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01, 2'b10: - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = - guard__h400500 == 2'b11 && + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + guard__h400501 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or - guard__h400500) + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or + guard__h400501) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - (guard__h400500 == 2'b0) ? + (guard__h400501 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h400500 == 2'b01 || guard__h400500 == 2'b10 || - guard__h400500 == 2'b11) && + (guard__h400501 == 2'b01 || guard__h400501 == 2'b10 || + guard__h400501 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = @@ -34615,34 +34666,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400500 or + always@(guard__h400501 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01, 2'b10: - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = - guard__h400500 != 2'b11 || + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + guard__h400501 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or - guard__h400500) + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or + guard__h400501) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - (guard__h400500 == 2'b0) ? + (guard__h400501 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h400500 != 2'b01 && guard__h400500 != 2'b10 && - guard__h400500 != 2'b11 || + guard__h400501 != 2'b01 && guard__h400501 != 2'b10 && + guard__h400501 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = @@ -34653,34 +34704,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409430 or + always@(guard__h409431 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01, 2'b10: - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = - guard__h409430 == 2'b11 && + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + guard__h409431 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or - guard__h409430) + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or + guard__h409431) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - (guard__h409430 == 2'b0) ? + (guard__h409431 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h409430 == 2'b01 || guard__h409430 == 2'b10 || - guard__h409430 == 2'b11) && + (guard__h409431 == 2'b01 || guard__h409431 == 2'b10 || + guard__h409431 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = @@ -34691,34 +34742,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409430 or + always@(guard__h409431 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01, 2'b10: - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = - guard__h409430 != 2'b11 || + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + guard__h409431 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or - guard__h409430) + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or + guard__h409431) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - (guard__h409430 == 2'b0) ? + (guard__h409431 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h409430 != 2'b01 && guard__h409430 != 2'b10 && - guard__h409430 != 2'b11 || + guard__h409431 != 2'b01 && guard__h409431 != 2'b10 && + guard__h409431 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = @@ -34729,34 +34780,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418266 or + always@(guard__h418267 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01, 2'b10: - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = - guard__h418266 == 2'b11 && + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + guard__h418267 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or - guard__h418266) + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or + guard__h418267) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - (guard__h418266 == 2'b0) ? + (guard__h418267 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h418266 == 2'b01 || guard__h418266 == 2'b10 || - guard__h418266 == 2'b11) && + (guard__h418267 == 2'b01 || guard__h418267 == 2'b10 || + guard__h418267 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = @@ -34767,34 +34818,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418266 or + always@(guard__h418267 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01, 2'b10: - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = - guard__h418266 != 2'b11 || + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418267 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or - guard__h418266) + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418267) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418266 == 2'b0) ? + (guard__h418267 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418266 != 2'b01 && guard__h418266 != 2'b10 && - guard__h418266 != 2'b11 || + guard__h418267 != 2'b01 && guard__h418267 != 2'b10 && + guard__h418267 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = @@ -34831,394 +34882,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h446195 or - _theResult___fst_exp__h454243 or - out_exp__h454688 or _theResult___exp__h454685) + always@(guard__h446196 or + _theResult___fst_exp__h454244 or + out_exp__h454689 or _theResult___exp__h454686) begin - case (guard__h446195) + case (guard__h446196) 2'b0, 2'b01: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 = - _theResult___fst_exp__h454243; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 = + _theResult___fst_exp__h454244; 2'b10: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 = - out_exp__h454688; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 = + out_exp__h454689; 2'b11: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 = - _theResult___exp__h454685; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 = + _theResult___exp__h454686; endcase end - always@(guard__h446195 or - _theResult___fst_exp__h454243 or _theResult___exp__h454685) + always@(guard__h446196 or + _theResult___fst_exp__h454244 or _theResult___exp__h454686) begin - case (guard__h446195) + case (guard__h446196) 2'b0: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 = - _theResult___fst_exp__h454243; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103 = + _theResult___fst_exp__h454244; 2'b01, 2'b10, 2'b11: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 = - _theResult___exp__h454685; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103 = + _theResult___exp__h454686; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 or - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 or + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 or + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 or - _theResult___fst_exp__h454243) + _theResult___fst_exp__h454244) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h454763 = - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102; + _theResult___fst_exp__h454764 = + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102; 3'd1: - _theResult___fst_exp__h454763 = - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103; + _theResult___fst_exp__h454764 = + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103; 3'd2: - _theResult___fst_exp__h454763 = + _theResult___fst_exp__h454764 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316; 3'd3: - _theResult___fst_exp__h454763 = + _theResult___fst_exp__h454764 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318; - 3'd4: _theResult___fst_exp__h454763 = _theResult___fst_exp__h454243; - default: _theResult___fst_exp__h454763 = 8'd0; + 3'd4: _theResult___fst_exp__h454764 = _theResult___fst_exp__h454244; + default: _theResult___fst_exp__h454764 = 8'd0; endcase end - always@(guard__h437488 or - _theResult___fst_exp__h445587 or - out_exp__h446106 or _theResult___exp__h446103) + always@(guard__h437489 or + _theResult___fst_exp__h445588 or + out_exp__h446107 or _theResult___exp__h446104) begin - case (guard__h437488) + case (guard__h437489) 2'b0, 2'b01: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 = - _theResult___fst_exp__h445587; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 = + _theResult___fst_exp__h445588; 2'b10: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 = - out_exp__h446106; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 = + out_exp__h446107; 2'b11: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 = - _theResult___exp__h446103; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 = + _theResult___exp__h446104; endcase end - always@(guard__h437488 or - _theResult___fst_exp__h445587 or _theResult___exp__h446103) + always@(guard__h437489 or + _theResult___fst_exp__h445588 or _theResult___exp__h446104) begin - case (guard__h437488) + case (guard__h437489) 2'b0: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 = - _theResult___fst_exp__h445587; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105 = + _theResult___fst_exp__h445588; 2'b01, 2'b10, 2'b11: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 = - _theResult___exp__h446103; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105 = + _theResult___exp__h446104; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 or - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 or + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 or + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 or - _theResult___fst_exp__h445587) + _theResult___fst_exp__h445588) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h446181 = - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104; + _theResult___fst_exp__h446182 = + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104; 3'd1: - _theResult___fst_exp__h446181 = - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105; + _theResult___fst_exp__h446182 = + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105; 3'd2: - _theResult___fst_exp__h446181 = + _theResult___fst_exp__h446182 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094; 3'd3: - _theResult___fst_exp__h446181 = + _theResult___fst_exp__h446182 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097; - 3'd4: _theResult___fst_exp__h446181 = _theResult___fst_exp__h445587; - default: _theResult___fst_exp__h446181 = 8'd0; + 3'd4: _theResult___fst_exp__h446182 = _theResult___fst_exp__h445588; + default: _theResult___fst_exp__h446182 = 8'd0; endcase end - always@(guard__h455125 or - _theResult___fst_exp__h463353 or - out_exp__h463872 or _theResult___exp__h463869) + always@(guard__h455126 or + _theResult___fst_exp__h463354 or + out_exp__h463873 or _theResult___exp__h463870) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 = - _theResult___fst_exp__h463353; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 = + _theResult___fst_exp__h463354; 2'b10: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 = - out_exp__h463872; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 = + out_exp__h463873; 2'b11: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 = - _theResult___exp__h463869; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 = + _theResult___exp__h463870; endcase end - always@(guard__h455125 or - _theResult___fst_exp__h463353 or _theResult___exp__h463869) + always@(guard__h455126 or + _theResult___fst_exp__h463354 or _theResult___exp__h463870) begin - case (guard__h455125) + case (guard__h455126) 2'b0: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 = - _theResult___fst_exp__h463353; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111 = + _theResult___fst_exp__h463354; 2'b01, 2'b10, 2'b11: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 = - _theResult___exp__h463869; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111 = + _theResult___exp__h463870; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 or - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 or + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 or + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 or - _theResult___fst_exp__h463353) + _theResult___fst_exp__h463354) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h463947 = - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110; + _theResult___fst_exp__h463948 = + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110; 3'd1: - _theResult___fst_exp__h463947 = - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111; + _theResult___fst_exp__h463948 = + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111; 3'd2: - _theResult___fst_exp__h463947 = + _theResult___fst_exp__h463948 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641; 3'd3: - _theResult___fst_exp__h463947 = + _theResult___fst_exp__h463948 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643; - 3'd4: _theResult___fst_exp__h463947 = _theResult___fst_exp__h463353; - default: _theResult___fst_exp__h463947 = 8'd0; + 3'd4: _theResult___fst_exp__h463948 = _theResult___fst_exp__h463354; + default: _theResult___fst_exp__h463948 = 8'd0; endcase end - always@(guard__h463961 or - _theResult___fst_exp__h472038 or - out_exp__h472508 or _theResult___exp__h472505) + always@(guard__h463962 or + _theResult___fst_exp__h472039 or + out_exp__h472509 or _theResult___exp__h472506) begin - case (guard__h463961) + case (guard__h463962) 2'b0, 2'b01: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 = - _theResult___fst_exp__h472038; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 = + _theResult___fst_exp__h472039; 2'b10: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 = - out_exp__h472508; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 = + out_exp__h472509; 2'b11: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 = - _theResult___exp__h472505; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 = + _theResult___exp__h472506; endcase end - always@(guard__h463961 or - _theResult___fst_exp__h472038 or _theResult___exp__h472505) + always@(guard__h463962 or + _theResult___fst_exp__h472039 or _theResult___exp__h472506) begin - case (guard__h463961) + case (guard__h463962) 2'b0: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 = - _theResult___fst_exp__h472038; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116 = + _theResult___fst_exp__h472039; 2'b01, 2'b10, 2'b11: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 = - _theResult___exp__h472505; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116 = + _theResult___exp__h472506; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 or - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 or + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 or + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 or - _theResult___fst_exp__h472038) + _theResult___fst_exp__h472039) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h472583 = - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115; + _theResult___fst_exp__h472584 = + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115; 3'd1: - _theResult___fst_exp__h472583 = - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116; + _theResult___fst_exp__h472584 = + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116; 3'd2: - _theResult___fst_exp__h472583 = + _theResult___fst_exp__h472584 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710; 3'd3: - _theResult___fst_exp__h472583 = + _theResult___fst_exp__h472584 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712; - 3'd4: _theResult___fst_exp__h472583 = _theResult___fst_exp__h472038; - default: _theResult___fst_exp__h472583 = 8'd0; + 3'd4: _theResult___fst_exp__h472584 = _theResult___fst_exp__h472039; + default: _theResult___fst_exp__h472584 = 8'd0; endcase end - always@(guard__h446195 or - _theResult___snd__h454194 or - out_sfd__h454689 or _theResult___sfd__h454686) + always@(guard__h446196 or + _theResult___snd__h454195 or + out_sfd__h454690 or _theResult___sfd__h454687) begin - case (guard__h446195) + case (guard__h446196) 2'b0, 2'b01: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 = - _theResult___snd__h454194[56:34]; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 = + _theResult___snd__h454195[56:34]; 2'b10: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 = - out_sfd__h454689; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 = + out_sfd__h454690; 2'b11: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 = - _theResult___sfd__h454686; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 = + _theResult___sfd__h454687; endcase end - always@(guard__h446195 or - _theResult___snd__h454194 or _theResult___sfd__h454686) + always@(guard__h446196 or + _theResult___snd__h454195 or _theResult___sfd__h454687) begin - case (guard__h446195) + case (guard__h446196) 2'b0: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 = - _theResult___snd__h454194[56:34]; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118 = + _theResult___snd__h454195[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 = - _theResult___sfd__h454686; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118 = + _theResult___sfd__h454687; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 or - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 or + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 or + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 or - _theResult___snd__h454194) + _theResult___snd__h454195) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h454764 = - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117; + _theResult___fst_sfd__h454765 = + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117; 3'd1: - _theResult___fst_sfd__h454764 = - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118; + _theResult___fst_sfd__h454765 = + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118; 3'd2: - _theResult___fst_sfd__h454764 = + _theResult___fst_sfd__h454765 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760; 3'd3: - _theResult___fst_sfd__h454764 = + _theResult___fst_sfd__h454765 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762; - 3'd4: _theResult___fst_sfd__h454764 = _theResult___snd__h454194[56:34]; - default: _theResult___fst_sfd__h454764 = 23'd0; + 3'd4: _theResult___fst_sfd__h454765 = _theResult___snd__h454195[56:34]; + default: _theResult___fst_sfd__h454765 = 23'd0; endcase end - always@(guard__h437488 or - sfdin__h445581 or out_sfd__h446107 or _theResult___sfd__h446104) + always@(guard__h437489 or + sfdin__h445582 or out_sfd__h446108 or _theResult___sfd__h446105) begin - case (guard__h437488) + case (guard__h437489) 2'b0, 2'b01: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 = - sfdin__h445581[56:34]; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 = + sfdin__h445582[56:34]; 2'b10: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 = - out_sfd__h446107; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 = + out_sfd__h446108; 2'b11: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 = - _theResult___sfd__h446104; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 = + _theResult___sfd__h446105; endcase end - always@(guard__h437488 or sfdin__h445581 or _theResult___sfd__h446104) + always@(guard__h437489 or sfdin__h445582 or _theResult___sfd__h446105) begin - case (guard__h437488) + case (guard__h437489) 2'b0: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 = - sfdin__h445581[56:34]; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120 = + sfdin__h445582[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h446104; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h446105; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 or - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 or + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 or + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 or - sfdin__h445581) + sfdin__h445582) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h446182 = - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119; + _theResult___fst_sfd__h446183 = + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119; 3'd1: - _theResult___fst_sfd__h446182 = - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h446183 = + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120; 3'd2: - _theResult___fst_sfd__h446182 = + _theResult___fst_sfd__h446183 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741; 3'd3: - _theResult___fst_sfd__h446182 = + _theResult___fst_sfd__h446183 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743; - 3'd4: _theResult___fst_sfd__h446182 = sfdin__h445581[56:34]; - default: _theResult___fst_sfd__h446182 = 23'd0; + 3'd4: _theResult___fst_sfd__h446183 = sfdin__h445582[56:34]; + default: _theResult___fst_sfd__h446183 = 23'd0; endcase end - always@(guard__h455125 or - sfdin__h463347 or out_sfd__h463873 or _theResult___sfd__h463870) + always@(guard__h455126 or + sfdin__h463348 or out_sfd__h463874 or _theResult___sfd__h463871) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 = - sfdin__h463347[56:34]; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 = + sfdin__h463348[56:34]; 2'b10: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 = - out_sfd__h463873; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 = + out_sfd__h463874; 2'b11: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h463870; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h463871; endcase end - always@(guard__h455125 or sfdin__h463347 or _theResult___sfd__h463870) + always@(guard__h455126 or sfdin__h463348 or _theResult___sfd__h463871) begin - case (guard__h455125) + case (guard__h455126) 2'b0: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 = - sfdin__h463347[56:34]; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122 = + sfdin__h463348[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h463870; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h463871; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 or - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 or + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 or + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 or - sfdin__h463347) + sfdin__h463348) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h463948 = - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h463949 = + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121; 3'd1: - _theResult___fst_sfd__h463948 = - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h463949 = + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122; 3'd2: - _theResult___fst_sfd__h463948 = + _theResult___fst_sfd__h463949 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787; 3'd3: - _theResult___fst_sfd__h463948 = + _theResult___fst_sfd__h463949 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789; - 3'd4: _theResult___fst_sfd__h463948 = sfdin__h463347[56:34]; - default: _theResult___fst_sfd__h463948 = 23'd0; + 3'd4: _theResult___fst_sfd__h463949 = sfdin__h463348[56:34]; + default: _theResult___fst_sfd__h463949 = 23'd0; endcase end - always@(guard__h437488 or + always@(guard__h463962 or + _theResult___snd__h471985 or + out_sfd__h472510 or _theResult___sfd__h472507) + begin + case (guard__h463962) + 2'b0, 2'b01: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 = + _theResult___snd__h471985[56:34]; + 2'b10: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 = + out_sfd__h472510; + 2'b11: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 = + _theResult___sfd__h472507; + endcase + end + always@(guard__h463962 or + _theResult___snd__h471985 or _theResult___sfd__h472507) + begin + case (guard__h463962) + 2'b0: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124 = + _theResult___snd__h471985[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124 = + _theResult___sfd__h472507; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 or + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or + _theResult___snd__h471985) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h472585 = + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123; + 3'd1: + _theResult___fst_sfd__h472585 = + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124; + 3'd2: + _theResult___fst_sfd__h472585 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; + 3'd3: + _theResult___fst_sfd__h472585 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; + 3'd4: _theResult___fst_sfd__h472585 = _theResult___snd__h471985[56:34]; + default: _theResult___fst_sfd__h472585 = 23'd0; + endcase + end + always@(guard__h437489 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437488) + case (guard__h437489) 2'b0, 2'b01, 2'b10: - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h437488 == 2'b11 && + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = + guard__h437489 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h437488) + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or + guard__h437489) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - (guard__h437488 == 2'b0) ? + (guard__h437489 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h437488 == 2'b01 || guard__h437488 == 2'b10 || - guard__h437488 == 2'b11) && + (guard__h437489 == 2'b01 || guard__h437489 == 2'b10 || + guard__h437489 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = @@ -35229,124 +35332,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463961 or - _theResult___snd__h471984 or - out_sfd__h472509 or _theResult___sfd__h472506) - begin - case (guard__h463961) - 2'b0, 2'b01: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 = - _theResult___snd__h471984[56:34]; - 2'b10: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 = - out_sfd__h472509; - 2'b11: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 = - _theResult___sfd__h472506; - endcase - end - always@(guard__h463961 or - _theResult___snd__h471984 or _theResult___sfd__h472506) - begin - case (guard__h463961) - 2'b0: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 = - _theResult___snd__h471984[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 = - _theResult___sfd__h472506; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 or - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___snd__h471984) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h472584 = - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124; - 3'd1: - _theResult___fst_sfd__h472584 = - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125; - 3'd2: - _theResult___fst_sfd__h472584 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; - 3'd3: - _theResult___fst_sfd__h472584 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_sfd__h472584 = _theResult___snd__h471984[56:34]; - default: _theResult___fst_sfd__h472584 = 23'd0; - endcase - end - always@(guard__h437488 or + always@(guard__h446196 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437488) + case (guard__h446196) 2'b0, 2'b01, 2'b10: - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h437488 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h437488) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - (guard__h437488 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h437488 != 2'b01 && guard__h437488 != 2'b10 && - guard__h437488 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h446195 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h446195) - 2'b0, 2'b01, 2'b10: - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = - guard__h446195 == 2'b11 && + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h446196 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or - guard__h446195) + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h446196) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - (guard__h446195 == 2'b0) ? + (guard__h446196 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h446195 == 2'b01 || guard__h446195 == 2'b10 || - guard__h446195 == 2'b11) && + (guard__h446196 == 2'b01 || guard__h446196 == 2'b10 || + guard__h446196 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = @@ -35357,34 +35370,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h446195 or + always@(guard__h437489 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h446195) + case (guard__h437489) 2'b0, 2'b01, 2'b10: - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = - guard__h446195 != 2'b11 || + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h437489 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or - guard__h446195) + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h437489) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + (guard__h437489 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h437489 != 2'b01 && guard__h437489 != 2'b10 && + guard__h437489 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h446196 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h446196) + 2'b0, 2'b01, 2'b10: + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h446196 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h446196) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - (guard__h446195 == 2'b0) ? + (guard__h446196 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h446195 != 2'b01 && guard__h446195 != 2'b10 && - guard__h446195 != 2'b11 || + guard__h446196 != 2'b01 && guard__h446196 != 2'b10 && + guard__h446196 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = @@ -35395,34 +35446,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455125 or + always@(guard__h455126 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01, 2'b10: - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = - guard__h455125 == 2'b11 && + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + guard__h455126 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or - guard__h455125) + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or + guard__h455126) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - (guard__h455125 == 2'b0) ? + (guard__h455126 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h455125 == 2'b01 || guard__h455125 == 2'b10 || - guard__h455125 == 2'b11) && + (guard__h455126 == 2'b01 || guard__h455126 == 2'b10 || + guard__h455126 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = @@ -35433,34 +35484,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455125 or + always@(guard__h455126 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01, 2'b10: - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - guard__h455125 != 2'b11 || + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + guard__h455126 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or - guard__h455125) + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or + guard__h455126) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - (guard__h455125 == 2'b0) ? + (guard__h455126 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h455125 != 2'b01 && guard__h455125 != 2'b10 && - guard__h455125 != 2'b11 || + guard__h455126 != 2'b01 && guard__h455126 != 2'b10 && + guard__h455126 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = @@ -35471,34 +35522,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463961 or + always@(guard__h463962 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463961) + case (guard__h463962) 2'b0, 2'b01, 2'b10: - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = - guard__h463961 == 2'b11 && + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + guard__h463962 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or - guard__h463961) + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or + guard__h463962) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - (guard__h463961 == 2'b0) ? + (guard__h463962 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h463961 == 2'b01 || guard__h463961 == 2'b10 || - guard__h463961 == 2'b11) && + (guard__h463962 == 2'b01 || guard__h463962 == 2'b10 || + guard__h463962 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = @@ -35509,34 +35560,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463961 or + always@(guard__h463962 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463961) + case (guard__h463962) 2'b0, 2'b01, 2'b10: - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = - guard__h463961 != 2'b11 || + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + guard__h463962 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or - guard__h463961) + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or + guard__h463962) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - (guard__h463961 == 2'b0) ? + (guard__h463962 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h463961 != 2'b01 && guard__h463961 != 2'b10 && - guard__h463961 != 2'b11 || + guard__h463962 != 2'b01 && guard__h463962 != 2'b10 && + guard__h463962 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = @@ -35593,28 +35644,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h493566 or - _theResult___fst_exp__h501527 or _theResult___exp__h502182) + always@(guard__h493567 or + _theResult___fst_exp__h501528 or _theResult___exp__h502183) begin - case (guard__h493566) + case (guard__h493567) 2'b0: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143 = - _theResult___fst_exp__h501527; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143 = + _theResult___fst_exp__h501528; 2'b01, 2'b10, 2'b11: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143 = - _theResult___exp__h502182; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143 = + _theResult___exp__h502183; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h501527 or + _theResult___fst_exp__h501528 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 or - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143) + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - _theResult___fst_exp__h501527; + _theResult___fst_exp__h501528; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015; @@ -35623,44 +35674,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = 11'd0; endcase end - always@(guard__h493566 or - _theResult___fst_exp__h501527 or - out_exp__h502185 or _theResult___exp__h502182) + always@(guard__h493567 or + _theResult___fst_exp__h501528 or + out_exp__h502186 or _theResult___exp__h502183) begin - case (guard__h493566) + case (guard__h493567) 2'b0, 2'b01: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 = - _theResult___fst_exp__h501527; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 = + _theResult___fst_exp__h501528; 2'b10: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 = - out_exp__h502185; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 = + out_exp__h502186; 2'b11: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 = - _theResult___exp__h502182; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 = + _theResult___exp__h502183; endcase end - always@(guard__h502878 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h493567 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h502878) + case (guard__h493567) 2'b0, 2'b01, 2'b10: - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h502878 == 2'b11 && + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h493567 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502878) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493567) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35670,12 +35721,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h502878 == 2'b0) ? + (guard__h493567 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h502878 == 2'b01 || guard__h502878 == 2'b10 || - guard__h502878 == 2'b11) && + (guard__h493567 == 2'b01 || guard__h493567 == 2'b10 || + guard__h493567 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35686,23 +35737,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h493566 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h511948 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h493566) + case (guard__h511948) 2'b0, 2'b01, 2'b10: - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h493566 == 2'b11 && + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h511948 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493566) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511948) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35712,12 +35763,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h493566 == 2'b0) ? + (guard__h511948 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h493566 == 2'b01 || guard__h493566 == 2'b10 || - guard__h493566 == 2'b11) && + (guard__h511948 == 2'b01 || guard__h511948 == 2'b10 || + guard__h511948 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35728,23 +35779,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h511947 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h502879 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h511947) + case (guard__h502879) 2'b0, 2'b01, 2'b10: - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h511947 == 2'b11 && + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h502879 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511947) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502879) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35754,12 +35805,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h511947 == 2'b0) ? + (guard__h502879 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h511947 == 2'b01 || guard__h511947 == 2'b10 || - guard__h511947 == 2'b11) && + (guard__h502879 == 2'b01 || guard__h502879 == 2'b10 || + guard__h502879 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35770,28 +35821,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h571723 or - _theResult___fst_exp__h579684 or _theResult___exp__h580339) + always@(guard__h571724 or + _theResult___fst_exp__h579685 or _theResult___exp__h580340) begin - case (guard__h571723) + case (guard__h571724) 2'b0: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160 = - _theResult___fst_exp__h579684; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160 = + _theResult___fst_exp__h579685; 2'b01, 2'b10, 2'b11: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160 = - _theResult___exp__h580339; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160 = + _theResult___exp__h580340; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h579684 or + _theResult___fst_exp__h579685 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 or - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160) + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - _theResult___fst_exp__h579684; + _theResult___fst_exp__h579685; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730; @@ -35800,42 +35851,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = 11'd0; endcase end - always@(guard__h571723 or - _theResult___fst_exp__h579684 or - out_exp__h580342 or _theResult___exp__h580339) + always@(guard__h571724 or + _theResult___fst_exp__h579685 or + out_exp__h580343 or _theResult___exp__h580340) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 = - _theResult___fst_exp__h579684; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 = + _theResult___fst_exp__h579685; 2'b10: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 = - out_exp__h580342; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 = + out_exp__h580343; 2'b11: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 = - _theResult___exp__h580339; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 = + _theResult___exp__h580340; endcase end - always@(guard__h571723 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571724 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01, 2'b10: - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h571723 == 2'b11 && + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571724 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571723) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571724) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35844,12 +35895,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h571723 == 2'b0) ? + (guard__h571724 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571723 == 2'b01 || guard__h571723 == 2'b10 || - guard__h571723 == 2'b11) && + (guard__h571724 == 2'b01 || guard__h571724 == 2'b10 || + guard__h571724 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35860,21 +35911,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581035 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01, 2'b10: - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h581035 == 2'b11 && + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581036 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581035) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35883,12 +35934,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h581035 == 2'b0) ? + (guard__h581036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581035 == 2'b01 || guard__h581035 == 2'b10 || - guard__h581035 == 2'b11) && + (guard__h581036 == 2'b01 || guard__h581036 == 2'b10 || + guard__h581036 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35899,21 +35950,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590104 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590105 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01, 2'b10: - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h590104 == 2'b11 && + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h590105 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590104) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590105) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35922,12 +35973,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h590104 == 2'b0) ? + (guard__h590105 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h590104 == 2'b01 || guard__h590104 == 2'b10 || - guard__h590104 == 2'b11) && + (guard__h590105 == 2'b01 || guard__h590105 == 2'b10 || + guard__h590105 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35938,21 +35989,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581035 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01, 2'b10: - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h581035 != 2'b11 || + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h581036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581035) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35961,12 +36012,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h581035 == 2'b0) ? + (guard__h581036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h581035 != 2'b01 && guard__h581035 != 2'b10 && - guard__h581035 != 2'b11 || + guard__h581036 != 2'b01 && guard__h581036 != 2'b10 && + guard__h581036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35977,21 +36028,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590104 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590105 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01, 2'b10: - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h590104 != 2'b11 || + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h590105 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590104) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590105) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36000,12 +36051,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h590104 == 2'b0) ? + (guard__h590105 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h590104 != 2'b01 && guard__h590104 != 2'b10 && - guard__h590104 != 2'b11 || + guard__h590105 != 2'b01 && guard__h590105 != 2'b10 && + guard__h590105 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36016,21 +36067,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571723 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571724 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01, 2'b10: - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h571723 != 2'b11 || + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h571724 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571723) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571724) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36039,12 +36090,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h571723 == 2'b0) ? + (guard__h571724 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h571723 != 2'b01 && guard__h571723 != 2'b10 && - guard__h571723 != 2'b11 || + guard__h571724 != 2'b01 && guard__h571724 != 2'b10 && + guard__h571724 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36055,28 +36106,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h532419 or - _theResult___fst_exp__h540380 or _theResult___exp__h541035) + always@(guard__h532420 or + _theResult___fst_exp__h540381 or _theResult___exp__h541036) begin - case (guard__h532419) + case (guard__h532420) 2'b0: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183 = - _theResult___fst_exp__h540380; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183 = + _theResult___fst_exp__h540381; 2'b01, 2'b10, 2'b11: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183 = - _theResult___exp__h541035; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183 = + _theResult___exp__h541036; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h540380 or + _theResult___fst_exp__h540381 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 or - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183) + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - _theResult___fst_exp__h540380; + _theResult___fst_exp__h540381; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500; @@ -36085,49 +36136,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = 11'd0; endcase end - always@(guard__h532419 or - _theResult___fst_exp__h540380 or - out_exp__h541038 or _theResult___exp__h541035) + always@(guard__h532420 or + _theResult___fst_exp__h540381 or + out_exp__h541039 or _theResult___exp__h541036) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 = - _theResult___fst_exp__h540380; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 = + _theResult___fst_exp__h540381; 2'b10: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 = - out_exp__h541038; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 = + out_exp__h541039; 2'b11: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 = - _theResult___exp__h541035; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 = + _theResult___exp__h541036; endcase end - always@(guard__h541731 or - _theResult___fst_exp__h549957 or _theResult___exp__h550686) + always@(guard__h541732 or + _theResult___fst_exp__h549958 or _theResult___exp__h550687) begin - case (guard__h541731) + case (guard__h541732) 2'b0: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185 = - _theResult___fst_exp__h549957; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185 = + _theResult___fst_exp__h549958; 2'b01, 2'b10, 2'b11: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185 = - _theResult___exp__h550686; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185 = + _theResult___exp__h550687; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h549957 or + _theResult___fst_exp__h549958 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 or - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185) + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - _theResult___fst_exp__h549957; + _theResult___fst_exp__h549958; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538; @@ -36136,49 +36187,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = 11'd0; endcase end - always@(guard__h541731 or - _theResult___fst_exp__h549957 or - out_exp__h550689 or _theResult___exp__h550686) + always@(guard__h541732 or + _theResult___fst_exp__h549958 or + out_exp__h550690 or _theResult___exp__h550687) begin - case (guard__h541731) + case (guard__h541732) 2'b0, 2'b01: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 = - _theResult___fst_exp__h549957; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 = + _theResult___fst_exp__h549958; 2'b10: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 = - out_exp__h550689; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 = + out_exp__h550690; 2'b11: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 = - _theResult___exp__h550686; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 = + _theResult___exp__h550687; endcase end - always@(guard__h550800 or - _theResult___fst_exp__h558790 or _theResult___exp__h559470) + always@(guard__h550801 or + _theResult___fst_exp__h558791 or _theResult___exp__h559471) begin - case (guard__h550800) + case (guard__h550801) 2'b0: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187 = - _theResult___fst_exp__h558790; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187 = + _theResult___fst_exp__h558791; 2'b01, 2'b10, 2'b11: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187 = - _theResult___exp__h559470; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187 = + _theResult___exp__h559471; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h558790 or + _theResult___fst_exp__h558791 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187) + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - _theResult___fst_exp__h558790; + _theResult___fst_exp__h558791; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569; @@ -36187,49 +36238,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = 11'd0; endcase end - always@(guard__h550800 or - _theResult___fst_exp__h558790 or - out_exp__h559473 or _theResult___exp__h559470) + always@(guard__h550801 or + _theResult___fst_exp__h558791 or + out_exp__h559474 or _theResult___exp__h559471) begin - case (guard__h550800) + case (guard__h550801) 2'b0, 2'b01: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 = - _theResult___fst_exp__h558790; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 = + _theResult___fst_exp__h558791; 2'b10: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 = - out_exp__h559473; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 = + out_exp__h559474; 2'b11: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 = - _theResult___exp__h559470; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 = + _theResult___exp__h559471; endcase end - always@(guard__h581035 or - _theResult___fst_exp__h589261 or _theResult___exp__h589990) + always@(guard__h581036 or + _theResult___fst_exp__h589262 or _theResult___exp__h589991) begin - case (guard__h581035) + case (guard__h581036) 2'b0: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189 = - _theResult___fst_exp__h589261; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189 = + _theResult___fst_exp__h589262; 2'b01, 2'b10, 2'b11: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189 = - _theResult___exp__h589990; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189 = + _theResult___exp__h589991; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h589261 or + _theResult___fst_exp__h589262 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189) + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - _theResult___fst_exp__h589261; + _theResult___fst_exp__h589262; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; @@ -36238,49 +36289,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = 11'd0; endcase end - always@(guard__h581035 or - _theResult___fst_exp__h589261 or - out_exp__h589993 or _theResult___exp__h589990) + always@(guard__h581036 or + _theResult___fst_exp__h589262 or + out_exp__h589994 or _theResult___exp__h589991) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 = - _theResult___fst_exp__h589261; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 = + _theResult___fst_exp__h589262; 2'b10: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 = - out_exp__h589993; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 = + out_exp__h589994; 2'b11: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 = - _theResult___exp__h589990; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 = + _theResult___exp__h589991; endcase end - always@(guard__h590104 or - _theResult___fst_exp__h598094 or _theResult___exp__h598774) + always@(guard__h590105 or + _theResult___fst_exp__h598095 or _theResult___exp__h598775) begin - case (guard__h590104) + case (guard__h590105) 2'b0: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191 = - _theResult___fst_exp__h598094; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191 = + _theResult___fst_exp__h598095; 2'b01, 2'b10, 2'b11: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191 = - _theResult___exp__h598774; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191 = + _theResult___exp__h598775; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h598094 or + _theResult___fst_exp__h598095 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191) + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - _theResult___fst_exp__h598094; + _theResult___fst_exp__h598095; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799; @@ -36289,44 +36340,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase end - always@(guard__h590104 or - _theResult___fst_exp__h598094 or - out_exp__h598777 or _theResult___exp__h598774) + always@(guard__h590105 or + _theResult___fst_exp__h598095 or + out_exp__h598778 or _theResult___exp__h598775) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 = - _theResult___fst_exp__h598094; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 = + _theResult___fst_exp__h598095; 2'b10: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 = - out_exp__h598777; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 = + out_exp__h598778; 2'b11: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 = - _theResult___exp__h598774; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 = + _theResult___exp__h598775; endcase end - always@(guard__h532419 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532420 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01, 2'b10: - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h532419 == 2'b11 && + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h532420 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532419) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532420) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36336,12 +36387,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h532419 == 2'b0) ? + (guard__h532420 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532419 == 2'b01 || guard__h532419 == 2'b10 || - guard__h532419 == 2'b11) && + (guard__h532420 == 2'b01 || guard__h532420 == 2'b10 || + guard__h532420 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36352,23 +36403,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550800 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541732 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550800) + case (guard__h541732) 2'b0, 2'b01, 2'b10: - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h550800 == 2'b11 && + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h541732 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550800) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541732) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36378,12 +36429,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h550800 == 2'b0) ? + (guard__h541732 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h550800 == 2'b01 || guard__h550800 == 2'b10 || - guard__h550800 == 2'b11) && + (guard__h541732 == 2'b01 || guard__h541732 == 2'b10 || + guard__h541732 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36394,23 +36445,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541731 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550801 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541731) + case (guard__h550801) 2'b0, 2'b01, 2'b10: - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h541731 == 2'b11 && + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h550801 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541731) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550801) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36420,12 +36471,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h541731 == 2'b0) ? + (guard__h550801 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h541731 == 2'b01 || guard__h541731 == 2'b10 || - guard__h541731 == 2'b11) && + (guard__h550801 == 2'b01 || guard__h550801 == 2'b10 || + guard__h550801 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36436,23 +36487,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541731 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541732 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541731) + case (guard__h541732) 2'b0, 2'b01, 2'b10: - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h541731 != 2'b11 || + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h541732 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541731) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541732) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36462,12 +36513,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h541731 == 2'b0) ? + (guard__h541732 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h541731 != 2'b01 && guard__h541731 != 2'b10 && - guard__h541731 != 2'b11 || + guard__h541732 != 2'b01 && guard__h541732 != 2'b10 && + guard__h541732 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36478,23 +36529,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550800 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550801 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550800) + case (guard__h550801) 2'b0, 2'b01, 2'b10: - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h550800 != 2'b11 || + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h550801 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550800) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550801) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36504,12 +36555,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h550800 == 2'b0) ? + (guard__h550801 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h550800 != 2'b01 && guard__h550800 != 2'b10 && - guard__h550800 != 2'b11 || + guard__h550801 != 2'b01 && guard__h550801 != 2'b10 && + guard__h550801 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36520,23 +36571,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532419 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532420 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01, 2'b10: - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h532419 != 2'b11 || + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532420 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532419) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532420) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36546,12 +36597,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h532419 == 2'b0) ? + (guard__h532420 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532419 != 2'b01 && guard__h532419 != 2'b10 && - guard__h532419 != 2'b11 || + guard__h532420 != 2'b01 && guard__h532420 != 2'b10 && + guard__h532420 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36562,28 +36613,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532419 or - _theResult___snd__h540331 or _theResult___sfd__h541036) + always@(guard__h532420 or + _theResult___snd__h540332 or _theResult___sfd__h541037) begin - case (guard__h532419) + case (guard__h532420) 2'b0: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205 = - _theResult___snd__h540331[56:5]; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205 = + _theResult___snd__h540332[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205 = - _theResult___sfd__h541036; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205 = + _theResult___sfd__h541037; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h540331 or + _theResult___snd__h540332 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 or - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205) + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - _theResult___snd__h540331[56:5]; + _theResult___snd__h540332[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595; @@ -36592,48 +36643,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = 52'd0; endcase end - always@(guard__h532419 or - _theResult___snd__h540331 or - out_sfd__h541039 or _theResult___sfd__h541036) + always@(guard__h532420 or + _theResult___snd__h540332 or + out_sfd__h541040 or _theResult___sfd__h541037) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 = - _theResult___snd__h540331[56:5]; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 = + _theResult___snd__h540332[56:5]; 2'b10: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 = - out_sfd__h541039; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 = + out_sfd__h541040; 2'b11: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 = - _theResult___sfd__h541036; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 = + _theResult___sfd__h541037; endcase end - always@(guard__h541731 or sfdin__h549951 or _theResult___sfd__h550687) + always@(guard__h541732 or sfdin__h549952 or _theResult___sfd__h550688) begin - case (guard__h541731) + case (guard__h541732) 2'b0: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h549951[56:5]; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h549952[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h550687; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h550688; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h549951 or + sfdin__h549952 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207) + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - sfdin__h549951[56:5]; + sfdin__h549952[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621; @@ -36642,48 +36693,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase end - always@(guard__h541731 or - sfdin__h549951 or out_sfd__h550690 or _theResult___sfd__h550687) + always@(guard__h541732 or + sfdin__h549952 or out_sfd__h550691 or _theResult___sfd__h550688) begin - case (guard__h541731) + case (guard__h541732) 2'b0, 2'b01: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h549951[56:5]; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h549952[56:5]; 2'b10: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h550690; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h550691; 2'b11: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h550687; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h550688; endcase end - always@(guard__h550800 or - _theResult___snd__h558736 or _theResult___sfd__h559471) + always@(guard__h550801 or + _theResult___snd__h558737 or _theResult___sfd__h559472) begin - case (guard__h550800) + case (guard__h550801) 2'b0: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209 = - _theResult___snd__h558736[56:5]; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209 = + _theResult___snd__h558737[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209 = - _theResult___sfd__h559471; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209 = + _theResult___sfd__h559472; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558736 or + _theResult___snd__h558737 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209) + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558736[56:5]; + _theResult___snd__h558737[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; @@ -36692,49 +36743,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = 52'd0; endcase end - always@(guard__h550800 or - _theResult___snd__h558736 or - out_sfd__h559474 or _theResult___sfd__h559471) + always@(guard__h550801 or + _theResult___snd__h558737 or + out_sfd__h559475 or _theResult___sfd__h559472) begin - case (guard__h550800) + case (guard__h550801) 2'b0, 2'b01: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 = - _theResult___snd__h558736[56:5]; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 = + _theResult___snd__h558737[56:5]; 2'b10: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 = - out_sfd__h559474; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 = + out_sfd__h559475; 2'b11: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 = - _theResult___sfd__h559471; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 = + _theResult___sfd__h559472; endcase end - always@(guard__h502878 or - _theResult___fst_exp__h511104 or _theResult___exp__h511833) + always@(guard__h502879 or + _theResult___fst_exp__h511105 or _theResult___exp__h511834) begin - case (guard__h502878) + case (guard__h502879) 2'b0: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211 = - _theResult___fst_exp__h511104; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211 = + _theResult___fst_exp__h511105; 2'b01, 2'b10, 2'b11: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211 = - _theResult___exp__h511833; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211 = + _theResult___exp__h511834; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h511104 or + _theResult___fst_exp__h511105 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 or - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211) + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - _theResult___fst_exp__h511104; + _theResult___fst_exp__h511105; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058; @@ -36743,49 +36794,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = 11'd0; endcase end - always@(guard__h502878 or - _theResult___fst_exp__h511104 or - out_exp__h511836 or _theResult___exp__h511833) + always@(guard__h502879 or + _theResult___fst_exp__h511105 or + out_exp__h511837 or _theResult___exp__h511834) begin - case (guard__h502878) + case (guard__h502879) 2'b0, 2'b01: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 = - _theResult___fst_exp__h511104; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 = + _theResult___fst_exp__h511105; 2'b10: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 = - out_exp__h511836; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 = + out_exp__h511837; 2'b11: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 = - _theResult___exp__h511833; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 = + _theResult___exp__h511834; endcase end - always@(guard__h511947 or - _theResult___fst_exp__h519937 or _theResult___exp__h520617) + always@(guard__h511948 or + _theResult___fst_exp__h519938 or _theResult___exp__h520618) begin - case (guard__h511947) + case (guard__h511948) 2'b0: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213 = - _theResult___fst_exp__h519937; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213 = + _theResult___fst_exp__h519938; 2'b01, 2'b10, 2'b11: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213 = - _theResult___exp__h520617; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213 = + _theResult___exp__h520618; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h519937 or + _theResult___fst_exp__h519938 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 or - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213) + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - _theResult___fst_exp__h519937; + _theResult___fst_exp__h519938; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089; @@ -36794,49 +36845,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = 11'd0; endcase end - always@(guard__h511947 or - _theResult___fst_exp__h519937 or - out_exp__h520620 or _theResult___exp__h520617) + always@(guard__h511948 or + _theResult___fst_exp__h519938 or + out_exp__h520621 or _theResult___exp__h520618) begin - case (guard__h511947) + case (guard__h511948) 2'b0, 2'b01: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 = - _theResult___fst_exp__h519937; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 = + _theResult___fst_exp__h519938; 2'b10: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 = - out_exp__h520620; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 = + out_exp__h520621; 2'b11: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 = - _theResult___exp__h520617; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 = + _theResult___exp__h520618; endcase end - always@(guard__h493566 or - _theResult___snd__h501478 or _theResult___sfd__h502183) + always@(guard__h493567 or + _theResult___snd__h501479 or _theResult___sfd__h502184) begin - case (guard__h493566) + case (guard__h493567) 2'b0: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215 = - _theResult___snd__h501478[56:5]; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215 = + _theResult___snd__h501479[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215 = - _theResult___sfd__h502183; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215 = + _theResult___sfd__h502184; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h501478 or + _theResult___snd__h501479 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215) + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - _theResult___snd__h501478[56:5]; + _theResult___snd__h501479[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115; @@ -36845,48 +36896,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase end - always@(guard__h493566 or - _theResult___snd__h501478 or - out_sfd__h502186 or _theResult___sfd__h502183) + always@(guard__h493567 or + _theResult___snd__h501479 or + out_sfd__h502187 or _theResult___sfd__h502184) begin - case (guard__h493566) + case (guard__h493567) 2'b0, 2'b01: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 = - _theResult___snd__h501478[56:5]; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 = + _theResult___snd__h501479[56:5]; 2'b10: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 = - out_sfd__h502186; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 = + out_sfd__h502187; 2'b11: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 = - _theResult___sfd__h502183; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 = + _theResult___sfd__h502184; endcase end - always@(guard__h502878 or sfdin__h511098 or _theResult___sfd__h511834) + always@(guard__h502879 or sfdin__h511099 or _theResult___sfd__h511835) begin - case (guard__h502878) + case (guard__h502879) 2'b0: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h511098[56:5]; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h511099[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h511834; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h511835; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511098 or + sfdin__h511099 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217) + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511098[56:5]; + sfdin__h511099[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; @@ -36895,48 +36946,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = 52'd0; endcase end - always@(guard__h502878 or - sfdin__h511098 or out_sfd__h511837 or _theResult___sfd__h511834) + always@(guard__h502879 or + sfdin__h511099 or out_sfd__h511838 or _theResult___sfd__h511835) begin - case (guard__h502878) + case (guard__h502879) 2'b0, 2'b01: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h511098[56:5]; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h511099[56:5]; 2'b10: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h511837; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h511838; 2'b11: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h511834; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h511835; endcase end - always@(guard__h511947 or - _theResult___snd__h519883 or _theResult___sfd__h520618) + always@(guard__h511948 or + _theResult___snd__h519884 or _theResult___sfd__h520619) begin - case (guard__h511947) + case (guard__h511948) 2'b0: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219 = - _theResult___snd__h519883[56:5]; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219 = + _theResult___snd__h519884[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219 = - _theResult___sfd__h520618; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219 = + _theResult___sfd__h520619; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h519883 or + _theResult___snd__h519884 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219) + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - _theResult___snd__h519883[56:5]; + _theResult___snd__h519884[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161; @@ -36945,49 +36996,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase end - always@(guard__h511947 or - _theResult___snd__h519883 or - out_sfd__h520621 or _theResult___sfd__h520618) + always@(guard__h511948 or + _theResult___snd__h519884 or + out_sfd__h520622 or _theResult___sfd__h520619) begin - case (guard__h511947) + case (guard__h511948) 2'b0, 2'b01: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 = - _theResult___snd__h519883[56:5]; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 = + _theResult___snd__h519884[56:5]; 2'b10: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 = - out_sfd__h520621; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 = + out_sfd__h520622; 2'b11: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 = - _theResult___sfd__h520618; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 = + _theResult___sfd__h520619; endcase end - always@(guard__h571723 or - _theResult___snd__h579635 or _theResult___sfd__h580340) + always@(guard__h571724 or + _theResult___snd__h579636 or _theResult___sfd__h580341) begin - case (guard__h571723) + case (guard__h571724) 2'b0: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221 = - _theResult___snd__h579635[56:5]; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221 = + _theResult___snd__h579636[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221 = - _theResult___sfd__h580340; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221 = + _theResult___sfd__h580341; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h579635 or + _theResult___snd__h579636 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 or - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221) + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - _theResult___snd__h579635[56:5]; + _theResult___snd__h579636[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825; @@ -36996,48 +37047,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = 52'd0; endcase end - always@(guard__h571723 or - _theResult___snd__h579635 or - out_sfd__h580343 or _theResult___sfd__h580340) + always@(guard__h571724 or + _theResult___snd__h579636 or + out_sfd__h580344 or _theResult___sfd__h580341) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 = - _theResult___snd__h579635[56:5]; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 = + _theResult___snd__h579636[56:5]; 2'b10: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 = - out_sfd__h580343; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 = + out_sfd__h580344; 2'b11: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 = - _theResult___sfd__h580340; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 = + _theResult___sfd__h580341; endcase end - always@(guard__h581035 or sfdin__h589255 or _theResult___sfd__h589991) + always@(guard__h581036 or sfdin__h589256 or _theResult___sfd__h589992) begin - case (guard__h581035) + case (guard__h581036) 2'b0: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h589255[56:5]; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h589256[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h589991; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h589992; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h589255 or + sfdin__h589256 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 or - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223) + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - sfdin__h589255[56:5]; + sfdin__h589256[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851; @@ -37046,32 +37097,30 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = 52'd0; endcase end - always@(guard__h581035 or - sfdin__h589255 or out_sfd__h589994 or _theResult___sfd__h589991) + always@(guard__h581036 or + sfdin__h589256 or out_sfd__h589995 or _theResult___sfd__h589992) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h589255[56:5]; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h589256[56:5]; 2'b10: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h589994; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h589995; 2'b11: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h589991; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h589992; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37079,8 +37128,7 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888; endcase @@ -37088,9 +37136,7 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37098,34 +37144,33 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852; endcase end - always@(guard__h590104 or - _theResult___snd__h598040 or _theResult___sfd__h598775) + always@(guard__h590105 or + _theResult___snd__h598041 or _theResult___sfd__h598776) begin - case (guard__h590104) + case (guard__h590105) 2'b0: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225 = - _theResult___snd__h598040[56:5]; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225 = + _theResult___snd__h598041[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225 = - _theResult___sfd__h598775; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225 = + _theResult___sfd__h598776; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h598040 or + _theResult___snd__h598041 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 or - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225) + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - _theResult___snd__h598040[56:5]; + _theResult___snd__h598041[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870; @@ -37134,33 +37179,31 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = 52'd0; endcase end - always@(guard__h590104 or - _theResult___snd__h598040 or - out_sfd__h598778 or _theResult___sfd__h598775) + always@(guard__h590105 or + _theResult___snd__h598041 or + out_sfd__h598779 or _theResult___sfd__h598776) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 = - _theResult___snd__h598040[56:5]; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 = + _theResult___snd__h598041[56:5]; 2'b10: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 = - out_sfd__h598778; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 = + out_sfd__h598779; 2'b11: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 = - _theResult___sfd__h598775; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 = + _theResult___sfd__h598776; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37168,8 +37211,7 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936; endcase @@ -37177,9 +37219,7 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37187,8 +37227,7 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978; endcase @@ -37196,9 +37235,7 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37206,116 +37243,35 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020; endcase end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[399:397]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 = - coreFix_aluExe_0_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 = 3'd7; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227) - begin - case (coreFix_aluExe_0_regToExeQ$first[416:414]) - 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - coreFix_aluExe_0_regToExeQ$first[416:396]; - 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - { coreFix_aluExe_0_regToExeQ$first[416:414], - 9'h0AA, - coreFix_aluExe_0_regToExeQ$first[404:400], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227, - coreFix_aluExe_0_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - { 3'd5, 18'h2AAAA }; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[394:383]) - 12'd1971, - 12'd1970, - 12'd1969, - 12'd1968, - 12'd1955, - 12'd1954, - 12'd1953, - 12'd1952, - 12'd3860, - 12'd3859, - 12'd3858, - 12'd3857, - 12'd2818, - 12'd2816, - 12'd836, - 12'd835, - 12'd834, - 12'd833, - 12'd832, - 12'd774, - 12'd773, - 12'd772, - 12'd771, - 12'd770, - 12'd769, - 12'd768, - 12'd384, - 12'd324, - 12'd323, - 12'd322, - 12'd321, - 12'd320, - 12'd262, - 12'd261, - 12'd260, - 12'd256, - 12'd2049, - 12'd2048, - 12'd3074, - 12'd3073, - 12'd3072, - 12'd3, - 12'd2, - 12'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 = - coreFix_aluExe_0_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 = - 12'd2303; - endcase - end always@(coreFix_aluExe_1_regToExeQ$first) begin case (coreFix_aluExe_1_regToExeQ$first[399:397]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = coreFix_aluExe_1_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227) begin case (coreFix_aluExe_1_regToExeQ$first[416:414]) 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = coreFix_aluExe_1_regToExeQ$first[416:396]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = { coreFix_aluExe_1_regToExeQ$first[416:414], 9'h0AA, coreFix_aluExe_1_regToExeQ$first[404:400], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, coreFix_aluExe_1_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = { 3'd5, 18'h2AAAA }; endcase end @@ -37366,9 +37322,89 @@ module mkCore(CLK, 12'd3, 12'd2, 12'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = coreFix_aluExe_1_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = + 12'd2303; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[399:397]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = + coreFix_aluExe_0_regToExeQ$first[399:397]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = 3'd7; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first or + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230) + begin + case (coreFix_aluExe_0_regToExeQ$first[416:414]) + 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + coreFix_aluExe_0_regToExeQ$first[416:396]; + 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + { coreFix_aluExe_0_regToExeQ$first[416:414], + 9'h0AA, + coreFix_aluExe_0_regToExeQ$first[404:400], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, + coreFix_aluExe_0_regToExeQ$first[396] }; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + { 3'd5, 18'h2AAAA }; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[394:383]) + 12'd1971, + 12'd1970, + 12'd1969, + 12'd1968, + 12'd1955, + 12'd1954, + 12'd1953, + 12'd1952, + 12'd3860, + 12'd3859, + 12'd3858, + 12'd3857, + 12'd2818, + 12'd2816, + 12'd836, + 12'd835, + 12'd834, + 12'd833, + 12'd832, + 12'd774, + 12'd773, + 12'd772, + 12'd771, + 12'd770, + 12'd769, + 12'd768, + 12'd384, + 12'd324, + 12'd323, + 12'd322, + 12'd321, + 12'd320, + 12'd262, + 12'd261, + 12'd260, + 12'd256, + 12'd2049, + 12'd2048, + 12'd3074, + 12'd3073, + 12'd3072, + 12'd3, + 12'd2, + 12'd1: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = + coreFix_aluExe_0_regToExeQ$first[394:383]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = 12'd2303; endcase end @@ -37481,10 +37517,10 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h669623 or + always@(k__h669625 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669623) + case (k__h669625) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 = coreFix_aluExe_0_rsAlu$canEnq; @@ -37523,10 +37559,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(k__h669623 or + always@(k__h669625 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669623) + case (k__h669625) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -37672,14 +37708,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h685368 or + always@(idx__h685370 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685368) + case (idx__h685370) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 = fetchStage$pipelines_0_canDeq && @@ -37800,29 +37836,18 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738; endcase end - always@(k__h669623 or + always@(k__h669625 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h669623) + case (k__h669625) 1'd0: - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or @@ -37842,10 +37867,21 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519); endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or - regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941 or + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 or @@ -37867,7 +37903,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 || - regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941; + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941; endcase end always@(fetchStage$pipelines_0_first or @@ -37911,14 +37947,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(idx__h685368 or + always@(idx__h685370 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685368) + case (idx__h685370) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 = (!fetchStage$pipelines_0_canDeq || @@ -38122,138 +38158,138 @@ module mkCore(CLK, begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = - csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + !csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = - csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = - csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + !csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + !csrf_rg_dcsr[12]; endcase end always@(csrf_prv_reg or csrf_rg_dcsr) begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = - !csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = - !csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = - !csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + csrf_rg_dcsr[12]; endcase end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd0; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd1; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd2; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd8; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd9; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd10; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd11; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd12; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd13; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd14; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd15; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd16; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd17; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd18; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd19; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd20; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd21; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd22; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd23; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd24; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd25; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd26; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd27; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd28; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd29; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd29; 12'd1952: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd36; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd36; 12'd1953: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd37; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd37; 12'd1954: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd38; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd38; 12'd1955: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd39; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd39; 12'd1968: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd40; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd40; 12'd1969: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd41; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd41; 12'd1970: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd42; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd42; 12'd1971: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd43; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd43; 12'd2048: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd6; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd7; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd30; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd31; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd3; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd4; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd5; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd32; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd33; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd34; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd44; endcase end - always@(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 or + always@(IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 or rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973) + case (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983) 6'd0: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38266,7 +38302,7 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 54'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8], 2'b0, @@ -38274,22 +38310,22 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd10, 6'd23: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38301,9 +38337,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h721446 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h722429 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38311,7 +38347,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21, 6'd22, 6'd29: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38320,12 +38356,12 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h721446 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h722429 = 64'd0; 6'd37: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38334,17 +38370,152 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h721446 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h722429 = rob$deqPort_0_deq_data[95:32]; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[180:169]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2816, + 12'd2818, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = + rob$deqPort_0_deq_data[180:169]; + default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = + 12'd2303; endcase end always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180) + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h722034 = - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180; - default: x__h722034 = rob$deqPort_0_deq_data[425:362]; + x__h723033 = + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191; + default: x__h723033 = rob$deqPort_0_deq_data[425:362]; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + 4'd15; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[97:96]) + 2'd0, 2'd1: + CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 = + commitStage_f_rob_data$D_OUT[97:96]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 = 2'd2; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 = + commitStage_f_rob_data$D_OUT[165:162]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 = + 4'd15; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 = + commitStage_f_rob_data$D_OUT[165:162]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[97:96]) + 2'd0, 2'd1: + CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 = + rob$deqPort_0_deq_data[97:96]; + default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 = 2'd2; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or @@ -38353,10 +38524,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; endcase end @@ -38366,10 +38537,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; endcase end @@ -38379,10 +38550,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; endcase end @@ -38392,10 +38563,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; endcase end @@ -38405,10 +38576,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; endcase end @@ -38418,13 +38589,31 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = + 3'd0; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -38638,125 +38827,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; endcase end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 = - 4'd15; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254 = 3'd7; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[180:169]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1952, - 12'd1953, - 12'd1954, - 12'd1955, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 = - rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 = - 12'd2303; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = - 3'd0; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[97:96]) - 2'd0, 2'd1: - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 = - rob$deqPort_0_deq_data[97:96]; - default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 = 2'd2; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -38778,25 +38855,16 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884; endcase end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[97:96]) - 2'd0, 2'd1: - CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = - commitStage_f_rob_data$D_OUT[97:96]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = 2'd2; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -38806,10 +38874,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -38819,10 +38887,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -38832,10 +38900,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -38845,10 +38913,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515]; endcase end @@ -38858,10 +38926,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513]; endcase end @@ -38871,10 +38939,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end @@ -38884,10 +38952,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516]; endcase end @@ -38897,13 +38965,33 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) + 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq; + 5'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq; + 5'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready or coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready or @@ -38926,36 +39014,16 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) - 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq; - 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq; - 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1) begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -38965,10 +39033,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -38978,10 +39046,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -38991,10 +39059,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -39004,10 +39072,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -39017,10 +39085,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end @@ -39030,10 +39098,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end @@ -39041,35 +39109,13 @@ module mkCore(CLK, begin case (mmio_dataReqQ_data_0[77:76]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276 = mmio_dataReqQ_data_0[77:72]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276 = { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -39086,9 +39132,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 = 4'd15; endcase end @@ -39139,44 +39207,12 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277 = + CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279 = commitStage_f_rob_data$D_OUT[180:169]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277 = + default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279 = 12'd2303; endcase end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 = - commitStage_f_rob_data$D_OUT[165:162]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 = - 4'd15; - endcase - end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 = - commitStage_f_rob_data$D_OUT[165:162]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 = - 4'd15; - endcase - end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) @@ -39679,6 +39715,7 @@ module mkCore(CLK, commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY 166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY 64'd0; commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0; commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0; coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -39974,6 +40011,9 @@ module mkCore(CLK, if (commitStage_rg_just_after_reset$EN) commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY commitStage_rg_just_after_reset$D_IN; + if (commitStage_rg_old_mip_csr_val$EN) + commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY + commitStage_rg_old_mip_csr_val$D_IN; if (commitStage_rg_run_state$EN) commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY commitStage_rg_run_state$D_IN; @@ -40604,6 +40644,7 @@ module mkCore(CLK, begin commitStage_commitTrap = 166'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; commitStage_rg_just_after_reset = 1'h0; + commitStage_rg_old_mip_csr_val = 64'hAAAAAAAAAAAAAAAA; commitStage_rg_run_state = 1'h0; commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA; coreFix_doStatsReg = 1'h0; @@ -41100,7 +41141,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == 6'd6) + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -41212,7 +41253,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] != 5'd19 && rob$deqPort_1_deq_data[329:325] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438, + commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450, rob$deqPort_1_deq_data[425:362], rob$deqPort_1_deq_data[361:330], " iType:"); @@ -41371,7 +41412,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h603882 == 2'd0) + v__h603883 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index 55f3e6a..ea0a6ee 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -1247,7 +1247,7 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip; // ports of submodule proc - wire [784 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get; + wire [861 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get; wire [76 : 0] proc$hart0_csr_mem_server_request_put; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; @@ -1424,7 +1424,7 @@ module mkCoreW(RST_N_dm_power_on_reset, tv_encode$RDY_v_cpu_in_1_put; // ports of submodule v_td2_to_td_0 - wire [784 : 0] v_td2_to_td_0$in_put; + wire [861 : 0] v_td2_to_td_0$in_put; wire [490 : 0] v_td2_to_td_0$out_get; wire v_td2_to_td_0$EN_in_put, v_td2_to_td_0$EN_out_get, @@ -1432,7 +1432,7 @@ module mkCoreW(RST_N_dm_power_on_reset, v_td2_to_td_0$RDY_out_get; // ports of submodule v_td2_to_td_1 - wire [784 : 0] v_td2_to_td_1$in_put; + wire [861 : 0] v_td2_to_td_1$in_put; wire [490 : 0] v_td2_to_td_1$out_get; wire v_td2_to_td_1$EN_in_put, v_td2_to_td_1$EN_out_get, @@ -1611,10 +1611,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // synopsys translate_off reg [31 : 0] v__h5047; reg [31 : 0] v__h5190; - reg [31 : 0] v__h15736; + reg [31 : 0] v__h15930; reg [31 : 0] v__h5041; reg [31 : 0] v__h5184; - reg [31 : 0] v__h15730; + reg [31 : 0] v__h15924; // synopsys translate_on // remaining internal signals @@ -3422,7 +3422,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule v_td2_to_td_0 assign v_td2_to_td_0$in_put = - { proc$v_to_TV_0_get[784:619], + { proc$v_to_TV_0_get[861:797], + proc$v_to_TV_0_get[797] ? + proc$v_to_TV_0_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + proc$v_to_TV_0_get[720:619], proc$v_to_TV_0_get[619] ? proc$v_to_TV_0_get[618:613] : 6'h2A, proc$v_to_TV_0_get[612:476], proc$v_to_TV_0_get[476] ? @@ -3443,7 +3447,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule v_td2_to_td_1 assign v_td2_to_td_1$in_put = - { proc$v_to_TV_1_get[784:619], + { proc$v_to_TV_1_get[861:797], + proc$v_to_TV_1_get[797] ? + proc$v_to_TV_1_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + proc$v_to_TV_1_get[720:619], proc$v_to_TV_1_get[619] ? proc$v_to_TV_1_get[618:613] : 6'h2A, proc$v_to_TV_1_get[612:476], proc$v_to_TV_1_get[476] ? @@ -3726,15 +3734,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15736 = $stime; + v__h15930 = $stime; #0; end - v__h15730 = v__h15736 / 32'd10; + v__h15924 = v__h15930 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15730, + v__h15924, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v index feb4788..8a1a6a7 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v +++ b/src_SSITH_P3/Verilog_RTL/mkFabric_2x3.v @@ -3328,17 +3328,17 @@ module mkFabric_2x3(CLK, 8'd0 : x__h12338 ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_0$D_OUT[3:0], 66'd3, @@ -3749,23 +3749,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_xactors_from_masters_0_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: @@ -3776,9 +3776,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && @@ -3877,23 +3877,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_xactors_from_masters_1_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: @@ -3904,9 +3904,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 5434ee4..4b6dec6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -88,9 +88,9 @@ // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg // RDY_hart0_put_other_req_put O 1 const -// v_to_TV_0_get O 785 +// v_to_TV_0_get O 862 // RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 785 +// v_to_TV_1_get O 862 // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset @@ -818,16 +818,16 @@ module mkProc(CLK, // actionvalue method v_to_TV_0_get input EN_v_to_TV_0_get; - output [784 : 0] v_to_TV_0_get; + output [861 : 0] v_to_TV_0_get; output RDY_v_to_TV_0_get; // actionvalue method v_to_TV_1_get input EN_v_to_TV_1_get; - output [784 : 0] v_to_TV_1_get; + output [861 : 0] v_to_TV_1_get; output RDY_v_to_TV_1_get; // signals for module outputs - wire [784 : 0] v_to_TV_0_get, v_to_TV_1_get; + wire [861 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; @@ -1357,7 +1357,7 @@ module mkProc(CLK, // ports of submodule core_0 reg [66 : 0] core_0$mmioToPlatform_pRs_enq_x; reg [38 : 0] core_0$mmioToPlatform_pRq_enq_x; - wire [784 : 0] core_0$v_to_TV_0_get, core_0$v_to_TV_1_get; + wire [861 : 0] core_0$v_to_TV_0_get, core_0$v_to_TV_1_get; wire [582 : 0] core_0$dCacheToParent_fromP_enq_x, core_0$iCacheToParent_fromP_enq_x; wire [578 : 0] core_0$dCacheToParent_rsToP_first, @@ -2205,9 +2205,9 @@ module mkProc(CLK, wire [511 : 0] IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1288, SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1438, new_cline__h134569; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1571, + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1570, SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1421; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1566, + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1565, SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1404; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1387; wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__70_BITS_14_ETC___d393; @@ -2347,8 +2347,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1258, IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1278, IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1294, - IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639, + IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638, IF_mmioPlatform_mtimecmp_0_48_ULE_IF_NOT_mmioP_ETC___d613, IF_mmioPlatform_reqFunc_28_BITS_5_TO_4_29_EQ_0_ETC___d445, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__83__ETC___d192, @@ -2363,8 +2363,8 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__000_THEN_propDstId_ETC___d1003, NOT_enqDst_0_dummy2_0_read__067_068_OR_NOT_enq_ETC___d1083, NOT_enqDst_1_0_dummy2_0_read__336_337_OR_NOT_e_ETC___d1352, - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689, + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d734, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d742, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d747, @@ -2383,8 +2383,8 @@ module mkProc(CLK, NOT_propDstData_1_1_dummy2_1_read__355_366_OR__ETC___d1367, NOT_propDstIdx_0_dummy2_1_read__046_047_OR_IF__ETC___d1080, NOT_propDstIdx_1_0_dummy2_1_read__305_306_OR_I_ETC___d1349, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504, mmioPlatform_cycle_39_ULT_99___d340, mmioPlatform_fetchingWay_53_ULT_mmioPlatform_r_ETC___d963, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d323, @@ -2785,7 +2785,11 @@ module mkProc(CLK, // actionvalue method v_to_TV_0_get assign v_to_TV_0_get = - { core_0$v_to_TV_0_get[784:619], + { core_0$v_to_TV_0_get[861:797], + core_0$v_to_TV_0_get[797] ? + core_0$v_to_TV_0_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + core_0$v_to_TV_0_get[720:619], core_0$v_to_TV_0_get[619] ? core_0$v_to_TV_0_get[618:613] : 6'h2A, @@ -2809,7 +2813,11 @@ module mkProc(CLK, // actionvalue method v_to_TV_1_get assign v_to_TV_1_get = - { core_0$v_to_TV_1_get[784:619], + { core_0$v_to_TV_1_get[861:797], + core_0$v_to_TV_1_get[797] ? + core_0$v_to_TV_1_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + core_0$v_to_TV_1_get[720:619], core_0$v_to_TV_1_get[619] ? core_0$v_to_TV_1_get[618:613] : 6'h2A, @@ -3559,32 +3567,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3924,7 +3936,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3942,7 +3954,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3960,7 +3972,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3970,7 +3982,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3979,7 +3991,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3990,7 +4002,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3999,7 +4011,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4007,7 +4019,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -4031,7 +4043,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4048,15 +4060,15 @@ module mkProc(CLK, // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -4290,7 +4302,7 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1571, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1570, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? new_dword__h89402 : @@ -4694,10 +4706,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656, + IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4711,8 +4723,8 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr @@ -5588,7 +5600,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5618,11 +5630,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5970,7 +5982,7 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1273, IF_enqDst_1_0_lat_1_whas__250_THEN_enqDst_1_0__ETC___d1296 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1566 = + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1565 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? new_dword__h89402 : @@ -5987,8 +5999,8 @@ module mkProc(CLK, 3'd4) ? new_dword__h89402 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1571 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1566, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1570 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1565, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? new_dword__h89402 : @@ -5997,11 +6009,11 @@ module mkProc(CLK, 3'd2) ? new_dword__h89402 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_curReq_23_BITS_2_TO_0_65_EQ_0x_ETC___d813 = @@ -6241,14 +6253,14 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__305_AND__ETC___d1346 || IF_NOT_propDstIdx_1_0_dummy2_1_read__305_306_O_ETC___d1350) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638 ; assign NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d734 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && @@ -6425,9 +6437,9 @@ module mkProc(CLK, assign line_addr__h101861 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 = line_addr__h101861 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 = + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 = line_addr__h101775 == llc_mem_server_rg_cacheline_cache_addr ; assign mask__h89398 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? @@ -6995,14 +7007,14 @@ module mkProc(CLK, always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147706 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147706 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147706 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147706 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147706 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147706 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147706 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147706 = llc$to_mem_toM_first[511:448]; + 3'd0: strb8__h147707 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147707 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147707 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147707 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147707 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147707 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147707 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147707 = llc$to_mem_toM_first[575:568]; endcase end always@(llc$dma_respLd_first) @@ -7021,14 +7033,14 @@ module mkProc(CLK, always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147707 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147707 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147707 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147707 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147707 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147707 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147707 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147707 = llc$to_mem_toM_first[575:568]; + 3'd0: data64__h147706 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147706 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147706 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147706 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147706 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147706 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147706 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147706 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or @@ -9807,7 +9819,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) begin v__h134266 = $stime; #0; @@ -9815,63 +9827,63 @@ module mkProc(CLK, v__h134260 = v__h134266 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h134260, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9947,119 +9959,119 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && @@ -11287,139 +11299,139 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", mem_req_wr_addr_awaddr__h147791); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", data64__h147706); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", strb8__h147707); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11506,103 +11518,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", mem_req_rd_addr_araddr__h133867); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) begin v__h160574 = $stime; #0; @@ -11610,41 +11622,41 @@ module mkProc(CLK, v__h160568 = v__h160574 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", v__h160568, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && diff --git a/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v b/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v index 6910a82..90c7ef6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v +++ b/src_SSITH_P3/Verilog_RTL/mkTrace_Data2_to_Trace_Data.v @@ -11,7 +11,7 @@ // RDY_out_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// in_put I 785 +// in_put I 862 // EN_in_put I 1 // EN_out_get I 1 // @@ -46,7 +46,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, input RST_N; // action method in_put - input [784 : 0] in_put; + input [861 : 0] in_put; input EN_in_put; output RDY_in_put; @@ -60,7 +60,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, wire RDY_in_put, RDY_out_get; // ports of submodule f_in - wire [784 : 0] f_in$D_IN, f_in$D_OUT; + wire [861 : 0] f_in$D_IN, f_in$D_OUT; wire f_in$CLR, f_in$DEQ, f_in$EMPTY_N, f_in$ENQ, f_in$FULL_N; // ports of submodule f_out @@ -76,51 +76,54 @@ module mkTrace_Data2_to_Trace_Data(CLK, WILL_FIRE_out_get; // remaining internal signals - reg [63 : 0] x1_avValue_pc__h3456, x1_avValue_word1__h3460; - reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, - csr_addr__h5126; - reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1, - x1_avValue_rd__h3459; - reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4; - reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5; - wire [63 : 0] td_word2__h3496, - td_word2__h3647, - td_word3__h3497, - td_word4__h3384, - x1_avValue_pc__h3420, - x1_avValue_pc__h3726, - x1_avValue_pc__h3793, - x1_avValue_word1__h3506, - x1_avValue_word1__h3543, - x1_avValue_word1__h3619, - x1_avValue_word1__h3696, - x1_avValue_word1__h3797, - x1_avValue_word2__h3507, - x1_avValue_word2__h3620, - x1_avValue_word2__h3798, - x1_avValue_word3__h3508, - x1_avValue_word3__h3799, - x1_avValue_word4__h3463, - x1_avValue_word4__h3583, - x1_avValue_word4__h3800, - x__h4701, - x__h4967, - x__h5065, - x__h5274, - x__h5697; - wire [11 : 0] csraddr__h3479; - wire [4 : 0] td_rd__h3380, - td_rd__h3448, - x1_avValue_rd__h3423, - x1_avValue_rd__h3542, - x1_avValue_rd__h3579, - x1_avValue_rd__h3618, - x1_avValue_rd__h3656, - x1_avValue_rd__h3695, - x1_avValue_rd__h3796, - x1_avValue_rd__h3866; - wire [2 : 0] st_funct3__h346; + reg [63 : 0] x1_avValue_pc__h3546, x1_avValue_word1__h3550; + reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, + csr_addr__h5294; + reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5, + x1_avValue_rd__h3549; + reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3; + reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4; + wire [63 : 0] td_word2__h3586, + td_word2__h3737, + td_word3__h3587, + td_word3__h3951, + td_word4__h3474, + x1_avValue_pc__h3510, + x1_avValue_pc__h3816, + x1_avValue_pc__h3883, + x1_avValue_word1__h3596, + x1_avValue_word1__h3633, + x1_avValue_word1__h3709, + x1_avValue_word1__h3786, + x1_avValue_word1__h3887, + x1_avValue_word2__h3597, + x1_avValue_word2__h3710, + x1_avValue_word2__h3888, + x1_avValue_word3__h3598, + x1_avValue_word3__h3889, + x1_avValue_word3__h3931, + x1_avValue_word4__h3553, + x1_avValue_word4__h3673, + x1_avValue_word4__h3890, + x1_avValue_word4__h3932, + x__h4843, + x__h5134, + x__h5233, + x__h5443, + x__h5875; + wire [11 : 0] csraddr__h3569; + wire [4 : 0] td_rd__h3470, + td_rd__h3538, + x1_avValue_rd__h3513, + x1_avValue_rd__h3632, + x1_avValue_rd__h3669, + x1_avValue_rd__h3708, + x1_avValue_rd__h3746, + x1_avValue_rd__h3785, + x1_avValue_rd__h3886, + x1_avValue_rd__h3987; + wire [2 : 0] st_funct3__h348; // action method in_put assign RDY_in_put = f_in$FULL_N ; @@ -134,7 +137,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, assign WILL_FIRE_out_get = EN_out_get ; // submodule f_in - FIFO2 #(.width(32'd785), .guarded(32'd1)) f_in(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) f_in(.RST(RST_N), .CLK(CLK), .D_IN(f_in$D_IN), .ENQ(f_in$ENQ), @@ -161,14 +164,14 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_in assign f_in$D_IN = - { in_put[784:476], - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + { in_put[861:476], + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, in_put[463:462], in_put[462] ? - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 : - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 : + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, in_put[457:394], - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5, + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4, in_put[391:0] } ; assign f_in$ENQ = EN_in_put ; assign f_in$DEQ = CAN_FIRE_RL_rl_td2_to_td ; @@ -176,68 +179,70 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_out assign f_out$D_IN = - { f_in$D_OUT[784:721], - (f_in$D_OUT[784:721] == 64'd0) ? + { f_in$D_OUT[861:798], + (f_in$D_OUT[861:798] == 64'd0) ? 5'd0 : - (f_in$D_OUT[463] ? - 5'd14 : - ((f_in$D_OUT[393:392] == 2'd0 && - f_in$D_OUT[624:620] == 5'd10) ? - 5'd5 : + (f_in$D_OUT[797] ? + 5'd3 : + (f_in$D_OUT[463] ? + 5'd14 : ((f_in$D_OUT[393:392] == 2'd0 && - (f_in$D_OUT[624:620] == 5'd8 || - f_in$D_OUT[624:620] == 5'd9) || - f_in$D_OUT[624:620] == 5'd3 || - f_in$D_OUT[624:620] == 5'd11) ? - 5'd6 : - ((f_in$D_OUT[619] && f_in$D_OUT[618] && - f_in$D_OUT[624:620] == 5'd12) ? - 5'd8 : - ((f_in$D_OUT[624:620] == 5'd12) ? - 5'd7 : - ((f_in$D_OUT[393:392] == 2'd1 && - f_in$D_OUT[619] && - f_in$D_OUT[618] && - f_in$D_OUT[624:620] == 5'd4) ? - 5'd10 : + f_in$D_OUT[624:620] == 5'd10) ? + 5'd5 : + ((f_in$D_OUT[393:392] == 2'd0 && + (f_in$D_OUT[624:620] == 5'd8 || + f_in$D_OUT[624:620] == 5'd9) || + f_in$D_OUT[624:620] == 5'd3 || + f_in$D_OUT[624:620] == 5'd11) ? + 5'd6 : + ((f_in$D_OUT[619] && f_in$D_OUT[618] && + f_in$D_OUT[624:620] == 5'd12) ? + 5'd8 : + ((f_in$D_OUT[624:620] == 5'd12) ? + 5'd7 : ((f_in$D_OUT[393:392] == 2'd1 && + f_in$D_OUT[619] && + f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? - 5'd9 : + 5'd10 : ((f_in$D_OUT[393:392] == 2'd1 && - f_in$D_OUT[624:620] == 5'd5) ? - 5'd11 : - ((f_in$D_OUT[393:392] != 2'd0 && - f_in$D_OUT[393:392] != 2'd1 && - f_in$D_OUT[624:620] == 5'd13) ? - 5'd16 : - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1))))))))), - x__h4701, + f_in$D_OUT[624:620] == 5'd4) ? + 5'd9 : + ((f_in$D_OUT[393:392] == 2'd1 && + f_in$D_OUT[624:620] == 5'd5) ? + 5'd11 : + ((f_in$D_OUT[393:392] != 2'd0 && + f_in$D_OUT[393:392] != 2'd1 && + f_in$D_OUT[624:620] == 5'd13) ? + 5'd16 : + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5)))))))))), + x__h4843, f_in$D_OUT[626:625] == 2'b11, f_in$D_OUT[656:625], - x1_avValue_rd__h3866, - x__h4967, - x__h5065, - x__h5274, - x__h5697, + x1_avValue_rd__h3987, + x__h5134, + x__h5233, + x__h5443, + x__h5875, f_in$D_OUT[612:549] } ; - assign f_out$ENQ = f_in$EMPTY_N && f_out$FULL_N ; + assign f_out$ENQ = CAN_FIRE_RL_rl_td2_to_td ; assign f_out$DEQ = EN_out_get ; assign f_out$CLR = 1'b0 ; // remaining internal signals - assign csraddr__h3479 = f_in$D_OUT[476] ? csr_addr__h5126 : 12'd0 ; - assign st_funct3__h346 = + assign csraddr__h3569 = f_in$D_OUT[476] ? csr_addr__h5294 : 12'd0 ; + assign st_funct3__h348 = f_in$D_OUT[484] ? 3'b011 : (f_in$D_OUT[480] ? 3'b010 : (f_in$D_OUT[478] ? 3'b001 : 3'b0)) ; - assign td_rd__h3380 = + assign td_rd__h3470 = (f_in$D_OUT[619] && !f_in$D_OUT[618]) ? f_in$D_OUT[617:613] : 5'd0 ; - assign td_rd__h3448 = { 3'd0, f_in$D_OUT[257:256] } ; - assign td_word2__h3496 = + assign td_rd__h3538 = { 3'd0, f_in$D_OUT[257:256] } ; + assign td_word2__h3586 = (f_in$D_OUT[476] && (f_in$D_OUT[638:637] == 2'b01 || (f_in$D_OUT[638:637] == 2'b10 || @@ -245,150 +250,155 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[644:640] != 5'd0)) ? 64'd1 : 64'd0 ; - assign td_word2__h3647 = { 59'd0, f_in$D_OUT[327:323] } ; - assign td_word3__h3497 = { 52'd0, csraddr__h3479 } ; - assign td_word4__h3384 = { 61'd0, st_funct3__h346 } ; - assign x1_avValue_pc__h3420 = + assign td_word2__h3737 = { 59'd0, f_in$D_OUT[327:323] } ; + assign td_word3__h3587 = { 52'd0, csraddr__h3569 } ; + assign td_word3__h3951 = { 52'd0, f_in$D_OUT[796:785] } ; + assign td_word4__h3474 = { 61'd0, st_funct3__h348 } ; + assign x1_avValue_pc__h3510 = f_in$D_OUT[720:657] + ((f_in$D_OUT[626:625] == 2'b11) ? 64'd4 : 64'd2) ; - assign x1_avValue_pc__h3726 = + assign x1_avValue_pc__h3816 = (f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11 || f_in$D_OUT[624:620] == 5'd12 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5 || f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - x1_avValue_pc__h3420 : - x1_avValue_pc__h3456 ; - assign x1_avValue_pc__h3793 = + x1_avValue_pc__h3510 : + x1_avValue_pc__h3546 ; + assign x1_avValue_pc__h3883 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd10 || f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9)) ? f_in$D_OUT[391:328] : - x1_avValue_pc__h3726 ; - assign x1_avValue_rd__h3423 = td_rd__h3380 ; - assign x1_avValue_rd__h3542 = + x1_avValue_pc__h3816 ; + assign x1_avValue_rd__h3513 = td_rd__h3470 ; + assign x1_avValue_rd__h3632 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_rd__h3380 : - x1_avValue_rd__h3459 ; - assign x1_avValue_rd__h3579 = + td_rd__h3470 : + x1_avValue_rd__h3549 ; + assign x1_avValue_rd__h3669 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4) ? - td_rd__h3380 : - x1_avValue_rd__h3542 ; - assign x1_avValue_rd__h3618 = + td_rd__h3470 : + x1_avValue_rd__h3632 ; + assign x1_avValue_rd__h3708 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[617:613] : - x1_avValue_rd__h3579 ; - assign x1_avValue_rd__h3656 = + x1_avValue_rd__h3669 ; + assign x1_avValue_rd__h3746 = (f_in$D_OUT[624:620] == 5'd12) ? - td_rd__h3380 : - x1_avValue_rd__h3618 ; - assign x1_avValue_rd__h3695 = + td_rd__h3470 : + x1_avValue_rd__h3708 ; + assign x1_avValue_rd__h3785 = (f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd12) ? f_in$D_OUT[617:613] : - x1_avValue_rd__h3656 ; - assign x1_avValue_rd__h3796 = + x1_avValue_rd__h3746 ; + assign x1_avValue_rd__h3886 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9) || f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11) ? - td_rd__h3380 : - x1_avValue_rd__h3695 ; - assign x1_avValue_rd__h3866 = - f_in$D_OUT[463] ? td_rd__h3448 : x1_avValue_rd__h3796 ; - assign x1_avValue_word1__h3506 = + td_rd__h3470 : + x1_avValue_rd__h3785 ; + assign x1_avValue_rd__h3987 = + f_in$D_OUT[463] ? td_rd__h3538 : x1_avValue_rd__h3886 ; + assign x1_avValue_word1__h3596 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3460 ; - assign x1_avValue_word1__h3543 = + x1_avValue_word1__h3550 ; + assign x1_avValue_word1__h3633 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5) ? - td_word4__h3384 : - x1_avValue_word1__h3506 ; - assign x1_avValue_word1__h3619 = + td_word4__h3474 : + x1_avValue_word1__h3596 ; + assign x1_avValue_word1__h3709 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3543 ; - assign x1_avValue_word1__h3696 = + x1_avValue_word1__h3633 ; + assign x1_avValue_word1__h3786 = (f_in$D_OUT[624:620] == 5'd12) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3619 ; - assign x1_avValue_word1__h3797 = + x1_avValue_word1__h3709 ; + assign x1_avValue_word1__h3887 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9) || f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3696 ; - assign x1_avValue_word2__h3507 = + x1_avValue_word1__h3786 ; + assign x1_avValue_word2__h3597 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_word2__h3496 : + td_word2__h3586 : f_in$D_OUT[548:485] ; - assign x1_avValue_word2__h3620 = + assign x1_avValue_word2__h3710 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5) ? f_in$D_OUT[548:485] : - x1_avValue_word2__h3507 ; - assign x1_avValue_word2__h3798 = + x1_avValue_word2__h3597 ; + assign x1_avValue_word2__h3888 = (f_in$D_OUT[624:620] == 5'd12) ? - td_word2__h3647 : - x1_avValue_word2__h3620 ; - assign x1_avValue_word3__h3508 = + td_word2__h3737 : + x1_avValue_word2__h3710 ; + assign x1_avValue_word3__h3598 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_word3__h3497 : + td_word3__h3587 : f_in$D_OUT[391:328] ; - assign x1_avValue_word3__h3799 = + assign x1_avValue_word3__h3889 = (f_in$D_OUT[393:392] == 2'd1 && (f_in$D_OUT[624:620] == 5'd4 || f_in$D_OUT[624:620] == 5'd5)) ? f_in$D_OUT[391:328] : - x1_avValue_word3__h3508 ; - assign x1_avValue_word4__h3463 = td_word4__h3384 ; - assign x1_avValue_word4__h3583 = + x1_avValue_word3__h3598 ; + assign x1_avValue_word3__h3931 = + f_in$D_OUT[463] ? f_in$D_OUT[63:0] : x1_avValue_word3__h3889 ; + assign x1_avValue_word4__h3553 = td_word4__h3474 ; + assign x1_avValue_word4__h3673 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? f_in$D_OUT[391:328] : - x1_avValue_word4__h3463 ; - assign x1_avValue_word4__h3800 = + x1_avValue_word4__h3553 ; + assign x1_avValue_word4__h3890 = (f_in$D_OUT[624:620] == 5'd12 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[321:258] : - x1_avValue_word4__h3583 ; - assign x__h4701 = - f_in$D_OUT[463] ? f_in$D_OUT[255:192] : x1_avValue_pc__h3793 ; - assign x__h4967 = - f_in$D_OUT[463] ? f_in$D_OUT[191:128] : x1_avValue_word1__h3797 ; - assign x__h5065 = - f_in$D_OUT[463] ? f_in$D_OUT[127:64] : x1_avValue_word2__h3798 ; - assign x__h5274 = - f_in$D_OUT[463] ? f_in$D_OUT[63:0] : x1_avValue_word3__h3799 ; - assign x__h5697 = - f_in$D_OUT[463] ? f_in$D_OUT[457:394] : x1_avValue_word4__h3800 ; + x1_avValue_word4__h3673 ; + assign x1_avValue_word4__h3932 = + f_in$D_OUT[463] ? f_in$D_OUT[457:394] : x1_avValue_word4__h3890 ; + assign x__h4843 = + f_in$D_OUT[463] ? f_in$D_OUT[255:192] : x1_avValue_pc__h3883 ; + assign x__h5134 = + f_in$D_OUT[463] ? f_in$D_OUT[191:128] : x1_avValue_word1__h3887 ; + assign x__h5233 = + f_in$D_OUT[463] ? f_in$D_OUT[127:64] : x1_avValue_word2__h3888 ; + assign x__h5443 = + f_in$D_OUT[797] ? td_word3__h3951 : x1_avValue_word3__h3931 ; + assign x__h5875 = + f_in$D_OUT[797] ? f_in$D_OUT[784:721] : x1_avValue_word4__h3932 ; always@(f_in$D_OUT) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_word1__h3460 = f_in$D_OUT[191:128]; - default: x1_avValue_word1__h3460 = f_in$D_OUT[612:549]; + 5'd19, 5'd20: x1_avValue_word1__h3550 = f_in$D_OUT[191:128]; + default: x1_avValue_word1__h3550 = f_in$D_OUT[612:549]; endcase end - always@(f_in$D_OUT or x1_avValue_pc__h3420) + always@(f_in$D_OUT or x1_avValue_pc__h3510) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_pc__h3456 = f_in$D_OUT[720:657]; - default: x1_avValue_pc__h3456 = x1_avValue_pc__h3420; + 5'd19, 5'd20: x1_avValue_pc__h3546 = f_in$D_OUT[720:657]; + default: x1_avValue_pc__h3546 = x1_avValue_pc__h3510; endcase end - always@(f_in$D_OUT or x1_avValue_rd__h3423 or td_rd__h3448) + always@(f_in$D_OUT or x1_avValue_rd__h3513 or td_rd__h3538) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_rd__h3459 = td_rd__h3448; - default: x1_avValue_rd__h3459 = x1_avValue_rd__h3423; + 5'd19, 5'd20: x1_avValue_rd__h3549 = td_rd__h3538; + default: x1_avValue_rd__h3549 = x1_avValue_rd__h3513; endcase end always@(f_in$D_OUT) @@ -438,24 +448,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - csr_addr__h5126 = f_in$D_OUT[475:464]; - default: csr_addr__h5126 = 12'd2303; - endcase - end - always@(f_in$D_OUT) - begin - case (f_in$D_OUT[624:620]) - 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd5; - 5'd19, 5'd20: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd15; - default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = - (f_in$D_OUT[393:392] == 2'd1 && - (f_in$D_OUT[624:620] == 5'd2 || - f_in$D_OUT[624:620] == 5'd6 || - f_in$D_OUT[624:620] == 5'd7)) ? - 5'd13 : - 5'd5; + csr_addr__h5294 = f_in$D_OUT[475:464]; + default: csr_addr__h5294 = 12'd2303; endcase end always@(in_put) @@ -505,9 +499,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = in_put[475:464]; - default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = 12'd2303; endcase end @@ -515,9 +509,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin case (in_put[461:458]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = 4'd15; endcase end always@(in_put) @@ -536,18 +530,34 @@ module mkTrace_Data2_to_Trace_Data(CLK, 4'd11, 4'd12, 4'd13: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; endcase end always@(in_put) begin case (in_put[393:392]) 2'd0, 2'd1: - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = in_put[393:392]; - default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = 2'd2; + default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = 2'd2; + endcase + end + always@(f_in$D_OUT) + begin + case (f_in$D_OUT[624:620]) + 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd5; + 5'd19, 5'd20: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd15; + default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = + (f_in$D_OUT[393:392] == 2'd1 && + (f_in$D_OUT[624:620] == 5'd2 || + f_in$D_OUT[624:620] == 5'd6 || + f_in$D_OUT[624:620] == 5'd7)) ? + 5'd13 : + 5'd5; endcase end @@ -558,7 +568,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -588,7 +599,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $display(" fav_td2_to_td: TBD: Unknown iType: Using mkTrace_OTHER for now"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -618,7 +630,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -648,7 +661,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("Trace_Data2 { ", "serial_num: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -676,9 +690,196 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd0 && f_in$D_OUT[624:620] != 5'd1 && f_in$D_OUT[624:620] != 5'd21) - $write("'h%h", f_in$D_OUT[784:721]); + $write("'h%h", f_in$D_OUT[861:798]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(", ", "maybe_csr_upd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -708,7 +909,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "pc: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -738,7 +940,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[720:657]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -768,7 +971,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "orig_inst: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -798,7 +1002,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[656:625]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -828,13 +1033,15 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "iType: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd2) $write("Amo"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || !f_in$D_OUT[618]) && @@ -842,49 +1049,57 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] == 5'd4) $write("Ld"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd5) $write("St"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd6) $write("Lr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd7) $write("Sc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd8) $write("J"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd9) $write("Jr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd10) $write("Br"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1) && f_in$D_OUT[624:620] == 5'd13) $write("Csr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -910,7 +1125,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd13) $write("Interrupt"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -940,7 +1156,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "dst: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -970,7 +1187,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[619]) $write("tagged Valid "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -998,7 +1216,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[619]) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1027,7 +1246,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[618]) $write("tagged Fpu ", "'h%h", f_in$D_OUT[617:613]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1056,7 +1276,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[618]) $write("tagged Gpr ", "'h%h", f_in$D_OUT[617:613]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1084,7 +1305,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[619]) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1114,7 +1336,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "dst_data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1144,7 +1367,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[612:549]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1174,7 +1398,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "store_data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1204,7 +1429,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[548:485]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1234,7 +1460,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "store_data_BE: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1264,7 +1491,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2090,7 +2344,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "csr: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2121,7 +2376,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[476]) $write("tagged Valid "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2152,7 +2408,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[476]) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2184,7 +2441,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1) $write("CSRfflags"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2216,7 +2474,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2) $write("CSRfrm"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2248,7 +2507,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3) $write("CSRfcsr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2280,7 +2540,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3072) $write("CSRcycle"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2312,7 +2573,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3073) $write("CSRtime"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2344,7 +2606,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3074) $write("CSRinstret"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2376,7 +2639,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2048) $write("CSRterminate"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2408,7 +2672,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2049) $write("CSRstats"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2440,7 +2705,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd256) $write("CSRsstatus"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2472,7 +2738,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd260) $write("CSRsie"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2504,7 +2771,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd261) $write("CSRstvec"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2536,7 +2804,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd262) $write("CSRscounteren"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2568,7 +2837,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd320) $write("CSRsscratch"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2600,7 +2870,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd321) $write("CSRsepc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2632,7 +2903,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd322) $write("CSRscause"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2664,7 +2936,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd323) $write("CSRstval"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2696,7 +2969,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd324) $write("CSRsip"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2728,7 +3002,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd384) $write("CSRsatp"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2760,7 +3035,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd768) $write("CSRmstatus"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2792,7 +3068,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd769) $write("CSRmisa"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2824,7 +3101,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd770) $write("CSRmedeleg"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2856,7 +3134,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd771) $write("CSRmideleg"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2888,7 +3167,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd772) $write("CSRmie"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2920,7 +3200,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd773) $write("CSRmtvec"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2952,7 +3233,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd774) $write("CSRmcounteren"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2984,7 +3266,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd832) $write("CSRmscratch"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3016,7 +3299,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd833) $write("CSRmepc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3048,7 +3332,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd834) $write("CSRmcause"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3080,7 +3365,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd835) $write("CSRmtval"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3112,7 +3398,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd836) $write("CSRmip"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3144,7 +3431,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2816) $write("CSRmcycle"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3176,7 +3464,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2818) $write("CSRminstret"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3208,7 +3497,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3857) $write("CSRmvendorid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3240,7 +3530,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3858) $write("CSRmarchid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3272,7 +3563,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3859) $write("CSRmimpid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3304,7 +3596,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3860) $write("CSRmhartid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3336,7 +3629,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1952) $write("CSRtselect"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3368,7 +3662,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1953) $write("CSRtdata1"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3400,7 +3695,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1954) $write("CSRtdata2"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3432,7 +3728,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1955) $write("CSRtdata3"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3464,7 +3761,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1968) $write("CSRdcsr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3496,7 +3794,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1969) $write("CSRdpc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3528,7 +3827,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1970) $write("CSRdscratch0"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3560,7 +3860,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1971) $write("CSRdscratch1"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3635,7 +3936,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] != 12'd1971) $write("CSRnone"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3666,7 +3968,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[476]) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3696,7 +3999,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "trap: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3726,7 +4030,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3756,7 +4061,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3786,7 +4092,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3816,7 +4123,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3846,7 +4154,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "tval: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3876,7 +4185,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[457:394]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3906,7 +4216,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "ppc_vaddr_csrData: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd10 && f_in$D_OUT[624:620] != 5'd8 && @@ -3927,7 +4238,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] == 2'd0) $write("tagged PPC ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -3952,7 +4264,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] == 2'd1) $write("tagged VAddr ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -3972,7 +4285,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] != 2'd1) $write("tagged CSRData ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4002,7 +4316,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "fflags: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4032,7 +4347,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[327:323]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4062,7 +4378,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "will_dirty_fpu_state: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4093,7 +4410,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[322]) $write("True"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4124,7 +4442,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[322]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4154,7 +4473,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "mstatus: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4184,7 +4504,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[321:258]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4214,7 +4535,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "prv: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4244,7 +4566,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[257:256]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4274,7 +4597,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "tvec: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4304,7 +4628,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[255:192]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4334,7 +4659,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "status: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4364,7 +4690,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[191:128]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4394,7 +4721,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "cause: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4424,7 +4752,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[127:64]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4454,7 +4783,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "epc: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4484,7 +4814,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[63:0], " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index 9e1307d..4003cc5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -98,9 +98,9 @@ // RDY_hart0_csr_mem_server_request_put O 1 reg // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg -// v_to_TV_0_get O 785 +// v_to_TV_0_get O 862 // RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 785 +// v_to_TV_1_get O 862 // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset @@ -668,16 +668,16 @@ module mkCore(CLK, // actionvalue method v_to_TV_0_get input EN_v_to_TV_0_get; - output [784 : 0] v_to_TV_0_get; + output [861 : 0] v_to_TV_0_get; output RDY_v_to_TV_0_get; // actionvalue method v_to_TV_1_get input EN_v_to_TV_1_get; - output [784 : 0] v_to_TV_1_get; + output [861 : 0] v_to_TV_1_get; output RDY_v_to_TV_1_get; // signals for module outputs - wire [784 : 0] v_to_TV_0_get, v_to_TV_1_get; + wire [861 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first; wire [162 : 0] deadlock_commitInstStuck_get, deadlock_commitUserInstStuck_get; @@ -848,6 +848,11 @@ module mkCore(CLK, wire commitStage_rg_just_after_reset$D_IN, commitStage_rg_just_after_reset$EN; + // register commitStage_rg_old_mip_csr_val + reg [63 : 0] commitStage_rg_old_mip_csr_val; + wire [63 : 0] commitStage_rg_old_mip_csr_val$D_IN; + wire commitStage_rg_old_mip_csr_val$EN; + // register commitStage_rg_run_state reg commitStage_rg_run_state; wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN; @@ -3783,8 +3788,8 @@ module mkCore(CLK, specTagManager$specUpdate_incorrectSpeculation_kill_all; // ports of submodule v_f_to_TV_0 - reg [784 : 0] v_f_to_TV_0$D_IN; - wire [784 : 0] v_f_to_TV_0$D_OUT; + reg [861 : 0] v_f_to_TV_0$D_IN; + wire [861 : 0] v_f_to_TV_0$D_OUT; wire v_f_to_TV_0$CLR, v_f_to_TV_0$DEQ, v_f_to_TV_0$EMPTY_N, @@ -3792,7 +3797,7 @@ module mkCore(CLK, v_f_to_TV_0$FULL_N; // ports of submodule v_f_to_TV_1 - wire [784 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT; + wire [861 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT; wire v_f_to_TV_1$CLR, v_f_to_TV_1$DEQ, v_f_to_TV_1$EMPTY_N, @@ -3808,6 +3813,7 @@ module mkCore(CLK, CAN_FIRE_RL_commitStage_doSetLSQAtCommit, CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1, CAN_FIRE_RL_commitStage_notifyLSQCommit, + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv, CAN_FIRE_RL_commitStage_rl_send_tv_reset, CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu, CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu, @@ -4049,6 +4055,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doSetLSQAtCommit, WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1, WILL_FIRE_RL_commitStage_notifyLSQCommit, + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv, WILL_FIRE_RL_commitStage_rl_send_tv_reset, WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu, WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu, @@ -4290,9 +4297,10 @@ module mkCore(CLK, reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1, MUX_coreFix_memExe_lsq$respLd_1__VAL_2; reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3; - wire [784 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1, + wire [861 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1, MUX_v_f_to_TV_0$enq_1__VAL_2, - MUX_v_f_to_TV_0$enq_1__VAL_4; + MUX_v_f_to_TV_0$enq_1__VAL_4, + MUX_v_f_to_TV_0$enq_1__VAL_5; wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3, @@ -4370,7 +4378,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3, @@ -4385,6 +4393,7 @@ module mkCore(CLK, MUX_csrf_prv_reg$write_1__VAL_1; wire MUX_commitStage_rg_run_state$write_1__SEL_1, MUX_commitStage_rg_serial_num$write_1__SEL_1, + MUX_commitStage_rg_serial_num$write_1__SEL_2, MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3, MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1, @@ -4501,7 +4510,7 @@ module mkCore(CLK, MUX_csrf_stvec_base_hi_reg$write_1__SEL_1, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, - MUX_flush_reservation$write_1__SEL_2, + MUX_flush_reservation$write_1__SEL_1, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -4517,7 +4526,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_1, MUX_rg_core_run_state$write_1__SEL_4, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_1, MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_1, MUX_sbAggr$setReady_4_put_1__SEL_1, @@ -4525,7 +4534,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_started$write_1__SEL_1, MUX_v_f_to_TV_0$enq_1__SEL_2; // remaining internal signals @@ -4535,53 +4543,53 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10059, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2972, - addr__h294420, - curData__h195852, - data_out__h746306, - data_warl_xformed__h730624, - rVal1__h615386, - rVal1__h640612, - trap_val__h718447, - x__h200591, - x__h731276; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, + addr__h294421, + curData__h195853, + data_out__h747341, + data_warl_xformed__h731607, + rVal1__h615388, + rVal1__h640614, + trap_val__h719427, + x__h200592, + x__h732275; + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20, - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q217, - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q218, - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q219, - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q220, - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q205, - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q206, - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q207, - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q208, - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q209, - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q210, - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q221, - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q222, - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q223, - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q224, - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q225, - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q226, - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q215, - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q216, + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q217, + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q218, + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q219, + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q220, + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q205, + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q206, + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q207, + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q208, + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q209, + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q210, + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q221, + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q222, + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q223, + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q224, + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q225, + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q226, + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q215, + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759, @@ -4593,50 +4601,50 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q83, - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q84, - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q87, - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q88, - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q90, - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q91, - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q120, - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q121, - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q50, - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q51, - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q118, - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q119, - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q48, - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q49, - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q122, - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q123, - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q52, - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q53, - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q124, - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q125, - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q55, - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q56, - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q85, - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q86, - _theResult___fst_sfd__h350488, - _theResult___fst_sfd__h359211, - _theResult___fst_sfd__h367793, - _theResult___fst_sfd__h376977, - _theResult___fst_sfd__h385613, - _theResult___fst_sfd__h396187, - _theResult___fst_sfd__h404908, - _theResult___fst_sfd__h413490, - _theResult___fst_sfd__h422674, - _theResult___fst_sfd__h431310, - _theResult___fst_sfd__h441882, - _theResult___fst_sfd__h450603, - _theResult___fst_sfd__h459185, - _theResult___fst_sfd__h468369, - _theResult___fst_sfd__h477005; + reg [22 : 0] CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q83, + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q84, + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q87, + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q88, + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q89, + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q90, + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q120, + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q121, + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q50, + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q51, + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q118, + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q119, + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q48, + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q49, + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q122, + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q123, + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q52, + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q53, + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q124, + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q125, + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q54, + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q55, + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q85, + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q86, + _theResult___fst_sfd__h350489, + _theResult___fst_sfd__h359212, + _theResult___fst_sfd__h367794, + _theResult___fst_sfd__h376978, + _theResult___fst_sfd__h385614, + _theResult___fst_sfd__h396188, + _theResult___fst_sfd__h404909, + _theResult___fst_sfd__h413491, + _theResult___fst_sfd__h422675, + _theResult___fst_sfd__h431311, + _theResult___fst_sfd__h441883, + _theResult___fst_sfd__h450604, + _theResult___fst_sfd__h459186, + _theResult___fst_sfd__h468370, + _theResult___fst_sfd__h477006; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q286, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q292, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q295, @@ -4644,40 +4652,40 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13829; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417; - reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278, + reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q280, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q287, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q284, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q293, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q290, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q254, + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q301, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q211, - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q212, - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q213, - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q214, - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q183, - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q184, - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q185, - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q186, - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q187, - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q188, - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q160, - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q161, - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q189, - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q190, - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q191, - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q192, - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q143, - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q144, + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q211, + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q212, + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q213, + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q214, + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q183, + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q184, + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q185, + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q186, + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q187, + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q188, + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q160, + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q161, + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q189, + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q190, + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q191, + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q192, + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q143, + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688, @@ -4687,62 +4695,62 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918; - reg [7 : 0] CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q68, - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q69, - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q76, - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q77, - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q81, - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q82, - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q105, - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q106, - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q35, - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q36, - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q103, - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q104, - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q33, - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q34, - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q111, - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q112, - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q41, - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q42, - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q116, - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q117, - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q46, - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q47, - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q70, - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q71, + reg [7 : 0] CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q68, + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q69, + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q76, + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q77, + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q81, + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q82, + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q105, + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q106, + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q35, + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q36, + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q103, + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q104, + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q33, + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q34, + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q111, + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q112, + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q41, + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q42, + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q116, + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q117, + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q46, + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q47, + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q70, + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q71, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430, - _theResult___fst_exp__h350487, - _theResult___fst_exp__h359210, - _theResult___fst_exp__h367792, - _theResult___fst_exp__h376976, - _theResult___fst_exp__h385612, - _theResult___fst_exp__h396186, - _theResult___fst_exp__h404907, - _theResult___fst_exp__h413489, - _theResult___fst_exp__h422673, - _theResult___fst_exp__h431309, - _theResult___fst_exp__h441881, - _theResult___fst_exp__h450602, - _theResult___fst_exp__h459184, - _theResult___fst_exp__h468368, - _theResult___fst_exp__h477004; + _theResult___fst_exp__h350488, + _theResult___fst_exp__h359211, + _theResult___fst_exp__h367793, + _theResult___fst_exp__h376977, + _theResult___fst_exp__h385613, + _theResult___fst_exp__h396187, + _theResult___fst_exp__h404908, + _theResult___fst_exp__h413490, + _theResult___fst_exp__h422674, + _theResult___fst_exp__h431310, + _theResult___fst_exp__h441882, + _theResult___fst_exp__h450603, + _theResult___fst_exp__h459185, + _theResult___fst_exp__h468369, + _theResult___fst_exp__h477005; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q281, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275, - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285; + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q277, + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295; reg [4 : 0] IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14390, IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14556; reg [3 : 0] CASE_checkForException_3243_BITS_3_TO_0_0_chec_ETC__q234, - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279, - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280, + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250, + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q21, CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q22, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q276, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q279, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q278, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, @@ -4750,30 +4758,30 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14393, IF_fetchStage_pipelines_0_first__2992_BIT_68_3_ETC___d13365, IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14557, - i__h717423, - i__h717583; + i__h718403, + i__h718563; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q291, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q255, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10832, - x__h290199, - x__h295969; - reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265, + x__h290200, + x__h295970; + reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q274, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, + CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302, CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8, CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4; @@ -4792,12 +4800,12 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q269, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q276, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241, @@ -4805,46 +4813,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard04921_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94, - CASE_guard04921_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93, - CASE_guard07807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_guard13851_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, - CASE_guard13851_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95, - CASE_guard16876_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard22687_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98, - CASE_guard22687_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, - CASE_guard37348_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard37348_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard41909_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, - CASE_guard41909_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, - CASE_guard46660_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard46660_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard50515_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, - CASE_guard50515_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, - CASE_guard50616_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, - CASE_guard50616_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, - CASE_guard55729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard55729_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard59224_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59, - CASE_guard59224_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58, - CASE_guard59546_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, - CASE_guard59546_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, - CASE_guard68154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61, - CASE_guard68154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, - CASE_guard68382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, - CASE_guard68382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, - CASE_guard76652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard76652_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard76990_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, - CASE_guard76990_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, - CASE_guard85964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard85964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard95033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard95033_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard96214_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, - CASE_guard96214_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, - CASE_guard98495_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_k77209_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_guard04922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94, + CASE_guard04922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93, + CASE_guard07808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard13852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, + CASE_guard13852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95, + CASE_guard16877_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard22688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98, + CASE_guard22688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, + CASE_guard37349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard37349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard41910_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, + CASE_guard41910_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard46661_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard46661_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard50516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, + CASE_guard50516_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, + CASE_guard50617_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, + CASE_guard50617_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, + CASE_guard55730_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard55730_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard59225_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59, + CASE_guard59225_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58, + CASE_guard59547_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, + CASE_guard59547_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, + CASE_guard68155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61, + CASE_guard68155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, + CASE_guard76653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard76653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard76991_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, + CASE_guard76991_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, + CASE_guard85965_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard85965_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard95034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard95034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard96215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, + CASE_guard96215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, + CASE_guard98496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6563, @@ -4915,27 +4923,28 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3042; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2240, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16381; - wire [457 : 0] IF_commitStage_commitTrap_4643_BIT_36_4891_THE_ETC___d15228; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16394; + wire [463 : 0] commitStage_f_rob_data_first__5067_BIT_167_516_ETC___d15239; + wire [457 : 0] rob_deqPort_0_deq_data__4646_BITS_161_TO_98_46_ETC___d15606; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037; - wire [393 : 0] IF_NOT_rob_deqPort_0_deq_data__4635_BITS_329_T_ETC___d15595; + wire [393 : 0] IF_commitStage_f_rob_data_first__5067_BITS_97__ETC___d15238; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3026, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16372; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16385; wire [321 : 0] basicExec___d12137, basicExec___d12839; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3017, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16363, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16376, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11191, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11204, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11197; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2027; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1734; - wire [127 : 0] b__h608062, b__h608138, b__h608239, b__h608251, x__h609063; + wire [127 : 0] b__h608063, b__h608139, b__h608240, b__h608252, x__h609064; wire [68 : 0] execFpuSimple___d11171; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627, - IF_rob_deqPort_0_deq_data__4635_BITS_97_TO_96__ETC___d14808; + IF_rob_deqPort_0_deq_data__4646_BITS_97_TO_96__ETC___d14819; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2602; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9288, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__241_ETC___d12672, @@ -4967,176 +4976,176 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_deq_data__4635_BITS_329_TO_32_ETC___d15494, - _theResult___fst__h608462, - _theResult___snd__h608463, - a___1__h608076, - a___1__h608467, - a__h607914, + IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15505, + _theResult___fst__h608463, + _theResult___snd__h608464, + a___1__h608077, + a___1__h608468, + a__h607915, amoExec___d882, - b___1__h608077, - b___1__h608528, - b__h607915, - base__h720368, - base__h720388, - commitStage_rg_serial_num_4820_PLUS_IF_rob_deq_ETC___d15758, + b___1__h608078, + b___1__h608529, + b__h607916, + base__h721348, + base__h721368, + commitStage_rg_serial_num_4635_PLUS_IF_rob_deq_ETC___d15770, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11260, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11261, - data___1__h479505, - data___1__h480399, - data__h478993, - data__h479887, - fallthrough_pc__h673430, - fallthrough_pc__h689938, - fcsr_csr__read__h615712, - fflags_csr__read__h615687, - frm_csr__read__h615698, - mcause_csr__read__h617354, - mcounteren_csr__read__h617099, - medeleg_csr__read__h616706, - mideleg_csr__read__h616801, - mie_csr__read__h616925, - mip_csr__read__h617587, - mstatus_csr__read__h616558, - mtvec_csr__read__h617007, - n___1__h201994, - n__h197390, - n__read__h617691, - n__read__h617882, + data___1__h479506, + data___1__h480400, + data__h478994, + data__h479888, + fallthrough_pc__h673432, + fallthrough_pc__h689940, + fcsr_csr__read__h615714, + fflags_csr__read__h615689, + frm_csr__read__h615700, + mcause_csr__read__h617356, + mcounteren_csr__read__h617101, + medeleg_csr__read__h616708, + mideleg_csr__read__h616803, + mie_csr__read__h616927, + mip_csr__read__h617589, + mstatus_csr__read__h616560, + mtvec_csr__read__h617009, + n___1__h201995, + n__h197391, + n__read__h617693, + n__read__h617884, n__read__h6759, - n__read__h735179, - next_pc__h730647, - pc__h720352, - q___1__h480474, - rVal1__h486684, - rVal2__h486685, - r___1__h480501, - res_data__h342289, - res_data__h342294, - res_data__h387991, - res_data__h387996, - res_data__h433686, - res_data__h433691, - resp_addr__h296397, - rg_tdata1__read__h618542, - rob_deqPort_0_deq_data__4635_BITS_425_TO_362_4_ETC___d15485, + n__read__h736179, + next_pc__h731630, + pc__h721332, + q___1__h480475, + rVal1__h486685, + rVal2__h486686, + r___1__h480502, + res_data__h342290, + res_data__h342295, + res_data__h387992, + res_data__h387997, + res_data__h433687, + res_data__h433692, + resp_addr__h296398, + rg_tdata1__read__h618544, + rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496, robdeqPort_0_deq_data_BITS_95_TO_32__q245, - satp_csr__read__h616415, - scause_csr__read__h616212, - scounteren_csr__read__h616074, - shiftData__h184459, - sie_csr__read__h615978, - sip_csr__read__h616352, - sstatus_csr__read__h615908, - stvec_csr__read__h616021, - trap_val__h717409, + satp_csr__read__h616417, + scause_csr__read__h616214, + scounteren_csr__read__h616076, + shiftData__h184460, + sie_csr__read__h615980, + sip_csr__read__h616354, + sstatus_csr__read__h615910, + stvec_csr__read__h616023, + trap_val__h718389, upd__h3993, upd__h5310, upd__h6873, - upd__h735290, - v__h614195, - v__h639576, - x__h155287, - x__h158834, - x__h161648, - x__h163496, - x__h18384, - x__h184366, + upd__h736290, + v__h614197, + v__h639578, + x__h155288, + x__h158835, + x__h161649, + x__h163497, + x__h18385, x__h184367, - x__h186791, - x__h20922, - x__h291644, - x__h293498, - x__h46291, - x__h486590, + x__h184368, + x__h186792, + x__h20923, + x__h291645, + x__h293499, + x__h46292, x__h486591, x__h486592, - x__h48827, - x__h608451, - x__h623641, - x__h623642, - x__h646648, - x__h646649, - x__h710207, - x__h722594, - x__h722786, - x__h734674, - x__h738459, - x__h741647, - x_addr__h318494, - x_quotient__h479689, - x_reg_ifc__read__h615817, - x_remainder__h479690, - y__h626399, - y__h649113, - y__h739350, - y__h742215, - y_avValue__h183532, - y_avValue__h184213, - y_avValue__h483729, - y_avValue__h484412, - y_avValue__h485089, - y_avValue__h615329, - y_avValue__h621619, - y_avValue__h640557, - y_avValue__h644636, - y_avValue_new_pc__h720144, - y_avValue_new_pc__h720330, - y_avValue_snd_snd_snd_snd_snd_fst__h739373, - y_avValue_snd_snd_snd_snd_snd_fst__h742276, - y_avValue_snd_snd_snd_snd_snd_fst__h742312, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h741629; + x__h486593, + x__h48828, + x__h608452, + x__h623643, + x__h623644, + x__h646650, + x__h646651, + x__h711187, + x__h723590, + x__h723782, + x__h735673, + x__h739476, + x__h742681, + x_addr__h318495, + x_quotient__h479690, + x_reg_ifc__read__h615819, + x_remainder__h479691, + y__h626401, + y__h649115, + y__h740368, + y__h743250, + y_avValue__h183533, + y_avValue__h184214, + y_avValue__h483730, + y_avValue__h484413, + y_avValue__h485090, + y_avValue__h615331, + y_avValue__h621621, + y_avValue__h640559, + y_avValue__h644638, + y_avValue_new_pc__h721124, + y_avValue_new_pc__h721310, + y_avValue_snd_snd_snd_snd_snd_fst__h740391, + y_avValue_snd_snd_snd_snd_snd_fst__h743311, + y_avValue_snd_snd_snd_snd_snd_fst__h743347, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h742663; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10767, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9997, - IF_csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_c_ETC___d15221, - r1__read__h619385, - r1__read__h619789, - r1__read__h620299, - r1__read__h620304, - r1__read__h620323, - r1__read__h620556, - r1__read__h620722, - r1__read__h620815, - r1__read__h620820, - r1__read__h620839; - wire [61 : 0] r1__read__h619387, + IF_csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_c_ETC___d15232, + r1__read__h619387, r1__read__h619791, + r1__read__h620301, r1__read__h620306, r1__read__h620325, r1__read__h620558, - r1__read__h620698, r1__read__h620724, + r1__read__h620817, r1__read__h620822, r1__read__h620841; - wire [60 : 0] r1__read__h620560, + wire [61 : 0] r1__read__h619389, + r1__read__h619793, + r1__read__h620308, + r1__read__h620327, + r1__read__h620560, r1__read__h620700, r1__read__h620726, + r1__read__h620824, r1__read__h620843; - wire [59 : 0] r1__read__h619389, - r1__read__h619793, - r1__read__h620317, - r1__read__h620327, - r1__read__h620562, + wire [60 : 0] r1__read__h620562, + r1__read__h620702, r1__read__h620728, - r1__read__h620833, r1__read__h620845; - wire [58 : 0] r1__read__h619391, + wire [59 : 0] r1__read__h619391, r1__read__h619795, + r1__read__h620319, r1__read__h620329, r1__read__h620564, r1__read__h620730, + r1__read__h620835, r1__read__h620847; - wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2582, - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3112, - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2791, - r1__read__h619393, + wire [58 : 0] r1__read__h619393, r1__read__h619797, r1__read__h620331, r1__read__h620566, - r1__read__h620702, r1__read__h620732, - r1__read__h620849, - y__h258549; + r1__read__h620849; + wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2582, + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3112, + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2791, + r1__read__h619395, + r1__read__h619799, + r1__read__h620333, + r1__read__h620568, + r1__read__h620704, + r1__read__h620734, + r1__read__h620851, + y__h258550; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99, @@ -5164,187 +5173,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442, - _theResult____h350505, - _theResult____h368144, - _theResult____h396204, - _theResult____h413841, - _theResult____h441899, - _theResult____h459536, - _theResult____h507797, - _theResult____h546650, - _theResult____h585954, - _theResult___snd__h358627, - _theResult___snd__h358638, - _theResult___snd__h358640, - _theResult___snd__h358650, - _theResult___snd__h358656, - _theResult___snd__h358679, - _theResult___snd__h367223, - _theResult___snd__h367225, - _theResult___snd__h367232, - _theResult___snd__h367238, - _theResult___snd__h367261, - _theResult___snd__h376393, - _theResult___snd__h376404, - _theResult___snd__h376406, - _theResult___snd__h376416, - _theResult___snd__h376422, - _theResult___snd__h376445, - _theResult___snd__h385013, - _theResult___snd__h385027, - _theResult___snd__h385033, - _theResult___snd__h385051, - _theResult___snd__h404324, - _theResult___snd__h404335, - _theResult___snd__h404337, - _theResult___snd__h404347, - _theResult___snd__h404353, - _theResult___snd__h404376, - _theResult___snd__h412920, - _theResult___snd__h412922, - _theResult___snd__h412929, - _theResult___snd__h412935, - _theResult___snd__h412958, - _theResult___snd__h422090, - _theResult___snd__h422101, - _theResult___snd__h422103, - _theResult___snd__h422113, - _theResult___snd__h422119, - _theResult___snd__h422142, - _theResult___snd__h430710, - _theResult___snd__h430724, - _theResult___snd__h430730, - _theResult___snd__h430748, - _theResult___snd__h450019, - _theResult___snd__h450030, - _theResult___snd__h450032, - _theResult___snd__h450042, - _theResult___snd__h450048, - _theResult___snd__h450071, - _theResult___snd__h458615, - _theResult___snd__h458617, - _theResult___snd__h458624, - _theResult___snd__h458630, - _theResult___snd__h458653, - _theResult___snd__h467785, - _theResult___snd__h467796, - _theResult___snd__h467798, - _theResult___snd__h467808, - _theResult___snd__h467814, - _theResult___snd__h467837, - _theResult___snd__h476405, - _theResult___snd__h476419, - _theResult___snd__h476425, - _theResult___snd__h476443, - _theResult___snd__h506407, - _theResult___snd__h506409, - _theResult___snd__h506416, - _theResult___snd__h506422, - _theResult___snd__h506445, - _theResult___snd__h516044, - _theResult___snd__h516055, - _theResult___snd__h516057, - _theResult___snd__h516067, - _theResult___snd__h516073, - _theResult___snd__h516096, - _theResult___snd__h524812, - _theResult___snd__h524826, - _theResult___snd__h524832, - _theResult___snd__h524850, - _theResult___snd__h545260, - _theResult___snd__h545262, - _theResult___snd__h545269, - _theResult___snd__h545275, - _theResult___snd__h545298, - _theResult___snd__h554897, - _theResult___snd__h554908, - _theResult___snd__h554910, - _theResult___snd__h554920, - _theResult___snd__h554926, - _theResult___snd__h554949, - _theResult___snd__h563665, - _theResult___snd__h563679, - _theResult___snd__h563685, - _theResult___snd__h563703, - _theResult___snd__h584564, - _theResult___snd__h584566, - _theResult___snd__h584573, - _theResult___snd__h584579, - _theResult___snd__h584602, - _theResult___snd__h594201, - _theResult___snd__h594212, - _theResult___snd__h594214, - _theResult___snd__h594224, - _theResult___snd__h594230, - _theResult___snd__h594253, - _theResult___snd__h602969, - _theResult___snd__h602983, - _theResult___snd__h602989, - _theResult___snd__h603007, - r1__read__h620568, - r1__read__h620704, - r1__read__h620734, - r1__read__h620851, - result__h368757, - result__h414454, - result__h460149, - result__h508410, - result__h547263, - result__h586567, - sfd__h342900, - sfd__h388602, - sfd__h434297, - sfd__h487430, - sfd__h526424, - sfd__h565728, - sfdin__h358610, - sfdin__h376376, - sfdin__h404307, - sfdin__h422073, - sfdin__h450002, - sfdin__h467768, - sfdin__h516027, - sfdin__h554880, - sfdin__h594184, - x__h368854, - x__h414551, - x__h460246, - x__h508505, - x__h547358, - x__h586662; - wire [55 : 0] r1__read__h619395, - r1__read__h619799, - r1__read__h620333, + _theResult____h350506, + _theResult____h368145, + _theResult____h396205, + _theResult____h413842, + _theResult____h441900, + _theResult____h459537, + _theResult____h507798, + _theResult____h546651, + _theResult____h585955, + _theResult___snd__h358628, + _theResult___snd__h358639, + _theResult___snd__h358641, + _theResult___snd__h358651, + _theResult___snd__h358657, + _theResult___snd__h358680, + _theResult___snd__h367224, + _theResult___snd__h367226, + _theResult___snd__h367233, + _theResult___snd__h367239, + _theResult___snd__h367262, + _theResult___snd__h376394, + _theResult___snd__h376405, + _theResult___snd__h376407, + _theResult___snd__h376417, + _theResult___snd__h376423, + _theResult___snd__h376446, + _theResult___snd__h385014, + _theResult___snd__h385028, + _theResult___snd__h385034, + _theResult___snd__h385052, + _theResult___snd__h404325, + _theResult___snd__h404336, + _theResult___snd__h404338, + _theResult___snd__h404348, + _theResult___snd__h404354, + _theResult___snd__h404377, + _theResult___snd__h412921, + _theResult___snd__h412923, + _theResult___snd__h412930, + _theResult___snd__h412936, + _theResult___snd__h412959, + _theResult___snd__h422091, + _theResult___snd__h422102, + _theResult___snd__h422104, + _theResult___snd__h422114, + _theResult___snd__h422120, + _theResult___snd__h422143, + _theResult___snd__h430711, + _theResult___snd__h430725, + _theResult___snd__h430731, + _theResult___snd__h430749, + _theResult___snd__h450020, + _theResult___snd__h450031, + _theResult___snd__h450033, + _theResult___snd__h450043, + _theResult___snd__h450049, + _theResult___snd__h450072, + _theResult___snd__h458616, + _theResult___snd__h458618, + _theResult___snd__h458625, + _theResult___snd__h458631, + _theResult___snd__h458654, + _theResult___snd__h467786, + _theResult___snd__h467797, + _theResult___snd__h467799, + _theResult___snd__h467809, + _theResult___snd__h467815, + _theResult___snd__h467838, + _theResult___snd__h476406, + _theResult___snd__h476420, + _theResult___snd__h476426, + _theResult___snd__h476444, + _theResult___snd__h506408, + _theResult___snd__h506410, + _theResult___snd__h506417, + _theResult___snd__h506423, + _theResult___snd__h506446, + _theResult___snd__h516045, + _theResult___snd__h516056, + _theResult___snd__h516058, + _theResult___snd__h516068, + _theResult___snd__h516074, + _theResult___snd__h516097, + _theResult___snd__h524813, + _theResult___snd__h524827, + _theResult___snd__h524833, + _theResult___snd__h524851, + _theResult___snd__h545261, + _theResult___snd__h545263, + _theResult___snd__h545270, + _theResult___snd__h545276, + _theResult___snd__h545299, + _theResult___snd__h554898, + _theResult___snd__h554909, + _theResult___snd__h554911, + _theResult___snd__h554921, + _theResult___snd__h554927, + _theResult___snd__h554950, + _theResult___snd__h563666, + _theResult___snd__h563680, + _theResult___snd__h563686, + _theResult___snd__h563704, + _theResult___snd__h584565, + _theResult___snd__h584567, + _theResult___snd__h584574, + _theResult___snd__h584580, + _theResult___snd__h584603, + _theResult___snd__h594202, + _theResult___snd__h594213, + _theResult___snd__h594215, + _theResult___snd__h594225, + _theResult___snd__h594231, + _theResult___snd__h594254, + _theResult___snd__h602970, + _theResult___snd__h602984, + _theResult___snd__h602990, + _theResult___snd__h603008, r1__read__h620570, + r1__read__h620706, r1__read__h620736, - r1__read__h620853; - wire [54 : 0] r1__read__h619397, + r1__read__h620853, + result__h368758, + result__h414455, + result__h460150, + result__h508411, + result__h547264, + result__h586568, + sfd__h342901, + sfd__h388603, + sfd__h434298, + sfd__h487431, + sfd__h526425, + sfd__h565729, + sfdin__h358611, + sfdin__h376377, + sfdin__h404308, + sfdin__h422074, + sfdin__h450003, + sfdin__h467769, + sfdin__h516028, + sfdin__h554881, + sfdin__h594185, + x__h368855, + x__h414552, + x__h460247, + x__h508506, + x__h547359, + x__h586663; + wire [55 : 0] r1__read__h619397, r1__read__h619801, r1__read__h620335, r1__read__h620572, r1__read__h620738, r1__read__h620855; - wire [53 : 0] r1__read__h620681, - r1__read__h620706, + wire [54 : 0] r1__read__h619399, + r1__read__h619803, + r1__read__h620337, + r1__read__h620574, r1__read__h620740, - r1__read__h620857, - sfd__h506474, - sfd__h516125, - sfd__h524885, - sfd__h545327, - sfd__h554978, - sfd__h563738, - sfd__h584631, - sfd__h594282, - sfd__h603042, - value__h351127, - value__h396824, - value__h442519; - wire [52 : 0] r1__read__h620574, - r1__read__h620683, + r1__read__h620857; + wire [53 : 0] r1__read__h620683, r1__read__h620708, r1__read__h620742, - r1__read__h620859; + r1__read__h620859, + sfd__h506475, + sfd__h516126, + sfd__h524886, + sfd__h545328, + sfd__h554979, + sfd__h563739, + sfd__h584632, + sfd__h594283, + sfd__h603043, + value__h351128, + value__h396825, + value__h442520; + wire [52 : 0] r1__read__h620576, + r1__read__h620685, + r1__read__h620710, + r1__read__h620744, + r1__read__h620861; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255, @@ -5366,111 +5375,111 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10766, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9287, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9996, - _theResult___fst_sfd__h491384, - _theResult___fst_sfd__h507212, - _theResult___fst_sfd__h507215, - _theResult___fst_sfd__h516863, - _theResult___fst_sfd__h516866, - _theResult___fst_sfd__h525647, - _theResult___fst_sfd__h525650, - _theResult___fst_sfd__h525659, - _theResult___fst_sfd__h525665, - _theResult___fst_sfd__h530237, - _theResult___fst_sfd__h546065, - _theResult___fst_sfd__h546068, - _theResult___fst_sfd__h555716, - _theResult___fst_sfd__h555719, - _theResult___fst_sfd__h564500, - _theResult___fst_sfd__h564503, - _theResult___fst_sfd__h564512, - _theResult___fst_sfd__h564518, - _theResult___fst_sfd__h569541, - _theResult___fst_sfd__h585369, - _theResult___fst_sfd__h585372, - _theResult___fst_sfd__h595020, - _theResult___fst_sfd__h595023, - _theResult___fst_sfd__h603804, - _theResult___fst_sfd__h603807, - _theResult___fst_sfd__h603816, - _theResult___fst_sfd__h603822, - _theResult___sfd__h507112, - _theResult___sfd__h516763, - _theResult___sfd__h525547, - _theResult___sfd__h545965, - _theResult___sfd__h555616, - _theResult___sfd__h564400, - _theResult___sfd__h585269, - _theResult___sfd__h594920, - _theResult___sfd__h603704, - _theResult___snd_fst_sfd__h487384, - _theResult___snd_fst_sfd__h507218, - _theResult___snd_fst_sfd__h525653, - _theResult___snd_fst_sfd__h526378, - _theResult___snd_fst_sfd__h546071, - _theResult___snd_fst_sfd__h564506, - _theResult___snd_fst_sfd__h565682, - _theResult___snd_fst_sfd__h585375, - _theResult___snd_fst_sfd__h603810, - out___1_sfd__h487132, - out___1_sfd__h526126, - out___1_sfd__h565430, - out_sfd__h507115, - out_sfd__h516766, - out_sfd__h525550, - out_sfd__h545968, - out_sfd__h555619, - out_sfd__h564403, - out_sfd__h585272, - out_sfd__h594923, - out_sfd__h603707; - wire [50 : 0] r1__read__h619399, r1__read__h620576; - wire [49 : 0] r1__read__h620685; - wire [48 : 0] r1__read_BITS_62_TO_14___h738479, - r1__read__h619401, - r1__read__h620687; - wire [46 : 0] r1__read__h619403, r1__read__h620580; - wire [45 : 0] r1__read__h619405, r1__read__h620582; - wire [44 : 0] r1__read__h619407, r1__read__h620584; - wire [43 : 0] r1__read__h619409, r1__read__h620586; - wire [42 : 0] r1__read__h620588; - wire [41 : 0] r1__read__h620590; - wire [40 : 0] r1__read__h620592; + _theResult___fst_sfd__h491385, + _theResult___fst_sfd__h507213, + _theResult___fst_sfd__h507216, + _theResult___fst_sfd__h516864, + _theResult___fst_sfd__h516867, + _theResult___fst_sfd__h525648, + _theResult___fst_sfd__h525651, + _theResult___fst_sfd__h525660, + _theResult___fst_sfd__h525666, + _theResult___fst_sfd__h530238, + _theResult___fst_sfd__h546066, + _theResult___fst_sfd__h546069, + _theResult___fst_sfd__h555717, + _theResult___fst_sfd__h555720, + _theResult___fst_sfd__h564501, + _theResult___fst_sfd__h564504, + _theResult___fst_sfd__h564513, + _theResult___fst_sfd__h564519, + _theResult___fst_sfd__h569542, + _theResult___fst_sfd__h585370, + _theResult___fst_sfd__h585373, + _theResult___fst_sfd__h595021, + _theResult___fst_sfd__h595024, + _theResult___fst_sfd__h603805, + _theResult___fst_sfd__h603808, + _theResult___fst_sfd__h603817, + _theResult___fst_sfd__h603823, + _theResult___sfd__h507113, + _theResult___sfd__h516764, + _theResult___sfd__h525548, + _theResult___sfd__h545966, + _theResult___sfd__h555617, + _theResult___sfd__h564401, + _theResult___sfd__h585270, + _theResult___sfd__h594921, + _theResult___sfd__h603705, + _theResult___snd_fst_sfd__h487385, + _theResult___snd_fst_sfd__h507219, + _theResult___snd_fst_sfd__h525654, + _theResult___snd_fst_sfd__h526379, + _theResult___snd_fst_sfd__h546072, + _theResult___snd_fst_sfd__h564507, + _theResult___snd_fst_sfd__h565683, + _theResult___snd_fst_sfd__h585376, + _theResult___snd_fst_sfd__h603811, + out___1_sfd__h487133, + out___1_sfd__h526127, + out___1_sfd__h565431, + out_sfd__h507116, + out_sfd__h516767, + out_sfd__h525551, + out_sfd__h545969, + out_sfd__h555620, + out_sfd__h564404, + out_sfd__h585273, + out_sfd__h594924, + out_sfd__h603708; + wire [50 : 0] r1__read__h619401, r1__read__h620578; + wire [49 : 0] r1__read__h620687; + wire [48 : 0] r1__read_BITS_62_TO_14___h739496, + r1__read__h619403, + r1__read__h620689; + wire [46 : 0] r1__read__h619405, r1__read__h620582; + wire [45 : 0] r1__read__h619407, r1__read__h620584; + wire [44 : 0] r1__read__h619409, r1__read__h620586; + wire [43 : 0] r1__read__h619411, r1__read__h620588; + wire [42 : 0] r1__read__h620590; + wire [41 : 0] r1__read__h620592; + wire [40 : 0] r1__read__h620594; wire [37 : 0] IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14396, IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14560; wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data78993_BITS_31_TO_0__q11, - data79887_BITS_31_TO_0__q15, - imm__h662585, - r1__read__h619411, - r1__read__h620594, - x__h196615, - x__h342304, - x__h388006, - x__h433701, - x__h76236, - x_data__h66085, - x_data_imm__h684503, - x_data_imm__h701169; - wire [29 : 0] r1__read__h619413, r1__read__h620596; - wire [27 : 0] r1__read__h620598; + data78994_BITS_31_TO_0__q11, + data79888_BITS_31_TO_0__q14, + imm__h662587, + r1__read__h619413, + r1__read__h620596, + x__h196616, + x__h342305, + x__h388007, + x__h433702, + x__h76237, + x_data__h66086, + x_data_imm__h684505, + x_data_imm__h701171; + wire [29 : 0] r1__read__h619415, r1__read__h620598; + wire [27 : 0] r1__read__h620600; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14442, - sfd__h358708, - sfd__h367290, - sfd__h376474, - sfd__h385086, - sfd__h404405, - sfd__h412987, - sfd__h422171, - sfd__h430783, - sfd__h450100, - sfd__h458682, - sfd__h467866, - sfd__h476478, - value__h492013, - value__h530866, - value__h570170; + sfd__h358709, + sfd__h367291, + sfd__h376475, + sfd__h385087, + sfd__h404406, + sfd__h412988, + sfd__h422172, + sfd__h430784, + sfd__h450101, + sfd__h458683, + sfd__h467867, + sfd__h476479, + value__h492014, + value__h530867, + value__h570171; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449, @@ -5495,77 +5504,77 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908, - _theResult___fst_sfd__h359214, - _theResult___fst_sfd__h367796, - _theResult___fst_sfd__h376980, - _theResult___fst_sfd__h385616, - _theResult___fst_sfd__h385625, - _theResult___fst_sfd__h385631, - _theResult___fst_sfd__h404911, - _theResult___fst_sfd__h413493, - _theResult___fst_sfd__h422677, - _theResult___fst_sfd__h431313, - _theResult___fst_sfd__h431322, - _theResult___fst_sfd__h431328, - _theResult___fst_sfd__h450606, - _theResult___fst_sfd__h459188, - _theResult___fst_sfd__h468372, - _theResult___fst_sfd__h477008, - _theResult___fst_sfd__h477017, - _theResult___fst_sfd__h477023, - _theResult___sfd__h359133, - _theResult___sfd__h367715, - _theResult___sfd__h376899, - _theResult___sfd__h385535, - _theResult___sfd__h385637, - _theResult___sfd__h404830, - _theResult___sfd__h413412, - _theResult___sfd__h422596, - _theResult___sfd__h431232, - _theResult___sfd__h431334, - _theResult___sfd__h450525, - _theResult___sfd__h459107, - _theResult___sfd__h468291, - _theResult___sfd__h476927, - _theResult___sfd__h477029, - _theResult___snd_fst_sfd__h342850, - _theResult___snd_fst_sfd__h367799, - _theResult___snd_fst_sfd__h385619, - _theResult___snd_fst_sfd__h388552, - _theResult___snd_fst_sfd__h413496, - _theResult___snd_fst_sfd__h431316, - _theResult___snd_fst_sfd__h434247, - _theResult___snd_fst_sfd__h459191, - _theResult___snd_fst_sfd__h477011, - f1_sfd__h487069, - f2_sfd__h526063, - f3_sfd__h565367, - out_f_sfd__h385914, - out_f_sfd__h431611, - out_f_sfd__h477306, - out_sfd__h359136, - out_sfd__h367718, - out_sfd__h376902, - out_sfd__h385538, - out_sfd__h404833, - out_sfd__h413415, - out_sfd__h422599, - out_sfd__h431235, - out_sfd__h450528, - out_sfd__h459110, - out_sfd__h468294, - out_sfd__h476930; - wire [19 : 0] r1__read__h620533; + _theResult___fst_sfd__h359215, + _theResult___fst_sfd__h367797, + _theResult___fst_sfd__h376981, + _theResult___fst_sfd__h385617, + _theResult___fst_sfd__h385626, + _theResult___fst_sfd__h385632, + _theResult___fst_sfd__h404912, + _theResult___fst_sfd__h413494, + _theResult___fst_sfd__h422678, + _theResult___fst_sfd__h431314, + _theResult___fst_sfd__h431323, + _theResult___fst_sfd__h431329, + _theResult___fst_sfd__h450607, + _theResult___fst_sfd__h459189, + _theResult___fst_sfd__h468373, + _theResult___fst_sfd__h477009, + _theResult___fst_sfd__h477018, + _theResult___fst_sfd__h477024, + _theResult___sfd__h359134, + _theResult___sfd__h367716, + _theResult___sfd__h376900, + _theResult___sfd__h385536, + _theResult___sfd__h385638, + _theResult___sfd__h404831, + _theResult___sfd__h413413, + _theResult___sfd__h422597, + _theResult___sfd__h431233, + _theResult___sfd__h431335, + _theResult___sfd__h450526, + _theResult___sfd__h459108, + _theResult___sfd__h468292, + _theResult___sfd__h476928, + _theResult___sfd__h477030, + _theResult___snd_fst_sfd__h342851, + _theResult___snd_fst_sfd__h367800, + _theResult___snd_fst_sfd__h385620, + _theResult___snd_fst_sfd__h388553, + _theResult___snd_fst_sfd__h413497, + _theResult___snd_fst_sfd__h431317, + _theResult___snd_fst_sfd__h434248, + _theResult___snd_fst_sfd__h459192, + _theResult___snd_fst_sfd__h477012, + f1_sfd__h487070, + f2_sfd__h526064, + f3_sfd__h565368, + out_f_sfd__h385915, + out_f_sfd__h431612, + out_f_sfd__h477307, + out_sfd__h359137, + out_sfd__h367719, + out_sfd__h376903, + out_sfd__h385539, + out_sfd__h404834, + out_sfd__h413416, + out_sfd__h422600, + out_sfd__h431236, + out_sfd__h450529, + out_sfd__h459111, + out_sfd__h468295, + out_sfd__h476931; + wire [19 : 0] r1__read__h620535; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059, - _theResult____h658374, - enabled_ints___1__h658899, - enabled_ints__h658945, - pend_ints__h658372, - y__h658911; - wire [13 : 0] r1__read_BITS_13_TO_0___h658921; - wire [12 : 0] IF_rob_deqPort_0_deq_data__4635_BITS_329_TO_32_ETC___d15585, + _theResult____h658376, + enabled_ints___1__h658901, + enabled_ints__h658947, + pend_ints__h658374, + y__h658913; + wire [13 : 0] r1__read_BITS_13_TO_0___h658923; + wire [12 : 0] IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15596, fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13921, - rob_deqPort_0_deq_data__4635_BIT_181_4710_CONC_ETC___d14801; + rob_deqPort_0_deq_data__4646_BIT_181_4721_CONC_ETC___d14812; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10546, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9061, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9776, @@ -5595,25 +5604,25 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438, - csr_addr__h662583, - renaming_spec_bits__h693435, - result__h653951, - result__h654002, - spec_bits__h696594, - w__h653946, - x__h368887, - x__h414584, - x__h460279, - x__h508538, - x__h547391, - x__h586695, - x__h653950, - x__h654001, - y__h653980, - y__h696607, - y_avValue_fst__h689767, - y_avValue_fst__h689796, - y_avValue_fst__h689830; + csr_addr__h662585, + renaming_spec_bits__h693437, + result__h653953, + result__h654004, + spec_bits__h696596, + w__h653948, + x__h368888, + x__h414585, + x__h460280, + x__h508539, + x__h547392, + x__h586696, + x__h653952, + x__h654003, + y__h653982, + y__h696609, + y_avValue_fst__h689769, + y_avValue_fst__h689798, + y_avValue_fst__h689832; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171, @@ -5635,102 +5644,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h507111, - _theResult___exp__h516762, - _theResult___exp__h525546, - _theResult___exp__h545964, - _theResult___exp__h555615, - _theResult___exp__h564399, - _theResult___exp__h585268, - _theResult___exp__h594919, - _theResult___exp__h603703, - _theResult___fst_exp__h491383, - _theResult___fst_exp__h506447, - _theResult___fst_exp__h506453, - _theResult___fst_exp__h506456, - _theResult___fst_exp__h507211, - _theResult___fst_exp__h507214, - _theResult___fst_exp__h516033, - _theResult___fst_exp__h516098, - _theResult___fst_exp__h516104, - _theResult___fst_exp__h516107, - _theResult___fst_exp__h516862, - _theResult___fst_exp__h516865, - _theResult___fst_exp__h524818, - _theResult___fst_exp__h524857, - _theResult___fst_exp__h524863, - _theResult___fst_exp__h524866, - _theResult___fst_exp__h525646, - _theResult___fst_exp__h525649, - _theResult___fst_exp__h525658, - _theResult___fst_exp__h525661, - _theResult___fst_exp__h530236, - _theResult___fst_exp__h545300, - _theResult___fst_exp__h545306, - _theResult___fst_exp__h545309, - _theResult___fst_exp__h546064, - _theResult___fst_exp__h546067, - _theResult___fst_exp__h554886, - _theResult___fst_exp__h554951, - _theResult___fst_exp__h554957, - _theResult___fst_exp__h554960, - _theResult___fst_exp__h555715, - _theResult___fst_exp__h555718, - _theResult___fst_exp__h563671, - _theResult___fst_exp__h563710, - _theResult___fst_exp__h563716, - _theResult___fst_exp__h563719, - _theResult___fst_exp__h564499, - _theResult___fst_exp__h564502, - _theResult___fst_exp__h564511, - _theResult___fst_exp__h564514, - _theResult___fst_exp__h569540, - _theResult___fst_exp__h584604, - _theResult___fst_exp__h584610, - _theResult___fst_exp__h584613, - _theResult___fst_exp__h585368, - _theResult___fst_exp__h585371, - _theResult___fst_exp__h594190, - _theResult___fst_exp__h594255, - _theResult___fst_exp__h594261, - _theResult___fst_exp__h594264, - _theResult___fst_exp__h595019, - _theResult___fst_exp__h595022, - _theResult___fst_exp__h602975, - _theResult___fst_exp__h603014, - _theResult___fst_exp__h603020, - _theResult___fst_exp__h603023, - _theResult___fst_exp__h603803, - _theResult___fst_exp__h603806, - _theResult___fst_exp__h603815, - _theResult___fst_exp__h603818, - _theResult___snd_fst_exp__h507217, - _theResult___snd_fst_exp__h525652, - _theResult___snd_fst_exp__h546070, - _theResult___snd_fst_exp__h564505, - _theResult___snd_fst_exp__h585374, - _theResult___snd_fst_exp__h603809, + _theResult___exp__h507112, + _theResult___exp__h516763, + _theResult___exp__h525547, + _theResult___exp__h545965, + _theResult___exp__h555616, + _theResult___exp__h564400, + _theResult___exp__h585269, + _theResult___exp__h594920, + _theResult___exp__h603704, + _theResult___fst_exp__h491384, + _theResult___fst_exp__h506448, + _theResult___fst_exp__h506454, + _theResult___fst_exp__h506457, + _theResult___fst_exp__h507212, + _theResult___fst_exp__h507215, + _theResult___fst_exp__h516034, + _theResult___fst_exp__h516099, + _theResult___fst_exp__h516105, + _theResult___fst_exp__h516108, + _theResult___fst_exp__h516863, + _theResult___fst_exp__h516866, + _theResult___fst_exp__h524819, + _theResult___fst_exp__h524858, + _theResult___fst_exp__h524864, + _theResult___fst_exp__h524867, + _theResult___fst_exp__h525647, + _theResult___fst_exp__h525650, + _theResult___fst_exp__h525659, + _theResult___fst_exp__h525662, + _theResult___fst_exp__h530237, + _theResult___fst_exp__h545301, + _theResult___fst_exp__h545307, + _theResult___fst_exp__h545310, + _theResult___fst_exp__h546065, + _theResult___fst_exp__h546068, + _theResult___fst_exp__h554887, + _theResult___fst_exp__h554952, + _theResult___fst_exp__h554958, + _theResult___fst_exp__h554961, + _theResult___fst_exp__h555716, + _theResult___fst_exp__h555719, + _theResult___fst_exp__h563672, + _theResult___fst_exp__h563711, + _theResult___fst_exp__h563717, + _theResult___fst_exp__h563720, + _theResult___fst_exp__h564500, + _theResult___fst_exp__h564503, + _theResult___fst_exp__h564512, + _theResult___fst_exp__h564515, + _theResult___fst_exp__h569541, + _theResult___fst_exp__h584605, + _theResult___fst_exp__h584611, + _theResult___fst_exp__h584614, + _theResult___fst_exp__h585369, + _theResult___fst_exp__h585372, + _theResult___fst_exp__h594191, + _theResult___fst_exp__h594256, + _theResult___fst_exp__h594262, + _theResult___fst_exp__h594265, + _theResult___fst_exp__h595020, + _theResult___fst_exp__h595023, + _theResult___fst_exp__h602976, + _theResult___fst_exp__h603015, + _theResult___fst_exp__h603021, + _theResult___fst_exp__h603024, + _theResult___fst_exp__h603804, + _theResult___fst_exp__h603807, + _theResult___fst_exp__h603816, + _theResult___fst_exp__h603819, + _theResult___snd_fst_exp__h507218, + _theResult___snd_fst_exp__h525653, + _theResult___snd_fst_exp__h546071, + _theResult___snd_fst_exp__h564506, + _theResult___snd_fst_exp__h585375, + _theResult___snd_fst_exp__h603810, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107, - din_inc___2_exp__h525706, - din_inc___2_exp__h525741, - din_inc___2_exp__h525767, - din_inc___2_exp__h564559, - din_inc___2_exp__h564594, - din_inc___2_exp__h564620, - din_inc___2_exp__h603863, - din_inc___2_exp__h603898, - din_inc___2_exp__h603924, - out_exp__h507114, - out_exp__h516765, - out_exp__h525549, - out_exp__h545967, - out_exp__h555618, - out_exp__h564402, - out_exp__h585271, - out_exp__h594922, - out_exp__h603706; + din_inc___2_exp__h525707, + din_inc___2_exp__h525742, + din_inc___2_exp__h525768, + din_inc___2_exp__h564560, + din_inc___2_exp__h564595, + din_inc___2_exp__h564621, + din_inc___2_exp__h603864, + din_inc___2_exp__h603899, + din_inc___2_exp__h603925, + out_exp__h507115, + out_exp__h516766, + out_exp__h525550, + out_exp__h545968, + out_exp__h555619, + out_exp__h564403, + out_exp__h585272, + out_exp__h594923, + out_exp__h603707; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4972, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756; @@ -5761,124 +5770,124 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113, - _theResult___exp__h359132, - _theResult___exp__h367714, - _theResult___exp__h376898, - _theResult___exp__h385534, - _theResult___exp__h385636, - _theResult___exp__h404829, - _theResult___exp__h413411, - _theResult___exp__h422595, - _theResult___exp__h431231, - _theResult___exp__h431333, - _theResult___exp__h450524, - _theResult___exp__h459106, - _theResult___exp__h468290, - _theResult___exp__h476926, - _theResult___exp__h477028, - _theResult___fst_exp__h358616, - _theResult___fst_exp__h358681, - _theResult___fst_exp__h358687, - _theResult___fst_exp__h358690, - _theResult___fst_exp__h359213, - _theResult___fst_exp__h367263, - _theResult___fst_exp__h367269, - _theResult___fst_exp__h367272, - _theResult___fst_exp__h367795, - _theResult___fst_exp__h376382, - _theResult___fst_exp__h376447, - _theResult___fst_exp__h376453, - _theResult___fst_exp__h376456, - _theResult___fst_exp__h376979, - _theResult___fst_exp__h385019, - _theResult___fst_exp__h385058, - _theResult___fst_exp__h385064, - _theResult___fst_exp__h385067, - _theResult___fst_exp__h385615, - _theResult___fst_exp__h385624, - _theResult___fst_exp__h385627, - _theResult___fst_exp__h404313, - _theResult___fst_exp__h404378, - _theResult___fst_exp__h404384, - _theResult___fst_exp__h404387, - _theResult___fst_exp__h404910, - _theResult___fst_exp__h412960, - _theResult___fst_exp__h412966, - _theResult___fst_exp__h412969, - _theResult___fst_exp__h413492, - _theResult___fst_exp__h422079, - _theResult___fst_exp__h422144, - _theResult___fst_exp__h422150, - _theResult___fst_exp__h422153, - _theResult___fst_exp__h422676, - _theResult___fst_exp__h430716, - _theResult___fst_exp__h430755, - _theResult___fst_exp__h430761, - _theResult___fst_exp__h430764, - _theResult___fst_exp__h431312, - _theResult___fst_exp__h431321, - _theResult___fst_exp__h431324, - _theResult___fst_exp__h450008, - _theResult___fst_exp__h450073, - _theResult___fst_exp__h450079, - _theResult___fst_exp__h450082, - _theResult___fst_exp__h450605, - _theResult___fst_exp__h458655, - _theResult___fst_exp__h458661, - _theResult___fst_exp__h458664, - _theResult___fst_exp__h459187, - _theResult___fst_exp__h467774, - _theResult___fst_exp__h467839, - _theResult___fst_exp__h467845, - _theResult___fst_exp__h467848, - _theResult___fst_exp__h468371, - _theResult___fst_exp__h476411, - _theResult___fst_exp__h476450, - _theResult___fst_exp__h476456, - _theResult___fst_exp__h476459, - _theResult___fst_exp__h477007, - _theResult___fst_exp__h477016, - _theResult___fst_exp__h477019, - _theResult___snd_fst_exp__h367798, - _theResult___snd_fst_exp__h385618, - _theResult___snd_fst_exp__h413495, - _theResult___snd_fst_exp__h431315, - _theResult___snd_fst_exp__h459190, - _theResult___snd_fst_exp__h477010, - din_inc___2_exp__h385649, - din_inc___2_exp__h385673, - din_inc___2_exp__h385703, - din_inc___2_exp__h385727, - din_inc___2_exp__h431346, - din_inc___2_exp__h431370, - din_inc___2_exp__h431400, - din_inc___2_exp__h431424, - din_inc___2_exp__h477041, - din_inc___2_exp__h477065, - din_inc___2_exp__h477095, - din_inc___2_exp__h477119, - f1_exp87068_MINUS_127__q136, - f1_exp__h487068, - f2_exp26062_MINUS_127__q176, - f2_exp__h526062, - f3_exp65366_MINUS_127__q153, - f3_exp__h565366, - out_exp__h359135, - out_exp__h367717, - out_exp__h376901, - out_exp__h385537, - out_exp__h404832, - out_exp__h413414, - out_exp__h422598, - out_exp__h431234, - out_exp__h450527, - out_exp__h459109, - out_exp__h468293, - out_exp__h476929, - out_f_exp__h385913, - out_f_exp__h431610, - out_f_exp__h477305, - x__h619370; + _theResult___exp__h359133, + _theResult___exp__h367715, + _theResult___exp__h376899, + _theResult___exp__h385535, + _theResult___exp__h385637, + _theResult___exp__h404830, + _theResult___exp__h413412, + _theResult___exp__h422596, + _theResult___exp__h431232, + _theResult___exp__h431334, + _theResult___exp__h450525, + _theResult___exp__h459107, + _theResult___exp__h468291, + _theResult___exp__h476927, + _theResult___exp__h477029, + _theResult___fst_exp__h358617, + _theResult___fst_exp__h358682, + _theResult___fst_exp__h358688, + _theResult___fst_exp__h358691, + _theResult___fst_exp__h359214, + _theResult___fst_exp__h367264, + _theResult___fst_exp__h367270, + _theResult___fst_exp__h367273, + _theResult___fst_exp__h367796, + _theResult___fst_exp__h376383, + _theResult___fst_exp__h376448, + _theResult___fst_exp__h376454, + _theResult___fst_exp__h376457, + _theResult___fst_exp__h376980, + _theResult___fst_exp__h385020, + _theResult___fst_exp__h385059, + _theResult___fst_exp__h385065, + _theResult___fst_exp__h385068, + _theResult___fst_exp__h385616, + _theResult___fst_exp__h385625, + _theResult___fst_exp__h385628, + _theResult___fst_exp__h404314, + _theResult___fst_exp__h404379, + _theResult___fst_exp__h404385, + _theResult___fst_exp__h404388, + _theResult___fst_exp__h404911, + _theResult___fst_exp__h412961, + _theResult___fst_exp__h412967, + _theResult___fst_exp__h412970, + _theResult___fst_exp__h413493, + _theResult___fst_exp__h422080, + _theResult___fst_exp__h422145, + _theResult___fst_exp__h422151, + _theResult___fst_exp__h422154, + _theResult___fst_exp__h422677, + _theResult___fst_exp__h430717, + _theResult___fst_exp__h430756, + _theResult___fst_exp__h430762, + _theResult___fst_exp__h430765, + _theResult___fst_exp__h431313, + _theResult___fst_exp__h431322, + _theResult___fst_exp__h431325, + _theResult___fst_exp__h450009, + _theResult___fst_exp__h450074, + _theResult___fst_exp__h450080, + _theResult___fst_exp__h450083, + _theResult___fst_exp__h450606, + _theResult___fst_exp__h458656, + _theResult___fst_exp__h458662, + _theResult___fst_exp__h458665, + _theResult___fst_exp__h459188, + _theResult___fst_exp__h467775, + _theResult___fst_exp__h467840, + _theResult___fst_exp__h467846, + _theResult___fst_exp__h467849, + _theResult___fst_exp__h468372, + _theResult___fst_exp__h476412, + _theResult___fst_exp__h476451, + _theResult___fst_exp__h476457, + _theResult___fst_exp__h476460, + _theResult___fst_exp__h477008, + _theResult___fst_exp__h477017, + _theResult___fst_exp__h477020, + _theResult___snd_fst_exp__h367799, + _theResult___snd_fst_exp__h385619, + _theResult___snd_fst_exp__h413496, + _theResult___snd_fst_exp__h431316, + _theResult___snd_fst_exp__h459191, + _theResult___snd_fst_exp__h477011, + din_inc___2_exp__h385650, + din_inc___2_exp__h385674, + din_inc___2_exp__h385704, + din_inc___2_exp__h385728, + din_inc___2_exp__h431347, + din_inc___2_exp__h431371, + din_inc___2_exp__h431401, + din_inc___2_exp__h431425, + din_inc___2_exp__h477042, + din_inc___2_exp__h477066, + din_inc___2_exp__h477096, + din_inc___2_exp__h477120, + f1_exp87069_MINUS_127__q136, + f1_exp__h487069, + f2_exp26063_MINUS_127__q176, + f2_exp__h526063, + f3_exp65367_MINUS_127__q153, + f3_exp__h565367, + out_exp__h359136, + out_exp__h367718, + out_exp__h376902, + out_exp__h385538, + out_exp__h404833, + out_exp__h413415, + out_exp__h422599, + out_exp__h431235, + out_exp__h450528, + out_exp__h459110, + out_exp__h468294, + out_exp__h476930, + out_f_exp__h385914, + out_f_exp__h431611, + out_f_exp__h477306, + x__h619372; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131, @@ -5898,11 +5907,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2176, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16407, - x__h184588, - x__h720383; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16420, + x__h184589, + x__h721363; wire [4 : 0] IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14613, - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15975, + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d15988, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5269, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6661, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8053, @@ -5920,25 +5929,25 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8065, checkForException___d13243, checkForException___d13943, - fflags__h736831, - fflags__h739527, - fflags__h742192, - old_fflags__h741619, - po_fflags__h736817, - po_fflags__h739513, - r1__read__h620936, - res_fflags__h342290, - res_fflags__h387992, - res_fflags__h433687, - rob_deqPort_0_deq_data__4635_BIT_166_4651_CONC_ETC___d14700, - rs1__h662584, - x__h155281, - x__h158828, - x__h161644, - x__h291632, - y_avValue_fst__h738888, - y_avValue_fst__h742097, - y_avValue_fst__h742129; + fflags__h737833, + fflags__h740546, + fflags__h743227, + old_fflags__h742653, + po_fflags__h737818, + po_fflags__h740531, + r1__read__h620938, + res_fflags__h342291, + res_fflags__h387993, + res_fflags__h433688, + rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, + rs1__h662586, + x__h155282, + x__h158829, + x__h161645, + x__h291633, + y_avValue_fst__h739906, + y_avValue_fst__h743132, + y_avValue_fst__h743164; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1879, IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1881, IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1883, @@ -5965,77 +5974,77 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2933, IF_coreFix_memExe_dTlb_procResp__742_BITS_177__ETC___d1824, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, - cause_code__h717408, - vm_mode_reg__read__h620539; + cause_code__h718388, + vm_mode_reg__read__h620541; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2571, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2890, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, - _theResult_____2__h300941, - dcsr_cause__h716927, - next_deqP___1__h301220, - v__h300361, - v__h300592, - x__h306571, - x_decodeInfo_frm__h662268; + _theResult_____2__h300942, + dcsr_cause__h717907, + next_deqP___1__h301221, + v__h300362, + v__h300593, + x__h306572, + x_decodeInfo_frm__h662270; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15994, - IF_sfdin04307_BIT_33_THEN_2_ELSE_0__q65, - IF_sfdin16027_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin22073_BIT_33_THEN_2_ELSE_0__q75, - IF_sfdin50002_BIT_33_THEN_2_ELSE_0__q100, - IF_sfdin54880_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin58610_BIT_33_THEN_2_ELSE_0__q30, - IF_sfdin67768_BIT_33_THEN_2_ELSE_0__q110, - IF_sfdin76376_BIT_33_THEN_2_ELSE_0__q40, - IF_sfdin94184_BIT_4_THEN_2_ELSE_0__q156, - IF_theResult___snd02969_BIT_4_THEN_2_ELSE_0__q159, - IF_theResult___snd06407_BIT_4_THEN_2_ELSE_0__q135, - IF_theResult___snd12920_BIT_33_THEN_2_ELSE_0__q67, - IF_theResult___snd24812_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd30710_BIT_33_THEN_2_ELSE_0__q80, - IF_theResult___snd45260_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd58615_BIT_33_THEN_2_ELSE_0__q102, - IF_theResult___snd63665_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd67223_BIT_33_THEN_2_ELSE_0__q32, - IF_theResult___snd76405_BIT_33_THEN_2_ELSE_0__q115, - IF_theResult___snd84564_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd85013_BIT_33_THEN_2_ELSE_0__q45, - guard__h350515, - guard__h359224, - guard__h368154, - guard__h376990, - guard__h396214, - guard__h404921, - guard__h413851, - guard__h422687, - guard__h441909, - guard__h450616, - guard__h459546, - guard__h468382, - guard__h498495, - guard__h507807, - guard__h516876, - guard__h537348, - guard__h546660, - guard__h555729, - guard__h576652, - guard__h585964, - guard__h595033, - prv__h743861, - prv__h743905, - r1__read_BITS_13_TO_12___h662453, - sbIdx__h158707, - v__h609133, - v__h609143, - v__h610174, - x__h730822, - x__h742456, - x_prv__h720451, - x_prv__h731271, - y_avValue_snd_snd_snd_fst__h739363, - y_avValue_snd_snd_snd_fst__h742266, - y_avValue_snd_snd_snd_fst__h742302; + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d16007, + IF_sfdin04308_BIT_33_THEN_2_ELSE_0__q65, + IF_sfdin16028_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin22074_BIT_33_THEN_2_ELSE_0__q75, + IF_sfdin50003_BIT_33_THEN_2_ELSE_0__q100, + IF_sfdin54881_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin58611_BIT_33_THEN_2_ELSE_0__q30, + IF_sfdin67769_BIT_33_THEN_2_ELSE_0__q110, + IF_sfdin76377_BIT_33_THEN_2_ELSE_0__q40, + IF_sfdin94185_BIT_4_THEN_2_ELSE_0__q156, + IF_theResult___snd02970_BIT_4_THEN_2_ELSE_0__q159, + IF_theResult___snd06408_BIT_4_THEN_2_ELSE_0__q135, + IF_theResult___snd12921_BIT_33_THEN_2_ELSE_0__q67, + IF_theResult___snd24813_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd30711_BIT_33_THEN_2_ELSE_0__q80, + IF_theResult___snd45261_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd58616_BIT_33_THEN_2_ELSE_0__q102, + IF_theResult___snd63666_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd67224_BIT_33_THEN_2_ELSE_0__q32, + IF_theResult___snd76406_BIT_33_THEN_2_ELSE_0__q115, + IF_theResult___snd84565_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd85014_BIT_33_THEN_2_ELSE_0__q45, + guard__h350516, + guard__h359225, + guard__h368155, + guard__h376991, + guard__h396215, + guard__h404922, + guard__h413852, + guard__h422688, + guard__h441910, + guard__h450617, + guard__h459547, + guard__h468383, + guard__h498496, + guard__h507808, + guard__h516877, + guard__h537349, + guard__h546661, + guard__h555730, + guard__h576653, + guard__h585965, + guard__h595034, + prv__h744896, + prv__h744940, + r1__read_BITS_13_TO_12___h662455, + sbIdx__h158708, + v__h609134, + v__h609144, + v__h610175, + x__h731805, + x__h743491, + x_prv__h721432, + x_prv__h732255, + y_avValue_snd_snd_snd_fst__h740381, + y_avValue_snd_snd_snd_fst__h743301, + y_avValue_snd_snd_snd_fst__h743337; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5169, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5219, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6561, @@ -6115,7 +6124,7 @@ module mkCore(CLK, IF_NOT_fetchStage_pipelines_0_canDeq__2990_299_ETC___d14161, IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14076, IF_NOT_fetchStage_pipelines_1_first__3001_BITS_ETC___d14160, - IF_NOT_rob_deqPort_1_deq_data__5631_BIT_25_563_ETC___d15985, + IF_NOT_rob_deqPort_1_deq_data__5642_BIT_25_564_ETC___d15998, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10051, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10587, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10820, @@ -6238,7 +6247,7 @@ module mkCore(CLK, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__5628_THEN_IF_NOT_rob__ETC___d15986, + IF_rob_deqPort_1_canDeq__5639_THEN_IF_NOT_rob__ETC___d15999, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5321, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5349, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6713, @@ -6248,7 +6257,7 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13579, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13668, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13970, - NOT_IF_NOT_rob_deqPort_0_canDeq__5623_5624_OR__ETC___d15991, + NOT_IF_NOT_rob_deqPort_0_canDeq__5634_5635_OR__ETC___d16004, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10880, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10922, @@ -6263,10 +6272,12 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401, NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13729, - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14926, - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14933, - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996, - NOT_commitStage_rg_run_state_4641_4642_AND_NOT_ETC___d15306, + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d14936, + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d14943, + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007, + NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15316, + NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15327, + NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15688, NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12437, NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12467, NOT_coreFix_aluExe_1_bypassWire_0_whas__1522_1_ETC___d11549, @@ -6326,7 +6337,7 @@ module mkCore(CLK, NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13572, NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13666, NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13968, - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043, + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054, NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13772, NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14015, NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14059, @@ -6382,10 +6393,10 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d13981, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14123, NOT_renameStage_rg_m_halt_req_3019_BIT_4_3020__ETC___d14141, - NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_RDY_ETC___d15665, - NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_deq_ETC___d15969, - NOT_rob_deqPort_0_deq_data__4635_BITS_329_TO_3_ETC___d15295, - NOT_rob_deqPort_1_deq_data__5631_BIT_25_5632_5_ETC___d15662, + NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_RDY_ETC___d15676, + NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_deq_ETC___d15982, + NOT_rob_deqPort_0_deq_data__4646_BITS_329_TO_3_ETC___d15305, + NOT_rob_deqPort_1_deq_data__5642_BIT_25_5643_5_ETC___d15673, NOT_specTagManager_canClaim__3651_3737_OR_NOT__ETC___d14252, NOT_specTagManager_canClaim__3651_3737_OR_NOT__ETC___d14319, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247, @@ -6424,8 +6435,9 @@ module mkCore(CLK, _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14173, _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14074, _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14265, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15017, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d14999, + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14631, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15028, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15010, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5284, @@ -6480,12 +6492,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h308937, - _theResult_____2__h314931, - _theResult_____2__h322785, - _theResult_____2__h333129, - _theResult_____2__h336354, - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956, + _theResult_____2__h308938, + _theResult_____2__h314932, + _theResult_____2__h322786, + _theResult_____2__h333130, + _theResult_____2__h336355, + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966, coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413, coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12454, coreFix_aluExe_0_bypassWire_1_wget__2424_BITS__ETC___d12426, @@ -6600,18 +6612,18 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3674, - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14958, + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14968, csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13280, csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13747, csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14036, - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019, - csrf_prv_reg_read__3022_ULE_1___d14997, + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030, + csrf_prv_reg_read__3022_ULE_1___d15008, csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275, csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13743, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13979, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14121, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14139, - f_csr_rsps_i_notFull__6101_AND_f_csr_reqs_firs_ETC___d16204, + f_csr_rsps_i_notFull__6114_AND_f_csr_reqs_firs_ETC___d16217, fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14323, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14263, fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345, @@ -6636,14 +6648,14 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14080, fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14218, fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14230, - guard__h368752, - guard__h414449, - guard__h460144, - guard__h508405, - guard__h547258, - guard__h586562, - idx__h693566, - k__h677209, + guard__h368753, + guard__h414450, + guard__h460145, + guard__h508406, + guard__h547259, + guard__h586563, + idx__h693568, + k__h677211, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6656,14 +6668,15 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14339, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h76121, - next_deqP___1__h309216, - next_deqP___1__h315497, - next_deqP___1__h323351, - next_deqP___1__h333408, - next_deqP___1__h336633, - r1__read_BIT_20___h663149, - regRenamingTable_RDY_rename_0_getRename__3536__ETC___d14186, + msip__h76122, + next_deqP___1__h309217, + next_deqP___1__h315498, + next_deqP___1__h323352, + next_deqP___1__h333409, + next_deqP___1__h336634, + r1__read_BIT_20___h663151, + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544, + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14186, regRenamingTable_RDY_rename_1_getRename__4249__ETC___d14267, regRenamingTable_rename_0_canRename__3653_AND__ETC___d13675, regRenamingTable_rename_0_canRename__3653_AND__ETC___d13724, @@ -6690,22 +6703,21 @@ module mkCore(CLK, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14044, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14085, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14165, - rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16040, - rob_RDY_deqPort_0_deq_data__4632_AND_rob_RDY_d_ETC___d15300, - rob_RDY_enqPort_0_enq__3014_AND_regRenamingTab_ETC___d13544, - tsr_val__h734794, - tvm_val__h734796, - v__h303706, - v__h304224, - v__h314220, - v__h314451, - v__h318096, - v__h318327, - v__h332697, - v__h332928, - v__h335922, - v__h336153, - x__h608477; + rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16053, + rob_RDY_deqPort_0_deq__4643_AND_rob_RDY_deqPor_ETC___d15310, + tsr_val__h735793, + tvm_val__h735795, + v__h303707, + v__h304225, + v__h314221, + v__h314452, + v__h318097, + v__h318328, + v__h332698, + v__h332929, + v__h335923, + v__h336154, + x__h608478; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6743,10 +6755,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16381 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16394 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6764,9 +6776,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16407 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q274, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16420 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -7053,7 +7065,7 @@ module mkCore(CLK, // actionvalue method v_to_TV_0_get assign v_to_TV_0_get = - { v_f_to_TV_0$D_OUT[784:476], + { v_f_to_TV_0$D_OUT[861:476], CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, v_f_to_TV_0$D_OUT[463:462], v_f_to_TV_0$D_OUT[462] ? @@ -7068,7 +7080,7 @@ module mkCore(CLK, // actionvalue method v_to_TV_1_get assign v_to_TV_1_get = - { v_f_to_TV_1$D_OUT[784:476], + { v_f_to_TV_1$D_OUT[861:476], CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, v_f_to_TV_1$D_OUT[463:462], v_f_to_TV_1$D_OUT[462] ? @@ -9872,7 +9884,7 @@ module mkCore(CLK, .RDY_isFull_ehrPort0()); // submodule v_f_to_TV_0 - FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N), .CLK(CLK), .D_IN(v_f_to_TV_0$D_IN), .ENQ(v_f_to_TV_0$ENQ), @@ -9883,7 +9895,7 @@ module mkCore(CLK, .EMPTY_N(v_f_to_TV_0$EMPTY_N)); // submodule v_f_to_TV_1 - FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N), .CLK(CLK), .D_IN(v_f_to_TV_1$D_IN), .ENQ(v_f_to_TV_1$ENQ), @@ -9899,32 +9911,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && - l2Tlb$RDY_toChildren_rsToC_deq && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && + l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9936,16 +9948,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9966,7 +9978,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16040 && + rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16053 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -10063,7 +10075,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__6101_AND_f_csr_reqs_firs_ETC___d16204 && + f_csr_rsps_i_notFull__6114_AND_f_csr_reqs_firs_ETC___d16217 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10083,9 +10095,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -10385,7 +10397,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && commitStage_f_rob_data$FULL_N && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && @@ -10426,27 +10438,17 @@ module mkCore(CLK, assign WILL_FIRE_RL_commitStage_rl_send_tv_reset = CAN_FIRE_RL_commitStage_rl_send_tv_reset ; - // rule RL_commitStage_doCommitTrap_handle - assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = - commitStage_f_rob_data$EMPTY_N && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14933 && - (commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || - coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14958) && - !commitStage_rg_run_state && - commitStage_commitTrap[165] ; - assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = - CAN_FIRE_RL_commitStage_doCommitTrap_handle && - !WILL_FIRE_RL_commitStage_rl_send_tv_reset && - !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - !WILL_FIRE_RL_renameStage_doRenaming_Trap && - !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_prepareCachesAndTlbs ; + // rule RL_commitStage_rl_send_mip_csr_change_to_tv + assign CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = + v_f_to_TV_0$FULL_N && !commitStage_rg_just_after_reset && + !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14631 ; + assign WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10479,20 +10481,29 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; + // rule RL_commitStage_doCommitTrap_handle + assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = + commitStage_f_rob_data$EMPTY_N && + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d14943 && + (commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || + coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14968) && + commitStage_commitTrap[165] && + !commitStage_rg_run_state && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14631 ; + assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = + CAN_FIRE_RL_commitStage_doCommitTrap_handle && + !WILL_FIRE_RL_commitStage_rl_send_tv_reset && + !WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + !WILL_FIRE_RL_renameStage_doRenaming_Trap && + !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && + !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && + !WILL_FIRE_RL_prepareCachesAndTlbs ; + // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq_data__4632_AND_rob_RDY_d_ETC___d15300 && - NOT_commitStage_rg_run_state_4641_4642_AND_NOT_ETC___d15306 && - (rob$deqPort_0_deq_data[329:325] == 5'd0 || - rob$deqPort_0_deq_data[329:325] == 5'd21 || - rob$deqPort_0_deq_data[329:325] == 5'd17 || - rob$deqPort_0_deq_data[329:325] == 5'd18 || - rob$deqPort_0_deq_data[329:325] == 5'd13 || - rob$deqPort_0_deq_data[329:325] == 5'd16 || - rob$deqPort_0_deq_data[329:325] == 5'd15 || - rob$deqPort_0_deq_data[329:325] == 5'd19 || - rob$deqPort_0_deq_data[329:325] == 5'd20) ; + rob_RDY_deqPort_0_deq__4643_AND_rob_RDY_deqPor_ETC___d15310 && + NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15327 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10526,17 +10537,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_RDY_ETC___d15665 && - NOT_commitStage_rg_run_state_4641_4642_AND_NOT_ETC___d15306 && - rob$deqPort_0_deq_data[329:325] != 5'd0 && - rob$deqPort_0_deq_data[329:325] != 5'd21 && - rob$deqPort_0_deq_data[329:325] != 5'd17 && - rob$deqPort_0_deq_data[329:325] != 5'd18 && - rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[329:325] != 5'd16 && - rob$deqPort_0_deq_data[329:325] != 5'd15 && - rob$deqPort_0_deq_data[329:325] != 5'd19 && - rob$deqPort_0_deq_data[329:325] != 5'd20 ; + NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_RDY_ETC___d15676 && + NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15688 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -10639,8 +10641,8 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$RDY_first ; assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu = CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -10651,8 +10653,8 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$RDY_first ; assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu = CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -10663,8 +10665,8 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ_RDY_first__1500_AN_ETC___d11591 ; assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu = CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -10675,32 +10677,32 @@ module mkCore(CLK, coreFix_aluExe_0_dispToRegQ_RDY_first__2388_AN_ETC___d12479 ; assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu = CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -10708,8 +10710,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10820,16 +10822,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -10853,8 +10855,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10872,8 +10874,8 @@ module mkCore(CLK, coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && @@ -10891,8 +10893,8 @@ module mkCore(CLK, coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue && @@ -10941,8 +10943,8 @@ module mkCore(CLK, coreFix_memExe_issueLd$whas ; assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate = CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ && @@ -10951,13 +10953,13 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10969,16 +10971,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || coreFix_memExe_stb$isEmpty) ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10988,19 +10990,21 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; - // rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq - assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = - !coreFix_memExe_respLrScAmoQ_empty && - rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; - assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = - CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && + // rule RL_coreFix_memExe_doDeqStQ_MMIO_deq + assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq = + !mmio_dataRespQ_empty && + NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 && + !coreFix_memExe_waitLrScAmoMMIOResp[0] && + mmio_dataRespQ_data_0[64] ; + assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq = + CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && @@ -11019,21 +11023,19 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; - // rule RL_coreFix_memExe_doDeqStQ_MMIO_deq - assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq = - !mmio_dataRespQ_empty && - NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 && - coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 && - !coreFix_memExe_waitLrScAmoMMIOResp[0] && - mmio_dataRespQ_data_0[64] ; - assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq = - CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + // rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq + assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = + !coreFix_memExe_respLrScAmoQ_empty && + rob$RDY_setExecuted_deqLSQ && + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && + coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; + assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = + CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && @@ -11065,8 +11067,8 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -11156,8 +11158,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -11167,8 +11169,8 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -11217,16 +11219,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush && + commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -11234,7 +11236,9 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_debug_resume = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -11242,20 +11246,20 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_RDY_enq__564_AND_core_ETC___d1654 ; assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem = CAN_FIRE_RL_coreFix_memExe_doRegReadMem && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -11264,7 +11268,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -11295,7 +11299,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q276 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -11427,10 +11431,6 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqStQ_data_0_canon assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ; @@ -11443,18 +11443,22 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqLdQ_full_canon assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLdQ_empty_canon - assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; - // rule RL_coreFix_memExe_reqLdQ_data_0_canon assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ; + // rule RL_coreFix_memExe_reqLdQ_empty_canon + assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ; + // rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq && @@ -11462,8 +11466,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d8545 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -11474,20 +11478,20 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first__2_ETC___d8399 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && - !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_commitStage_doCommitTrap_flush && + !WILL_FIRE_RL_commitStage_doCommitKilledLd && !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; @@ -11527,9 +11531,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13290 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11541,8 +11545,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__3014_AND_regRenamingTab_ETC___d13544 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13600 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11628,10 +11632,13 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 ; + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 ; + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 ; + assign MUX_commitStage_rg_serial_num$write_1__SEL_2 = + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || + WILL_FIRE_RL_commitStage_doCommitSystemInst ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -11640,7 +11647,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11823,9 +11831,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd9 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11833,9 +11841,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd16 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11844,20 +11852,20 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd29 ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5623_5624_OR__ETC___d15991 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__5634_5635_OR__ETC___d16004 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd0 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11866,22 +11874,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd1 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd0 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd1 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd2 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd8 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11893,9 +11901,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd8 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11905,21 +11913,21 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 ; + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 ; + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11933,7 +11941,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11941,7 +11949,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11955,7 +11963,7 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; @@ -11965,7 +11973,7 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11988,12 +11996,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd40 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd41 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12019,7 +12027,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12030,7 +12038,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12050,7 +12058,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -12068,7 +12076,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14470 && NOT_fetchStage_pipelines_1_first__3001_BITS_19_ETC___d14481 && IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14147 ; - assign MUX_flush_reservation$write_1__SEL_2 = + assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -12103,7 +12111,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[84] ; assign MUX_rg_core_run_state$write_1__SEL_4 = WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -12125,9 +12133,6 @@ module mkCore(CLK, assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 && coreFix_memExe_lsq$firstLd[89] ; - assign MUX_started$write_1__SEL_1 = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -12138,15 +12143,27 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h710207, - rob_deqPort_0_deq_data__4635_BIT_166_4651_CONC_ETC___d14700, + x__h711187, + rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h742215 ; + commitStage_rg_serial_num + y__h743250 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h677209 == 1'd0 && + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + (k__h677211 == 1'd0 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, @@ -12167,22 +12184,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693435, + renaming_spec_bits__h693437, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -12270,7 +12275,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2791, @@ -12284,10 +12289,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h290199 } ; + x__h290200 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h291644, + x__h291645, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12295,7 +12300,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h294420, + addr__h294421, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3042 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12308,12 +12313,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h155281, x__h155287, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h155282, x__h155288, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h158828, x__h158834, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h158829, x__h158835, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h161644, - x__h161648, + { x__h161645, + x__h161649, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, @@ -12324,7 +12329,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255, - x__h163496, + x__h163497, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, @@ -12337,7 +12342,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h296397, + resp_addr__h296398, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -12345,8 +12350,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h743905, - prv__h743905 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h744940, + prv__h744940 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12423,7 +12428,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h200591 } ; + x__h200592 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12458,8 +12463,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h195852 : - { {32{x__h196615[31]}}, x__h196615 } } ; + curData__h195853 : + { {32{x__h196616[31]}}, x__h196616 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12492,9 +12497,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h742192 ; + csrf_fflags_reg | fflags__h743227 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ; @@ -12502,10 +12507,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 or + always@(IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285) + case (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13]; @@ -12520,55 +12525,55 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd8 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h735179 + 64'd1 ; + n__read__h736179 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h735179 + { 62'd0, x__h742456 } ; + n__read__h736179 + { 62'd0, x__h743491 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 != + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 != 6'd8 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 != + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 != + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h730822 : + x__h731805 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h716927, + dcsr_cause__h717907, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12578,13 +12583,13 @@ module mkCore(CLK, amoExec___d882[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd8 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h746306 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h747341 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12593,12 +12598,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h730647 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h731630 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h730647; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h731630; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12610,7 +12615,7 @@ module mkCore(CLK, assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275, + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q277, mmio_dataReqQ_data_0[71:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, @@ -12633,24 +12638,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h342294 : - res_data__h342289 ; + res_data__h342295 : + res_data__h342290 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h387996 : - res_data__h387991 ; + res_data__h387997 : + res_data__h387992 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h433691 : - res_data__h433686 ; + res_data__h433692 : + res_data__h433687 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h479505 : - data__h478993 ; + data___1__h479506 : + data__h478994 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h480399 : - data__h479887 ; + data___1__h480400 : + data__h479888 ; assign MUX_rf$write_3_wr_2__VAL_4 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -12710,54 +12715,57 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q276 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q278 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q279 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h342290 ; + res_fflags__h342291 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h387992 ; + res_fflags__h387993 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h433687 ; + res_fflags__h433688 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, commitStage_f_rob_data$D_OUT[425:181], - CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278, - commitStage_f_rob_data$D_OUT[167:166], - commitStage_f_rob_data$D_OUT[166] ? - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 : - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280, - IF_commitStage_commitTrap_4643_BIT_36_4891_THE_ETC___d15228 } ; + CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q280, + commitStage_f_rob_data_first__5067_BIT_167_516_ETC___d15239 } ; assign MUX_v_f_to_TV_0$enq_1__VAL_2 = { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4635_BIT_181_4710_CONC_ETC___d14801, + rob_deqPort_0_deq_data__4646_BIT_181_4721_CONC_ETC___d14812, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4635_BIT_166_4651_CONC_ETC___d14700, + rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4635_BITS_97_TO_96__ETC___d14808, - fflags__h736831, + IF_rob_deqPort_0_deq_data__4646_BITS_97_TO_96__ETC___d14819, + fflags__h737833, rob$deqPort_0_deq_data[26], - x__h738459, + x__h739476, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, - x__h731276, + 13'd4932, + mip_csr__read__h617589, + 721'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign MUX_v_f_to_TV_0$enq_1__VAL_5 = + { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, + x__h732275, rob$deqPort_0_deq_data[361:182], - rob_deqPort_0_deq_data__4635_BIT_181_4710_CONC_ETC___d14801, + rob_deqPort_0_deq_data__4646_BIT_181_4721_CONC_ETC___d14812, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4635_BIT_166_4651_CONC_ETC___d14700, - rob$deqPort_0_deq_data[161:98], - IF_NOT_rob_deqPort_0_deq_data__4635_BITS_329_T_ETC___d15595 } ; + rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, + rob_deqPort_0_deq_data__4646_BITS_161_TO_98_46_ETC___d15606 } ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -13063,18 +13071,23 @@ module mkCore(CLK, assign commitStage_rg_just_after_reset$EN = CAN_FIRE_RL_commitStage_rl_send_tv_reset ; + // register commitStage_rg_old_mip_csr_val + assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h617589 ; + assign commitStage_rg_old_mip_csr_val$EN = + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; + // register commitStage_rg_run_state assign commitStage_rg_run_state$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serial_num always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_commitStage_rg_serial_num$write_1__VAL_1 or - WILL_FIRE_RL_commitStage_doCommitSystemInst or + MUX_commitStage_rg_serial_num$write_1__SEL_2 or WILL_FIRE_RL_commitStage_doCommitNormalInst or MUX_commitStage_rg_serial_num$write_1__VAL_3 or WILL_FIRE_RL_commitStage_rl_send_tv_reset) @@ -13083,7 +13096,7 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_1; - WILL_FIRE_RL_commitStage_doCommitSystemInst: + MUX_commitStage_rg_serial_num$write_1__SEL_2: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_1; WILL_FIRE_RL_commitStage_doCommitNormalInst: @@ -13097,7 +13110,8 @@ module mkCore(CLK, end assign commitStage_rg_serial_num$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 || + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst || WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -13125,8 +13139,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h610174 : - v__h609133 ; + v__h610175 : + v__h609134 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -13272,7 +13286,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h300941 ; + _theResult_____2__h300942 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -13294,7 +13308,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h300361 ; + v__h300362 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -13340,7 +13354,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3227 && - _theResult_____2__h308937 ; + _theResult_____2__h308938 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -13358,7 +13372,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3227 && - v__h303706 ; + v__h303707 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13458,7 +13472,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3398 && - _theResult_____2__h314931 ; + _theResult_____2__h314932 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13476,7 +13490,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3398 && - v__h314220 ; + v__h314221 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13497,7 +13511,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h318494, + { x_addr__h318495, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13527,7 +13541,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3494 && - _theResult_____2__h322785 ; + _theResult_____2__h322786 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13545,7 +13559,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3494 && - v__h318096 ; + v__h318097 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13622,7 +13636,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3817 && - _theResult_____2__h336354 ; + _theResult_____2__h336355 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13640,7 +13654,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3817 && - v__h335922 ; + v__h335923 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13683,7 +13697,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3723 && - _theResult_____2__h333129 ; + _theResult_____2__h333130 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13701,7 +13715,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3723 && - v__h332697 ; + v__h332698 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13881,7 +13895,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13930,7 +13944,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd29 || EN_setMEIP ; @@ -13952,12 +13966,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd0 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5623_5624_OR__ETC___d15991 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5634_5635_OR__ETC___d16004 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13970,9 +13984,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd1 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13994,7 +14008,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5623_5624_OR__ETC___d15991 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5634_5635_OR__ETC___d16004 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -14027,13 +14041,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -14049,24 +14063,24 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 ; + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h717408 or + cause_code__h718388 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h717408; + csrf_mcause_code_reg$D_IN = cause_code__h718388; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14075,11 +14089,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -14102,11 +14116,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -14119,7 +14133,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -14132,7 +14146,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -14145,7 +14159,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -14162,7 +14176,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd20 ; // register csrf_medeleg_15_reg @@ -14175,7 +14189,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -14188,7 +14202,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd20 ; // register csrf_mepc_csr @@ -14211,11 +14225,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd26 ; // register csrf_mideleg_11_reg @@ -14228,7 +14242,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -14241,7 +14255,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -14254,7 +14268,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -14267,7 +14281,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -14292,12 +14306,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 ; + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -14309,7 +14323,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18 ; // register csrf_mscratch_csr @@ -14322,19 +14336,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd25 ; // register csrf_mtval_csr always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h717409 or + trap_val__h718389 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h717409; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h718389; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14344,11 +14358,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -14361,7 +14375,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14374,7 +14388,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd23 ; // register csrf_mxr_reg @@ -14398,7 +14412,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14427,13 +14441,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -14450,34 +14464,34 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 ; + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h720451 or + x_prv__h721432 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h720451; + csrf_prv_reg$D_IN = x_prv__h721432; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -14497,12 +14511,12 @@ module mkCore(CLK, endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd40 ; // register csrf_rg_dpc @@ -14521,12 +14535,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd41 ; // register csrf_rg_dscratch0 @@ -14539,7 +14553,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd42 ; // register csrf_rg_dscratch1 @@ -14552,7 +14566,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd43 ; // register csrf_rg_tdata1_data @@ -14565,7 +14579,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd37 ; // register csrf_rg_tdata1_dmode @@ -14578,7 +14592,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd37 ; // register csrf_rg_tdata2 @@ -14591,7 +14605,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd38 ; // register csrf_rg_tdata3 @@ -14604,7 +14618,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd39 ; // register csrf_rg_tselect @@ -14617,20 +14631,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd36 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h717408 or + cause_code__h718388 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h717408; + csrf_scause_code_reg$D_IN = cause_code__h718388; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14639,11 +14653,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14666,11 +14680,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14683,7 +14697,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14696,7 +14710,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14709,7 +14723,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd11 ; // register csrf_sepc_csr @@ -14732,11 +14746,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14764,7 +14778,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14808,7 +14822,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd29 ; // register csrf_spp_reg @@ -14825,13 +14839,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14843,7 +14857,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd12 ; // register csrf_stats_module_doStats @@ -14854,12 +14868,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h717409 or + trap_val__h718389 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h717409; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h718389; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14869,11 +14883,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 && - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 && + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14886,7 +14900,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14899,7 +14913,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd10 ; // register csrf_sum_reg @@ -14942,7 +14956,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14976,7 +14990,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18 ; // register csrf_tvm_reg @@ -14989,7 +15003,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18 ; // register csrf_tw_reg @@ -15002,7 +15016,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -15015,28 +15029,28 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -15044,11 +15058,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[329:325] == 5'd16 || rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -15057,7 +15071,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46291, + { x__h46292, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15069,7 +15083,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48827 } ; + x__h48828 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -15162,7 +15176,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18384, + { x__h18385, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15174,7 +15188,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20922 } ; + x__h20923 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -15258,7 +15272,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h66085 } ; + x_data__h66086 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -15381,18 +15395,18 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data assign commitStage_f_rob_data$D_IN = { rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4635_BIT_181_4710_CONC_ETC___d14801, + rob_deqPort_0_deq_data__4646_BIT_181_4721_CONC_ETC___d14812, rob$deqPort_0_deq_data[168:167], - rob_deqPort_0_deq_data__4635_BIT_166_4651_CONC_ETC___d14700, + rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4635_BITS_97_TO_96__ETC___d14808, + IF_rob_deqPort_0_deq_data__4646_BITS_97_TO_96__ETC___d14819, rob$deqPort_0_deq_data[31:0] } ; assign commitStage_f_rob_data$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_flush ; @@ -15501,8 +15515,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q287, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h646648, - x__h646649, + x__h646650, + x__h646651, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -15640,9 +15654,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -15792,8 +15806,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q293, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h623641, - x__h623642, + x__h623643, + x__h623644, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -15835,7 +15849,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h677209 == 1'd1 && + (k__h677211 == 1'd1 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, @@ -15856,7 +15870,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693435, + renaming_spec_bits__h693437, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16334,12 +16348,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h608451, - b__h607915 == 64'd0, - a__h607914, + { x__h608452, + b__h607916 == 64'd0, + a__h607915, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h608477, - a__h607914[63], + x__h608478, + a__h607915[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -16354,8 +16368,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h608463 : - b__h607915 ; + _theResult___snd__h608464 : + b__h607916 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -16368,7 +16382,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h609063, + { x__h609064, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -16449,9 +16463,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h486590, x__h486591, x__h486592, + x__h486593, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12933 ; @@ -16503,7 +16517,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13829, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693435, + renaming_spec_bits__h693437, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16661,8 +16675,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h291632, - x__h291644, + { x__h291633, + x__h291645, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2890, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2894, @@ -16673,13 +16687,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2920, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2925, - x__h293498, + x__h293499, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2933, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2945 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h290199 ; + x__h290200 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -16902,7 +16916,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN = 1'd1 ; assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN = - MUX_flush_reservation$write_1__SEL_2 ; + MUX_flush_reservation$write_1__SEL_1 ; // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = @@ -17473,7 +17487,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3653_AND__ETC___d14414) ? specTagManager$currentSpecBits : - renaming_spec_bits__h693435 ; + renaming_spec_bits__h693437 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3653_AND__ETC___d14422) ? @@ -17493,7 +17507,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3653_AND__ETC___d14422) ? specTagManager$currentSpecBits : - renaming_spec_bits__h693435 ; + renaming_spec_bits__h693437 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17573,7 +17587,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h184459 ; + shiftData__h184460 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17673,8 +17687,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h184366, x__h184367, + x__h184368, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12933 ; @@ -17938,7 +17952,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14560, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693435, + renaming_spec_bits__h693437, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -18166,7 +18180,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -18180,7 +18194,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -18198,7 +18212,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -18209,7 +18223,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -18386,7 +18400,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h720352 or + pc__h721332 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18400,7 +18414,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h720352; + fetchStage$redirect_pc = pc__h721332; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18499,14 +18513,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18820,7 +18834,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h693435 ; + renaming_spec_bits__h693437 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -19092,7 +19106,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14554, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14613, 7'd32, - renaming_spec_bits__h693435 } ; + renaming_spec_bits__h693437 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -19102,24 +19116,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -19407,16 +19421,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -19709,8 +19723,10 @@ module mkCore(CLK, MUX_v_f_to_TV_0$enq_1__SEL_2 or MUX_v_f_to_TV_0$enq_1__VAL_2 or WILL_FIRE_RL_commitStage_rl_send_tv_reset or + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv or + MUX_v_f_to_TV_0$enq_1__VAL_4 or WILL_FIRE_RL_commitStage_doCommitSystemInst or - MUX_v_f_to_TV_0$enq_1__VAL_4) + MUX_v_f_to_TV_0$enq_1__VAL_5) begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: @@ -19719,35 +19735,39 @@ module mkCore(CLK, v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_2; WILL_FIRE_RL_commitStage_rl_send_tv_reset: v_f_to_TV_0$D_IN = - 785'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_commitStage_doCommitSystemInst: + 862'h000000000000000015555555555555555554AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv: v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_4; + WILL_FIRE_RL_commitStage_doCommitSystemInst: + v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_5; default: v_f_to_TV_0$D_IN = - 785'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 862'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign v_f_to_TV_0$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 || WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq || WILL_FIRE_RL_commitStage_rl_send_tv_reset || + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst ; assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ; assign v_f_to_TV_0$CLR = 1'b0 ; // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { commitStage_rg_serial_num_4820_PLUS_IF_rob_deq_ETC___d15758, + { commitStage_rg_serial_num_4635_PLUS_IF_rob_deq_ETC___d15770, + 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_1_deq_data[425:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q301, 6'd10, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302, rob$deqPort_1_deq_data[95:32], - fflags__h739527, + fflags__h740546, rob$deqPort_1_deq_data[26], - x__h741647, + x__h742681, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19769,33 +19789,21 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h195852), + .amoExec_current_data(curData__h195853), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h197390)); + .amoExec(n__h197391)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h76121 }), - .amoExec_in_data({ 32'd0, x__h76236 }), + msip__h76122 }), + .amoExec_in_data({ 32'd0, x__h76237 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d882)); - module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228, - { coreFix_aluExe_0_regToExeQ$first[395], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229, - coreFix_aluExe_0_regToExeQ$first[382], - coreFix_aluExe_0_regToExeQ$first[381:350] } }), - .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), - .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), - .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), - .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), - .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12839)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, { coreFix_aluExe_1_regToExeQ$first[395], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, coreFix_aluExe_1_regToExeQ$first[382], coreFix_aluExe_1_regToExeQ$first[381:350] } }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]), @@ -19804,12 +19812,24 @@ module mkCore(CLK, .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), .basicExec(basicExec___d12137)); + module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, + { coreFix_aluExe_0_regToExeQ$first[395], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, + coreFix_aluExe_0_regToExeQ$first[382], + coreFix_aluExe_0_regToExeQ$first[381:350] } }), + .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), + .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), + .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), + .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), + .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), + .basicExec(basicExec___d12839)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208 }, fetchStage$pipelines_0_first[160], - x_data_imm__h684503 } }), + x_data_imm__h684505 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19818,13 +19838,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h662268, - r1__read_BITS_13_TO_12___h662453 != + .checkForException_csrState({ x_decodeInfo_frm__h662270, + r1__read_BITS_13_TO_12___h662455 != 2'd0, - { prv__h743861, - tvm_val__h734796, - { r1__read_BIT_20___h663149, - tsr_val__h734794, + { prv__h744896, + tvm_val__h735795, + { r1__read_BIT_20___h663151, + tsr_val__h735793, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19839,7 +19859,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13829, { fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13921, fetchStage$pipelines_1_first[160], - x_data_imm__h701169 } }), + x_data_imm__h701171 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19848,13 +19868,13 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h662268, - r1__read_BITS_13_TO_12___h662453 != + .checkForException_csrState({ x_decodeInfo_frm__h662270, + r1__read_BITS_13_TO_12___h662455 != 2'd0, - { prv__h743861, - tvm_val__h734796, - { r1__read_BIT_20___h663149, - tsr_val__h734794, + { prv__h744896, + tvm_val__h735795, + { r1__read_BIT_20___h663151, + tsr_val__h735793, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19866,1198 +19886,1198 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13943)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q255, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h486684), - .execFpuSimple_rVal2(rVal2__h486685), + .execFpuSimple_rVal1(rVal1__h486685), + .execFpuSimple_rVal2(rVal2__h486686), .execFpuSimple(execFpuSimple___d11171)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4349 ? - _theResult___snd__h358679 : - _theResult____h350505 ; + _theResult___snd__h358680 : + _theResult____h350506 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5741 ? - _theResult___snd__h404376 : - _theResult____h396204 ; + _theResult___snd__h404377 : + _theResult____h396205 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7133 ? - _theResult___snd__h450071 : - _theResult____h441899 ; + _theResult___snd__h450072 : + _theResult____h441900 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9012 ? - _theResult___snd__h516096 : - _theResult____h507797 ; + _theResult___snd__h516097 : + _theResult____h507798 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9727 ? - _theResult___snd__h594253 : - _theResult____h585954 ; + _theResult___snd__h594254 : + _theResult____h585955 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10497 ? - _theResult___snd__h554949 : - _theResult____h546650 ; + _theResult___snd__h554950 : + _theResult____h546651 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7684 ? - _theResult___snd__h467837 : - _theResult____h459536 ; + _theResult___snd__h467838 : + _theResult____h459537 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4900 ? - _theResult___snd__h376445 : - _theResult____h368144 ; + _theResult___snd__h376446 : + _theResult____h368145 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6292 ? - _theResult___snd__h422142 : - _theResult____h413841 ; + _theResult___snd__h422143 : + _theResult____h413842 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8700 ? - _theResult___snd__h506445 : + _theResult___snd__h506446 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9062 ? - _theResult___snd__h506445 : - _theResult___snd__h524850 ; + _theResult___snd__h506446 : + _theResult___snd__h524851 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9430 ? - _theResult___snd__h584602 : + _theResult___snd__h584603 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9777 ? - _theResult___snd__h584602 : - _theResult___snd__h603007 ; + _theResult___snd__h584603 : + _theResult___snd__h603008 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10200 ? - _theResult___snd__h545298 : + _theResult___snd__h545299 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10547 ? - _theResult___snd__h545298 : - _theResult___snd__h563703 ; + _theResult___snd__h545299 : + _theResult___snd__h563704 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7364 ? - _theResult___snd__h458653 : + _theResult___snd__h458654 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7757 ? - _theResult___snd__h458653 : - _theResult___snd__h476443 ; + _theResult___snd__h458654 : + _theResult___snd__h476444 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4580 ? - _theResult___snd__h367261 : + _theResult___snd__h367262 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4973 ? - _theResult___snd__h367261 : - _theResult___snd__h385051 ; + _theResult___snd__h367262 : + _theResult___snd__h385052 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5972 ? - _theResult___snd__h412958 : + _theResult___snd__h412959 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6365 ? - _theResult___snd__h412958 : - _theResult___snd__h430748 ; + _theResult___snd__h412959 : + _theResult___snd__h430749 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5169 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - ((_theResult___fst_exp__h358616 == 8'd255) ? + ((_theResult___fst_exp__h358617 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154) : - ((_theResult___fst_exp__h367272 == 8'd255) ? + ((_theResult___fst_exp__h367273 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5219 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - ((_theResult___fst_exp__h358616 == 8'd255) ? + ((_theResult___fst_exp__h358617 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210) : - ((_theResult___fst_exp__h367272 == 8'd255) ? + ((_theResult___fst_exp__h367273 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6561 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - ((_theResult___fst_exp__h404313 == 8'd255) ? + ((_theResult___fst_exp__h404314 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546) : - ((_theResult___fst_exp__h412969 == 8'd255) ? + ((_theResult___fst_exp__h412970 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6611 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - ((_theResult___fst_exp__h404313 == 8'd255) ? + ((_theResult___fst_exp__h404314 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602) : - ((_theResult___fst_exp__h412969 == 8'd255) ? + ((_theResult___fst_exp__h412970 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7953 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - ((_theResult___fst_exp__h450008 == 8'd255) ? + ((_theResult___fst_exp__h450009 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938) : - ((_theResult___fst_exp__h458664 == 8'd255) ? + ((_theResult___fst_exp__h458665 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d8003 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - ((_theResult___fst_exp__h450008 == 8'd255) ? + ((_theResult___fst_exp__h450009 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994) : - ((_theResult___fst_exp__h458664 == 8'd255) ? + ((_theResult___fst_exp__h458665 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347 = - (_theResult____h350505[56] ? + (_theResult____h350506[56] ? 6'd0 : - (_theResult____h350505[55] ? + (_theResult____h350506[55] ? 6'd1 : - (_theResult____h350505[54] ? + (_theResult____h350506[54] ? 6'd2 : - (_theResult____h350505[53] ? + (_theResult____h350506[53] ? 6'd3 : - (_theResult____h350505[52] ? + (_theResult____h350506[52] ? 6'd4 : - (_theResult____h350505[51] ? + (_theResult____h350506[51] ? 6'd5 : - (_theResult____h350505[50] ? + (_theResult____h350506[50] ? 6'd6 : - (_theResult____h350505[49] ? + (_theResult____h350506[49] ? 6'd7 : - (_theResult____h350505[48] ? + (_theResult____h350506[48] ? 6'd8 : - (_theResult____h350505[47] ? + (_theResult____h350506[47] ? 6'd9 : - (_theResult____h350505[46] ? + (_theResult____h350506[46] ? 6'd10 : - (_theResult____h350505[45] ? + (_theResult____h350506[45] ? 6'd11 : - (_theResult____h350505[44] ? + (_theResult____h350506[44] ? 6'd12 : - (_theResult____h350505[43] ? + (_theResult____h350506[43] ? 6'd13 : - (_theResult____h350505[42] ? + (_theResult____h350506[42] ? 6'd14 : - (_theResult____h350505[41] ? + (_theResult____h350506[41] ? 6'd15 : - (_theResult____h350505[40] ? + (_theResult____h350506[40] ? 6'd16 : - (_theResult____h350505[39] ? + (_theResult____h350506[39] ? 6'd17 : - (_theResult____h350505[38] ? + (_theResult____h350506[38] ? 6'd18 : - (_theResult____h350505[37] ? + (_theResult____h350506[37] ? 6'd19 : - (_theResult____h350505[36] ? + (_theResult____h350506[36] ? 6'd20 : - (_theResult____h350505[35] ? + (_theResult____h350506[35] ? 6'd21 : - (_theResult____h350505[34] ? + (_theResult____h350506[34] ? 6'd22 : - (_theResult____h350505[33] ? + (_theResult____h350506[33] ? 6'd23 : - (_theResult____h350505[32] ? + (_theResult____h350506[32] ? 6'd24 : - (_theResult____h350505[31] ? + (_theResult____h350506[31] ? 6'd25 : - (_theResult____h350505[30] ? + (_theResult____h350506[30] ? 6'd26 : - (_theResult____h350505[29] ? + (_theResult____h350506[29] ? 6'd27 : - (_theResult____h350505[28] ? + (_theResult____h350506[28] ? 6'd28 : - (_theResult____h350505[27] ? + (_theResult____h350506[27] ? 6'd29 : - (_theResult____h350505[26] ? + (_theResult____h350506[26] ? 6'd30 : - (_theResult____h350505[25] ? + (_theResult____h350506[25] ? 6'd31 : - (_theResult____h350505[24] ? + (_theResult____h350506[24] ? 6'd32 : - (_theResult____h350505[23] ? + (_theResult____h350506[23] ? 6'd33 : - (_theResult____h350505[22] ? + (_theResult____h350506[22] ? 6'd34 : - (_theResult____h350505[21] ? + (_theResult____h350506[21] ? 6'd35 : - (_theResult____h350505[20] ? + (_theResult____h350506[20] ? 6'd36 : - (_theResult____h350505[19] ? + (_theResult____h350506[19] ? 6'd37 : - (_theResult____h350505[18] ? + (_theResult____h350506[18] ? 6'd38 : - (_theResult____h350505[17] ? + (_theResult____h350506[17] ? 6'd39 : - (_theResult____h350505[16] ? + (_theResult____h350506[16] ? 6'd40 : - (_theResult____h350505[15] ? + (_theResult____h350506[15] ? 6'd41 : - (_theResult____h350505[14] ? + (_theResult____h350506[14] ? 6'd42 : - (_theResult____h350505[13] ? + (_theResult____h350506[13] ? 6'd43 : - (_theResult____h350505[12] ? + (_theResult____h350506[12] ? 6'd44 : - (_theResult____h350505[11] ? + (_theResult____h350506[11] ? 6'd45 : - (_theResult____h350505[10] ? + (_theResult____h350506[10] ? 6'd46 : - (_theResult____h350505[9] ? + (_theResult____h350506[9] ? 6'd47 : - (_theResult____h350505[8] ? + (_theResult____h350506[8] ? 6'd48 : - (_theResult____h350505[7] ? + (_theResult____h350506[7] ? 6'd49 : - (_theResult____h350505[6] ? + (_theResult____h350506[6] ? 6'd50 : - (_theResult____h350505[5] ? + (_theResult____h350506[5] ? 6'd51 : - (_theResult____h350505[4] ? + (_theResult____h350506[4] ? 6'd52 : - (_theResult____h350505[3] ? + (_theResult____h350506[3] ? 6'd53 : - (_theResult____h350505[2] ? + (_theResult____h350506[2] ? 6'd54 : - (_theResult____h350505[1] ? + (_theResult____h350506[1] ? 6'd55 : - (_theResult____h350505[0] ? + (_theResult____h350506[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 = - (_theResult____h396204[56] ? + (_theResult____h396205[56] ? 6'd0 : - (_theResult____h396204[55] ? + (_theResult____h396205[55] ? 6'd1 : - (_theResult____h396204[54] ? + (_theResult____h396205[54] ? 6'd2 : - (_theResult____h396204[53] ? + (_theResult____h396205[53] ? 6'd3 : - (_theResult____h396204[52] ? + (_theResult____h396205[52] ? 6'd4 : - (_theResult____h396204[51] ? + (_theResult____h396205[51] ? 6'd5 : - (_theResult____h396204[50] ? + (_theResult____h396205[50] ? 6'd6 : - (_theResult____h396204[49] ? + (_theResult____h396205[49] ? 6'd7 : - (_theResult____h396204[48] ? + (_theResult____h396205[48] ? 6'd8 : - (_theResult____h396204[47] ? + (_theResult____h396205[47] ? 6'd9 : - (_theResult____h396204[46] ? + (_theResult____h396205[46] ? 6'd10 : - (_theResult____h396204[45] ? + (_theResult____h396205[45] ? 6'd11 : - (_theResult____h396204[44] ? + (_theResult____h396205[44] ? 6'd12 : - (_theResult____h396204[43] ? + (_theResult____h396205[43] ? 6'd13 : - (_theResult____h396204[42] ? + (_theResult____h396205[42] ? 6'd14 : - (_theResult____h396204[41] ? + (_theResult____h396205[41] ? 6'd15 : - (_theResult____h396204[40] ? + (_theResult____h396205[40] ? 6'd16 : - (_theResult____h396204[39] ? + (_theResult____h396205[39] ? 6'd17 : - (_theResult____h396204[38] ? + (_theResult____h396205[38] ? 6'd18 : - (_theResult____h396204[37] ? + (_theResult____h396205[37] ? 6'd19 : - (_theResult____h396204[36] ? + (_theResult____h396205[36] ? 6'd20 : - (_theResult____h396204[35] ? + (_theResult____h396205[35] ? 6'd21 : - (_theResult____h396204[34] ? + (_theResult____h396205[34] ? 6'd22 : - (_theResult____h396204[33] ? + (_theResult____h396205[33] ? 6'd23 : - (_theResult____h396204[32] ? + (_theResult____h396205[32] ? 6'd24 : - (_theResult____h396204[31] ? + (_theResult____h396205[31] ? 6'd25 : - (_theResult____h396204[30] ? + (_theResult____h396205[30] ? 6'd26 : - (_theResult____h396204[29] ? + (_theResult____h396205[29] ? 6'd27 : - (_theResult____h396204[28] ? + (_theResult____h396205[28] ? 6'd28 : - (_theResult____h396204[27] ? + (_theResult____h396205[27] ? 6'd29 : - (_theResult____h396204[26] ? + (_theResult____h396205[26] ? 6'd30 : - (_theResult____h396204[25] ? + (_theResult____h396205[25] ? 6'd31 : - (_theResult____h396204[24] ? + (_theResult____h396205[24] ? 6'd32 : - (_theResult____h396204[23] ? + (_theResult____h396205[23] ? 6'd33 : - (_theResult____h396204[22] ? + (_theResult____h396205[22] ? 6'd34 : - (_theResult____h396204[21] ? + (_theResult____h396205[21] ? 6'd35 : - (_theResult____h396204[20] ? + (_theResult____h396205[20] ? 6'd36 : - (_theResult____h396204[19] ? + (_theResult____h396205[19] ? 6'd37 : - (_theResult____h396204[18] ? + (_theResult____h396205[18] ? 6'd38 : - (_theResult____h396204[17] ? + (_theResult____h396205[17] ? 6'd39 : - (_theResult____h396204[16] ? + (_theResult____h396205[16] ? 6'd40 : - (_theResult____h396204[15] ? + (_theResult____h396205[15] ? 6'd41 : - (_theResult____h396204[14] ? + (_theResult____h396205[14] ? 6'd42 : - (_theResult____h396204[13] ? + (_theResult____h396205[13] ? 6'd43 : - (_theResult____h396204[12] ? + (_theResult____h396205[12] ? 6'd44 : - (_theResult____h396204[11] ? + (_theResult____h396205[11] ? 6'd45 : - (_theResult____h396204[10] ? + (_theResult____h396205[10] ? 6'd46 : - (_theResult____h396204[9] ? + (_theResult____h396205[9] ? 6'd47 : - (_theResult____h396204[8] ? + (_theResult____h396205[8] ? 6'd48 : - (_theResult____h396204[7] ? + (_theResult____h396205[7] ? 6'd49 : - (_theResult____h396204[6] ? + (_theResult____h396205[6] ? 6'd50 : - (_theResult____h396204[5] ? + (_theResult____h396205[5] ? 6'd51 : - (_theResult____h396204[4] ? + (_theResult____h396205[4] ? 6'd52 : - (_theResult____h396204[3] ? + (_theResult____h396205[3] ? 6'd53 : - (_theResult____h396204[2] ? + (_theResult____h396205[2] ? 6'd54 : - (_theResult____h396204[1] ? + (_theResult____h396205[1] ? 6'd55 : - (_theResult____h396204[0] ? + (_theResult____h396205[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 = - (_theResult____h441899[56] ? + (_theResult____h441900[56] ? 6'd0 : - (_theResult____h441899[55] ? + (_theResult____h441900[55] ? 6'd1 : - (_theResult____h441899[54] ? + (_theResult____h441900[54] ? 6'd2 : - (_theResult____h441899[53] ? + (_theResult____h441900[53] ? 6'd3 : - (_theResult____h441899[52] ? + (_theResult____h441900[52] ? 6'd4 : - (_theResult____h441899[51] ? + (_theResult____h441900[51] ? 6'd5 : - (_theResult____h441899[50] ? + (_theResult____h441900[50] ? 6'd6 : - (_theResult____h441899[49] ? + (_theResult____h441900[49] ? 6'd7 : - (_theResult____h441899[48] ? + (_theResult____h441900[48] ? 6'd8 : - (_theResult____h441899[47] ? + (_theResult____h441900[47] ? 6'd9 : - (_theResult____h441899[46] ? + (_theResult____h441900[46] ? 6'd10 : - (_theResult____h441899[45] ? + (_theResult____h441900[45] ? 6'd11 : - (_theResult____h441899[44] ? + (_theResult____h441900[44] ? 6'd12 : - (_theResult____h441899[43] ? + (_theResult____h441900[43] ? 6'd13 : - (_theResult____h441899[42] ? + (_theResult____h441900[42] ? 6'd14 : - (_theResult____h441899[41] ? + (_theResult____h441900[41] ? 6'd15 : - (_theResult____h441899[40] ? + (_theResult____h441900[40] ? 6'd16 : - (_theResult____h441899[39] ? + (_theResult____h441900[39] ? 6'd17 : - (_theResult____h441899[38] ? + (_theResult____h441900[38] ? 6'd18 : - (_theResult____h441899[37] ? + (_theResult____h441900[37] ? 6'd19 : - (_theResult____h441899[36] ? + (_theResult____h441900[36] ? 6'd20 : - (_theResult____h441899[35] ? + (_theResult____h441900[35] ? 6'd21 : - (_theResult____h441899[34] ? + (_theResult____h441900[34] ? 6'd22 : - (_theResult____h441899[33] ? + (_theResult____h441900[33] ? 6'd23 : - (_theResult____h441899[32] ? + (_theResult____h441900[32] ? 6'd24 : - (_theResult____h441899[31] ? + (_theResult____h441900[31] ? 6'd25 : - (_theResult____h441899[30] ? + (_theResult____h441900[30] ? 6'd26 : - (_theResult____h441899[29] ? + (_theResult____h441900[29] ? 6'd27 : - (_theResult____h441899[28] ? + (_theResult____h441900[28] ? 6'd28 : - (_theResult____h441899[27] ? + (_theResult____h441900[27] ? 6'd29 : - (_theResult____h441899[26] ? + (_theResult____h441900[26] ? 6'd30 : - (_theResult____h441899[25] ? + (_theResult____h441900[25] ? 6'd31 : - (_theResult____h441899[24] ? + (_theResult____h441900[24] ? 6'd32 : - (_theResult____h441899[23] ? + (_theResult____h441900[23] ? 6'd33 : - (_theResult____h441899[22] ? + (_theResult____h441900[22] ? 6'd34 : - (_theResult____h441899[21] ? + (_theResult____h441900[21] ? 6'd35 : - (_theResult____h441899[20] ? + (_theResult____h441900[20] ? 6'd36 : - (_theResult____h441899[19] ? + (_theResult____h441900[19] ? 6'd37 : - (_theResult____h441899[18] ? + (_theResult____h441900[18] ? 6'd38 : - (_theResult____h441899[17] ? + (_theResult____h441900[17] ? 6'd39 : - (_theResult____h441899[16] ? + (_theResult____h441900[16] ? 6'd40 : - (_theResult____h441899[15] ? + (_theResult____h441900[15] ? 6'd41 : - (_theResult____h441899[14] ? + (_theResult____h441900[14] ? 6'd42 : - (_theResult____h441899[13] ? + (_theResult____h441900[13] ? 6'd43 : - (_theResult____h441899[12] ? + (_theResult____h441900[12] ? 6'd44 : - (_theResult____h441899[11] ? + (_theResult____h441900[11] ? 6'd45 : - (_theResult____h441899[10] ? + (_theResult____h441900[10] ? 6'd46 : - (_theResult____h441899[9] ? + (_theResult____h441900[9] ? 6'd47 : - (_theResult____h441899[8] ? + (_theResult____h441900[8] ? 6'd48 : - (_theResult____h441899[7] ? + (_theResult____h441900[7] ? 6'd49 : - (_theResult____h441899[6] ? + (_theResult____h441900[6] ? 6'd50 : - (_theResult____h441899[5] ? + (_theResult____h441900[5] ? 6'd51 : - (_theResult____h441899[4] ? + (_theResult____h441900[4] ? 6'd52 : - (_theResult____h441899[3] ? + (_theResult____h441900[3] ? 6'd53 : - (_theResult____h441899[2] ? + (_theResult____h441900[2] ? 6'd54 : - (_theResult____h441899[1] ? + (_theResult____h441900[1] ? 6'd55 : - (_theResult____h441899[0] ? + (_theResult____h441900[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 = - (_theResult____h546650[56] ? + (_theResult____h546651[56] ? 6'd0 : - (_theResult____h546650[55] ? + (_theResult____h546651[55] ? 6'd1 : - (_theResult____h546650[54] ? + (_theResult____h546651[54] ? 6'd2 : - (_theResult____h546650[53] ? + (_theResult____h546651[53] ? 6'd3 : - (_theResult____h546650[52] ? + (_theResult____h546651[52] ? 6'd4 : - (_theResult____h546650[51] ? + (_theResult____h546651[51] ? 6'd5 : - (_theResult____h546650[50] ? + (_theResult____h546651[50] ? 6'd6 : - (_theResult____h546650[49] ? + (_theResult____h546651[49] ? 6'd7 : - (_theResult____h546650[48] ? + (_theResult____h546651[48] ? 6'd8 : - (_theResult____h546650[47] ? + (_theResult____h546651[47] ? 6'd9 : - (_theResult____h546650[46] ? + (_theResult____h546651[46] ? 6'd10 : - (_theResult____h546650[45] ? + (_theResult____h546651[45] ? 6'd11 : - (_theResult____h546650[44] ? + (_theResult____h546651[44] ? 6'd12 : - (_theResult____h546650[43] ? + (_theResult____h546651[43] ? 6'd13 : - (_theResult____h546650[42] ? + (_theResult____h546651[42] ? 6'd14 : - (_theResult____h546650[41] ? + (_theResult____h546651[41] ? 6'd15 : - (_theResult____h546650[40] ? + (_theResult____h546651[40] ? 6'd16 : - (_theResult____h546650[39] ? + (_theResult____h546651[39] ? 6'd17 : - (_theResult____h546650[38] ? + (_theResult____h546651[38] ? 6'd18 : - (_theResult____h546650[37] ? + (_theResult____h546651[37] ? 6'd19 : - (_theResult____h546650[36] ? + (_theResult____h546651[36] ? 6'd20 : - (_theResult____h546650[35] ? + (_theResult____h546651[35] ? 6'd21 : - (_theResult____h546650[34] ? + (_theResult____h546651[34] ? 6'd22 : - (_theResult____h546650[33] ? + (_theResult____h546651[33] ? 6'd23 : - (_theResult____h546650[32] ? + (_theResult____h546651[32] ? 6'd24 : - (_theResult____h546650[31] ? + (_theResult____h546651[31] ? 6'd25 : - (_theResult____h546650[30] ? + (_theResult____h546651[30] ? 6'd26 : - (_theResult____h546650[29] ? + (_theResult____h546651[29] ? 6'd27 : - (_theResult____h546650[28] ? + (_theResult____h546651[28] ? 6'd28 : - (_theResult____h546650[27] ? + (_theResult____h546651[27] ? 6'd29 : - (_theResult____h546650[26] ? + (_theResult____h546651[26] ? 6'd30 : - (_theResult____h546650[25] ? + (_theResult____h546651[25] ? 6'd31 : - (_theResult____h546650[24] ? + (_theResult____h546651[24] ? 6'd32 : - (_theResult____h546650[23] ? + (_theResult____h546651[23] ? 6'd33 : - (_theResult____h546650[22] ? + (_theResult____h546651[22] ? 6'd34 : - (_theResult____h546650[21] ? + (_theResult____h546651[21] ? 6'd35 : - (_theResult____h546650[20] ? + (_theResult____h546651[20] ? 6'd36 : - (_theResult____h546650[19] ? + (_theResult____h546651[19] ? 6'd37 : - (_theResult____h546650[18] ? + (_theResult____h546651[18] ? 6'd38 : - (_theResult____h546650[17] ? + (_theResult____h546651[17] ? 6'd39 : - (_theResult____h546650[16] ? + (_theResult____h546651[16] ? 6'd40 : - (_theResult____h546650[15] ? + (_theResult____h546651[15] ? 6'd41 : - (_theResult____h546650[14] ? + (_theResult____h546651[14] ? 6'd42 : - (_theResult____h546650[13] ? + (_theResult____h546651[13] ? 6'd43 : - (_theResult____h546650[12] ? + (_theResult____h546651[12] ? 6'd44 : - (_theResult____h546650[11] ? + (_theResult____h546651[11] ? 6'd45 : - (_theResult____h546650[10] ? + (_theResult____h546651[10] ? 6'd46 : - (_theResult____h546650[9] ? + (_theResult____h546651[9] ? 6'd47 : - (_theResult____h546650[8] ? + (_theResult____h546651[8] ? 6'd48 : - (_theResult____h546650[7] ? + (_theResult____h546651[7] ? 6'd49 : - (_theResult____h546650[6] ? + (_theResult____h546651[6] ? 6'd50 : - (_theResult____h546650[5] ? + (_theResult____h546651[5] ? 6'd51 : - (_theResult____h546650[4] ? + (_theResult____h546651[4] ? 6'd52 : - (_theResult____h546650[3] ? + (_theResult____h546651[3] ? 6'd53 : - (_theResult____h546650[2] ? + (_theResult____h546651[2] ? 6'd54 : - (_theResult____h546650[1] ? + (_theResult____h546651[1] ? 6'd55 : - (_theResult____h546650[0] ? + (_theResult____h546651[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 = - (_theResult____h507797[56] ? + (_theResult____h507798[56] ? 6'd0 : - (_theResult____h507797[55] ? + (_theResult____h507798[55] ? 6'd1 : - (_theResult____h507797[54] ? + (_theResult____h507798[54] ? 6'd2 : - (_theResult____h507797[53] ? + (_theResult____h507798[53] ? 6'd3 : - (_theResult____h507797[52] ? + (_theResult____h507798[52] ? 6'd4 : - (_theResult____h507797[51] ? + (_theResult____h507798[51] ? 6'd5 : - (_theResult____h507797[50] ? + (_theResult____h507798[50] ? 6'd6 : - (_theResult____h507797[49] ? + (_theResult____h507798[49] ? 6'd7 : - (_theResult____h507797[48] ? + (_theResult____h507798[48] ? 6'd8 : - (_theResult____h507797[47] ? + (_theResult____h507798[47] ? 6'd9 : - (_theResult____h507797[46] ? + (_theResult____h507798[46] ? 6'd10 : - (_theResult____h507797[45] ? + (_theResult____h507798[45] ? 6'd11 : - (_theResult____h507797[44] ? + (_theResult____h507798[44] ? 6'd12 : - (_theResult____h507797[43] ? + (_theResult____h507798[43] ? 6'd13 : - (_theResult____h507797[42] ? + (_theResult____h507798[42] ? 6'd14 : - (_theResult____h507797[41] ? + (_theResult____h507798[41] ? 6'd15 : - (_theResult____h507797[40] ? + (_theResult____h507798[40] ? 6'd16 : - (_theResult____h507797[39] ? + (_theResult____h507798[39] ? 6'd17 : - (_theResult____h507797[38] ? + (_theResult____h507798[38] ? 6'd18 : - (_theResult____h507797[37] ? + (_theResult____h507798[37] ? 6'd19 : - (_theResult____h507797[36] ? + (_theResult____h507798[36] ? 6'd20 : - (_theResult____h507797[35] ? + (_theResult____h507798[35] ? 6'd21 : - (_theResult____h507797[34] ? + (_theResult____h507798[34] ? 6'd22 : - (_theResult____h507797[33] ? + (_theResult____h507798[33] ? 6'd23 : - (_theResult____h507797[32] ? + (_theResult____h507798[32] ? 6'd24 : - (_theResult____h507797[31] ? + (_theResult____h507798[31] ? 6'd25 : - (_theResult____h507797[30] ? + (_theResult____h507798[30] ? 6'd26 : - (_theResult____h507797[29] ? + (_theResult____h507798[29] ? 6'd27 : - (_theResult____h507797[28] ? + (_theResult____h507798[28] ? 6'd28 : - (_theResult____h507797[27] ? + (_theResult____h507798[27] ? 6'd29 : - (_theResult____h507797[26] ? + (_theResult____h507798[26] ? 6'd30 : - (_theResult____h507797[25] ? + (_theResult____h507798[25] ? 6'd31 : - (_theResult____h507797[24] ? + (_theResult____h507798[24] ? 6'd32 : - (_theResult____h507797[23] ? + (_theResult____h507798[23] ? 6'd33 : - (_theResult____h507797[22] ? + (_theResult____h507798[22] ? 6'd34 : - (_theResult____h507797[21] ? + (_theResult____h507798[21] ? 6'd35 : - (_theResult____h507797[20] ? + (_theResult____h507798[20] ? 6'd36 : - (_theResult____h507797[19] ? + (_theResult____h507798[19] ? 6'd37 : - (_theResult____h507797[18] ? + (_theResult____h507798[18] ? 6'd38 : - (_theResult____h507797[17] ? + (_theResult____h507798[17] ? 6'd39 : - (_theResult____h507797[16] ? + (_theResult____h507798[16] ? 6'd40 : - (_theResult____h507797[15] ? + (_theResult____h507798[15] ? 6'd41 : - (_theResult____h507797[14] ? + (_theResult____h507798[14] ? 6'd42 : - (_theResult____h507797[13] ? + (_theResult____h507798[13] ? 6'd43 : - (_theResult____h507797[12] ? + (_theResult____h507798[12] ? 6'd44 : - (_theResult____h507797[11] ? + (_theResult____h507798[11] ? 6'd45 : - (_theResult____h507797[10] ? + (_theResult____h507798[10] ? 6'd46 : - (_theResult____h507797[9] ? + (_theResult____h507798[9] ? 6'd47 : - (_theResult____h507797[8] ? + (_theResult____h507798[8] ? 6'd48 : - (_theResult____h507797[7] ? + (_theResult____h507798[7] ? 6'd49 : - (_theResult____h507797[6] ? + (_theResult____h507798[6] ? 6'd50 : - (_theResult____h507797[5] ? + (_theResult____h507798[5] ? 6'd51 : - (_theResult____h507797[4] ? + (_theResult____h507798[4] ? 6'd52 : - (_theResult____h507797[3] ? + (_theResult____h507798[3] ? 6'd53 : - (_theResult____h507797[2] ? + (_theResult____h507798[2] ? 6'd54 : - (_theResult____h507797[1] ? + (_theResult____h507798[1] ? 6'd55 : - (_theResult____h507797[0] ? + (_theResult____h507798[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9725 = - (_theResult____h585954[56] ? + (_theResult____h585955[56] ? 6'd0 : - (_theResult____h585954[55] ? + (_theResult____h585955[55] ? 6'd1 : - (_theResult____h585954[54] ? + (_theResult____h585955[54] ? 6'd2 : - (_theResult____h585954[53] ? + (_theResult____h585955[53] ? 6'd3 : - (_theResult____h585954[52] ? + (_theResult____h585955[52] ? 6'd4 : - (_theResult____h585954[51] ? + (_theResult____h585955[51] ? 6'd5 : - (_theResult____h585954[50] ? + (_theResult____h585955[50] ? 6'd6 : - (_theResult____h585954[49] ? + (_theResult____h585955[49] ? 6'd7 : - (_theResult____h585954[48] ? + (_theResult____h585955[48] ? 6'd8 : - (_theResult____h585954[47] ? + (_theResult____h585955[47] ? 6'd9 : - (_theResult____h585954[46] ? + (_theResult____h585955[46] ? 6'd10 : - (_theResult____h585954[45] ? + (_theResult____h585955[45] ? 6'd11 : - (_theResult____h585954[44] ? + (_theResult____h585955[44] ? 6'd12 : - (_theResult____h585954[43] ? + (_theResult____h585955[43] ? 6'd13 : - (_theResult____h585954[42] ? + (_theResult____h585955[42] ? 6'd14 : - (_theResult____h585954[41] ? + (_theResult____h585955[41] ? 6'd15 : - (_theResult____h585954[40] ? + (_theResult____h585955[40] ? 6'd16 : - (_theResult____h585954[39] ? + (_theResult____h585955[39] ? 6'd17 : - (_theResult____h585954[38] ? + (_theResult____h585955[38] ? 6'd18 : - (_theResult____h585954[37] ? + (_theResult____h585955[37] ? 6'd19 : - (_theResult____h585954[36] ? + (_theResult____h585955[36] ? 6'd20 : - (_theResult____h585954[35] ? + (_theResult____h585955[35] ? 6'd21 : - (_theResult____h585954[34] ? + (_theResult____h585955[34] ? 6'd22 : - (_theResult____h585954[33] ? + (_theResult____h585955[33] ? 6'd23 : - (_theResult____h585954[32] ? + (_theResult____h585955[32] ? 6'd24 : - (_theResult____h585954[31] ? + (_theResult____h585955[31] ? 6'd25 : - (_theResult____h585954[30] ? + (_theResult____h585955[30] ? 6'd26 : - (_theResult____h585954[29] ? + (_theResult____h585955[29] ? 6'd27 : - (_theResult____h585954[28] ? + (_theResult____h585955[28] ? 6'd28 : - (_theResult____h585954[27] ? + (_theResult____h585955[27] ? 6'd29 : - (_theResult____h585954[26] ? + (_theResult____h585955[26] ? 6'd30 : - (_theResult____h585954[25] ? + (_theResult____h585955[25] ? 6'd31 : - (_theResult____h585954[24] ? + (_theResult____h585955[24] ? 6'd32 : - (_theResult____h585954[23] ? + (_theResult____h585955[23] ? 6'd33 : - (_theResult____h585954[22] ? + (_theResult____h585955[22] ? 6'd34 : - (_theResult____h585954[21] ? + (_theResult____h585955[21] ? 6'd35 : - (_theResult____h585954[20] ? + (_theResult____h585955[20] ? 6'd36 : - (_theResult____h585954[19] ? + (_theResult____h585955[19] ? 6'd37 : - (_theResult____h585954[18] ? + (_theResult____h585955[18] ? 6'd38 : - (_theResult____h585954[17] ? + (_theResult____h585955[17] ? 6'd39 : - (_theResult____h585954[16] ? + (_theResult____h585955[16] ? 6'd40 : - (_theResult____h585954[15] ? + (_theResult____h585955[15] ? 6'd41 : - (_theResult____h585954[14] ? + (_theResult____h585955[14] ? 6'd42 : - (_theResult____h585954[13] ? + (_theResult____h585955[13] ? 6'd43 : - (_theResult____h585954[12] ? + (_theResult____h585955[12] ? 6'd44 : - (_theResult____h585954[11] ? + (_theResult____h585955[11] ? 6'd45 : - (_theResult____h585954[10] ? + (_theResult____h585955[10] ? 6'd46 : - (_theResult____h585954[9] ? + (_theResult____h585955[9] ? 6'd47 : - (_theResult____h585954[8] ? + (_theResult____h585955[8] ? 6'd48 : - (_theResult____h585954[7] ? + (_theResult____h585955[7] ? 6'd49 : - (_theResult____h585954[6] ? + (_theResult____h585955[6] ? 6'd50 : - (_theResult____h585954[5] ? + (_theResult____h585955[5] ? 6'd51 : - (_theResult____h585954[4] ? + (_theResult____h585955[4] ? 6'd52 : - (_theResult____h585954[3] ? + (_theResult____h585955[3] ? 6'd53 : - (_theResult____h585954[2] ? + (_theResult____h585955[2] ? 6'd54 : - (_theResult____h585954[1] ? + (_theResult____h585955[1] ? 6'd55 : - (_theResult____h585954[0] ? + (_theResult____h585955[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4898 = - (_theResult____h368144[56] ? + (_theResult____h368145[56] ? 6'd0 : - (_theResult____h368144[55] ? + (_theResult____h368145[55] ? 6'd1 : - (_theResult____h368144[54] ? + (_theResult____h368145[54] ? 6'd2 : - (_theResult____h368144[53] ? + (_theResult____h368145[53] ? 6'd3 : - (_theResult____h368144[52] ? + (_theResult____h368145[52] ? 6'd4 : - (_theResult____h368144[51] ? + (_theResult____h368145[51] ? 6'd5 : - (_theResult____h368144[50] ? + (_theResult____h368145[50] ? 6'd6 : - (_theResult____h368144[49] ? + (_theResult____h368145[49] ? 6'd7 : - (_theResult____h368144[48] ? + (_theResult____h368145[48] ? 6'd8 : - (_theResult____h368144[47] ? + (_theResult____h368145[47] ? 6'd9 : - (_theResult____h368144[46] ? + (_theResult____h368145[46] ? 6'd10 : - (_theResult____h368144[45] ? + (_theResult____h368145[45] ? 6'd11 : - (_theResult____h368144[44] ? + (_theResult____h368145[44] ? 6'd12 : - (_theResult____h368144[43] ? + (_theResult____h368145[43] ? 6'd13 : - (_theResult____h368144[42] ? + (_theResult____h368145[42] ? 6'd14 : - (_theResult____h368144[41] ? + (_theResult____h368145[41] ? 6'd15 : - (_theResult____h368144[40] ? + (_theResult____h368145[40] ? 6'd16 : - (_theResult____h368144[39] ? + (_theResult____h368145[39] ? 6'd17 : - (_theResult____h368144[38] ? + (_theResult____h368145[38] ? 6'd18 : - (_theResult____h368144[37] ? + (_theResult____h368145[37] ? 6'd19 : - (_theResult____h368144[36] ? + (_theResult____h368145[36] ? 6'd20 : - (_theResult____h368144[35] ? + (_theResult____h368145[35] ? 6'd21 : - (_theResult____h368144[34] ? + (_theResult____h368145[34] ? 6'd22 : - (_theResult____h368144[33] ? + (_theResult____h368145[33] ? 6'd23 : - (_theResult____h368144[32] ? + (_theResult____h368145[32] ? 6'd24 : - (_theResult____h368144[31] ? + (_theResult____h368145[31] ? 6'd25 : - (_theResult____h368144[30] ? + (_theResult____h368145[30] ? 6'd26 : - (_theResult____h368144[29] ? + (_theResult____h368145[29] ? 6'd27 : - (_theResult____h368144[28] ? + (_theResult____h368145[28] ? 6'd28 : - (_theResult____h368144[27] ? + (_theResult____h368145[27] ? 6'd29 : - (_theResult____h368144[26] ? + (_theResult____h368145[26] ? 6'd30 : - (_theResult____h368144[25] ? + (_theResult____h368145[25] ? 6'd31 : - (_theResult____h368144[24] ? + (_theResult____h368145[24] ? 6'd32 : - (_theResult____h368144[23] ? + (_theResult____h368145[23] ? 6'd33 : - (_theResult____h368144[22] ? + (_theResult____h368145[22] ? 6'd34 : - (_theResult____h368144[21] ? + (_theResult____h368145[21] ? 6'd35 : - (_theResult____h368144[20] ? + (_theResult____h368145[20] ? 6'd36 : - (_theResult____h368144[19] ? + (_theResult____h368145[19] ? 6'd37 : - (_theResult____h368144[18] ? + (_theResult____h368145[18] ? 6'd38 : - (_theResult____h368144[17] ? + (_theResult____h368145[17] ? 6'd39 : - (_theResult____h368144[16] ? + (_theResult____h368145[16] ? 6'd40 : - (_theResult____h368144[15] ? + (_theResult____h368145[15] ? 6'd41 : - (_theResult____h368144[14] ? + (_theResult____h368145[14] ? 6'd42 : - (_theResult____h368144[13] ? + (_theResult____h368145[13] ? 6'd43 : - (_theResult____h368144[12] ? + (_theResult____h368145[12] ? 6'd44 : - (_theResult____h368144[11] ? + (_theResult____h368145[11] ? 6'd45 : - (_theResult____h368144[10] ? + (_theResult____h368145[10] ? 6'd46 : - (_theResult____h368144[9] ? + (_theResult____h368145[9] ? 6'd47 : - (_theResult____h368144[8] ? + (_theResult____h368145[8] ? 6'd48 : - (_theResult____h368144[7] ? + (_theResult____h368145[7] ? 6'd49 : - (_theResult____h368144[6] ? + (_theResult____h368145[6] ? 6'd50 : - (_theResult____h368144[5] ? + (_theResult____h368145[5] ? 6'd51 : - (_theResult____h368144[4] ? + (_theResult____h368145[4] ? 6'd52 : - (_theResult____h368144[3] ? + (_theResult____h368145[3] ? 6'd53 : - (_theResult____h368144[2] ? + (_theResult____h368145[2] ? 6'd54 : - (_theResult____h368144[1] ? + (_theResult____h368145[1] ? 6'd55 : - (_theResult____h368144[0] ? + (_theResult____h368145[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 = - (_theResult____h413841[56] ? + (_theResult____h413842[56] ? 6'd0 : - (_theResult____h413841[55] ? + (_theResult____h413842[55] ? 6'd1 : - (_theResult____h413841[54] ? + (_theResult____h413842[54] ? 6'd2 : - (_theResult____h413841[53] ? + (_theResult____h413842[53] ? 6'd3 : - (_theResult____h413841[52] ? + (_theResult____h413842[52] ? 6'd4 : - (_theResult____h413841[51] ? + (_theResult____h413842[51] ? 6'd5 : - (_theResult____h413841[50] ? + (_theResult____h413842[50] ? 6'd6 : - (_theResult____h413841[49] ? + (_theResult____h413842[49] ? 6'd7 : - (_theResult____h413841[48] ? + (_theResult____h413842[48] ? 6'd8 : - (_theResult____h413841[47] ? + (_theResult____h413842[47] ? 6'd9 : - (_theResult____h413841[46] ? + (_theResult____h413842[46] ? 6'd10 : - (_theResult____h413841[45] ? + (_theResult____h413842[45] ? 6'd11 : - (_theResult____h413841[44] ? + (_theResult____h413842[44] ? 6'd12 : - (_theResult____h413841[43] ? + (_theResult____h413842[43] ? 6'd13 : - (_theResult____h413841[42] ? + (_theResult____h413842[42] ? 6'd14 : - (_theResult____h413841[41] ? + (_theResult____h413842[41] ? 6'd15 : - (_theResult____h413841[40] ? + (_theResult____h413842[40] ? 6'd16 : - (_theResult____h413841[39] ? + (_theResult____h413842[39] ? 6'd17 : - (_theResult____h413841[38] ? + (_theResult____h413842[38] ? 6'd18 : - (_theResult____h413841[37] ? + (_theResult____h413842[37] ? 6'd19 : - (_theResult____h413841[36] ? + (_theResult____h413842[36] ? 6'd20 : - (_theResult____h413841[35] ? + (_theResult____h413842[35] ? 6'd21 : - (_theResult____h413841[34] ? + (_theResult____h413842[34] ? 6'd22 : - (_theResult____h413841[33] ? + (_theResult____h413842[33] ? 6'd23 : - (_theResult____h413841[32] ? + (_theResult____h413842[32] ? 6'd24 : - (_theResult____h413841[31] ? + (_theResult____h413842[31] ? 6'd25 : - (_theResult____h413841[30] ? + (_theResult____h413842[30] ? 6'd26 : - (_theResult____h413841[29] ? + (_theResult____h413842[29] ? 6'd27 : - (_theResult____h413841[28] ? + (_theResult____h413842[28] ? 6'd28 : - (_theResult____h413841[27] ? + (_theResult____h413842[27] ? 6'd29 : - (_theResult____h413841[26] ? + (_theResult____h413842[26] ? 6'd30 : - (_theResult____h413841[25] ? + (_theResult____h413842[25] ? 6'd31 : - (_theResult____h413841[24] ? + (_theResult____h413842[24] ? 6'd32 : - (_theResult____h413841[23] ? + (_theResult____h413842[23] ? 6'd33 : - (_theResult____h413841[22] ? + (_theResult____h413842[22] ? 6'd34 : - (_theResult____h413841[21] ? + (_theResult____h413842[21] ? 6'd35 : - (_theResult____h413841[20] ? + (_theResult____h413842[20] ? 6'd36 : - (_theResult____h413841[19] ? + (_theResult____h413842[19] ? 6'd37 : - (_theResult____h413841[18] ? + (_theResult____h413842[18] ? 6'd38 : - (_theResult____h413841[17] ? + (_theResult____h413842[17] ? 6'd39 : - (_theResult____h413841[16] ? + (_theResult____h413842[16] ? 6'd40 : - (_theResult____h413841[15] ? + (_theResult____h413842[15] ? 6'd41 : - (_theResult____h413841[14] ? + (_theResult____h413842[14] ? 6'd42 : - (_theResult____h413841[13] ? + (_theResult____h413842[13] ? 6'd43 : - (_theResult____h413841[12] ? + (_theResult____h413842[12] ? 6'd44 : - (_theResult____h413841[11] ? + (_theResult____h413842[11] ? 6'd45 : - (_theResult____h413841[10] ? + (_theResult____h413842[10] ? 6'd46 : - (_theResult____h413841[9] ? + (_theResult____h413842[9] ? 6'd47 : - (_theResult____h413841[8] ? + (_theResult____h413842[8] ? 6'd48 : - (_theResult____h413841[7] ? + (_theResult____h413842[7] ? 6'd49 : - (_theResult____h413841[6] ? + (_theResult____h413842[6] ? 6'd50 : - (_theResult____h413841[5] ? + (_theResult____h413842[5] ? 6'd51 : - (_theResult____h413841[4] ? + (_theResult____h413842[4] ? 6'd52 : - (_theResult____h413841[3] ? + (_theResult____h413842[3] ? 6'd53 : - (_theResult____h413841[2] ? + (_theResult____h413842[2] ? 6'd54 : - (_theResult____h413841[1] ? + (_theResult____h413842[1] ? 6'd55 : - (_theResult____h413841[0] ? + (_theResult____h413842[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 = - (_theResult____h459536[56] ? + (_theResult____h459537[56] ? 6'd0 : - (_theResult____h459536[55] ? + (_theResult____h459537[55] ? 6'd1 : - (_theResult____h459536[54] ? + (_theResult____h459537[54] ? 6'd2 : - (_theResult____h459536[53] ? + (_theResult____h459537[53] ? 6'd3 : - (_theResult____h459536[52] ? + (_theResult____h459537[52] ? 6'd4 : - (_theResult____h459536[51] ? + (_theResult____h459537[51] ? 6'd5 : - (_theResult____h459536[50] ? + (_theResult____h459537[50] ? 6'd6 : - (_theResult____h459536[49] ? + (_theResult____h459537[49] ? 6'd7 : - (_theResult____h459536[48] ? + (_theResult____h459537[48] ? 6'd8 : - (_theResult____h459536[47] ? + (_theResult____h459537[47] ? 6'd9 : - (_theResult____h459536[46] ? + (_theResult____h459537[46] ? 6'd10 : - (_theResult____h459536[45] ? + (_theResult____h459537[45] ? 6'd11 : - (_theResult____h459536[44] ? + (_theResult____h459537[44] ? 6'd12 : - (_theResult____h459536[43] ? + (_theResult____h459537[43] ? 6'd13 : - (_theResult____h459536[42] ? + (_theResult____h459537[42] ? 6'd14 : - (_theResult____h459536[41] ? + (_theResult____h459537[41] ? 6'd15 : - (_theResult____h459536[40] ? + (_theResult____h459537[40] ? 6'd16 : - (_theResult____h459536[39] ? + (_theResult____h459537[39] ? 6'd17 : - (_theResult____h459536[38] ? + (_theResult____h459537[38] ? 6'd18 : - (_theResult____h459536[37] ? + (_theResult____h459537[37] ? 6'd19 : - (_theResult____h459536[36] ? + (_theResult____h459537[36] ? 6'd20 : - (_theResult____h459536[35] ? + (_theResult____h459537[35] ? 6'd21 : - (_theResult____h459536[34] ? + (_theResult____h459537[34] ? 6'd22 : - (_theResult____h459536[33] ? + (_theResult____h459537[33] ? 6'd23 : - (_theResult____h459536[32] ? + (_theResult____h459537[32] ? 6'd24 : - (_theResult____h459536[31] ? + (_theResult____h459537[31] ? 6'd25 : - (_theResult____h459536[30] ? + (_theResult____h459537[30] ? 6'd26 : - (_theResult____h459536[29] ? + (_theResult____h459537[29] ? 6'd27 : - (_theResult____h459536[28] ? + (_theResult____h459537[28] ? 6'd28 : - (_theResult____h459536[27] ? + (_theResult____h459537[27] ? 6'd29 : - (_theResult____h459536[26] ? + (_theResult____h459537[26] ? 6'd30 : - (_theResult____h459536[25] ? + (_theResult____h459537[25] ? 6'd31 : - (_theResult____h459536[24] ? + (_theResult____h459537[24] ? 6'd32 : - (_theResult____h459536[23] ? + (_theResult____h459537[23] ? 6'd33 : - (_theResult____h459536[22] ? + (_theResult____h459537[22] ? 6'd34 : - (_theResult____h459536[21] ? + (_theResult____h459537[21] ? 6'd35 : - (_theResult____h459536[20] ? + (_theResult____h459537[20] ? 6'd36 : - (_theResult____h459536[19] ? + (_theResult____h459537[19] ? 6'd37 : - (_theResult____h459536[18] ? + (_theResult____h459537[18] ? 6'd38 : - (_theResult____h459536[17] ? + (_theResult____h459537[17] ? 6'd39 : - (_theResult____h459536[16] ? + (_theResult____h459537[16] ? 6'd40 : - (_theResult____h459536[15] ? + (_theResult____h459537[15] ? 6'd41 : - (_theResult____h459536[14] ? + (_theResult____h459537[14] ? 6'd42 : - (_theResult____h459536[13] ? + (_theResult____h459537[13] ? 6'd43 : - (_theResult____h459536[12] ? + (_theResult____h459537[12] ? 6'd44 : - (_theResult____h459536[11] ? + (_theResult____h459537[11] ? 6'd45 : - (_theResult____h459536[10] ? + (_theResult____h459537[10] ? 6'd46 : - (_theResult____h459536[9] ? + (_theResult____h459537[9] ? 6'd47 : - (_theResult____h459536[8] ? + (_theResult____h459537[8] ? 6'd48 : - (_theResult____h459536[7] ? + (_theResult____h459537[7] ? 6'd49 : - (_theResult____h459536[6] ? + (_theResult____h459537[6] ? 6'd50 : - (_theResult____h459536[5] ? + (_theResult____h459537[5] ? 6'd51 : - (_theResult____h459536[4] ? + (_theResult____h459537[4] ? 6'd52 : - (_theResult____h459536[3] ? + (_theResult____h459537[3] ? 6'd53 : - (_theResult____h459536[2] ? + (_theResult____h459537[2] ? 6'd54 : - (_theResult____h459536[1] ? + (_theResult____h459537[1] ? 6'd55 : - (_theResult____h459536[0] ? + (_theResult____h459537[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10037 = - (_theResult___fst_exp__h594190 == 11'd2047) ? + (_theResult___fst_exp__h594191 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21065,10 +21085,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard85965_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10539 = - (_theResult___fst_exp__h554886 == 11'd2047) ? + (_theResult___fst_exp__h554887 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21076,10 +21096,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46660_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard46661_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10806 = - (_theResult___fst_exp__h554886 == 11'd2047) ? + (_theResult___fst_exp__h554887 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21087,10 +21107,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46660_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard46661_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9054 = - (_theResult___fst_exp__h516033 == 11'd2047) ? + (_theResult___fst_exp__h516034 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21098,10 +21118,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_guard07808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9769 = - (_theResult___fst_exp__h594190 == 11'd2047) ? + (_theResult___fst_exp__h594191 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21109,538 +21129,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard85965_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410 = - (guard__h350515 == 2'b0 || + (guard__h350516 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h358616 : - _theResult___exp__h359132 ; + _theResult___fst_exp__h358617 : + _theResult___exp__h359133 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4413 = - (guard__h350515 == 2'b0) ? - _theResult___fst_exp__h358616 : + (guard__h350516 == 2'b0) ? + _theResult___fst_exp__h358617 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h359132 : - _theResult___fst_exp__h358616) ; + _theResult___exp__h359133 : + _theResult___fst_exp__h358617) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057 = - (guard__h350515 == 2'b0 || + (guard__h350516 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h358610[56:34] : - _theResult___sfd__h359133 ; + sfdin__h358611[56:34] : + _theResult___sfd__h359134 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059 = - (guard__h350515 == 2'b0) ? - sfdin__h358610[56:34] : + (guard__h350516 == 2'b0) ? + sfdin__h358611[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h359133 : - sfdin__h358610[56:34]) ; + _theResult___sfd__h359134 : + sfdin__h358611[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802 = - (guard__h396214 == 2'b0 || + (guard__h396215 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h404313 : - _theResult___exp__h404829 ; + _theResult___fst_exp__h404314 : + _theResult___exp__h404830 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5805 = - (guard__h396214 == 2'b0) ? - _theResult___fst_exp__h404313 : + (guard__h396215 == 2'b0) ? + _theResult___fst_exp__h404314 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h404829 : - _theResult___fst_exp__h404313) ; + _theResult___exp__h404830 : + _theResult___fst_exp__h404314) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449 = - (guard__h396214 == 2'b0 || + (guard__h396215 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h404307[56:34] : - _theResult___sfd__h404830 ; + sfdin__h404308[56:34] : + _theResult___sfd__h404831 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6451 = - (guard__h396214 == 2'b0) ? - sfdin__h404307[56:34] : + (guard__h396215 == 2'b0) ? + sfdin__h404308[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h404830 : - sfdin__h404307[56:34]) ; + _theResult___sfd__h404831 : + sfdin__h404308[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194 = - (guard__h441909 == 2'b0 || + (guard__h441910 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h450008 : - _theResult___exp__h450524 ; + _theResult___fst_exp__h450009 : + _theResult___exp__h450525 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7197 = - (guard__h441909 == 2'b0) ? - _theResult___fst_exp__h450008 : + (guard__h441910 == 2'b0) ? + _theResult___fst_exp__h450009 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h450524 : - _theResult___fst_exp__h450008) ; + _theResult___exp__h450525 : + _theResult___fst_exp__h450009) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841 = - (guard__h441909 == 2'b0 || + (guard__h441910 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h450002[56:34] : - _theResult___sfd__h450525 ; + sfdin__h450003[56:34] : + _theResult___sfd__h450526 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843 = - (guard__h441909 == 2'b0) ? - sfdin__h450002[56:34] : + (guard__h441910 == 2'b0) ? + sfdin__h450003[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h450525 : - sfdin__h450002[56:34]) ; + _theResult___sfd__h450526 : + sfdin__h450003[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651 = - (guard__h546660 == 2'b0 || + (guard__h546661 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h554886 : - _theResult___exp__h555615 ; + _theResult___fst_exp__h554887 : + _theResult___exp__h555616 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653 = - (guard__h546660 == 2'b0) ? - _theResult___fst_exp__h554886 : + (guard__h546661 == 2'b0) ? + _theResult___fst_exp__h554887 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h555615 : - _theResult___fst_exp__h554886) ; + _theResult___exp__h555616 : + _theResult___fst_exp__h554887) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734 = - (guard__h546660 == 2'b0 || + (guard__h546661 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h554880[56:5] : - _theResult___sfd__h555616 ; + sfdin__h554881[56:5] : + _theResult___sfd__h555617 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736 = - (guard__h546660 == 2'b0) ? - sfdin__h554880[56:5] : + (guard__h546661 == 2'b0) ? + sfdin__h554881[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h555616 : - sfdin__h554880[56:5]) ; + _theResult___sfd__h555617 : + sfdin__h554881[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171 = - (guard__h507807 == 2'b0 || + (guard__h507808 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h516033 : - _theResult___exp__h516762 ; + _theResult___fst_exp__h516034 : + _theResult___exp__h516763 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9173 = - (guard__h507807 == 2'b0) ? - _theResult___fst_exp__h516033 : + (guard__h507808 == 2'b0) ? + _theResult___fst_exp__h516034 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h516762 : - _theResult___fst_exp__h516033) ; + _theResult___exp__h516763 : + _theResult___fst_exp__h516034) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255 = - (guard__h507807 == 2'b0 || + (guard__h507808 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h516027[56:5] : - _theResult___sfd__h516763 ; + sfdin__h516028[56:5] : + _theResult___sfd__h516764 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9257 = - (guard__h507807 == 2'b0) ? - sfdin__h516027[56:5] : + (guard__h507808 == 2'b0) ? + sfdin__h516028[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h516763 : - sfdin__h516027[56:5]) ; + _theResult___sfd__h516764 : + sfdin__h516028[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 = - (guard__h585964 == 2'b0 || + (guard__h585965 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h594190 : - _theResult___exp__h594919 ; + _theResult___fst_exp__h594191 : + _theResult___exp__h594920 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 = - (guard__h585964 == 2'b0) ? - _theResult___fst_exp__h594190 : + (guard__h585965 == 2'b0) ? + _theResult___fst_exp__h594191 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h594919 : - _theResult___fst_exp__h594190) ; + _theResult___exp__h594920 : + _theResult___fst_exp__h594191) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9964 = - (guard__h585964 == 2'b0 || + (guard__h585965 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h594184[56:5] : - _theResult___sfd__h594920 ; + sfdin__h594185[56:5] : + _theResult___sfd__h594921 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9966 = - (guard__h585964 == 2'b0) ? - sfdin__h594184[56:5] : + (guard__h585965 == 2'b0) ? + sfdin__h594185[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h594920 : - sfdin__h594184[56:5]) ; + _theResult___sfd__h594921 : + sfdin__h594185[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4957 = - (guard__h368154 == 2'b0 || + (guard__h368155 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h376382 : - _theResult___exp__h376898 ; + _theResult___fst_exp__h376383 : + _theResult___exp__h376899 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4959 = - (guard__h368154 == 2'b0) ? - _theResult___fst_exp__h376382 : + (guard__h368155 == 2'b0) ? + _theResult___fst_exp__h376383 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h376898 : - _theResult___fst_exp__h376382) ; + _theResult___exp__h376899 : + _theResult___fst_exp__h376383) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5103 = - (guard__h368154 == 2'b0 || + (guard__h368155 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h376376[56:34] : - _theResult___sfd__h376899 ; + sfdin__h376377[56:34] : + _theResult___sfd__h376900 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5105 = - (guard__h368154 == 2'b0) ? - sfdin__h376376[56:34] : + (guard__h368155 == 2'b0) ? + sfdin__h376377[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h376899 : - sfdin__h376376[56:34]) ; + _theResult___sfd__h376900 : + sfdin__h376377[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6349 = - (guard__h413851 == 2'b0 || + (guard__h413852 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h422079 : - _theResult___exp__h422595 ; + _theResult___fst_exp__h422080 : + _theResult___exp__h422596 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6351 = - (guard__h413851 == 2'b0) ? - _theResult___fst_exp__h422079 : + (guard__h413852 == 2'b0) ? + _theResult___fst_exp__h422080 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h422595 : - _theResult___fst_exp__h422079) ; + _theResult___exp__h422596 : + _theResult___fst_exp__h422080) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6495 = - (guard__h413851 == 2'b0 || + (guard__h413852 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h422073[56:34] : - _theResult___sfd__h422596 ; + sfdin__h422074[56:34] : + _theResult___sfd__h422597 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6497 = - (guard__h413851 == 2'b0) ? - sfdin__h422073[56:34] : + (guard__h413852 == 2'b0) ? + sfdin__h422074[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h422596 : - sfdin__h422073[56:34]) ; + _theResult___sfd__h422597 : + sfdin__h422074[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7741 = - (guard__h459546 == 2'b0 || + (guard__h459547 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h467774 : - _theResult___exp__h468290 ; + _theResult___fst_exp__h467775 : + _theResult___exp__h468291 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7743 = - (guard__h459546 == 2'b0) ? - _theResult___fst_exp__h467774 : + (guard__h459547 == 2'b0) ? + _theResult___fst_exp__h467775 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h468290 : - _theResult___fst_exp__h467774) ; + _theResult___exp__h468291 : + _theResult___fst_exp__h467775) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7887 = - (guard__h459546 == 2'b0 || + (guard__h459547 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h467768[56:34] : - _theResult___sfd__h468291 ; + sfdin__h467769[56:34] : + _theResult___sfd__h468292 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7889 = - (guard__h459546 == 2'b0) ? - sfdin__h467768[56:34] : + (guard__h459547 == 2'b0) ? + sfdin__h467769[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h468291 : - sfdin__h467768[56:34]) ; + _theResult___sfd__h468292 : + sfdin__h467769[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10613 = - (guard__h537348 == 2'b0 || + (guard__h537349 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h545309 : - _theResult___exp__h545964 ; + _theResult___fst_exp__h545310 : + _theResult___exp__h545965 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10615 = - (guard__h537348 == 2'b0) ? - _theResult___fst_exp__h545309 : + (guard__h537349 == 2'b0) ? + _theResult___fst_exp__h545310 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h545964 : - _theResult___fst_exp__h545309) ; + _theResult___exp__h545965 : + _theResult___fst_exp__h545310) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682 = - (guard__h555729 == 2'b0 || + (guard__h555730 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h563719 : - _theResult___exp__h564399 ; + _theResult___fst_exp__h563720 : + _theResult___exp__h564400 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684 = - (guard__h555729 == 2'b0) ? - _theResult___fst_exp__h563719 : + (guard__h555730 == 2'b0) ? + _theResult___fst_exp__h563720 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h564399 : - _theResult___fst_exp__h563719) ; + _theResult___exp__h564400 : + _theResult___fst_exp__h563720) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708 = - (guard__h537348 == 2'b0 || + (guard__h537349 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h545260[56:5] : - _theResult___sfd__h545965 ; + _theResult___snd__h545261[56:5] : + _theResult___sfd__h545966 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10710 = - (guard__h537348 == 2'b0) ? - _theResult___snd__h545260[56:5] : + (guard__h537349 == 2'b0) ? + _theResult___snd__h545261[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h545965 : - _theResult___snd__h545260[56:5]) ; + _theResult___sfd__h545966 : + _theResult___snd__h545261[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10753 = - (guard__h555729 == 2'b0 || + (guard__h555730 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h563665[56:5] : - _theResult___sfd__h564400 ; + _theResult___snd__h563666[56:5] : + _theResult___sfd__h564401 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10755 = - (guard__h555729 == 2'b0) ? - _theResult___snd__h563665[56:5] : + (guard__h555730 == 2'b0) ? + _theResult___snd__h563666[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h564400 : - _theResult___snd__h563665[56:5]) ; + _theResult___sfd__h564401 : + _theResult___snd__h563666[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9128 = - (guard__h498495 == 2'b0 || + (guard__h498496 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h506456 : - _theResult___exp__h507111 ; + _theResult___fst_exp__h506457 : + _theResult___exp__h507112 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9130 = - (guard__h498495 == 2'b0) ? - _theResult___fst_exp__h506456 : + (guard__h498496 == 2'b0) ? + _theResult___fst_exp__h506457 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h507111 : - _theResult___fst_exp__h506456) ; + _theResult___exp__h507112 : + _theResult___fst_exp__h506457) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9202 = - (guard__h516876 == 2'b0 || + (guard__h516877 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h524866 : - _theResult___exp__h525546 ; + _theResult___fst_exp__h524867 : + _theResult___exp__h525547 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9204 = - (guard__h516876 == 2'b0) ? - _theResult___fst_exp__h524866 : + (guard__h516877 == 2'b0) ? + _theResult___fst_exp__h524867 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h525546 : - _theResult___fst_exp__h524866) ; + _theResult___exp__h525547 : + _theResult___fst_exp__h524867) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9228 = - (guard__h498495 == 2'b0 || + (guard__h498496 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h506407[56:5] : - _theResult___sfd__h507112 ; + _theResult___snd__h506408[56:5] : + _theResult___sfd__h507113 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9230 = - (guard__h498495 == 2'b0) ? - _theResult___snd__h506407[56:5] : + (guard__h498496 == 2'b0) ? + _theResult___snd__h506408[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h507112 : - _theResult___snd__h506407[56:5]) ; + _theResult___sfd__h507113 : + _theResult___snd__h506408[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9274 = - (guard__h516876 == 2'b0 || + (guard__h516877 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h524812[56:5] : - _theResult___sfd__h525547 ; + _theResult___snd__h524813[56:5] : + _theResult___sfd__h525548 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9276 = - (guard__h516876 == 2'b0) ? - _theResult___snd__h524812[56:5] : + (guard__h516877 == 2'b0) ? + _theResult___snd__h524813[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h525547 : - _theResult___snd__h524812[56:5]) ; + _theResult___sfd__h525548 : + _theResult___snd__h524813[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9843 = - (guard__h576652 == 2'b0 || + (guard__h576653 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h584613 : - _theResult___exp__h585268 ; + _theResult___fst_exp__h584614 : + _theResult___exp__h585269 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9845 = - (guard__h576652 == 2'b0) ? - _theResult___fst_exp__h584613 : + (guard__h576653 == 2'b0) ? + _theResult___fst_exp__h584614 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h585268 : - _theResult___fst_exp__h584613) ; + _theResult___exp__h585269 : + _theResult___fst_exp__h584614) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912 = - (guard__h595033 == 2'b0 || + (guard__h595034 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h603023 : - _theResult___exp__h603703 ; + _theResult___fst_exp__h603024 : + _theResult___exp__h603704 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914 = - (guard__h595033 == 2'b0) ? - _theResult___fst_exp__h603023 : + (guard__h595034 == 2'b0) ? + _theResult___fst_exp__h603024 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h603703 : - _theResult___fst_exp__h603023) ; + _theResult___exp__h603704 : + _theResult___fst_exp__h603024) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9938 = - (guard__h576652 == 2'b0 || + (guard__h576653 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h584564[56:5] : - _theResult___sfd__h585269 ; + _theResult___snd__h584565[56:5] : + _theResult___sfd__h585270 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9940 = - (guard__h576652 == 2'b0) ? - _theResult___snd__h584564[56:5] : + (guard__h576653 == 2'b0) ? + _theResult___snd__h584565[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h585269 : - _theResult___snd__h584564[56:5]) ; + _theResult___sfd__h585270 : + _theResult___snd__h584565[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9983 = - (guard__h595033 == 2'b0 || + (guard__h595034 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h602969[56:5] : - _theResult___sfd__h603704 ; + _theResult___snd__h602970[56:5] : + _theResult___sfd__h603705 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9985 = - (guard__h595033 == 2'b0) ? - _theResult___snd__h602969[56:5] : + (guard__h595034 == 2'b0) ? + _theResult___snd__h602970[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h603704 : - _theResult___snd__h602969[56:5]) ; + _theResult___sfd__h603705 : + _theResult___snd__h602970[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4632 = - (guard__h359224 == 2'b0 || + (guard__h359225 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h367272 : - _theResult___exp__h367714 ; + _theResult___fst_exp__h367273 : + _theResult___exp__h367715 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4634 = - (guard__h359224 == 2'b0) ? - _theResult___fst_exp__h367272 : + (guard__h359225 == 2'b0) ? + _theResult___fst_exp__h367273 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h367714 : - _theResult___fst_exp__h367272) ; + _theResult___exp__h367715 : + _theResult___fst_exp__h367273) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5026 = - (guard__h376990 == 2'b0 || + (guard__h376991 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h385067 : - _theResult___exp__h385534 ; + _theResult___fst_exp__h385068 : + _theResult___exp__h385535 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5028 = - (guard__h376990 == 2'b0) ? - _theResult___fst_exp__h385067 : + (guard__h376991 == 2'b0) ? + _theResult___fst_exp__h385068 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h385534 : - _theResult___fst_exp__h385067) ; + _theResult___exp__h385535 : + _theResult___fst_exp__h385068) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5076 = - (guard__h359224 == 2'b0 || + (guard__h359225 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h367223[56:34] : - _theResult___sfd__h367715 ; + _theResult___snd__h367224[56:34] : + _theResult___sfd__h367716 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5078 = - (guard__h359224 == 2'b0) ? - _theResult___snd__h367223[56:34] : + (guard__h359225 == 2'b0) ? + _theResult___snd__h367224[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h367715 : - _theResult___snd__h367223[56:34]) ; + _theResult___sfd__h367716 : + _theResult___snd__h367224[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122 = - (guard__h376990 == 2'b0 || + (guard__h376991 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h385013[56:34] : - _theResult___sfd__h385535 ; + _theResult___snd__h385014[56:34] : + _theResult___sfd__h385536 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124 = - (guard__h376990 == 2'b0) ? - _theResult___snd__h385013[56:34] : + (guard__h376991 == 2'b0) ? + _theResult___snd__h385014[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h385535 : - _theResult___snd__h385013[56:34]) ; + _theResult___sfd__h385536 : + _theResult___snd__h385014[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6024 = - (guard__h404921 == 2'b0 || + (guard__h404922 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h412969 : - _theResult___exp__h413411 ; + _theResult___fst_exp__h412970 : + _theResult___exp__h413412 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6026 = - (guard__h404921 == 2'b0) ? - _theResult___fst_exp__h412969 : + (guard__h404922 == 2'b0) ? + _theResult___fst_exp__h412970 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h413411 : - _theResult___fst_exp__h412969) ; + _theResult___exp__h413412 : + _theResult___fst_exp__h412970) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6418 = - (guard__h422687 == 2'b0 || + (guard__h422688 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h430764 : - _theResult___exp__h431231 ; + _theResult___fst_exp__h430765 : + _theResult___exp__h431232 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6420 = - (guard__h422687 == 2'b0) ? - _theResult___fst_exp__h430764 : + (guard__h422688 == 2'b0) ? + _theResult___fst_exp__h430765 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h431231 : - _theResult___fst_exp__h430764) ; + _theResult___exp__h431232 : + _theResult___fst_exp__h430765) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6468 = - (guard__h404921 == 2'b0 || + (guard__h404922 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h412920[56:34] : - _theResult___sfd__h413412 ; + _theResult___snd__h412921[56:34] : + _theResult___sfd__h413413 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6470 = - (guard__h404921 == 2'b0) ? - _theResult___snd__h412920[56:34] : + (guard__h404922 == 2'b0) ? + _theResult___snd__h412921[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h413412 : - _theResult___snd__h412920[56:34]) ; + _theResult___sfd__h413413 : + _theResult___snd__h412921[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514 = - (guard__h422687 == 2'b0 || + (guard__h422688 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h430710[56:34] : - _theResult___sfd__h431232 ; + _theResult___snd__h430711[56:34] : + _theResult___sfd__h431233 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516 = - (guard__h422687 == 2'b0) ? - _theResult___snd__h430710[56:34] : + (guard__h422688 == 2'b0) ? + _theResult___snd__h430711[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h431232 : - _theResult___snd__h430710[56:34]) ; + _theResult___sfd__h431233 : + _theResult___snd__h430711[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7416 = - (guard__h450616 == 2'b0 || + (guard__h450617 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h458664 : - _theResult___exp__h459106 ; + _theResult___fst_exp__h458665 : + _theResult___exp__h459107 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7418 = - (guard__h450616 == 2'b0) ? - _theResult___fst_exp__h458664 : + (guard__h450617 == 2'b0) ? + _theResult___fst_exp__h458665 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h459106 : - _theResult___fst_exp__h458664) ; + _theResult___exp__h459107 : + _theResult___fst_exp__h458665) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7810 = - (guard__h468382 == 2'b0 || + (guard__h468383 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h476459 : - _theResult___exp__h476926 ; + _theResult___fst_exp__h476460 : + _theResult___exp__h476927 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7812 = - (guard__h468382 == 2'b0) ? - _theResult___fst_exp__h476459 : + (guard__h468383 == 2'b0) ? + _theResult___fst_exp__h476460 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h476926 : - _theResult___fst_exp__h476459) ; + _theResult___exp__h476927 : + _theResult___fst_exp__h476460) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 = - (guard__h450616 == 2'b0 || + (guard__h450617 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h458615[56:34] : - _theResult___sfd__h459107 ; + _theResult___snd__h458616[56:34] : + _theResult___sfd__h459108 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 = - (guard__h450616 == 2'b0) ? - _theResult___snd__h458615[56:34] : + (guard__h450617 == 2'b0) ? + _theResult___snd__h458616[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h459107 : - _theResult___snd__h458615[56:34]) ; + _theResult___sfd__h459108 : + _theResult___snd__h458616[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906 = - (guard__h468382 == 2'b0 || + (guard__h468383 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h476405[56:34] : - _theResult___sfd__h476927 ; + _theResult___snd__h476406[56:34] : + _theResult___sfd__h476928 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908 = - (guard__h468382 == 2'b0) ? - _theResult___snd__h476405[56:34] : + (guard__h468383 == 2'b0) ? + _theResult___snd__h476406[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h476927 : - _theResult___snd__h476405[56:34]) ; + _theResult___sfd__h476928 : + _theResult___snd__h476406[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10022 = - (_theResult___fst_exp__h584613 == 11'd2047) ? + (_theResult___fst_exp__h584614 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21648,10 +21668,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard76653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10049 = - (_theResult___fst_exp__h603023 == 11'd2047) ? + (_theResult___fst_exp__h603024 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21659,10 +21679,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard95034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10585 = - (_theResult___fst_exp__h563719 == 11'd2047) ? + (_theResult___fst_exp__h563720 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21670,10 +21690,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55729_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_guard55730_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10791 = - (_theResult___fst_exp__h545309 == 11'd2047) ? + (_theResult___fst_exp__h545310 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21681,10 +21701,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37348_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard37349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10818 = - (_theResult___fst_exp__h563719 == 11'd2047) ? + (_theResult___fst_exp__h563720 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21692,10 +21712,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard55730_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9100 = - (_theResult___fst_exp__h524866 == 11'd2047) ? + (_theResult___fst_exp__h524867 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21703,10 +21723,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16876_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_guard16877_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9815 = - (_theResult___fst_exp__h603023 == 11'd2047) ? + (_theResult___fst_exp__h603024 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21714,14 +21734,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95033_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_guard95034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059 = - (_theResult____h658374 == 16'd0 && + (_theResult____h658376 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h658945 : - _theResult____h658374 ; + enabled_ints__h658947 : + _theResult____h658376 ; assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13287 = IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[1] || @@ -21783,7 +21803,7 @@ module mkCore(CLK, checkForException___d13943[4] || csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14036 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10052 = - (f3_exp__h565366 == 8'd0) ? + (f3_exp__h565367 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21793,85 +21813,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10024) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10051 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10053 = - (f3_exp__h565366 == 8'd255 && f3_sfd__h565367 != 23'd0 || - (f3_exp__h565366 == 8'd255 || f3_exp__h565366 == 8'd0) && - f3_sfd__h565367 == 23'd0) ? + (f3_exp__h565367 == 8'd255 && f3_sfd__h565368 != 23'd0 || + (f3_exp__h565367 == 8'd255 || f3_exp__h565367 == 8'd0) && + f3_sfd__h565368 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10052 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 = - ((f2_exp__h526062 == 8'd0) ? - (f2_sfd__h526063[22] ? + ((f2_exp__h526063 == 8'd0) ? + (f2_sfd__h526064[22] ? 6'd2 : - (f2_sfd__h526063[21] ? + (f2_sfd__h526064[21] ? 6'd3 : - (f2_sfd__h526063[20] ? + (f2_sfd__h526064[20] ? 6'd4 : - (f2_sfd__h526063[19] ? + (f2_sfd__h526064[19] ? 6'd5 : - (f2_sfd__h526063[18] ? + (f2_sfd__h526064[18] ? 6'd6 : - (f2_sfd__h526063[17] ? + (f2_sfd__h526064[17] ? 6'd7 : - (f2_sfd__h526063[16] ? + (f2_sfd__h526064[16] ? 6'd8 : - (f2_sfd__h526063[15] ? + (f2_sfd__h526064[15] ? 6'd9 : - (f2_sfd__h526063[14] ? + (f2_sfd__h526064[14] ? 6'd10 : - (f2_sfd__h526063[13] ? + (f2_sfd__h526064[13] ? 6'd11 : - (f2_sfd__h526063[12] ? + (f2_sfd__h526064[12] ? 6'd12 : - (f2_sfd__h526063[11] ? + (f2_sfd__h526064[11] ? 6'd13 : - (f2_sfd__h526063[10] ? + (f2_sfd__h526064[10] ? 6'd14 : - (f2_sfd__h526063[9] ? + (f2_sfd__h526064[9] ? 6'd15 : - (f2_sfd__h526063[8] ? + (f2_sfd__h526064[8] ? 6'd16 : - (f2_sfd__h526063[7] ? + (f2_sfd__h526064[7] ? 6'd17 : - (f2_sfd__h526063[6] ? + (f2_sfd__h526064[6] ? 6'd18 : - (f2_sfd__h526063[5] ? + (f2_sfd__h526064[5] ? 6'd19 : - (f2_sfd__h526063[4] ? + (f2_sfd__h526064[4] ? 6'd20 : - (f2_sfd__h526063[3] ? + (f2_sfd__h526064[3] ? 6'd21 : - (f2_sfd__h526063[2] ? + (f2_sfd__h526064[2] ? 6'd22 : - (f2_sfd__h526063[1] ? + (f2_sfd__h526064[1] ? 6'd23 : - (f2_sfd__h526063[0] ? + (f2_sfd__h526064[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10589 = - (f2_exp__h526062 == 8'd255 && f2_sfd__h526063 != 23'd0 || - (f2_exp__h526062 == 8'd255 || f2_exp__h526062 == 8'd0) && - f2_sfd__h526063 == 23'd0) ? + (f2_exp__h526063 == 8'd255 && f2_sfd__h526064 != 23'd0 || + (f2_exp__h526063 == 8'd255 || f2_exp__h526063 == 8'd0) && + f2_sfd__h526064 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h526062 == 8'd0) ? + ((f2_exp__h526063 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10244 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10587) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10766 = - (f2_exp__h526062 == 8'd255 && f2_sfd__h526063 != 23'd0) ? - _theResult___snd_fst_sfd__h526378 : - _theResult___fst_sfd__h564518 ; + (f2_exp__h526063 == 8'd255 && f2_sfd__h526064 != 23'd0) ? + _theResult___snd_fst_sfd__h526379 : + _theResult___fst_sfd__h564519 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10767 = - { (f2_exp__h526062 == 8'd255) ? + { (f2_exp__h526063 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h564514, + _theResult___fst_exp__h564515, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10766 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10821 = - (f2_exp__h526062 == 8'd0) ? + (f2_exp__h526063 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21881,15 +21901,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10793) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10820 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10822 = - (f2_exp__h526062 == 8'd255 && f2_sfd__h526063 != 23'd0 || - (f2_exp__h526062 == 8'd255 || f2_exp__h526062 == 8'd0) && - f2_sfd__h526063 == 23'd0) ? + (f2_exp__h526063 == 8'd255 && f2_sfd__h526064 != 23'd0 || + (f2_exp__h526063 == 8'd255 || f2_exp__h526063 == 8'd0) && + f2_sfd__h526064 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10821 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10877 = - (f1_exp__h487068 == 8'd0) ? + (f1_exp__h487069 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[4] : @@ -21897,7 +21917,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10918 = - (f2_exp__h526062 == 8'd0) ? + (f2_exp__h526063 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[4] : @@ -21905,7 +21925,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10962 = - (f3_exp__h565366 == 8'd0) ? + (f3_exp__h565367 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[4] : @@ -21913,7 +21933,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10977 = - (f1_exp__h487068 == 8'd0) ? + (f1_exp__h487069 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[3] : @@ -21921,7 +21941,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 = - (f2_exp__h526062 == 8'd0) ? + (f2_exp__h526063 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[3] : @@ -21929,7 +21949,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10998 = - (f3_exp__h565366 == 8'd0) ? + (f3_exp__h565367 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[3] : @@ -21937,208 +21957,208 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11017 = - (f1_exp__h487068 == 8'd0) ? + (f1_exp__h487069 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11015 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11031 = - (f2_exp__h526062 == 8'd0) ? + (f2_exp__h526063 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11029 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11046 = - (f3_exp__h565366 == 8'd0) ? + (f3_exp__h565367 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11044 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11063 = - (f1_exp__h487068 == 8'd0) ? + (f1_exp__h487069 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11061 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11075 = - (f2_exp__h526062 == 8'd0) ? + (f2_exp__h526063 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11073 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11088 = - (f3_exp__h565366 == 8'd0) ? + (f3_exp__h565367 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11086 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11105 = - (f1_exp__h487068 == 8'd0) ? + (f1_exp__h487069 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11103 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11117 = - (f2_exp__h526062 == 8'd0) ? + (f2_exp__h526063 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11115 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11130 = - (f3_exp__h565366 == 8'd0) ? + (f3_exp__h565367 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11128 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 = - ((f1_exp__h487068 == 8'd0) ? - (f1_sfd__h487069[22] ? + ((f1_exp__h487069 == 8'd0) ? + (f1_sfd__h487070[22] ? 6'd2 : - (f1_sfd__h487069[21] ? + (f1_sfd__h487070[21] ? 6'd3 : - (f1_sfd__h487069[20] ? + (f1_sfd__h487070[20] ? 6'd4 : - (f1_sfd__h487069[19] ? + (f1_sfd__h487070[19] ? 6'd5 : - (f1_sfd__h487069[18] ? + (f1_sfd__h487070[18] ? 6'd6 : - (f1_sfd__h487069[17] ? + (f1_sfd__h487070[17] ? 6'd7 : - (f1_sfd__h487069[16] ? + (f1_sfd__h487070[16] ? 6'd8 : - (f1_sfd__h487069[15] ? + (f1_sfd__h487070[15] ? 6'd9 : - (f1_sfd__h487069[14] ? + (f1_sfd__h487070[14] ? 6'd10 : - (f1_sfd__h487069[13] ? + (f1_sfd__h487070[13] ? 6'd11 : - (f1_sfd__h487069[12] ? + (f1_sfd__h487070[12] ? 6'd12 : - (f1_sfd__h487069[11] ? + (f1_sfd__h487070[11] ? 6'd13 : - (f1_sfd__h487069[10] ? + (f1_sfd__h487070[10] ? 6'd14 : - (f1_sfd__h487069[9] ? + (f1_sfd__h487070[9] ? 6'd15 : - (f1_sfd__h487069[8] ? + (f1_sfd__h487070[8] ? 6'd16 : - (f1_sfd__h487069[7] ? + (f1_sfd__h487070[7] ? 6'd17 : - (f1_sfd__h487069[6] ? + (f1_sfd__h487070[6] ? 6'd18 : - (f1_sfd__h487069[5] ? + (f1_sfd__h487070[5] ? 6'd19 : - (f1_sfd__h487069[4] ? + (f1_sfd__h487070[4] ? 6'd20 : - (f1_sfd__h487069[3] ? + (f1_sfd__h487070[3] ? 6'd21 : - (f1_sfd__h487069[2] ? + (f1_sfd__h487070[2] ? 6'd22 : - (f1_sfd__h487069[1] ? + (f1_sfd__h487070[1] ? 6'd23 : - (f1_sfd__h487069[0] ? + (f1_sfd__h487070[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9104 = - (f1_exp__h487068 == 8'd255 && f1_sfd__h487069 != 23'd0 || - (f1_exp__h487068 == 8'd255 || f1_exp__h487068 == 8'd0) && - f1_sfd__h487069 == 23'd0) ? + (f1_exp__h487069 == 8'd255 && f1_sfd__h487070 != 23'd0 || + (f1_exp__h487069 == 8'd255 || f1_exp__h487069 == 8'd0) && + f1_sfd__h487070 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h487068 == 8'd0) ? + ((f1_exp__h487069 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8759 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9102) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9287 = - (f1_exp__h487068 == 8'd255 && f1_sfd__h487069 != 23'd0) ? - _theResult___snd_fst_sfd__h487384 : - _theResult___fst_sfd__h525665 ; + (f1_exp__h487069 == 8'd255 && f1_sfd__h487070 != 23'd0) ? + _theResult___snd_fst_sfd__h487385 : + _theResult___fst_sfd__h525666 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9288 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9104, - (f1_exp__h487068 == 8'd255) ? + (f1_exp__h487069 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h525661, + _theResult___fst_exp__h525662, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9287 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 = - ((f3_exp__h565366 == 8'd0) ? - (f3_sfd__h565367[22] ? + ((f3_exp__h565367 == 8'd0) ? + (f3_sfd__h565368[22] ? 6'd2 : - (f3_sfd__h565367[21] ? + (f3_sfd__h565368[21] ? 6'd3 : - (f3_sfd__h565367[20] ? + (f3_sfd__h565368[20] ? 6'd4 : - (f3_sfd__h565367[19] ? + (f3_sfd__h565368[19] ? 6'd5 : - (f3_sfd__h565367[18] ? + (f3_sfd__h565368[18] ? 6'd6 : - (f3_sfd__h565367[17] ? + (f3_sfd__h565368[17] ? 6'd7 : - (f3_sfd__h565367[16] ? + (f3_sfd__h565368[16] ? 6'd8 : - (f3_sfd__h565367[15] ? + (f3_sfd__h565368[15] ? 6'd9 : - (f3_sfd__h565367[14] ? + (f3_sfd__h565368[14] ? 6'd10 : - (f3_sfd__h565367[13] ? + (f3_sfd__h565368[13] ? 6'd11 : - (f3_sfd__h565367[12] ? + (f3_sfd__h565368[12] ? 6'd12 : - (f3_sfd__h565367[11] ? + (f3_sfd__h565368[11] ? 6'd13 : - (f3_sfd__h565367[10] ? + (f3_sfd__h565368[10] ? 6'd14 : - (f3_sfd__h565367[9] ? + (f3_sfd__h565368[9] ? 6'd15 : - (f3_sfd__h565367[8] ? + (f3_sfd__h565368[8] ? 6'd16 : - (f3_sfd__h565367[7] ? + (f3_sfd__h565368[7] ? 6'd17 : - (f3_sfd__h565367[6] ? + (f3_sfd__h565368[6] ? 6'd18 : - (f3_sfd__h565367[5] ? + (f3_sfd__h565368[5] ? 6'd19 : - (f3_sfd__h565367[4] ? + (f3_sfd__h565368[4] ? 6'd20 : - (f3_sfd__h565367[3] ? + (f3_sfd__h565368[3] ? 6'd21 : - (f3_sfd__h565367[2] ? + (f3_sfd__h565368[2] ? 6'd22 : - (f3_sfd__h565367[1] ? + (f3_sfd__h565368[1] ? 6'd23 : - (f3_sfd__h565367[0] ? + (f3_sfd__h565368[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9819 = - (f3_exp__h565366 == 8'd255 && f3_sfd__h565367 != 23'd0 || - (f3_exp__h565366 == 8'd255 || f3_exp__h565366 == 8'd0) && - f3_sfd__h565367 == 23'd0) ? + (f3_exp__h565367 == 8'd255 && f3_sfd__h565368 != 23'd0 || + (f3_exp__h565367 == 8'd255 || f3_exp__h565367 == 8'd0) && + f3_sfd__h565368 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h565366 == 8'd0) ? + ((f3_exp__h565367 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9474 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9817) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9996 = - (f3_exp__h565366 == 8'd255 && f3_sfd__h565367 != 23'd0) ? - _theResult___snd_fst_sfd__h565682 : - _theResult___fst_sfd__h603822 ; + (f3_exp__h565367 == 8'd255 && f3_sfd__h565368 != 23'd0) ? + _theResult___snd_fst_sfd__h565683 : + _theResult___fst_sfd__h603823 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9997 = - { (f3_exp__h565366 == 8'd255) ? + { (f3_exp__h565367 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h603818, + _theResult___fst_exp__h603819, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9996 } ; assign IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1879 = IF_coreFix_memExe_dTlb_procResp__742_BIT_182_7_ETC___d1868 ? @@ -22344,7 +22364,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10244 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 || - _theResult___fst_exp__h545309 == 11'd2047) ? + _theResult___fst_exp__h545310 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22352,12 +22372,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37348_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; + CASE_guard37349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8759 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 || - _theResult___fst_exp__h506456 == 11'd2047) ? + _theResult___fst_exp__h506457 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -22365,12 +22385,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98495_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_guard98496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9474 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 || - _theResult___fst_exp__h584613 == 11'd2047) ? + _theResult___fst_exp__h584614 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22378,7 +22398,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76652_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_guard76653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3__ETC___d13478 = IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] ? @@ -22854,25 +22874,7 @@ module mkCore(CLK, 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_0_deq_data__4635_BITS_329_T_ETC___d15595 = - { (rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[97:96] == 2'd0) ? - { 2'd0, rob$deqPort_0_deq_data[95:32] } : - ((rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[97:96] == 2'd1) ? - { 2'd1, rob$deqPort_0_deq_data[95:32] } : - { 2'd2, - (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h730624 : - rob$deqPort_0_deq_data[95:32] }), - 5'h0A, - rob$deqPort_0_deq_data[26], - 64'hAAAAAAAAAAAAAAAA, - x_prv__h731271, - 64'hAAAAAAAAAAAAAAAA, - x__h734674, - 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign IF_NOT_rob_deqPort_1_deq_data__5631_BIT_25_563_ETC___d15985 = + assign IF_NOT_rob_deqPort_1_deq_data__5642_BIT_25_564_ETC___d15998 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -22917,48 +22919,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11015 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[2] : - _theResult___fst_exp__h525649 == 11'd2047 && - _theResult___fst_sfd__h525650 == 52'd0 ; + _theResult___fst_exp__h525650 == 11'd2047 && + _theResult___fst_sfd__h525651 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11029 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[2] : - _theResult___fst_exp__h564502 == 11'd2047 && - _theResult___fst_sfd__h564503 == 52'd0 ; + _theResult___fst_exp__h564503 == 11'd2047 && + _theResult___fst_sfd__h564504 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11044 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[2] : - _theResult___fst_exp__h603806 == 11'd2047 && - _theResult___fst_sfd__h603807 == 52'd0 ; + _theResult___fst_exp__h603807 == 11'd2047 && + _theResult___fst_sfd__h603808 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11061 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[1] : - _theResult___fst_exp__h524866 == 11'd0 && - guard__h516876 != 2'b0 ; + _theResult___fst_exp__h524867 == 11'd0 && + guard__h516877 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11073 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[1] : - _theResult___fst_exp__h563719 == 11'd0 && - guard__h555729 != 2'b0 ; + _theResult___fst_exp__h563720 == 11'd0 && + guard__h555730 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11086 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[1] : - _theResult___fst_exp__h603023 == 11'd0 && - guard__h595033 != 2'b0 ; + _theResult___fst_exp__h603024 == 11'd0 && + guard__h595034 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11103 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[0] : - _theResult___fst_exp__h524866 != 11'd2047 && - guard__h516876 != 2'b0 ; + _theResult___fst_exp__h524867 != 11'd2047 && + guard__h516877 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11115 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[0] : - _theResult___fst_exp__h563719 != 11'd2047 && - guard__h555729 != 2'b0 ; + _theResult___fst_exp__h563720 != 11'd2047 && + guard__h555730 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11128 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[0] : - _theResult___fst_exp__h603023 != 11'd2047 && - guard__h595033 != 2'b0 ; + _theResult___fst_exp__h603024 != 11'd2047 && + guard__h595034 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9061 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -22998,35 +23000,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5199 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - ((_theResult___fst_exp__h376382 == 8'd255) ? + ((_theResult___fst_exp__h376383 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184) : - ((_theResult___fst_exp__h385067 == 8'd255) ? + ((_theResult___fst_exp__h385068 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - ((_theResult___fst_exp__h376382 == 8'd255) ? + ((_theResult___fst_exp__h376383 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227) : - ((_theResult___fst_exp__h385067 == 8'd255) ? + ((_theResult___fst_exp__h385068 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5327 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298[2] : - _theResult___fst_exp__h385615 == 8'd255 && - _theResult___fst_sfd__h385616 == 23'd0 ; + _theResult___fst_exp__h385616 == 8'd255 && + _theResult___fst_sfd__h385617 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5340 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298[1] : - _theResult___fst_exp__h385067 == 8'd0 && - guard__h376990 != 2'b0 ; + _theResult___fst_exp__h385068 == 8'd0 && + guard__h376991 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5353 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298[0] : - _theResult___fst_exp__h385067 != 8'd255 && - guard__h376990 != 2'b0 ; + _theResult___fst_exp__h385068 != 8'd255 && + guard__h376991 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] == 8'd0) ? @@ -23036,35 +23038,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6591 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - ((_theResult___fst_exp__h422079 == 8'd255) ? + ((_theResult___fst_exp__h422080 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576) : - ((_theResult___fst_exp__h430764 == 8'd255) ? + ((_theResult___fst_exp__h430765 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - ((_theResult___fst_exp__h422079 == 8'd255) ? + ((_theResult___fst_exp__h422080 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619) : - ((_theResult___fst_exp__h430764 == 8'd255) ? + ((_theResult___fst_exp__h430765 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6719 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690[2] : - _theResult___fst_exp__h431312 == 8'd255 && - _theResult___fst_sfd__h431313 == 23'd0 ; + _theResult___fst_exp__h431313 == 8'd255 && + _theResult___fst_sfd__h431314 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6732 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690[1] : - _theResult___fst_exp__h430764 == 8'd0 && - guard__h422687 != 2'b0 ; + _theResult___fst_exp__h430765 == 8'd0 && + guard__h422688 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6745 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690[0] : - _theResult___fst_exp__h430764 != 8'd255 && - guard__h422687 != 2'b0 ; + _theResult___fst_exp__h430765 != 8'd255 && + guard__h422688 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] == 8'd0) ? @@ -23074,50 +23076,49 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7983 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - ((_theResult___fst_exp__h467774 == 8'd255) ? + ((_theResult___fst_exp__h467775 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968) : - ((_theResult___fst_exp__h476459 == 8'd255) ? + ((_theResult___fst_exp__h476460 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - ((_theResult___fst_exp__h467774 == 8'd255) ? + ((_theResult___fst_exp__h467775 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011) : - ((_theResult___fst_exp__h476459 == 8'd255) ? + ((_theResult___fst_exp__h476460 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8111 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082[2] : - _theResult___fst_exp__h477007 == 8'd255 && - _theResult___fst_sfd__h477008 == 23'd0 ; + _theResult___fst_exp__h477008 == 8'd255 && + _theResult___fst_sfd__h477009 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8124 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082[1] : - _theResult___fst_exp__h476459 == 8'd0 && - guard__h468382 != 2'b0 ; + _theResult___fst_exp__h476460 == 8'd0 && + guard__h468383 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8137 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082[0] : - _theResult___fst_exp__h476459 != 8'd255 && - guard__h468382 != 2'b0 ; + _theResult___fst_exp__h476460 != 8'd255 && + guard__h468383 != 2'b0 ; assign IF_checkForException_3243_BIT_4_3244_THEN_IF_c_ETC___d13394 = checkForException___d13243[4] ? CASE_checkForException_3243_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_commitStage_commitTrap_4643_BIT_36_4891_THE_ETC___d15228 = - { trap_val__h717409, - CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257, + assign IF_commitStage_f_rob_data_first__5067_BITS_97__ETC___d15238 = + { CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, commitStage_f_rob_data$D_OUT[95:32], 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h720451, - pc__h720352, - x__h722594, - x__h722786, + x_prv__h721432, + pc__h721332, + x__h723590, + x__h723782, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2388_ETC___d12421 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -23772,8 +23773,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9997 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12933 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h653951 : - w__h653946 ; + result__h653953 : + w__h653948 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2116 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23795,39 +23796,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2240 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h201994 : + n___1__h201995 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2553 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23880,7 +23881,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2599 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h200591 : + x__h200592 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2182 ? 64'd0 : 64'd1) ; @@ -23892,7 +23893,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3158 = - _theResult_____2__h300941 == v__h300361 ; + _theResult_____2__h300942 == v__h300362 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3238 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23901,7 +23902,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3260 = - _theResult_____2__h308937 == v__h303706 ; + _theResult_____2__h308938 == v__h303707 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3280 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23930,14 +23931,14 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h306571 } ; + x__h306572 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3104 = - !MUX_flush_reservation$write_1__SEL_2 && + !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3112 = - MUX_flush_reservation$write_1__SEL_2 ? + MUX_flush_reservation$write_1__SEL_1 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -24028,35 +24029,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2027 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2027, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h197390 : + n__h197391 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -24084,7 +24085,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3432 = - _theResult_____2__h314931 == v__h314220 ; + _theResult_____2__h314932 == v__h314221 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3505 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24093,7 +24094,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3528 = - _theResult_____2__h322785 == v__h318096 ; + _theResult_____2__h322786 == v__h318097 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3547 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24245,7 +24246,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3850 = - _theResult_____2__h336354 == v__h335922 ; + _theResult_____2__h336355 == v__h335923 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3843 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -24294,7 +24295,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) : IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3756 = - _theResult_____2__h333129 == v__h332697 ; + _theResult_____2__h333130 == v__h332698 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3749 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -24326,10 +24327,10 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h735290 : + upd__h736290 : csrf_minstret_ehr_data_rl ; - assign IF_csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_c_ETC___d15221 = - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 ? + assign IF_csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_c_ETC___d15232 = + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 ? { 43'd8192, csrf_mxr_reg, csrf_sum_reg, @@ -24394,8 +24395,8 @@ module mkCore(CLK, assign IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14199 = IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14192 || rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; @@ -24411,8 +24412,8 @@ module mkCore(CLK, IF_fetchStage_RDY_pipelines_1_first__3000_AND__ETC___d14078 && (IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14313 || rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && regRenamingTable$RDY_rename_1_getRename && + regRenamingTable$RDY_rename_1_claimRename && fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14323) ; assign IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14613 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && @@ -24452,17 +24453,17 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15975 = - rob$deqPort_0_canDeq ? y_avValue_fst__h738888 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15994 = + assign IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d15988 = + rob$deqPort_0_canDeq ? y_avValue_fst__h739906 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d16007 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h739363 : + y_avValue_snd_snd_snd_fst__h740381 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__4635_BITS_329_TO_32_ETC___d15494 = + assign IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15505 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? csrf_sepc_csr : csrf_mepc_csr ; - assign IF_rob_deqPort_0_deq_data__4635_BITS_329_TO_32_ETC___d15585 = + assign IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15596 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? { csrf_mpp_reg, 3'd0, @@ -24482,55 +24483,55 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_rob_deqPort_0_deq_data__4635_BITS_97_TO_96__ETC___d14808 = - { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256, + assign IF_rob_deqPort_0_deq_data__4646_BITS_97_TO_96__ETC___d14819 = + { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, rob$deqPort_0_deq_data[95:32] } ; - assign IF_rob_deqPort_1_canDeq__5628_THEN_IF_NOT_rob__ETC___d15986 = + assign IF_rob_deqPort_1_canDeq__5639_THEN_IF_NOT_rob__ETC___d15999 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__5631_BIT_25_563_ETC___d15985 : + IF_NOT_rob_deqPort_1_deq_data__5642_BIT_25_564_ETC___d15998 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin04307_BIT_33_THEN_2_ELSE_0__q65 = - sfdin__h404307[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin16027_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h516027[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin22073_BIT_33_THEN_2_ELSE_0__q75 = - sfdin__h422073[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin50002_BIT_33_THEN_2_ELSE_0__q100 = - sfdin__h450002[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin54880_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h554880[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin58610_BIT_33_THEN_2_ELSE_0__q30 = - sfdin__h358610[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin67768_BIT_33_THEN_2_ELSE_0__q110 = - sfdin__h467768[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin76376_BIT_33_THEN_2_ELSE_0__q40 = - sfdin__h376376[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin94184_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h594184[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd02969_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h602969[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06407_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h506407[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd12920_BIT_33_THEN_2_ELSE_0__q67 = - _theResult___snd__h412920[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd24812_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h524812[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30710_BIT_33_THEN_2_ELSE_0__q80 = - _theResult___snd__h430710[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd45260_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h545260[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58615_BIT_33_THEN_2_ELSE_0__q102 = - _theResult___snd__h458615[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd63665_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h563665[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd67223_BIT_33_THEN_2_ELSE_0__q32 = - _theResult___snd__h367223[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76405_BIT_33_THEN_2_ELSE_0__q115 = - _theResult___snd__h476405[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84564_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h584564[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd85013_BIT_33_THEN_2_ELSE_0__q45 = - _theResult___snd__h385013[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin04308_BIT_33_THEN_2_ELSE_0__q65 = + sfdin__h404308[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin16028_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h516028[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin22074_BIT_33_THEN_2_ELSE_0__q75 = + sfdin__h422074[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin50003_BIT_33_THEN_2_ELSE_0__q100 = + sfdin__h450003[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin54881_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h554881[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin58611_BIT_33_THEN_2_ELSE_0__q30 = + sfdin__h358611[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin67769_BIT_33_THEN_2_ELSE_0__q110 = + sfdin__h467769[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin76377_BIT_33_THEN_2_ELSE_0__q40 = + sfdin__h376377[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin94185_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h594185[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02970_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h602970[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06408_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h506408[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12921_BIT_33_THEN_2_ELSE_0__q67 = + _theResult___snd__h412921[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd24813_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h524813[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30711_BIT_33_THEN_2_ELSE_0__q80 = + _theResult___snd__h430711[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd45261_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h545261[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58616_BIT_33_THEN_2_ELSE_0__q102 = + _theResult___snd__h458616[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd63666_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h563666[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd67224_BIT_33_THEN_2_ELSE_0__q32 = + _theResult___snd__h367224[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76406_BIT_33_THEN_2_ELSE_0__q115 = + _theResult___snd__h476406[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84565_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h584565[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd85014_BIT_33_THEN_2_ELSE_0__q45 = + _theResult___snd__h385014[33] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5321 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? @@ -24621,138 +24622,138 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[15] && !checkForException___d13943[4] && NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13968 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__5623_5624_OR__ETC___d15991 = - (fflags__h742192 & csrf_fflags_reg) != fflags__h742192 || + assign NOT_IF_NOT_rob_deqPort_0_canDeq__5634_5635_OR__ETC___d16004 = + (fflags__h743227 & csrf_fflags_reg) != fflags__h743227 || csrf_fs_reg != 2'b11 && - (IF_rob_deqPort_1_canDeq__5628_THEN_IF_NOT_rob__ETC___d15986 || - fflags__h742192 != 5'd0) ; + (IF_rob_deqPort_1_canDeq__5639_THEN_IF_NOT_rob__ETC___d15999 || + fflags__h743227 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171 = - !f2_sfd__h526063[21] && !f2_sfd__h526063[20] && - !f2_sfd__h526063[19] && - !f2_sfd__h526063[18] && - !f2_sfd__h526063[17] && - !f2_sfd__h526063[16] && - !f2_sfd__h526063[15] && - !f2_sfd__h526063[14] && - !f2_sfd__h526063[13] && - !f2_sfd__h526063[12] && - !f2_sfd__h526063[11] && - !f2_sfd__h526063[10] && - !f2_sfd__h526063[9] && - !f2_sfd__h526063[8] && - !f2_sfd__h526063[7] && - !f2_sfd__h526063[6] && - !f2_sfd__h526063[5] && - !f2_sfd__h526063[4] && - !f2_sfd__h526063[3] && - !f2_sfd__h526063[2] && - !f2_sfd__h526063[1] && - !f2_sfd__h526063[0] ; + !f2_sfd__h526064[21] && !f2_sfd__h526064[20] && + !f2_sfd__h526064[19] && + !f2_sfd__h526064[18] && + !f2_sfd__h526064[17] && + !f2_sfd__h526064[16] && + !f2_sfd__h526064[15] && + !f2_sfd__h526064[14] && + !f2_sfd__h526064[13] && + !f2_sfd__h526064[12] && + !f2_sfd__h526064[11] && + !f2_sfd__h526064[10] && + !f2_sfd__h526064[9] && + !f2_sfd__h526064[8] && + !f2_sfd__h526064[7] && + !f2_sfd__h526064[6] && + !f2_sfd__h526064[5] && + !f2_sfd__h526064[4] && + !f2_sfd__h526064[3] && + !f2_sfd__h526064[2] && + !f2_sfd__h526064[1] && + !f2_sfd__h526064[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10880 = - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 == 23'd0) && - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 != 23'd0) && - (f1_exp__h487068 != 8'd0 || f1_sfd__h487069 != 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 == 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 != 23'd0) && + (f1_exp__h487069 != 8'd0 || f1_sfd__h487070 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10877 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10922 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10880 | - ((f2_exp__h526062 != 8'd255 || f2_sfd__h526063 == 23'd0) && - (f2_exp__h526062 != 8'd255 || f2_sfd__h526063 != 23'd0) && - (f2_exp__h526062 != 8'd0 || f2_sfd__h526063 != 23'd0) && + ((f2_exp__h526063 != 8'd255 || f2_sfd__h526064 == 23'd0) && + (f2_exp__h526063 != 8'd255 || f2_sfd__h526064 != 23'd0) && + (f2_exp__h526063 != 8'd0 || f2_sfd__h526064 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10918) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10980 = - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 == 23'd0) && - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 != 23'd0) && - (f1_exp__h487068 != 8'd0 || f1_sfd__h487069 != 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 == 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 != 23'd0) && + (f1_exp__h487069 != 8'd0 || f1_sfd__h487070 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10977 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10991 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10980 | - ((f2_exp__h526062 != 8'd255 || f2_sfd__h526063 == 23'd0) && - (f2_exp__h526062 != 8'd255 || f2_sfd__h526063 != 23'd0) && - (f2_exp__h526062 != 8'd0 || f2_sfd__h526063 != 23'd0) && + ((f2_exp__h526063 != 8'd255 || f2_sfd__h526064 == 23'd0) && + (f2_exp__h526063 != 8'd255 || f2_sfd__h526064 != 23'd0) && + (f2_exp__h526063 != 8'd0 || f2_sfd__h526064 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11020 = - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 == 23'd0) && - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 != 23'd0) && - (f1_exp__h487068 != 8'd0 || f1_sfd__h487069 != 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 == 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 != 23'd0) && + (f1_exp__h487069 != 8'd0 || f1_sfd__h487070 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11017 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11035 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11020 | - ((f2_exp__h526062 != 8'd255 || f2_sfd__h526063 == 23'd0) && - (f2_exp__h526062 != 8'd255 || f2_sfd__h526063 != 23'd0) && - (f2_exp__h526062 != 8'd0 || f2_sfd__h526063 != 23'd0) && + ((f2_exp__h526063 != 8'd255 || f2_sfd__h526064 == 23'd0) && + (f2_exp__h526063 != 8'd255 || f2_sfd__h526064 != 23'd0) && + (f2_exp__h526063 != 8'd0 || f2_sfd__h526064 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11031) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11066 = - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 == 23'd0) && - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 != 23'd0) && - (f1_exp__h487068 != 8'd0 || f1_sfd__h487069 != 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 == 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 != 23'd0) && + (f1_exp__h487069 != 8'd0 || f1_sfd__h487070 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11063 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11079 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11066 | - ((f2_exp__h526062 != 8'd255 || f2_sfd__h526063 == 23'd0) && - (f2_exp__h526062 != 8'd255 || f2_sfd__h526063 != 23'd0) && - (f2_exp__h526062 != 8'd0 || f2_sfd__h526063 != 23'd0) && + ((f2_exp__h526063 != 8'd255 || f2_sfd__h526064 == 23'd0) && + (f2_exp__h526063 != 8'd255 || f2_sfd__h526064 != 23'd0) && + (f2_exp__h526063 != 8'd0 || f2_sfd__h526064 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11075) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11108 = - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 == 23'd0) && - (f1_exp__h487068 != 8'd255 || f1_sfd__h487069 != 23'd0) && - (f1_exp__h487068 != 8'd0 || f1_sfd__h487069 != 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 == 23'd0) && + (f1_exp__h487069 != 8'd255 || f1_sfd__h487070 != 23'd0) && + (f1_exp__h487069 != 8'd0 || f1_sfd__h487070 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11105 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11121 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11108 | - ((f2_exp__h526062 != 8'd255 || f2_sfd__h526063 == 23'd0) && - (f2_exp__h526062 != 8'd255 || f2_sfd__h526063 != 23'd0) && - (f2_exp__h526062 != 8'd0 || f2_sfd__h526063 != 23'd0) && + ((f2_exp__h526063 != 8'd255 || f2_sfd__h526064 == 23'd0) && + (f2_exp__h526063 != 8'd255 || f2_sfd__h526064 != 23'd0) && + (f2_exp__h526063 != 8'd0 || f2_sfd__h526064 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11117) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671 = - !f1_sfd__h487069[21] && !f1_sfd__h487069[20] && - !f1_sfd__h487069[19] && - !f1_sfd__h487069[18] && - !f1_sfd__h487069[17] && - !f1_sfd__h487069[16] && - !f1_sfd__h487069[15] && - !f1_sfd__h487069[14] && - !f1_sfd__h487069[13] && - !f1_sfd__h487069[12] && - !f1_sfd__h487069[11] && - !f1_sfd__h487069[10] && - !f1_sfd__h487069[9] && - !f1_sfd__h487069[8] && - !f1_sfd__h487069[7] && - !f1_sfd__h487069[6] && - !f1_sfd__h487069[5] && - !f1_sfd__h487069[4] && - !f1_sfd__h487069[3] && - !f1_sfd__h487069[2] && - !f1_sfd__h487069[1] && - !f1_sfd__h487069[0] ; + !f1_sfd__h487070[21] && !f1_sfd__h487070[20] && + !f1_sfd__h487070[19] && + !f1_sfd__h487070[18] && + !f1_sfd__h487070[17] && + !f1_sfd__h487070[16] && + !f1_sfd__h487070[15] && + !f1_sfd__h487070[14] && + !f1_sfd__h487070[13] && + !f1_sfd__h487070[12] && + !f1_sfd__h487070[11] && + !f1_sfd__h487070[10] && + !f1_sfd__h487070[9] && + !f1_sfd__h487070[8] && + !f1_sfd__h487070[7] && + !f1_sfd__h487070[6] && + !f1_sfd__h487070[5] && + !f1_sfd__h487070[4] && + !f1_sfd__h487070[3] && + !f1_sfd__h487070[2] && + !f1_sfd__h487070[1] && + !f1_sfd__h487070[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401 = - !f3_sfd__h565367[21] && !f3_sfd__h565367[20] && - !f3_sfd__h565367[19] && - !f3_sfd__h565367[18] && - !f3_sfd__h565367[17] && - !f3_sfd__h565367[16] && - !f3_sfd__h565367[15] && - !f3_sfd__h565367[14] && - !f3_sfd__h565367[13] && - !f3_sfd__h565367[12] && - !f3_sfd__h565367[11] && - !f3_sfd__h565367[10] && - !f3_sfd__h565367[9] && - !f3_sfd__h565367[8] && - !f3_sfd__h565367[7] && - !f3_sfd__h565367[6] && - !f3_sfd__h565367[5] && - !f3_sfd__h565367[4] && - !f3_sfd__h565367[3] && - !f3_sfd__h565367[2] && - !f3_sfd__h565367[1] && - !f3_sfd__h565367[0] ; + !f3_sfd__h565368[21] && !f3_sfd__h565368[20] && + !f3_sfd__h565368[19] && + !f3_sfd__h565368[18] && + !f3_sfd__h565368[17] && + !f3_sfd__h565368[16] && + !f3_sfd__h565368[15] && + !f3_sfd__h565368[14] && + !f3_sfd__h565368[13] && + !f3_sfd__h565368[12] && + !f3_sfd__h565368[11] && + !f3_sfd__h565368[10] && + !f3_sfd__h565368[9] && + !f3_sfd__h565368[8] && + !f3_sfd__h565368[7] && + !f3_sfd__h565368[6] && + !f3_sfd__h565368[5] && + !f3_sfd__h565368[4] && + !f3_sfd__h565368[3] && + !f3_sfd__h565368[2] && + !f3_sfd__h565368[1] && + !f3_sfd__h565368[0] ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13729 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13727 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3653_AND__ETC___d13675 ; - assign NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14926 = + assign NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d14936 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] == 4'd0 || commitStage_commitTrap[35:32] == 4'd1 || @@ -24766,12 +24767,12 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14933 = - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14926 || + assign NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d14943 = + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d14936 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 = + assign NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd14) && (!commitStage_commitTrap[36] || @@ -24788,11 +24789,35 @@ module mkCore(CLK, (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; - assign NOT_commitStage_rg_run_state_4641_4642_AND_NOT_ETC___d15306 = + assign NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15316 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; + assign NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15327 = + NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15316 && + (rob$deqPort_0_deq_data[329:325] == 5'd0 || + rob$deqPort_0_deq_data[329:325] == 5'd21 || + rob$deqPort_0_deq_data[329:325] == 5'd17 || + rob$deqPort_0_deq_data[329:325] == 5'd18 || + rob$deqPort_0_deq_data[329:325] == 5'd13 || + rob$deqPort_0_deq_data[329:325] == 5'd16 || + rob$deqPort_0_deq_data[329:325] == 5'd15 || + rob$deqPort_0_deq_data[329:325] == 5'd19 || + rob$deqPort_0_deq_data[329:325] == 5'd20) && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14631 ; + assign NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15688 = + NOT_commitStage_rg_run_state_4652_4653_AND_NOT_ETC___d15316 && + rob$deqPort_0_deq_data[329:325] != 5'd0 && + rob$deqPort_0_deq_data[329:325] != 5'd21 && + rob$deqPort_0_deq_data[329:325] != 5'd17 && + rob$deqPort_0_deq_data[329:325] != 5'd18 && + rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[329:325] != 5'd16 && + rob$deqPort_0_deq_data[329:325] != 5'd15 && + rob$deqPort_0_deq_data[329:325] != 5'd19 && + rob$deqPort_0_deq_data[329:325] != 5'd20 && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14631 ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12437 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413) && @@ -25003,7 +25028,7 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ; assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8544 = coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 || - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267 ; + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q269 ; assign NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_memExe_bypassWire_0_wget__586_BITS_70__ETC___d1588) && @@ -25332,7 +25357,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13566 && !csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 && - csr_addr__h662583 != 12'h8FF) ; + csr_addr__h662585 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13666 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -25357,11 +25382,11 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__3022_ULE_1_4997_5039_OR_ETC___d15043 = - !csrf_prv_reg_read__3022_ULE_1___d14997 || + assign NOT_csrf_prv_reg_read__3022_ULE_1_5008_5050_OR_ETC___d15054 = + !csrf_prv_reg_read__3022_ULE_1___d15008 || (commitStage_commitTrap[36] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d14999 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15017) ; + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15010 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15028) ; assign NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d13772 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || @@ -25471,9 +25496,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13566 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h662584 == 5'd0 && - imm__h662585 == 32'd0 || - csr_addr__h662583[11:10] != 2'b11 ; + rs1__h662586 == 5'd0 && + imm__h662587 == 32'd0 || + csr_addr__h662585[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13711 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && @@ -25520,7 +25545,7 @@ module mkCore(CLK, specTagManager$currentSpecBits } ; assign NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14366 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h673430 ; + fallthrough_pc__h673432 ; assign NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13722 = !fetchStage$pipelines_0_first[68] && !checkForException___d13243[4] && @@ -25560,7 +25585,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3775_AND__ETC___d14480 ; assign NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14535 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h689938 ; + fallthrough_pc__h689940 ; assign NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14478 = !fetchStage$pipelines_1_first[68] && !checkForException___d13943[4] && @@ -25590,12 +25615,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -25732,14 +25757,14 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_302_ETC___d13970 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d14139 ; - assign NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_RDY_ETC___d15665 = + assign NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_RDY_ETC___d15676 = (!rob$deqPort_0_canDeq || rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__5631_BIT_25_5632_5_ETC___d15662) ; - assign NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_deq_ETC___d15969 = + NOT_rob_deqPort_1_deq_data__5642_BIT_25_5643_5_ETC___d15673) ; + assign NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_deq_ETC___d15982 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25753,15 +25778,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4635_BITS_329_TO_3_ETC___d15295 = + assign NOT_rob_deqPort_0_deq_data__4646_BITS_329_TO_3_ETC___d15305 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 != + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 != + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__5631_BIT_25_5632_5_ETC___d15662 = + assign NOT_rob_deqPort_1_deq_data__5642_BIT_25_5643_5_ETC___d15673 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -25800,33 +25825,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q28 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3026, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3042 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, - x__h295969 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16407 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16363 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16372 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16363, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16381 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16372, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 } ; + x__h295970 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16420 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16376 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16385 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16376, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16394 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16385, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10246 = - { {4{f2_exp26062_MINUS_127__q176[7]}}, - f2_exp26062_MINUS_127__q176 } ; + { {4{f2_exp26063_MINUS_127__q176[7]}}, + f2_exp26063_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10246 ^ 12'h800) <= @@ -25836,12 +25861,12 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11191 = - b__h608062 * b__h608138 ; + b__h608063 * b__h608139 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11204 = - b__h608062 * b__h608251 ; + b__h608063 * b__h608252 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8761 = - { {4{f1_exp87068_MINUS_127__q136[7]}}, - f1_exp87068_MINUS_127__q136 } ; + { {4{f1_exp87069_MINUS_127__q136[7]}}, + f1_exp87069_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8761 ^ 12'h800) <= @@ -25851,8 +25876,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9476 = - { {4{f3_exp65366_MINUS_127__q153[7]}}, - f3_exp65366_MINUS_127__q153 } ; + { {4{f3_exp65367_MINUS_127__q153[7]}}, + f3_exp65367_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9476 ^ 12'h800) <= @@ -25937,15 +25962,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5269 = { 3'd0, - _theResult___fst_exp__h358616 == 8'd0 && - (sfdin__h358610[56:34] == 23'd0 || guard__h350515 != 2'b0), + _theResult___fst_exp__h358617 == 8'd0 && + (sfdin__h358611[56:34] == 23'd0 || guard__h350516 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h359213 == 8'd255 && - _theResult___fst_sfd__h359214 == 23'd0, + _theResult___fst_exp__h359214 == 8'd255 && + _theResult___fst_sfd__h359215 == 23'd0, 1'd0, - _theResult___fst_exp__h358616 != 8'd255 && - guard__h350515 != 2'b0 } ; + _theResult___fst_exp__h358617 != 8'd255 && + guard__h350516 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5741 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 } ^ @@ -25953,15 +25978,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6661 = { 3'd0, - _theResult___fst_exp__h404313 == 8'd0 && - (sfdin__h404307[56:34] == 23'd0 || guard__h396214 != 2'b0), + _theResult___fst_exp__h404314 == 8'd0 && + (sfdin__h404308[56:34] == 23'd0 || guard__h396215 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h404910 == 8'd255 && - _theResult___fst_sfd__h404911 == 23'd0, + _theResult___fst_exp__h404911 == 8'd255 && + _theResult___fst_sfd__h404912 == 23'd0, 1'd0, - _theResult___fst_exp__h404313 != 8'd255 && - guard__h396214 != 2'b0 } ; + _theResult___fst_exp__h404314 != 8'd255 && + guard__h396215 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7133 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 } ^ @@ -25969,15 +25994,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8053 = { 3'd0, - _theResult___fst_exp__h450008 == 8'd0 && - (sfdin__h450002[56:34] == 23'd0 || guard__h441909 != 2'b0), + _theResult___fst_exp__h450009 == 8'd0 && + (sfdin__h450003[56:34] == 23'd0 || guard__h441910 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h450605 == 8'd255 && - _theResult___fst_sfd__h450606 == 23'd0, + _theResult___fst_exp__h450606 == 8'd255 && + _theResult___fst_sfd__h450607 == 23'd0, 1'd0, - _theResult___fst_exp__h450008 != 8'd255 && - guard__h441909 != 2'b0 } ; + _theResult___fst_exp__h450009 != 8'd255 && + guard__h441910 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10497 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 } ^ @@ -25985,37 +26010,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873 = { 3'd0, - _theResult___fst_exp__h516033 == 11'd0 && - (sfdin__h516027[56:5] == 52'd0 || guard__h507807 != 2'b0), + _theResult___fst_exp__h516034 == 11'd0 && + (sfdin__h516028[56:5] == 52'd0 || guard__h507808 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h516865 == 11'd2047 && - _theResult___fst_sfd__h516866 == 52'd0, + _theResult___fst_exp__h516866 == 11'd2047 && + _theResult___fst_sfd__h516867 == 52'd0, 1'd0, - _theResult___fst_exp__h516033 != 11'd2047 && - guard__h507807 != 2'b0 } ; + _theResult___fst_exp__h516034 != 11'd2047 && + guard__h507808 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914 = { 3'd0, - _theResult___fst_exp__h554886 == 11'd0 && - (sfdin__h554880[56:5] == 52'd0 || guard__h546660 != 2'b0), + _theResult___fst_exp__h554887 == 11'd0 && + (sfdin__h554881[56:5] == 52'd0 || guard__h546661 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h555718 == 11'd2047 && - _theResult___fst_sfd__h555719 == 52'd0, + _theResult___fst_exp__h555719 == 11'd2047 && + _theResult___fst_sfd__h555720 == 52'd0, 1'd0, - _theResult___fst_exp__h554886 != 11'd2047 && - guard__h546660 != 2'b0 } ; + _theResult___fst_exp__h554887 != 11'd2047 && + guard__h546661 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958 = { 3'd0, - _theResult___fst_exp__h594190 == 11'd0 && - (sfdin__h594184[56:5] == 52'd0 || guard__h585964 != 2'b0), + _theResult___fst_exp__h594191 == 11'd0 && + (sfdin__h594185[56:5] == 52'd0 || guard__h585965 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h595022 == 11'd2047 && - _theResult___fst_sfd__h595023 == 52'd0, + _theResult___fst_exp__h595023 == 11'd2047 && + _theResult___fst_sfd__h595024 == 52'd0, 1'd0, - _theResult___fst_exp__h594190 != 11'd2047 && - guard__h585964 != 2'b0 } ; + _theResult___fst_exp__h594191 != 11'd2047 && + guard__h585965 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9012 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 } ^ @@ -26033,15 +26058,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298 = { 3'd0, - _theResult___fst_exp__h376382 == 8'd0 && - (sfdin__h376376[56:34] == 23'd0 || guard__h368154 != 2'b0), + _theResult___fst_exp__h376383 == 8'd0 && + (sfdin__h376377[56:34] == 23'd0 || guard__h368155 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h376979 == 8'd255 && - _theResult___fst_sfd__h376980 == 23'd0, + _theResult___fst_exp__h376980 == 8'd255 && + _theResult___fst_sfd__h376981 == 23'd0, 1'd0, - _theResult___fst_exp__h376382 != 8'd255 && - guard__h368154 != 2'b0 } ; + _theResult___fst_exp__h376383 != 8'd255 && + guard__h368155 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6292 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 } ^ @@ -26049,15 +26074,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690 = { 3'd0, - _theResult___fst_exp__h422079 == 8'd0 && - (sfdin__h422073[56:34] == 23'd0 || guard__h413851 != 2'b0), + _theResult___fst_exp__h422080 == 8'd0 && + (sfdin__h422074[56:34] == 23'd0 || guard__h413852 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h422676 == 8'd255 && - _theResult___fst_sfd__h422677 == 23'd0, + _theResult___fst_exp__h422677 == 8'd255 && + _theResult___fst_sfd__h422678 == 23'd0, 1'd0, - _theResult___fst_exp__h422079 != 8'd255 && - guard__h413851 != 2'b0 } ; + _theResult___fst_exp__h422080 != 8'd255 && + guard__h413852 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7684 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 } ^ @@ -26065,15 +26090,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082 = { 3'd0, - _theResult___fst_exp__h467774 == 8'd0 && - (sfdin__h467768[56:34] == 23'd0 || guard__h459546 != 2'b0), + _theResult___fst_exp__h467775 == 8'd0 && + (sfdin__h467769[56:34] == 23'd0 || guard__h459547 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h468371 == 8'd255 && - _theResult___fst_sfd__h468372 == 23'd0, + _theResult___fst_exp__h468372 == 8'd255 && + _theResult___fst_sfd__h468373 == 23'd0, 1'd0, - _theResult___fst_exp__h467774 != 8'd255 && - guard__h459546 != 2'b0 } ; + _theResult___fst_exp__h467775 != 8'd255 && + guard__h459547 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10200 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 } ^ @@ -26087,37 +26112,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856 = { 3'd0, - _theResult___fst_exp__h506456 == 11'd0 && - guard__h498495 != 2'b0, + _theResult___fst_exp__h506457 == 11'd0 && + guard__h498496 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h507214 == 11'd2047 && - _theResult___fst_sfd__h507215 == 52'd0, + _theResult___fst_exp__h507215 == 11'd2047 && + _theResult___fst_sfd__h507216 == 52'd0, 1'd0, - _theResult___fst_exp__h506456 != 11'd2047 && - guard__h498495 != 2'b0 } ; + _theResult___fst_exp__h506457 != 11'd2047 && + guard__h498496 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897 = { 3'd0, - _theResult___fst_exp__h545309 == 11'd0 && - guard__h537348 != 2'b0, + _theResult___fst_exp__h545310 == 11'd0 && + guard__h537349 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h546067 == 11'd2047 && - _theResult___fst_sfd__h546068 == 52'd0, + _theResult___fst_exp__h546068 == 11'd2047 && + _theResult___fst_sfd__h546069 == 52'd0, 1'd0, - _theResult___fst_exp__h545309 != 11'd2047 && - guard__h537348 != 2'b0 } ; + _theResult___fst_exp__h545310 != 11'd2047 && + guard__h537349 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941 = { 3'd0, - _theResult___fst_exp__h584613 == 11'd0 && - guard__h576652 != 2'b0, + _theResult___fst_exp__h584614 == 11'd0 && + guard__h576653 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h585371 == 11'd2047 && - _theResult___fst_sfd__h585372 == 52'd0, + _theResult___fst_exp__h585372 == 11'd2047 && + _theResult___fst_sfd__h585373 == 52'd0, 1'd0, - _theResult___fst_exp__h584613 != 11'd2047 && - guard__h576652 != 2'b0 } ; + _theResult___fst_exp__h584614 != 11'd2047 && + guard__h576653 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8700 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 } ^ @@ -26153,15 +26178,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5281 = { 3'd0, - _theResult___fst_exp__h367272 == 8'd0 && - guard__h359224 != 2'b0, + _theResult___fst_exp__h367273 == 8'd0 && + guard__h359225 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h367795 == 8'd255 && - _theResult___fst_sfd__h367796 == 23'd0, + _theResult___fst_exp__h367796 == 8'd255 && + _theResult___fst_sfd__h367797 == 23'd0, 1'd0, - _theResult___fst_exp__h367272 != 8'd255 && - guard__h359224 != 2'b0 } ; + _theResult___fst_exp__h367273 != 8'd255 && + guard__h359225 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5972 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 } ^ @@ -26175,15 +26200,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6673 = { 3'd0, - _theResult___fst_exp__h412969 == 8'd0 && - guard__h404921 != 2'b0, + _theResult___fst_exp__h412970 == 8'd0 && + guard__h404922 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h413492 == 8'd255 && - _theResult___fst_sfd__h413493 == 23'd0, + _theResult___fst_exp__h413493 == 8'd255 && + _theResult___fst_sfd__h413494 == 23'd0, 1'd0, - _theResult___fst_exp__h412969 != 8'd255 && - guard__h404921 != 2'b0 } ; + _theResult___fst_exp__h412970 != 8'd255 && + guard__h404922 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7364 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 } ^ @@ -26197,17 +26222,17 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8065 = { 3'd0, - _theResult___fst_exp__h458664 == 8'd0 && - guard__h450616 != 2'b0, + _theResult___fst_exp__h458665 == 8'd0 && + guard__h450617 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h459187 == 8'd255 && - _theResult___fst_sfd__h459188 == 23'd0, + _theResult___fst_exp__h459188 == 8'd255 && + _theResult___fst_sfd__h459189 == 23'd0, 1'd0, - _theResult___fst_exp__h458664 != 8'd255 && - guard__h450616 != 2'b0 } ; + _theResult___fst_exp__h458665 != 8'd255 && + guard__h450617 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11197 = - b__h608239 * b__h608251 ; + b__h608240 * b__h608252 ; assign _0_CONCAT_csrf_external_int_en_vec_3_read__1864_ETC___d13033 = { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, @@ -26221,7 +26246,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14173 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k77209_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14074 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -26235,33 +26260,35 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10253 = - sfd__h526424 >> + sfd__h526425 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10249 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8768 = - sfd__h487430 >> + sfd__h487431 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8764 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9483 = - sfd__h565728 >> + sfd__h565729 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9479 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658 = - sfd__h342900 >> + sfd__h342901 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050 = - sfd__h388602 >> + sfd__h388603 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442 = - sfd__h434297 >> + sfd__h434298 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15017 = - medeleg_csr__read__h616706[i__h717423] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d14999 = - mideleg_csr__read__h616801[i__h717583] ; + assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14631 = + mip_csr__read__h617589 == commitStage_rg_old_mip_csr_val ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15028 = + medeleg_csr__read__h616708[i__h718403] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15010 = + mideleg_csr__read__h616803[i__h718563] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4111 = 12'd3074 - { 6'd0, @@ -26667,51 +26694,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 = 12'd3970 - { 7'd0, - f2_sfd__h526063[22] ? + f2_sfd__h526064[22] ? 5'd0 : - (f2_sfd__h526063[21] ? + (f2_sfd__h526064[21] ? 5'd1 : - (f2_sfd__h526063[20] ? + (f2_sfd__h526064[20] ? 5'd2 : - (f2_sfd__h526063[19] ? + (f2_sfd__h526064[19] ? 5'd3 : - (f2_sfd__h526063[18] ? + (f2_sfd__h526064[18] ? 5'd4 : - (f2_sfd__h526063[17] ? + (f2_sfd__h526064[17] ? 5'd5 : - (f2_sfd__h526063[16] ? + (f2_sfd__h526064[16] ? 5'd6 : - (f2_sfd__h526063[15] ? + (f2_sfd__h526064[15] ? 5'd7 : - (f2_sfd__h526063[14] ? + (f2_sfd__h526064[14] ? 5'd8 : - (f2_sfd__h526063[13] ? + (f2_sfd__h526064[13] ? 5'd9 : - (f2_sfd__h526063[12] ? + (f2_sfd__h526064[12] ? 5'd10 : - (f2_sfd__h526063[11] ? + (f2_sfd__h526064[11] ? 5'd11 : - (f2_sfd__h526063[10] ? + (f2_sfd__h526064[10] ? 5'd12 : - (f2_sfd__h526063[9] ? + (f2_sfd__h526064[9] ? 5'd13 : - (f2_sfd__h526063[8] ? + (f2_sfd__h526064[8] ? 5'd14 : - (f2_sfd__h526063[7] ? + (f2_sfd__h526064[7] ? 5'd15 : - (f2_sfd__h526063[6] ? + (f2_sfd__h526064[6] ? 5'd16 : - (f2_sfd__h526063[5] ? + (f2_sfd__h526064[5] ? 5'd17 : - (f2_sfd__h526063[4] ? + (f2_sfd__h526064[4] ? 5'd18 : - (f2_sfd__h526063[3] ? + (f2_sfd__h526064[3] ? 5'd19 : - (f2_sfd__h526063[2] ? + (f2_sfd__h526064[2] ? 5'd20 : - (f2_sfd__h526063[1] ? + (f2_sfd__h526064[1] ? 5'd21 : - (f2_sfd__h526063[0] ? + (f2_sfd__h526064[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 = @@ -26725,51 +26752,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 = 12'd3970 - { 7'd0, - f1_sfd__h487069[22] ? + f1_sfd__h487070[22] ? 5'd0 : - (f1_sfd__h487069[21] ? + (f1_sfd__h487070[21] ? 5'd1 : - (f1_sfd__h487069[20] ? + (f1_sfd__h487070[20] ? 5'd2 : - (f1_sfd__h487069[19] ? + (f1_sfd__h487070[19] ? 5'd3 : - (f1_sfd__h487069[18] ? + (f1_sfd__h487070[18] ? 5'd4 : - (f1_sfd__h487069[17] ? + (f1_sfd__h487070[17] ? 5'd5 : - (f1_sfd__h487069[16] ? + (f1_sfd__h487070[16] ? 5'd6 : - (f1_sfd__h487069[15] ? + (f1_sfd__h487070[15] ? 5'd7 : - (f1_sfd__h487069[14] ? + (f1_sfd__h487070[14] ? 5'd8 : - (f1_sfd__h487069[13] ? + (f1_sfd__h487070[13] ? 5'd9 : - (f1_sfd__h487069[12] ? + (f1_sfd__h487070[12] ? 5'd10 : - (f1_sfd__h487069[11] ? + (f1_sfd__h487070[11] ? 5'd11 : - (f1_sfd__h487069[10] ? + (f1_sfd__h487070[10] ? 5'd12 : - (f1_sfd__h487069[9] ? + (f1_sfd__h487070[9] ? 5'd13 : - (f1_sfd__h487069[8] ? + (f1_sfd__h487070[8] ? 5'd14 : - (f1_sfd__h487069[7] ? + (f1_sfd__h487070[7] ? 5'd15 : - (f1_sfd__h487069[6] ? + (f1_sfd__h487070[6] ? 5'd16 : - (f1_sfd__h487069[5] ? + (f1_sfd__h487070[5] ? 5'd17 : - (f1_sfd__h487069[4] ? + (f1_sfd__h487070[4] ? 5'd18 : - (f1_sfd__h487069[3] ? + (f1_sfd__h487070[3] ? 5'd19 : - (f1_sfd__h487069[2] ? + (f1_sfd__h487070[2] ? 5'd20 : - (f1_sfd__h487069[1] ? + (f1_sfd__h487070[1] ? 5'd21 : - (f1_sfd__h487069[0] ? + (f1_sfd__h487070[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 = @@ -26783,51 +26810,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 = 12'd3970 - { 7'd0, - f3_sfd__h565367[22] ? + f3_sfd__h565368[22] ? 5'd0 : - (f3_sfd__h565367[21] ? + (f3_sfd__h565368[21] ? 5'd1 : - (f3_sfd__h565367[20] ? + (f3_sfd__h565368[20] ? 5'd2 : - (f3_sfd__h565367[19] ? + (f3_sfd__h565368[19] ? 5'd3 : - (f3_sfd__h565367[18] ? + (f3_sfd__h565368[18] ? 5'd4 : - (f3_sfd__h565367[17] ? + (f3_sfd__h565368[17] ? 5'd5 : - (f3_sfd__h565367[16] ? + (f3_sfd__h565368[16] ? 5'd6 : - (f3_sfd__h565367[15] ? + (f3_sfd__h565368[15] ? 5'd7 : - (f3_sfd__h565367[14] ? + (f3_sfd__h565368[14] ? 5'd8 : - (f3_sfd__h565367[13] ? + (f3_sfd__h565368[13] ? 5'd9 : - (f3_sfd__h565367[12] ? + (f3_sfd__h565368[12] ? 5'd10 : - (f3_sfd__h565367[11] ? + (f3_sfd__h565368[11] ? 5'd11 : - (f3_sfd__h565367[10] ? + (f3_sfd__h565368[10] ? 5'd12 : - (f3_sfd__h565367[9] ? + (f3_sfd__h565368[9] ? 5'd13 : - (f3_sfd__h565367[8] ? + (f3_sfd__h565368[8] ? 5'd14 : - (f3_sfd__h565367[7] ? + (f3_sfd__h565368[7] ? 5'd15 : - (f3_sfd__h565367[6] ? + (f3_sfd__h565368[6] ? 5'd16 : - (f3_sfd__h565367[5] ? + (f3_sfd__h565368[5] ? 5'd17 : - (f3_sfd__h565367[4] ? + (f3_sfd__h565368[4] ? 5'd18 : - (f3_sfd__h565367[3] ? + (f3_sfd__h565368[3] ? 5'd19 : - (f3_sfd__h565367[2] ? + (f3_sfd__h565368[2] ? 5'd20 : - (f3_sfd__h565367[1] ? + (f3_sfd__h565368[1] ? 5'd21 : - (f3_sfd__h565367[0] ? + (f3_sfd__h565368[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 = @@ -26856,14 +26883,14 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14548 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h677209 == 1'd1 && + k__h677211 == 1'd1 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345 || (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14452 || NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14465) == 1'd1 && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14484 ; assign _dfoo18 = - k__h677209 == 1'd0 && + k__h677211 == 1'd0 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345 || (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14452 || NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14465) == @@ -26879,24 +26906,24 @@ module mkCore(CLK, fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; assign _dfoo20 = - commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 || - NOT_commitStage_commitTrap_4643_BIT_36_4891_48_ETC___d14996 ; + commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 || + NOT_commitStage_commitTrap_4654_BIT_36_4901_49_ETC___d15007 ; assign _dfoo24 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd40 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo32 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd8 || - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd18) || rob$deqPort_0_deq_data[329:325] == 5'd19 ; assign _dfoo7 = @@ -26980,1421 +27007,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h300941 = + assign _theResult_____2__h300942 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3146) ? - next_deqP___1__h301220 : + next_deqP___1__h301221 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h308937 = + assign _theResult_____2__h308938 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3253) ? - next_deqP___1__h309216 : + next_deqP___1__h309217 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h314931 = + assign _theResult_____2__h314932 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3424) ? - next_deqP___1__h315497 : + next_deqP___1__h315498 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h322785 = + assign _theResult_____2__h322786 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3520) ? - next_deqP___1__h323351 : + next_deqP___1__h323352 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h333129 = + assign _theResult_____2__h333130 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3749) ? - next_deqP___1__h333408 : + next_deqP___1__h333409 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h336354 = + assign _theResult_____2__h336355 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3843) ? - next_deqP___1__h336633 : + next_deqP___1__h336634 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h350505 = - (value__h351127 == 54'd0) ? sfd__h342900 : 57'd1 ; - assign _theResult____h368144 = + assign _theResult____h350506 = + (value__h351128 == 54'd0) ? sfd__h342901 : 57'd1 ; + assign _theResult____h368145 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654 ^ 12'h800) < 12'd2105) ? - result__h368757 : - _theResult____h350505 ; - assign _theResult____h396204 = - (value__h396824 == 54'd0) ? sfd__h388602 : 57'd1 ; - assign _theResult____h413841 = + result__h368758 : + _theResult____h350506 ; + assign _theResult____h396205 = + (value__h396825 == 54'd0) ? sfd__h388603 : 57'd1 ; + assign _theResult____h413842 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046 ^ 12'h800) < 12'd2105) ? - result__h414454 : - _theResult____h396204 ; - assign _theResult____h441899 = - (value__h442519 == 54'd0) ? sfd__h434297 : 57'd1 ; - assign _theResult____h459536 = + result__h414455 : + _theResult____h396205 ; + assign _theResult____h441900 = + (value__h442520 == 54'd0) ? sfd__h434298 : 57'd1 ; + assign _theResult____h459537 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438 ^ 12'h800) < 12'd2105) ? - result__h460149 : - _theResult____h441899 ; - assign _theResult____h507797 = + result__h460150 : + _theResult____h441900 ; + assign _theResult____h507798 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8764 ^ 12'h800) < 12'd2105) ? - result__h508410 : - ((value__h492013 == 25'd0) ? sfd__h487430 : 57'd1) ; - assign _theResult____h546650 = + result__h508411 : + ((value__h492014 == 25'd0) ? sfd__h487431 : 57'd1) ; + assign _theResult____h546651 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10249 ^ 12'h800) < 12'd2105) ? - result__h547263 : - ((value__h530866 == 25'd0) ? sfd__h526424 : 57'd1) ; - assign _theResult____h585954 = + result__h547264 : + ((value__h530867 == 25'd0) ? sfd__h526425 : 57'd1) ; + assign _theResult____h585955 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9479 ^ 12'h800) < 12'd2105) ? - result__h586567 : - ((value__h570170 == 25'd0) ? sfd__h565728 : 57'd1) ; - assign _theResult____h658374 = + result__h586568 : + ((value__h570171 == 25'd0) ? sfd__h565729 : 57'd1) ; + assign _theResult____h658376 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h658899 : + enabled_ints___1__h658901 : 16'd0 ; - assign _theResult___exp__h359132 = - sfd__h358708[24] ? - ((_theResult___fst_exp__h358616 == 8'd254) ? + assign _theResult___exp__h359133 = + sfd__h358709[24] ? + ((_theResult___fst_exp__h358617 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385649) : - ((_theResult___fst_exp__h358616 == 8'd0 && - sfd__h358708[24:23] == 2'b01) ? + din_inc___2_exp__h385650) : + ((_theResult___fst_exp__h358617 == 8'd0 && + sfd__h358709[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h358616) ; - assign _theResult___exp__h367714 = - sfd__h367290[24] ? - ((_theResult___fst_exp__h367272 == 8'd254) ? + _theResult___fst_exp__h358617) ; + assign _theResult___exp__h367715 = + sfd__h367291[24] ? + ((_theResult___fst_exp__h367273 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385673) : - ((_theResult___fst_exp__h367272 == 8'd0 && - sfd__h367290[24:23] == 2'b01) ? + din_inc___2_exp__h385674) : + ((_theResult___fst_exp__h367273 == 8'd0 && + sfd__h367291[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h367272) ; - assign _theResult___exp__h376898 = - sfd__h376474[24] ? - ((_theResult___fst_exp__h376382 == 8'd254) ? + _theResult___fst_exp__h367273) ; + assign _theResult___exp__h376899 = + sfd__h376475[24] ? + ((_theResult___fst_exp__h376383 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385703) : - ((_theResult___fst_exp__h376382 == 8'd0 && - sfd__h376474[24:23] == 2'b01) ? + din_inc___2_exp__h385704) : + ((_theResult___fst_exp__h376383 == 8'd0 && + sfd__h376475[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h376382) ; - assign _theResult___exp__h385534 = - sfd__h385086[24] ? - ((_theResult___fst_exp__h385067 == 8'd254) ? + _theResult___fst_exp__h376383) ; + assign _theResult___exp__h385535 = + sfd__h385087[24] ? + ((_theResult___fst_exp__h385068 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385727) : - ((_theResult___fst_exp__h385067 == 8'd0 && - sfd__h385086[24:23] == 2'b01) ? + din_inc___2_exp__h385728) : + ((_theResult___fst_exp__h385068 == 8'd0 && + sfd__h385087[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h385067) ; - assign _theResult___exp__h385636 = + _theResult___fst_exp__h385068) ; + assign _theResult___exp__h385637 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385627 ; - assign _theResult___exp__h404829 = - sfd__h404405[24] ? - ((_theResult___fst_exp__h404313 == 8'd254) ? + _theResult___fst_exp__h385628 ; + assign _theResult___exp__h404830 = + sfd__h404406[24] ? + ((_theResult___fst_exp__h404314 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431346) : - ((_theResult___fst_exp__h404313 == 8'd0 && - sfd__h404405[24:23] == 2'b01) ? + din_inc___2_exp__h431347) : + ((_theResult___fst_exp__h404314 == 8'd0 && + sfd__h404406[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h404313) ; - assign _theResult___exp__h413411 = - sfd__h412987[24] ? - ((_theResult___fst_exp__h412969 == 8'd254) ? + _theResult___fst_exp__h404314) ; + assign _theResult___exp__h413412 = + sfd__h412988[24] ? + ((_theResult___fst_exp__h412970 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431370) : - ((_theResult___fst_exp__h412969 == 8'd0 && - sfd__h412987[24:23] == 2'b01) ? + din_inc___2_exp__h431371) : + ((_theResult___fst_exp__h412970 == 8'd0 && + sfd__h412988[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h412969) ; - assign _theResult___exp__h422595 = - sfd__h422171[24] ? - ((_theResult___fst_exp__h422079 == 8'd254) ? + _theResult___fst_exp__h412970) ; + assign _theResult___exp__h422596 = + sfd__h422172[24] ? + ((_theResult___fst_exp__h422080 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431400) : - ((_theResult___fst_exp__h422079 == 8'd0 && - sfd__h422171[24:23] == 2'b01) ? + din_inc___2_exp__h431401) : + ((_theResult___fst_exp__h422080 == 8'd0 && + sfd__h422172[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h422079) ; - assign _theResult___exp__h431231 = - sfd__h430783[24] ? - ((_theResult___fst_exp__h430764 == 8'd254) ? + _theResult___fst_exp__h422080) ; + assign _theResult___exp__h431232 = + sfd__h430784[24] ? + ((_theResult___fst_exp__h430765 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431424) : - ((_theResult___fst_exp__h430764 == 8'd0 && - sfd__h430783[24:23] == 2'b01) ? + din_inc___2_exp__h431425) : + ((_theResult___fst_exp__h430765 == 8'd0 && + sfd__h430784[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h430764) ; - assign _theResult___exp__h431333 = + _theResult___fst_exp__h430765) ; + assign _theResult___exp__h431334 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431324 ; - assign _theResult___exp__h450524 = - sfd__h450100[24] ? - ((_theResult___fst_exp__h450008 == 8'd254) ? + _theResult___fst_exp__h431325 ; + assign _theResult___exp__h450525 = + sfd__h450101[24] ? + ((_theResult___fst_exp__h450009 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477041) : - ((_theResult___fst_exp__h450008 == 8'd0 && - sfd__h450100[24:23] == 2'b01) ? + din_inc___2_exp__h477042) : + ((_theResult___fst_exp__h450009 == 8'd0 && + sfd__h450101[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h450008) ; - assign _theResult___exp__h459106 = - sfd__h458682[24] ? - ((_theResult___fst_exp__h458664 == 8'd254) ? + _theResult___fst_exp__h450009) ; + assign _theResult___exp__h459107 = + sfd__h458683[24] ? + ((_theResult___fst_exp__h458665 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477065) : - ((_theResult___fst_exp__h458664 == 8'd0 && - sfd__h458682[24:23] == 2'b01) ? + din_inc___2_exp__h477066) : + ((_theResult___fst_exp__h458665 == 8'd0 && + sfd__h458683[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h458664) ; - assign _theResult___exp__h468290 = - sfd__h467866[24] ? - ((_theResult___fst_exp__h467774 == 8'd254) ? + _theResult___fst_exp__h458665) ; + assign _theResult___exp__h468291 = + sfd__h467867[24] ? + ((_theResult___fst_exp__h467775 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477095) : - ((_theResult___fst_exp__h467774 == 8'd0 && - sfd__h467866[24:23] == 2'b01) ? + din_inc___2_exp__h477096) : + ((_theResult___fst_exp__h467775 == 8'd0 && + sfd__h467867[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h467774) ; - assign _theResult___exp__h476926 = - sfd__h476478[24] ? - ((_theResult___fst_exp__h476459 == 8'd254) ? + _theResult___fst_exp__h467775) ; + assign _theResult___exp__h476927 = + sfd__h476479[24] ? + ((_theResult___fst_exp__h476460 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477119) : - ((_theResult___fst_exp__h476459 == 8'd0 && - sfd__h476478[24:23] == 2'b01) ? + din_inc___2_exp__h477120) : + ((_theResult___fst_exp__h476460 == 8'd0 && + sfd__h476479[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h476459) ; - assign _theResult___exp__h477028 = + _theResult___fst_exp__h476460) ; + assign _theResult___exp__h477029 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477019 ; - assign _theResult___exp__h507111 = - sfd__h506474[53] ? - ((_theResult___fst_exp__h506456 == 11'd2046) ? + _theResult___fst_exp__h477020 ; + assign _theResult___exp__h507112 = + sfd__h506475[53] ? + ((_theResult___fst_exp__h506457 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525706) : - ((_theResult___fst_exp__h506456 == 11'd0 && - sfd__h506474[53:52] == 2'b01) ? + din_inc___2_exp__h525707) : + ((_theResult___fst_exp__h506457 == 11'd0 && + sfd__h506475[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h506456) ; - assign _theResult___exp__h516762 = - sfd__h516125[53] ? - ((_theResult___fst_exp__h516033 == 11'd2046) ? + _theResult___fst_exp__h506457) ; + assign _theResult___exp__h516763 = + sfd__h516126[53] ? + ((_theResult___fst_exp__h516034 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525741) : - ((_theResult___fst_exp__h516033 == 11'd0 && - sfd__h516125[53:52] == 2'b01) ? + din_inc___2_exp__h525742) : + ((_theResult___fst_exp__h516034 == 11'd0 && + sfd__h516126[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h516033) ; - assign _theResult___exp__h525546 = - sfd__h524885[53] ? - ((_theResult___fst_exp__h524866 == 11'd2046) ? + _theResult___fst_exp__h516034) ; + assign _theResult___exp__h525547 = + sfd__h524886[53] ? + ((_theResult___fst_exp__h524867 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525767) : - ((_theResult___fst_exp__h524866 == 11'd0 && - sfd__h524885[53:52] == 2'b01) ? + din_inc___2_exp__h525768) : + ((_theResult___fst_exp__h524867 == 11'd0 && + sfd__h524886[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h524866) ; - assign _theResult___exp__h545964 = - sfd__h545327[53] ? - ((_theResult___fst_exp__h545309 == 11'd2046) ? + _theResult___fst_exp__h524867) ; + assign _theResult___exp__h545965 = + sfd__h545328[53] ? + ((_theResult___fst_exp__h545310 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564559) : - ((_theResult___fst_exp__h545309 == 11'd0 && - sfd__h545327[53:52] == 2'b01) ? + din_inc___2_exp__h564560) : + ((_theResult___fst_exp__h545310 == 11'd0 && + sfd__h545328[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h545309) ; - assign _theResult___exp__h555615 = - sfd__h554978[53] ? - ((_theResult___fst_exp__h554886 == 11'd2046) ? + _theResult___fst_exp__h545310) ; + assign _theResult___exp__h555616 = + sfd__h554979[53] ? + ((_theResult___fst_exp__h554887 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564594) : - ((_theResult___fst_exp__h554886 == 11'd0 && - sfd__h554978[53:52] == 2'b01) ? + din_inc___2_exp__h564595) : + ((_theResult___fst_exp__h554887 == 11'd0 && + sfd__h554979[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h554886) ; - assign _theResult___exp__h564399 = - sfd__h563738[53] ? - ((_theResult___fst_exp__h563719 == 11'd2046) ? + _theResult___fst_exp__h554887) ; + assign _theResult___exp__h564400 = + sfd__h563739[53] ? + ((_theResult___fst_exp__h563720 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564620) : - ((_theResult___fst_exp__h563719 == 11'd0 && - sfd__h563738[53:52] == 2'b01) ? + din_inc___2_exp__h564621) : + ((_theResult___fst_exp__h563720 == 11'd0 && + sfd__h563739[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h563719) ; - assign _theResult___exp__h585268 = - sfd__h584631[53] ? - ((_theResult___fst_exp__h584613 == 11'd2046) ? + _theResult___fst_exp__h563720) ; + assign _theResult___exp__h585269 = + sfd__h584632[53] ? + ((_theResult___fst_exp__h584614 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603863) : - ((_theResult___fst_exp__h584613 == 11'd0 && - sfd__h584631[53:52] == 2'b01) ? + din_inc___2_exp__h603864) : + ((_theResult___fst_exp__h584614 == 11'd0 && + sfd__h584632[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h584613) ; - assign _theResult___exp__h594919 = - sfd__h594282[53] ? - ((_theResult___fst_exp__h594190 == 11'd2046) ? + _theResult___fst_exp__h584614) ; + assign _theResult___exp__h594920 = + sfd__h594283[53] ? + ((_theResult___fst_exp__h594191 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603898) : - ((_theResult___fst_exp__h594190 == 11'd0 && - sfd__h594282[53:52] == 2'b01) ? + din_inc___2_exp__h603899) : + ((_theResult___fst_exp__h594191 == 11'd0 && + sfd__h594283[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h594190) ; - assign _theResult___exp__h603703 = - sfd__h603042[53] ? - ((_theResult___fst_exp__h603023 == 11'd2046) ? + _theResult___fst_exp__h594191) ; + assign _theResult___exp__h603704 = + sfd__h603043[53] ? + ((_theResult___fst_exp__h603024 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603924) : - ((_theResult___fst_exp__h603023 == 11'd0 && - sfd__h603042[53:52] == 2'b01) ? + din_inc___2_exp__h603925) : + ((_theResult___fst_exp__h603024 == 11'd0 && + sfd__h603043[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h603023) ; - assign _theResult___fst__h608462 = - a__h607914[63] ? a___1__h608467 : a__h607914 ; - assign _theResult___fst_exp__h358616 = - _theResult____h350505[56] ? + _theResult___fst_exp__h603024) ; + assign _theResult___fst__h608463 = + a__h607915[63] ? a___1__h608468 : a__h607915 ; + assign _theResult___fst_exp__h358617 = + _theResult____h350506[56] ? 8'd2 : - _theResult___fst_exp__h358690 ; - assign _theResult___fst_exp__h358681 = + _theResult___fst_exp__h358691 ; + assign _theResult___fst_exp__h358682 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347 } ; - assign _theResult___fst_exp__h358687 = - (!_theResult____h350505[56] && !_theResult____h350505[55] && - !_theResult____h350505[54] && - !_theResult____h350505[53] && - !_theResult____h350505[52] && - !_theResult____h350505[51] && - !_theResult____h350505[50] && - !_theResult____h350505[49] && - !_theResult____h350505[48] && - !_theResult____h350505[47] && - !_theResult____h350505[46] && - !_theResult____h350505[45] && - !_theResult____h350505[44] && - !_theResult____h350505[43] && - !_theResult____h350505[42] && - !_theResult____h350505[41] && - !_theResult____h350505[40] && - !_theResult____h350505[39] && - !_theResult____h350505[38] && - !_theResult____h350505[37] && - !_theResult____h350505[36] && - !_theResult____h350505[35] && - !_theResult____h350505[34] && - !_theResult____h350505[33] && - !_theResult____h350505[32] && - !_theResult____h350505[31] && - !_theResult____h350505[30] && - !_theResult____h350505[29] && - !_theResult____h350505[28] && - !_theResult____h350505[27] && - !_theResult____h350505[26] && - !_theResult____h350505[25] && - !_theResult____h350505[24] && - !_theResult____h350505[23] && - !_theResult____h350505[22] && - !_theResult____h350505[21] && - !_theResult____h350505[20] && - !_theResult____h350505[19] && - !_theResult____h350505[18] && - !_theResult____h350505[17] && - !_theResult____h350505[16] && - !_theResult____h350505[15] && - !_theResult____h350505[14] && - !_theResult____h350505[13] && - !_theResult____h350505[12] && - !_theResult____h350505[11] && - !_theResult____h350505[10] && - !_theResult____h350505[9] && - !_theResult____h350505[8] && - !_theResult____h350505[7] && - !_theResult____h350505[6] && - !_theResult____h350505[5] && - !_theResult____h350505[4] && - !_theResult____h350505[3] && - !_theResult____h350505[2] && - !_theResult____h350505[1] && - !_theResult____h350505[0] || + assign _theResult___fst_exp__h358688 = + (!_theResult____h350506[56] && !_theResult____h350506[55] && + !_theResult____h350506[54] && + !_theResult____h350506[53] && + !_theResult____h350506[52] && + !_theResult____h350506[51] && + !_theResult____h350506[50] && + !_theResult____h350506[49] && + !_theResult____h350506[48] && + !_theResult____h350506[47] && + !_theResult____h350506[46] && + !_theResult____h350506[45] && + !_theResult____h350506[44] && + !_theResult____h350506[43] && + !_theResult____h350506[42] && + !_theResult____h350506[41] && + !_theResult____h350506[40] && + !_theResult____h350506[39] && + !_theResult____h350506[38] && + !_theResult____h350506[37] && + !_theResult____h350506[36] && + !_theResult____h350506[35] && + !_theResult____h350506[34] && + !_theResult____h350506[33] && + !_theResult____h350506[32] && + !_theResult____h350506[31] && + !_theResult____h350506[30] && + !_theResult____h350506[29] && + !_theResult____h350506[28] && + !_theResult____h350506[27] && + !_theResult____h350506[26] && + !_theResult____h350506[25] && + !_theResult____h350506[24] && + !_theResult____h350506[23] && + !_theResult____h350506[22] && + !_theResult____h350506[21] && + !_theResult____h350506[20] && + !_theResult____h350506[19] && + !_theResult____h350506[18] && + !_theResult____h350506[17] && + !_theResult____h350506[16] && + !_theResult____h350506[15] && + !_theResult____h350506[14] && + !_theResult____h350506[13] && + !_theResult____h350506[12] && + !_theResult____h350506[11] && + !_theResult____h350506[10] && + !_theResult____h350506[9] && + !_theResult____h350506[8] && + !_theResult____h350506[7] && + !_theResult____h350506[6] && + !_theResult____h350506[5] && + !_theResult____h350506[4] && + !_theResult____h350506[3] && + !_theResult____h350506[2] && + !_theResult____h350506[1] && + !_theResult____h350506[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4349) ? 8'd0 : - _theResult___fst_exp__h358681 ; - assign _theResult___fst_exp__h358690 = - (!_theResult____h350505[56] && _theResult____h350505[55]) ? + _theResult___fst_exp__h358682 ; + assign _theResult___fst_exp__h358691 = + (!_theResult____h350506[56] && _theResult____h350506[55]) ? 8'd1 : - _theResult___fst_exp__h358687 ; - assign _theResult___fst_exp__h359213 = - (_theResult___fst_exp__h358616 == 8'd255) ? - _theResult___fst_exp__h358616 : - _theResult___fst_exp__h359210 ; - assign _theResult___fst_exp__h367263 = + _theResult___fst_exp__h358688 ; + assign _theResult___fst_exp__h359214 = + (_theResult___fst_exp__h358617 == 8'd255) ? + _theResult___fst_exp__h358617 : + _theResult___fst_exp__h359211 ; + assign _theResult___fst_exp__h367264 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578 } ; - assign _theResult___fst_exp__h367269 = + assign _theResult___fst_exp__h367270 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4580) ? 8'd0 : - _theResult___fst_exp__h367263 ; - assign _theResult___fst_exp__h367272 = + _theResult___fst_exp__h367264 ; + assign _theResult___fst_exp__h367273 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h367269 : + _theResult___fst_exp__h367270 : 8'd129 ; - assign _theResult___fst_exp__h367795 = - (_theResult___fst_exp__h367272 == 8'd255) ? - _theResult___fst_exp__h367272 : - _theResult___fst_exp__h367792 ; - assign _theResult___fst_exp__h376382 = - _theResult____h368144[56] ? + assign _theResult___fst_exp__h367796 = + (_theResult___fst_exp__h367273 == 8'd255) ? + _theResult___fst_exp__h367273 : + _theResult___fst_exp__h367793 ; + assign _theResult___fst_exp__h376383 = + _theResult____h368145[56] ? 8'd2 : - _theResult___fst_exp__h376456 ; - assign _theResult___fst_exp__h376447 = + _theResult___fst_exp__h376457 ; + assign _theResult___fst_exp__h376448 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4898 } ; - assign _theResult___fst_exp__h376453 = - (!_theResult____h368144[56] && !_theResult____h368144[55] && - !_theResult____h368144[54] && - !_theResult____h368144[53] && - !_theResult____h368144[52] && - !_theResult____h368144[51] && - !_theResult____h368144[50] && - !_theResult____h368144[49] && - !_theResult____h368144[48] && - !_theResult____h368144[47] && - !_theResult____h368144[46] && - !_theResult____h368144[45] && - !_theResult____h368144[44] && - !_theResult____h368144[43] && - !_theResult____h368144[42] && - !_theResult____h368144[41] && - !_theResult____h368144[40] && - !_theResult____h368144[39] && - !_theResult____h368144[38] && - !_theResult____h368144[37] && - !_theResult____h368144[36] && - !_theResult____h368144[35] && - !_theResult____h368144[34] && - !_theResult____h368144[33] && - !_theResult____h368144[32] && - !_theResult____h368144[31] && - !_theResult____h368144[30] && - !_theResult____h368144[29] && - !_theResult____h368144[28] && - !_theResult____h368144[27] && - !_theResult____h368144[26] && - !_theResult____h368144[25] && - !_theResult____h368144[24] && - !_theResult____h368144[23] && - !_theResult____h368144[22] && - !_theResult____h368144[21] && - !_theResult____h368144[20] && - !_theResult____h368144[19] && - !_theResult____h368144[18] && - !_theResult____h368144[17] && - !_theResult____h368144[16] && - !_theResult____h368144[15] && - !_theResult____h368144[14] && - !_theResult____h368144[13] && - !_theResult____h368144[12] && - !_theResult____h368144[11] && - !_theResult____h368144[10] && - !_theResult____h368144[9] && - !_theResult____h368144[8] && - !_theResult____h368144[7] && - !_theResult____h368144[6] && - !_theResult____h368144[5] && - !_theResult____h368144[4] && - !_theResult____h368144[3] && - !_theResult____h368144[2] && - !_theResult____h368144[1] && - !_theResult____h368144[0] || + assign _theResult___fst_exp__h376454 = + (!_theResult____h368145[56] && !_theResult____h368145[55] && + !_theResult____h368145[54] && + !_theResult____h368145[53] && + !_theResult____h368145[52] && + !_theResult____h368145[51] && + !_theResult____h368145[50] && + !_theResult____h368145[49] && + !_theResult____h368145[48] && + !_theResult____h368145[47] && + !_theResult____h368145[46] && + !_theResult____h368145[45] && + !_theResult____h368145[44] && + !_theResult____h368145[43] && + !_theResult____h368145[42] && + !_theResult____h368145[41] && + !_theResult____h368145[40] && + !_theResult____h368145[39] && + !_theResult____h368145[38] && + !_theResult____h368145[37] && + !_theResult____h368145[36] && + !_theResult____h368145[35] && + !_theResult____h368145[34] && + !_theResult____h368145[33] && + !_theResult____h368145[32] && + !_theResult____h368145[31] && + !_theResult____h368145[30] && + !_theResult____h368145[29] && + !_theResult____h368145[28] && + !_theResult____h368145[27] && + !_theResult____h368145[26] && + !_theResult____h368145[25] && + !_theResult____h368145[24] && + !_theResult____h368145[23] && + !_theResult____h368145[22] && + !_theResult____h368145[21] && + !_theResult____h368145[20] && + !_theResult____h368145[19] && + !_theResult____h368145[18] && + !_theResult____h368145[17] && + !_theResult____h368145[16] && + !_theResult____h368145[15] && + !_theResult____h368145[14] && + !_theResult____h368145[13] && + !_theResult____h368145[12] && + !_theResult____h368145[11] && + !_theResult____h368145[10] && + !_theResult____h368145[9] && + !_theResult____h368145[8] && + !_theResult____h368145[7] && + !_theResult____h368145[6] && + !_theResult____h368145[5] && + !_theResult____h368145[4] && + !_theResult____h368145[3] && + !_theResult____h368145[2] && + !_theResult____h368145[1] && + !_theResult____h368145[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4900) ? 8'd0 : - _theResult___fst_exp__h376447 ; - assign _theResult___fst_exp__h376456 = - (!_theResult____h368144[56] && _theResult____h368144[55]) ? + _theResult___fst_exp__h376448 ; + assign _theResult___fst_exp__h376457 = + (!_theResult____h368145[56] && _theResult____h368145[55]) ? 8'd1 : - _theResult___fst_exp__h376453 ; - assign _theResult___fst_exp__h376979 = - (_theResult___fst_exp__h376382 == 8'd255) ? - _theResult___fst_exp__h376382 : - _theResult___fst_exp__h376976 ; - assign _theResult___fst_exp__h385019 = + _theResult___fst_exp__h376454 ; + assign _theResult___fst_exp__h376980 = + (_theResult___fst_exp__h376383 == 8'd255) ? + _theResult___fst_exp__h376383 : + _theResult___fst_exp__h376977 ; + assign _theResult___fst_exp__h385020 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] ; - assign _theResult___fst_exp__h385058 = + assign _theResult___fst_exp__h385059 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578 } ; - assign _theResult___fst_exp__h385064 = + assign _theResult___fst_exp__h385065 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4973) ? 8'd0 : - _theResult___fst_exp__h385058 ; - assign _theResult___fst_exp__h385067 = + _theResult___fst_exp__h385059 ; + assign _theResult___fst_exp__h385068 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h385064 : - _theResult___fst_exp__h385019 ; - assign _theResult___fst_exp__h385615 = - (_theResult___fst_exp__h385067 == 8'd255) ? - _theResult___fst_exp__h385067 : - _theResult___fst_exp__h385612 ; - assign _theResult___fst_exp__h385624 = + _theResult___fst_exp__h385065 : + _theResult___fst_exp__h385020 ; + assign _theResult___fst_exp__h385616 = + (_theResult___fst_exp__h385068 == 8'd255) ? + _theResult___fst_exp__h385068 : + _theResult___fst_exp__h385613 ; + assign _theResult___fst_exp__h385625 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112 ? - _theResult___snd_fst_exp__h367798 : - _theResult___fst_exp__h350487) : + _theResult___snd_fst_exp__h367799 : + _theResult___fst_exp__h350488) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4652 ? - _theResult___snd_fst_exp__h385618 : - _theResult___fst_exp__h350487) ; - assign _theResult___fst_exp__h385627 = + _theResult___snd_fst_exp__h385619 : + _theResult___fst_exp__h350488) ; + assign _theResult___fst_exp__h385628 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h385624 ; - assign _theResult___fst_exp__h404313 = - _theResult____h396204[56] ? + _theResult___fst_exp__h385625 ; + assign _theResult___fst_exp__h404314 = + _theResult____h396205[56] ? 8'd2 : - _theResult___fst_exp__h404387 ; - assign _theResult___fst_exp__h404378 = + _theResult___fst_exp__h404388 ; + assign _theResult___fst_exp__h404379 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 } ; - assign _theResult___fst_exp__h404384 = - (!_theResult____h396204[56] && !_theResult____h396204[55] && - !_theResult____h396204[54] && - !_theResult____h396204[53] && - !_theResult____h396204[52] && - !_theResult____h396204[51] && - !_theResult____h396204[50] && - !_theResult____h396204[49] && - !_theResult____h396204[48] && - !_theResult____h396204[47] && - !_theResult____h396204[46] && - !_theResult____h396204[45] && - !_theResult____h396204[44] && - !_theResult____h396204[43] && - !_theResult____h396204[42] && - !_theResult____h396204[41] && - !_theResult____h396204[40] && - !_theResult____h396204[39] && - !_theResult____h396204[38] && - !_theResult____h396204[37] && - !_theResult____h396204[36] && - !_theResult____h396204[35] && - !_theResult____h396204[34] && - !_theResult____h396204[33] && - !_theResult____h396204[32] && - !_theResult____h396204[31] && - !_theResult____h396204[30] && - !_theResult____h396204[29] && - !_theResult____h396204[28] && - !_theResult____h396204[27] && - !_theResult____h396204[26] && - !_theResult____h396204[25] && - !_theResult____h396204[24] && - !_theResult____h396204[23] && - !_theResult____h396204[22] && - !_theResult____h396204[21] && - !_theResult____h396204[20] && - !_theResult____h396204[19] && - !_theResult____h396204[18] && - !_theResult____h396204[17] && - !_theResult____h396204[16] && - !_theResult____h396204[15] && - !_theResult____h396204[14] && - !_theResult____h396204[13] && - !_theResult____h396204[12] && - !_theResult____h396204[11] && - !_theResult____h396204[10] && - !_theResult____h396204[9] && - !_theResult____h396204[8] && - !_theResult____h396204[7] && - !_theResult____h396204[6] && - !_theResult____h396204[5] && - !_theResult____h396204[4] && - !_theResult____h396204[3] && - !_theResult____h396204[2] && - !_theResult____h396204[1] && - !_theResult____h396204[0] || + assign _theResult___fst_exp__h404385 = + (!_theResult____h396205[56] && !_theResult____h396205[55] && + !_theResult____h396205[54] && + !_theResult____h396205[53] && + !_theResult____h396205[52] && + !_theResult____h396205[51] && + !_theResult____h396205[50] && + !_theResult____h396205[49] && + !_theResult____h396205[48] && + !_theResult____h396205[47] && + !_theResult____h396205[46] && + !_theResult____h396205[45] && + !_theResult____h396205[44] && + !_theResult____h396205[43] && + !_theResult____h396205[42] && + !_theResult____h396205[41] && + !_theResult____h396205[40] && + !_theResult____h396205[39] && + !_theResult____h396205[38] && + !_theResult____h396205[37] && + !_theResult____h396205[36] && + !_theResult____h396205[35] && + !_theResult____h396205[34] && + !_theResult____h396205[33] && + !_theResult____h396205[32] && + !_theResult____h396205[31] && + !_theResult____h396205[30] && + !_theResult____h396205[29] && + !_theResult____h396205[28] && + !_theResult____h396205[27] && + !_theResult____h396205[26] && + !_theResult____h396205[25] && + !_theResult____h396205[24] && + !_theResult____h396205[23] && + !_theResult____h396205[22] && + !_theResult____h396205[21] && + !_theResult____h396205[20] && + !_theResult____h396205[19] && + !_theResult____h396205[18] && + !_theResult____h396205[17] && + !_theResult____h396205[16] && + !_theResult____h396205[15] && + !_theResult____h396205[14] && + !_theResult____h396205[13] && + !_theResult____h396205[12] && + !_theResult____h396205[11] && + !_theResult____h396205[10] && + !_theResult____h396205[9] && + !_theResult____h396205[8] && + !_theResult____h396205[7] && + !_theResult____h396205[6] && + !_theResult____h396205[5] && + !_theResult____h396205[4] && + !_theResult____h396205[3] && + !_theResult____h396205[2] && + !_theResult____h396205[1] && + !_theResult____h396205[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5741) ? 8'd0 : - _theResult___fst_exp__h404378 ; - assign _theResult___fst_exp__h404387 = - (!_theResult____h396204[56] && _theResult____h396204[55]) ? + _theResult___fst_exp__h404379 ; + assign _theResult___fst_exp__h404388 = + (!_theResult____h396205[56] && _theResult____h396205[55]) ? 8'd1 : - _theResult___fst_exp__h404384 ; - assign _theResult___fst_exp__h404910 = - (_theResult___fst_exp__h404313 == 8'd255) ? - _theResult___fst_exp__h404313 : - _theResult___fst_exp__h404907 ; - assign _theResult___fst_exp__h412960 = + _theResult___fst_exp__h404385 ; + assign _theResult___fst_exp__h404911 = + (_theResult___fst_exp__h404314 == 8'd255) ? + _theResult___fst_exp__h404314 : + _theResult___fst_exp__h404908 ; + assign _theResult___fst_exp__h412961 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 } ; - assign _theResult___fst_exp__h412966 = + assign _theResult___fst_exp__h412967 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5972) ? 8'd0 : - _theResult___fst_exp__h412960 ; - assign _theResult___fst_exp__h412969 = + _theResult___fst_exp__h412961 ; + assign _theResult___fst_exp__h412970 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h412966 : + _theResult___fst_exp__h412967 : 8'd129 ; - assign _theResult___fst_exp__h413492 = - (_theResult___fst_exp__h412969 == 8'd255) ? - _theResult___fst_exp__h412969 : - _theResult___fst_exp__h413489 ; - assign _theResult___fst_exp__h422079 = - _theResult____h413841[56] ? + assign _theResult___fst_exp__h413493 = + (_theResult___fst_exp__h412970 == 8'd255) ? + _theResult___fst_exp__h412970 : + _theResult___fst_exp__h413490 ; + assign _theResult___fst_exp__h422080 = + _theResult____h413842[56] ? 8'd2 : - _theResult___fst_exp__h422153 ; - assign _theResult___fst_exp__h422144 = + _theResult___fst_exp__h422154 ; + assign _theResult___fst_exp__h422145 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 } ; - assign _theResult___fst_exp__h422150 = - (!_theResult____h413841[56] && !_theResult____h413841[55] && - !_theResult____h413841[54] && - !_theResult____h413841[53] && - !_theResult____h413841[52] && - !_theResult____h413841[51] && - !_theResult____h413841[50] && - !_theResult____h413841[49] && - !_theResult____h413841[48] && - !_theResult____h413841[47] && - !_theResult____h413841[46] && - !_theResult____h413841[45] && - !_theResult____h413841[44] && - !_theResult____h413841[43] && - !_theResult____h413841[42] && - !_theResult____h413841[41] && - !_theResult____h413841[40] && - !_theResult____h413841[39] && - !_theResult____h413841[38] && - !_theResult____h413841[37] && - !_theResult____h413841[36] && - !_theResult____h413841[35] && - !_theResult____h413841[34] && - !_theResult____h413841[33] && - !_theResult____h413841[32] && - !_theResult____h413841[31] && - !_theResult____h413841[30] && - !_theResult____h413841[29] && - !_theResult____h413841[28] && - !_theResult____h413841[27] && - !_theResult____h413841[26] && - !_theResult____h413841[25] && - !_theResult____h413841[24] && - !_theResult____h413841[23] && - !_theResult____h413841[22] && - !_theResult____h413841[21] && - !_theResult____h413841[20] && - !_theResult____h413841[19] && - !_theResult____h413841[18] && - !_theResult____h413841[17] && - !_theResult____h413841[16] && - !_theResult____h413841[15] && - !_theResult____h413841[14] && - !_theResult____h413841[13] && - !_theResult____h413841[12] && - !_theResult____h413841[11] && - !_theResult____h413841[10] && - !_theResult____h413841[9] && - !_theResult____h413841[8] && - !_theResult____h413841[7] && - !_theResult____h413841[6] && - !_theResult____h413841[5] && - !_theResult____h413841[4] && - !_theResult____h413841[3] && - !_theResult____h413841[2] && - !_theResult____h413841[1] && - !_theResult____h413841[0] || + assign _theResult___fst_exp__h422151 = + (!_theResult____h413842[56] && !_theResult____h413842[55] && + !_theResult____h413842[54] && + !_theResult____h413842[53] && + !_theResult____h413842[52] && + !_theResult____h413842[51] && + !_theResult____h413842[50] && + !_theResult____h413842[49] && + !_theResult____h413842[48] && + !_theResult____h413842[47] && + !_theResult____h413842[46] && + !_theResult____h413842[45] && + !_theResult____h413842[44] && + !_theResult____h413842[43] && + !_theResult____h413842[42] && + !_theResult____h413842[41] && + !_theResult____h413842[40] && + !_theResult____h413842[39] && + !_theResult____h413842[38] && + !_theResult____h413842[37] && + !_theResult____h413842[36] && + !_theResult____h413842[35] && + !_theResult____h413842[34] && + !_theResult____h413842[33] && + !_theResult____h413842[32] && + !_theResult____h413842[31] && + !_theResult____h413842[30] && + !_theResult____h413842[29] && + !_theResult____h413842[28] && + !_theResult____h413842[27] && + !_theResult____h413842[26] && + !_theResult____h413842[25] && + !_theResult____h413842[24] && + !_theResult____h413842[23] && + !_theResult____h413842[22] && + !_theResult____h413842[21] && + !_theResult____h413842[20] && + !_theResult____h413842[19] && + !_theResult____h413842[18] && + !_theResult____h413842[17] && + !_theResult____h413842[16] && + !_theResult____h413842[15] && + !_theResult____h413842[14] && + !_theResult____h413842[13] && + !_theResult____h413842[12] && + !_theResult____h413842[11] && + !_theResult____h413842[10] && + !_theResult____h413842[9] && + !_theResult____h413842[8] && + !_theResult____h413842[7] && + !_theResult____h413842[6] && + !_theResult____h413842[5] && + !_theResult____h413842[4] && + !_theResult____h413842[3] && + !_theResult____h413842[2] && + !_theResult____h413842[1] && + !_theResult____h413842[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6292) ? 8'd0 : - _theResult___fst_exp__h422144 ; - assign _theResult___fst_exp__h422153 = - (!_theResult____h413841[56] && _theResult____h413841[55]) ? + _theResult___fst_exp__h422145 ; + assign _theResult___fst_exp__h422154 = + (!_theResult____h413842[56] && _theResult____h413842[55]) ? 8'd1 : - _theResult___fst_exp__h422150 ; - assign _theResult___fst_exp__h422676 = - (_theResult___fst_exp__h422079 == 8'd255) ? - _theResult___fst_exp__h422079 : - _theResult___fst_exp__h422673 ; - assign _theResult___fst_exp__h430716 = + _theResult___fst_exp__h422151 ; + assign _theResult___fst_exp__h422677 = + (_theResult___fst_exp__h422080 == 8'd255) ? + _theResult___fst_exp__h422080 : + _theResult___fst_exp__h422674 ; + assign _theResult___fst_exp__h430717 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] ; - assign _theResult___fst_exp__h430755 = + assign _theResult___fst_exp__h430756 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 } ; - assign _theResult___fst_exp__h430761 = + assign _theResult___fst_exp__h430762 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6365) ? 8'd0 : - _theResult___fst_exp__h430755 ; - assign _theResult___fst_exp__h430764 = + _theResult___fst_exp__h430756 ; + assign _theResult___fst_exp__h430765 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h430761 : - _theResult___fst_exp__h430716 ; - assign _theResult___fst_exp__h431312 = - (_theResult___fst_exp__h430764 == 8'd255) ? - _theResult___fst_exp__h430764 : - _theResult___fst_exp__h431309 ; - assign _theResult___fst_exp__h431321 = + _theResult___fst_exp__h430762 : + _theResult___fst_exp__h430717 ; + assign _theResult___fst_exp__h431313 = + (_theResult___fst_exp__h430765 == 8'd255) ? + _theResult___fst_exp__h430765 : + _theResult___fst_exp__h431310 ; + assign _theResult___fst_exp__h431322 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5504 ? - _theResult___snd_fst_exp__h413495 : - _theResult___fst_exp__h396186) : + _theResult___snd_fst_exp__h413496 : + _theResult___fst_exp__h396187) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6044 ? - _theResult___snd_fst_exp__h431315 : - _theResult___fst_exp__h396186) ; - assign _theResult___fst_exp__h431324 = + _theResult___snd_fst_exp__h431316 : + _theResult___fst_exp__h396187) ; + assign _theResult___fst_exp__h431325 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h431321 ; - assign _theResult___fst_exp__h450008 = - _theResult____h441899[56] ? + _theResult___fst_exp__h431322 ; + assign _theResult___fst_exp__h450009 = + _theResult____h441900[56] ? 8'd2 : - _theResult___fst_exp__h450082 ; - assign _theResult___fst_exp__h450073 = + _theResult___fst_exp__h450083 ; + assign _theResult___fst_exp__h450074 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 } ; - assign _theResult___fst_exp__h450079 = - (!_theResult____h441899[56] && !_theResult____h441899[55] && - !_theResult____h441899[54] && - !_theResult____h441899[53] && - !_theResult____h441899[52] && - !_theResult____h441899[51] && - !_theResult____h441899[50] && - !_theResult____h441899[49] && - !_theResult____h441899[48] && - !_theResult____h441899[47] && - !_theResult____h441899[46] && - !_theResult____h441899[45] && - !_theResult____h441899[44] && - !_theResult____h441899[43] && - !_theResult____h441899[42] && - !_theResult____h441899[41] && - !_theResult____h441899[40] && - !_theResult____h441899[39] && - !_theResult____h441899[38] && - !_theResult____h441899[37] && - !_theResult____h441899[36] && - !_theResult____h441899[35] && - !_theResult____h441899[34] && - !_theResult____h441899[33] && - !_theResult____h441899[32] && - !_theResult____h441899[31] && - !_theResult____h441899[30] && - !_theResult____h441899[29] && - !_theResult____h441899[28] && - !_theResult____h441899[27] && - !_theResult____h441899[26] && - !_theResult____h441899[25] && - !_theResult____h441899[24] && - !_theResult____h441899[23] && - !_theResult____h441899[22] && - !_theResult____h441899[21] && - !_theResult____h441899[20] && - !_theResult____h441899[19] && - !_theResult____h441899[18] && - !_theResult____h441899[17] && - !_theResult____h441899[16] && - !_theResult____h441899[15] && - !_theResult____h441899[14] && - !_theResult____h441899[13] && - !_theResult____h441899[12] && - !_theResult____h441899[11] && - !_theResult____h441899[10] && - !_theResult____h441899[9] && - !_theResult____h441899[8] && - !_theResult____h441899[7] && - !_theResult____h441899[6] && - !_theResult____h441899[5] && - !_theResult____h441899[4] && - !_theResult____h441899[3] && - !_theResult____h441899[2] && - !_theResult____h441899[1] && - !_theResult____h441899[0] || + assign _theResult___fst_exp__h450080 = + (!_theResult____h441900[56] && !_theResult____h441900[55] && + !_theResult____h441900[54] && + !_theResult____h441900[53] && + !_theResult____h441900[52] && + !_theResult____h441900[51] && + !_theResult____h441900[50] && + !_theResult____h441900[49] && + !_theResult____h441900[48] && + !_theResult____h441900[47] && + !_theResult____h441900[46] && + !_theResult____h441900[45] && + !_theResult____h441900[44] && + !_theResult____h441900[43] && + !_theResult____h441900[42] && + !_theResult____h441900[41] && + !_theResult____h441900[40] && + !_theResult____h441900[39] && + !_theResult____h441900[38] && + !_theResult____h441900[37] && + !_theResult____h441900[36] && + !_theResult____h441900[35] && + !_theResult____h441900[34] && + !_theResult____h441900[33] && + !_theResult____h441900[32] && + !_theResult____h441900[31] && + !_theResult____h441900[30] && + !_theResult____h441900[29] && + !_theResult____h441900[28] && + !_theResult____h441900[27] && + !_theResult____h441900[26] && + !_theResult____h441900[25] && + !_theResult____h441900[24] && + !_theResult____h441900[23] && + !_theResult____h441900[22] && + !_theResult____h441900[21] && + !_theResult____h441900[20] && + !_theResult____h441900[19] && + !_theResult____h441900[18] && + !_theResult____h441900[17] && + !_theResult____h441900[16] && + !_theResult____h441900[15] && + !_theResult____h441900[14] && + !_theResult____h441900[13] && + !_theResult____h441900[12] && + !_theResult____h441900[11] && + !_theResult____h441900[10] && + !_theResult____h441900[9] && + !_theResult____h441900[8] && + !_theResult____h441900[7] && + !_theResult____h441900[6] && + !_theResult____h441900[5] && + !_theResult____h441900[4] && + !_theResult____h441900[3] && + !_theResult____h441900[2] && + !_theResult____h441900[1] && + !_theResult____h441900[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7133) ? 8'd0 : - _theResult___fst_exp__h450073 ; - assign _theResult___fst_exp__h450082 = - (!_theResult____h441899[56] && _theResult____h441899[55]) ? + _theResult___fst_exp__h450074 ; + assign _theResult___fst_exp__h450083 = + (!_theResult____h441900[56] && _theResult____h441900[55]) ? 8'd1 : - _theResult___fst_exp__h450079 ; - assign _theResult___fst_exp__h450605 = - (_theResult___fst_exp__h450008 == 8'd255) ? - _theResult___fst_exp__h450008 : - _theResult___fst_exp__h450602 ; - assign _theResult___fst_exp__h458655 = + _theResult___fst_exp__h450080 ; + assign _theResult___fst_exp__h450606 = + (_theResult___fst_exp__h450009 == 8'd255) ? + _theResult___fst_exp__h450009 : + _theResult___fst_exp__h450603 ; + assign _theResult___fst_exp__h458656 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 } ; - assign _theResult___fst_exp__h458661 = + assign _theResult___fst_exp__h458662 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7364) ? 8'd0 : - _theResult___fst_exp__h458655 ; - assign _theResult___fst_exp__h458664 = + _theResult___fst_exp__h458656 ; + assign _theResult___fst_exp__h458665 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h458661 : + _theResult___fst_exp__h458662 : 8'd129 ; - assign _theResult___fst_exp__h459187 = - (_theResult___fst_exp__h458664 == 8'd255) ? - _theResult___fst_exp__h458664 : - _theResult___fst_exp__h459184 ; - assign _theResult___fst_exp__h467774 = - _theResult____h459536[56] ? + assign _theResult___fst_exp__h459188 = + (_theResult___fst_exp__h458665 == 8'd255) ? + _theResult___fst_exp__h458665 : + _theResult___fst_exp__h459185 ; + assign _theResult___fst_exp__h467775 = + _theResult____h459537[56] ? 8'd2 : - _theResult___fst_exp__h467848 ; - assign _theResult___fst_exp__h467839 = + _theResult___fst_exp__h467849 ; + assign _theResult___fst_exp__h467840 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 } ; - assign _theResult___fst_exp__h467845 = - (!_theResult____h459536[56] && !_theResult____h459536[55] && - !_theResult____h459536[54] && - !_theResult____h459536[53] && - !_theResult____h459536[52] && - !_theResult____h459536[51] && - !_theResult____h459536[50] && - !_theResult____h459536[49] && - !_theResult____h459536[48] && - !_theResult____h459536[47] && - !_theResult____h459536[46] && - !_theResult____h459536[45] && - !_theResult____h459536[44] && - !_theResult____h459536[43] && - !_theResult____h459536[42] && - !_theResult____h459536[41] && - !_theResult____h459536[40] && - !_theResult____h459536[39] && - !_theResult____h459536[38] && - !_theResult____h459536[37] && - !_theResult____h459536[36] && - !_theResult____h459536[35] && - !_theResult____h459536[34] && - !_theResult____h459536[33] && - !_theResult____h459536[32] && - !_theResult____h459536[31] && - !_theResult____h459536[30] && - !_theResult____h459536[29] && - !_theResult____h459536[28] && - !_theResult____h459536[27] && - !_theResult____h459536[26] && - !_theResult____h459536[25] && - !_theResult____h459536[24] && - !_theResult____h459536[23] && - !_theResult____h459536[22] && - !_theResult____h459536[21] && - !_theResult____h459536[20] && - !_theResult____h459536[19] && - !_theResult____h459536[18] && - !_theResult____h459536[17] && - !_theResult____h459536[16] && - !_theResult____h459536[15] && - !_theResult____h459536[14] && - !_theResult____h459536[13] && - !_theResult____h459536[12] && - !_theResult____h459536[11] && - !_theResult____h459536[10] && - !_theResult____h459536[9] && - !_theResult____h459536[8] && - !_theResult____h459536[7] && - !_theResult____h459536[6] && - !_theResult____h459536[5] && - !_theResult____h459536[4] && - !_theResult____h459536[3] && - !_theResult____h459536[2] && - !_theResult____h459536[1] && - !_theResult____h459536[0] || + assign _theResult___fst_exp__h467846 = + (!_theResult____h459537[56] && !_theResult____h459537[55] && + !_theResult____h459537[54] && + !_theResult____h459537[53] && + !_theResult____h459537[52] && + !_theResult____h459537[51] && + !_theResult____h459537[50] && + !_theResult____h459537[49] && + !_theResult____h459537[48] && + !_theResult____h459537[47] && + !_theResult____h459537[46] && + !_theResult____h459537[45] && + !_theResult____h459537[44] && + !_theResult____h459537[43] && + !_theResult____h459537[42] && + !_theResult____h459537[41] && + !_theResult____h459537[40] && + !_theResult____h459537[39] && + !_theResult____h459537[38] && + !_theResult____h459537[37] && + !_theResult____h459537[36] && + !_theResult____h459537[35] && + !_theResult____h459537[34] && + !_theResult____h459537[33] && + !_theResult____h459537[32] && + !_theResult____h459537[31] && + !_theResult____h459537[30] && + !_theResult____h459537[29] && + !_theResult____h459537[28] && + !_theResult____h459537[27] && + !_theResult____h459537[26] && + !_theResult____h459537[25] && + !_theResult____h459537[24] && + !_theResult____h459537[23] && + !_theResult____h459537[22] && + !_theResult____h459537[21] && + !_theResult____h459537[20] && + !_theResult____h459537[19] && + !_theResult____h459537[18] && + !_theResult____h459537[17] && + !_theResult____h459537[16] && + !_theResult____h459537[15] && + !_theResult____h459537[14] && + !_theResult____h459537[13] && + !_theResult____h459537[12] && + !_theResult____h459537[11] && + !_theResult____h459537[10] && + !_theResult____h459537[9] && + !_theResult____h459537[8] && + !_theResult____h459537[7] && + !_theResult____h459537[6] && + !_theResult____h459537[5] && + !_theResult____h459537[4] && + !_theResult____h459537[3] && + !_theResult____h459537[2] && + !_theResult____h459537[1] && + !_theResult____h459537[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7684) ? 8'd0 : - _theResult___fst_exp__h467839 ; - assign _theResult___fst_exp__h467848 = - (!_theResult____h459536[56] && _theResult____h459536[55]) ? + _theResult___fst_exp__h467840 ; + assign _theResult___fst_exp__h467849 = + (!_theResult____h459537[56] && _theResult____h459537[55]) ? 8'd1 : - _theResult___fst_exp__h467845 ; - assign _theResult___fst_exp__h468371 = - (_theResult___fst_exp__h467774 == 8'd255) ? - _theResult___fst_exp__h467774 : - _theResult___fst_exp__h468368 ; - assign _theResult___fst_exp__h476411 = + _theResult___fst_exp__h467846 ; + assign _theResult___fst_exp__h468372 = + (_theResult___fst_exp__h467775 == 8'd255) ? + _theResult___fst_exp__h467775 : + _theResult___fst_exp__h468369 ; + assign _theResult___fst_exp__h476412 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] ; - assign _theResult___fst_exp__h476450 = + assign _theResult___fst_exp__h476451 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 } ; - assign _theResult___fst_exp__h476456 = + assign _theResult___fst_exp__h476457 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7757) ? 8'd0 : - _theResult___fst_exp__h476450 ; - assign _theResult___fst_exp__h476459 = + _theResult___fst_exp__h476451 ; + assign _theResult___fst_exp__h476460 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h476456 : - _theResult___fst_exp__h476411 ; - assign _theResult___fst_exp__h477007 = - (_theResult___fst_exp__h476459 == 8'd255) ? - _theResult___fst_exp__h476459 : - _theResult___fst_exp__h477004 ; - assign _theResult___fst_exp__h477016 = + _theResult___fst_exp__h476457 : + _theResult___fst_exp__h476412 ; + assign _theResult___fst_exp__h477008 = + (_theResult___fst_exp__h476460 == 8'd255) ? + _theResult___fst_exp__h476460 : + _theResult___fst_exp__h477005 ; + assign _theResult___fst_exp__h477017 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6896 ? - _theResult___snd_fst_exp__h459190 : - _theResult___fst_exp__h441881) : + _theResult___snd_fst_exp__h459191 : + _theResult___fst_exp__h441882) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7436 ? - _theResult___snd_fst_exp__h477010 : - _theResult___fst_exp__h441881) ; - assign _theResult___fst_exp__h477019 = + _theResult___snd_fst_exp__h477011 : + _theResult___fst_exp__h441882) ; + assign _theResult___fst_exp__h477020 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h477016 ; - assign _theResult___fst_exp__h491383 = + _theResult___fst_exp__h477017 ; + assign _theResult___fst_exp__h491384 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_exp__h506447 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; + assign _theResult___fst_exp__h506448 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 } ; - assign _theResult___fst_exp__h506453 = - (f1_exp__h487068 == 8'd0 && !f1_sfd__h487069[22] && + assign _theResult___fst_exp__h506454 = + (f1_exp__h487069 == 8'd0 && !f1_sfd__h487070[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8700) ? 11'd0 : - _theResult___fst_exp__h506447 ; - assign _theResult___fst_exp__h506456 = - (f1_exp__h487068 == 8'd0) ? - _theResult___fst_exp__h506453 : + _theResult___fst_exp__h506448 ; + assign _theResult___fst_exp__h506457 = + (f1_exp__h487069 == 8'd0) ? + _theResult___fst_exp__h506454 : 11'd897 ; - assign _theResult___fst_exp__h507211 = + assign _theResult___fst_exp__h507212 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q144 : + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q144 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 ; - assign _theResult___fst_exp__h507214 = - (_theResult___fst_exp__h506456 == 11'd2047) ? - _theResult___fst_exp__h506456 : - _theResult___fst_exp__h507211 ; - assign _theResult___fst_exp__h516033 = - _theResult____h507797[56] ? + assign _theResult___fst_exp__h507215 = + (_theResult___fst_exp__h506457 == 11'd2047) ? + _theResult___fst_exp__h506457 : + _theResult___fst_exp__h507212 ; + assign _theResult___fst_exp__h516034 = + _theResult____h507798[56] ? 11'd2 : - _theResult___fst_exp__h516107 ; - assign _theResult___fst_exp__h516098 = + _theResult___fst_exp__h516108 ; + assign _theResult___fst_exp__h516099 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 } ; - assign _theResult___fst_exp__h516104 = - (!_theResult____h507797[56] && !_theResult____h507797[55] && - !_theResult____h507797[54] && - !_theResult____h507797[53] && - !_theResult____h507797[52] && - !_theResult____h507797[51] && - !_theResult____h507797[50] && - !_theResult____h507797[49] && - !_theResult____h507797[48] && - !_theResult____h507797[47] && - !_theResult____h507797[46] && - !_theResult____h507797[45] && - !_theResult____h507797[44] && - !_theResult____h507797[43] && - !_theResult____h507797[42] && - !_theResult____h507797[41] && - !_theResult____h507797[40] && - !_theResult____h507797[39] && - !_theResult____h507797[38] && - !_theResult____h507797[37] && - !_theResult____h507797[36] && - !_theResult____h507797[35] && - !_theResult____h507797[34] && - !_theResult____h507797[33] && - !_theResult____h507797[32] && - !_theResult____h507797[31] && - !_theResult____h507797[30] && - !_theResult____h507797[29] && - !_theResult____h507797[28] && - !_theResult____h507797[27] && - !_theResult____h507797[26] && - !_theResult____h507797[25] && - !_theResult____h507797[24] && - !_theResult____h507797[23] && - !_theResult____h507797[22] && - !_theResult____h507797[21] && - !_theResult____h507797[20] && - !_theResult____h507797[19] && - !_theResult____h507797[18] && - !_theResult____h507797[17] && - !_theResult____h507797[16] && - !_theResult____h507797[15] && - !_theResult____h507797[14] && - !_theResult____h507797[13] && - !_theResult____h507797[12] && - !_theResult____h507797[11] && - !_theResult____h507797[10] && - !_theResult____h507797[9] && - !_theResult____h507797[8] && - !_theResult____h507797[7] && - !_theResult____h507797[6] && - !_theResult____h507797[5] && - !_theResult____h507797[4] && - !_theResult____h507797[3] && - !_theResult____h507797[2] && - !_theResult____h507797[1] && - !_theResult____h507797[0] || + assign _theResult___fst_exp__h516105 = + (!_theResult____h507798[56] && !_theResult____h507798[55] && + !_theResult____h507798[54] && + !_theResult____h507798[53] && + !_theResult____h507798[52] && + !_theResult____h507798[51] && + !_theResult____h507798[50] && + !_theResult____h507798[49] && + !_theResult____h507798[48] && + !_theResult____h507798[47] && + !_theResult____h507798[46] && + !_theResult____h507798[45] && + !_theResult____h507798[44] && + !_theResult____h507798[43] && + !_theResult____h507798[42] && + !_theResult____h507798[41] && + !_theResult____h507798[40] && + !_theResult____h507798[39] && + !_theResult____h507798[38] && + !_theResult____h507798[37] && + !_theResult____h507798[36] && + !_theResult____h507798[35] && + !_theResult____h507798[34] && + !_theResult____h507798[33] && + !_theResult____h507798[32] && + !_theResult____h507798[31] && + !_theResult____h507798[30] && + !_theResult____h507798[29] && + !_theResult____h507798[28] && + !_theResult____h507798[27] && + !_theResult____h507798[26] && + !_theResult____h507798[25] && + !_theResult____h507798[24] && + !_theResult____h507798[23] && + !_theResult____h507798[22] && + !_theResult____h507798[21] && + !_theResult____h507798[20] && + !_theResult____h507798[19] && + !_theResult____h507798[18] && + !_theResult____h507798[17] && + !_theResult____h507798[16] && + !_theResult____h507798[15] && + !_theResult____h507798[14] && + !_theResult____h507798[13] && + !_theResult____h507798[12] && + !_theResult____h507798[11] && + !_theResult____h507798[10] && + !_theResult____h507798[9] && + !_theResult____h507798[8] && + !_theResult____h507798[7] && + !_theResult____h507798[6] && + !_theResult____h507798[5] && + !_theResult____h507798[4] && + !_theResult____h507798[3] && + !_theResult____h507798[2] && + !_theResult____h507798[1] && + !_theResult____h507798[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9012) ? 11'd0 : - _theResult___fst_exp__h516098 ; - assign _theResult___fst_exp__h516107 = - (!_theResult____h507797[56] && _theResult____h507797[55]) ? + _theResult___fst_exp__h516099 ; + assign _theResult___fst_exp__h516108 = + (!_theResult____h507798[56] && _theResult____h507798[55]) ? 11'd1 : - _theResult___fst_exp__h516104 ; - assign _theResult___fst_exp__h516862 = + _theResult___fst_exp__h516105 ; + assign _theResult___fst_exp__h516863 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q212 : + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 ; - assign _theResult___fst_exp__h516865 = - (_theResult___fst_exp__h516033 == 11'd2047) ? - _theResult___fst_exp__h516033 : - _theResult___fst_exp__h516862 ; - assign _theResult___fst_exp__h524818 = + assign _theResult___fst_exp__h516866 = + (_theResult___fst_exp__h516034 == 11'd2047) ? + _theResult___fst_exp__h516034 : + _theResult___fst_exp__h516863 ; + assign _theResult___fst_exp__h524819 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h524857 = + assign _theResult___fst_exp__h524858 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 } ; - assign _theResult___fst_exp__h524863 = - (f1_exp__h487068 == 8'd0 && !f1_sfd__h487069[22] && + assign _theResult___fst_exp__h524864 = + (f1_exp__h487069 == 8'd0 && !f1_sfd__h487070[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9062) ? 11'd0 : - _theResult___fst_exp__h524857 ; - assign _theResult___fst_exp__h524866 = - (f1_exp__h487068 == 8'd0) ? - _theResult___fst_exp__h524863 : - _theResult___fst_exp__h524818 ; - assign _theResult___fst_exp__h525646 = + _theResult___fst_exp__h524858 ; + assign _theResult___fst_exp__h524867 = + (f1_exp__h487069 == 8'd0) ? + _theResult___fst_exp__h524864 : + _theResult___fst_exp__h524819 ; + assign _theResult___fst_exp__h525647 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q214 : + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 ; - assign _theResult___fst_exp__h525649 = - (_theResult___fst_exp__h524866 == 11'd2047) ? - _theResult___fst_exp__h524866 : - _theResult___fst_exp__h525646 ; - assign _theResult___fst_exp__h525658 = - (f1_exp__h487068 == 8'd0) ? + assign _theResult___fst_exp__h525650 = + (_theResult___fst_exp__h524867 == 11'd2047) ? + _theResult___fst_exp__h524867 : + _theResult___fst_exp__h525647 ; + assign _theResult___fst_exp__h525659 = + (f1_exp__h487069 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 ? - _theResult___snd_fst_exp__h507217 : - _theResult___fst_exp__h491383) : + _theResult___snd_fst_exp__h507218 : + _theResult___fst_exp__h491384) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 ? - _theResult___snd_fst_exp__h525652 : - _theResult___fst_exp__h491383) ; - assign _theResult___fst_exp__h525661 = - (f1_exp__h487068 == 8'd0 && f1_sfd__h487069 == 23'd0) ? + _theResult___snd_fst_exp__h525653 : + _theResult___fst_exp__h491384) ; + assign _theResult___fst_exp__h525662 = + (f1_exp__h487069 == 8'd0 && f1_sfd__h487070 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h525658 ; - assign _theResult___fst_exp__h530236 = + _theResult___fst_exp__h525659 ; + assign _theResult___fst_exp__h530237 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; - assign _theResult___fst_exp__h545300 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; + assign _theResult___fst_exp__h545301 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 } ; - assign _theResult___fst_exp__h545306 = - (f2_exp__h526062 == 8'd0 && !f2_sfd__h526063[22] && + assign _theResult___fst_exp__h545307 = + (f2_exp__h526063 == 8'd0 && !f2_sfd__h526064[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10200) ? 11'd0 : - _theResult___fst_exp__h545300 ; - assign _theResult___fst_exp__h545309 = - (f2_exp__h526062 == 8'd0) ? - _theResult___fst_exp__h545306 : + _theResult___fst_exp__h545301 ; + assign _theResult___fst_exp__h545310 = + (f2_exp__h526063 == 8'd0) ? + _theResult___fst_exp__h545307 : 11'd897 ; - assign _theResult___fst_exp__h546064 = + assign _theResult___fst_exp__h546065 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q184 : + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 ; - assign _theResult___fst_exp__h546067 = - (_theResult___fst_exp__h545309 == 11'd2047) ? - _theResult___fst_exp__h545309 : - _theResult___fst_exp__h546064 ; - assign _theResult___fst_exp__h554886 = - _theResult____h546650[56] ? + assign _theResult___fst_exp__h546068 = + (_theResult___fst_exp__h545310 == 11'd2047) ? + _theResult___fst_exp__h545310 : + _theResult___fst_exp__h546065 ; + assign _theResult___fst_exp__h554887 = + _theResult____h546651[56] ? 11'd2 : - _theResult___fst_exp__h554960 ; - assign _theResult___fst_exp__h554951 = + _theResult___fst_exp__h554961 ; + assign _theResult___fst_exp__h554952 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 } ; - assign _theResult___fst_exp__h554957 = - (!_theResult____h546650[56] && !_theResult____h546650[55] && - !_theResult____h546650[54] && - !_theResult____h546650[53] && - !_theResult____h546650[52] && - !_theResult____h546650[51] && - !_theResult____h546650[50] && - !_theResult____h546650[49] && - !_theResult____h546650[48] && - !_theResult____h546650[47] && - !_theResult____h546650[46] && - !_theResult____h546650[45] && - !_theResult____h546650[44] && - !_theResult____h546650[43] && - !_theResult____h546650[42] && - !_theResult____h546650[41] && - !_theResult____h546650[40] && - !_theResult____h546650[39] && - !_theResult____h546650[38] && - !_theResult____h546650[37] && - !_theResult____h546650[36] && - !_theResult____h546650[35] && - !_theResult____h546650[34] && - !_theResult____h546650[33] && - !_theResult____h546650[32] && - !_theResult____h546650[31] && - !_theResult____h546650[30] && - !_theResult____h546650[29] && - !_theResult____h546650[28] && - !_theResult____h546650[27] && - !_theResult____h546650[26] && - !_theResult____h546650[25] && - !_theResult____h546650[24] && - !_theResult____h546650[23] && - !_theResult____h546650[22] && - !_theResult____h546650[21] && - !_theResult____h546650[20] && - !_theResult____h546650[19] && - !_theResult____h546650[18] && - !_theResult____h546650[17] && - !_theResult____h546650[16] && - !_theResult____h546650[15] && - !_theResult____h546650[14] && - !_theResult____h546650[13] && - !_theResult____h546650[12] && - !_theResult____h546650[11] && - !_theResult____h546650[10] && - !_theResult____h546650[9] && - !_theResult____h546650[8] && - !_theResult____h546650[7] && - !_theResult____h546650[6] && - !_theResult____h546650[5] && - !_theResult____h546650[4] && - !_theResult____h546650[3] && - !_theResult____h546650[2] && - !_theResult____h546650[1] && - !_theResult____h546650[0] || + assign _theResult___fst_exp__h554958 = + (!_theResult____h546651[56] && !_theResult____h546651[55] && + !_theResult____h546651[54] && + !_theResult____h546651[53] && + !_theResult____h546651[52] && + !_theResult____h546651[51] && + !_theResult____h546651[50] && + !_theResult____h546651[49] && + !_theResult____h546651[48] && + !_theResult____h546651[47] && + !_theResult____h546651[46] && + !_theResult____h546651[45] && + !_theResult____h546651[44] && + !_theResult____h546651[43] && + !_theResult____h546651[42] && + !_theResult____h546651[41] && + !_theResult____h546651[40] && + !_theResult____h546651[39] && + !_theResult____h546651[38] && + !_theResult____h546651[37] && + !_theResult____h546651[36] && + !_theResult____h546651[35] && + !_theResult____h546651[34] && + !_theResult____h546651[33] && + !_theResult____h546651[32] && + !_theResult____h546651[31] && + !_theResult____h546651[30] && + !_theResult____h546651[29] && + !_theResult____h546651[28] && + !_theResult____h546651[27] && + !_theResult____h546651[26] && + !_theResult____h546651[25] && + !_theResult____h546651[24] && + !_theResult____h546651[23] && + !_theResult____h546651[22] && + !_theResult____h546651[21] && + !_theResult____h546651[20] && + !_theResult____h546651[19] && + !_theResult____h546651[18] && + !_theResult____h546651[17] && + !_theResult____h546651[16] && + !_theResult____h546651[15] && + !_theResult____h546651[14] && + !_theResult____h546651[13] && + !_theResult____h546651[12] && + !_theResult____h546651[11] && + !_theResult____h546651[10] && + !_theResult____h546651[9] && + !_theResult____h546651[8] && + !_theResult____h546651[7] && + !_theResult____h546651[6] && + !_theResult____h546651[5] && + !_theResult____h546651[4] && + !_theResult____h546651[3] && + !_theResult____h546651[2] && + !_theResult____h546651[1] && + !_theResult____h546651[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10497) ? 11'd0 : - _theResult___fst_exp__h554951 ; - assign _theResult___fst_exp__h554960 = - (!_theResult____h546650[56] && _theResult____h546650[55]) ? + _theResult___fst_exp__h554952 ; + assign _theResult___fst_exp__h554961 = + (!_theResult____h546651[56] && _theResult____h546651[55]) ? 11'd1 : - _theResult___fst_exp__h554957 ; - assign _theResult___fst_exp__h555715 = + _theResult___fst_exp__h554958 ; + assign _theResult___fst_exp__h555716 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q186 : + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q186 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 ; - assign _theResult___fst_exp__h555718 = - (_theResult___fst_exp__h554886 == 11'd2047) ? - _theResult___fst_exp__h554886 : - _theResult___fst_exp__h555715 ; - assign _theResult___fst_exp__h563671 = + assign _theResult___fst_exp__h555719 = + (_theResult___fst_exp__h554887 == 11'd2047) ? + _theResult___fst_exp__h554887 : + _theResult___fst_exp__h555716 ; + assign _theResult___fst_exp__h563672 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h563710 = + assign _theResult___fst_exp__h563711 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 } ; - assign _theResult___fst_exp__h563716 = - (f2_exp__h526062 == 8'd0 && !f2_sfd__h526063[22] && + assign _theResult___fst_exp__h563717 = + (f2_exp__h526063 == 8'd0 && !f2_sfd__h526064[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10547) ? 11'd0 : - _theResult___fst_exp__h563710 ; - assign _theResult___fst_exp__h563719 = - (f2_exp__h526062 == 8'd0) ? - _theResult___fst_exp__h563716 : - _theResult___fst_exp__h563671 ; - assign _theResult___fst_exp__h564499 = + _theResult___fst_exp__h563711 ; + assign _theResult___fst_exp__h563720 = + (f2_exp__h526063 == 8'd0) ? + _theResult___fst_exp__h563717 : + _theResult___fst_exp__h563672 ; + assign _theResult___fst_exp__h564500 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q188 : + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 ; - assign _theResult___fst_exp__h564502 = - (_theResult___fst_exp__h563719 == 11'd2047) ? - _theResult___fst_exp__h563719 : - _theResult___fst_exp__h564499 ; - assign _theResult___fst_exp__h564511 = - (f2_exp__h526062 == 8'd0) ? + assign _theResult___fst_exp__h564503 = + (_theResult___fst_exp__h563720 == 11'd2047) ? + _theResult___fst_exp__h563720 : + _theResult___fst_exp__h564500 ; + assign _theResult___fst_exp__h564512 = + (f2_exp__h526063 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 ? - _theResult___snd_fst_exp__h546070 : - _theResult___fst_exp__h530236) : + _theResult___snd_fst_exp__h546071 : + _theResult___fst_exp__h530237) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 ? - _theResult___snd_fst_exp__h564505 : - _theResult___fst_exp__h530236) ; - assign _theResult___fst_exp__h564514 = - (f2_exp__h526062 == 8'd0 && f2_sfd__h526063 == 23'd0) ? + _theResult___snd_fst_exp__h564506 : + _theResult___fst_exp__h530237) ; + assign _theResult___fst_exp__h564515 = + (f2_exp__h526063 == 8'd0 && f2_sfd__h526064 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h564511 ; - assign _theResult___fst_exp__h569540 = + _theResult___fst_exp__h564512 ; + assign _theResult___fst_exp__h569541 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_exp__h584604 = + assign _theResult___fst_exp__h584605 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 } ; - assign _theResult___fst_exp__h584610 = - (f3_exp__h565366 == 8'd0 && !f3_sfd__h565367[22] && + assign _theResult___fst_exp__h584611 = + (f3_exp__h565367 == 8'd0 && !f3_sfd__h565368[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9430) ? 11'd0 : - _theResult___fst_exp__h584604 ; - assign _theResult___fst_exp__h584613 = - (f3_exp__h565366 == 8'd0) ? - _theResult___fst_exp__h584610 : + _theResult___fst_exp__h584605 ; + assign _theResult___fst_exp__h584614 = + (f3_exp__h565367 == 8'd0) ? + _theResult___fst_exp__h584611 : 11'd897 ; - assign _theResult___fst_exp__h585368 = + assign _theResult___fst_exp__h585369 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q161 : + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 ; - assign _theResult___fst_exp__h585371 = - (_theResult___fst_exp__h584613 == 11'd2047) ? - _theResult___fst_exp__h584613 : - _theResult___fst_exp__h585368 ; - assign _theResult___fst_exp__h594190 = - _theResult____h585954[56] ? + assign _theResult___fst_exp__h585372 = + (_theResult___fst_exp__h584614 == 11'd2047) ? + _theResult___fst_exp__h584614 : + _theResult___fst_exp__h585369 ; + assign _theResult___fst_exp__h594191 = + _theResult____h585955[56] ? 11'd2 : - _theResult___fst_exp__h594264 ; - assign _theResult___fst_exp__h594255 = + _theResult___fst_exp__h594265 ; + assign _theResult___fst_exp__h594256 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9725 } ; - assign _theResult___fst_exp__h594261 = - (!_theResult____h585954[56] && !_theResult____h585954[55] && - !_theResult____h585954[54] && - !_theResult____h585954[53] && - !_theResult____h585954[52] && - !_theResult____h585954[51] && - !_theResult____h585954[50] && - !_theResult____h585954[49] && - !_theResult____h585954[48] && - !_theResult____h585954[47] && - !_theResult____h585954[46] && - !_theResult____h585954[45] && - !_theResult____h585954[44] && - !_theResult____h585954[43] && - !_theResult____h585954[42] && - !_theResult____h585954[41] && - !_theResult____h585954[40] && - !_theResult____h585954[39] && - !_theResult____h585954[38] && - !_theResult____h585954[37] && - !_theResult____h585954[36] && - !_theResult____h585954[35] && - !_theResult____h585954[34] && - !_theResult____h585954[33] && - !_theResult____h585954[32] && - !_theResult____h585954[31] && - !_theResult____h585954[30] && - !_theResult____h585954[29] && - !_theResult____h585954[28] && - !_theResult____h585954[27] && - !_theResult____h585954[26] && - !_theResult____h585954[25] && - !_theResult____h585954[24] && - !_theResult____h585954[23] && - !_theResult____h585954[22] && - !_theResult____h585954[21] && - !_theResult____h585954[20] && - !_theResult____h585954[19] && - !_theResult____h585954[18] && - !_theResult____h585954[17] && - !_theResult____h585954[16] && - !_theResult____h585954[15] && - !_theResult____h585954[14] && - !_theResult____h585954[13] && - !_theResult____h585954[12] && - !_theResult____h585954[11] && - !_theResult____h585954[10] && - !_theResult____h585954[9] && - !_theResult____h585954[8] && - !_theResult____h585954[7] && - !_theResult____h585954[6] && - !_theResult____h585954[5] && - !_theResult____h585954[4] && - !_theResult____h585954[3] && - !_theResult____h585954[2] && - !_theResult____h585954[1] && - !_theResult____h585954[0] || + assign _theResult___fst_exp__h594262 = + (!_theResult____h585955[56] && !_theResult____h585955[55] && + !_theResult____h585955[54] && + !_theResult____h585955[53] && + !_theResult____h585955[52] && + !_theResult____h585955[51] && + !_theResult____h585955[50] && + !_theResult____h585955[49] && + !_theResult____h585955[48] && + !_theResult____h585955[47] && + !_theResult____h585955[46] && + !_theResult____h585955[45] && + !_theResult____h585955[44] && + !_theResult____h585955[43] && + !_theResult____h585955[42] && + !_theResult____h585955[41] && + !_theResult____h585955[40] && + !_theResult____h585955[39] && + !_theResult____h585955[38] && + !_theResult____h585955[37] && + !_theResult____h585955[36] && + !_theResult____h585955[35] && + !_theResult____h585955[34] && + !_theResult____h585955[33] && + !_theResult____h585955[32] && + !_theResult____h585955[31] && + !_theResult____h585955[30] && + !_theResult____h585955[29] && + !_theResult____h585955[28] && + !_theResult____h585955[27] && + !_theResult____h585955[26] && + !_theResult____h585955[25] && + !_theResult____h585955[24] && + !_theResult____h585955[23] && + !_theResult____h585955[22] && + !_theResult____h585955[21] && + !_theResult____h585955[20] && + !_theResult____h585955[19] && + !_theResult____h585955[18] && + !_theResult____h585955[17] && + !_theResult____h585955[16] && + !_theResult____h585955[15] && + !_theResult____h585955[14] && + !_theResult____h585955[13] && + !_theResult____h585955[12] && + !_theResult____h585955[11] && + !_theResult____h585955[10] && + !_theResult____h585955[9] && + !_theResult____h585955[8] && + !_theResult____h585955[7] && + !_theResult____h585955[6] && + !_theResult____h585955[5] && + !_theResult____h585955[4] && + !_theResult____h585955[3] && + !_theResult____h585955[2] && + !_theResult____h585955[1] && + !_theResult____h585955[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9727) ? 11'd0 : - _theResult___fst_exp__h594255 ; - assign _theResult___fst_exp__h594264 = - (!_theResult____h585954[56] && _theResult____h585954[55]) ? + _theResult___fst_exp__h594256 ; + assign _theResult___fst_exp__h594265 = + (!_theResult____h585955[56] && _theResult____h585955[55]) ? 11'd1 : - _theResult___fst_exp__h594261 ; - assign _theResult___fst_exp__h595019 = + _theResult___fst_exp__h594262 ; + assign _theResult___fst_exp__h595020 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q190 : + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 ; - assign _theResult___fst_exp__h595022 = - (_theResult___fst_exp__h594190 == 11'd2047) ? - _theResult___fst_exp__h594190 : - _theResult___fst_exp__h595019 ; - assign _theResult___fst_exp__h602975 = + assign _theResult___fst_exp__h595023 = + (_theResult___fst_exp__h594191 == 11'd2047) ? + _theResult___fst_exp__h594191 : + _theResult___fst_exp__h595020 ; + assign _theResult___fst_exp__h602976 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h603014 = + assign _theResult___fst_exp__h603015 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 } ; - assign _theResult___fst_exp__h603020 = - (f3_exp__h565366 == 8'd0 && !f3_sfd__h565367[22] && + assign _theResult___fst_exp__h603021 = + (f3_exp__h565367 == 8'd0 && !f3_sfd__h565368[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9777) ? 11'd0 : - _theResult___fst_exp__h603014 ; - assign _theResult___fst_exp__h603023 = - (f3_exp__h565366 == 8'd0) ? - _theResult___fst_exp__h603020 : - _theResult___fst_exp__h602975 ; - assign _theResult___fst_exp__h603803 = + _theResult___fst_exp__h603015 ; + assign _theResult___fst_exp__h603024 = + (f3_exp__h565367 == 8'd0) ? + _theResult___fst_exp__h603021 : + _theResult___fst_exp__h602976 ; + assign _theResult___fst_exp__h603804 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q192 : + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 ; - assign _theResult___fst_exp__h603806 = - (_theResult___fst_exp__h603023 == 11'd2047) ? - _theResult___fst_exp__h603023 : - _theResult___fst_exp__h603803 ; - assign _theResult___fst_exp__h603815 = - (f3_exp__h565366 == 8'd0) ? + assign _theResult___fst_exp__h603807 = + (_theResult___fst_exp__h603024 == 11'd2047) ? + _theResult___fst_exp__h603024 : + _theResult___fst_exp__h603804 ; + assign _theResult___fst_exp__h603816 = + (f3_exp__h565367 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 ? - _theResult___snd_fst_exp__h585374 : - _theResult___fst_exp__h569540) : + _theResult___snd_fst_exp__h585375 : + _theResult___fst_exp__h569541) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 ? - _theResult___snd_fst_exp__h603809 : - _theResult___fst_exp__h569540) ; - assign _theResult___fst_exp__h603818 = - (f3_exp__h565366 == 8'd0 && f3_sfd__h565367 == 23'd0) ? + _theResult___snd_fst_exp__h603810 : + _theResult___fst_exp__h569541) ; + assign _theResult___fst_exp__h603819 = + (f3_exp__h565367 == 8'd0 && f3_sfd__h565368 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h603815 ; - assign _theResult___fst_sfd__h359214 = - (_theResult___fst_exp__h358616 == 8'd255) ? - sfdin__h358610[56:34] : - _theResult___fst_sfd__h359211 ; - assign _theResult___fst_sfd__h367796 = - (_theResult___fst_exp__h367272 == 8'd255) ? - _theResult___snd__h367223[56:34] : - _theResult___fst_sfd__h367793 ; - assign _theResult___fst_sfd__h376980 = - (_theResult___fst_exp__h376382 == 8'd255) ? - sfdin__h376376[56:34] : - _theResult___fst_sfd__h376977 ; - assign _theResult___fst_sfd__h385616 = - (_theResult___fst_exp__h385067 == 8'd255) ? - _theResult___snd__h385013[56:34] : - _theResult___fst_sfd__h385613 ; - assign _theResult___fst_sfd__h385625 = + _theResult___fst_exp__h603816 ; + assign _theResult___fst_sfd__h359215 = + (_theResult___fst_exp__h358617 == 8'd255) ? + sfdin__h358611[56:34] : + _theResult___fst_sfd__h359212 ; + assign _theResult___fst_sfd__h367797 = + (_theResult___fst_exp__h367273 == 8'd255) ? + _theResult___snd__h367224[56:34] : + _theResult___fst_sfd__h367794 ; + assign _theResult___fst_sfd__h376981 = + (_theResult___fst_exp__h376383 == 8'd255) ? + sfdin__h376377[56:34] : + _theResult___fst_sfd__h376978 ; + assign _theResult___fst_sfd__h385617 = + (_theResult___fst_exp__h385068 == 8'd255) ? + _theResult___snd__h385014[56:34] : + _theResult___fst_sfd__h385614 ; + assign _theResult___fst_sfd__h385626 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112 ? - _theResult___snd_fst_sfd__h367799 : - _theResult___fst_sfd__h350488) : + _theResult___snd_fst_sfd__h367800 : + _theResult___fst_sfd__h350489) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4652 ? - _theResult___snd_fst_sfd__h385619 : - _theResult___fst_sfd__h350488) ; - assign _theResult___fst_sfd__h385631 = + _theResult___snd_fst_sfd__h385620 : + _theResult___fst_sfd__h350489) ; + assign _theResult___fst_sfd__h385632 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -28402,33 +28429,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h385625 ; - assign _theResult___fst_sfd__h404911 = - (_theResult___fst_exp__h404313 == 8'd255) ? - sfdin__h404307[56:34] : - _theResult___fst_sfd__h404908 ; - assign _theResult___fst_sfd__h413493 = - (_theResult___fst_exp__h412969 == 8'd255) ? - _theResult___snd__h412920[56:34] : - _theResult___fst_sfd__h413490 ; - assign _theResult___fst_sfd__h422677 = - (_theResult___fst_exp__h422079 == 8'd255) ? - sfdin__h422073[56:34] : - _theResult___fst_sfd__h422674 ; - assign _theResult___fst_sfd__h431313 = - (_theResult___fst_exp__h430764 == 8'd255) ? - _theResult___snd__h430710[56:34] : - _theResult___fst_sfd__h431310 ; - assign _theResult___fst_sfd__h431322 = + _theResult___fst_sfd__h385626 ; + assign _theResult___fst_sfd__h404912 = + (_theResult___fst_exp__h404314 == 8'd255) ? + sfdin__h404308[56:34] : + _theResult___fst_sfd__h404909 ; + assign _theResult___fst_sfd__h413494 = + (_theResult___fst_exp__h412970 == 8'd255) ? + _theResult___snd__h412921[56:34] : + _theResult___fst_sfd__h413491 ; + assign _theResult___fst_sfd__h422678 = + (_theResult___fst_exp__h422080 == 8'd255) ? + sfdin__h422074[56:34] : + _theResult___fst_sfd__h422675 ; + assign _theResult___fst_sfd__h431314 = + (_theResult___fst_exp__h430765 == 8'd255) ? + _theResult___snd__h430711[56:34] : + _theResult___fst_sfd__h431311 ; + assign _theResult___fst_sfd__h431323 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5504 ? - _theResult___snd_fst_sfd__h413496 : - _theResult___fst_sfd__h396187) : + _theResult___snd_fst_sfd__h413497 : + _theResult___fst_sfd__h396188) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6044 ? - _theResult___snd_fst_sfd__h431316 : - _theResult___fst_sfd__h396187) ; - assign _theResult___fst_sfd__h431328 = + _theResult___snd_fst_sfd__h431317 : + _theResult___fst_sfd__h396188) ; + assign _theResult___fst_sfd__h431329 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -28436,33 +28463,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h431322 ; - assign _theResult___fst_sfd__h450606 = - (_theResult___fst_exp__h450008 == 8'd255) ? - sfdin__h450002[56:34] : - _theResult___fst_sfd__h450603 ; - assign _theResult___fst_sfd__h459188 = - (_theResult___fst_exp__h458664 == 8'd255) ? - _theResult___snd__h458615[56:34] : - _theResult___fst_sfd__h459185 ; - assign _theResult___fst_sfd__h468372 = - (_theResult___fst_exp__h467774 == 8'd255) ? - sfdin__h467768[56:34] : - _theResult___fst_sfd__h468369 ; - assign _theResult___fst_sfd__h477008 = - (_theResult___fst_exp__h476459 == 8'd255) ? - _theResult___snd__h476405[56:34] : - _theResult___fst_sfd__h477005 ; - assign _theResult___fst_sfd__h477017 = + _theResult___fst_sfd__h431323 ; + assign _theResult___fst_sfd__h450607 = + (_theResult___fst_exp__h450009 == 8'd255) ? + sfdin__h450003[56:34] : + _theResult___fst_sfd__h450604 ; + assign _theResult___fst_sfd__h459189 = + (_theResult___fst_exp__h458665 == 8'd255) ? + _theResult___snd__h458616[56:34] : + _theResult___fst_sfd__h459186 ; + assign _theResult___fst_sfd__h468373 = + (_theResult___fst_exp__h467775 == 8'd255) ? + sfdin__h467769[56:34] : + _theResult___fst_sfd__h468370 ; + assign _theResult___fst_sfd__h477009 = + (_theResult___fst_exp__h476460 == 8'd255) ? + _theResult___snd__h476406[56:34] : + _theResult___fst_sfd__h477006 ; + assign _theResult___fst_sfd__h477018 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6896 ? - _theResult___snd_fst_sfd__h459191 : - _theResult___fst_sfd__h441882) : + _theResult___snd_fst_sfd__h459192 : + _theResult___fst_sfd__h441883) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7436 ? - _theResult___snd_fst_sfd__h477011 : - _theResult___fst_sfd__h441882) ; - assign _theResult___fst_sfd__h477023 = + _theResult___snd_fst_sfd__h477012 : + _theResult___fst_sfd__h441883) ; + assign _theResult___fst_sfd__h477024 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -28470,1313 +28497,1313 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h477017 ; - assign _theResult___fst_sfd__h491384 = + _theResult___fst_sfd__h477018 ; + assign _theResult___fst_sfd__h491385 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_sfd__h507212 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + assign _theResult___fst_sfd__h507213 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q216 : + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 ; - assign _theResult___fst_sfd__h507215 = - (_theResult___fst_exp__h506456 == 11'd2047) ? - _theResult___snd__h506407[56:5] : - _theResult___fst_sfd__h507212 ; - assign _theResult___fst_sfd__h516863 = + assign _theResult___fst_sfd__h507216 = + (_theResult___fst_exp__h506457 == 11'd2047) ? + _theResult___snd__h506408[56:5] : + _theResult___fst_sfd__h507213 ; + assign _theResult___fst_sfd__h516864 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 ; - assign _theResult___fst_sfd__h516866 = - (_theResult___fst_exp__h516033 == 11'd2047) ? - sfdin__h516027[56:5] : - _theResult___fst_sfd__h516863 ; - assign _theResult___fst_sfd__h525647 = + assign _theResult___fst_sfd__h516867 = + (_theResult___fst_exp__h516034 == 11'd2047) ? + sfdin__h516028[56:5] : + _theResult___fst_sfd__h516864 ; + assign _theResult___fst_sfd__h525648 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q220 : + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 ; - assign _theResult___fst_sfd__h525650 = - (_theResult___fst_exp__h524866 == 11'd2047) ? - _theResult___snd__h524812[56:5] : - _theResult___fst_sfd__h525647 ; - assign _theResult___fst_sfd__h525659 = - (f1_exp__h487068 == 8'd0) ? + assign _theResult___fst_sfd__h525651 = + (_theResult___fst_exp__h524867 == 11'd2047) ? + _theResult___snd__h524813[56:5] : + _theResult___fst_sfd__h525648 ; + assign _theResult___fst_sfd__h525660 = + (f1_exp__h487069 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 ? - _theResult___snd_fst_sfd__h507218 : - _theResult___fst_sfd__h491384) : + _theResult___snd_fst_sfd__h507219 : + _theResult___fst_sfd__h491385) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 ? - _theResult___snd_fst_sfd__h525653 : - _theResult___fst_sfd__h491384) ; - assign _theResult___fst_sfd__h525665 = - ((f1_exp__h487068 == 8'd255 || f1_exp__h487068 == 8'd0) && - f1_sfd__h487069 == 23'd0) ? + _theResult___snd_fst_sfd__h525654 : + _theResult___fst_sfd__h491385) ; + assign _theResult___fst_sfd__h525666 = + ((f1_exp__h487069 == 8'd255 || f1_exp__h487069 == 8'd0) && + f1_sfd__h487070 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h525659 ; - assign _theResult___fst_sfd__h530237 = + _theResult___fst_sfd__h525660 ; + assign _theResult___fst_sfd__h530238 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_sfd__h546065 = + assign _theResult___fst_sfd__h546066 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q206 : + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 ; - assign _theResult___fst_sfd__h546068 = - (_theResult___fst_exp__h545309 == 11'd2047) ? - _theResult___snd__h545260[56:5] : - _theResult___fst_sfd__h546065 ; - assign _theResult___fst_sfd__h555716 = + assign _theResult___fst_sfd__h546069 = + (_theResult___fst_exp__h545310 == 11'd2047) ? + _theResult___snd__h545261[56:5] : + _theResult___fst_sfd__h546066 ; + assign _theResult___fst_sfd__h555717 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 ; - assign _theResult___fst_sfd__h555719 = - (_theResult___fst_exp__h554886 == 11'd2047) ? - sfdin__h554880[56:5] : - _theResult___fst_sfd__h555716 ; - assign _theResult___fst_sfd__h564500 = + assign _theResult___fst_sfd__h555720 = + (_theResult___fst_exp__h554887 == 11'd2047) ? + sfdin__h554881[56:5] : + _theResult___fst_sfd__h555717 ; + assign _theResult___fst_sfd__h564501 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q210 : + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 ; - assign _theResult___fst_sfd__h564503 = - (_theResult___fst_exp__h563719 == 11'd2047) ? - _theResult___snd__h563665[56:5] : - _theResult___fst_sfd__h564500 ; - assign _theResult___fst_sfd__h564512 = - (f2_exp__h526062 == 8'd0) ? + assign _theResult___fst_sfd__h564504 = + (_theResult___fst_exp__h563720 == 11'd2047) ? + _theResult___snd__h563666[56:5] : + _theResult___fst_sfd__h564501 ; + assign _theResult___fst_sfd__h564513 = + (f2_exp__h526063 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 ? - _theResult___snd_fst_sfd__h546071 : - _theResult___fst_sfd__h530237) : + _theResult___snd_fst_sfd__h546072 : + _theResult___fst_sfd__h530238) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 ? - _theResult___snd_fst_sfd__h564506 : - _theResult___fst_sfd__h530237) ; - assign _theResult___fst_sfd__h564518 = - ((f2_exp__h526062 == 8'd255 || f2_exp__h526062 == 8'd0) && - f2_sfd__h526063 == 23'd0) ? + _theResult___snd_fst_sfd__h564507 : + _theResult___fst_sfd__h530238) ; + assign _theResult___fst_sfd__h564519 = + ((f2_exp__h526063 == 8'd255 || f2_exp__h526063 == 8'd0) && + f2_sfd__h526064 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h564512 ; - assign _theResult___fst_sfd__h569541 = + _theResult___fst_sfd__h564513 ; + assign _theResult___fst_sfd__h569542 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 ; - assign _theResult___fst_sfd__h585369 = + assign _theResult___fst_sfd__h585370 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q222 : + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 ; - assign _theResult___fst_sfd__h585372 = - (_theResult___fst_exp__h584613 == 11'd2047) ? - _theResult___snd__h584564[56:5] : - _theResult___fst_sfd__h585369 ; - assign _theResult___fst_sfd__h595020 = + assign _theResult___fst_sfd__h585373 = + (_theResult___fst_exp__h584614 == 11'd2047) ? + _theResult___snd__h584565[56:5] : + _theResult___fst_sfd__h585370 ; + assign _theResult___fst_sfd__h595021 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 ; - assign _theResult___fst_sfd__h595023 = - (_theResult___fst_exp__h594190 == 11'd2047) ? - sfdin__h594184[56:5] : - _theResult___fst_sfd__h595020 ; - assign _theResult___fst_sfd__h603804 = + assign _theResult___fst_sfd__h595024 = + (_theResult___fst_exp__h594191 == 11'd2047) ? + sfdin__h594185[56:5] : + _theResult___fst_sfd__h595021 ; + assign _theResult___fst_sfd__h603805 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q226 : + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 ; - assign _theResult___fst_sfd__h603807 = - (_theResult___fst_exp__h603023 == 11'd2047) ? - _theResult___snd__h602969[56:5] : - _theResult___fst_sfd__h603804 ; - assign _theResult___fst_sfd__h603816 = - (f3_exp__h565366 == 8'd0) ? + assign _theResult___fst_sfd__h603808 = + (_theResult___fst_exp__h603024 == 11'd2047) ? + _theResult___snd__h602970[56:5] : + _theResult___fst_sfd__h603805 ; + assign _theResult___fst_sfd__h603817 = + (f3_exp__h565367 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 ? - _theResult___snd_fst_sfd__h585375 : - _theResult___fst_sfd__h569541) : + _theResult___snd_fst_sfd__h585376 : + _theResult___fst_sfd__h569542) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 ? - _theResult___snd_fst_sfd__h603810 : - _theResult___fst_sfd__h569541) ; - assign _theResult___fst_sfd__h603822 = - ((f3_exp__h565366 == 8'd255 || f3_exp__h565366 == 8'd0) && - f3_sfd__h565367 == 23'd0) ? + _theResult___snd_fst_sfd__h603811 : + _theResult___fst_sfd__h569542) ; + assign _theResult___fst_sfd__h603823 = + ((f3_exp__h565367 == 8'd255 || f3_exp__h565367 == 8'd0) && + f3_sfd__h565368 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h603816 ; - assign _theResult___sfd__h359133 = - sfd__h358708[24] ? - ((_theResult___fst_exp__h358616 == 8'd254) ? + _theResult___fst_sfd__h603817 ; + assign _theResult___sfd__h359134 = + sfd__h358709[24] ? + ((_theResult___fst_exp__h358617 == 8'd254) ? 23'd0 : - sfd__h358708[23:1]) : - sfd__h358708[22:0] ; - assign _theResult___sfd__h367715 = - sfd__h367290[24] ? - ((_theResult___fst_exp__h367272 == 8'd254) ? + sfd__h358709[23:1]) : + sfd__h358709[22:0] ; + assign _theResult___sfd__h367716 = + sfd__h367291[24] ? + ((_theResult___fst_exp__h367273 == 8'd254) ? 23'd0 : - sfd__h367290[23:1]) : - sfd__h367290[22:0] ; - assign _theResult___sfd__h376899 = - sfd__h376474[24] ? - ((_theResult___fst_exp__h376382 == 8'd254) ? + sfd__h367291[23:1]) : + sfd__h367291[22:0] ; + assign _theResult___sfd__h376900 = + sfd__h376475[24] ? + ((_theResult___fst_exp__h376383 == 8'd254) ? 23'd0 : - sfd__h376474[23:1]) : - sfd__h376474[22:0] ; - assign _theResult___sfd__h385535 = - sfd__h385086[24] ? - ((_theResult___fst_exp__h385067 == 8'd254) ? + sfd__h376475[23:1]) : + sfd__h376475[22:0] ; + assign _theResult___sfd__h385536 = + sfd__h385087[24] ? + ((_theResult___fst_exp__h385068 == 8'd254) ? 23'd0 : - sfd__h385086[23:1]) : - sfd__h385086[22:0] ; - assign _theResult___sfd__h385637 = + sfd__h385087[23:1]) : + sfd__h385087[22:0] ; + assign _theResult___sfd__h385638 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h342850 : - _theResult___fst_sfd__h385631 ; - assign _theResult___sfd__h404830 = - sfd__h404405[24] ? - ((_theResult___fst_exp__h404313 == 8'd254) ? + _theResult___snd_fst_sfd__h342851 : + _theResult___fst_sfd__h385632 ; + assign _theResult___sfd__h404831 = + sfd__h404406[24] ? + ((_theResult___fst_exp__h404314 == 8'd254) ? 23'd0 : - sfd__h404405[23:1]) : - sfd__h404405[22:0] ; - assign _theResult___sfd__h413412 = - sfd__h412987[24] ? - ((_theResult___fst_exp__h412969 == 8'd254) ? + sfd__h404406[23:1]) : + sfd__h404406[22:0] ; + assign _theResult___sfd__h413413 = + sfd__h412988[24] ? + ((_theResult___fst_exp__h412970 == 8'd254) ? 23'd0 : - sfd__h412987[23:1]) : - sfd__h412987[22:0] ; - assign _theResult___sfd__h422596 = - sfd__h422171[24] ? - ((_theResult___fst_exp__h422079 == 8'd254) ? + sfd__h412988[23:1]) : + sfd__h412988[22:0] ; + assign _theResult___sfd__h422597 = + sfd__h422172[24] ? + ((_theResult___fst_exp__h422080 == 8'd254) ? 23'd0 : - sfd__h422171[23:1]) : - sfd__h422171[22:0] ; - assign _theResult___sfd__h431232 = - sfd__h430783[24] ? - ((_theResult___fst_exp__h430764 == 8'd254) ? + sfd__h422172[23:1]) : + sfd__h422172[22:0] ; + assign _theResult___sfd__h431233 = + sfd__h430784[24] ? + ((_theResult___fst_exp__h430765 == 8'd254) ? 23'd0 : - sfd__h430783[23:1]) : - sfd__h430783[22:0] ; - assign _theResult___sfd__h431334 = + sfd__h430784[23:1]) : + sfd__h430784[22:0] ; + assign _theResult___sfd__h431335 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h388552 : - _theResult___fst_sfd__h431328 ; - assign _theResult___sfd__h450525 = - sfd__h450100[24] ? - ((_theResult___fst_exp__h450008 == 8'd254) ? + _theResult___snd_fst_sfd__h388553 : + _theResult___fst_sfd__h431329 ; + assign _theResult___sfd__h450526 = + sfd__h450101[24] ? + ((_theResult___fst_exp__h450009 == 8'd254) ? 23'd0 : - sfd__h450100[23:1]) : - sfd__h450100[22:0] ; - assign _theResult___sfd__h459107 = - sfd__h458682[24] ? - ((_theResult___fst_exp__h458664 == 8'd254) ? + sfd__h450101[23:1]) : + sfd__h450101[22:0] ; + assign _theResult___sfd__h459108 = + sfd__h458683[24] ? + ((_theResult___fst_exp__h458665 == 8'd254) ? 23'd0 : - sfd__h458682[23:1]) : - sfd__h458682[22:0] ; - assign _theResult___sfd__h468291 = - sfd__h467866[24] ? - ((_theResult___fst_exp__h467774 == 8'd254) ? + sfd__h458683[23:1]) : + sfd__h458683[22:0] ; + assign _theResult___sfd__h468292 = + sfd__h467867[24] ? + ((_theResult___fst_exp__h467775 == 8'd254) ? 23'd0 : - sfd__h467866[23:1]) : - sfd__h467866[22:0] ; - assign _theResult___sfd__h476927 = - sfd__h476478[24] ? - ((_theResult___fst_exp__h476459 == 8'd254) ? + sfd__h467867[23:1]) : + sfd__h467867[22:0] ; + assign _theResult___sfd__h476928 = + sfd__h476479[24] ? + ((_theResult___fst_exp__h476460 == 8'd254) ? 23'd0 : - sfd__h476478[23:1]) : - sfd__h476478[22:0] ; - assign _theResult___sfd__h477029 = + sfd__h476479[23:1]) : + sfd__h476479[22:0] ; + assign _theResult___sfd__h477030 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h434247 : - _theResult___fst_sfd__h477023 ; - assign _theResult___sfd__h507112 = - sfd__h506474[53] ? - ((_theResult___fst_exp__h506456 == 11'd2046) ? + _theResult___snd_fst_sfd__h434248 : + _theResult___fst_sfd__h477024 ; + assign _theResult___sfd__h507113 = + sfd__h506475[53] ? + ((_theResult___fst_exp__h506457 == 11'd2046) ? 52'd0 : - sfd__h506474[52:1]) : - sfd__h506474[51:0] ; - assign _theResult___sfd__h516763 = - sfd__h516125[53] ? - ((_theResult___fst_exp__h516033 == 11'd2046) ? + sfd__h506475[52:1]) : + sfd__h506475[51:0] ; + assign _theResult___sfd__h516764 = + sfd__h516126[53] ? + ((_theResult___fst_exp__h516034 == 11'd2046) ? 52'd0 : - sfd__h516125[52:1]) : - sfd__h516125[51:0] ; - assign _theResult___sfd__h525547 = - sfd__h524885[53] ? - ((_theResult___fst_exp__h524866 == 11'd2046) ? + sfd__h516126[52:1]) : + sfd__h516126[51:0] ; + assign _theResult___sfd__h525548 = + sfd__h524886[53] ? + ((_theResult___fst_exp__h524867 == 11'd2046) ? 52'd0 : - sfd__h524885[52:1]) : - sfd__h524885[51:0] ; - assign _theResult___sfd__h545965 = - sfd__h545327[53] ? - ((_theResult___fst_exp__h545309 == 11'd2046) ? + sfd__h524886[52:1]) : + sfd__h524886[51:0] ; + assign _theResult___sfd__h545966 = + sfd__h545328[53] ? + ((_theResult___fst_exp__h545310 == 11'd2046) ? 52'd0 : - sfd__h545327[52:1]) : - sfd__h545327[51:0] ; - assign _theResult___sfd__h555616 = - sfd__h554978[53] ? - ((_theResult___fst_exp__h554886 == 11'd2046) ? + sfd__h545328[52:1]) : + sfd__h545328[51:0] ; + assign _theResult___sfd__h555617 = + sfd__h554979[53] ? + ((_theResult___fst_exp__h554887 == 11'd2046) ? 52'd0 : - sfd__h554978[52:1]) : - sfd__h554978[51:0] ; - assign _theResult___sfd__h564400 = - sfd__h563738[53] ? - ((_theResult___fst_exp__h563719 == 11'd2046) ? + sfd__h554979[52:1]) : + sfd__h554979[51:0] ; + assign _theResult___sfd__h564401 = + sfd__h563739[53] ? + ((_theResult___fst_exp__h563720 == 11'd2046) ? 52'd0 : - sfd__h563738[52:1]) : - sfd__h563738[51:0] ; - assign _theResult___sfd__h585269 = - sfd__h584631[53] ? - ((_theResult___fst_exp__h584613 == 11'd2046) ? + sfd__h563739[52:1]) : + sfd__h563739[51:0] ; + assign _theResult___sfd__h585270 = + sfd__h584632[53] ? + ((_theResult___fst_exp__h584614 == 11'd2046) ? 52'd0 : - sfd__h584631[52:1]) : - sfd__h584631[51:0] ; - assign _theResult___sfd__h594920 = - sfd__h594282[53] ? - ((_theResult___fst_exp__h594190 == 11'd2046) ? + sfd__h584632[52:1]) : + sfd__h584632[51:0] ; + assign _theResult___sfd__h594921 = + sfd__h594283[53] ? + ((_theResult___fst_exp__h594191 == 11'd2046) ? 52'd0 : - sfd__h594282[52:1]) : - sfd__h594282[51:0] ; - assign _theResult___sfd__h603704 = - sfd__h603042[53] ? - ((_theResult___fst_exp__h603023 == 11'd2046) ? + sfd__h594283[52:1]) : + sfd__h594283[51:0] ; + assign _theResult___sfd__h603705 = + sfd__h603043[53] ? + ((_theResult___fst_exp__h603024 == 11'd2046) ? 52'd0 : - sfd__h603042[52:1]) : - sfd__h603042[51:0] ; - assign _theResult___snd__h358627 = { _theResult____h350505[55:0], 1'd0 } ; - assign _theResult___snd__h358638 = - (!_theResult____h350505[56] && _theResult____h350505[55]) ? - _theResult___snd__h358640 : - _theResult___snd__h358650 ; - assign _theResult___snd__h358640 = { _theResult____h350505[54:0], 2'd0 } ; - assign _theResult___snd__h358650 = - (!_theResult____h350505[56] && !_theResult____h350505[55] && - !_theResult____h350505[54] && - !_theResult____h350505[53] && - !_theResult____h350505[52] && - !_theResult____h350505[51] && - !_theResult____h350505[50] && - !_theResult____h350505[49] && - !_theResult____h350505[48] && - !_theResult____h350505[47] && - !_theResult____h350505[46] && - !_theResult____h350505[45] && - !_theResult____h350505[44] && - !_theResult____h350505[43] && - !_theResult____h350505[42] && - !_theResult____h350505[41] && - !_theResult____h350505[40] && - !_theResult____h350505[39] && - !_theResult____h350505[38] && - !_theResult____h350505[37] && - !_theResult____h350505[36] && - !_theResult____h350505[35] && - !_theResult____h350505[34] && - !_theResult____h350505[33] && - !_theResult____h350505[32] && - !_theResult____h350505[31] && - !_theResult____h350505[30] && - !_theResult____h350505[29] && - !_theResult____h350505[28] && - !_theResult____h350505[27] && - !_theResult____h350505[26] && - !_theResult____h350505[25] && - !_theResult____h350505[24] && - !_theResult____h350505[23] && - !_theResult____h350505[22] && - !_theResult____h350505[21] && - !_theResult____h350505[20] && - !_theResult____h350505[19] && - !_theResult____h350505[18] && - !_theResult____h350505[17] && - !_theResult____h350505[16] && - !_theResult____h350505[15] && - !_theResult____h350505[14] && - !_theResult____h350505[13] && - !_theResult____h350505[12] && - !_theResult____h350505[11] && - !_theResult____h350505[10] && - !_theResult____h350505[9] && - !_theResult____h350505[8] && - !_theResult____h350505[7] && - !_theResult____h350505[6] && - !_theResult____h350505[5] && - !_theResult____h350505[4] && - !_theResult____h350505[3] && - !_theResult____h350505[2] && - !_theResult____h350505[1] && - !_theResult____h350505[0]) ? - _theResult____h350505 : - _theResult___snd__h358656 ; - assign _theResult___snd__h358656 = + sfd__h603043[52:1]) : + sfd__h603043[51:0] ; + assign _theResult___snd__h358628 = { _theResult____h350506[55:0], 1'd0 } ; + assign _theResult___snd__h358639 = + (!_theResult____h350506[56] && _theResult____h350506[55]) ? + _theResult___snd__h358641 : + _theResult___snd__h358651 ; + assign _theResult___snd__h358641 = { _theResult____h350506[54:0], 2'd0 } ; + assign _theResult___snd__h358651 = + (!_theResult____h350506[56] && !_theResult____h350506[55] && + !_theResult____h350506[54] && + !_theResult____h350506[53] && + !_theResult____h350506[52] && + !_theResult____h350506[51] && + !_theResult____h350506[50] && + !_theResult____h350506[49] && + !_theResult____h350506[48] && + !_theResult____h350506[47] && + !_theResult____h350506[46] && + !_theResult____h350506[45] && + !_theResult____h350506[44] && + !_theResult____h350506[43] && + !_theResult____h350506[42] && + !_theResult____h350506[41] && + !_theResult____h350506[40] && + !_theResult____h350506[39] && + !_theResult____h350506[38] && + !_theResult____h350506[37] && + !_theResult____h350506[36] && + !_theResult____h350506[35] && + !_theResult____h350506[34] && + !_theResult____h350506[33] && + !_theResult____h350506[32] && + !_theResult____h350506[31] && + !_theResult____h350506[30] && + !_theResult____h350506[29] && + !_theResult____h350506[28] && + !_theResult____h350506[27] && + !_theResult____h350506[26] && + !_theResult____h350506[25] && + !_theResult____h350506[24] && + !_theResult____h350506[23] && + !_theResult____h350506[22] && + !_theResult____h350506[21] && + !_theResult____h350506[20] && + !_theResult____h350506[19] && + !_theResult____h350506[18] && + !_theResult____h350506[17] && + !_theResult____h350506[16] && + !_theResult____h350506[15] && + !_theResult____h350506[14] && + !_theResult____h350506[13] && + !_theResult____h350506[12] && + !_theResult____h350506[11] && + !_theResult____h350506[10] && + !_theResult____h350506[9] && + !_theResult____h350506[8] && + !_theResult____h350506[7] && + !_theResult____h350506[6] && + !_theResult____h350506[5] && + !_theResult____h350506[4] && + !_theResult____h350506[3] && + !_theResult____h350506[2] && + !_theResult____h350506[1] && + !_theResult____h350506[0]) ? + _theResult____h350506 : + _theResult___snd__h358657 ; + assign _theResult___snd__h358657 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29[54:0], 2'd0 } ; - assign _theResult___snd__h358679 = - _theResult____h350505 << + assign _theResult___snd__h358680 = + _theResult____h350506 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347 ; - assign _theResult___snd__h367223 = + assign _theResult___snd__h367224 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h367232 : - _theResult___snd__h367225 ; - assign _theResult___snd__h367225 = + _theResult___snd__h367233 : + _theResult___snd__h367226 ; + assign _theResult___snd__h367226 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h367232 = + assign _theResult___snd__h367233 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523) ? - sfd__h342900 : - _theResult___snd__h367238 ; - assign _theResult___snd__h367238 = + sfd__h342901 : + _theResult___snd__h367239 ; + assign _theResult___snd__h367239 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31[54:0], 2'd0 } ; - assign _theResult___snd__h367261 = - sfd__h342900 << + assign _theResult___snd__h367262 = + sfd__h342901 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578 ; - assign _theResult___snd__h376393 = { _theResult____h368144[55:0], 1'd0 } ; - assign _theResult___snd__h376404 = - (!_theResult____h368144[56] && _theResult____h368144[55]) ? - _theResult___snd__h376406 : - _theResult___snd__h376416 ; - assign _theResult___snd__h376406 = { _theResult____h368144[54:0], 2'd0 } ; - assign _theResult___snd__h376416 = - (!_theResult____h368144[56] && !_theResult____h368144[55] && - !_theResult____h368144[54] && - !_theResult____h368144[53] && - !_theResult____h368144[52] && - !_theResult____h368144[51] && - !_theResult____h368144[50] && - !_theResult____h368144[49] && - !_theResult____h368144[48] && - !_theResult____h368144[47] && - !_theResult____h368144[46] && - !_theResult____h368144[45] && - !_theResult____h368144[44] && - !_theResult____h368144[43] && - !_theResult____h368144[42] && - !_theResult____h368144[41] && - !_theResult____h368144[40] && - !_theResult____h368144[39] && - !_theResult____h368144[38] && - !_theResult____h368144[37] && - !_theResult____h368144[36] && - !_theResult____h368144[35] && - !_theResult____h368144[34] && - !_theResult____h368144[33] && - !_theResult____h368144[32] && - !_theResult____h368144[31] && - !_theResult____h368144[30] && - !_theResult____h368144[29] && - !_theResult____h368144[28] && - !_theResult____h368144[27] && - !_theResult____h368144[26] && - !_theResult____h368144[25] && - !_theResult____h368144[24] && - !_theResult____h368144[23] && - !_theResult____h368144[22] && - !_theResult____h368144[21] && - !_theResult____h368144[20] && - !_theResult____h368144[19] && - !_theResult____h368144[18] && - !_theResult____h368144[17] && - !_theResult____h368144[16] && - !_theResult____h368144[15] && - !_theResult____h368144[14] && - !_theResult____h368144[13] && - !_theResult____h368144[12] && - !_theResult____h368144[11] && - !_theResult____h368144[10] && - !_theResult____h368144[9] && - !_theResult____h368144[8] && - !_theResult____h368144[7] && - !_theResult____h368144[6] && - !_theResult____h368144[5] && - !_theResult____h368144[4] && - !_theResult____h368144[3] && - !_theResult____h368144[2] && - !_theResult____h368144[1] && - !_theResult____h368144[0]) ? - _theResult____h368144 : - _theResult___snd__h376422 ; - assign _theResult___snd__h376422 = + assign _theResult___snd__h376394 = { _theResult____h368145[55:0], 1'd0 } ; + assign _theResult___snd__h376405 = + (!_theResult____h368145[56] && _theResult____h368145[55]) ? + _theResult___snd__h376407 : + _theResult___snd__h376417 ; + assign _theResult___snd__h376407 = { _theResult____h368145[54:0], 2'd0 } ; + assign _theResult___snd__h376417 = + (!_theResult____h368145[56] && !_theResult____h368145[55] && + !_theResult____h368145[54] && + !_theResult____h368145[53] && + !_theResult____h368145[52] && + !_theResult____h368145[51] && + !_theResult____h368145[50] && + !_theResult____h368145[49] && + !_theResult____h368145[48] && + !_theResult____h368145[47] && + !_theResult____h368145[46] && + !_theResult____h368145[45] && + !_theResult____h368145[44] && + !_theResult____h368145[43] && + !_theResult____h368145[42] && + !_theResult____h368145[41] && + !_theResult____h368145[40] && + !_theResult____h368145[39] && + !_theResult____h368145[38] && + !_theResult____h368145[37] && + !_theResult____h368145[36] && + !_theResult____h368145[35] && + !_theResult____h368145[34] && + !_theResult____h368145[33] && + !_theResult____h368145[32] && + !_theResult____h368145[31] && + !_theResult____h368145[30] && + !_theResult____h368145[29] && + !_theResult____h368145[28] && + !_theResult____h368145[27] && + !_theResult____h368145[26] && + !_theResult____h368145[25] && + !_theResult____h368145[24] && + !_theResult____h368145[23] && + !_theResult____h368145[22] && + !_theResult____h368145[21] && + !_theResult____h368145[20] && + !_theResult____h368145[19] && + !_theResult____h368145[18] && + !_theResult____h368145[17] && + !_theResult____h368145[16] && + !_theResult____h368145[15] && + !_theResult____h368145[14] && + !_theResult____h368145[13] && + !_theResult____h368145[12] && + !_theResult____h368145[11] && + !_theResult____h368145[10] && + !_theResult____h368145[9] && + !_theResult____h368145[8] && + !_theResult____h368145[7] && + !_theResult____h368145[6] && + !_theResult____h368145[5] && + !_theResult____h368145[4] && + !_theResult____h368145[3] && + !_theResult____h368145[2] && + !_theResult____h368145[1] && + !_theResult____h368145[0]) ? + _theResult____h368145 : + _theResult___snd__h376423 ; + assign _theResult___snd__h376423 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39[54:0], 2'd0 } ; - assign _theResult___snd__h376445 = - _theResult____h368144 << + assign _theResult___snd__h376446 = + _theResult____h368145 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4898 ; - assign _theResult___snd__h385013 = + assign _theResult___snd__h385014 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h385027 : - _theResult___snd__h367225 ; - assign _theResult___snd__h385027 = + _theResult___snd__h385028 : + _theResult___snd__h367226 ; + assign _theResult___snd__h385028 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523) ? - sfd__h342900 : - _theResult___snd__h385033 ; - assign _theResult___snd__h385033 = + sfd__h342901 : + _theResult___snd__h385034 ; + assign _theResult___snd__h385034 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44[54:0], 2'd0 } ; - assign _theResult___snd__h385051 = - sfd__h342900 << + assign _theResult___snd__h385052 = + sfd__h342901 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4972[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4972) ; - assign _theResult___snd__h404324 = { _theResult____h396204[55:0], 1'd0 } ; - assign _theResult___snd__h404335 = - (!_theResult____h396204[56] && _theResult____h396204[55]) ? - _theResult___snd__h404337 : - _theResult___snd__h404347 ; - assign _theResult___snd__h404337 = { _theResult____h396204[54:0], 2'd0 } ; - assign _theResult___snd__h404347 = - (!_theResult____h396204[56] && !_theResult____h396204[55] && - !_theResult____h396204[54] && - !_theResult____h396204[53] && - !_theResult____h396204[52] && - !_theResult____h396204[51] && - !_theResult____h396204[50] && - !_theResult____h396204[49] && - !_theResult____h396204[48] && - !_theResult____h396204[47] && - !_theResult____h396204[46] && - !_theResult____h396204[45] && - !_theResult____h396204[44] && - !_theResult____h396204[43] && - !_theResult____h396204[42] && - !_theResult____h396204[41] && - !_theResult____h396204[40] && - !_theResult____h396204[39] && - !_theResult____h396204[38] && - !_theResult____h396204[37] && - !_theResult____h396204[36] && - !_theResult____h396204[35] && - !_theResult____h396204[34] && - !_theResult____h396204[33] && - !_theResult____h396204[32] && - !_theResult____h396204[31] && - !_theResult____h396204[30] && - !_theResult____h396204[29] && - !_theResult____h396204[28] && - !_theResult____h396204[27] && - !_theResult____h396204[26] && - !_theResult____h396204[25] && - !_theResult____h396204[24] && - !_theResult____h396204[23] && - !_theResult____h396204[22] && - !_theResult____h396204[21] && - !_theResult____h396204[20] && - !_theResult____h396204[19] && - !_theResult____h396204[18] && - !_theResult____h396204[17] && - !_theResult____h396204[16] && - !_theResult____h396204[15] && - !_theResult____h396204[14] && - !_theResult____h396204[13] && - !_theResult____h396204[12] && - !_theResult____h396204[11] && - !_theResult____h396204[10] && - !_theResult____h396204[9] && - !_theResult____h396204[8] && - !_theResult____h396204[7] && - !_theResult____h396204[6] && - !_theResult____h396204[5] && - !_theResult____h396204[4] && - !_theResult____h396204[3] && - !_theResult____h396204[2] && - !_theResult____h396204[1] && - !_theResult____h396204[0]) ? - _theResult____h396204 : - _theResult___snd__h404353 ; - assign _theResult___snd__h404353 = + assign _theResult___snd__h404325 = { _theResult____h396205[55:0], 1'd0 } ; + assign _theResult___snd__h404336 = + (!_theResult____h396205[56] && _theResult____h396205[55]) ? + _theResult___snd__h404338 : + _theResult___snd__h404348 ; + assign _theResult___snd__h404338 = { _theResult____h396205[54:0], 2'd0 } ; + assign _theResult___snd__h404348 = + (!_theResult____h396205[56] && !_theResult____h396205[55] && + !_theResult____h396205[54] && + !_theResult____h396205[53] && + !_theResult____h396205[52] && + !_theResult____h396205[51] && + !_theResult____h396205[50] && + !_theResult____h396205[49] && + !_theResult____h396205[48] && + !_theResult____h396205[47] && + !_theResult____h396205[46] && + !_theResult____h396205[45] && + !_theResult____h396205[44] && + !_theResult____h396205[43] && + !_theResult____h396205[42] && + !_theResult____h396205[41] && + !_theResult____h396205[40] && + !_theResult____h396205[39] && + !_theResult____h396205[38] && + !_theResult____h396205[37] && + !_theResult____h396205[36] && + !_theResult____h396205[35] && + !_theResult____h396205[34] && + !_theResult____h396205[33] && + !_theResult____h396205[32] && + !_theResult____h396205[31] && + !_theResult____h396205[30] && + !_theResult____h396205[29] && + !_theResult____h396205[28] && + !_theResult____h396205[27] && + !_theResult____h396205[26] && + !_theResult____h396205[25] && + !_theResult____h396205[24] && + !_theResult____h396205[23] && + !_theResult____h396205[22] && + !_theResult____h396205[21] && + !_theResult____h396205[20] && + !_theResult____h396205[19] && + !_theResult____h396205[18] && + !_theResult____h396205[17] && + !_theResult____h396205[16] && + !_theResult____h396205[15] && + !_theResult____h396205[14] && + !_theResult____h396205[13] && + !_theResult____h396205[12] && + !_theResult____h396205[11] && + !_theResult____h396205[10] && + !_theResult____h396205[9] && + !_theResult____h396205[8] && + !_theResult____h396205[7] && + !_theResult____h396205[6] && + !_theResult____h396205[5] && + !_theResult____h396205[4] && + !_theResult____h396205[3] && + !_theResult____h396205[2] && + !_theResult____h396205[1] && + !_theResult____h396205[0]) ? + _theResult____h396205 : + _theResult___snd__h404354 ; + assign _theResult___snd__h404354 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64[54:0], 2'd0 } ; - assign _theResult___snd__h404376 = - _theResult____h396204 << + assign _theResult___snd__h404377 = + _theResult____h396205 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 ; - assign _theResult___snd__h412920 = + assign _theResult___snd__h412921 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h412929 : - _theResult___snd__h412922 ; - assign _theResult___snd__h412922 = + _theResult___snd__h412930 : + _theResult___snd__h412923 ; + assign _theResult___snd__h412923 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h412929 = + assign _theResult___snd__h412930 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915) ? - sfd__h388602 : - _theResult___snd__h412935 ; - assign _theResult___snd__h412935 = + sfd__h388603 : + _theResult___snd__h412936 ; + assign _theResult___snd__h412936 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66[54:0], 2'd0 } ; - assign _theResult___snd__h412958 = - sfd__h388602 << + assign _theResult___snd__h412959 = + sfd__h388603 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 ; - assign _theResult___snd__h422090 = { _theResult____h413841[55:0], 1'd0 } ; - assign _theResult___snd__h422101 = - (!_theResult____h413841[56] && _theResult____h413841[55]) ? - _theResult___snd__h422103 : - _theResult___snd__h422113 ; - assign _theResult___snd__h422103 = { _theResult____h413841[54:0], 2'd0 } ; - assign _theResult___snd__h422113 = - (!_theResult____h413841[56] && !_theResult____h413841[55] && - !_theResult____h413841[54] && - !_theResult____h413841[53] && - !_theResult____h413841[52] && - !_theResult____h413841[51] && - !_theResult____h413841[50] && - !_theResult____h413841[49] && - !_theResult____h413841[48] && - !_theResult____h413841[47] && - !_theResult____h413841[46] && - !_theResult____h413841[45] && - !_theResult____h413841[44] && - !_theResult____h413841[43] && - !_theResult____h413841[42] && - !_theResult____h413841[41] && - !_theResult____h413841[40] && - !_theResult____h413841[39] && - !_theResult____h413841[38] && - !_theResult____h413841[37] && - !_theResult____h413841[36] && - !_theResult____h413841[35] && - !_theResult____h413841[34] && - !_theResult____h413841[33] && - !_theResult____h413841[32] && - !_theResult____h413841[31] && - !_theResult____h413841[30] && - !_theResult____h413841[29] && - !_theResult____h413841[28] && - !_theResult____h413841[27] && - !_theResult____h413841[26] && - !_theResult____h413841[25] && - !_theResult____h413841[24] && - !_theResult____h413841[23] && - !_theResult____h413841[22] && - !_theResult____h413841[21] && - !_theResult____h413841[20] && - !_theResult____h413841[19] && - !_theResult____h413841[18] && - !_theResult____h413841[17] && - !_theResult____h413841[16] && - !_theResult____h413841[15] && - !_theResult____h413841[14] && - !_theResult____h413841[13] && - !_theResult____h413841[12] && - !_theResult____h413841[11] && - !_theResult____h413841[10] && - !_theResult____h413841[9] && - !_theResult____h413841[8] && - !_theResult____h413841[7] && - !_theResult____h413841[6] && - !_theResult____h413841[5] && - !_theResult____h413841[4] && - !_theResult____h413841[3] && - !_theResult____h413841[2] && - !_theResult____h413841[1] && - !_theResult____h413841[0]) ? - _theResult____h413841 : - _theResult___snd__h422119 ; - assign _theResult___snd__h422119 = + assign _theResult___snd__h422091 = { _theResult____h413842[55:0], 1'd0 } ; + assign _theResult___snd__h422102 = + (!_theResult____h413842[56] && _theResult____h413842[55]) ? + _theResult___snd__h422104 : + _theResult___snd__h422114 ; + assign _theResult___snd__h422104 = { _theResult____h413842[54:0], 2'd0 } ; + assign _theResult___snd__h422114 = + (!_theResult____h413842[56] && !_theResult____h413842[55] && + !_theResult____h413842[54] && + !_theResult____h413842[53] && + !_theResult____h413842[52] && + !_theResult____h413842[51] && + !_theResult____h413842[50] && + !_theResult____h413842[49] && + !_theResult____h413842[48] && + !_theResult____h413842[47] && + !_theResult____h413842[46] && + !_theResult____h413842[45] && + !_theResult____h413842[44] && + !_theResult____h413842[43] && + !_theResult____h413842[42] && + !_theResult____h413842[41] && + !_theResult____h413842[40] && + !_theResult____h413842[39] && + !_theResult____h413842[38] && + !_theResult____h413842[37] && + !_theResult____h413842[36] && + !_theResult____h413842[35] && + !_theResult____h413842[34] && + !_theResult____h413842[33] && + !_theResult____h413842[32] && + !_theResult____h413842[31] && + !_theResult____h413842[30] && + !_theResult____h413842[29] && + !_theResult____h413842[28] && + !_theResult____h413842[27] && + !_theResult____h413842[26] && + !_theResult____h413842[25] && + !_theResult____h413842[24] && + !_theResult____h413842[23] && + !_theResult____h413842[22] && + !_theResult____h413842[21] && + !_theResult____h413842[20] && + !_theResult____h413842[19] && + !_theResult____h413842[18] && + !_theResult____h413842[17] && + !_theResult____h413842[16] && + !_theResult____h413842[15] && + !_theResult____h413842[14] && + !_theResult____h413842[13] && + !_theResult____h413842[12] && + !_theResult____h413842[11] && + !_theResult____h413842[10] && + !_theResult____h413842[9] && + !_theResult____h413842[8] && + !_theResult____h413842[7] && + !_theResult____h413842[6] && + !_theResult____h413842[5] && + !_theResult____h413842[4] && + !_theResult____h413842[3] && + !_theResult____h413842[2] && + !_theResult____h413842[1] && + !_theResult____h413842[0]) ? + _theResult____h413842 : + _theResult___snd__h422120 ; + assign _theResult___snd__h422120 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74[54:0], 2'd0 } ; - assign _theResult___snd__h422142 = - _theResult____h413841 << + assign _theResult___snd__h422143 = + _theResult____h413842 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 ; - assign _theResult___snd__h430710 = + assign _theResult___snd__h430711 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h430724 : - _theResult___snd__h412922 ; - assign _theResult___snd__h430724 = + _theResult___snd__h430725 : + _theResult___snd__h412923 ; + assign _theResult___snd__h430725 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915) ? - sfd__h388602 : - _theResult___snd__h430730 ; - assign _theResult___snd__h430730 = + sfd__h388603 : + _theResult___snd__h430731 ; + assign _theResult___snd__h430731 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79[54:0], 2'd0 } ; - assign _theResult___snd__h430748 = - sfd__h388602 << + assign _theResult___snd__h430749 = + sfd__h388603 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364) ; - assign _theResult___snd__h450019 = { _theResult____h441899[55:0], 1'd0 } ; - assign _theResult___snd__h450030 = - (!_theResult____h441899[56] && _theResult____h441899[55]) ? - _theResult___snd__h450032 : - _theResult___snd__h450042 ; - assign _theResult___snd__h450032 = { _theResult____h441899[54:0], 2'd0 } ; - assign _theResult___snd__h450042 = - (!_theResult____h441899[56] && !_theResult____h441899[55] && - !_theResult____h441899[54] && - !_theResult____h441899[53] && - !_theResult____h441899[52] && - !_theResult____h441899[51] && - !_theResult____h441899[50] && - !_theResult____h441899[49] && - !_theResult____h441899[48] && - !_theResult____h441899[47] && - !_theResult____h441899[46] && - !_theResult____h441899[45] && - !_theResult____h441899[44] && - !_theResult____h441899[43] && - !_theResult____h441899[42] && - !_theResult____h441899[41] && - !_theResult____h441899[40] && - !_theResult____h441899[39] && - !_theResult____h441899[38] && - !_theResult____h441899[37] && - !_theResult____h441899[36] && - !_theResult____h441899[35] && - !_theResult____h441899[34] && - !_theResult____h441899[33] && - !_theResult____h441899[32] && - !_theResult____h441899[31] && - !_theResult____h441899[30] && - !_theResult____h441899[29] && - !_theResult____h441899[28] && - !_theResult____h441899[27] && - !_theResult____h441899[26] && - !_theResult____h441899[25] && - !_theResult____h441899[24] && - !_theResult____h441899[23] && - !_theResult____h441899[22] && - !_theResult____h441899[21] && - !_theResult____h441899[20] && - !_theResult____h441899[19] && - !_theResult____h441899[18] && - !_theResult____h441899[17] && - !_theResult____h441899[16] && - !_theResult____h441899[15] && - !_theResult____h441899[14] && - !_theResult____h441899[13] && - !_theResult____h441899[12] && - !_theResult____h441899[11] && - !_theResult____h441899[10] && - !_theResult____h441899[9] && - !_theResult____h441899[8] && - !_theResult____h441899[7] && - !_theResult____h441899[6] && - !_theResult____h441899[5] && - !_theResult____h441899[4] && - !_theResult____h441899[3] && - !_theResult____h441899[2] && - !_theResult____h441899[1] && - !_theResult____h441899[0]) ? - _theResult____h441899 : - _theResult___snd__h450048 ; - assign _theResult___snd__h450048 = + assign _theResult___snd__h450020 = { _theResult____h441900[55:0], 1'd0 } ; + assign _theResult___snd__h450031 = + (!_theResult____h441900[56] && _theResult____h441900[55]) ? + _theResult___snd__h450033 : + _theResult___snd__h450043 ; + assign _theResult___snd__h450033 = { _theResult____h441900[54:0], 2'd0 } ; + assign _theResult___snd__h450043 = + (!_theResult____h441900[56] && !_theResult____h441900[55] && + !_theResult____h441900[54] && + !_theResult____h441900[53] && + !_theResult____h441900[52] && + !_theResult____h441900[51] && + !_theResult____h441900[50] && + !_theResult____h441900[49] && + !_theResult____h441900[48] && + !_theResult____h441900[47] && + !_theResult____h441900[46] && + !_theResult____h441900[45] && + !_theResult____h441900[44] && + !_theResult____h441900[43] && + !_theResult____h441900[42] && + !_theResult____h441900[41] && + !_theResult____h441900[40] && + !_theResult____h441900[39] && + !_theResult____h441900[38] && + !_theResult____h441900[37] && + !_theResult____h441900[36] && + !_theResult____h441900[35] && + !_theResult____h441900[34] && + !_theResult____h441900[33] && + !_theResult____h441900[32] && + !_theResult____h441900[31] && + !_theResult____h441900[30] && + !_theResult____h441900[29] && + !_theResult____h441900[28] && + !_theResult____h441900[27] && + !_theResult____h441900[26] && + !_theResult____h441900[25] && + !_theResult____h441900[24] && + !_theResult____h441900[23] && + !_theResult____h441900[22] && + !_theResult____h441900[21] && + !_theResult____h441900[20] && + !_theResult____h441900[19] && + !_theResult____h441900[18] && + !_theResult____h441900[17] && + !_theResult____h441900[16] && + !_theResult____h441900[15] && + !_theResult____h441900[14] && + !_theResult____h441900[13] && + !_theResult____h441900[12] && + !_theResult____h441900[11] && + !_theResult____h441900[10] && + !_theResult____h441900[9] && + !_theResult____h441900[8] && + !_theResult____h441900[7] && + !_theResult____h441900[6] && + !_theResult____h441900[5] && + !_theResult____h441900[4] && + !_theResult____h441900[3] && + !_theResult____h441900[2] && + !_theResult____h441900[1] && + !_theResult____h441900[0]) ? + _theResult____h441900 : + _theResult___snd__h450049 ; + assign _theResult___snd__h450049 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99[54:0], 2'd0 } ; - assign _theResult___snd__h450071 = - _theResult____h441899 << + assign _theResult___snd__h450072 = + _theResult____h441900 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 ; - assign _theResult___snd__h458615 = + assign _theResult___snd__h458616 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h458624 : - _theResult___snd__h458617 ; - assign _theResult___snd__h458617 = + _theResult___snd__h458625 : + _theResult___snd__h458618 ; + assign _theResult___snd__h458618 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h458624 = + assign _theResult___snd__h458625 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307) ? - sfd__h434297 : - _theResult___snd__h458630 ; - assign _theResult___snd__h458630 = + sfd__h434298 : + _theResult___snd__h458631 ; + assign _theResult___snd__h458631 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101[54:0], 2'd0 } ; - assign _theResult___snd__h458653 = - sfd__h434297 << + assign _theResult___snd__h458654 = + sfd__h434298 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 ; - assign _theResult___snd__h467785 = { _theResult____h459536[55:0], 1'd0 } ; - assign _theResult___snd__h467796 = - (!_theResult____h459536[56] && _theResult____h459536[55]) ? - _theResult___snd__h467798 : - _theResult___snd__h467808 ; - assign _theResult___snd__h467798 = { _theResult____h459536[54:0], 2'd0 } ; - assign _theResult___snd__h467808 = - (!_theResult____h459536[56] && !_theResult____h459536[55] && - !_theResult____h459536[54] && - !_theResult____h459536[53] && - !_theResult____h459536[52] && - !_theResult____h459536[51] && - !_theResult____h459536[50] && - !_theResult____h459536[49] && - !_theResult____h459536[48] && - !_theResult____h459536[47] && - !_theResult____h459536[46] && - !_theResult____h459536[45] && - !_theResult____h459536[44] && - !_theResult____h459536[43] && - !_theResult____h459536[42] && - !_theResult____h459536[41] && - !_theResult____h459536[40] && - !_theResult____h459536[39] && - !_theResult____h459536[38] && - !_theResult____h459536[37] && - !_theResult____h459536[36] && - !_theResult____h459536[35] && - !_theResult____h459536[34] && - !_theResult____h459536[33] && - !_theResult____h459536[32] && - !_theResult____h459536[31] && - !_theResult____h459536[30] && - !_theResult____h459536[29] && - !_theResult____h459536[28] && - !_theResult____h459536[27] && - !_theResult____h459536[26] && - !_theResult____h459536[25] && - !_theResult____h459536[24] && - !_theResult____h459536[23] && - !_theResult____h459536[22] && - !_theResult____h459536[21] && - !_theResult____h459536[20] && - !_theResult____h459536[19] && - !_theResult____h459536[18] && - !_theResult____h459536[17] && - !_theResult____h459536[16] && - !_theResult____h459536[15] && - !_theResult____h459536[14] && - !_theResult____h459536[13] && - !_theResult____h459536[12] && - !_theResult____h459536[11] && - !_theResult____h459536[10] && - !_theResult____h459536[9] && - !_theResult____h459536[8] && - !_theResult____h459536[7] && - !_theResult____h459536[6] && - !_theResult____h459536[5] && - !_theResult____h459536[4] && - !_theResult____h459536[3] && - !_theResult____h459536[2] && - !_theResult____h459536[1] && - !_theResult____h459536[0]) ? - _theResult____h459536 : - _theResult___snd__h467814 ; - assign _theResult___snd__h467814 = + assign _theResult___snd__h467786 = { _theResult____h459537[55:0], 1'd0 } ; + assign _theResult___snd__h467797 = + (!_theResult____h459537[56] && _theResult____h459537[55]) ? + _theResult___snd__h467799 : + _theResult___snd__h467809 ; + assign _theResult___snd__h467799 = { _theResult____h459537[54:0], 2'd0 } ; + assign _theResult___snd__h467809 = + (!_theResult____h459537[56] && !_theResult____h459537[55] && + !_theResult____h459537[54] && + !_theResult____h459537[53] && + !_theResult____h459537[52] && + !_theResult____h459537[51] && + !_theResult____h459537[50] && + !_theResult____h459537[49] && + !_theResult____h459537[48] && + !_theResult____h459537[47] && + !_theResult____h459537[46] && + !_theResult____h459537[45] && + !_theResult____h459537[44] && + !_theResult____h459537[43] && + !_theResult____h459537[42] && + !_theResult____h459537[41] && + !_theResult____h459537[40] && + !_theResult____h459537[39] && + !_theResult____h459537[38] && + !_theResult____h459537[37] && + !_theResult____h459537[36] && + !_theResult____h459537[35] && + !_theResult____h459537[34] && + !_theResult____h459537[33] && + !_theResult____h459537[32] && + !_theResult____h459537[31] && + !_theResult____h459537[30] && + !_theResult____h459537[29] && + !_theResult____h459537[28] && + !_theResult____h459537[27] && + !_theResult____h459537[26] && + !_theResult____h459537[25] && + !_theResult____h459537[24] && + !_theResult____h459537[23] && + !_theResult____h459537[22] && + !_theResult____h459537[21] && + !_theResult____h459537[20] && + !_theResult____h459537[19] && + !_theResult____h459537[18] && + !_theResult____h459537[17] && + !_theResult____h459537[16] && + !_theResult____h459537[15] && + !_theResult____h459537[14] && + !_theResult____h459537[13] && + !_theResult____h459537[12] && + !_theResult____h459537[11] && + !_theResult____h459537[10] && + !_theResult____h459537[9] && + !_theResult____h459537[8] && + !_theResult____h459537[7] && + !_theResult____h459537[6] && + !_theResult____h459537[5] && + !_theResult____h459537[4] && + !_theResult____h459537[3] && + !_theResult____h459537[2] && + !_theResult____h459537[1] && + !_theResult____h459537[0]) ? + _theResult____h459537 : + _theResult___snd__h467815 ; + assign _theResult___snd__h467815 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109[54:0], 2'd0 } ; - assign _theResult___snd__h467837 = - _theResult____h459536 << + assign _theResult___snd__h467838 = + _theResult____h459537 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 ; - assign _theResult___snd__h476405 = + assign _theResult___snd__h476406 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h476419 : - _theResult___snd__h458617 ; - assign _theResult___snd__h476419 = + _theResult___snd__h476420 : + _theResult___snd__h458618 ; + assign _theResult___snd__h476420 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307) ? - sfd__h434297 : - _theResult___snd__h476425 ; - assign _theResult___snd__h476425 = + sfd__h434298 : + _theResult___snd__h476426 ; + assign _theResult___snd__h476426 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114[54:0], 2'd0 } ; - assign _theResult___snd__h476443 = - sfd__h434297 << + assign _theResult___snd__h476444 = + sfd__h434298 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756) ; - assign _theResult___snd__h506407 = - (f1_exp__h487068 == 8'd0) ? - _theResult___snd__h506416 : - _theResult___snd__h506409 ; - assign _theResult___snd__h506409 = { f1_sfd__h487069, 34'd0 } ; - assign _theResult___snd__h506416 = - (f1_exp__h487068 == 8'd0 && !f1_sfd__h487069[22] && + assign _theResult___snd__h506408 = + (f1_exp__h487069 == 8'd0) ? + _theResult___snd__h506417 : + _theResult___snd__h506410 ; + assign _theResult___snd__h506410 = { f1_sfd__h487070, 34'd0 } ; + assign _theResult___snd__h506417 = + (f1_exp__h487069 == 8'd0 && !f1_sfd__h487070[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671) ? - sfd__h487430 : - _theResult___snd__h506422 ; - assign _theResult___snd__h506422 = + sfd__h487431 : + _theResult___snd__h506423 ; + assign _theResult___snd__h506423 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h506445 = - sfd__h487430 << + assign _theResult___snd__h506446 = + sfd__h487431 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 ; - assign _theResult___snd__h516044 = { _theResult____h507797[55:0], 1'd0 } ; - assign _theResult___snd__h516055 = - (!_theResult____h507797[56] && _theResult____h507797[55]) ? - _theResult___snd__h516057 : - _theResult___snd__h516067 ; - assign _theResult___snd__h516057 = { _theResult____h507797[54:0], 2'd0 } ; - assign _theResult___snd__h516067 = - (!_theResult____h507797[56] && !_theResult____h507797[55] && - !_theResult____h507797[54] && - !_theResult____h507797[53] && - !_theResult____h507797[52] && - !_theResult____h507797[51] && - !_theResult____h507797[50] && - !_theResult____h507797[49] && - !_theResult____h507797[48] && - !_theResult____h507797[47] && - !_theResult____h507797[46] && - !_theResult____h507797[45] && - !_theResult____h507797[44] && - !_theResult____h507797[43] && - !_theResult____h507797[42] && - !_theResult____h507797[41] && - !_theResult____h507797[40] && - !_theResult____h507797[39] && - !_theResult____h507797[38] && - !_theResult____h507797[37] && - !_theResult____h507797[36] && - !_theResult____h507797[35] && - !_theResult____h507797[34] && - !_theResult____h507797[33] && - !_theResult____h507797[32] && - !_theResult____h507797[31] && - !_theResult____h507797[30] && - !_theResult____h507797[29] && - !_theResult____h507797[28] && - !_theResult____h507797[27] && - !_theResult____h507797[26] && - !_theResult____h507797[25] && - !_theResult____h507797[24] && - !_theResult____h507797[23] && - !_theResult____h507797[22] && - !_theResult____h507797[21] && - !_theResult____h507797[20] && - !_theResult____h507797[19] && - !_theResult____h507797[18] && - !_theResult____h507797[17] && - !_theResult____h507797[16] && - !_theResult____h507797[15] && - !_theResult____h507797[14] && - !_theResult____h507797[13] && - !_theResult____h507797[12] && - !_theResult____h507797[11] && - !_theResult____h507797[10] && - !_theResult____h507797[9] && - !_theResult____h507797[8] && - !_theResult____h507797[7] && - !_theResult____h507797[6] && - !_theResult____h507797[5] && - !_theResult____h507797[4] && - !_theResult____h507797[3] && - !_theResult____h507797[2] && - !_theResult____h507797[1] && - !_theResult____h507797[0]) ? - _theResult____h507797 : - _theResult___snd__h516073 ; - assign _theResult___snd__h516073 = + assign _theResult___snd__h516045 = { _theResult____h507798[55:0], 1'd0 } ; + assign _theResult___snd__h516056 = + (!_theResult____h507798[56] && _theResult____h507798[55]) ? + _theResult___snd__h516058 : + _theResult___snd__h516068 ; + assign _theResult___snd__h516058 = { _theResult____h507798[54:0], 2'd0 } ; + assign _theResult___snd__h516068 = + (!_theResult____h507798[56] && !_theResult____h507798[55] && + !_theResult____h507798[54] && + !_theResult____h507798[53] && + !_theResult____h507798[52] && + !_theResult____h507798[51] && + !_theResult____h507798[50] && + !_theResult____h507798[49] && + !_theResult____h507798[48] && + !_theResult____h507798[47] && + !_theResult____h507798[46] && + !_theResult____h507798[45] && + !_theResult____h507798[44] && + !_theResult____h507798[43] && + !_theResult____h507798[42] && + !_theResult____h507798[41] && + !_theResult____h507798[40] && + !_theResult____h507798[39] && + !_theResult____h507798[38] && + !_theResult____h507798[37] && + !_theResult____h507798[36] && + !_theResult____h507798[35] && + !_theResult____h507798[34] && + !_theResult____h507798[33] && + !_theResult____h507798[32] && + !_theResult____h507798[31] && + !_theResult____h507798[30] && + !_theResult____h507798[29] && + !_theResult____h507798[28] && + !_theResult____h507798[27] && + !_theResult____h507798[26] && + !_theResult____h507798[25] && + !_theResult____h507798[24] && + !_theResult____h507798[23] && + !_theResult____h507798[22] && + !_theResult____h507798[21] && + !_theResult____h507798[20] && + !_theResult____h507798[19] && + !_theResult____h507798[18] && + !_theResult____h507798[17] && + !_theResult____h507798[16] && + !_theResult____h507798[15] && + !_theResult____h507798[14] && + !_theResult____h507798[13] && + !_theResult____h507798[12] && + !_theResult____h507798[11] && + !_theResult____h507798[10] && + !_theResult____h507798[9] && + !_theResult____h507798[8] && + !_theResult____h507798[7] && + !_theResult____h507798[6] && + !_theResult____h507798[5] && + !_theResult____h507798[4] && + !_theResult____h507798[3] && + !_theResult____h507798[2] && + !_theResult____h507798[1] && + !_theResult____h507798[0]) ? + _theResult____h507798 : + _theResult___snd__h516074 ; + assign _theResult___snd__h516074 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h516096 = - _theResult____h507797 << + assign _theResult___snd__h516097 = + _theResult____h507798 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 ; - assign _theResult___snd__h524812 = - (f1_exp__h487068 == 8'd0) ? - _theResult___snd__h524826 : - _theResult___snd__h506409 ; - assign _theResult___snd__h524826 = - (f1_exp__h487068 == 8'd0 && !f1_sfd__h487069[22] && + assign _theResult___snd__h524813 = + (f1_exp__h487069 == 8'd0) ? + _theResult___snd__h524827 : + _theResult___snd__h506410 ; + assign _theResult___snd__h524827 = + (f1_exp__h487069 == 8'd0 && !f1_sfd__h487070[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671) ? - sfd__h487430 : - _theResult___snd__h524832 ; - assign _theResult___snd__h524832 = + sfd__h487431 : + _theResult___snd__h524833 ; + assign _theResult___snd__h524833 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h524850 = - sfd__h487430 << + assign _theResult___snd__h524851 = + sfd__h487431 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9061 ; - assign _theResult___snd__h545260 = - (f2_exp__h526062 == 8'd0) ? - _theResult___snd__h545269 : - _theResult___snd__h545262 ; - assign _theResult___snd__h545262 = { f2_sfd__h526063, 34'd0 } ; - assign _theResult___snd__h545269 = - (f2_exp__h526062 == 8'd0 && !f2_sfd__h526063[22] && + assign _theResult___snd__h545261 = + (f2_exp__h526063 == 8'd0) ? + _theResult___snd__h545270 : + _theResult___snd__h545263 ; + assign _theResult___snd__h545263 = { f2_sfd__h526064, 34'd0 } ; + assign _theResult___snd__h545270 = + (f2_exp__h526063 == 8'd0 && !f2_sfd__h526064[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171) ? - sfd__h526424 : - _theResult___snd__h545275 ; - assign _theResult___snd__h545275 = + sfd__h526425 : + _theResult___snd__h545276 ; + assign _theResult___snd__h545276 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h545298 = - sfd__h526424 << + assign _theResult___snd__h545299 = + sfd__h526425 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 ; - assign _theResult___snd__h554897 = { _theResult____h546650[55:0], 1'd0 } ; - assign _theResult___snd__h554908 = - (!_theResult____h546650[56] && _theResult____h546650[55]) ? - _theResult___snd__h554910 : - _theResult___snd__h554920 ; - assign _theResult___snd__h554910 = { _theResult____h546650[54:0], 2'd0 } ; - assign _theResult___snd__h554920 = - (!_theResult____h546650[56] && !_theResult____h546650[55] && - !_theResult____h546650[54] && - !_theResult____h546650[53] && - !_theResult____h546650[52] && - !_theResult____h546650[51] && - !_theResult____h546650[50] && - !_theResult____h546650[49] && - !_theResult____h546650[48] && - !_theResult____h546650[47] && - !_theResult____h546650[46] && - !_theResult____h546650[45] && - !_theResult____h546650[44] && - !_theResult____h546650[43] && - !_theResult____h546650[42] && - !_theResult____h546650[41] && - !_theResult____h546650[40] && - !_theResult____h546650[39] && - !_theResult____h546650[38] && - !_theResult____h546650[37] && - !_theResult____h546650[36] && - !_theResult____h546650[35] && - !_theResult____h546650[34] && - !_theResult____h546650[33] && - !_theResult____h546650[32] && - !_theResult____h546650[31] && - !_theResult____h546650[30] && - !_theResult____h546650[29] && - !_theResult____h546650[28] && - !_theResult____h546650[27] && - !_theResult____h546650[26] && - !_theResult____h546650[25] && - !_theResult____h546650[24] && - !_theResult____h546650[23] && - !_theResult____h546650[22] && - !_theResult____h546650[21] && - !_theResult____h546650[20] && - !_theResult____h546650[19] && - !_theResult____h546650[18] && - !_theResult____h546650[17] && - !_theResult____h546650[16] && - !_theResult____h546650[15] && - !_theResult____h546650[14] && - !_theResult____h546650[13] && - !_theResult____h546650[12] && - !_theResult____h546650[11] && - !_theResult____h546650[10] && - !_theResult____h546650[9] && - !_theResult____h546650[8] && - !_theResult____h546650[7] && - !_theResult____h546650[6] && - !_theResult____h546650[5] && - !_theResult____h546650[4] && - !_theResult____h546650[3] && - !_theResult____h546650[2] && - !_theResult____h546650[1] && - !_theResult____h546650[0]) ? - _theResult____h546650 : - _theResult___snd__h554926 ; - assign _theResult___snd__h554926 = + assign _theResult___snd__h554898 = { _theResult____h546651[55:0], 1'd0 } ; + assign _theResult___snd__h554909 = + (!_theResult____h546651[56] && _theResult____h546651[55]) ? + _theResult___snd__h554911 : + _theResult___snd__h554921 ; + assign _theResult___snd__h554911 = { _theResult____h546651[54:0], 2'd0 } ; + assign _theResult___snd__h554921 = + (!_theResult____h546651[56] && !_theResult____h546651[55] && + !_theResult____h546651[54] && + !_theResult____h546651[53] && + !_theResult____h546651[52] && + !_theResult____h546651[51] && + !_theResult____h546651[50] && + !_theResult____h546651[49] && + !_theResult____h546651[48] && + !_theResult____h546651[47] && + !_theResult____h546651[46] && + !_theResult____h546651[45] && + !_theResult____h546651[44] && + !_theResult____h546651[43] && + !_theResult____h546651[42] && + !_theResult____h546651[41] && + !_theResult____h546651[40] && + !_theResult____h546651[39] && + !_theResult____h546651[38] && + !_theResult____h546651[37] && + !_theResult____h546651[36] && + !_theResult____h546651[35] && + !_theResult____h546651[34] && + !_theResult____h546651[33] && + !_theResult____h546651[32] && + !_theResult____h546651[31] && + !_theResult____h546651[30] && + !_theResult____h546651[29] && + !_theResult____h546651[28] && + !_theResult____h546651[27] && + !_theResult____h546651[26] && + !_theResult____h546651[25] && + !_theResult____h546651[24] && + !_theResult____h546651[23] && + !_theResult____h546651[22] && + !_theResult____h546651[21] && + !_theResult____h546651[20] && + !_theResult____h546651[19] && + !_theResult____h546651[18] && + !_theResult____h546651[17] && + !_theResult____h546651[16] && + !_theResult____h546651[15] && + !_theResult____h546651[14] && + !_theResult____h546651[13] && + !_theResult____h546651[12] && + !_theResult____h546651[11] && + !_theResult____h546651[10] && + !_theResult____h546651[9] && + !_theResult____h546651[8] && + !_theResult____h546651[7] && + !_theResult____h546651[6] && + !_theResult____h546651[5] && + !_theResult____h546651[4] && + !_theResult____h546651[3] && + !_theResult____h546651[2] && + !_theResult____h546651[1] && + !_theResult____h546651[0]) ? + _theResult____h546651 : + _theResult___snd__h554927 ; + assign _theResult___snd__h554927 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h554949 = - _theResult____h546650 << + assign _theResult___snd__h554950 = + _theResult____h546651 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 ; - assign _theResult___snd__h563665 = - (f2_exp__h526062 == 8'd0) ? - _theResult___snd__h563679 : - _theResult___snd__h545262 ; - assign _theResult___snd__h563679 = - (f2_exp__h526062 == 8'd0 && !f2_sfd__h526063[22] && + assign _theResult___snd__h563666 = + (f2_exp__h526063 == 8'd0) ? + _theResult___snd__h563680 : + _theResult___snd__h545263 ; + assign _theResult___snd__h563680 = + (f2_exp__h526063 == 8'd0 && !f2_sfd__h526064[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171) ? - sfd__h526424 : - _theResult___snd__h563685 ; - assign _theResult___snd__h563685 = + sfd__h526425 : + _theResult___snd__h563686 ; + assign _theResult___snd__h563686 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h563703 = - sfd__h526424 << + assign _theResult___snd__h563704 = + sfd__h526425 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10546 ; - assign _theResult___snd__h584564 = - (f3_exp__h565366 == 8'd0) ? - _theResult___snd__h584573 : - _theResult___snd__h584566 ; - assign _theResult___snd__h584566 = { f3_sfd__h565367, 34'd0 } ; - assign _theResult___snd__h584573 = - (f3_exp__h565366 == 8'd0 && !f3_sfd__h565367[22] && + assign _theResult___snd__h584565 = + (f3_exp__h565367 == 8'd0) ? + _theResult___snd__h584574 : + _theResult___snd__h584567 ; + assign _theResult___snd__h584567 = { f3_sfd__h565368, 34'd0 } ; + assign _theResult___snd__h584574 = + (f3_exp__h565367 == 8'd0 && !f3_sfd__h565368[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401) ? - sfd__h565728 : - _theResult___snd__h584579 ; - assign _theResult___snd__h584579 = + sfd__h565729 : + _theResult___snd__h584580 ; + assign _theResult___snd__h584580 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h584602 = - sfd__h565728 << + assign _theResult___snd__h584603 = + sfd__h565729 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 ; - assign _theResult___snd__h594201 = { _theResult____h585954[55:0], 1'd0 } ; - assign _theResult___snd__h594212 = - (!_theResult____h585954[56] && _theResult____h585954[55]) ? - _theResult___snd__h594214 : - _theResult___snd__h594224 ; - assign _theResult___snd__h594214 = { _theResult____h585954[54:0], 2'd0 } ; - assign _theResult___snd__h594224 = - (!_theResult____h585954[56] && !_theResult____h585954[55] && - !_theResult____h585954[54] && - !_theResult____h585954[53] && - !_theResult____h585954[52] && - !_theResult____h585954[51] && - !_theResult____h585954[50] && - !_theResult____h585954[49] && - !_theResult____h585954[48] && - !_theResult____h585954[47] && - !_theResult____h585954[46] && - !_theResult____h585954[45] && - !_theResult____h585954[44] && - !_theResult____h585954[43] && - !_theResult____h585954[42] && - !_theResult____h585954[41] && - !_theResult____h585954[40] && - !_theResult____h585954[39] && - !_theResult____h585954[38] && - !_theResult____h585954[37] && - !_theResult____h585954[36] && - !_theResult____h585954[35] && - !_theResult____h585954[34] && - !_theResult____h585954[33] && - !_theResult____h585954[32] && - !_theResult____h585954[31] && - !_theResult____h585954[30] && - !_theResult____h585954[29] && - !_theResult____h585954[28] && - !_theResult____h585954[27] && - !_theResult____h585954[26] && - !_theResult____h585954[25] && - !_theResult____h585954[24] && - !_theResult____h585954[23] && - !_theResult____h585954[22] && - !_theResult____h585954[21] && - !_theResult____h585954[20] && - !_theResult____h585954[19] && - !_theResult____h585954[18] && - !_theResult____h585954[17] && - !_theResult____h585954[16] && - !_theResult____h585954[15] && - !_theResult____h585954[14] && - !_theResult____h585954[13] && - !_theResult____h585954[12] && - !_theResult____h585954[11] && - !_theResult____h585954[10] && - !_theResult____h585954[9] && - !_theResult____h585954[8] && - !_theResult____h585954[7] && - !_theResult____h585954[6] && - !_theResult____h585954[5] && - !_theResult____h585954[4] && - !_theResult____h585954[3] && - !_theResult____h585954[2] && - !_theResult____h585954[1] && - !_theResult____h585954[0]) ? - _theResult____h585954 : - _theResult___snd__h594230 ; - assign _theResult___snd__h594230 = + assign _theResult___snd__h594202 = { _theResult____h585955[55:0], 1'd0 } ; + assign _theResult___snd__h594213 = + (!_theResult____h585955[56] && _theResult____h585955[55]) ? + _theResult___snd__h594215 : + _theResult___snd__h594225 ; + assign _theResult___snd__h594215 = { _theResult____h585955[54:0], 2'd0 } ; + assign _theResult___snd__h594225 = + (!_theResult____h585955[56] && !_theResult____h585955[55] && + !_theResult____h585955[54] && + !_theResult____h585955[53] && + !_theResult____h585955[52] && + !_theResult____h585955[51] && + !_theResult____h585955[50] && + !_theResult____h585955[49] && + !_theResult____h585955[48] && + !_theResult____h585955[47] && + !_theResult____h585955[46] && + !_theResult____h585955[45] && + !_theResult____h585955[44] && + !_theResult____h585955[43] && + !_theResult____h585955[42] && + !_theResult____h585955[41] && + !_theResult____h585955[40] && + !_theResult____h585955[39] && + !_theResult____h585955[38] && + !_theResult____h585955[37] && + !_theResult____h585955[36] && + !_theResult____h585955[35] && + !_theResult____h585955[34] && + !_theResult____h585955[33] && + !_theResult____h585955[32] && + !_theResult____h585955[31] && + !_theResult____h585955[30] && + !_theResult____h585955[29] && + !_theResult____h585955[28] && + !_theResult____h585955[27] && + !_theResult____h585955[26] && + !_theResult____h585955[25] && + !_theResult____h585955[24] && + !_theResult____h585955[23] && + !_theResult____h585955[22] && + !_theResult____h585955[21] && + !_theResult____h585955[20] && + !_theResult____h585955[19] && + !_theResult____h585955[18] && + !_theResult____h585955[17] && + !_theResult____h585955[16] && + !_theResult____h585955[15] && + !_theResult____h585955[14] && + !_theResult____h585955[13] && + !_theResult____h585955[12] && + !_theResult____h585955[11] && + !_theResult____h585955[10] && + !_theResult____h585955[9] && + !_theResult____h585955[8] && + !_theResult____h585955[7] && + !_theResult____h585955[6] && + !_theResult____h585955[5] && + !_theResult____h585955[4] && + !_theResult____h585955[3] && + !_theResult____h585955[2] && + !_theResult____h585955[1] && + !_theResult____h585955[0]) ? + _theResult____h585955 : + _theResult___snd__h594231 ; + assign _theResult___snd__h594231 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h594253 = - _theResult____h585954 << + assign _theResult___snd__h594254 = + _theResult____h585955 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9725 ; - assign _theResult___snd__h602969 = - (f3_exp__h565366 == 8'd0) ? - _theResult___snd__h602983 : - _theResult___snd__h584566 ; - assign _theResult___snd__h602983 = - (f3_exp__h565366 == 8'd0 && !f3_sfd__h565367[22] && + assign _theResult___snd__h602970 = + (f3_exp__h565367 == 8'd0) ? + _theResult___snd__h602984 : + _theResult___snd__h584567 ; + assign _theResult___snd__h602984 = + (f3_exp__h565367 == 8'd0 && !f3_sfd__h565368[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401) ? - sfd__h565728 : - _theResult___snd__h602989 ; - assign _theResult___snd__h602989 = + sfd__h565729 : + _theResult___snd__h602990 ; + assign _theResult___snd__h602990 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h603007 = - sfd__h565728 << + assign _theResult___snd__h603008 = + sfd__h565729 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9776 ; - assign _theResult___snd__h608463 = - b__h607915[63] ? b___1__h608528 : b__h607915 ; - assign _theResult___snd_fst_exp__h367798 = + assign _theResult___snd__h608464 = + b__h607916[63] ? b___1__h608529 : b__h607916 ; + assign _theResult___snd_fst_exp__h367799 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - _theResult___fst_exp__h359213 : - _theResult___fst_exp__h367795 ; - assign _theResult___snd_fst_exp__h385618 = + _theResult___fst_exp__h359214 : + _theResult___fst_exp__h367796 ; + assign _theResult___snd_fst_exp__h385619 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - _theResult___fst_exp__h376979 : - _theResult___fst_exp__h385615 ; - assign _theResult___snd_fst_exp__h413495 = + _theResult___fst_exp__h376980 : + _theResult___fst_exp__h385616 ; + assign _theResult___snd_fst_exp__h413496 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - _theResult___fst_exp__h404910 : - _theResult___fst_exp__h413492 ; - assign _theResult___snd_fst_exp__h431315 = + _theResult___fst_exp__h404911 : + _theResult___fst_exp__h413493 ; + assign _theResult___snd_fst_exp__h431316 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - _theResult___fst_exp__h422676 : - _theResult___fst_exp__h431312 ; - assign _theResult___snd_fst_exp__h459190 = + _theResult___fst_exp__h422677 : + _theResult___fst_exp__h431313 ; + assign _theResult___snd_fst_exp__h459191 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - _theResult___fst_exp__h450605 : - _theResult___fst_exp__h459187 ; - assign _theResult___snd_fst_exp__h477010 = + _theResult___fst_exp__h450606 : + _theResult___fst_exp__h459188 ; + assign _theResult___snd_fst_exp__h477011 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - _theResult___fst_exp__h468371 : - _theResult___fst_exp__h477007 ; - assign _theResult___snd_fst_exp__h507217 = + _theResult___fst_exp__h468372 : + _theResult___fst_exp__h477008 ; + assign _theResult___snd_fst_exp__h507218 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 ? 11'd0 : - _theResult___fst_exp__h507214 ; - assign _theResult___snd_fst_exp__h525652 = + _theResult___fst_exp__h507215 ; + assign _theResult___snd_fst_exp__h525653 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? - _theResult___fst_exp__h516865 : - _theResult___fst_exp__h525649 ; - assign _theResult___snd_fst_exp__h546070 = + _theResult___fst_exp__h516866 : + _theResult___fst_exp__h525650 ; + assign _theResult___snd_fst_exp__h546071 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 ? 11'd0 : - _theResult___fst_exp__h546067 ; - assign _theResult___snd_fst_exp__h564505 = + _theResult___fst_exp__h546068 ; + assign _theResult___snd_fst_exp__h564506 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? - _theResult___fst_exp__h555718 : - _theResult___fst_exp__h564502 ; - assign _theResult___snd_fst_exp__h585374 = + _theResult___fst_exp__h555719 : + _theResult___fst_exp__h564503 ; + assign _theResult___snd_fst_exp__h585375 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 ? 11'd0 : - _theResult___fst_exp__h585371 ; - assign _theResult___snd_fst_exp__h603809 = + _theResult___fst_exp__h585372 ; + assign _theResult___snd_fst_exp__h603810 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? - _theResult___fst_exp__h595022 : - _theResult___fst_exp__h603806 ; - assign _theResult___snd_fst_sfd__h342850 = + _theResult___fst_exp__h595023 : + _theResult___fst_exp__h603807 ; + assign _theResult___snd_fst_sfd__h342851 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h367799 = + assign _theResult___snd_fst_sfd__h367800 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - _theResult___fst_sfd__h359214 : - _theResult___fst_sfd__h367796 ; - assign _theResult___snd_fst_sfd__h385619 = + _theResult___fst_sfd__h359215 : + _theResult___fst_sfd__h367797 ; + assign _theResult___snd_fst_sfd__h385620 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - _theResult___fst_sfd__h376980 : - _theResult___fst_sfd__h385616 ; - assign _theResult___snd_fst_sfd__h388552 = + _theResult___fst_sfd__h376981 : + _theResult___fst_sfd__h385617 ; + assign _theResult___snd_fst_sfd__h388553 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h413496 = + assign _theResult___snd_fst_sfd__h413497 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - _theResult___fst_sfd__h404911 : - _theResult___fst_sfd__h413493 ; - assign _theResult___snd_fst_sfd__h431316 = + _theResult___fst_sfd__h404912 : + _theResult___fst_sfd__h413494 ; + assign _theResult___snd_fst_sfd__h431317 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - _theResult___fst_sfd__h422677 : - _theResult___fst_sfd__h431313 ; - assign _theResult___snd_fst_sfd__h434247 = + _theResult___fst_sfd__h422678 : + _theResult___fst_sfd__h431314 ; + assign _theResult___snd_fst_sfd__h434248 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h459191 = + assign _theResult___snd_fst_sfd__h459192 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - _theResult___fst_sfd__h450606 : - _theResult___fst_sfd__h459188 ; - assign _theResult___snd_fst_sfd__h477011 = + _theResult___fst_sfd__h450607 : + _theResult___fst_sfd__h459189 ; + assign _theResult___snd_fst_sfd__h477012 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - _theResult___fst_sfd__h468372 : - _theResult___fst_sfd__h477008 ; - assign _theResult___snd_fst_sfd__h487384 = - (f1_sfd__h487069 == 23'd0) ? + _theResult___fst_sfd__h468373 : + _theResult___fst_sfd__h477009 ; + assign _theResult___snd_fst_sfd__h487385 = + (f1_sfd__h487070 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h487132 ; - assign _theResult___snd_fst_sfd__h507218 = + out___1_sfd__h487133 ; + assign _theResult___snd_fst_sfd__h507219 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 ? 52'd0 : - _theResult___fst_sfd__h507215 ; - assign _theResult___snd_fst_sfd__h525653 = + _theResult___fst_sfd__h507216 ; + assign _theResult___snd_fst_sfd__h525654 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? - _theResult___fst_sfd__h516866 : - _theResult___fst_sfd__h525650 ; - assign _theResult___snd_fst_sfd__h526378 = - (f2_sfd__h526063 == 23'd0) ? + _theResult___fst_sfd__h516867 : + _theResult___fst_sfd__h525651 ; + assign _theResult___snd_fst_sfd__h526379 = + (f2_sfd__h526064 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h526126 ; - assign _theResult___snd_fst_sfd__h546071 = + out___1_sfd__h526127 ; + assign _theResult___snd_fst_sfd__h546072 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 ? 52'd0 : - _theResult___fst_sfd__h546068 ; - assign _theResult___snd_fst_sfd__h564506 = + _theResult___fst_sfd__h546069 ; + assign _theResult___snd_fst_sfd__h564507 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? - _theResult___fst_sfd__h555719 : - _theResult___fst_sfd__h564503 ; - assign _theResult___snd_fst_sfd__h565682 = - (f3_sfd__h565367 == 23'd0) ? + _theResult___fst_sfd__h555720 : + _theResult___fst_sfd__h564504 ; + assign _theResult___snd_fst_sfd__h565683 = + (f3_sfd__h565368 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h565430 ; - assign _theResult___snd_fst_sfd__h585375 = + out___1_sfd__h565431 ; + assign _theResult___snd_fst_sfd__h585376 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 ? 52'd0 : - _theResult___fst_sfd__h585372 ; - assign _theResult___snd_fst_sfd__h603810 = + _theResult___fst_sfd__h585373 ; + assign _theResult___snd_fst_sfd__h603811 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? - _theResult___fst_sfd__h595023 : - _theResult___fst_sfd__h603807 ; - assign a___1__h608076 = + _theResult___fst_sfd__h595024 : + _theResult___fst_sfd__h603808 ; + assign a___1__h608077 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12 } ; - assign a___1__h608467 = 64'd0 - a__h607914 ; - assign a__h607914 = + assign a___1__h608468 = 64'd0 - a__h607915 ; + assign a__h607915 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h608076 : + a___1__h608077 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h608077 = + assign b___1__h608078 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h608528 = 64'd0 - b__h607915 ; - assign b__h607915 = + assign b___1__h608529 = 64'd0 - b__h607916 ; + assign b__h607916 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h608077 : + b___1__h608078 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h608062 = { {64{a__h607914[63]}}, a__h607914 } ; - assign b__h608138 = { {64{b__h607915[63]}}, b__h607915 } ; - assign b__h608239 = { 64'd0, a__h607914 } ; - assign b__h608251 = { 64'd0, b__h607915 } ; - assign base__h720368 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h720388 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h717408 = - commitStage_commitTrap[36] ? i__h717583 : i__h717423 ; - assign commitStage_commitTrap_4643_BIT_36_4891_AND_co_ETC___d14956 = + assign b__h608063 = { {64{a__h607915[63]}}, a__h607915 } ; + assign b__h608139 = { {64{b__h607916[63]}}, b__h607916 } ; + assign b__h608240 = { 64'd0, a__h607915 } ; + assign b__h608252 = { 64'd0, b__h607916 } ; + assign base__h721348 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h721368 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h718388 = + commitStage_commitTrap[36] ? i__h718563 : i__h718403 ; + assign commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && commitStage_commitTrap[35:32] != 4'd1 && @@ -29790,8 +29817,15 @@ module mkCore(CLK, !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; - assign commitStage_rg_serial_num_4820_PLUS_IF_rob_deq_ETC___d15758 = - commitStage_rg_serial_num + y__h739350 ; + assign commitStage_f_rob_data_first__5067_BIT_167_516_ETC___d15239 = + { commitStage_f_rob_data$D_OUT[167:166], + commitStage_f_rob_data$D_OUT[166] ? + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, + trap_val__h718389, + IF_commitStage_f_rob_data_first__5067_BITS_97__ETC___d15238 } ; + assign commitStage_rg_serial_num_4635_PLUS_IF_rob_deq_ETC___d15770 = + commitStage_rg_serial_num + y__h740368 ; assign coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29978,9 +30012,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10922 | - ((f3_exp__h565366 != 8'd255 || f3_sfd__h565367 == 23'd0) && - (f3_exp__h565366 != 8'd255 || f3_sfd__h565367 != 23'd0) && - (f3_exp__h565366 != 8'd0 || f3_sfd__h565367 != 23'd0) && + ((f3_exp__h565367 != 8'd255 || f3_sfd__h565368 == 23'd0) && + (f3_exp__h565367 != 8'd255 || f3_sfd__h565368 != 23'd0) && + (f3_exp__h565367 != 8'd0 || f3_sfd__h565368 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10962) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11003 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29988,9 +30022,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10991 | - ((f3_exp__h565366 != 8'd255 || f3_sfd__h565367 == 23'd0) && - (f3_exp__h565366 != 8'd255 || f3_sfd__h565367 != 23'd0) && - (f3_exp__h565366 != 8'd0 || f3_sfd__h565367 != 23'd0) && + ((f3_exp__h565367 != 8'd255 || f3_sfd__h565368 == 23'd0) && + (f3_exp__h565367 != 8'd255 || f3_sfd__h565368 != 23'd0) && + (f3_exp__h565367 != 8'd0 || f3_sfd__h565368 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10998) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11051 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29998,9 +30032,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11035 | - ((f3_exp__h565366 != 8'd255 || f3_sfd__h565367 == 23'd0) && - (f3_exp__h565366 != 8'd255 || f3_sfd__h565367 != 23'd0) && - (f3_exp__h565366 != 8'd0 || f3_sfd__h565367 != 23'd0) && + ((f3_exp__h565367 != 8'd255 || f3_sfd__h565368 == 23'd0) && + (f3_exp__h565367 != 8'd255 || f3_sfd__h565368 != 23'd0) && + (f3_exp__h565367 != 8'd0 || f3_sfd__h565368 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11046) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11093 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -30008,9 +30042,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11079 | - ((f3_exp__h565366 != 8'd255 || f3_sfd__h565367 == 23'd0) && - (f3_exp__h565366 != 8'd255 || f3_sfd__h565367 != 23'd0) && - (f3_exp__h565366 != 8'd0 || f3_sfd__h565367 != 23'd0) && + ((f3_exp__h565367 != 8'd255 || f3_sfd__h565368 == 23'd0) && + (f3_exp__h565367 != 8'd255 || f3_sfd__h565368 != 23'd0) && + (f3_exp__h565367 != 8'd0 || f3_sfd__h565368 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11088) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11135 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -30018,9 +30052,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11121 | - ((f3_exp__h565366 != 8'd255 || f3_sfd__h565367 == 23'd0) && - (f3_exp__h565366 != 8'd255 || f3_sfd__h565367 != 23'd0) && - (f3_exp__h565366 != 8'd0 || f3_sfd__h565367 != 23'd0) && + ((f3_exp__h565367 != 8'd255 || f3_sfd__h565368 == 23'd0) && + (f3_exp__h565367 != 8'd255 || f3_sfd__h565368 != 23'd0) && + (f3_exp__h565367 != 8'd0 || f3_sfd__h565368 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11130) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -30066,7 +30100,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h258549 ; + y__h258550 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3167 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3131 || @@ -30322,15 +30356,15 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_deqReq_rl) && coreFix_memExe_forwardQ_full ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1734 = - { coreFix_memExe_lsq$getOrigBE << x__h186791[2:0], - x__h186791, + { coreFix_memExe_lsq$getOrigBE << x__h186792[2:0], + x__h186792, coreFix_memExe_regToExeQ$first[75:12], coreFix_memExe_lsq$getOrigBE, coreFix_memExe_lsq$getOrigBE[7] ? - x__h186791[2:0] != 3'd0 : + x__h186792[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - x__h186791[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && x__h186791[0]) } ; + x__h186792[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && x__h186792[0]) } ; assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3765 = coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3734 || @@ -30413,12 +30447,12 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14958 = + assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14968 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign csr_addr__h662583 = + assign csr_addr__h662585 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208 : 12'hCFF ; @@ -30434,7 +30468,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13273 || csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 || - csr_addr__h662583 == 12'h8FF) ; + csr_addr__h662585 == 12'h8FF) ; assign csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13747 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -30459,37 +30493,37 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 = - csrf_prv_reg_read__3022_ULE_1___d14997 && + assign csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 = + csrf_prv_reg_read__3022_ULE_1___d15008 && (commitStage_commitTrap[36] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d14999 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15017) ; - assign csrf_prv_reg_read__3022_ULE_1___d14997 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15010 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15028) ; + assign csrf_prv_reg_read__3022_ULE_1___d15008 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 = - csrf_prv_reg < csr_addr__h662583[9:8] ; + csrf_prv_reg < csr_addr__h662585[9:8] ; assign csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13743 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13681 ; - assign data78993_BITS_31_TO_0__q11 = data__h478993[31:0] ; - assign data79887_BITS_31_TO_0__q15 = data__h479887[31:0] ; - assign data___1__h479505 = - { {32{data78993_BITS_31_TO_0__q11[31]}}, - data78993_BITS_31_TO_0__q11 } ; - assign data___1__h480399 = - { {32{data79887_BITS_31_TO_0__q15[31]}}, - data79887_BITS_31_TO_0__q15 } ; - assign data__h478993 = + assign data78994_BITS_31_TO_0__q11 = data__h478994[31:0] ; + assign data79888_BITS_31_TO_0__q14 = data__h479888[31:0] ; + assign data___1__h479506 = + { {32{data78994_BITS_31_TO_0__q11[31]}}, + data78994_BITS_31_TO_0__q11 } ; + assign data___1__h480400 = + { {32{data79888_BITS_31_TO_0__q14[31]}}, + data79888_BITS_31_TO_0__q14 } ; + assign data__h478994 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h479887 = + assign data__h479888 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h479689 : - x_remainder__h479690 ; - assign dcsr_cause__h716927 = + x_quotient__h479690 : + x_remainder__h479691 ; + assign dcsr_cause__h717907 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30506,31 +30540,31 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h385649 = _theResult___fst_exp__h358616 + 8'd1 ; - assign din_inc___2_exp__h385673 = _theResult___fst_exp__h367272 + 8'd1 ; - assign din_inc___2_exp__h385703 = _theResult___fst_exp__h376382 + 8'd1 ; - assign din_inc___2_exp__h385727 = _theResult___fst_exp__h385067 + 8'd1 ; - assign din_inc___2_exp__h431346 = _theResult___fst_exp__h404313 + 8'd1 ; - assign din_inc___2_exp__h431370 = _theResult___fst_exp__h412969 + 8'd1 ; - assign din_inc___2_exp__h431400 = _theResult___fst_exp__h422079 + 8'd1 ; - assign din_inc___2_exp__h431424 = _theResult___fst_exp__h430764 + 8'd1 ; - assign din_inc___2_exp__h477041 = _theResult___fst_exp__h450008 + 8'd1 ; - assign din_inc___2_exp__h477065 = _theResult___fst_exp__h458664 + 8'd1 ; - assign din_inc___2_exp__h477095 = _theResult___fst_exp__h467774 + 8'd1 ; - assign din_inc___2_exp__h477119 = _theResult___fst_exp__h476459 + 8'd1 ; - assign din_inc___2_exp__h525706 = _theResult___fst_exp__h506456 + 11'd1 ; - assign din_inc___2_exp__h525741 = _theResult___fst_exp__h516033 + 11'd1 ; - assign din_inc___2_exp__h525767 = _theResult___fst_exp__h524866 + 11'd1 ; - assign din_inc___2_exp__h564559 = _theResult___fst_exp__h545309 + 11'd1 ; - assign din_inc___2_exp__h564594 = _theResult___fst_exp__h554886 + 11'd1 ; - assign din_inc___2_exp__h564620 = _theResult___fst_exp__h563719 + 11'd1 ; - assign din_inc___2_exp__h603863 = _theResult___fst_exp__h584613 + 11'd1 ; - assign din_inc___2_exp__h603898 = _theResult___fst_exp__h594190 + 11'd1 ; - assign din_inc___2_exp__h603924 = _theResult___fst_exp__h603023 + 11'd1 ; - assign enabled_ints___1__h658899 = pend_ints__h658372 & y__h658911 ; - assign enabled_ints__h658945 = - pend_ints__h658372 & - { r1__read_BITS_13_TO_0___h658921, csrf_mideleg_1_0_reg } ; + assign din_inc___2_exp__h385650 = _theResult___fst_exp__h358617 + 8'd1 ; + assign din_inc___2_exp__h385674 = _theResult___fst_exp__h367273 + 8'd1 ; + assign din_inc___2_exp__h385704 = _theResult___fst_exp__h376383 + 8'd1 ; + assign din_inc___2_exp__h385728 = _theResult___fst_exp__h385068 + 8'd1 ; + assign din_inc___2_exp__h431347 = _theResult___fst_exp__h404314 + 8'd1 ; + assign din_inc___2_exp__h431371 = _theResult___fst_exp__h412970 + 8'd1 ; + assign din_inc___2_exp__h431401 = _theResult___fst_exp__h422080 + 8'd1 ; + assign din_inc___2_exp__h431425 = _theResult___fst_exp__h430765 + 8'd1 ; + assign din_inc___2_exp__h477042 = _theResult___fst_exp__h450009 + 8'd1 ; + assign din_inc___2_exp__h477066 = _theResult___fst_exp__h458665 + 8'd1 ; + assign din_inc___2_exp__h477096 = _theResult___fst_exp__h467775 + 8'd1 ; + assign din_inc___2_exp__h477120 = _theResult___fst_exp__h476460 + 8'd1 ; + assign din_inc___2_exp__h525707 = _theResult___fst_exp__h506457 + 11'd1 ; + assign din_inc___2_exp__h525742 = _theResult___fst_exp__h516034 + 11'd1 ; + assign din_inc___2_exp__h525768 = _theResult___fst_exp__h524867 + 11'd1 ; + assign din_inc___2_exp__h564560 = _theResult___fst_exp__h545310 + 11'd1 ; + assign din_inc___2_exp__h564595 = _theResult___fst_exp__h554887 + 11'd1 ; + assign din_inc___2_exp__h564621 = _theResult___fst_exp__h563720 + 11'd1 ; + assign din_inc___2_exp__h603864 = _theResult___fst_exp__h584614 + 11'd1 ; + assign din_inc___2_exp__h603899 = _theResult___fst_exp__h594191 + 11'd1 ; + assign din_inc___2_exp__h603925 = _theResult___fst_exp__h603024 + 11'd1 ; + assign enabled_ints___1__h658901 = pend_ints__h658374 & y__h658913 ; + assign enabled_ints__h658947 = + pend_ints__h658374 & + { r1__read_BITS_13_TO_0___h658923, csrf_mideleg_1_0_reg } ; assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13979 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || @@ -30552,52 +30586,52 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3653_AND__ETC___d13724 && IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14135) ; - assign f1_exp87068_MINUS_127__q136 = f1_exp__h487068 - 8'd127 ; - assign f1_exp__h487068 = + assign f1_exp87069_MINUS_127__q136 = f1_exp__h487069 - 8'd127 ; + assign f1_exp__h487069 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h487069 = + assign f1_sfd__h487070 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp26062_MINUS_127__q176 = f2_exp__h526062 - 8'd127 ; - assign f2_exp__h526062 = + assign f2_exp26063_MINUS_127__q176 = f2_exp__h526063 - 8'd127 ; + assign f2_exp__h526063 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h526063 = + assign f2_sfd__h526064 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp65366_MINUS_127__q153 = f3_exp__h565366 - 8'd127 ; - assign f3_exp__h565366 = + assign f3_exp65367_MINUS_127__q153 = f3_exp__h565367 - 8'd127 ; + assign f3_exp__h565367 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h565367 = + assign f3_sfd__h565368 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__6101_AND_f_csr_reqs_firs_ETC___d16204 = + assign f_csr_rsps_i_notFull__6114_AND_f_csr_reqs_firs_ETC___d16217 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fallthrough_pc__h673430 = + assign fallthrough_pc__h673432 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h689938 = + assign fallthrough_pc__h689940 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; - assign fcsr_csr__read__h615712 = { 56'd0, x__h619370 } ; + assign fcsr_csr__read__h615714 = { 56'd0, x__h619372 } ; assign fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14323 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || @@ -30678,9 +30712,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13273 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h662584 != 5'd0 || - imm__h662585 != 32'd0) && - csr_addr__h662583[11:10] == 2'b11 ; + rs1__h662586 != 5'd0 || + imm__h662587 != 32'd0) && + csr_addr__h662585[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13990 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -30787,7 +30821,7 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13921 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h736831 = + assign fflags__h737833 = ({ rob$deqPort_0_deq_data[361:356], 1'd0, rob$deqPort_0_deq_data[354:350], @@ -30797,8 +30831,8 @@ module mkCore(CLK, rob$deqPort_0_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h736817 ; - assign fflags__h739527 = + po_fflags__h737818 ; + assign fflags__h740546 = ({ rob$deqPort_1_deq_data[361:356], 1'd0, rob$deqPort_1_deq_data[354:350], @@ -30808,105 +30842,105 @@ module mkCore(CLK, rob$deqPort_1_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h739513 ; - assign fflags__h742192 = - NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_deq_ETC___d15969 ? - y_avValue_fst__h742129 : - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15975 ; - assign fflags_csr__read__h615687 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h615698 = { 61'd0, csrf_frm_reg } ; - assign guard__h350515 = - { IF_sfdin58610_BIT_33_THEN_2_ELSE_0__q30[1], - { sfdin__h358610[32:0], 23'd0 } != 56'd0 } ; - assign guard__h359224 = - { IF_theResult___snd67223_BIT_33_THEN_2_ELSE_0__q32[1], - { _theResult___snd__h367223[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368154 = - { IF_sfdin76376_BIT_33_THEN_2_ELSE_0__q40[1], - { sfdin__h376376[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368752 = x__h368854 != 57'd0 ; - assign guard__h376990 = - { IF_theResult___snd85013_BIT_33_THEN_2_ELSE_0__q45[1], - { _theResult___snd__h385013[32:0], 23'd0 } != 56'd0 } ; - assign guard__h396214 = - { IF_sfdin04307_BIT_33_THEN_2_ELSE_0__q65[1], - { sfdin__h404307[32:0], 23'd0 } != 56'd0 } ; - assign guard__h404921 = - { IF_theResult___snd12920_BIT_33_THEN_2_ELSE_0__q67[1], - { _theResult___snd__h412920[32:0], 23'd0 } != 56'd0 } ; - assign guard__h413851 = - { IF_sfdin22073_BIT_33_THEN_2_ELSE_0__q75[1], - { sfdin__h422073[32:0], 23'd0 } != 56'd0 } ; - assign guard__h414449 = x__h414551 != 57'd0 ; - assign guard__h422687 = - { IF_theResult___snd30710_BIT_33_THEN_2_ELSE_0__q80[1], - { _theResult___snd__h430710[32:0], 23'd0 } != 56'd0 } ; - assign guard__h441909 = - { IF_sfdin50002_BIT_33_THEN_2_ELSE_0__q100[1], - { sfdin__h450002[32:0], 23'd0 } != 56'd0 } ; - assign guard__h450616 = - { IF_theResult___snd58615_BIT_33_THEN_2_ELSE_0__q102[1], - { _theResult___snd__h458615[32:0], 23'd0 } != 56'd0 } ; - assign guard__h459546 = - { IF_sfdin67768_BIT_33_THEN_2_ELSE_0__q110[1], - { sfdin__h467768[32:0], 23'd0 } != 56'd0 } ; - assign guard__h460144 = x__h460246 != 57'd0 ; - assign guard__h468382 = - { IF_theResult___snd76405_BIT_33_THEN_2_ELSE_0__q115[1], - { _theResult___snd__h476405[32:0], 23'd0 } != 56'd0 } ; - assign guard__h498495 = - { IF_theResult___snd06407_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h506407[3:0], 52'd0 } != 56'd0 } ; - assign guard__h507807 = - { IF_sfdin16027_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h516027[3:0], 52'd0 } != 56'd0 } ; - assign guard__h508405 = x__h508505 != 57'd0 ; - assign guard__h516876 = - { IF_theResult___snd24812_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h524812[3:0], 52'd0 } != 56'd0 } ; - assign guard__h537348 = - { IF_theResult___snd45260_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h545260[3:0], 52'd0 } != 56'd0 } ; - assign guard__h546660 = - { IF_sfdin54880_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h554880[3:0], 52'd0 } != 56'd0 } ; - assign guard__h547258 = x__h547358 != 57'd0 ; - assign guard__h555729 = - { IF_theResult___snd63665_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h563665[3:0], 52'd0 } != 56'd0 } ; - assign guard__h576652 = - { IF_theResult___snd84564_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h584564[3:0], 52'd0 } != 56'd0 } ; - assign guard__h585964 = - { IF_sfdin94184_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h594184[3:0], 52'd0 } != 56'd0 } ; - assign guard__h586562 = x__h586662 != 57'd0 ; - assign guard__h595033 = - { IF_theResult___snd02969_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h602969[3:0], 52'd0 } != 56'd0 } ; - assign idx__h693566 = + po_fflags__h740531 ; + assign fflags__h743227 = + NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_deq_ETC___d15982 ? + y_avValue_fst__h743164 : + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d15988 ; + assign fflags_csr__read__h615689 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h615700 = { 61'd0, csrf_frm_reg } ; + assign guard__h350516 = + { IF_sfdin58611_BIT_33_THEN_2_ELSE_0__q30[1], + { sfdin__h358611[32:0], 23'd0 } != 56'd0 } ; + assign guard__h359225 = + { IF_theResult___snd67224_BIT_33_THEN_2_ELSE_0__q32[1], + { _theResult___snd__h367224[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368155 = + { IF_sfdin76377_BIT_33_THEN_2_ELSE_0__q40[1], + { sfdin__h376377[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368753 = x__h368855 != 57'd0 ; + assign guard__h376991 = + { IF_theResult___snd85014_BIT_33_THEN_2_ELSE_0__q45[1], + { _theResult___snd__h385014[32:0], 23'd0 } != 56'd0 } ; + assign guard__h396215 = + { IF_sfdin04308_BIT_33_THEN_2_ELSE_0__q65[1], + { sfdin__h404308[32:0], 23'd0 } != 56'd0 } ; + assign guard__h404922 = + { IF_theResult___snd12921_BIT_33_THEN_2_ELSE_0__q67[1], + { _theResult___snd__h412921[32:0], 23'd0 } != 56'd0 } ; + assign guard__h413852 = + { IF_sfdin22074_BIT_33_THEN_2_ELSE_0__q75[1], + { sfdin__h422074[32:0], 23'd0 } != 56'd0 } ; + assign guard__h414450 = x__h414552 != 57'd0 ; + assign guard__h422688 = + { IF_theResult___snd30711_BIT_33_THEN_2_ELSE_0__q80[1], + { _theResult___snd__h430711[32:0], 23'd0 } != 56'd0 } ; + assign guard__h441910 = + { IF_sfdin50003_BIT_33_THEN_2_ELSE_0__q100[1], + { sfdin__h450003[32:0], 23'd0 } != 56'd0 } ; + assign guard__h450617 = + { IF_theResult___snd58616_BIT_33_THEN_2_ELSE_0__q102[1], + { _theResult___snd__h458616[32:0], 23'd0 } != 56'd0 } ; + assign guard__h459547 = + { IF_sfdin67769_BIT_33_THEN_2_ELSE_0__q110[1], + { sfdin__h467769[32:0], 23'd0 } != 56'd0 } ; + assign guard__h460145 = x__h460247 != 57'd0 ; + assign guard__h468383 = + { IF_theResult___snd76406_BIT_33_THEN_2_ELSE_0__q115[1], + { _theResult___snd__h476406[32:0], 23'd0 } != 56'd0 } ; + assign guard__h498496 = + { IF_theResult___snd06408_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h506408[3:0], 52'd0 } != 56'd0 } ; + assign guard__h507808 = + { IF_sfdin16028_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h516028[3:0], 52'd0 } != 56'd0 } ; + assign guard__h508406 = x__h508506 != 57'd0 ; + assign guard__h516877 = + { IF_theResult___snd24813_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h524813[3:0], 52'd0 } != 56'd0 } ; + assign guard__h537349 = + { IF_theResult___snd45261_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h545261[3:0], 52'd0 } != 56'd0 } ; + assign guard__h546661 = + { IF_sfdin54881_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h554881[3:0], 52'd0 } != 56'd0 } ; + assign guard__h547259 = x__h547359 != 57'd0 ; + assign guard__h555730 = + { IF_theResult___snd63666_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h563666[3:0], 52'd0 } != 56'd0 } ; + assign guard__h576653 = + { IF_theResult___snd84565_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h584565[3:0], 52'd0 } != 56'd0 } ; + assign guard__h585965 = + { IF_sfdin94185_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h594185[3:0], 52'd0 } != 56'd0 } ; + assign guard__h586563 = x__h586663 != 57'd0 ; + assign guard__h595034 = + { IF_theResult___snd02970_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h602970[3:0], 52'd0 } != 56'd0 } ; + assign idx__h693568 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13991 || !coreFix_aluExe_0_rsAlu$canEnq || NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14015 ; - assign imm__h662585 = + assign imm__h662587 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h677209 = + assign k__h677211 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3688__ETC___d13690 ; - assign mcause_csr__read__h617354 = - { r1__read__h620833, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h617099 = - { r1__read__h620820, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h616706 = - { r1__read__h620681, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h616801 = - { r1__read__h620698, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h616925 = { r1__read__h620722, 1'b0 } ; - assign mip_csr__read__h617587 = { r1__read__h620839, 1'b0 } ; + assign mcause_csr__read__h617356 = + { r1__read__h620835, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h617101 = + { r1__read__h620822, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h616708 = + { r1__read__h620683, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h616803 = + { r1__read__h620700, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h616927 = { r1__read__h620724, 1'b0 } ; + assign mip_csr__read__h617589 = { r1__read__h620841, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30990,41 +31024,41 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h76121 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h616558 = { r1__read__h620556, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h617007 = - { r1__read__h620815, csrf_mtvec_mode_low_reg } ; - assign n___1__h201994 = + assign msip__h76122 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h616560 = { r1__read__h620558, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h617009 = + { r1__read__h620817, csrf_mtvec_mode_low_reg } ; + assign n___1__h201995 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h200591[63:56], + x__h200592[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h200591[55:48], + x__h200592[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h200591[47:40], + x__h200592[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h200591[39:32], + x__h200592[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h200591[31:24], + x__h200592[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h200591[23:16], + x__h200592[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h200591[15:8], + x__h200592[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h200591[7:0] } ; - assign n__read__h617691 = + x__h200592[7:0] } ; + assign n__read__h617693 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h617882 = + assign n__read__h617884 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -31035,257 +31069,257 @@ module mkCore(CLK, upd__h6873 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h735179 = + assign n__read__h736179 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h301220 = + assign next_deqP___1__h301221 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h309216 = + assign next_deqP___1__h309217 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h315497 = + assign next_deqP___1__h315498 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h323351 = + assign next_deqP___1__h323352 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h333408 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h336633 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h730647 = + assign next_deqP___1__h333409 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h336634 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h731630 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : - rob_deqPort_0_deq_data__4635_BITS_425_TO_362_4_ETC___d15485 ; - assign old_fflags__h741619 = + rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496 ; + assign old_fflags__h742653 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; - assign out___1_sfd__h487132 = { f1_sfd__h487069, 29'd0 } ; - assign out___1_sfd__h526126 = { f2_sfd__h526063, 29'd0 } ; - assign out___1_sfd__h565430 = { f3_sfd__h565367, 29'd0 } ; - assign out_exp__h359135 = - sfdin__h358610[34] ? - _theResult___exp__h359132 : - _theResult___fst_exp__h358616 ; - assign out_exp__h367717 = - _theResult___snd__h367223[34] ? - _theResult___exp__h367714 : - _theResult___fst_exp__h367272 ; - assign out_exp__h376901 = - sfdin__h376376[34] ? - _theResult___exp__h376898 : - _theResult___fst_exp__h376382 ; - assign out_exp__h385537 = - _theResult___snd__h385013[34] ? - _theResult___exp__h385534 : - _theResult___fst_exp__h385067 ; - assign out_exp__h404832 = - sfdin__h404307[34] ? - _theResult___exp__h404829 : - _theResult___fst_exp__h404313 ; - assign out_exp__h413414 = - _theResult___snd__h412920[34] ? - _theResult___exp__h413411 : - _theResult___fst_exp__h412969 ; - assign out_exp__h422598 = - sfdin__h422073[34] ? - _theResult___exp__h422595 : - _theResult___fst_exp__h422079 ; - assign out_exp__h431234 = - _theResult___snd__h430710[34] ? - _theResult___exp__h431231 : - _theResult___fst_exp__h430764 ; - assign out_exp__h450527 = - sfdin__h450002[34] ? - _theResult___exp__h450524 : - _theResult___fst_exp__h450008 ; - assign out_exp__h459109 = - _theResult___snd__h458615[34] ? - _theResult___exp__h459106 : - _theResult___fst_exp__h458664 ; - assign out_exp__h468293 = - sfdin__h467768[34] ? - _theResult___exp__h468290 : - _theResult___fst_exp__h467774 ; - assign out_exp__h476929 = - _theResult___snd__h476405[34] ? - _theResult___exp__h476926 : - _theResult___fst_exp__h476459 ; - assign out_exp__h507114 = - _theResult___snd__h506407[5] ? - _theResult___exp__h507111 : - _theResult___fst_exp__h506456 ; - assign out_exp__h516765 = - sfdin__h516027[5] ? - _theResult___exp__h516762 : - _theResult___fst_exp__h516033 ; - assign out_exp__h525549 = - _theResult___snd__h524812[5] ? - _theResult___exp__h525546 : - _theResult___fst_exp__h524866 ; - assign out_exp__h545967 = - _theResult___snd__h545260[5] ? - _theResult___exp__h545964 : - _theResult___fst_exp__h545309 ; - assign out_exp__h555618 = - sfdin__h554880[5] ? - _theResult___exp__h555615 : - _theResult___fst_exp__h554886 ; - assign out_exp__h564402 = - _theResult___snd__h563665[5] ? - _theResult___exp__h564399 : - _theResult___fst_exp__h563719 ; - assign out_exp__h585271 = - _theResult___snd__h584564[5] ? - _theResult___exp__h585268 : - _theResult___fst_exp__h584613 ; - assign out_exp__h594922 = - sfdin__h594184[5] ? - _theResult___exp__h594919 : - _theResult___fst_exp__h594190 ; - assign out_exp__h603706 = - _theResult___snd__h602969[5] ? - _theResult___exp__h603703 : - _theResult___fst_exp__h603023 ; - assign out_f_exp__h385913 = - (_theResult___exp__h385636 == 8'd255 && - _theResult___sfd__h385637 != 23'd0 || + assign out___1_sfd__h487133 = { f1_sfd__h487070, 29'd0 } ; + assign out___1_sfd__h526127 = { f2_sfd__h526064, 29'd0 } ; + assign out___1_sfd__h565431 = { f3_sfd__h565368, 29'd0 } ; + assign out_exp__h359136 = + sfdin__h358611[34] ? + _theResult___exp__h359133 : + _theResult___fst_exp__h358617 ; + assign out_exp__h367718 = + _theResult___snd__h367224[34] ? + _theResult___exp__h367715 : + _theResult___fst_exp__h367273 ; + assign out_exp__h376902 = + sfdin__h376377[34] ? + _theResult___exp__h376899 : + _theResult___fst_exp__h376383 ; + assign out_exp__h385538 = + _theResult___snd__h385014[34] ? + _theResult___exp__h385535 : + _theResult___fst_exp__h385068 ; + assign out_exp__h404833 = + sfdin__h404308[34] ? + _theResult___exp__h404830 : + _theResult___fst_exp__h404314 ; + assign out_exp__h413415 = + _theResult___snd__h412921[34] ? + _theResult___exp__h413412 : + _theResult___fst_exp__h412970 ; + assign out_exp__h422599 = + sfdin__h422074[34] ? + _theResult___exp__h422596 : + _theResult___fst_exp__h422080 ; + assign out_exp__h431235 = + _theResult___snd__h430711[34] ? + _theResult___exp__h431232 : + _theResult___fst_exp__h430765 ; + assign out_exp__h450528 = + sfdin__h450003[34] ? + _theResult___exp__h450525 : + _theResult___fst_exp__h450009 ; + assign out_exp__h459110 = + _theResult___snd__h458616[34] ? + _theResult___exp__h459107 : + _theResult___fst_exp__h458665 ; + assign out_exp__h468294 = + sfdin__h467769[34] ? + _theResult___exp__h468291 : + _theResult___fst_exp__h467775 ; + assign out_exp__h476930 = + _theResult___snd__h476406[34] ? + _theResult___exp__h476927 : + _theResult___fst_exp__h476460 ; + assign out_exp__h507115 = + _theResult___snd__h506408[5] ? + _theResult___exp__h507112 : + _theResult___fst_exp__h506457 ; + assign out_exp__h516766 = + sfdin__h516028[5] ? + _theResult___exp__h516763 : + _theResult___fst_exp__h516034 ; + assign out_exp__h525550 = + _theResult___snd__h524813[5] ? + _theResult___exp__h525547 : + _theResult___fst_exp__h524867 ; + assign out_exp__h545968 = + _theResult___snd__h545261[5] ? + _theResult___exp__h545965 : + _theResult___fst_exp__h545310 ; + assign out_exp__h555619 = + sfdin__h554881[5] ? + _theResult___exp__h555616 : + _theResult___fst_exp__h554887 ; + assign out_exp__h564403 = + _theResult___snd__h563666[5] ? + _theResult___exp__h564400 : + _theResult___fst_exp__h563720 ; + assign out_exp__h585272 = + _theResult___snd__h584565[5] ? + _theResult___exp__h585269 : + _theResult___fst_exp__h584614 ; + assign out_exp__h594923 = + sfdin__h594185[5] ? + _theResult___exp__h594920 : + _theResult___fst_exp__h594191 ; + assign out_exp__h603707 = + _theResult___snd__h602970[5] ? + _theResult___exp__h603704 : + _theResult___fst_exp__h603024 ; + assign out_f_exp__h385914 = + (_theResult___exp__h385637 == 8'd255 && + _theResult___sfd__h385638 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385627 ; - assign out_f_exp__h431610 = - (_theResult___exp__h431333 == 8'd255 && - _theResult___sfd__h431334 != 23'd0 || + _theResult___fst_exp__h385628 ; + assign out_f_exp__h431611 = + (_theResult___exp__h431334 == 8'd255 && + _theResult___sfd__h431335 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431324 ; - assign out_f_exp__h477305 = - (_theResult___exp__h477028 == 8'd255 && - _theResult___sfd__h477029 != 23'd0 || + _theResult___fst_exp__h431325 ; + assign out_f_exp__h477306 = + (_theResult___exp__h477029 == 8'd255 && + _theResult___sfd__h477030 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477019 ; - assign out_f_sfd__h385914 = - (_theResult___exp__h385636 == 8'd255 && - _theResult___sfd__h385637 != 23'd0) ? + _theResult___fst_exp__h477020 ; + assign out_f_sfd__h385915 = + (_theResult___exp__h385637 == 8'd255 && + _theResult___sfd__h385638 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h385637 ; - assign out_f_sfd__h431611 = - (_theResult___exp__h431333 == 8'd255 && - _theResult___sfd__h431334 != 23'd0) ? + _theResult___sfd__h385638 ; + assign out_f_sfd__h431612 = + (_theResult___exp__h431334 == 8'd255 && + _theResult___sfd__h431335 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h431334 ; - assign out_f_sfd__h477306 = - (_theResult___exp__h477028 == 8'd255 && - _theResult___sfd__h477029 != 23'd0) ? + _theResult___sfd__h431335 ; + assign out_f_sfd__h477307 = + (_theResult___exp__h477029 == 8'd255 && + _theResult___sfd__h477030 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h477029 ; - assign out_sfd__h359136 = - sfdin__h358610[34] ? - _theResult___sfd__h359133 : - sfdin__h358610[56:34] ; - assign out_sfd__h367718 = - _theResult___snd__h367223[34] ? - _theResult___sfd__h367715 : - _theResult___snd__h367223[56:34] ; - assign out_sfd__h376902 = - sfdin__h376376[34] ? - _theResult___sfd__h376899 : - sfdin__h376376[56:34] ; - assign out_sfd__h385538 = - _theResult___snd__h385013[34] ? - _theResult___sfd__h385535 : - _theResult___snd__h385013[56:34] ; - assign out_sfd__h404833 = - sfdin__h404307[34] ? - _theResult___sfd__h404830 : - sfdin__h404307[56:34] ; - assign out_sfd__h413415 = - _theResult___snd__h412920[34] ? - _theResult___sfd__h413412 : - _theResult___snd__h412920[56:34] ; - assign out_sfd__h422599 = - sfdin__h422073[34] ? - _theResult___sfd__h422596 : - sfdin__h422073[56:34] ; - assign out_sfd__h431235 = - _theResult___snd__h430710[34] ? - _theResult___sfd__h431232 : - _theResult___snd__h430710[56:34] ; - assign out_sfd__h450528 = - sfdin__h450002[34] ? - _theResult___sfd__h450525 : - sfdin__h450002[56:34] ; - assign out_sfd__h459110 = - _theResult___snd__h458615[34] ? - _theResult___sfd__h459107 : - _theResult___snd__h458615[56:34] ; - assign out_sfd__h468294 = - sfdin__h467768[34] ? - _theResult___sfd__h468291 : - sfdin__h467768[56:34] ; - assign out_sfd__h476930 = - _theResult___snd__h476405[34] ? - _theResult___sfd__h476927 : - _theResult___snd__h476405[56:34] ; - assign out_sfd__h507115 = - _theResult___snd__h506407[5] ? - _theResult___sfd__h507112 : - _theResult___snd__h506407[56:5] ; - assign out_sfd__h516766 = - sfdin__h516027[5] ? - _theResult___sfd__h516763 : - sfdin__h516027[56:5] ; - assign out_sfd__h525550 = - _theResult___snd__h524812[5] ? - _theResult___sfd__h525547 : - _theResult___snd__h524812[56:5] ; - assign out_sfd__h545968 = - _theResult___snd__h545260[5] ? - _theResult___sfd__h545965 : - _theResult___snd__h545260[56:5] ; - assign out_sfd__h555619 = - sfdin__h554880[5] ? - _theResult___sfd__h555616 : - sfdin__h554880[56:5] ; - assign out_sfd__h564403 = - _theResult___snd__h563665[5] ? - _theResult___sfd__h564400 : - _theResult___snd__h563665[56:5] ; - assign out_sfd__h585272 = - _theResult___snd__h584564[5] ? - _theResult___sfd__h585269 : - _theResult___snd__h584564[56:5] ; - assign out_sfd__h594923 = - sfdin__h594184[5] ? - _theResult___sfd__h594920 : - sfdin__h594184[56:5] ; - assign out_sfd__h603707 = - _theResult___snd__h602969[5] ? - _theResult___sfd__h603704 : - _theResult___snd__h602969[56:5] ; - assign pc__h720352 = - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 ? - y_avValue_new_pc__h720144 : - y_avValue_new_pc__h720330 ; - assign pend_ints__h658372 = + _theResult___sfd__h477030 ; + assign out_sfd__h359137 = + sfdin__h358611[34] ? + _theResult___sfd__h359134 : + sfdin__h358611[56:34] ; + assign out_sfd__h367719 = + _theResult___snd__h367224[34] ? + _theResult___sfd__h367716 : + _theResult___snd__h367224[56:34] ; + assign out_sfd__h376903 = + sfdin__h376377[34] ? + _theResult___sfd__h376900 : + sfdin__h376377[56:34] ; + assign out_sfd__h385539 = + _theResult___snd__h385014[34] ? + _theResult___sfd__h385536 : + _theResult___snd__h385014[56:34] ; + assign out_sfd__h404834 = + sfdin__h404308[34] ? + _theResult___sfd__h404831 : + sfdin__h404308[56:34] ; + assign out_sfd__h413416 = + _theResult___snd__h412921[34] ? + _theResult___sfd__h413413 : + _theResult___snd__h412921[56:34] ; + assign out_sfd__h422600 = + sfdin__h422074[34] ? + _theResult___sfd__h422597 : + sfdin__h422074[56:34] ; + assign out_sfd__h431236 = + _theResult___snd__h430711[34] ? + _theResult___sfd__h431233 : + _theResult___snd__h430711[56:34] ; + assign out_sfd__h450529 = + sfdin__h450003[34] ? + _theResult___sfd__h450526 : + sfdin__h450003[56:34] ; + assign out_sfd__h459111 = + _theResult___snd__h458616[34] ? + _theResult___sfd__h459108 : + _theResult___snd__h458616[56:34] ; + assign out_sfd__h468295 = + sfdin__h467769[34] ? + _theResult___sfd__h468292 : + sfdin__h467769[56:34] ; + assign out_sfd__h476931 = + _theResult___snd__h476406[34] ? + _theResult___sfd__h476928 : + _theResult___snd__h476406[56:34] ; + assign out_sfd__h507116 = + _theResult___snd__h506408[5] ? + _theResult___sfd__h507113 : + _theResult___snd__h506408[56:5] ; + assign out_sfd__h516767 = + sfdin__h516028[5] ? + _theResult___sfd__h516764 : + sfdin__h516028[56:5] ; + assign out_sfd__h525551 = + _theResult___snd__h524813[5] ? + _theResult___sfd__h525548 : + _theResult___snd__h524813[56:5] ; + assign out_sfd__h545969 = + _theResult___snd__h545261[5] ? + _theResult___sfd__h545966 : + _theResult___snd__h545261[56:5] ; + assign out_sfd__h555620 = + sfdin__h554881[5] ? + _theResult___sfd__h555617 : + sfdin__h554881[56:5] ; + assign out_sfd__h564404 = + _theResult___snd__h563666[5] ? + _theResult___sfd__h564401 : + _theResult___snd__h563666[56:5] ; + assign out_sfd__h585273 = + _theResult___snd__h584565[5] ? + _theResult___sfd__h585270 : + _theResult___snd__h584565[56:5] ; + assign out_sfd__h594924 = + sfdin__h594185[5] ? + _theResult___sfd__h594921 : + sfdin__h594185[56:5] ; + assign out_sfd__h603708 = + _theResult___snd__h602970[5] ? + _theResult___sfd__h603705 : + _theResult___snd__h602970[56:5] ; + assign pc__h721332 = + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 ? + y_avValue_new_pc__h721124 : + y_avValue_new_pc__h721310 ; + assign pend_ints__h658374 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1864_ETC___d13033, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h736817 = old_fflags__h741619 ; - assign po_fflags__h739513 = - old_fflags__h741619 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h743861 = csrf_prv_reg ; - assign prv__h743905 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h480474 = + assign po_fflags__h737818 = old_fflags__h742653 ; + assign po_fflags__h740531 = + old_fflags__h742653 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h744896 = csrf_prv_reg ; + assign prv__h744940 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h480475 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_0___h658921 = + assign r1__read_BITS_13_TO_0___h658923 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -31293,119 +31327,127 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h662453 = csrf_fs_reg ; - assign r1__read_BITS_62_TO_14___h738479 = { r1__read__h620580, 2'd0 } ; - assign r1__read_BIT_20___h663149 = csrf_tw_reg ; - assign r1__read__h619385 = { r1__read__h619387, csrf_ie_vec_1 } ; - assign r1__read__h619387 = { r1__read__h619389, 2'b0 } ; - assign r1__read__h619389 = { r1__read__h619391, csrf_prev_ie_vec_0 } ; - assign r1__read__h619391 = { r1__read__h619393, csrf_prev_ie_vec_1 } ; - assign r1__read__h619393 = { r1__read__h619395, 2'b0 } ; - assign r1__read__h619395 = { r1__read__h619397, csrf_spp_reg } ; - assign r1__read__h619397 = { r1__read__h619399, 4'b0 } ; - assign r1__read__h619399 = { r1__read__h619401, csrf_fs_reg } ; - assign r1__read__h619401 = { r1__read__h619403, 2'd0 } ; - assign r1__read__h619403 = { r1__read__h619405, 1'b0 } ; - assign r1__read__h619405 = { r1__read__h619407, csrf_sum_reg } ; - assign r1__read__h619407 = { r1__read__h619409, csrf_mxr_reg } ; - assign r1__read__h619409 = { r1__read__h619411, 12'b0 } ; - assign r1__read__h619411 = { r1__read__h619413, 2'b10 } ; - assign r1__read__h619413 = { csrf_fs_reg == 2'b11, 29'b0 } ; - assign r1__read__h619789 = - { r1__read__h619791, csrf_software_int_en_vec_1 } ; - assign r1__read__h619791 = { r1__read__h619793, 2'b0 } ; - assign r1__read__h619793 = { r1__read__h619795, 1'b0 } ; - assign r1__read__h619795 = { r1__read__h619797, csrf_timer_int_en_vec_1 } ; - assign r1__read__h619797 = { r1__read__h619799, 2'b0 } ; - assign r1__read__h619799 = { r1__read__h619801, 1'b0 } ; - assign r1__read__h619801 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h620299 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620304 = { r1__read__h620306, csrf_scounteren_tm_reg } ; - assign r1__read__h620306 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h620317 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h620323 = - { r1__read__h620325, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620325 = { r1__read__h620327, 2'b0 } ; - assign r1__read__h620327 = { r1__read__h620329, 1'b0 } ; - assign r1__read__h620329 = - { r1__read__h620331, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620331 = { r1__read__h620333, 2'b0 } ; - assign r1__read__h620333 = { r1__read__h620335, 1'b0 } ; - assign r1__read__h620335 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620533 = { vm_mode_reg__read__h620539, 16'd0 } ; - assign r1__read__h620556 = { r1__read__h620558, csrf_ie_vec_1 } ; - assign r1__read__h620558 = { r1__read__h620560, 1'b0 } ; - assign r1__read__h620560 = { r1__read__h620562, csrf_ie_vec_3 } ; - assign r1__read__h620562 = { r1__read__h620564, csrf_prev_ie_vec_0 } ; - assign r1__read__h620564 = { r1__read__h620566, csrf_prev_ie_vec_1 } ; - assign r1__read__h620566 = { r1__read__h620568, 1'b0 } ; - assign r1__read__h620568 = { r1__read__h620570, csrf_prev_ie_vec_3 } ; - assign r1__read__h620570 = { r1__read__h620572, csrf_spp_reg } ; - assign r1__read__h620572 = { r1__read__h620574, 2'b0 } ; - assign r1__read__h620574 = { r1__read__h620576, csrf_mpp_reg } ; - assign r1__read__h620576 = - { r1__read_BITS_62_TO_14___h738479, csrf_fs_reg } ; - assign r1__read__h620580 = { r1__read__h620582, csrf_mprv_reg } ; - assign r1__read__h620582 = { r1__read__h620584, csrf_sum_reg } ; - assign r1__read__h620584 = { r1__read__h620586, csrf_mxr_reg } ; - assign r1__read__h620586 = { r1__read__h620588, csrf_tvm_reg } ; - assign r1__read__h620588 = { r1__read__h620590, csrf_tw_reg } ; - assign r1__read__h620590 = { r1__read__h620592, csrf_tsr_reg } ; - assign r1__read__h620592 = { r1__read__h620594, 9'b0 } ; - assign r1__read__h620594 = { r1__read__h620596, 2'b10 } ; + assign r1__read_BITS_13_TO_12___h662455 = csrf_fs_reg ; + assign r1__read_BITS_62_TO_14___h739496 = { r1__read__h620582, 2'd0 } ; + assign r1__read_BIT_20___h663151 = csrf_tw_reg ; + assign r1__read__h619387 = { r1__read__h619389, csrf_ie_vec_1 } ; + assign r1__read__h619389 = { r1__read__h619391, 2'b0 } ; + assign r1__read__h619391 = { r1__read__h619393, csrf_prev_ie_vec_0 } ; + assign r1__read__h619393 = { r1__read__h619395, csrf_prev_ie_vec_1 } ; + assign r1__read__h619395 = { r1__read__h619397, 2'b0 } ; + assign r1__read__h619397 = { r1__read__h619399, csrf_spp_reg } ; + assign r1__read__h619399 = { r1__read__h619401, 4'b0 } ; + assign r1__read__h619401 = { r1__read__h619403, csrf_fs_reg } ; + assign r1__read__h619403 = { r1__read__h619405, 2'd0 } ; + assign r1__read__h619405 = { r1__read__h619407, 1'b0 } ; + assign r1__read__h619407 = { r1__read__h619409, csrf_sum_reg } ; + assign r1__read__h619409 = { r1__read__h619411, csrf_mxr_reg } ; + assign r1__read__h619411 = { r1__read__h619413, 12'b0 } ; + assign r1__read__h619413 = { r1__read__h619415, 2'b10 } ; + assign r1__read__h619415 = { csrf_fs_reg == 2'b11, 29'b0 } ; + assign r1__read__h619791 = + { r1__read__h619793, csrf_software_int_en_vec_1 } ; + assign r1__read__h619793 = { r1__read__h619795, 2'b0 } ; + assign r1__read__h619795 = { r1__read__h619797, 1'b0 } ; + assign r1__read__h619797 = { r1__read__h619799, csrf_timer_int_en_vec_1 } ; + assign r1__read__h619799 = { r1__read__h619801, 2'b0 } ; + assign r1__read__h619801 = { r1__read__h619803, 1'b0 } ; + assign r1__read__h619803 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h620301 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620306 = { r1__read__h620308, csrf_scounteren_tm_reg } ; + assign r1__read__h620308 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h620319 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h620325 = + { r1__read__h620327, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620327 = { r1__read__h620329, 2'b0 } ; + assign r1__read__h620329 = { r1__read__h620331, 1'b0 } ; + assign r1__read__h620331 = + { r1__read__h620333, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620333 = { r1__read__h620335, 2'b0 } ; + assign r1__read__h620335 = { r1__read__h620337, 1'b0 } ; + assign r1__read__h620337 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620535 = { vm_mode_reg__read__h620541, 16'd0 } ; + assign r1__read__h620558 = { r1__read__h620560, csrf_ie_vec_1 } ; + assign r1__read__h620560 = { r1__read__h620562, 1'b0 } ; + assign r1__read__h620562 = { r1__read__h620564, csrf_ie_vec_3 } ; + assign r1__read__h620564 = { r1__read__h620566, csrf_prev_ie_vec_0 } ; + assign r1__read__h620566 = { r1__read__h620568, csrf_prev_ie_vec_1 } ; + assign r1__read__h620568 = { r1__read__h620570, 1'b0 } ; + assign r1__read__h620570 = { r1__read__h620572, csrf_prev_ie_vec_3 } ; + assign r1__read__h620572 = { r1__read__h620574, csrf_spp_reg } ; + assign r1__read__h620574 = { r1__read__h620576, 2'b0 } ; + assign r1__read__h620576 = { r1__read__h620578, csrf_mpp_reg } ; + assign r1__read__h620578 = + { r1__read_BITS_62_TO_14___h739496, csrf_fs_reg } ; + assign r1__read__h620582 = { r1__read__h620584, csrf_mprv_reg } ; + assign r1__read__h620584 = { r1__read__h620586, csrf_sum_reg } ; + assign r1__read__h620586 = { r1__read__h620588, csrf_mxr_reg } ; + assign r1__read__h620588 = { r1__read__h620590, csrf_tvm_reg } ; + assign r1__read__h620590 = { r1__read__h620592, csrf_tw_reg } ; + assign r1__read__h620592 = { r1__read__h620594, csrf_tsr_reg } ; + assign r1__read__h620594 = { r1__read__h620596, 9'b0 } ; assign r1__read__h620596 = { r1__read__h620598, 2'b10 } ; - assign r1__read__h620598 = { csrf_fs_reg == 2'b11, 27'b0 } ; - assign r1__read__h620681 = { r1__read__h620683, 1'b0 } ; - assign r1__read__h620683 = { r1__read__h620685, csrf_medeleg_13_11_reg } ; - assign r1__read__h620685 = { r1__read__h620687, 1'b0 } ; - assign r1__read__h620687 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h620698 = { r1__read__h620700, 1'b0 } ; - assign r1__read__h620700 = { r1__read__h620702, csrf_mideleg_5_3_reg } ; - assign r1__read__h620702 = { r1__read__h620704, 1'b0 } ; - assign r1__read__h620704 = { r1__read__h620706, csrf_mideleg_9_7_reg } ; - assign r1__read__h620706 = { r1__read__h620708, 1'b0 } ; - assign r1__read__h620708 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h620722 = - { r1__read__h620724, csrf_software_int_en_vec_1 } ; - assign r1__read__h620724 = { r1__read__h620726, 1'b0 } ; - assign r1__read__h620726 = - { r1__read__h620728, csrf_software_int_en_vec_3 } ; - assign r1__read__h620728 = { r1__read__h620730, 1'b0 } ; - assign r1__read__h620730 = { r1__read__h620732, csrf_timer_int_en_vec_1 } ; - assign r1__read__h620732 = { r1__read__h620734, 1'b0 } ; - assign r1__read__h620734 = { r1__read__h620736, csrf_timer_int_en_vec_3 } ; - assign r1__read__h620736 = { r1__read__h620738, 1'b0 } ; - assign r1__read__h620738 = - { r1__read__h620740, csrf_external_int_en_vec_1 } ; - assign r1__read__h620740 = { r1__read__h620742, 1'b0 } ; - assign r1__read__h620742 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h620815 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620820 = { r1__read__h620822, csrf_mcounteren_tm_reg } ; - assign r1__read__h620822 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h620833 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h620839 = - { r1__read__h620841, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620841 = { r1__read__h620843, 1'b0 } ; - assign r1__read__h620843 = - { r1__read__h620845, csrf_software_int_pend_vec_3 } ; - assign r1__read__h620845 = { r1__read__h620847, 1'b0 } ; - assign r1__read__h620847 = - { r1__read__h620849, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620849 = { r1__read__h620851, 1'b0 } ; - assign r1__read__h620851 = - { r1__read__h620853, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h620853 = { r1__read__h620855, 1'b0 } ; - assign r1__read__h620855 = - { r1__read__h620857, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620857 = { r1__read__h620859, 1'b0 } ; - assign r1__read__h620859 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h620936 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h486684 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h486685 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h480501 = + assign r1__read__h620598 = { r1__read__h620600, 2'b10 } ; + assign r1__read__h620600 = { csrf_fs_reg == 2'b11, 27'b0 } ; + assign r1__read__h620683 = { r1__read__h620685, 1'b0 } ; + assign r1__read__h620685 = { r1__read__h620687, csrf_medeleg_13_11_reg } ; + assign r1__read__h620687 = { r1__read__h620689, 1'b0 } ; + assign r1__read__h620689 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h620700 = { r1__read__h620702, 1'b0 } ; + assign r1__read__h620702 = { r1__read__h620704, csrf_mideleg_5_3_reg } ; + assign r1__read__h620704 = { r1__read__h620706, 1'b0 } ; + assign r1__read__h620706 = { r1__read__h620708, csrf_mideleg_9_7_reg } ; + assign r1__read__h620708 = { r1__read__h620710, 1'b0 } ; + assign r1__read__h620710 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h620724 = + { r1__read__h620726, csrf_software_int_en_vec_1 } ; + assign r1__read__h620726 = { r1__read__h620728, 1'b0 } ; + assign r1__read__h620728 = + { r1__read__h620730, csrf_software_int_en_vec_3 } ; + assign r1__read__h620730 = { r1__read__h620732, 1'b0 } ; + assign r1__read__h620732 = { r1__read__h620734, csrf_timer_int_en_vec_1 } ; + assign r1__read__h620734 = { r1__read__h620736, 1'b0 } ; + assign r1__read__h620736 = { r1__read__h620738, csrf_timer_int_en_vec_3 } ; + assign r1__read__h620738 = { r1__read__h620740, 1'b0 } ; + assign r1__read__h620740 = + { r1__read__h620742, csrf_external_int_en_vec_1 } ; + assign r1__read__h620742 = { r1__read__h620744, 1'b0 } ; + assign r1__read__h620744 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h620817 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620822 = { r1__read__h620824, csrf_mcounteren_tm_reg } ; + assign r1__read__h620824 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h620835 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h620841 = + { r1__read__h620843, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620843 = { r1__read__h620845, 1'b0 } ; + assign r1__read__h620845 = + { r1__read__h620847, csrf_software_int_pend_vec_3 } ; + assign r1__read__h620847 = { r1__read__h620849, 1'b0 } ; + assign r1__read__h620849 = + { r1__read__h620851, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620851 = { r1__read__h620853, 1'b0 } ; + assign r1__read__h620853 = + { r1__read__h620855, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h620855 = { r1__read__h620857, 1'b0 } ; + assign r1__read__h620857 = + { r1__read__h620859, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620859 = { r1__read__h620861, 1'b0 } ; + assign r1__read__h620861 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h620938 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h486685 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h486686 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h480502 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign regRenamingTable_RDY_rename_0_getRename__3536__ETC___d14186 = + assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 = + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14186 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || @@ -31646,12 +31688,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[68] || checkForException___d13243[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h693435 = + assign renaming_spec_bits__h693437 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h689830 : + y_avValue_fst__h689832 : specTagManager$currentSpecBits ; - assign res_data__h342289 = { 32'hFFFFFFFF, x__h342304 } ; - assign res_data__h342294 = + assign res_data__h342290 = { 32'hFFFFFFFF, x__h342305 } ; + assign res_data__h342295 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -31664,8 +31706,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h387991 = { 32'hFFFFFFFF, x__h388006 } ; - assign res_data__h387996 = + assign res_data__h387992 = { 32'hFFFFFFFF, x__h388007 } ; + assign res_data__h387997 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -31678,8 +31720,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h433686 = { 32'hFFFFFFFF, x__h433701 } ; - assign res_data__h433691 = + assign res_data__h433687 = { 32'hFFFFFFFF, x__h433702 } ; + assign res_data__h433692 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -31692,7 +31734,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h342290 = + assign res_fflags__h342291 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -31760,7 +31802,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5355 } ; - assign res_fflags__h387992 = + assign res_fflags__h387993 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -31828,7 +31870,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6747 } ; - assign res_fflags__h433687 = + assign res_fflags__h433688 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31896,245 +31938,256 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8139 } ; - assign resp_addr__h296397 = + assign resp_addr__h296398 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h368757 = + assign result__h368758 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658[0] | - guard__h368752 } ; - assign result__h414454 = + guard__h368753 } ; + assign result__h414455 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050[0] | - guard__h414449 } ; - assign result__h460149 = + guard__h414450 } ; + assign result__h460150 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442[0] | - guard__h460144 } ; - assign result__h508410 = + guard__h460145 } ; + assign result__h508411 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8768[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8768[0] | - guard__h508405 } ; - assign result__h547263 = + guard__h508406 } ; + assign result__h547264 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10253[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10253[0] | - guard__h547258 } ; - assign result__h586567 = + guard__h547259 } ; + assign result__h586568 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9483[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9483[0] | - guard__h586562 } ; - assign result__h653951 = w__h653946 & y__h653980 ; - assign result__h654002 = ~x__h654001 ; - assign rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16040 = + guard__h586563 } ; + assign result__h653953 = w__h653948 & y__h653982 ; + assign result__h654004 = ~x__h654003 ; + assign rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16053 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h618542 = - { r1__read__h620936, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq_data__4632_AND_rob_RDY_d_ETC___d15300 = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + assign rg_tdata1__read__h618544 = + { r1__read__h620938, csrf_rg_tdata1_data } ; + assign rob_RDY_deqPort_0_deq__4643_AND_rob_RDY_deqPor_ETC___d15310 = + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4635_BITS_329_TO_3_ETC___d15295 ; - assign rob_RDY_enqPort_0_enq__3014_AND_regRenamingTab_ETC___d13544 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign rob_deqPort_0_deq_data__4635_BITS_425_TO_362_4_ETC___d15485 = + NOT_rob_deqPort_0_deq_data__4646_BITS_329_TO_3_ETC___d15305 ; + assign rob_deqPort_0_deq_data__4646_BITS_161_TO_98_46_ETC___d15606 = + { rob$deqPort_0_deq_data[161:98], + (rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[97:96] == 2'd0) ? + { 2'd0, rob$deqPort_0_deq_data[95:32] } : + ((rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[97:96] == 2'd1) ? + { 2'd1, rob$deqPort_0_deq_data[95:32] } : + { 2'd2, + (rob$deqPort_0_deq_data[329:325] == 5'd13) ? + data_warl_xformed__h731607 : + rob$deqPort_0_deq_data[95:32] }), + 5'h0A, + rob$deqPort_0_deq_data[26], + 64'hAAAAAAAAAAAAAAAA, + x_prv__h732255, + 64'hAAAAAAAAAAAAAAAA, + x__h735673, + 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496 = rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign rob_deqPort_0_deq_data__4635_BIT_166_4651_CONC_ETC___d14700 = + assign rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 } ; - assign rob_deqPort_0_deq_data__4635_BIT_181_4710_CONC_ETC___d14801 = + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; + assign rob_deqPort_0_deq_data__4646_BIT_181_4721_CONC_ETC___d14812 = { rob$deqPort_0_deq_data[181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q254 } ; + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h662584 = + assign rs1__h662586 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h616415 = { r1__read__h620533, csrf_ppn_reg } ; - assign sbIdx__h158707 = + assign satp_csr__read__h616417 = { r1__read__h620535, csrf_ppn_reg } ; + assign sbIdx__h158708 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h616212 = - { r1__read__h620317, csrf_scause_code_reg } ; - assign scounteren_csr__read__h616074 = - { r1__read__h620304, csrf_scounteren_cy_reg } ; - assign sfd__h342900 = { value__h351127, 3'd0 } ; - assign sfd__h358708 = + assign scause_csr__read__h616214 = + { r1__read__h620319, csrf_scause_code_reg } ; + assign scounteren_csr__read__h616076 = + { r1__read__h620306, csrf_scounteren_cy_reg } ; + assign sfd__h342901 = { value__h351128, 3'd0 } ; + assign sfd__h358709 = { 1'b0, - _theResult___fst_exp__h358616 != 8'd0, - sfdin__h358610[56:34] } + + _theResult___fst_exp__h358617 != 8'd0, + sfdin__h358611[56:34] } + 25'd1 ; - assign sfd__h367290 = + assign sfd__h367291 = { 1'b0, - _theResult___fst_exp__h367272 != 8'd0, - _theResult___snd__h367223[56:34] } + + _theResult___fst_exp__h367273 != 8'd0, + _theResult___snd__h367224[56:34] } + 25'd1 ; - assign sfd__h376474 = + assign sfd__h376475 = { 1'b0, - _theResult___fst_exp__h376382 != 8'd0, - sfdin__h376376[56:34] } + + _theResult___fst_exp__h376383 != 8'd0, + sfdin__h376377[56:34] } + 25'd1 ; - assign sfd__h385086 = + assign sfd__h385087 = { 1'b0, - _theResult___fst_exp__h385067 != 8'd0, - _theResult___snd__h385013[56:34] } + + _theResult___fst_exp__h385068 != 8'd0, + _theResult___snd__h385014[56:34] } + 25'd1 ; - assign sfd__h388602 = { value__h396824, 3'd0 } ; - assign sfd__h404405 = + assign sfd__h388603 = { value__h396825, 3'd0 } ; + assign sfd__h404406 = { 1'b0, - _theResult___fst_exp__h404313 != 8'd0, - sfdin__h404307[56:34] } + + _theResult___fst_exp__h404314 != 8'd0, + sfdin__h404308[56:34] } + 25'd1 ; - assign sfd__h412987 = + assign sfd__h412988 = { 1'b0, - _theResult___fst_exp__h412969 != 8'd0, - _theResult___snd__h412920[56:34] } + + _theResult___fst_exp__h412970 != 8'd0, + _theResult___snd__h412921[56:34] } + 25'd1 ; - assign sfd__h422171 = + assign sfd__h422172 = { 1'b0, - _theResult___fst_exp__h422079 != 8'd0, - sfdin__h422073[56:34] } + + _theResult___fst_exp__h422080 != 8'd0, + sfdin__h422074[56:34] } + 25'd1 ; - assign sfd__h430783 = + assign sfd__h430784 = { 1'b0, - _theResult___fst_exp__h430764 != 8'd0, - _theResult___snd__h430710[56:34] } + + _theResult___fst_exp__h430765 != 8'd0, + _theResult___snd__h430711[56:34] } + 25'd1 ; - assign sfd__h434297 = { value__h442519, 3'd0 } ; - assign sfd__h450100 = + assign sfd__h434298 = { value__h442520, 3'd0 } ; + assign sfd__h450101 = { 1'b0, - _theResult___fst_exp__h450008 != 8'd0, - sfdin__h450002[56:34] } + + _theResult___fst_exp__h450009 != 8'd0, + sfdin__h450003[56:34] } + 25'd1 ; - assign sfd__h458682 = + assign sfd__h458683 = { 1'b0, - _theResult___fst_exp__h458664 != 8'd0, - _theResult___snd__h458615[56:34] } + + _theResult___fst_exp__h458665 != 8'd0, + _theResult___snd__h458616[56:34] } + 25'd1 ; - assign sfd__h467866 = + assign sfd__h467867 = { 1'b0, - _theResult___fst_exp__h467774 != 8'd0, - sfdin__h467768[56:34] } + + _theResult___fst_exp__h467775 != 8'd0, + sfdin__h467769[56:34] } + 25'd1 ; - assign sfd__h476478 = + assign sfd__h476479 = { 1'b0, - _theResult___fst_exp__h476459 != 8'd0, - _theResult___snd__h476405[56:34] } + + _theResult___fst_exp__h476460 != 8'd0, + _theResult___snd__h476406[56:34] } + 25'd1 ; - assign sfd__h487430 = { value__h492013, 32'd0 } ; - assign sfd__h506474 = + assign sfd__h487431 = { value__h492014, 32'd0 } ; + assign sfd__h506475 = { 1'b0, - _theResult___fst_exp__h506456 != 11'd0, - _theResult___snd__h506407[56:5] } + + _theResult___fst_exp__h506457 != 11'd0, + _theResult___snd__h506408[56:5] } + 54'd1 ; - assign sfd__h516125 = + assign sfd__h516126 = { 1'b0, - _theResult___fst_exp__h516033 != 11'd0, - sfdin__h516027[56:5] } + + _theResult___fst_exp__h516034 != 11'd0, + sfdin__h516028[56:5] } + 54'd1 ; - assign sfd__h524885 = + assign sfd__h524886 = { 1'b0, - _theResult___fst_exp__h524866 != 11'd0, - _theResult___snd__h524812[56:5] } + + _theResult___fst_exp__h524867 != 11'd0, + _theResult___snd__h524813[56:5] } + 54'd1 ; - assign sfd__h526424 = { value__h530866, 32'd0 } ; - assign sfd__h545327 = + assign sfd__h526425 = { value__h530867, 32'd0 } ; + assign sfd__h545328 = { 1'b0, - _theResult___fst_exp__h545309 != 11'd0, - _theResult___snd__h545260[56:5] } + + _theResult___fst_exp__h545310 != 11'd0, + _theResult___snd__h545261[56:5] } + 54'd1 ; - assign sfd__h554978 = + assign sfd__h554979 = { 1'b0, - _theResult___fst_exp__h554886 != 11'd0, - sfdin__h554880[56:5] } + + _theResult___fst_exp__h554887 != 11'd0, + sfdin__h554881[56:5] } + 54'd1 ; - assign sfd__h563738 = + assign sfd__h563739 = { 1'b0, - _theResult___fst_exp__h563719 != 11'd0, - _theResult___snd__h563665[56:5] } + + _theResult___fst_exp__h563720 != 11'd0, + _theResult___snd__h563666[56:5] } + 54'd1 ; - assign sfd__h565728 = { value__h570170, 32'd0 } ; - assign sfd__h584631 = + assign sfd__h565729 = { value__h570171, 32'd0 } ; + assign sfd__h584632 = { 1'b0, - _theResult___fst_exp__h584613 != 11'd0, - _theResult___snd__h584564[56:5] } + + _theResult___fst_exp__h584614 != 11'd0, + _theResult___snd__h584565[56:5] } + 54'd1 ; - assign sfd__h594282 = + assign sfd__h594283 = { 1'b0, - _theResult___fst_exp__h594190 != 11'd0, - sfdin__h594184[56:5] } + + _theResult___fst_exp__h594191 != 11'd0, + sfdin__h594185[56:5] } + 54'd1 ; - assign sfd__h603042 = + assign sfd__h603043 = { 1'b0, - _theResult___fst_exp__h603023 != 11'd0, - _theResult___snd__h602969[56:5] } + + _theResult___fst_exp__h603024 != 11'd0, + _theResult___snd__h602970[56:5] } + 54'd1 ; - assign sfdin__h358610 = - _theResult____h350505[56] ? - _theResult___snd__h358627 : - _theResult___snd__h358638 ; - assign sfdin__h376376 = - _theResult____h368144[56] ? - _theResult___snd__h376393 : - _theResult___snd__h376404 ; - assign sfdin__h404307 = - _theResult____h396204[56] ? - _theResult___snd__h404324 : - _theResult___snd__h404335 ; - assign sfdin__h422073 = - _theResult____h413841[56] ? - _theResult___snd__h422090 : - _theResult___snd__h422101 ; - assign sfdin__h450002 = - _theResult____h441899[56] ? - _theResult___snd__h450019 : - _theResult___snd__h450030 ; - assign sfdin__h467768 = - _theResult____h459536[56] ? - _theResult___snd__h467785 : - _theResult___snd__h467796 ; - assign sfdin__h516027 = - _theResult____h507797[56] ? - _theResult___snd__h516044 : - _theResult___snd__h516055 ; - assign sfdin__h554880 = - _theResult____h546650[56] ? - _theResult___snd__h554897 : - _theResult___snd__h554908 ; - assign sfdin__h594184 = - _theResult____h585954[56] ? - _theResult___snd__h594201 : - _theResult___snd__h594212 ; - assign shiftData__h184459 = - coreFix_memExe_regToExeQ$first[75:12] << x__h184588 ; - assign sie_csr__read__h615978 = { r1__read__h619789, 1'b0 } ; - assign sip_csr__read__h616352 = { r1__read__h620323, 1'b0 } ; - assign spec_bits__h696594 = specTagManager$currentSpecBits | y__h696607 ; - assign sstatus_csr__read__h615908 = { r1__read__h619385, csrf_ie_vec_0 } ; - assign stvec_csr__read__h616021 = - { r1__read__h620299, csrf_stvec_mode_low_reg } ; - assign trap_val__h717409 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h718447 ; - assign tsr_val__h734794 = csrf_tsr_reg ; - assign tvm_val__h734796 = csrf_tvm_reg ; + assign sfdin__h358611 = + _theResult____h350506[56] ? + _theResult___snd__h358628 : + _theResult___snd__h358639 ; + assign sfdin__h376377 = + _theResult____h368145[56] ? + _theResult___snd__h376394 : + _theResult___snd__h376405 ; + assign sfdin__h404308 = + _theResult____h396205[56] ? + _theResult___snd__h404325 : + _theResult___snd__h404336 ; + assign sfdin__h422074 = + _theResult____h413842[56] ? + _theResult___snd__h422091 : + _theResult___snd__h422102 ; + assign sfdin__h450003 = + _theResult____h441900[56] ? + _theResult___snd__h450020 : + _theResult___snd__h450031 ; + assign sfdin__h467769 = + _theResult____h459537[56] ? + _theResult___snd__h467786 : + _theResult___snd__h467797 ; + assign sfdin__h516028 = + _theResult____h507798[56] ? + _theResult___snd__h516045 : + _theResult___snd__h516056 ; + assign sfdin__h554881 = + _theResult____h546651[56] ? + _theResult___snd__h554898 : + _theResult___snd__h554909 ; + assign sfdin__h594185 = + _theResult____h585955[56] ? + _theResult___snd__h594202 : + _theResult___snd__h594213 ; + assign shiftData__h184460 = + coreFix_memExe_regToExeQ$first[75:12] << x__h184589 ; + assign sie_csr__read__h615980 = { r1__read__h619791, 1'b0 } ; + assign sip_csr__read__h616354 = { r1__read__h620325, 1'b0 } ; + assign spec_bits__h696596 = specTagManager$currentSpecBits | y__h696609 ; + assign sstatus_csr__read__h615910 = { r1__read__h619387, csrf_ie_vec_0 } ; + assign stvec_csr__read__h616023 = + { r1__read__h620301, csrf_stvec_mode_low_reg } ; + assign trap_val__h718389 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h719427 ; + assign tsr_val__h735793 = csrf_tsr_reg ; + assign tvm_val__h735795 = csrf_tvm_reg ; assign upd__h3993 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : @@ -32144,265 +32197,265 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h735290 = + assign upd__h736290 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h300361 = + assign v__h300362 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3131) ? - v__h300592 : + v__h300593 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h300592 = + assign v__h300593 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h303706 = + assign v__h303707 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3238) ? - v__h304224 : + v__h304225 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h304224 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h314220 = + assign v__h304225 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h314221 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3409) ? - v__h314451 : + v__h314452 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h314451 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h318096 = + assign v__h314452 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h318097 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3505) ? - v__h318327 : + v__h318328 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h318327 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h332697 = + assign v__h318328 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h332698 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3734) ? - v__h332928 : + v__h332929 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h332928 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h335922 = + assign v__h332929 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h335923 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3828) ? - v__h336153 : + v__h336154 : coreFix_memExe_forwardQ_enqP ; - assign v__h336153 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h609133 = + assign v__h336154 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h609134 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h609143 : + v__h609144 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h609143 = + assign v__h609144 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h610174 = v__h609133 - 2'd1 ; - assign v__h614195 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615329 ; - assign v__h639576 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640557 ; - assign value__h351127 = + assign v__h610175 = v__h609134 - 2'd1 ; + assign v__h614197 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615331 ; + assign v__h639578 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640559 ; + assign value__h351128 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h396824 = + assign value__h396825 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h442519 = + assign value__h442520 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h492013 = { 1'b0, f1_exp__h487068 != 8'd0, f1_sfd__h487069 } ; - assign value__h530866 = { 1'b0, f2_exp__h526062 != 8'd0, f2_sfd__h526063 } ; - assign value__h570170 = { 1'b0, f3_exp__h565366 != 8'd0, f3_sfd__h565367 } ; - assign vm_mode_reg__read__h620539 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h653946 = + assign value__h492014 = { 1'b0, f1_exp__h487069 != 8'd0, f1_sfd__h487070 } ; + assign value__h530867 = { 1'b0, f2_exp__h526063 != 8'd0, f2_sfd__h526064 } ; + assign value__h570171 = { 1'b0, f3_exp__h565367 != 8'd0, f3_sfd__h565368 } ; + assign vm_mode_reg__read__h620541 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h653948 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h654002 : + result__h654004 : 12'd4095 ; - assign x__h155281 = + assign x__h155282 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h155287 = + assign x__h155288 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h158828 = { 3'd0, sbIdx__h158707 } ; - assign x__h158834 = + assign x__h158829 = { 3'd0, sbIdx__h158708 } ; + assign x__h158835 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h161644 = + assign x__h161645 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h161648 = + assign x__h161649 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h163496 = + assign x__h163497 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h18384 = + assign x__h18385 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h184366 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183532 ; assign x__h184367 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184213 ; - assign x__h184588 = { x__h186791[2:0], 3'b0 } ; - assign x__h186791 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183533 ; + assign x__h184368 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184214 ; + assign x__h184589 = { x__h186792[2:0], 3'b0 } ; + assign x__h186792 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ; - assign x__h196615 = + assign x__h196616 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h195852[63:32] : - curData__h195852[31:0] ; - assign x__h20922 = + curData__h195853[63:32] : + curData__h195853[31:0] ; + assign x__h20923 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h291632 = + assign x__h291633 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h291644 = + assign x__h291645 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h293498 = + assign x__h293499 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h306571 = + assign x__h306572 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h342304 = - { (_theResult___exp__h385636 != 8'd255 || - _theResult___sfd__h385637 == 23'd0) && + assign x__h342305 = + { (_theResult___exp__h385637 != 8'd255 || + _theResult___sfd__h385638 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5240, - out_f_exp__h385913, - out_f_sfd__h385914 } ; - assign x__h368854 = - sfd__h342900 << (x__h368887[11] ? 12'hAAA : x__h368887) ; - assign x__h368887 = + out_f_exp__h385914, + out_f_sfd__h385915 } ; + assign x__h368855 = + sfd__h342901 << (x__h368888[11] ? 12'hAAA : x__h368888) ; + assign x__h368888 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654 ; - assign x__h388006 = - { (_theResult___exp__h431333 != 8'd255 || - _theResult___sfd__h431334 == 23'd0) && + assign x__h388007 = + { (_theResult___exp__h431334 != 8'd255 || + _theResult___sfd__h431335 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6632, - out_f_exp__h431610, - out_f_sfd__h431611 } ; - assign x__h414551 = - sfd__h388602 << (x__h414584[11] ? 12'hAAA : x__h414584) ; - assign x__h414584 = + out_f_exp__h431611, + out_f_sfd__h431612 } ; + assign x__h414552 = + sfd__h388603 << (x__h414585[11] ? 12'hAAA : x__h414585) ; + assign x__h414585 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046 ; - assign x__h433701 = - { (_theResult___exp__h477028 != 8'd255 || - _theResult___sfd__h477029 == 23'd0) && + assign x__h433702 = + { (_theResult___exp__h477029 != 8'd255 || + _theResult___sfd__h477030 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8024, - out_f_exp__h477305, - out_f_sfd__h477306 } ; - assign x__h460246 = - sfd__h434297 << (x__h460279[11] ? 12'hAAA : x__h460279) ; - assign x__h460279 = + out_f_exp__h477306, + out_f_sfd__h477307 } ; + assign x__h460247 = + sfd__h434298 << (x__h460280[11] ? 12'hAAA : x__h460280) ; + assign x__h460280 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438 ; - assign x__h46291 = + assign x__h46292 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h486590 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h483729 ; assign x__h486591 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484412 ; + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h483730 ; assign x__h486592 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485089 ; - assign x__h48827 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484413 ; + assign x__h486593 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485090 ; + assign x__h48828 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h508505 = sfd__h487430 << x__h508538 ; - assign x__h508538 = + assign x__h508506 = sfd__h487431 << x__h508539 ; + assign x__h508539 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8764 ; - assign x__h547358 = sfd__h526424 << x__h547391 ; - assign x__h547391 = + assign x__h547359 = sfd__h526425 << x__h547392 ; + assign x__h547392 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10249 ; - assign x__h586662 = sfd__h565728 << x__h586695 ; - assign x__h586695 = + assign x__h586663 = sfd__h565729 << x__h586696 ; + assign x__h586696 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9479 ; - assign x__h608451 = + assign x__h608452 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h608462 : - a__h607914 ; - assign x__h608477 = a__h607914[63] ^ b__h607915[63] ; - assign x__h609063 = + _theResult___fst__h608463 : + a__h607915 ; + assign x__h608478 = a__h607915[63] ^ b__h607916[63] ; + assign x__h609064 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11260, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11261 } ; - assign x__h619370 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h623641 = + assign x__h619372 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h623643 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h615386 : - v__h614195 ; - assign x__h623642 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621619 ; - assign x__h646648 = + rVal1__h615388 : + v__h614197 ; + assign x__h623644 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621621 ; + assign x__h646650 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h640612 : - v__h639576 ; - assign x__h646649 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644636 ; - assign x__h653950 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h654001 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h710207 = + rVal1__h640614 : + v__h639578 ; + assign x__h646651 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644638 ; + assign x__h653952 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h654003 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h711187 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h720383 = { cause_code__h717408, 2'b0 } ; - assign x__h722594 = + assign x__h721363 = { cause_code__h718388, 2'b0 } ; + assign x__h723590 = { csrf_fs_reg == 2'b11, - IF_csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_c_ETC___d15221 } ; - assign x__h722786 = - { commitStage_commitTrap[36], 59'b0, cause_code__h717408 } ; - assign x__h730822 = { 1'b0, csrf_spp_reg } ; - assign x__h734674 = + IF_csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_c_ETC___d15232 } ; + assign x__h723782 = + { commitStage_commitTrap[36], 59'b0, cause_code__h718388 } ; + assign x__h731805 = { 1'b0, csrf_spp_reg } ; + assign x__h735673 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32413,9 +32466,9 @@ module mkCore(CLK, csrf_mprv_reg, 2'd0, csrf_fs_reg, - IF_rob_deqPort_0_deq_data__4635_BITS_329_TO_32_ETC___d15585 } ; - assign x__h738459 = - { r1__read_BITS_62_TO_14___h738479, + IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15596 } ; + assign x__h739476 = + { r1__read_BITS_62_TO_14___h739496, 2'b11, csrf_mpp_reg, 2'b0, @@ -32428,56 +32481,56 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h741647 = - { y_avValue_snd_snd_snd_snd_snd_snd_snd__h741629[63:15], + assign x__h742681 = + { y_avValue_snd_snd_snd_snd_snd_snd_snd__h742663[63:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h741629[12:0] } ; - assign x__h742456 = - NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_deq_ETC___d15969 ? - y_avValue_snd_snd_snd_fst__h742266 : - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15994 ; - assign x__h76236 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h318494 = + y_avValue_snd_snd_snd_snd_snd_snd_snd__h742663[12:0] } ; + assign x__h743491 = + NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_deq_ETC___d15982 ? + y_avValue_snd_snd_snd_fst__h743301 : + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d16007 ; + assign x__h76237 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h318495 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h66085 = + assign x_data__h66086 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h684503 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h701169 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h662268 = csrf_frm_reg ; - assign x_prv__h720451 = - csrf_prv_reg_read__3022_ULE_1_4997_AND_IF_comm_ETC___d15019 ? + assign x_data_imm__h684505 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h701171 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h662270 = csrf_frm_reg ; + assign x_prv__h721432 = + csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 ? 2'd1 : 2'd3 ; - assign x_prv__h731271 = + assign x_prv__h732255 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h730822 : + x__h731805 : csrf_mpp_reg ; - assign x_quotient__h479689 = + assign x_quotient__h479690 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h480474 : + q___1__h480475 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h615817 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h479690 = + assign x_reg_ifc__read__h615819 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h479691 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h480501 : + r___1__h480502 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h258549 = + assign y__h258550 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h626399 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; - assign y__h649113 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; - assign y__h653980 = ~x__h653950 ; - assign y__h658911 = + assign y__h626401 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; + assign y__h649115 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; + assign y__h653982 = ~x__h653952 ; + assign y__h658913 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -32486,66 +32539,66 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h696607 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h739350 = + assign y__h696609 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h740368 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h739373 : + y_avValue_snd_snd_snd_snd_snd_fst__h740391 : 64'd0 ; - assign y__h742215 = - NOT_rob_deqPort_0_canDeq__5623_5624_OR_rob_deq_ETC___d15969 ? - y_avValue_snd_snd_snd_snd_snd_fst__h742276 : - y__h739350 ; - assign y_avValue__h183532 = + assign y__h743250 = + NOT_rob_deqPort_0_canDeq__5634_5635_OR_rob_deq_ETC___d15982 ? + y_avValue_snd_snd_snd_snd_snd_fst__h743311 : + y__h740368 ; + assign y_avValue__h183533 = NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1680 ; - assign y_avValue__h184213 = + assign y_avValue__h184214 = NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1641 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1688 ; - assign y_avValue__h483729 = + assign y_avValue__h483730 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8331 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8458 ; - assign y_avValue__h484412 = + assign y_avValue__h484413 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8360 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8466 ; - assign y_avValue__h485089 = + assign y_avValue__h485090 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8386 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8474 ; - assign y_avValue__h615329 = + assign y_avValue__h615331 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1522_1_ETC___d11549 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__152_ETC___d11971 ; - assign y_avValue__h621619 = + assign y_avValue__h621621 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1522_1_ETC___d11579 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__152_ETC___d11980 ; - assign y_avValue__h640557 = + assign y_avValue__h640559 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12437 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__241_ETC___d12673 ; - assign y_avValue__h644636 = + assign y_avValue__h644638 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12467 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__241_ETC___d12682 ; - assign y_avValue_fst__h689767 = + assign y_avValue_fst__h689769 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h696594 : + spec_bits__h696596 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h689796 = + assign y_avValue_fst__h689798 = IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13734 ? - y_avValue_fst__h689767 : + y_avValue_fst__h689769 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h689830 = + assign y_avValue_fst__h689832 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3653_AND__ETC___d13675) ? - y_avValue_fst__h689796 : + y_avValue_fst__h689798 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h738888 = + assign y_avValue_fst__h739906 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32559,10 +32612,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h742097 = - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15975 | + assign y_avValue_fst__h743132 = + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d15988 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h742129 = + assign y_avValue_fst__h743164 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32574,17 +32627,17 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15975 : - y_avValue_fst__h742097 ; - assign y_avValue_new_pc__h720144 = + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d15988 : + y_avValue_fst__h743132 ; + assign y_avValue_new_pc__h721124 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h720368 + { 58'd0, x__h720383 } : - base__h720368 ; - assign y_avValue_new_pc__h720330 = + base__h721348 + { 58'd0, x__h721363 } : + base__h721348 ; + assign y_avValue_new_pc__h721310 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h720388 + { 58'd0, x__h720383 } : - base__h720388 ; - assign y_avValue_snd_snd_snd_fst__h739363 = + base__h721368 + { 58'd0, x__h721363 } : + base__h721368 ; + assign y_avValue_snd_snd_snd_fst__h740381 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32598,7 +32651,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h742266 = + assign y_avValue_snd_snd_snd_fst__h743301 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32610,12 +32663,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15994 : - y_avValue_snd_snd_snd_fst__h742302 ; - assign y_avValue_snd_snd_snd_fst__h742302 = - IF_rob_deqPort_0_canDeq__5623_THEN_IF_NOT_rob__ETC___d15994 + + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d16007 : + y_avValue_snd_snd_snd_fst__h743337 ; + assign y_avValue_snd_snd_snd_fst__h743337 = + IF_rob_deqPort_0_canDeq__5634_THEN_IF_NOT_rob__ETC___d16007 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h739373 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h740391 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32629,7 +32682,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h742276 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h743311 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32641,10 +32694,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h739350 : - y_avValue_snd_snd_snd_snd_snd_fst__h742312 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h742312 = y__h739350 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h741629 = x__h738459 ; + y__h740368 : + y_avValue_snd_snd_snd_snd_snd_fst__h743347 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h743347 = y__h740368 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h742663 = x__h739476 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32845,28 +32898,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h200591 = + x__h200592 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -32882,28 +32935,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h290199 = + x__h290200 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -32913,10 +32966,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h294420 = + addr__h294421 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h294420 = + addr__h294421 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -32925,37 +32978,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h195852 = + curData__h195853 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h718447 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h718447 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h718447 = + 4'd0, 4'd3: trap_val__h719427 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h719427 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h719427 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -32969,425 +33022,425 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h295969 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h295970 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h295969 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h295970 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h615687 or - frm_csr__read__h615698 or - fcsr_csr__read__h615712 or - sstatus_csr__read__h615908 or - sie_csr__read__h615978 or - stvec_csr__read__h616021 or - scounteren_csr__read__h616074 or + fflags_csr__read__h615689 or + frm_csr__read__h615700 or + fcsr_csr__read__h615714 or + sstatus_csr__read__h615910 or + sie_csr__read__h615980 or + stvec_csr__read__h616023 or + scounteren_csr__read__h616076 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616212 or + scause_csr__read__h616214 or csrf_stval_csr or - sip_csr__read__h616352 or - satp_csr__read__h616415 or - mstatus_csr__read__h616558 or - medeleg_csr__read__h616706 or - mideleg_csr__read__h616801 or - mie_csr__read__h616925 or - mtvec_csr__read__h617007 or - mcounteren_csr__read__h617099 or + sip_csr__read__h616354 or + satp_csr__read__h616417 or + mstatus_csr__read__h616560 or + medeleg_csr__read__h616708 or + mideleg_csr__read__h616803 or + mie_csr__read__h616927 or + mtvec_csr__read__h617009 or + mcounteren_csr__read__h617101 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617354 or + mcause_csr__read__h617356 or csrf_mtval_csr or - mip_csr__read__h617587 or + mip_csr__read__h617589 or csrf_rg_tselect or - rg_tdata1__read__h618542 or + rg_tdata1__read__h618544 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h615817 or - n__read__h617691 or n__read__h617882 or csrf_time_reg) + x_reg_ifc__read__h615819 or + n__read__h617693 or n__read__h617884 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h746306 = fflags_csr__read__h615687; - 12'd2: data_out__h746306 = frm_csr__read__h615698; - 12'd3: data_out__h746306 = fcsr_csr__read__h615712; - 12'd256: data_out__h746306 = sstatus_csr__read__h615908; - 12'd260: data_out__h746306 = sie_csr__read__h615978; - 12'd261: data_out__h746306 = stvec_csr__read__h616021; - 12'd262: data_out__h746306 = scounteren_csr__read__h616074; - 12'd320: data_out__h746306 = csrf_sscratch_csr; - 12'd321: data_out__h746306 = csrf_sepc_csr; - 12'd322: data_out__h746306 = scause_csr__read__h616212; - 12'd323: data_out__h746306 = csrf_stval_csr; - 12'd324: data_out__h746306 = sip_csr__read__h616352; - 12'd384: data_out__h746306 = satp_csr__read__h616415; - 12'd768: data_out__h746306 = mstatus_csr__read__h616558; - 12'd769: data_out__h746306 = 64'h800000000014112D; - 12'd770: data_out__h746306 = medeleg_csr__read__h616706; - 12'd771: data_out__h746306 = mideleg_csr__read__h616801; - 12'd772: data_out__h746306 = mie_csr__read__h616925; - 12'd773: data_out__h746306 = mtvec_csr__read__h617007; - 12'd774: data_out__h746306 = mcounteren_csr__read__h617099; - 12'd832: data_out__h746306 = csrf_mscratch_csr; - 12'd833: data_out__h746306 = csrf_mepc_csr; - 12'd834: data_out__h746306 = mcause_csr__read__h617354; - 12'd835: data_out__h746306 = csrf_mtval_csr; - 12'd836: data_out__h746306 = mip_csr__read__h617587; - 12'd1952: data_out__h746306 = csrf_rg_tselect; - 12'd1953: data_out__h746306 = rg_tdata1__read__h618542; - 12'd1954: data_out__h746306 = csrf_rg_tdata2; - 12'd1955: data_out__h746306 = csrf_rg_tdata3; - 12'd1968: data_out__h746306 = csrf_rg_dcsr; - 12'd1969: data_out__h746306 = csrf_rg_dpc; - 12'd1970: data_out__h746306 = csrf_rg_dscratch0; - 12'd1971: data_out__h746306 = csrf_rg_dscratch1; + 12'd1: data_out__h747341 = fflags_csr__read__h615689; + 12'd2: data_out__h747341 = frm_csr__read__h615700; + 12'd3: data_out__h747341 = fcsr_csr__read__h615714; + 12'd256: data_out__h747341 = sstatus_csr__read__h615910; + 12'd260: data_out__h747341 = sie_csr__read__h615980; + 12'd261: data_out__h747341 = stvec_csr__read__h616023; + 12'd262: data_out__h747341 = scounteren_csr__read__h616076; + 12'd320: data_out__h747341 = csrf_sscratch_csr; + 12'd321: data_out__h747341 = csrf_sepc_csr; + 12'd322: data_out__h747341 = scause_csr__read__h616214; + 12'd323: data_out__h747341 = csrf_stval_csr; + 12'd324: data_out__h747341 = sip_csr__read__h616354; + 12'd384: data_out__h747341 = satp_csr__read__h616417; + 12'd768: data_out__h747341 = mstatus_csr__read__h616560; + 12'd769: data_out__h747341 = 64'h800000000014112D; + 12'd770: data_out__h747341 = medeleg_csr__read__h616708; + 12'd771: data_out__h747341 = mideleg_csr__read__h616803; + 12'd772: data_out__h747341 = mie_csr__read__h616927; + 12'd773: data_out__h747341 = mtvec_csr__read__h617009; + 12'd774: data_out__h747341 = mcounteren_csr__read__h617101; + 12'd832: data_out__h747341 = csrf_mscratch_csr; + 12'd833: data_out__h747341 = csrf_mepc_csr; + 12'd834: data_out__h747341 = mcause_csr__read__h617356; + 12'd835: data_out__h747341 = csrf_mtval_csr; + 12'd836: data_out__h747341 = mip_csr__read__h617589; + 12'd1952: data_out__h747341 = csrf_rg_tselect; + 12'd1953: data_out__h747341 = rg_tdata1__read__h618544; + 12'd1954: data_out__h747341 = csrf_rg_tdata2; + 12'd1955: data_out__h747341 = csrf_rg_tdata3; + 12'd1968: data_out__h747341 = csrf_rg_dcsr; + 12'd1969: data_out__h747341 = csrf_rg_dpc; + 12'd1970: data_out__h747341 = csrf_rg_dscratch0; + 12'd1971: data_out__h747341 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h746306 = 64'd0; - 12'd2049: data_out__h746306 = x_reg_ifc__read__h615817; - 12'd2816, 12'd3072: data_out__h746306 = n__read__h617691; - 12'd2818, 12'd3074: data_out__h746306 = n__read__h617882; - 12'd3073: data_out__h746306 = csrf_time_reg; - default: data_out__h746306 = 64'b0; + data_out__h747341 = 64'd0; + 12'd2049: data_out__h747341 = x_reg_ifc__read__h615819; + 12'd2816, 12'd3072: data_out__h747341 = n__read__h617693; + 12'd2818, 12'd3074: data_out__h747341 = n__read__h617884; + 12'd3073: data_out__h747341 = csrf_time_reg; + default: data_out__h747341 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h615687 or - frm_csr__read__h615698 or - fcsr_csr__read__h615712 or - sstatus_csr__read__h615908 or - sie_csr__read__h615978 or - stvec_csr__read__h616021 or - scounteren_csr__read__h616074 or + fflags_csr__read__h615689 or + frm_csr__read__h615700 or + fcsr_csr__read__h615714 or + sstatus_csr__read__h615910 or + sie_csr__read__h615980 or + stvec_csr__read__h616023 or + scounteren_csr__read__h616076 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616212 or + scause_csr__read__h616214 or csrf_stval_csr or - sip_csr__read__h616352 or - satp_csr__read__h616415 or - mstatus_csr__read__h616558 or - medeleg_csr__read__h616706 or - mideleg_csr__read__h616801 or - mie_csr__read__h616925 or - mtvec_csr__read__h617007 or - mcounteren_csr__read__h617099 or + sip_csr__read__h616354 or + satp_csr__read__h616417 or + mstatus_csr__read__h616560 or + medeleg_csr__read__h616708 or + mideleg_csr__read__h616803 or + mie_csr__read__h616927 or + mtvec_csr__read__h617009 or + mcounteren_csr__read__h617101 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617354 or + mcause_csr__read__h617356 or csrf_mtval_csr or - mip_csr__read__h617587 or + mip_csr__read__h617589 or csrf_rg_tselect or - rg_tdata1__read__h618542 or + rg_tdata1__read__h618544 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h615817 or - n__read__h617691 or n__read__h617882 or csrf_time_reg) + x_reg_ifc__read__h615819 or + n__read__h617693 or n__read__h617884 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h615386 = fflags_csr__read__h615687; - 12'd2: rVal1__h615386 = frm_csr__read__h615698; - 12'd3: rVal1__h615386 = fcsr_csr__read__h615712; - 12'd256: rVal1__h615386 = sstatus_csr__read__h615908; - 12'd260: rVal1__h615386 = sie_csr__read__h615978; - 12'd261: rVal1__h615386 = stvec_csr__read__h616021; - 12'd262: rVal1__h615386 = scounteren_csr__read__h616074; - 12'd320: rVal1__h615386 = csrf_sscratch_csr; - 12'd321: rVal1__h615386 = csrf_sepc_csr; - 12'd322: rVal1__h615386 = scause_csr__read__h616212; - 12'd323: rVal1__h615386 = csrf_stval_csr; - 12'd324: rVal1__h615386 = sip_csr__read__h616352; - 12'd384: rVal1__h615386 = satp_csr__read__h616415; - 12'd768: rVal1__h615386 = mstatus_csr__read__h616558; - 12'd769: rVal1__h615386 = 64'h800000000014112D; - 12'd770: rVal1__h615386 = medeleg_csr__read__h616706; - 12'd771: rVal1__h615386 = mideleg_csr__read__h616801; - 12'd772: rVal1__h615386 = mie_csr__read__h616925; - 12'd773: rVal1__h615386 = mtvec_csr__read__h617007; - 12'd774: rVal1__h615386 = mcounteren_csr__read__h617099; - 12'd832: rVal1__h615386 = csrf_mscratch_csr; - 12'd833: rVal1__h615386 = csrf_mepc_csr; - 12'd834: rVal1__h615386 = mcause_csr__read__h617354; - 12'd835: rVal1__h615386 = csrf_mtval_csr; - 12'd836: rVal1__h615386 = mip_csr__read__h617587; - 12'd1952: rVal1__h615386 = csrf_rg_tselect; - 12'd1953: rVal1__h615386 = rg_tdata1__read__h618542; - 12'd1954: rVal1__h615386 = csrf_rg_tdata2; - 12'd1955: rVal1__h615386 = csrf_rg_tdata3; - 12'd1968: rVal1__h615386 = csrf_rg_dcsr; - 12'd1969: rVal1__h615386 = csrf_rg_dpc; - 12'd1970: rVal1__h615386 = csrf_rg_dscratch0; - 12'd1971: rVal1__h615386 = csrf_rg_dscratch1; + 12'd1: rVal1__h615388 = fflags_csr__read__h615689; + 12'd2: rVal1__h615388 = frm_csr__read__h615700; + 12'd3: rVal1__h615388 = fcsr_csr__read__h615714; + 12'd256: rVal1__h615388 = sstatus_csr__read__h615910; + 12'd260: rVal1__h615388 = sie_csr__read__h615980; + 12'd261: rVal1__h615388 = stvec_csr__read__h616023; + 12'd262: rVal1__h615388 = scounteren_csr__read__h616076; + 12'd320: rVal1__h615388 = csrf_sscratch_csr; + 12'd321: rVal1__h615388 = csrf_sepc_csr; + 12'd322: rVal1__h615388 = scause_csr__read__h616214; + 12'd323: rVal1__h615388 = csrf_stval_csr; + 12'd324: rVal1__h615388 = sip_csr__read__h616354; + 12'd384: rVal1__h615388 = satp_csr__read__h616417; + 12'd768: rVal1__h615388 = mstatus_csr__read__h616560; + 12'd769: rVal1__h615388 = 64'h800000000014112D; + 12'd770: rVal1__h615388 = medeleg_csr__read__h616708; + 12'd771: rVal1__h615388 = mideleg_csr__read__h616803; + 12'd772: rVal1__h615388 = mie_csr__read__h616927; + 12'd773: rVal1__h615388 = mtvec_csr__read__h617009; + 12'd774: rVal1__h615388 = mcounteren_csr__read__h617101; + 12'd832: rVal1__h615388 = csrf_mscratch_csr; + 12'd833: rVal1__h615388 = csrf_mepc_csr; + 12'd834: rVal1__h615388 = mcause_csr__read__h617356; + 12'd835: rVal1__h615388 = csrf_mtval_csr; + 12'd836: rVal1__h615388 = mip_csr__read__h617589; + 12'd1952: rVal1__h615388 = csrf_rg_tselect; + 12'd1953: rVal1__h615388 = rg_tdata1__read__h618544; + 12'd1954: rVal1__h615388 = csrf_rg_tdata2; + 12'd1955: rVal1__h615388 = csrf_rg_tdata3; + 12'd1968: rVal1__h615388 = csrf_rg_dcsr; + 12'd1969: rVal1__h615388 = csrf_rg_dpc; + 12'd1970: rVal1__h615388 = csrf_rg_dscratch0; + 12'd1971: rVal1__h615388 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h615386 = 64'd0; - 12'd2049: rVal1__h615386 = x_reg_ifc__read__h615817; - 12'd2816, 12'd3072: rVal1__h615386 = n__read__h617691; - 12'd2818, 12'd3074: rVal1__h615386 = n__read__h617882; - 12'd3073: rVal1__h615386 = csrf_time_reg; - default: rVal1__h615386 = 64'b0; + rVal1__h615388 = 64'd0; + 12'd2049: rVal1__h615388 = x_reg_ifc__read__h615819; + 12'd2816, 12'd3072: rVal1__h615388 = n__read__h617693; + 12'd2818, 12'd3074: rVal1__h615388 = n__read__h617884; + 12'd3073: rVal1__h615388 = csrf_time_reg; + default: rVal1__h615388 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h615687 or - frm_csr__read__h615698 or - fcsr_csr__read__h615712 or - sstatus_csr__read__h615908 or - sie_csr__read__h615978 or - stvec_csr__read__h616021 or - scounteren_csr__read__h616074 or + fflags_csr__read__h615689 or + frm_csr__read__h615700 or + fcsr_csr__read__h615714 or + sstatus_csr__read__h615910 or + sie_csr__read__h615980 or + stvec_csr__read__h616023 or + scounteren_csr__read__h616076 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616212 or + scause_csr__read__h616214 or csrf_stval_csr or - sip_csr__read__h616352 or - satp_csr__read__h616415 or - mstatus_csr__read__h616558 or - medeleg_csr__read__h616706 or - mideleg_csr__read__h616801 or - mie_csr__read__h616925 or - mtvec_csr__read__h617007 or - mcounteren_csr__read__h617099 or + sip_csr__read__h616354 or + satp_csr__read__h616417 or + mstatus_csr__read__h616560 or + medeleg_csr__read__h616708 or + mideleg_csr__read__h616803 or + mie_csr__read__h616927 or + mtvec_csr__read__h617009 or + mcounteren_csr__read__h617101 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617354 or + mcause_csr__read__h617356 or csrf_mtval_csr or - mip_csr__read__h617587 or + mip_csr__read__h617589 or csrf_rg_tselect or - rg_tdata1__read__h618542 or + rg_tdata1__read__h618544 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h615817 or - n__read__h617691 or n__read__h617882 or csrf_time_reg) + x_reg_ifc__read__h615819 or + n__read__h617693 or n__read__h617884 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h640612 = fflags_csr__read__h615687; - 12'd2: rVal1__h640612 = frm_csr__read__h615698; - 12'd3: rVal1__h640612 = fcsr_csr__read__h615712; - 12'd256: rVal1__h640612 = sstatus_csr__read__h615908; - 12'd260: rVal1__h640612 = sie_csr__read__h615978; - 12'd261: rVal1__h640612 = stvec_csr__read__h616021; - 12'd262: rVal1__h640612 = scounteren_csr__read__h616074; - 12'd320: rVal1__h640612 = csrf_sscratch_csr; - 12'd321: rVal1__h640612 = csrf_sepc_csr; - 12'd322: rVal1__h640612 = scause_csr__read__h616212; - 12'd323: rVal1__h640612 = csrf_stval_csr; - 12'd324: rVal1__h640612 = sip_csr__read__h616352; - 12'd384: rVal1__h640612 = satp_csr__read__h616415; - 12'd768: rVal1__h640612 = mstatus_csr__read__h616558; - 12'd769: rVal1__h640612 = 64'h800000000014112D; - 12'd770: rVal1__h640612 = medeleg_csr__read__h616706; - 12'd771: rVal1__h640612 = mideleg_csr__read__h616801; - 12'd772: rVal1__h640612 = mie_csr__read__h616925; - 12'd773: rVal1__h640612 = mtvec_csr__read__h617007; - 12'd774: rVal1__h640612 = mcounteren_csr__read__h617099; - 12'd832: rVal1__h640612 = csrf_mscratch_csr; - 12'd833: rVal1__h640612 = csrf_mepc_csr; - 12'd834: rVal1__h640612 = mcause_csr__read__h617354; - 12'd835: rVal1__h640612 = csrf_mtval_csr; - 12'd836: rVal1__h640612 = mip_csr__read__h617587; - 12'd1952: rVal1__h640612 = csrf_rg_tselect; - 12'd1953: rVal1__h640612 = rg_tdata1__read__h618542; - 12'd1954: rVal1__h640612 = csrf_rg_tdata2; - 12'd1955: rVal1__h640612 = csrf_rg_tdata3; - 12'd1968: rVal1__h640612 = csrf_rg_dcsr; - 12'd1969: rVal1__h640612 = csrf_rg_dpc; - 12'd1970: rVal1__h640612 = csrf_rg_dscratch0; - 12'd1971: rVal1__h640612 = csrf_rg_dscratch1; + 12'd1: rVal1__h640614 = fflags_csr__read__h615689; + 12'd2: rVal1__h640614 = frm_csr__read__h615700; + 12'd3: rVal1__h640614 = fcsr_csr__read__h615714; + 12'd256: rVal1__h640614 = sstatus_csr__read__h615910; + 12'd260: rVal1__h640614 = sie_csr__read__h615980; + 12'd261: rVal1__h640614 = stvec_csr__read__h616023; + 12'd262: rVal1__h640614 = scounteren_csr__read__h616076; + 12'd320: rVal1__h640614 = csrf_sscratch_csr; + 12'd321: rVal1__h640614 = csrf_sepc_csr; + 12'd322: rVal1__h640614 = scause_csr__read__h616214; + 12'd323: rVal1__h640614 = csrf_stval_csr; + 12'd324: rVal1__h640614 = sip_csr__read__h616354; + 12'd384: rVal1__h640614 = satp_csr__read__h616417; + 12'd768: rVal1__h640614 = mstatus_csr__read__h616560; + 12'd769: rVal1__h640614 = 64'h800000000014112D; + 12'd770: rVal1__h640614 = medeleg_csr__read__h616708; + 12'd771: rVal1__h640614 = mideleg_csr__read__h616803; + 12'd772: rVal1__h640614 = mie_csr__read__h616927; + 12'd773: rVal1__h640614 = mtvec_csr__read__h617009; + 12'd774: rVal1__h640614 = mcounteren_csr__read__h617101; + 12'd832: rVal1__h640614 = csrf_mscratch_csr; + 12'd833: rVal1__h640614 = csrf_mepc_csr; + 12'd834: rVal1__h640614 = mcause_csr__read__h617356; + 12'd835: rVal1__h640614 = csrf_mtval_csr; + 12'd836: rVal1__h640614 = mip_csr__read__h617589; + 12'd1952: rVal1__h640614 = csrf_rg_tselect; + 12'd1953: rVal1__h640614 = rg_tdata1__read__h618544; + 12'd1954: rVal1__h640614 = csrf_rg_tdata2; + 12'd1955: rVal1__h640614 = csrf_rg_tdata3; + 12'd1968: rVal1__h640614 = csrf_rg_dcsr; + 12'd1969: rVal1__h640614 = csrf_rg_dpc; + 12'd1970: rVal1__h640614 = csrf_rg_dscratch0; + 12'd1971: rVal1__h640614 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h640612 = 64'd0; - 12'd2049: rVal1__h640612 = x_reg_ifc__read__h615817; - 12'd2816, 12'd3072: rVal1__h640612 = n__read__h617691; - 12'd2818, 12'd3074: rVal1__h640612 = n__read__h617882; - 12'd3073: rVal1__h640612 = csrf_time_reg; - default: rVal1__h640612 = 64'b0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; + rVal1__h640614 = 64'd0; + 12'd2049: rVal1__h640614 = x_reg_ifc__read__h615819; + 12'd2816, 12'd3072: rVal1__h640614 = n__read__h617693; + 12'd2818, 12'd3074: rVal1__h640614 = n__read__h617884; + 12'd3073: rVal1__h640614 = csrf_time_reg; + default: rVal1__h640614 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h350487 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h350488 = 8'd255; 3'd2: - _theResult___fst_exp__h350487 = + _theResult___fst_exp__h350488 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h350487 = + _theResult___fst_exp__h350488 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h350487 = 8'd254; - default: _theResult___fst_exp__h350487 = 8'd0; + 3'd4: _theResult___fst_exp__h350488 = 8'd254; + default: _theResult___fst_exp__h350488 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h350488 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h350489 = 23'd0; 3'd2: - _theResult___fst_sfd__h350488 = + _theResult___fst_sfd__h350489 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h350488 = + _theResult___fst_sfd__h350489 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h350488 = 23'd8388607; - default: _theResult___fst_sfd__h350488 = 23'd0; + 3'd4: _theResult___fst_sfd__h350489 = 23'd8388607; + default: _theResult___fst_sfd__h350489 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h396186 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h396187 = 8'd255; 3'd2: - _theResult___fst_exp__h396186 = + _theResult___fst_exp__h396187 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h396186 = + _theResult___fst_exp__h396187 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h396186 = 8'd254; - default: _theResult___fst_exp__h396186 = 8'd0; + 3'd4: _theResult___fst_exp__h396187 = 8'd254; + default: _theResult___fst_exp__h396187 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h396187 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h396188 = 23'd0; 3'd2: - _theResult___fst_sfd__h396187 = + _theResult___fst_sfd__h396188 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h396187 = + _theResult___fst_sfd__h396188 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h396187 = 23'd8388607; - default: _theResult___fst_sfd__h396187 = 23'd0; + 3'd4: _theResult___fst_sfd__h396188 = 23'd8388607; + default: _theResult___fst_sfd__h396188 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h441881 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h441882 = 8'd255; 3'd2: - _theResult___fst_exp__h441881 = + _theResult___fst_exp__h441882 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h441881 = + _theResult___fst_exp__h441882 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h441881 = 8'd254; - default: _theResult___fst_exp__h441881 = 8'd0; + 3'd4: _theResult___fst_exp__h441882 = 8'd254; + default: _theResult___fst_exp__h441882 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h441882 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h441883 = 23'd0; 3'd2: - _theResult___fst_sfd__h441882 = + _theResult___fst_sfd__h441883 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h441882 = + _theResult___fst_sfd__h441883 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h441882 = 23'd8388607; - default: _theResult___fst_sfd__h441882 = 23'd0; + 3'd4: _theResult___fst_sfd__h441883 = 23'd8388607; + default: _theResult___fst_sfd__h441883 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33473,16 +33526,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h717423 = commitStage_commitTrap[35:32]; - default: i__h717423 = 4'd15; + i__h718403 = commitStage_commitTrap[35:32]; + default: i__h718403 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h717583 = commitStage_commitTrap[35:32]; - default: i__h717583 = 4'd15; + i__h718563 = commitStage_commitTrap[35:32]; + default: i__h718563 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -33496,17 +33549,6 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[63:32]; endcase end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = - mmio_dataRespQ_data_0[31:0]; - 1'd1: - SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = - mmio_dataRespQ_data_0[63:32]; - endcase - end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:18]) @@ -33554,6 +33596,17 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19]) + 1'd0: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = + mmio_dataRespQ_data_0[31:0]; + 1'd1: + SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 = + mmio_dataRespQ_data_0[63:32]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:18]) 2'd0: @@ -33710,394 +33763,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h359224 or - _theResult___fst_exp__h367272 or - out_exp__h367717 or _theResult___exp__h367714) + always@(guard__h359225 or + _theResult___fst_exp__h367273 or + out_exp__h367718 or _theResult___exp__h367715) begin - case (guard__h359224) + case (guard__h359225) 2'b0, 2'b01: - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q33 = - _theResult___fst_exp__h367272; + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q33 = + _theResult___fst_exp__h367273; 2'b10: - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q33 = - out_exp__h367717; + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q33 = + out_exp__h367718; 2'b11: - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q33 = - _theResult___exp__h367714; + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q33 = + _theResult___exp__h367715; endcase end - always@(guard__h359224 or - _theResult___fst_exp__h367272 or _theResult___exp__h367714) + always@(guard__h359225 or + _theResult___fst_exp__h367273 or _theResult___exp__h367715) begin - case (guard__h359224) + case (guard__h359225) 2'b0: - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q34 = - _theResult___fst_exp__h367272; + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q34 = + _theResult___fst_exp__h367273; 2'b01, 2'b10, 2'b11: - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q34 = - _theResult___exp__h367714; + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q34 = + _theResult___exp__h367715; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q33 or - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q34 or + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q33 or + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q34 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4632 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4634 or - _theResult___fst_exp__h367272) + _theResult___fst_exp__h367273) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h367792 = - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q33; + _theResult___fst_exp__h367793 = + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q33; 3'd1: - _theResult___fst_exp__h367792 = - CASE_guard59224_0b0_theResult___fst_exp67272_0_ETC__q34; + _theResult___fst_exp__h367793 = + CASE_guard59225_0b0_theResult___fst_exp67273_0_ETC__q34; 3'd2: - _theResult___fst_exp__h367792 = + _theResult___fst_exp__h367793 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4632; 3'd3: - _theResult___fst_exp__h367792 = + _theResult___fst_exp__h367793 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4634; - 3'd4: _theResult___fst_exp__h367792 = _theResult___fst_exp__h367272; - default: _theResult___fst_exp__h367792 = 8'd0; + 3'd4: _theResult___fst_exp__h367793 = _theResult___fst_exp__h367273; + default: _theResult___fst_exp__h367793 = 8'd0; endcase end - always@(guard__h350515 or - _theResult___fst_exp__h358616 or - out_exp__h359135 or _theResult___exp__h359132) + always@(guard__h350516 or + _theResult___fst_exp__h358617 or + out_exp__h359136 or _theResult___exp__h359133) begin - case (guard__h350515) + case (guard__h350516) 2'b0, 2'b01: - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q35 = - _theResult___fst_exp__h358616; + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q35 = + _theResult___fst_exp__h358617; 2'b10: - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q35 = - out_exp__h359135; + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q35 = + out_exp__h359136; 2'b11: - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q35 = - _theResult___exp__h359132; + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q35 = + _theResult___exp__h359133; endcase end - always@(guard__h350515 or - _theResult___fst_exp__h358616 or _theResult___exp__h359132) + always@(guard__h350516 or + _theResult___fst_exp__h358617 or _theResult___exp__h359133) begin - case (guard__h350515) + case (guard__h350516) 2'b0: - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q36 = - _theResult___fst_exp__h358616; + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q36 = + _theResult___fst_exp__h358617; 2'b01, 2'b10, 2'b11: - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q36 = - _theResult___exp__h359132; + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q36 = + _theResult___exp__h359133; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q35 or - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q36 or + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q35 or + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q36 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4413 or - _theResult___fst_exp__h358616) + _theResult___fst_exp__h358617) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h359210 = - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q35; + _theResult___fst_exp__h359211 = + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q35; 3'd1: - _theResult___fst_exp__h359210 = - CASE_guard50515_0b0_theResult___fst_exp58616_0_ETC__q36; + _theResult___fst_exp__h359211 = + CASE_guard50516_0b0_theResult___fst_exp58617_0_ETC__q36; 3'd2: - _theResult___fst_exp__h359210 = + _theResult___fst_exp__h359211 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410; 3'd3: - _theResult___fst_exp__h359210 = + _theResult___fst_exp__h359211 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4413; - 3'd4: _theResult___fst_exp__h359210 = _theResult___fst_exp__h358616; - default: _theResult___fst_exp__h359210 = 8'd0; + 3'd4: _theResult___fst_exp__h359211 = _theResult___fst_exp__h358617; + default: _theResult___fst_exp__h359211 = 8'd0; endcase end - always@(guard__h368154 or - _theResult___fst_exp__h376382 or - out_exp__h376901 or _theResult___exp__h376898) + always@(guard__h368155 or + _theResult___fst_exp__h376383 or + out_exp__h376902 or _theResult___exp__h376899) begin - case (guard__h368154) + case (guard__h368155) 2'b0, 2'b01: - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q41 = - _theResult___fst_exp__h376382; + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q41 = + _theResult___fst_exp__h376383; 2'b10: - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q41 = - out_exp__h376901; + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q41 = + out_exp__h376902; 2'b11: - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q41 = - _theResult___exp__h376898; + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q41 = + _theResult___exp__h376899; endcase end - always@(guard__h368154 or - _theResult___fst_exp__h376382 or _theResult___exp__h376898) + always@(guard__h368155 or + _theResult___fst_exp__h376383 or _theResult___exp__h376899) begin - case (guard__h368154) + case (guard__h368155) 2'b0: - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q42 = - _theResult___fst_exp__h376382; + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q42 = + _theResult___fst_exp__h376383; 2'b01, 2'b10, 2'b11: - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q42 = - _theResult___exp__h376898; + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q42 = + _theResult___exp__h376899; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q41 or - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q42 or + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q41 or + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q42 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4957 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4959 or - _theResult___fst_exp__h376382) + _theResult___fst_exp__h376383) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h376976 = - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q41; + _theResult___fst_exp__h376977 = + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q41; 3'd1: - _theResult___fst_exp__h376976 = - CASE_guard68154_0b0_theResult___fst_exp76382_0_ETC__q42; + _theResult___fst_exp__h376977 = + CASE_guard68155_0b0_theResult___fst_exp76383_0_ETC__q42; 3'd2: - _theResult___fst_exp__h376976 = + _theResult___fst_exp__h376977 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4957; 3'd3: - _theResult___fst_exp__h376976 = + _theResult___fst_exp__h376977 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4959; - 3'd4: _theResult___fst_exp__h376976 = _theResult___fst_exp__h376382; - default: _theResult___fst_exp__h376976 = 8'd0; + 3'd4: _theResult___fst_exp__h376977 = _theResult___fst_exp__h376383; + default: _theResult___fst_exp__h376977 = 8'd0; endcase end - always@(guard__h376990 or - _theResult___fst_exp__h385067 or - out_exp__h385537 or _theResult___exp__h385534) + always@(guard__h376991 or + _theResult___fst_exp__h385068 or + out_exp__h385538 or _theResult___exp__h385535) begin - case (guard__h376990) + case (guard__h376991) 2'b0, 2'b01: - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q46 = - _theResult___fst_exp__h385067; + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q46 = + _theResult___fst_exp__h385068; 2'b10: - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q46 = - out_exp__h385537; + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q46 = + out_exp__h385538; 2'b11: - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q46 = - _theResult___exp__h385534; + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q46 = + _theResult___exp__h385535; endcase end - always@(guard__h376990 or - _theResult___fst_exp__h385067 or _theResult___exp__h385534) + always@(guard__h376991 or + _theResult___fst_exp__h385068 or _theResult___exp__h385535) begin - case (guard__h376990) + case (guard__h376991) 2'b0: - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q47 = - _theResult___fst_exp__h385067; + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q47 = + _theResult___fst_exp__h385068; 2'b01, 2'b10, 2'b11: - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q47 = - _theResult___exp__h385534; + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q47 = + _theResult___exp__h385535; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q46 or - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q47 or + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q46 or + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q47 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5026 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5028 or - _theResult___fst_exp__h385067) + _theResult___fst_exp__h385068) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h385612 = - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q46; + _theResult___fst_exp__h385613 = + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q46; 3'd1: - _theResult___fst_exp__h385612 = - CASE_guard76990_0b0_theResult___fst_exp85067_0_ETC__q47; + _theResult___fst_exp__h385613 = + CASE_guard76991_0b0_theResult___fst_exp85068_0_ETC__q47; 3'd2: - _theResult___fst_exp__h385612 = + _theResult___fst_exp__h385613 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5026; 3'd3: - _theResult___fst_exp__h385612 = + _theResult___fst_exp__h385613 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5028; - 3'd4: _theResult___fst_exp__h385612 = _theResult___fst_exp__h385067; - default: _theResult___fst_exp__h385612 = 8'd0; + 3'd4: _theResult___fst_exp__h385613 = _theResult___fst_exp__h385068; + default: _theResult___fst_exp__h385613 = 8'd0; endcase end - always@(guard__h359224 or - _theResult___snd__h367223 or - out_sfd__h367718 or _theResult___sfd__h367715) + always@(guard__h359225 or + _theResult___snd__h367224 or + out_sfd__h367719 or _theResult___sfd__h367716) begin - case (guard__h359224) + case (guard__h359225) 2'b0, 2'b01: - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q48 = - _theResult___snd__h367223[56:34]; + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q48 = + _theResult___snd__h367224[56:34]; 2'b10: - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q48 = - out_sfd__h367718; + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q48 = + out_sfd__h367719; 2'b11: - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q48 = - _theResult___sfd__h367715; + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q48 = + _theResult___sfd__h367716; endcase end - always@(guard__h359224 or - _theResult___snd__h367223 or _theResult___sfd__h367715) + always@(guard__h359225 or + _theResult___snd__h367224 or _theResult___sfd__h367716) begin - case (guard__h359224) + case (guard__h359225) 2'b0: - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q49 = - _theResult___snd__h367223[56:34]; + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q49 = + _theResult___snd__h367224[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q49 = - _theResult___sfd__h367715; + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q49 = + _theResult___sfd__h367716; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q48 or - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q49 or + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q48 or + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q49 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5076 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5078 or - _theResult___snd__h367223) + _theResult___snd__h367224) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h367793 = - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q48; + _theResult___fst_sfd__h367794 = + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q48; 3'd1: - _theResult___fst_sfd__h367793 = - CASE_guard59224_0b0_theResult___snd67223_BITS__ETC__q49; + _theResult___fst_sfd__h367794 = + CASE_guard59225_0b0_theResult___snd67224_BITS__ETC__q49; 3'd2: - _theResult___fst_sfd__h367793 = + _theResult___fst_sfd__h367794 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5076; 3'd3: - _theResult___fst_sfd__h367793 = + _theResult___fst_sfd__h367794 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5078; - 3'd4: _theResult___fst_sfd__h367793 = _theResult___snd__h367223[56:34]; - default: _theResult___fst_sfd__h367793 = 23'd0; + 3'd4: _theResult___fst_sfd__h367794 = _theResult___snd__h367224[56:34]; + default: _theResult___fst_sfd__h367794 = 23'd0; endcase end - always@(guard__h350515 or - sfdin__h358610 or out_sfd__h359136 or _theResult___sfd__h359133) + always@(guard__h350516 or + sfdin__h358611 or out_sfd__h359137 or _theResult___sfd__h359134) begin - case (guard__h350515) + case (guard__h350516) 2'b0, 2'b01: - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q50 = - sfdin__h358610[56:34]; + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q50 = + sfdin__h358611[56:34]; 2'b10: - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q50 = - out_sfd__h359136; + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q50 = + out_sfd__h359137; 2'b11: - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h359133; + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h359134; endcase end - always@(guard__h350515 or sfdin__h358610 or _theResult___sfd__h359133) + always@(guard__h350516 or sfdin__h358611 or _theResult___sfd__h359134) begin - case (guard__h350515) + case (guard__h350516) 2'b0: - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q51 = - sfdin__h358610[56:34]; + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q51 = + sfdin__h358611[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h359133; + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h359134; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q50 or - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q51 or + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q50 or + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q51 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059 or - sfdin__h358610) + sfdin__h358611) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h359211 = - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h359212 = + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q50; 3'd1: - _theResult___fst_sfd__h359211 = - CASE_guard50515_0b0_sfdin58610_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h359212 = + CASE_guard50516_0b0_sfdin58611_BITS_56_TO_34_0_ETC__q51; 3'd2: - _theResult___fst_sfd__h359211 = + _theResult___fst_sfd__h359212 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057; 3'd3: - _theResult___fst_sfd__h359211 = + _theResult___fst_sfd__h359212 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059; - 3'd4: _theResult___fst_sfd__h359211 = sfdin__h358610[56:34]; - default: _theResult___fst_sfd__h359211 = 23'd0; + 3'd4: _theResult___fst_sfd__h359212 = sfdin__h358611[56:34]; + default: _theResult___fst_sfd__h359212 = 23'd0; endcase end - always@(guard__h368154 or - sfdin__h376376 or out_sfd__h376902 or _theResult___sfd__h376899) + always@(guard__h368155 or + sfdin__h376377 or out_sfd__h376903 or _theResult___sfd__h376900) begin - case (guard__h368154) + case (guard__h368155) 2'b0, 2'b01: - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q52 = - sfdin__h376376[56:34]; + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q52 = + sfdin__h376377[56:34]; 2'b10: - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q52 = - out_sfd__h376902; + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q52 = + out_sfd__h376903; 2'b11: - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h376899; + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h376900; endcase end - always@(guard__h368154 or sfdin__h376376 or _theResult___sfd__h376899) + always@(guard__h368155 or sfdin__h376377 or _theResult___sfd__h376900) begin - case (guard__h368154) + case (guard__h368155) 2'b0: - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q53 = - sfdin__h376376[56:34]; + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q53 = + sfdin__h376377[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q53 = - _theResult___sfd__h376899; + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q53 = + _theResult___sfd__h376900; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q52 or - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q53 or + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q52 or + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q53 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5103 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5105 or - sfdin__h376376) + sfdin__h376377) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h376977 = - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h376978 = + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q52; 3'd1: - _theResult___fst_sfd__h376977 = - CASE_guard68154_0b0_sfdin76376_BITS_56_TO_34_0_ETC__q53; + _theResult___fst_sfd__h376978 = + CASE_guard68155_0b0_sfdin76377_BITS_56_TO_34_0_ETC__q53; 3'd2: - _theResult___fst_sfd__h376977 = + _theResult___fst_sfd__h376978 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5103; 3'd3: - _theResult___fst_sfd__h376977 = + _theResult___fst_sfd__h376978 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5105; - 3'd4: _theResult___fst_sfd__h376977 = sfdin__h376376[56:34]; - default: _theResult___fst_sfd__h376977 = 23'd0; + 3'd4: _theResult___fst_sfd__h376978 = sfdin__h376377[56:34]; + default: _theResult___fst_sfd__h376978 = 23'd0; endcase end - always@(guard__h350515 or + always@(guard__h376991 or + _theResult___snd__h385014 or + out_sfd__h385539 or _theResult___sfd__h385536) + begin + case (guard__h376991) + 2'b0, 2'b01: + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q54 = + _theResult___snd__h385014[56:34]; + 2'b10: + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q54 = + out_sfd__h385539; + 2'b11: + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q54 = + _theResult___sfd__h385536; + endcase + end + always@(guard__h376991 or + _theResult___snd__h385014 or _theResult___sfd__h385536) + begin + case (guard__h376991) + 2'b0: + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q55 = + _theResult___snd__h385014[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q55 = + _theResult___sfd__h385536; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q54 or + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q55 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124 or + _theResult___snd__h385014) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h385614 = + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q54; + 3'd1: + _theResult___fst_sfd__h385614 = + CASE_guard76991_0b0_theResult___snd85014_BITS__ETC__q55; + 3'd2: + _theResult___fst_sfd__h385614 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122; + 3'd3: + _theResult___fst_sfd__h385614 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124; + 3'd4: _theResult___fst_sfd__h385614 = _theResult___snd__h385014[56:34]; + default: _theResult___fst_sfd__h385614 = 23'd0; + endcase + end + always@(guard__h350516 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350515) + case (guard__h350516) 2'b0, 2'b01, 2'b10: - CASE_guard50515_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + CASE_guard50516_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50515_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = - guard__h350515 == 2'b11 && + CASE_guard50516_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = + guard__h350516 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50515_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or - guard__h350515) + CASE_guard50516_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or + guard__h350516) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = - CASE_guard50515_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; + CASE_guard50516_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = - (guard__h350515 == 2'b0) ? + (guard__h350516 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h350515 == 2'b01 || guard__h350515 == 2'b10 || - guard__h350515 == 2'b11) && + (guard__h350516 == 2'b01 || guard__h350516 == 2'b10 || + guard__h350516 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = @@ -34108,86 +34213,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376990 or - _theResult___snd__h385013 or - out_sfd__h385538 or _theResult___sfd__h385535) - begin - case (guard__h376990) - 2'b0, 2'b01: - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q55 = - _theResult___snd__h385013[56:34]; - 2'b10: - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q55 = - out_sfd__h385538; - 2'b11: - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q55 = - _theResult___sfd__h385535; - endcase - end - always@(guard__h376990 or - _theResult___snd__h385013 or _theResult___sfd__h385535) - begin - case (guard__h376990) - 2'b0: - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q56 = - _theResult___snd__h385013[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q56 = - _theResult___sfd__h385535; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q55 or - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q56 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124 or - _theResult___snd__h385013) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h385613 = - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q55; - 3'd1: - _theResult___fst_sfd__h385613 = - CASE_guard76990_0b0_theResult___snd85013_BITS__ETC__q56; - 3'd2: - _theResult___fst_sfd__h385613 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122; - 3'd3: - _theResult___fst_sfd__h385613 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124; - 3'd4: _theResult___fst_sfd__h385613 = _theResult___snd__h385013[56:34]; - default: _theResult___fst_sfd__h385613 = 23'd0; - endcase - end - always@(guard__h350515 or + always@(guard__h350516 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350515) + case (guard__h350516) 2'b0, 2'b01, 2'b10: - CASE_guard50515_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard50516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50515_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = - guard__h350515 != 2'b11 || + CASE_guard50516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + guard__h350516 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50515_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or - guard__h350515) + CASE_guard50516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or + guard__h350516) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - CASE_guard50515_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + CASE_guard50516_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - (guard__h350515 == 2'b0) ? + (guard__h350516 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h350515 != 2'b01 && guard__h350515 != 2'b10 && - guard__h350515 != 2'b11 || + guard__h350516 != 2'b01 && guard__h350516 != 2'b10 && + guard__h350516 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = @@ -34198,34 +34251,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359224 or + always@(guard__h359225 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359224) + case (guard__h359225) 2'b0, 2'b01, 2'b10: - CASE_guard59224_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = + CASE_guard59225_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59224_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = - guard__h359224 == 2'b11 && + CASE_guard59225_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = + guard__h359225 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59224_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 or - guard__h359224) + CASE_guard59225_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 or + guard__h359225) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 = - CASE_guard59224_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58; + CASE_guard59225_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 = - (guard__h359224 == 2'b0) ? + (guard__h359225 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h359224 == 2'b01 || guard__h359224 == 2'b10 || - guard__h359224 == 2'b11) && + (guard__h359225 == 2'b01 || guard__h359225 == 2'b10 || + guard__h359225 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 = @@ -34236,34 +34289,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359224 or + always@(guard__h359225 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359224) + case (guard__h359225) 2'b0, 2'b01, 2'b10: - CASE_guard59224_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = + CASE_guard59225_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59224_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = - guard__h359224 != 2'b11 || + CASE_guard59225_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = + guard__h359225 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59224_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 or - guard__h359224) + CASE_guard59225_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 or + guard__h359225) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 = - CASE_guard59224_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59; + CASE_guard59225_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 = - (guard__h359224 == 2'b0) ? + (guard__h359225 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h359224 != 2'b01 && guard__h359224 != 2'b10 && - guard__h359224 != 2'b11 || + guard__h359225 != 2'b01 && guard__h359225 != 2'b10 && + guard__h359225 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 = @@ -34274,34 +34327,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368154 or + always@(guard__h368155 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368154) + case (guard__h368155) 2'b0, 2'b01, 2'b10: - CASE_guard68154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = + CASE_guard68155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = - guard__h368154 == 2'b11 && + CASE_guard68155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = + guard__h368155 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 or - guard__h368154) + CASE_guard68155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 or + guard__h368155) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227 = - CASE_guard68154_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60; + CASE_guard68155_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227 = - (guard__h368154 == 2'b0) ? + (guard__h368155 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h368154 == 2'b01 || guard__h368154 == 2'b10 || - guard__h368154 == 2'b11) && + (guard__h368155 == 2'b01 || guard__h368155 == 2'b10 || + guard__h368155 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227 = @@ -34312,34 +34365,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368154 or + always@(guard__h368155 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368154) + case (guard__h368155) 2'b0, 2'b01, 2'b10: - CASE_guard68154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = + CASE_guard68155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = - guard__h368154 != 2'b11 || + CASE_guard68155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = + guard__h368155 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 or - guard__h368154) + CASE_guard68155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 or + guard__h368155) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = - CASE_guard68154_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61; + CASE_guard68155_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = - (guard__h368154 == 2'b0) ? + (guard__h368155 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h368154 != 2'b01 && guard__h368154 != 2'b10 && - guard__h368154 != 2'b11 || + guard__h368155 != 2'b01 && guard__h368155 != 2'b10 && + guard__h368155 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = @@ -34350,34 +34403,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376990 or + always@(guard__h376991 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h376990) + case (guard__h376991) 2'b0, 2'b01, 2'b10: - CASE_guard76990_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = + CASE_guard76991_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76990_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = - guard__h376990 == 2'b11 && + CASE_guard76991_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = + guard__h376991 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76990_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 or - guard__h376990) + CASE_guard76991_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 or + guard__h376991) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - CASE_guard76990_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62; + CASE_guard76991_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - (guard__h376990 == 2'b0) ? + (guard__h376991 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h376990 == 2'b01 || guard__h376990 == 2'b10 || - guard__h376990 == 2'b11) && + (guard__h376991 == 2'b01 || guard__h376991 == 2'b10 || + guard__h376991 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = @@ -34388,34 +34441,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376990 or + always@(guard__h376991 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h376990) + case (guard__h376991) 2'b0, 2'b01, 2'b10: - CASE_guard76990_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = + CASE_guard76991_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76990_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = - guard__h376990 != 2'b11 || + CASE_guard76991_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = + guard__h376991 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76990_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 or - guard__h376990) + CASE_guard76991_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 or + guard__h376991) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197 = - CASE_guard76990_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63; + CASE_guard76991_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197 = - (guard__h376990 == 2'b0) ? + (guard__h376991 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h376990 != 2'b01 && guard__h376990 != 2'b10 && - guard__h376990 != 2'b11 || + guard__h376991 != 2'b01 && guard__h376991 != 2'b10 && + guard__h376991 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197 = @@ -34452,394 +34505,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h404921 or - _theResult___fst_exp__h412969 or - out_exp__h413414 or _theResult___exp__h413411) + always@(guard__h404922 or + _theResult___fst_exp__h412970 or + out_exp__h413415 or _theResult___exp__h413412) begin - case (guard__h404921) + case (guard__h404922) 2'b0, 2'b01: - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q68 = - _theResult___fst_exp__h412969; + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q68 = + _theResult___fst_exp__h412970; 2'b10: - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q68 = - out_exp__h413414; + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q68 = + out_exp__h413415; 2'b11: - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q68 = - _theResult___exp__h413411; + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q68 = + _theResult___exp__h413412; endcase end - always@(guard__h404921 or - _theResult___fst_exp__h412969 or _theResult___exp__h413411) + always@(guard__h404922 or + _theResult___fst_exp__h412970 or _theResult___exp__h413412) begin - case (guard__h404921) + case (guard__h404922) 2'b0: - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q69 = - _theResult___fst_exp__h412969; + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q69 = + _theResult___fst_exp__h412970; 2'b01, 2'b10, 2'b11: - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q69 = - _theResult___exp__h413411; + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q69 = + _theResult___exp__h413412; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q68 or - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q69 or + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q68 or + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q69 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6024 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6026 or - _theResult___fst_exp__h412969) + _theResult___fst_exp__h412970) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h413489 = - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q68; + _theResult___fst_exp__h413490 = + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q68; 3'd1: - _theResult___fst_exp__h413489 = - CASE_guard04921_0b0_theResult___fst_exp12969_0_ETC__q69; + _theResult___fst_exp__h413490 = + CASE_guard04922_0b0_theResult___fst_exp12970_0_ETC__q69; 3'd2: - _theResult___fst_exp__h413489 = + _theResult___fst_exp__h413490 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6024; 3'd3: - _theResult___fst_exp__h413489 = + _theResult___fst_exp__h413490 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6026; - 3'd4: _theResult___fst_exp__h413489 = _theResult___fst_exp__h412969; - default: _theResult___fst_exp__h413489 = 8'd0; + 3'd4: _theResult___fst_exp__h413490 = _theResult___fst_exp__h412970; + default: _theResult___fst_exp__h413490 = 8'd0; endcase end - always@(guard__h396214 or - _theResult___fst_exp__h404313 or - out_exp__h404832 or _theResult___exp__h404829) + always@(guard__h396215 or + _theResult___fst_exp__h404314 or + out_exp__h404833 or _theResult___exp__h404830) begin - case (guard__h396214) + case (guard__h396215) 2'b0, 2'b01: - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q70 = - _theResult___fst_exp__h404313; + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q70 = + _theResult___fst_exp__h404314; 2'b10: - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q70 = - out_exp__h404832; + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q70 = + out_exp__h404833; 2'b11: - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q70 = - _theResult___exp__h404829; + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q70 = + _theResult___exp__h404830; endcase end - always@(guard__h396214 or - _theResult___fst_exp__h404313 or _theResult___exp__h404829) + always@(guard__h396215 or + _theResult___fst_exp__h404314 or _theResult___exp__h404830) begin - case (guard__h396214) + case (guard__h396215) 2'b0: - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q71 = - _theResult___fst_exp__h404313; + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q71 = + _theResult___fst_exp__h404314; 2'b01, 2'b10, 2'b11: - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q71 = - _theResult___exp__h404829; + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q71 = + _theResult___exp__h404830; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q70 or - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q71 or + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q70 or + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q71 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5805 or - _theResult___fst_exp__h404313) + _theResult___fst_exp__h404314) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h404907 = - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q70; + _theResult___fst_exp__h404908 = + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q70; 3'd1: - _theResult___fst_exp__h404907 = - CASE_guard96214_0b0_theResult___fst_exp04313_0_ETC__q71; + _theResult___fst_exp__h404908 = + CASE_guard96215_0b0_theResult___fst_exp04314_0_ETC__q71; 3'd2: - _theResult___fst_exp__h404907 = + _theResult___fst_exp__h404908 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802; 3'd3: - _theResult___fst_exp__h404907 = + _theResult___fst_exp__h404908 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5805; - 3'd4: _theResult___fst_exp__h404907 = _theResult___fst_exp__h404313; - default: _theResult___fst_exp__h404907 = 8'd0; + 3'd4: _theResult___fst_exp__h404908 = _theResult___fst_exp__h404314; + default: _theResult___fst_exp__h404908 = 8'd0; endcase end - always@(guard__h413851 or - _theResult___fst_exp__h422079 or - out_exp__h422598 or _theResult___exp__h422595) + always@(guard__h413852 or + _theResult___fst_exp__h422080 or + out_exp__h422599 or _theResult___exp__h422596) begin - case (guard__h413851) + case (guard__h413852) 2'b0, 2'b01: - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q76 = - _theResult___fst_exp__h422079; + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q76 = + _theResult___fst_exp__h422080; 2'b10: - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q76 = - out_exp__h422598; + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q76 = + out_exp__h422599; 2'b11: - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q76 = - _theResult___exp__h422595; + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q76 = + _theResult___exp__h422596; endcase end - always@(guard__h413851 or - _theResult___fst_exp__h422079 or _theResult___exp__h422595) + always@(guard__h413852 or + _theResult___fst_exp__h422080 or _theResult___exp__h422596) begin - case (guard__h413851) + case (guard__h413852) 2'b0: - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q77 = - _theResult___fst_exp__h422079; + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q77 = + _theResult___fst_exp__h422080; 2'b01, 2'b10, 2'b11: - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q77 = - _theResult___exp__h422595; + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q77 = + _theResult___exp__h422596; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q76 or - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q77 or + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q76 or + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q77 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6349 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6351 or - _theResult___fst_exp__h422079) + _theResult___fst_exp__h422080) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h422673 = - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q76; + _theResult___fst_exp__h422674 = + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q76; 3'd1: - _theResult___fst_exp__h422673 = - CASE_guard13851_0b0_theResult___fst_exp22079_0_ETC__q77; + _theResult___fst_exp__h422674 = + CASE_guard13852_0b0_theResult___fst_exp22080_0_ETC__q77; 3'd2: - _theResult___fst_exp__h422673 = + _theResult___fst_exp__h422674 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6349; 3'd3: - _theResult___fst_exp__h422673 = + _theResult___fst_exp__h422674 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6351; - 3'd4: _theResult___fst_exp__h422673 = _theResult___fst_exp__h422079; - default: _theResult___fst_exp__h422673 = 8'd0; + 3'd4: _theResult___fst_exp__h422674 = _theResult___fst_exp__h422080; + default: _theResult___fst_exp__h422674 = 8'd0; endcase end - always@(guard__h422687 or - _theResult___fst_exp__h430764 or - out_exp__h431234 or _theResult___exp__h431231) + always@(guard__h422688 or + _theResult___fst_exp__h430765 or + out_exp__h431235 or _theResult___exp__h431232) begin - case (guard__h422687) + case (guard__h422688) 2'b0, 2'b01: - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q81 = - _theResult___fst_exp__h430764; + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q81 = + _theResult___fst_exp__h430765; 2'b10: - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q81 = - out_exp__h431234; + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q81 = + out_exp__h431235; 2'b11: - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q81 = - _theResult___exp__h431231; + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q81 = + _theResult___exp__h431232; endcase end - always@(guard__h422687 or - _theResult___fst_exp__h430764 or _theResult___exp__h431231) + always@(guard__h422688 or + _theResult___fst_exp__h430765 or _theResult___exp__h431232) begin - case (guard__h422687) + case (guard__h422688) 2'b0: - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q82 = - _theResult___fst_exp__h430764; + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q82 = + _theResult___fst_exp__h430765; 2'b01, 2'b10, 2'b11: - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q82 = - _theResult___exp__h431231; + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q82 = + _theResult___exp__h431232; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q81 or - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q82 or + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q81 or + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q82 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6418 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6420 or - _theResult___fst_exp__h430764) + _theResult___fst_exp__h430765) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h431309 = - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q81; + _theResult___fst_exp__h431310 = + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q81; 3'd1: - _theResult___fst_exp__h431309 = - CASE_guard22687_0b0_theResult___fst_exp30764_0_ETC__q82; + _theResult___fst_exp__h431310 = + CASE_guard22688_0b0_theResult___fst_exp30765_0_ETC__q82; 3'd2: - _theResult___fst_exp__h431309 = + _theResult___fst_exp__h431310 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6418; 3'd3: - _theResult___fst_exp__h431309 = + _theResult___fst_exp__h431310 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6420; - 3'd4: _theResult___fst_exp__h431309 = _theResult___fst_exp__h430764; - default: _theResult___fst_exp__h431309 = 8'd0; + 3'd4: _theResult___fst_exp__h431310 = _theResult___fst_exp__h430765; + default: _theResult___fst_exp__h431310 = 8'd0; endcase end - always@(guard__h404921 or - _theResult___snd__h412920 or - out_sfd__h413415 or _theResult___sfd__h413412) + always@(guard__h404922 or + _theResult___snd__h412921 or + out_sfd__h413416 or _theResult___sfd__h413413) begin - case (guard__h404921) + case (guard__h404922) 2'b0, 2'b01: - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q83 = - _theResult___snd__h412920[56:34]; + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q83 = + _theResult___snd__h412921[56:34]; 2'b10: - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q83 = - out_sfd__h413415; + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q83 = + out_sfd__h413416; 2'b11: - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q83 = - _theResult___sfd__h413412; + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q83 = + _theResult___sfd__h413413; endcase end - always@(guard__h404921 or - _theResult___snd__h412920 or _theResult___sfd__h413412) + always@(guard__h404922 or + _theResult___snd__h412921 or _theResult___sfd__h413413) begin - case (guard__h404921) + case (guard__h404922) 2'b0: - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q84 = - _theResult___snd__h412920[56:34]; + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q84 = + _theResult___snd__h412921[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q84 = - _theResult___sfd__h413412; + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q84 = + _theResult___sfd__h413413; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q83 or - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q84 or + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q83 or + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q84 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6468 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6470 or - _theResult___snd__h412920) + _theResult___snd__h412921) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h413490 = - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q83; + _theResult___fst_sfd__h413491 = + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q83; 3'd1: - _theResult___fst_sfd__h413490 = - CASE_guard04921_0b0_theResult___snd12920_BITS__ETC__q84; + _theResult___fst_sfd__h413491 = + CASE_guard04922_0b0_theResult___snd12921_BITS__ETC__q84; 3'd2: - _theResult___fst_sfd__h413490 = + _theResult___fst_sfd__h413491 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6468; 3'd3: - _theResult___fst_sfd__h413490 = + _theResult___fst_sfd__h413491 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6470; - 3'd4: _theResult___fst_sfd__h413490 = _theResult___snd__h412920[56:34]; - default: _theResult___fst_sfd__h413490 = 23'd0; + 3'd4: _theResult___fst_sfd__h413491 = _theResult___snd__h412921[56:34]; + default: _theResult___fst_sfd__h413491 = 23'd0; endcase end - always@(guard__h396214 or - sfdin__h404307 or out_sfd__h404833 or _theResult___sfd__h404830) + always@(guard__h396215 or + sfdin__h404308 or out_sfd__h404834 or _theResult___sfd__h404831) begin - case (guard__h396214) + case (guard__h396215) 2'b0, 2'b01: - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q85 = - sfdin__h404307[56:34]; + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q85 = + sfdin__h404308[56:34]; 2'b10: - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q85 = - out_sfd__h404833; + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q85 = + out_sfd__h404834; 2'b11: - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q85 = - _theResult___sfd__h404830; + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h404831; endcase end - always@(guard__h396214 or sfdin__h404307 or _theResult___sfd__h404830) + always@(guard__h396215 or sfdin__h404308 or _theResult___sfd__h404831) begin - case (guard__h396214) + case (guard__h396215) 2'b0: - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q86 = - sfdin__h404307[56:34]; + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q86 = + sfdin__h404308[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h404830; + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h404831; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q85 or - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q86 or + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q85 or + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q86 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6451 or - sfdin__h404307) + sfdin__h404308) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h404908 = - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q85; + _theResult___fst_sfd__h404909 = + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q85; 3'd1: - _theResult___fst_sfd__h404908 = - CASE_guard96214_0b0_sfdin04307_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h404909 = + CASE_guard96215_0b0_sfdin04308_BITS_56_TO_34_0_ETC__q86; 3'd2: - _theResult___fst_sfd__h404908 = + _theResult___fst_sfd__h404909 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449; 3'd3: - _theResult___fst_sfd__h404908 = + _theResult___fst_sfd__h404909 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6451; - 3'd4: _theResult___fst_sfd__h404908 = sfdin__h404307[56:34]; - default: _theResult___fst_sfd__h404908 = 23'd0; + 3'd4: _theResult___fst_sfd__h404909 = sfdin__h404308[56:34]; + default: _theResult___fst_sfd__h404909 = 23'd0; endcase end - always@(guard__h413851 or - sfdin__h422073 or out_sfd__h422599 or _theResult___sfd__h422596) + always@(guard__h413852 or + sfdin__h422074 or out_sfd__h422600 or _theResult___sfd__h422597) begin - case (guard__h413851) + case (guard__h413852) 2'b0, 2'b01: - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q87 = - sfdin__h422073[56:34]; + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q87 = + sfdin__h422074[56:34]; 2'b10: - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q87 = - out_sfd__h422599; + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q87 = + out_sfd__h422600; 2'b11: - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h422596; + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h422597; endcase end - always@(guard__h413851 or sfdin__h422073 or _theResult___sfd__h422596) + always@(guard__h413852 or sfdin__h422074 or _theResult___sfd__h422597) begin - case (guard__h413851) + case (guard__h413852) 2'b0: - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q88 = - sfdin__h422073[56:34]; + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q88 = + sfdin__h422074[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q88 = - _theResult___sfd__h422596; + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q88 = + _theResult___sfd__h422597; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q87 or - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q88 or + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q87 or + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q88 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6495 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6497 or - sfdin__h422073) + sfdin__h422074) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h422674 = - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h422675 = + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q87; 3'd1: - _theResult___fst_sfd__h422674 = - CASE_guard13851_0b0_sfdin22073_BITS_56_TO_34_0_ETC__q88; + _theResult___fst_sfd__h422675 = + CASE_guard13852_0b0_sfdin22074_BITS_56_TO_34_0_ETC__q88; 3'd2: - _theResult___fst_sfd__h422674 = + _theResult___fst_sfd__h422675 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6495; 3'd3: - _theResult___fst_sfd__h422674 = + _theResult___fst_sfd__h422675 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6497; - 3'd4: _theResult___fst_sfd__h422674 = sfdin__h422073[56:34]; - default: _theResult___fst_sfd__h422674 = 23'd0; + 3'd4: _theResult___fst_sfd__h422675 = sfdin__h422074[56:34]; + default: _theResult___fst_sfd__h422675 = 23'd0; endcase end - always@(guard__h396214 or + always@(guard__h422688 or + _theResult___snd__h430711 or + out_sfd__h431236 or _theResult___sfd__h431233) + begin + case (guard__h422688) + 2'b0, 2'b01: + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q89 = + _theResult___snd__h430711[56:34]; + 2'b10: + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q89 = + out_sfd__h431236; + 2'b11: + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q89 = + _theResult___sfd__h431233; + endcase + end + always@(guard__h422688 or + _theResult___snd__h430711 or _theResult___sfd__h431233) + begin + case (guard__h422688) + 2'b0: + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q90 = + _theResult___snd__h430711[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q90 = + _theResult___sfd__h431233; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q89 or + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q90 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516 or + _theResult___snd__h430711) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h431311 = + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q89; + 3'd1: + _theResult___fst_sfd__h431311 = + CASE_guard22688_0b0_theResult___snd30711_BITS__ETC__q90; + 3'd2: + _theResult___fst_sfd__h431311 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514; + 3'd3: + _theResult___fst_sfd__h431311 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516; + 3'd4: _theResult___fst_sfd__h431311 = _theResult___snd__h430711[56:34]; + default: _theResult___fst_sfd__h431311 = 23'd0; + endcase + end + always@(guard__h396215 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396214) + case (guard__h396215) 2'b0, 2'b01, 2'b10: - CASE_guard96214_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + CASE_guard96215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96214_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = - guard__h396214 == 2'b11 && + CASE_guard96215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = + guard__h396215 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96214_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or - guard__h396214) + CASE_guard96215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or + guard__h396215) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = - CASE_guard96214_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; + CASE_guard96215_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = - (guard__h396214 == 2'b0) ? + (guard__h396215 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h396214 == 2'b01 || guard__h396214 == 2'b10 || - guard__h396214 == 2'b11) && + (guard__h396215 == 2'b01 || guard__h396215 == 2'b10 || + guard__h396215 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = @@ -34850,86 +34955,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422687 or - _theResult___snd__h430710 or - out_sfd__h431235 or _theResult___sfd__h431232) - begin - case (guard__h422687) - 2'b0, 2'b01: - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q90 = - _theResult___snd__h430710[56:34]; - 2'b10: - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q90 = - out_sfd__h431235; - 2'b11: - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q90 = - _theResult___sfd__h431232; - endcase - end - always@(guard__h422687 or - _theResult___snd__h430710 or _theResult___sfd__h431232) - begin - case (guard__h422687) - 2'b0: - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q91 = - _theResult___snd__h430710[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q91 = - _theResult___sfd__h431232; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q90 or - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q91 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516 or - _theResult___snd__h430710) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h431310 = - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q90; - 3'd1: - _theResult___fst_sfd__h431310 = - CASE_guard22687_0b0_theResult___snd30710_BITS__ETC__q91; - 3'd2: - _theResult___fst_sfd__h431310 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514; - 3'd3: - _theResult___fst_sfd__h431310 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516; - 3'd4: _theResult___fst_sfd__h431310 = _theResult___snd__h430710[56:34]; - default: _theResult___fst_sfd__h431310 = 23'd0; - endcase - end - always@(guard__h396214 or + always@(guard__h396215 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396214) + case (guard__h396215) 2'b0, 2'b01, 2'b10: - CASE_guard96214_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + CASE_guard96215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96214_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = - guard__h396214 != 2'b11 || + CASE_guard96215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + guard__h396215 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96214_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or - guard__h396214) + CASE_guard96215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or + guard__h396215) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - CASE_guard96214_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; + CASE_guard96215_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - (guard__h396214 == 2'b0) ? + (guard__h396215 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h396214 != 2'b01 && guard__h396214 != 2'b10 && - guard__h396214 != 2'b11 || + guard__h396215 != 2'b01 && guard__h396215 != 2'b10 && + guard__h396215 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = @@ -34940,34 +34993,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h404921 or + always@(guard__h404922 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h404921) + case (guard__h404922) 2'b0, 2'b01, 2'b10: - CASE_guard04921_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = + CASE_guard04922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard04921_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = - guard__h404921 == 2'b11 && + CASE_guard04922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = + guard__h404922 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard04921_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 or - guard__h404921) + CASE_guard04922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 or + guard__h404922) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 = - CASE_guard04921_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93; + CASE_guard04922_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 = - (guard__h404921 == 2'b0) ? + (guard__h404922 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h404921 == 2'b01 || guard__h404921 == 2'b10 || - guard__h404921 == 2'b11) && + (guard__h404922 == 2'b01 || guard__h404922 == 2'b10 || + guard__h404922 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 = @@ -34978,34 +35031,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h404921 or + always@(guard__h404922 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h404921) + case (guard__h404922) 2'b0, 2'b01, 2'b10: - CASE_guard04921_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = + CASE_guard04922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard04921_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = - guard__h404921 != 2'b11 || + CASE_guard04922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = + guard__h404922 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard04921_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 or - guard__h404921) + CASE_guard04922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 or + guard__h404922) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 = - CASE_guard04921_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94; + CASE_guard04922_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 = - (guard__h404921 == 2'b0) ? + (guard__h404922 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h404921 != 2'b01 && guard__h404921 != 2'b10 && - guard__h404921 != 2'b11 || + guard__h404922 != 2'b01 && guard__h404922 != 2'b10 && + guard__h404922 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 = @@ -35016,34 +35069,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h413851 or + always@(guard__h413852 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h413851) + case (guard__h413852) 2'b0, 2'b01, 2'b10: - CASE_guard13851_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = + CASE_guard13852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard13851_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = - guard__h413851 == 2'b11 && + CASE_guard13852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = + guard__h413852 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard13851_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 or - guard__h413851) + CASE_guard13852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 or + guard__h413852) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619 = - CASE_guard13851_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95; + CASE_guard13852_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619 = - (guard__h413851 == 2'b0) ? + (guard__h413852 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h413851 == 2'b01 || guard__h413851 == 2'b10 || - guard__h413851 == 2'b11) && + (guard__h413852 == 2'b01 || guard__h413852 == 2'b10 || + guard__h413852 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619 = @@ -35054,34 +35107,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h413851 or + always@(guard__h413852 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h413851) + case (guard__h413852) 2'b0, 2'b01, 2'b10: - CASE_guard13851_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = + CASE_guard13852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard13851_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - guard__h413851 != 2'b11 || + CASE_guard13852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = + guard__h413852 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard13851_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or - guard__h413851) + CASE_guard13852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or + guard__h413852) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576 = - CASE_guard13851_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; + CASE_guard13852_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576 = - (guard__h413851 == 2'b0) ? + (guard__h413852 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h413851 != 2'b01 && guard__h413851 != 2'b10 && - guard__h413851 != 2'b11 || + guard__h413852 != 2'b01 && guard__h413852 != 2'b10 && + guard__h413852 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576 = @@ -35092,34 +35145,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422687 or + always@(guard__h422688 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422687) + case (guard__h422688) 2'b0, 2'b01, 2'b10: - CASE_guard22687_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard22688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22687_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = - guard__h422687 == 2'b11 && + CASE_guard22688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + guard__h422688 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22687_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or - guard__h422687) + CASE_guard22688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or + guard__h422688) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626 = - CASE_guard22687_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; + CASE_guard22688_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626 = - (guard__h422687 == 2'b0) ? + (guard__h422688 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h422687 == 2'b01 || guard__h422687 == 2'b10 || - guard__h422687 == 2'b11) && + (guard__h422688 == 2'b01 || guard__h422688 == 2'b10 || + guard__h422688 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626 = @@ -35130,34 +35183,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422687 or + always@(guard__h422688 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422687) + case (guard__h422688) 2'b0, 2'b01, 2'b10: - CASE_guard22687_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = + CASE_guard22688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22687_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = - guard__h422687 != 2'b11 || + CASE_guard22688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = + guard__h422688 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22687_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 or - guard__h422687) + CASE_guard22688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 or + guard__h422688) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589 = - CASE_guard22687_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98; + CASE_guard22688_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589 = - (guard__h422687 == 2'b0) ? + (guard__h422688 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h422687 != 2'b01 && guard__h422687 != 2'b10 && - guard__h422687 != 2'b11 || + guard__h422688 != 2'b01 && guard__h422688 != 2'b10 && + guard__h422688 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589 = @@ -35194,446 +35247,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h450616 or - _theResult___fst_exp__h458664 or - out_exp__h459109 or _theResult___exp__h459106) + always@(guard__h450617 or + _theResult___fst_exp__h458665 or + out_exp__h459110 or _theResult___exp__h459107) begin - case (guard__h450616) + case (guard__h450617) 2'b0, 2'b01: - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q103 = - _theResult___fst_exp__h458664; + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q103 = + _theResult___fst_exp__h458665; 2'b10: - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q103 = - out_exp__h459109; + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q103 = + out_exp__h459110; 2'b11: - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q103 = - _theResult___exp__h459106; + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q103 = + _theResult___exp__h459107; endcase end - always@(guard__h450616 or - _theResult___fst_exp__h458664 or _theResult___exp__h459106) + always@(guard__h450617 or + _theResult___fst_exp__h458665 or _theResult___exp__h459107) begin - case (guard__h450616) + case (guard__h450617) 2'b0: - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q104 = - _theResult___fst_exp__h458664; + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q104 = + _theResult___fst_exp__h458665; 2'b01, 2'b10, 2'b11: - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q104 = - _theResult___exp__h459106; + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q104 = + _theResult___exp__h459107; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q103 or - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q104 or + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q103 or + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q104 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7416 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7418 or - _theResult___fst_exp__h458664) + _theResult___fst_exp__h458665) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h459184 = - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q103; + _theResult___fst_exp__h459185 = + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q103; 3'd1: - _theResult___fst_exp__h459184 = - CASE_guard50616_0b0_theResult___fst_exp58664_0_ETC__q104; + _theResult___fst_exp__h459185 = + CASE_guard50617_0b0_theResult___fst_exp58665_0_ETC__q104; 3'd2: - _theResult___fst_exp__h459184 = + _theResult___fst_exp__h459185 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7416; 3'd3: - _theResult___fst_exp__h459184 = + _theResult___fst_exp__h459185 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7418; - 3'd4: _theResult___fst_exp__h459184 = _theResult___fst_exp__h458664; - default: _theResult___fst_exp__h459184 = 8'd0; + 3'd4: _theResult___fst_exp__h459185 = _theResult___fst_exp__h458665; + default: _theResult___fst_exp__h459185 = 8'd0; endcase end - always@(guard__h441909 or - _theResult___fst_exp__h450008 or - out_exp__h450527 or _theResult___exp__h450524) + always@(guard__h441910 or + _theResult___fst_exp__h450009 or + out_exp__h450528 or _theResult___exp__h450525) begin - case (guard__h441909) + case (guard__h441910) 2'b0, 2'b01: - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q105 = - _theResult___fst_exp__h450008; + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q105 = + _theResult___fst_exp__h450009; 2'b10: - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q105 = - out_exp__h450527; + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q105 = + out_exp__h450528; 2'b11: - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q105 = - _theResult___exp__h450524; + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q105 = + _theResult___exp__h450525; endcase end - always@(guard__h441909 or - _theResult___fst_exp__h450008 or _theResult___exp__h450524) + always@(guard__h441910 or + _theResult___fst_exp__h450009 or _theResult___exp__h450525) begin - case (guard__h441909) + case (guard__h441910) 2'b0: - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q106 = - _theResult___fst_exp__h450008; + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q106 = + _theResult___fst_exp__h450009; 2'b01, 2'b10, 2'b11: - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q106 = - _theResult___exp__h450524; + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q106 = + _theResult___exp__h450525; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q105 or - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q106 or + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q105 or + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q106 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7197 or - _theResult___fst_exp__h450008) + _theResult___fst_exp__h450009) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h450602 = - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q105; + _theResult___fst_exp__h450603 = + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q105; 3'd1: - _theResult___fst_exp__h450602 = - CASE_guard41909_0b0_theResult___fst_exp50008_0_ETC__q106; + _theResult___fst_exp__h450603 = + CASE_guard41910_0b0_theResult___fst_exp50009_0_ETC__q106; 3'd2: - _theResult___fst_exp__h450602 = + _theResult___fst_exp__h450603 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194; 3'd3: - _theResult___fst_exp__h450602 = + _theResult___fst_exp__h450603 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7197; - 3'd4: _theResult___fst_exp__h450602 = _theResult___fst_exp__h450008; - default: _theResult___fst_exp__h450602 = 8'd0; + 3'd4: _theResult___fst_exp__h450603 = _theResult___fst_exp__h450009; + default: _theResult___fst_exp__h450603 = 8'd0; endcase end - always@(guard__h459546 or - _theResult___fst_exp__h467774 or - out_exp__h468293 or _theResult___exp__h468290) + always@(guard__h459547 or + _theResult___fst_exp__h467775 or + out_exp__h468294 or _theResult___exp__h468291) begin - case (guard__h459546) + case (guard__h459547) 2'b0, 2'b01: - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q111 = - _theResult___fst_exp__h467774; + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q111 = + _theResult___fst_exp__h467775; 2'b10: - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q111 = - out_exp__h468293; + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q111 = + out_exp__h468294; 2'b11: - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q111 = - _theResult___exp__h468290; + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q111 = + _theResult___exp__h468291; endcase end - always@(guard__h459546 or - _theResult___fst_exp__h467774 or _theResult___exp__h468290) + always@(guard__h459547 or + _theResult___fst_exp__h467775 or _theResult___exp__h468291) begin - case (guard__h459546) + case (guard__h459547) 2'b0: - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q112 = - _theResult___fst_exp__h467774; + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q112 = + _theResult___fst_exp__h467775; 2'b01, 2'b10, 2'b11: - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q112 = - _theResult___exp__h468290; + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q112 = + _theResult___exp__h468291; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q111 or - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q112 or + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q111 or + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q112 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7741 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7743 or - _theResult___fst_exp__h467774) + _theResult___fst_exp__h467775) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h468368 = - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q111; + _theResult___fst_exp__h468369 = + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q111; 3'd1: - _theResult___fst_exp__h468368 = - CASE_guard59546_0b0_theResult___fst_exp67774_0_ETC__q112; + _theResult___fst_exp__h468369 = + CASE_guard59547_0b0_theResult___fst_exp67775_0_ETC__q112; 3'd2: - _theResult___fst_exp__h468368 = + _theResult___fst_exp__h468369 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7741; 3'd3: - _theResult___fst_exp__h468368 = + _theResult___fst_exp__h468369 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7743; - 3'd4: _theResult___fst_exp__h468368 = _theResult___fst_exp__h467774; - default: _theResult___fst_exp__h468368 = 8'd0; + 3'd4: _theResult___fst_exp__h468369 = _theResult___fst_exp__h467775; + default: _theResult___fst_exp__h468369 = 8'd0; endcase end - always@(guard__h468382 or - _theResult___fst_exp__h476459 or - out_exp__h476929 or _theResult___exp__h476926) + always@(guard__h468383 or + _theResult___fst_exp__h476460 or + out_exp__h476930 or _theResult___exp__h476927) begin - case (guard__h468382) + case (guard__h468383) 2'b0, 2'b01: - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q116 = - _theResult___fst_exp__h476459; + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q116 = + _theResult___fst_exp__h476460; 2'b10: - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q116 = - out_exp__h476929; + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q116 = + out_exp__h476930; 2'b11: - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q116 = - _theResult___exp__h476926; + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q116 = + _theResult___exp__h476927; endcase end - always@(guard__h468382 or - _theResult___fst_exp__h476459 or _theResult___exp__h476926) + always@(guard__h468383 or + _theResult___fst_exp__h476460 or _theResult___exp__h476927) begin - case (guard__h468382) + case (guard__h468383) 2'b0: - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q117 = - _theResult___fst_exp__h476459; + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q117 = + _theResult___fst_exp__h476460; 2'b01, 2'b10, 2'b11: - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q117 = - _theResult___exp__h476926; + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q117 = + _theResult___exp__h476927; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q116 or - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q117 or + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q116 or + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q117 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7810 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7812 or - _theResult___fst_exp__h476459) + _theResult___fst_exp__h476460) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h477004 = - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q116; + _theResult___fst_exp__h477005 = + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q116; 3'd1: - _theResult___fst_exp__h477004 = - CASE_guard68382_0b0_theResult___fst_exp76459_0_ETC__q117; + _theResult___fst_exp__h477005 = + CASE_guard68383_0b0_theResult___fst_exp76460_0_ETC__q117; 3'd2: - _theResult___fst_exp__h477004 = + _theResult___fst_exp__h477005 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7810; 3'd3: - _theResult___fst_exp__h477004 = + _theResult___fst_exp__h477005 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7812; - 3'd4: _theResult___fst_exp__h477004 = _theResult___fst_exp__h476459; - default: _theResult___fst_exp__h477004 = 8'd0; + 3'd4: _theResult___fst_exp__h477005 = _theResult___fst_exp__h476460; + default: _theResult___fst_exp__h477005 = 8'd0; endcase end - always@(guard__h450616 or - _theResult___snd__h458615 or - out_sfd__h459110 or _theResult___sfd__h459107) + always@(guard__h450617 or + _theResult___snd__h458616 or + out_sfd__h459111 or _theResult___sfd__h459108) begin - case (guard__h450616) + case (guard__h450617) 2'b0, 2'b01: - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q118 = - _theResult___snd__h458615[56:34]; + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q118 = + _theResult___snd__h458616[56:34]; 2'b10: - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q118 = - out_sfd__h459110; + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q118 = + out_sfd__h459111; 2'b11: - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q118 = - _theResult___sfd__h459107; + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q118 = + _theResult___sfd__h459108; endcase end - always@(guard__h450616 or - _theResult___snd__h458615 or _theResult___sfd__h459107) + always@(guard__h450617 or + _theResult___snd__h458616 or _theResult___sfd__h459108) begin - case (guard__h450616) + case (guard__h450617) 2'b0: - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q119 = - _theResult___snd__h458615[56:34]; + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q119 = + _theResult___snd__h458616[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q119 = - _theResult___sfd__h459107; + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q119 = + _theResult___sfd__h459108; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q118 or - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q119 or + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q118 or + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q119 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 or - _theResult___snd__h458615) + _theResult___snd__h458616) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h459185 = - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q118; + _theResult___fst_sfd__h459186 = + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q118; 3'd1: - _theResult___fst_sfd__h459185 = - CASE_guard50616_0b0_theResult___snd58615_BITS__ETC__q119; + _theResult___fst_sfd__h459186 = + CASE_guard50617_0b0_theResult___snd58616_BITS__ETC__q119; 3'd2: - _theResult___fst_sfd__h459185 = + _theResult___fst_sfd__h459186 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860; 3'd3: - _theResult___fst_sfd__h459185 = + _theResult___fst_sfd__h459186 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862; - 3'd4: _theResult___fst_sfd__h459185 = _theResult___snd__h458615[56:34]; - default: _theResult___fst_sfd__h459185 = 23'd0; + 3'd4: _theResult___fst_sfd__h459186 = _theResult___snd__h458616[56:34]; + default: _theResult___fst_sfd__h459186 = 23'd0; endcase end - always@(guard__h441909 or - sfdin__h450002 or out_sfd__h450528 or _theResult___sfd__h450525) + always@(guard__h441910 or + sfdin__h450003 or out_sfd__h450529 or _theResult___sfd__h450526) begin - case (guard__h441909) + case (guard__h441910) 2'b0, 2'b01: - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q120 = - sfdin__h450002[56:34]; + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q120 = + sfdin__h450003[56:34]; 2'b10: - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q120 = - out_sfd__h450528; + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q120 = + out_sfd__h450529; 2'b11: - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h450525; + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h450526; endcase end - always@(guard__h441909 or sfdin__h450002 or _theResult___sfd__h450525) + always@(guard__h441910 or sfdin__h450003 or _theResult___sfd__h450526) begin - case (guard__h441909) + case (guard__h441910) 2'b0: - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q121 = - sfdin__h450002[56:34]; + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q121 = + sfdin__h450003[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h450525; + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h450526; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q120 or - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q121 or + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q120 or + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q121 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843 or - sfdin__h450002) + sfdin__h450003) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h450603 = - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h450604 = + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q120; 3'd1: - _theResult___fst_sfd__h450603 = - CASE_guard41909_0b0_sfdin50002_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h450604 = + CASE_guard41910_0b0_sfdin50003_BITS_56_TO_34_0_ETC__q121; 3'd2: - _theResult___fst_sfd__h450603 = + _theResult___fst_sfd__h450604 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841; 3'd3: - _theResult___fst_sfd__h450603 = + _theResult___fst_sfd__h450604 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843; - 3'd4: _theResult___fst_sfd__h450603 = sfdin__h450002[56:34]; - default: _theResult___fst_sfd__h450603 = 23'd0; + 3'd4: _theResult___fst_sfd__h450604 = sfdin__h450003[56:34]; + default: _theResult___fst_sfd__h450604 = 23'd0; endcase end - always@(guard__h459546 or - sfdin__h467768 or out_sfd__h468294 or _theResult___sfd__h468291) + always@(guard__h459547 or + sfdin__h467769 or out_sfd__h468295 or _theResult___sfd__h468292) begin - case (guard__h459546) + case (guard__h459547) 2'b0, 2'b01: - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q122 = - sfdin__h467768[56:34]; + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q122 = + sfdin__h467769[56:34]; 2'b10: - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q122 = - out_sfd__h468294; + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q122 = + out_sfd__h468295; 2'b11: - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h468291; + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h468292; endcase end - always@(guard__h459546 or sfdin__h467768 or _theResult___sfd__h468291) + always@(guard__h459547 or sfdin__h467769 or _theResult___sfd__h468292) begin - case (guard__h459546) + case (guard__h459547) 2'b0: - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q123 = - sfdin__h467768[56:34]; + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q123 = + sfdin__h467769[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q123 = - _theResult___sfd__h468291; + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q123 = + _theResult___sfd__h468292; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q122 or - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q123 or + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q122 or + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q123 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7887 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7889 or - sfdin__h467768) + sfdin__h467769) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h468369 = - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h468370 = + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q122; 3'd1: - _theResult___fst_sfd__h468369 = - CASE_guard59546_0b0_sfdin67768_BITS_56_TO_34_0_ETC__q123; + _theResult___fst_sfd__h468370 = + CASE_guard59547_0b0_sfdin67769_BITS_56_TO_34_0_ETC__q123; 3'd2: - _theResult___fst_sfd__h468369 = + _theResult___fst_sfd__h468370 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7887; 3'd3: - _theResult___fst_sfd__h468369 = + _theResult___fst_sfd__h468370 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7889; - 3'd4: _theResult___fst_sfd__h468369 = sfdin__h467768[56:34]; - default: _theResult___fst_sfd__h468369 = 23'd0; + 3'd4: _theResult___fst_sfd__h468370 = sfdin__h467769[56:34]; + default: _theResult___fst_sfd__h468370 = 23'd0; endcase end - always@(guard__h468382 or - _theResult___snd__h476405 or - out_sfd__h476930 or _theResult___sfd__h476927) + always@(guard__h468383 or + _theResult___snd__h476406 or + out_sfd__h476931 or _theResult___sfd__h476928) begin - case (guard__h468382) + case (guard__h468383) 2'b0, 2'b01: - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q124 = - _theResult___snd__h476405[56:34]; + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q124 = + _theResult___snd__h476406[56:34]; 2'b10: - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q124 = - out_sfd__h476930; + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q124 = + out_sfd__h476931; 2'b11: - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q124 = - _theResult___sfd__h476927; + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q124 = + _theResult___sfd__h476928; endcase end - always@(guard__h468382 or - _theResult___snd__h476405 or _theResult___sfd__h476927) + always@(guard__h468383 or + _theResult___snd__h476406 or _theResult___sfd__h476928) begin - case (guard__h468382) + case (guard__h468383) 2'b0: - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q125 = - _theResult___snd__h476405[56:34]; + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q125 = + _theResult___snd__h476406[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q125 = - _theResult___sfd__h476927; + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q125 = + _theResult___sfd__h476928; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q124 or - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q125 or + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q124 or + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q125 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908 or - _theResult___snd__h476405) + _theResult___snd__h476406) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h477005 = - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q124; + _theResult___fst_sfd__h477006 = + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q124; 3'd1: - _theResult___fst_sfd__h477005 = - CASE_guard68382_0b0_theResult___snd76405_BITS__ETC__q125; + _theResult___fst_sfd__h477006 = + CASE_guard68383_0b0_theResult___snd76406_BITS__ETC__q125; 3'd2: - _theResult___fst_sfd__h477005 = + _theResult___fst_sfd__h477006 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906; 3'd3: - _theResult___fst_sfd__h477005 = + _theResult___fst_sfd__h477006 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908; - 3'd4: _theResult___fst_sfd__h477005 = _theResult___snd__h476405[56:34]; - default: _theResult___fst_sfd__h477005 = 23'd0; + 3'd4: _theResult___fst_sfd__h477006 = _theResult___snd__h476406[56:34]; + default: _theResult___fst_sfd__h477006 = 23'd0; endcase end - always@(guard__h441909 or + always@(guard__h441910 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h441909) + case (guard__h441910) 2'b0, 2'b01, 2'b10: - CASE_guard41909_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + CASE_guard41910_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard41909_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = - guard__h441909 == 2'b11 && + CASE_guard41910_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h441910 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41909_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or - guard__h441909) + CASE_guard41910_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h441910) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = - CASE_guard41909_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; + CASE_guard41910_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = - (guard__h441909 == 2'b0) ? + (guard__h441910 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h441909 == 2'b01 || guard__h441909 == 2'b10 || - guard__h441909 == 2'b11) && + (guard__h441910 == 2'b01 || guard__h441910 == 2'b10 || + guard__h441910 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = @@ -35644,34 +35697,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h441909 or + always@(guard__h441910 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h441909) + case (guard__h441910) 2'b0, 2'b01, 2'b10: - CASE_guard41909_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + CASE_guard41910_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard41909_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = - guard__h441909 != 2'b11 || + CASE_guard41910_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h441910 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41909_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or - guard__h441909) + CASE_guard41910_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h441910) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - CASE_guard41909_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + CASE_guard41910_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - (guard__h441909 == 2'b0) ? + (guard__h441910 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h441909 != 2'b01 && guard__h441909 != 2'b10 && - guard__h441909 != 2'b11 || + guard__h441910 != 2'b01 && guard__h441910 != 2'b10 && + guard__h441910 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = @@ -35682,34 +35735,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h450616 or + always@(guard__h450617 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h450616) + case (guard__h450617) 2'b0, 2'b01, 2'b10: - CASE_guard50616_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + CASE_guard50617_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50616_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = - guard__h450616 == 2'b11 && + CASE_guard50617_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + guard__h450617 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50616_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or - guard__h450616) + CASE_guard50617_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or + guard__h450617) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = - CASE_guard50616_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128; + CASE_guard50617_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = - (guard__h450616 == 2'b0) ? + (guard__h450617 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h450616 == 2'b01 || guard__h450616 == 2'b10 || - guard__h450616 == 2'b11) && + (guard__h450617 == 2'b01 || guard__h450617 == 2'b10 || + guard__h450617 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = @@ -35720,34 +35773,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h450616 or + always@(guard__h450617 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h450616) + case (guard__h450617) 2'b0, 2'b01, 2'b10: - CASE_guard50616_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = + CASE_guard50617_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50616_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = - guard__h450616 != 2'b11 || + CASE_guard50617_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = + guard__h450617 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50616_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 or - guard__h450616) + CASE_guard50617_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 or + guard__h450617) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 = - CASE_guard50616_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129; + CASE_guard50617_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 = - (guard__h450616 == 2'b0) ? + (guard__h450617 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h450616 != 2'b01 && guard__h450616 != 2'b10 && - guard__h450616 != 2'b11 || + guard__h450617 != 2'b01 && guard__h450617 != 2'b10 && + guard__h450617 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 = @@ -35758,34 +35811,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459546 or + always@(guard__h459547 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459546) + case (guard__h459547) 2'b0, 2'b01, 2'b10: - CASE_guard59546_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = + CASE_guard59547_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59546_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = - guard__h459546 == 2'b11 && + CASE_guard59547_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = + guard__h459547 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59546_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or - guard__h459546) + CASE_guard59547_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or + guard__h459547) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011 = - CASE_guard59546_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130; + CASE_guard59547_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011 = - (guard__h459546 == 2'b0) ? + (guard__h459547 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h459546 == 2'b01 || guard__h459546 == 2'b10 || - guard__h459546 == 2'b11) && + (guard__h459547 == 2'b01 || guard__h459547 == 2'b10 || + guard__h459547 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011 = @@ -35796,34 +35849,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459546 or + always@(guard__h459547 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459546) + case (guard__h459547) 2'b0, 2'b01, 2'b10: - CASE_guard59546_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = + CASE_guard59547_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59546_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = - guard__h459546 != 2'b11 || + CASE_guard59547_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = + guard__h459547 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59546_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or - guard__h459546) + CASE_guard59547_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or + guard__h459547) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968 = - CASE_guard59546_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131; + CASE_guard59547_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968 = - (guard__h459546 == 2'b0) ? + (guard__h459547 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h459546 != 2'b01 && guard__h459546 != 2'b10 && - guard__h459546 != 2'b11 || + guard__h459547 != 2'b01 && guard__h459547 != 2'b10 && + guard__h459547 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968 = @@ -35834,34 +35887,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468382 or + always@(guard__h468383 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468382) + case (guard__h468383) 2'b0, 2'b01, 2'b10: - CASE_guard68382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = - guard__h468382 == 2'b11 && + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = + guard__h468383 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 or - guard__h468382) + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 or + guard__h468383) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018 = - CASE_guard68382_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132; + CASE_guard68383_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018 = - (guard__h468382 == 2'b0) ? + (guard__h468383 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h468382 == 2'b01 || guard__h468382 == 2'b10 || - guard__h468382 == 2'b11) && + (guard__h468383 == 2'b01 || guard__h468383 == 2'b10 || + guard__h468383 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018 = @@ -35872,34 +35925,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468382 or + always@(guard__h468383 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468382) + case (guard__h468383) 2'b0, 2'b01, 2'b10: - CASE_guard68382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = - guard__h468382 != 2'b11 || + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = + guard__h468383 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 or - guard__h468382) + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 or + guard__h468383) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981 = - CASE_guard68382_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133; + CASE_guard68383_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981 = - (guard__h468382 == 2'b0) ? + (guard__h468383 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h468382 != 2'b01 && guard__h468382 != 2'b10 && - guard__h468382 != 2'b11 || + guard__h468383 != 2'b01 && guard__h468383 != 2'b10 && + guard__h468383 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981 = @@ -35956,28 +36009,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h498495 or - _theResult___fst_exp__h506456 or _theResult___exp__h507111) + always@(guard__h498496 or + _theResult___fst_exp__h506457 or _theResult___exp__h507112) begin - case (guard__h498495) + case (guard__h498496) 2'b0: - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q143 = - _theResult___fst_exp__h506456; + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q143 = + _theResult___fst_exp__h506457; 2'b01, 2'b10, 2'b11: - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q143 = - _theResult___exp__h507111; + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q143 = + _theResult___exp__h507112; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h506456 or + _theResult___fst_exp__h506457 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9130 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9128 or - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q143) + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = - _theResult___fst_exp__h506456; + _theResult___fst_exp__h506457; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9130; @@ -35986,44 +36039,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9128; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q143; + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = 11'd0; endcase end - always@(guard__h498495 or - _theResult___fst_exp__h506456 or - out_exp__h507114 or _theResult___exp__h507111) + always@(guard__h498496 or + _theResult___fst_exp__h506457 or + out_exp__h507115 or _theResult___exp__h507112) begin - case (guard__h498495) + case (guard__h498496) 2'b0, 2'b01: - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q144 = - _theResult___fst_exp__h506456; + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q144 = + _theResult___fst_exp__h506457; 2'b10: - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q144 = - out_exp__h507114; + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q144 = + out_exp__h507115; 2'b11: - CASE_guard98495_0b0_theResult___fst_exp06456_0_ETC__q144 = - _theResult___exp__h507111; + CASE_guard98496_0b0_theResult___fst_exp06457_0_ETC__q144 = + _theResult___exp__h507112; endcase end - always@(guard__h498495 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h498496 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h498495) + case (guard__h498496) 2'b0, 2'b01, 2'b10: - CASE_guard98495_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard98496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard98495_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h498495 == 2'b11 && + CASE_guard98496_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h498496 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498495) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498496) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36033,12 +36086,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h498495 == 2'b0) ? + (guard__h498496 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h498495 == 2'b01 || guard__h498495 == 2'b10 || - guard__h498495 == 2'b11) && + (guard__h498496 == 2'b01 || guard__h498496 == 2'b10 || + guard__h498496 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -36049,23 +36102,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h507807 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h507808 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h507807) + case (guard__h507808) 2'b0, 2'b01, 2'b10: - CASE_guard07807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard07808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard07807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h507807 == 2'b11 && + CASE_guard07808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h507808 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507807) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507808) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36075,12 +36128,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h507807 == 2'b0) ? + (guard__h507808 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h507807 == 2'b01 || guard__h507807 == 2'b10 || - guard__h507807 == 2'b11) && + (guard__h507808 == 2'b01 || guard__h507808 == 2'b10 || + guard__h507808 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -36091,23 +36144,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h516876 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h516877 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h516876) + case (guard__h516877) 2'b0, 2'b01, 2'b10: - CASE_guard16876_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard16877_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard16876_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h516876 == 2'b11 && + CASE_guard16877_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h516877 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h516876) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h516877) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36117,12 +36170,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h516876 == 2'b0) ? + (guard__h516877 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h516876 == 2'b01 || guard__h516876 == 2'b10 || - guard__h516876 == 2'b11) && + (guard__h516877 == 2'b01 || guard__h516877 == 2'b10 || + guard__h516877 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -36133,28 +36186,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h576652 or - _theResult___fst_exp__h584613 or _theResult___exp__h585268) + always@(guard__h576653 or + _theResult___fst_exp__h584614 or _theResult___exp__h585269) begin - case (guard__h576652) + case (guard__h576653) 2'b0: - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q160 = - _theResult___fst_exp__h584613; + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q160 = + _theResult___fst_exp__h584614; 2'b01, 2'b10, 2'b11: - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q160 = - _theResult___exp__h585268; + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q160 = + _theResult___exp__h585269; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h584613 or + _theResult___fst_exp__h584614 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9845 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9843 or - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q160) + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = - _theResult___fst_exp__h584613; + _theResult___fst_exp__h584614; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9845; @@ -36163,42 +36216,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9843; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q160; + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = 11'd0; endcase end - always@(guard__h576652 or - _theResult___fst_exp__h584613 or - out_exp__h585271 or _theResult___exp__h585268) + always@(guard__h576653 or + _theResult___fst_exp__h584614 or + out_exp__h585272 or _theResult___exp__h585269) begin - case (guard__h576652) + case (guard__h576653) 2'b0, 2'b01: - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q161 = - _theResult___fst_exp__h584613; + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q161 = + _theResult___fst_exp__h584614; 2'b10: - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q161 = - out_exp__h585271; + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q161 = + out_exp__h585272; 2'b11: - CASE_guard76652_0b0_theResult___fst_exp84613_0_ETC__q161 = - _theResult___exp__h585268; + CASE_guard76653_0b0_theResult___fst_exp84614_0_ETC__q161 = + _theResult___exp__h585269; endcase end - always@(guard__h576652 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576653 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576652) + case (guard__h576653) 2'b0, 2'b01, 2'b10: - CASE_guard76652_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard76653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76652_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h576652 == 2'b11 && + CASE_guard76653_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h576653 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576652) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576653) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36207,12 +36260,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h576652 == 2'b0) ? + (guard__h576653 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h576652 == 2'b01 || guard__h576652 == 2'b10 || - guard__h576652 == 2'b11) && + (guard__h576653 == 2'b01 || guard__h576653 == 2'b10 || + guard__h576653 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36223,21 +36276,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595033 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595034 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595033) + case (guard__h595034) 2'b0, 2'b01, 2'b10: - CASE_guard95033_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard95034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95033_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h595033 == 2'b11 && + CASE_guard95034_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h595034 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595033) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595034) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36246,12 +36299,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h595033 == 2'b0) ? + (guard__h595034 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h595033 == 2'b01 || guard__h595033 == 2'b10 || - guard__h595033 == 2'b11) && + (guard__h595034 == 2'b01 || guard__h595034 == 2'b10 || + guard__h595034 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36262,21 +36315,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h585964 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h585965 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h585964) + case (guard__h585965) 2'b0, 2'b01, 2'b10: - CASE_guard85964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard85965_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard85964_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h585964 == 2'b11 && + CASE_guard85965_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h585965 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585964) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585965) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36285,12 +36338,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h585964 == 2'b0) ? + (guard__h585965 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h585964 == 2'b01 || guard__h585964 == 2'b10 || - guard__h585964 == 2'b11) && + (guard__h585965 == 2'b01 || guard__h585965 == 2'b10 || + guard__h585965 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36301,21 +36354,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h585964 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h585965 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h585964) + case (guard__h585965) 2'b0, 2'b01, 2'b10: - CASE_guard85964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard85965_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard85964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h585964 != 2'b11 || + CASE_guard85965_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h585965 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585964) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585965) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36324,12 +36377,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h585964 == 2'b0) ? + (guard__h585965 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h585964 != 2'b01 && guard__h585964 != 2'b10 && - guard__h585964 != 2'b11 || + guard__h585965 != 2'b01 && guard__h585965 != 2'b10 && + guard__h585965 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36340,21 +36393,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595033 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595034 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595033) + case (guard__h595034) 2'b0, 2'b01, 2'b10: - CASE_guard95033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard95034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95033_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h595033 != 2'b11 || + CASE_guard95034_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h595034 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595033) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595034) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36363,12 +36416,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h595033 == 2'b0) ? + (guard__h595034 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595033 != 2'b01 && guard__h595033 != 2'b10 && - guard__h595033 != 2'b11 || + guard__h595034 != 2'b01 && guard__h595034 != 2'b10 && + guard__h595034 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36379,21 +36432,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h576652 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576653 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576652) + case (guard__h576653) 2'b0, 2'b01, 2'b10: - CASE_guard76652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard76653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76652_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h576652 != 2'b11 || + CASE_guard76653_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h576653 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576652) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576653) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36402,12 +36455,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h576652 == 2'b0) ? + (guard__h576653 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h576652 != 2'b01 && guard__h576652 != 2'b10 && - guard__h576652 != 2'b11 || + guard__h576653 != 2'b01 && guard__h576653 != 2'b10 && + guard__h576653 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36418,28 +36471,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h537348 or - _theResult___fst_exp__h545309 or _theResult___exp__h545964) + always@(guard__h537349 or + _theResult___fst_exp__h545310 or _theResult___exp__h545965) begin - case (guard__h537348) + case (guard__h537349) 2'b0: - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q183 = - _theResult___fst_exp__h545309; + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q183 = + _theResult___fst_exp__h545310; 2'b01, 2'b10, 2'b11: - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q183 = - _theResult___exp__h545964; + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q183 = + _theResult___exp__h545965; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h545309 or + _theResult___fst_exp__h545310 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10615 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10613 or - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q183) + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = - _theResult___fst_exp__h545309; + _theResult___fst_exp__h545310; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10615; @@ -36448,49 +36501,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10613; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q183; + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = 11'd0; endcase end - always@(guard__h537348 or - _theResult___fst_exp__h545309 or - out_exp__h545967 or _theResult___exp__h545964) + always@(guard__h537349 or + _theResult___fst_exp__h545310 or + out_exp__h545968 or _theResult___exp__h545965) begin - case (guard__h537348) + case (guard__h537349) 2'b0, 2'b01: - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q184 = - _theResult___fst_exp__h545309; + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q184 = + _theResult___fst_exp__h545310; 2'b10: - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q184 = - out_exp__h545967; + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q184 = + out_exp__h545968; 2'b11: - CASE_guard37348_0b0_theResult___fst_exp45309_0_ETC__q184 = - _theResult___exp__h545964; + CASE_guard37349_0b0_theResult___fst_exp45310_0_ETC__q184 = + _theResult___exp__h545965; endcase end - always@(guard__h546660 or - _theResult___fst_exp__h554886 or _theResult___exp__h555615) + always@(guard__h546661 or + _theResult___fst_exp__h554887 or _theResult___exp__h555616) begin - case (guard__h546660) + case (guard__h546661) 2'b0: - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q185 = - _theResult___fst_exp__h554886; + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q185 = + _theResult___fst_exp__h554887; 2'b01, 2'b10, 2'b11: - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q185 = - _theResult___exp__h555615; + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q185 = + _theResult___exp__h555616; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h554886 or + _theResult___fst_exp__h554887 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651 or - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q185) + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = - _theResult___fst_exp__h554886; + _theResult___fst_exp__h554887; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653; @@ -36499,49 +36552,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q185; + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = 11'd0; endcase end - always@(guard__h546660 or - _theResult___fst_exp__h554886 or - out_exp__h555618 or _theResult___exp__h555615) + always@(guard__h546661 or + _theResult___fst_exp__h554887 or + out_exp__h555619 or _theResult___exp__h555616) begin - case (guard__h546660) + case (guard__h546661) 2'b0, 2'b01: - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q186 = - _theResult___fst_exp__h554886; + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q186 = + _theResult___fst_exp__h554887; 2'b10: - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q186 = - out_exp__h555618; + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q186 = + out_exp__h555619; 2'b11: - CASE_guard46660_0b0_theResult___fst_exp54886_0_ETC__q186 = - _theResult___exp__h555615; + CASE_guard46661_0b0_theResult___fst_exp54887_0_ETC__q186 = + _theResult___exp__h555616; endcase end - always@(guard__h555729 or - _theResult___fst_exp__h563719 or _theResult___exp__h564399) + always@(guard__h555730 or + _theResult___fst_exp__h563720 or _theResult___exp__h564400) begin - case (guard__h555729) + case (guard__h555730) 2'b0: - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q187 = - _theResult___fst_exp__h563719; + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q187 = + _theResult___fst_exp__h563720; 2'b01, 2'b10, 2'b11: - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q187 = - _theResult___exp__h564399; + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q187 = + _theResult___exp__h564400; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h563719 or + _theResult___fst_exp__h563720 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682 or - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q187) + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = - _theResult___fst_exp__h563719; + _theResult___fst_exp__h563720; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684; @@ -36550,49 +36603,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q187; + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = 11'd0; endcase end - always@(guard__h555729 or - _theResult___fst_exp__h563719 or - out_exp__h564402 or _theResult___exp__h564399) + always@(guard__h555730 or + _theResult___fst_exp__h563720 or + out_exp__h564403 or _theResult___exp__h564400) begin - case (guard__h555729) + case (guard__h555730) 2'b0, 2'b01: - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q188 = - _theResult___fst_exp__h563719; + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q188 = + _theResult___fst_exp__h563720; 2'b10: - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q188 = - out_exp__h564402; + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q188 = + out_exp__h564403; 2'b11: - CASE_guard55729_0b0_theResult___fst_exp63719_0_ETC__q188 = - _theResult___exp__h564399; + CASE_guard55730_0b0_theResult___fst_exp63720_0_ETC__q188 = + _theResult___exp__h564400; endcase end - always@(guard__h585964 or - _theResult___fst_exp__h594190 or _theResult___exp__h594919) + always@(guard__h585965 or + _theResult___fst_exp__h594191 or _theResult___exp__h594920) begin - case (guard__h585964) + case (guard__h585965) 2'b0: - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q189 = - _theResult___fst_exp__h594190; + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q189 = + _theResult___fst_exp__h594191; 2'b01, 2'b10, 2'b11: - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q189 = - _theResult___exp__h594919; + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q189 = + _theResult___exp__h594920; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h594190 or + _theResult___fst_exp__h594191 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 or - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q189) + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - _theResult___fst_exp__h594190; + _theResult___fst_exp__h594191; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883; @@ -36601,49 +36654,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q189; + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = 11'd0; endcase end - always@(guard__h585964 or - _theResult___fst_exp__h594190 or - out_exp__h594922 or _theResult___exp__h594919) + always@(guard__h585965 or + _theResult___fst_exp__h594191 or + out_exp__h594923 or _theResult___exp__h594920) begin - case (guard__h585964) + case (guard__h585965) 2'b0, 2'b01: - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q190 = - _theResult___fst_exp__h594190; + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q190 = + _theResult___fst_exp__h594191; 2'b10: - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q190 = - out_exp__h594922; + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q190 = + out_exp__h594923; 2'b11: - CASE_guard85964_0b0_theResult___fst_exp94190_0_ETC__q190 = - _theResult___exp__h594919; + CASE_guard85965_0b0_theResult___fst_exp94191_0_ETC__q190 = + _theResult___exp__h594920; endcase end - always@(guard__h595033 or - _theResult___fst_exp__h603023 or _theResult___exp__h603703) + always@(guard__h595034 or + _theResult___fst_exp__h603024 or _theResult___exp__h603704) begin - case (guard__h595033) + case (guard__h595034) 2'b0: - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q191 = - _theResult___fst_exp__h603023; + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q191 = + _theResult___fst_exp__h603024; 2'b01, 2'b10, 2'b11: - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q191 = - _theResult___exp__h603703; + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q191 = + _theResult___exp__h603704; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h603023 or + _theResult___fst_exp__h603024 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912 or - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q191) + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = - _theResult___fst_exp__h603023; + _theResult___fst_exp__h603024; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914; @@ -36652,44 +36705,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q191; + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = 11'd0; endcase end - always@(guard__h595033 or - _theResult___fst_exp__h603023 or - out_exp__h603706 or _theResult___exp__h603703) + always@(guard__h595034 or + _theResult___fst_exp__h603024 or + out_exp__h603707 or _theResult___exp__h603704) begin - case (guard__h595033) + case (guard__h595034) 2'b0, 2'b01: - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q192 = - _theResult___fst_exp__h603023; + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q192 = + _theResult___fst_exp__h603024; 2'b10: - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q192 = - out_exp__h603706; + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q192 = + out_exp__h603707; 2'b11: - CASE_guard95033_0b0_theResult___fst_exp03023_0_ETC__q192 = - _theResult___exp__h603703; + CASE_guard95034_0b0_theResult___fst_exp03024_0_ETC__q192 = + _theResult___exp__h603704; endcase end - always@(guard__h537348 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h546661 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537348) + case (guard__h546661) 2'b0, 2'b01, 2'b10: - CASE_guard37348_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard46661_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37348_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h537348 == 2'b11 && + CASE_guard46661_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h546661 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537348) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546661) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36699,12 +36752,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h537348 == 2'b0) ? + (guard__h546661 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h537348 == 2'b01 || guard__h537348 == 2'b10 || - guard__h537348 == 2'b11) && + (guard__h546661 == 2'b01 || guard__h546661 == 2'b10 || + guard__h546661 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36715,23 +36768,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h546660 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537349 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h546660) + case (guard__h537349) 2'b0, 2'b01, 2'b10: - CASE_guard46660_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard37349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard46660_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h546660 == 2'b11 && + CASE_guard37349_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h537349 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546660) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537349) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36741,12 +36794,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h546660 == 2'b0) ? + (guard__h537349 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h546660 == 2'b01 || guard__h546660 == 2'b10 || - guard__h546660 == 2'b11) && + (guard__h537349 == 2'b01 || guard__h537349 == 2'b10 || + guard__h537349 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36757,23 +36810,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h555729 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h555730 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h555729) + case (guard__h555730) 2'b0, 2'b01, 2'b10: - CASE_guard55729_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard55730_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard55729_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h555729 == 2'b11 && + CASE_guard55730_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h555730 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555729) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555730) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36783,12 +36836,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h555729 == 2'b0) ? + (guard__h555730 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h555729 == 2'b01 || guard__h555729 == 2'b10 || - guard__h555729 == 2'b11) && + (guard__h555730 == 2'b01 || guard__h555730 == 2'b10 || + guard__h555730 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36799,23 +36852,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h546660 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h546661 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h546660) + case (guard__h546661) 2'b0, 2'b01, 2'b10: - CASE_guard46660_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard46661_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard46660_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h546660 != 2'b11 || + CASE_guard46661_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h546661 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546660) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546661) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36825,12 +36878,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h546660 == 2'b0) ? + (guard__h546661 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h546660 != 2'b01 && guard__h546660 != 2'b10 && - guard__h546660 != 2'b11 || + guard__h546661 != 2'b01 && guard__h546661 != 2'b10 && + guard__h546661 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36841,23 +36894,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h555729 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h555730 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h555729) + case (guard__h555730) 2'b0, 2'b01, 2'b10: - CASE_guard55729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard55730_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard55729_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h555729 != 2'b11 || + CASE_guard55730_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h555730 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555729) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555730) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36867,12 +36920,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h555729 == 2'b0) ? + (guard__h555730 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h555729 != 2'b01 && guard__h555729 != 2'b10 && - guard__h555729 != 2'b11 || + guard__h555730 != 2'b01 && guard__h555730 != 2'b10 && + guard__h555730 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36883,23 +36936,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537348 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537349 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537348) + case (guard__h537349) 2'b0, 2'b01, 2'b10: - CASE_guard37348_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard37349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37348_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h537348 != 2'b11 || + CASE_guard37349_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h537349 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537348) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537349) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36909,12 +36962,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h537348 == 2'b0) ? + (guard__h537349 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h537348 != 2'b01 && guard__h537348 != 2'b10 && - guard__h537348 != 2'b11 || + guard__h537349 != 2'b01 && guard__h537349 != 2'b10 && + guard__h537349 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36925,28 +36978,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537348 or - _theResult___snd__h545260 or _theResult___sfd__h545965) + always@(guard__h537349 or + _theResult___snd__h545261 or _theResult___sfd__h545966) begin - case (guard__h537348) + case (guard__h537349) 2'b0: - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q205 = - _theResult___snd__h545260[56:5]; + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q205 = + _theResult___snd__h545261[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q205 = - _theResult___sfd__h545965; + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q205 = + _theResult___sfd__h545966; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h545260 or + _theResult___snd__h545261 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10710 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708 or - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q205) + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = - _theResult___snd__h545260[56:5]; + _theResult___snd__h545261[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10710; @@ -36955,48 +37008,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q205; + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = 52'd0; endcase end - always@(guard__h537348 or - _theResult___snd__h545260 or - out_sfd__h545968 or _theResult___sfd__h545965) + always@(guard__h537349 or + _theResult___snd__h545261 or + out_sfd__h545969 or _theResult___sfd__h545966) begin - case (guard__h537348) + case (guard__h537349) 2'b0, 2'b01: - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q206 = - _theResult___snd__h545260[56:5]; + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q206 = + _theResult___snd__h545261[56:5]; 2'b10: - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q206 = - out_sfd__h545968; + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q206 = + out_sfd__h545969; 2'b11: - CASE_guard37348_0b0_theResult___snd45260_BITS__ETC__q206 = - _theResult___sfd__h545965; + CASE_guard37349_0b0_theResult___snd45261_BITS__ETC__q206 = + _theResult___sfd__h545966; endcase end - always@(guard__h546660 or sfdin__h554880 or _theResult___sfd__h555616) + always@(guard__h546661 or sfdin__h554881 or _theResult___sfd__h555617) begin - case (guard__h546660) + case (guard__h546661) 2'b0: - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h554880[56:5]; + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h554881[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h555616; + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h555617; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h554880 or + sfdin__h554881 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734 or - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q207) + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = - sfdin__h554880[56:5]; + sfdin__h554881[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736; @@ -37005,48 +37058,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q207; + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = 52'd0; endcase end - always@(guard__h546660 or - sfdin__h554880 or out_sfd__h555619 or _theResult___sfd__h555616) + always@(guard__h546661 or + sfdin__h554881 or out_sfd__h555620 or _theResult___sfd__h555617) begin - case (guard__h546660) + case (guard__h546661) 2'b0, 2'b01: - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h554880[56:5]; + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h554881[56:5]; 2'b10: - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h555619; + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h555620; 2'b11: - CASE_guard46660_0b0_sfdin54880_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h555616; + CASE_guard46661_0b0_sfdin54881_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h555617; endcase end - always@(guard__h555729 or - _theResult___snd__h563665 or _theResult___sfd__h564400) + always@(guard__h555730 or + _theResult___snd__h563666 or _theResult___sfd__h564401) begin - case (guard__h555729) + case (guard__h555730) 2'b0: - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q209 = - _theResult___snd__h563665[56:5]; + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q209 = + _theResult___snd__h563666[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q209 = - _theResult___sfd__h564400; + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q209 = + _theResult___sfd__h564401; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h563665 or + _theResult___snd__h563666 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10755 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10753 or - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q209) + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = - _theResult___snd__h563665[56:5]; + _theResult___snd__h563666[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10755; @@ -37055,49 +37108,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10753; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q209; + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = 52'd0; endcase end - always@(guard__h555729 or - _theResult___snd__h563665 or - out_sfd__h564403 or _theResult___sfd__h564400) + always@(guard__h555730 or + _theResult___snd__h563666 or + out_sfd__h564404 or _theResult___sfd__h564401) begin - case (guard__h555729) + case (guard__h555730) 2'b0, 2'b01: - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q210 = - _theResult___snd__h563665[56:5]; + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q210 = + _theResult___snd__h563666[56:5]; 2'b10: - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q210 = - out_sfd__h564403; + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q210 = + out_sfd__h564404; 2'b11: - CASE_guard55729_0b0_theResult___snd63665_BITS__ETC__q210 = - _theResult___sfd__h564400; + CASE_guard55730_0b0_theResult___snd63666_BITS__ETC__q210 = + _theResult___sfd__h564401; endcase end - always@(guard__h507807 or - _theResult___fst_exp__h516033 or _theResult___exp__h516762) + always@(guard__h507808 or + _theResult___fst_exp__h516034 or _theResult___exp__h516763) begin - case (guard__h507807) + case (guard__h507808) 2'b0: - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q211 = - _theResult___fst_exp__h516033; + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q211 = + _theResult___fst_exp__h516034; 2'b01, 2'b10, 2'b11: - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q211 = - _theResult___exp__h516762; + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q211 = + _theResult___exp__h516763; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h516033 or + _theResult___fst_exp__h516034 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9173 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171 or - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q211) + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = - _theResult___fst_exp__h516033; + _theResult___fst_exp__h516034; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9173; @@ -37106,49 +37159,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q211; + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = 11'd0; endcase end - always@(guard__h507807 or - _theResult___fst_exp__h516033 or - out_exp__h516765 or _theResult___exp__h516762) + always@(guard__h507808 or + _theResult___fst_exp__h516034 or + out_exp__h516766 or _theResult___exp__h516763) begin - case (guard__h507807) + case (guard__h507808) 2'b0, 2'b01: - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q212 = - _theResult___fst_exp__h516033; + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q212 = + _theResult___fst_exp__h516034; 2'b10: - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q212 = - out_exp__h516765; + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q212 = + out_exp__h516766; 2'b11: - CASE_guard07807_0b0_theResult___fst_exp16033_0_ETC__q212 = - _theResult___exp__h516762; + CASE_guard07808_0b0_theResult___fst_exp16034_0_ETC__q212 = + _theResult___exp__h516763; endcase end - always@(guard__h516876 or - _theResult___fst_exp__h524866 or _theResult___exp__h525546) + always@(guard__h516877 or + _theResult___fst_exp__h524867 or _theResult___exp__h525547) begin - case (guard__h516876) + case (guard__h516877) 2'b0: - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q213 = - _theResult___fst_exp__h524866; + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q213 = + _theResult___fst_exp__h524867; 2'b01, 2'b10, 2'b11: - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q213 = - _theResult___exp__h525546; + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q213 = + _theResult___exp__h525547; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h524866 or + _theResult___fst_exp__h524867 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9204 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9202 or - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q213) + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = - _theResult___fst_exp__h524866; + _theResult___fst_exp__h524867; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9204; @@ -37157,49 +37210,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9202; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q213; + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = 11'd0; endcase end - always@(guard__h516876 or - _theResult___fst_exp__h524866 or - out_exp__h525549 or _theResult___exp__h525546) + always@(guard__h516877 or + _theResult___fst_exp__h524867 or + out_exp__h525550 or _theResult___exp__h525547) begin - case (guard__h516876) + case (guard__h516877) 2'b0, 2'b01: - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q214 = - _theResult___fst_exp__h524866; + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q214 = + _theResult___fst_exp__h524867; 2'b10: - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q214 = - out_exp__h525549; + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q214 = + out_exp__h525550; 2'b11: - CASE_guard16876_0b0_theResult___fst_exp24866_0_ETC__q214 = - _theResult___exp__h525546; + CASE_guard16877_0b0_theResult___fst_exp24867_0_ETC__q214 = + _theResult___exp__h525547; endcase end - always@(guard__h498495 or - _theResult___snd__h506407 or _theResult___sfd__h507112) + always@(guard__h498496 or + _theResult___snd__h506408 or _theResult___sfd__h507113) begin - case (guard__h498495) + case (guard__h498496) 2'b0: - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q215 = - _theResult___snd__h506407[56:5]; + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q215 = + _theResult___snd__h506408[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q215 = - _theResult___sfd__h507112; + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q215 = + _theResult___sfd__h507113; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h506407 or + _theResult___snd__h506408 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9230 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9228 or - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q215) + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = - _theResult___snd__h506407[56:5]; + _theResult___snd__h506408[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9230; @@ -37208,48 +37261,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9228; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q215; + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = 52'd0; endcase end - always@(guard__h498495 or - _theResult___snd__h506407 or - out_sfd__h507115 or _theResult___sfd__h507112) + always@(guard__h498496 or + _theResult___snd__h506408 or + out_sfd__h507116 or _theResult___sfd__h507113) begin - case (guard__h498495) + case (guard__h498496) 2'b0, 2'b01: - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q216 = - _theResult___snd__h506407[56:5]; + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q216 = + _theResult___snd__h506408[56:5]; 2'b10: - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q216 = - out_sfd__h507115; + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q216 = + out_sfd__h507116; 2'b11: - CASE_guard98495_0b0_theResult___snd06407_BITS__ETC__q216 = - _theResult___sfd__h507112; + CASE_guard98496_0b0_theResult___snd06408_BITS__ETC__q216 = + _theResult___sfd__h507113; endcase end - always@(guard__h507807 or sfdin__h516027 or _theResult___sfd__h516763) + always@(guard__h507808 or sfdin__h516028 or _theResult___sfd__h516764) begin - case (guard__h507807) + case (guard__h507808) 2'b0: - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h516027[56:5]; + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h516028[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h516763; + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h516764; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h516027 or + sfdin__h516028 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9257 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255 or - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q217) + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = - sfdin__h516027[56:5]; + sfdin__h516028[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9257; @@ -37258,48 +37311,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q217; + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = 52'd0; endcase end - always@(guard__h507807 or - sfdin__h516027 or out_sfd__h516766 or _theResult___sfd__h516763) + always@(guard__h507808 or + sfdin__h516028 or out_sfd__h516767 or _theResult___sfd__h516764) begin - case (guard__h507807) + case (guard__h507808) 2'b0, 2'b01: - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h516027[56:5]; + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h516028[56:5]; 2'b10: - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h516766; + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h516767; 2'b11: - CASE_guard07807_0b0_sfdin16027_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h516763; + CASE_guard07808_0b0_sfdin16028_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h516764; endcase end - always@(guard__h516876 or - _theResult___snd__h524812 or _theResult___sfd__h525547) + always@(guard__h516877 or + _theResult___snd__h524813 or _theResult___sfd__h525548) begin - case (guard__h516876) + case (guard__h516877) 2'b0: - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q219 = - _theResult___snd__h524812[56:5]; + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q219 = + _theResult___snd__h524813[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q219 = - _theResult___sfd__h525547; + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q219 = + _theResult___sfd__h525548; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h524812 or + _theResult___snd__h524813 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9276 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9274 or - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q219) + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = - _theResult___snd__h524812[56:5]; + _theResult___snd__h524813[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9276; @@ -37308,49 +37361,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9274; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q219; + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = 52'd0; endcase end - always@(guard__h516876 or - _theResult___snd__h524812 or - out_sfd__h525550 or _theResult___sfd__h525547) + always@(guard__h516877 or + _theResult___snd__h524813 or + out_sfd__h525551 or _theResult___sfd__h525548) begin - case (guard__h516876) + case (guard__h516877) 2'b0, 2'b01: - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q220 = - _theResult___snd__h524812[56:5]; + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q220 = + _theResult___snd__h524813[56:5]; 2'b10: - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q220 = - out_sfd__h525550; + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q220 = + out_sfd__h525551; 2'b11: - CASE_guard16876_0b0_theResult___snd24812_BITS__ETC__q220 = - _theResult___sfd__h525547; + CASE_guard16877_0b0_theResult___snd24813_BITS__ETC__q220 = + _theResult___sfd__h525548; endcase end - always@(guard__h576652 or - _theResult___snd__h584564 or _theResult___sfd__h585269) + always@(guard__h576653 or + _theResult___snd__h584565 or _theResult___sfd__h585270) begin - case (guard__h576652) + case (guard__h576653) 2'b0: - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q221 = - _theResult___snd__h584564[56:5]; + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q221 = + _theResult___snd__h584565[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q221 = - _theResult___sfd__h585269; + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q221 = + _theResult___sfd__h585270; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h584564 or + _theResult___snd__h584565 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9940 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9938 or - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q221) + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = - _theResult___snd__h584564[56:5]; + _theResult___snd__h584565[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9940; @@ -37359,48 +37412,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9938; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q221; + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = 52'd0; endcase end - always@(guard__h576652 or - _theResult___snd__h584564 or - out_sfd__h585272 or _theResult___sfd__h585269) + always@(guard__h576653 or + _theResult___snd__h584565 or + out_sfd__h585273 or _theResult___sfd__h585270) begin - case (guard__h576652) + case (guard__h576653) 2'b0, 2'b01: - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q222 = - _theResult___snd__h584564[56:5]; + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q222 = + _theResult___snd__h584565[56:5]; 2'b10: - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q222 = - out_sfd__h585272; + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q222 = + out_sfd__h585273; 2'b11: - CASE_guard76652_0b0_theResult___snd84564_BITS__ETC__q222 = - _theResult___sfd__h585269; + CASE_guard76653_0b0_theResult___snd84565_BITS__ETC__q222 = + _theResult___sfd__h585270; endcase end - always@(guard__h585964 or sfdin__h594184 or _theResult___sfd__h594920) + always@(guard__h585965 or sfdin__h594185 or _theResult___sfd__h594921) begin - case (guard__h585964) + case (guard__h585965) 2'b0: - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h594184[56:5]; + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h594185[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h594920; + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h594921; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h594184 or + sfdin__h594185 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9966 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9964 or - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q223) + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = - sfdin__h594184[56:5]; + sfdin__h594185[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9966; @@ -37409,24 +37462,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9964; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q223; + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = 52'd0; endcase end - always@(guard__h585964 or - sfdin__h594184 or out_sfd__h594923 or _theResult___sfd__h594920) + always@(guard__h585965 or + sfdin__h594185 or out_sfd__h594924 or _theResult___sfd__h594921) begin - case (guard__h585964) + case (guard__h585965) 2'b0, 2'b01: - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h594184[56:5]; + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h594185[56:5]; 2'b10: - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h594923; + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h594924; 2'b11: - CASE_guard85964_0b0_sfdin94184_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h594920; + CASE_guard85965_0b0_sfdin94185_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h594921; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37461,28 +37514,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d10967; endcase end - always@(guard__h595033 or - _theResult___snd__h602969 or _theResult___sfd__h603704) + always@(guard__h595034 or + _theResult___snd__h602970 or _theResult___sfd__h603705) begin - case (guard__h595033) + case (guard__h595034) 2'b0: - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q225 = - _theResult___snd__h602969[56:5]; + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q225 = + _theResult___snd__h602970[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q225 = - _theResult___sfd__h603704; + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q225 = + _theResult___sfd__h603705; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h602969 or + _theResult___snd__h602970 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9985 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9983 or - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q225) + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = - _theResult___snd__h602969[56:5]; + _theResult___snd__h602970[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9985; @@ -37491,25 +37544,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9983; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q225; + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = 52'd0; endcase end - always@(guard__h595033 or - _theResult___snd__h602969 or - out_sfd__h603707 or _theResult___sfd__h603704) + always@(guard__h595034 or + _theResult___snd__h602970 or + out_sfd__h603708 or _theResult___sfd__h603705) begin - case (guard__h595033) + case (guard__h595034) 2'b0, 2'b01: - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q226 = - _theResult___snd__h602969[56:5]; + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q226 = + _theResult___snd__h602970[56:5]; 2'b10: - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q226 = - out_sfd__h603707; + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q226 = + out_sfd__h603708; 2'b11: - CASE_guard95033_0b0_theResult___snd02969_BITS__ETC__q226 = - _theResult___sfd__h603704; + CASE_guard95034_0b0_theResult___snd02970_BITS__ETC__q226 = + _theResult___sfd__h603705; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37560,110 +37613,30 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11135; endcase end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[399:397]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 = - coreFix_aluExe_0_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 = 3'd7; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227) - begin - case (coreFix_aluExe_0_regToExeQ$first[416:414]) - 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - coreFix_aluExe_0_regToExeQ$first[416:396]; - 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - { coreFix_aluExe_0_regToExeQ$first[416:414], - 9'h0AA, - coreFix_aluExe_0_regToExeQ$first[404:400], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227, - coreFix_aluExe_0_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - { 3'd5, 18'h2AAAA }; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[394:383]) - 12'd1971, - 12'd1970, - 12'd1969, - 12'd1968, - 12'd1955, - 12'd1954, - 12'd1953, - 12'd1952, - 12'd3860, - 12'd3859, - 12'd3858, - 12'd3857, - 12'd2818, - 12'd2816, - 12'd836, - 12'd835, - 12'd834, - 12'd833, - 12'd832, - 12'd774, - 12'd773, - 12'd772, - 12'd771, - 12'd770, - 12'd769, - 12'd768, - 12'd384, - 12'd324, - 12'd323, - 12'd322, - 12'd321, - 12'd320, - 12'd262, - 12'd261, - 12'd260, - 12'd256, - 12'd2049, - 12'd2048, - 12'd3074, - 12'd3073, - 12'd3072, - 12'd3, - 12'd2, - 12'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 = - coreFix_aluExe_0_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 = - 12'd2303; - endcase - end always@(coreFix_aluExe_1_regToExeQ$first) begin case (coreFix_aluExe_1_regToExeQ$first[399:397]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = coreFix_aluExe_1_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227) begin case (coreFix_aluExe_1_regToExeQ$first[416:414]) 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = coreFix_aluExe_1_regToExeQ$first[416:396]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = { coreFix_aluExe_1_regToExeQ$first[416:414], 9'h0AA, coreFix_aluExe_1_regToExeQ$first[404:400], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, coreFix_aluExe_1_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = { 3'd5, 18'h2AAAA }; endcase end @@ -37714,9 +37687,89 @@ module mkCore(CLK, 12'd3, 12'd2, 12'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = coreFix_aluExe_1_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = + 12'd2303; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[399:397]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = + coreFix_aluExe_0_regToExeQ$first[399:397]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = 3'd7; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first or + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230) + begin + case (coreFix_aluExe_0_regToExeQ$first[416:414]) + 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + coreFix_aluExe_0_regToExeQ$first[416:396]; + 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + { coreFix_aluExe_0_regToExeQ$first[416:414], + 9'h0AA, + coreFix_aluExe_0_regToExeQ$first[404:400], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, + coreFix_aluExe_0_regToExeQ$first[396] }; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + { 3'd5, 18'h2AAAA }; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[394:383]) + 12'd1971, + 12'd1970, + 12'd1969, + 12'd1968, + 12'd1955, + 12'd1954, + 12'd1953, + 12'd1952, + 12'd3860, + 12'd3859, + 12'd3858, + 12'd3857, + 12'd2818, + 12'd2816, + 12'd836, + 12'd835, + 12'd834, + 12'd833, + 12'd832, + 12'd774, + 12'd773, + 12'd772, + 12'd771, + 12'd770, + 12'd769, + 12'd768, + 12'd384, + 12'd324, + 12'd323, + 12'd322, + 12'd321, + 12'd320, + 12'd262, + 12'd261, + 12'd260, + 12'd256, + 12'd2049, + 12'd2048, + 12'd3074, + 12'd3073, + 12'd3072, + 12'd3, + 12'd2, + 12'd1: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = + coreFix_aluExe_0_regToExeQ$first[394:383]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = 12'd2303; endcase end @@ -37829,10 +37882,10 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h677209 or + always@(k__h677211 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h677209) + case (k__h677211) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3684_co_ETC___d13694 = coreFix_aluExe_0_rsAlu$canEnq; @@ -37871,10 +37924,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13706; endcase end - always@(k__h677209 or + always@(k__h677211 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h677209) + case (k__h677211) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13727 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -38020,14 +38073,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h693566 or + always@(idx__h693568 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13991 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13997 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h693566) + case (idx__h693568) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14017 = fetchStage$pipelines_0_canDeq && @@ -38148,15 +38201,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3775_AND__ETC___d13983; endcase end - always@(k__h677209 or + always@(k__h677211 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h677209) + case (k__h677211) 1'd0: - CASE_k77209_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k77209_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -38193,7 +38246,7 @@ module mkCore(CLK, always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13764 or - regRenamingTable_RDY_rename_0_getRename__3536__ETC___d14186 or + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14186 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3684_co_ETC___d13694 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14173 or @@ -38215,7 +38268,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13764 || - regRenamingTable_RDY_rename_0_getRename__3536__ETC___d14186; + regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14186; endcase end always@(fetchStage$pipelines_0_first or @@ -38259,14 +38312,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13706; endcase end - always@(idx__h693566 or + always@(idx__h693568 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14236 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14243 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h693566) + case (idx__h693568) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14247 = (!fetchStage$pipelines_0_canDeq || @@ -38405,10 +38458,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14390 = - coreFix_memExe_lsq$enqLdTag[4:0]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14390 = - coreFix_memExe_lsq$enqStTag[4:0]; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14393 = + coreFix_memExe_lsq$enqLdTag[3:0]; + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14393 = + coreFix_memExe_lsq$enqStTag[3:0]; endcase end always@(fetchStage$pipelines_0_first or @@ -38416,10 +38469,10 @@ module mkCore(CLK, begin case (fetchStage$pipelines_0_first[191:189]) 3'd0, 3'd2: - IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14393 = - coreFix_memExe_lsq$enqLdTag[3:0]; - default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14393 = - coreFix_memExe_lsq$enqStTag[3:0]; + IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14390 = + coreFix_memExe_lsq$enqLdTag[4:0]; + default: IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14390 = + coreFix_memExe_lsq$enqStTag[4:0]; endcase end always@(fetchStage$pipelines_1_first or @@ -38496,112 +38549,112 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd0; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd1; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd2; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd8; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd9; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd10; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd11; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd12; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd13; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd14; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd15; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd16; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd17; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd18; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd19; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd20; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd21; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd22; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd23; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd24; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd25; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd26; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd27; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd28; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd29; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd29; 12'd1952: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd36; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd36; 12'd1953: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd37; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd37; 12'd1954: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd38; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd38; 12'd1955: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd39; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd39; 12'd1968: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd40; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd40; 12'd1969: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd41; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd41; 12'd1970: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd42; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd42; 12'd1971: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd43; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd43; 12'd2048: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd6; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd7; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd30; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd31; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd3; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd4; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd5; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd32; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd33; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd34; + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 = + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 = 6'd44; endcase end - always@(IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 or + always@(IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 or rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285) + case (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295) 6'd0: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38614,7 +38667,7 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 54'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8], 2'b0, @@ -38622,22 +38675,22 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd10, 6'd23: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38649,9 +38702,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h730624 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h731607 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38659,7 +38712,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21, 6'd22, 6'd29: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38668,12 +38721,12 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h730624 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h731607 = 64'd0; 6'd37: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h730624 = + data_warl_xformed__h731607 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38682,127 +38735,17 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h730624 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h731607 = rob$deqPort_0_deq_data[95:32]; endcase end always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4635_BITS_329_TO_32_ETC___d15494) + IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15505) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h731276 = - IF_rob_deqPort_0_deq_data__4635_BITS_329_TO_32_ETC___d15494; - default: x__h731276 = rob$deqPort_0_deq_data[425:362]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; - endcase - end - always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) - 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; - 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 = - coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 = - 4'd15; + x__h732275 = + IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15505; + default: x__h732275 = rob$deqPort_0_deq_data[425:362]; endcase end always@(rob$deqPort_0_deq_data) @@ -38852,12 +38795,172 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q254 = + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q254 = + default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = 12'd2303; endcase end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + 4'd15; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[97:96]) + 2'd0, 2'd1: + CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 = + commitStage_f_rob_data$D_OUT[97:96]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 = 2'd2; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 = + commitStage_f_rob_data$D_OUT[165:162]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 = + 4'd15; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 = + commitStage_f_rob_data$D_OUT[165:162]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[97:96]) + 2'd0, 2'd1: + CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 = + rob$deqPort_0_deq_data[97:96]; + default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 = 2'd2; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; + endcase + end + always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) + 1'd0: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; + 1'd1: + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = + coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -39093,18 +39196,9 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q255 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q255 = 3'd7; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[97:96]) - 2'd0, 2'd1: - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 = - rob$deqPort_0_deq_data[97:96]; - default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 = 2'd2; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -39126,25 +39220,16 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9999; endcase end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[97:96]) - 2'd0, 2'd1: - CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = - commitStage_f_rob_data$D_OUT[97:96]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = 2'd2; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -39154,10 +39239,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -39167,10 +39252,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -39180,10 +39265,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -39193,10 +39278,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515]; endcase end @@ -39206,10 +39291,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513]; endcase end @@ -39219,10 +39304,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end @@ -39232,10 +39317,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516]; endcase end @@ -39245,10 +39330,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end @@ -39279,10 +39364,10 @@ module mkCore(CLK, begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228]) 2'd0, 2'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q269 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 && coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q267 = + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q269 = coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8542; endcase end @@ -39292,10 +39377,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -39305,10 +39390,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -39318,10 +39403,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -39331,10 +39416,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -39344,10 +39429,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q274 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q274 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -39357,10 +39442,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end @@ -39370,10 +39455,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q276 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q276 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end @@ -39381,35 +39466,13 @@ module mkCore(CLK, begin case (mmio_dataReqQ_data_0[77:76]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q277 = mmio_dataReqQ_data_0[77:72]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q275 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q277 = { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q276 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q276 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -39426,9 +39489,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q278 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q278 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q279 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q279 = 4'd15; endcase end @@ -39479,44 +39564,12 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278 = + CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q280 = commitStage_f_rob_data$D_OUT[180:169]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q278 = + default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q280 = 12'd2303; endcase end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 = - commitStage_f_rob_data$D_OUT[165:162]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 = - 4'd15; - endcase - end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280 = - commitStage_f_rob_data$D_OUT[165:162]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q280 = - 4'd15; - endcase - end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) @@ -40019,6 +40072,7 @@ module mkCore(CLK, commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY 166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY 64'd0; commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0; commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0; coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -40328,6 +40382,9 @@ module mkCore(CLK, if (commitStage_rg_just_after_reset$EN) commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY commitStage_rg_just_after_reset$D_IN; + if (commitStage_rg_old_mip_csr_val$EN) + commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY + commitStage_rg_old_mip_csr_val$D_IN; if (commitStage_rg_run_state$EN) commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY commitStage_rg_run_state$D_IN; @@ -40979,6 +41036,7 @@ module mkCore(CLK, begin commitStage_commitTrap = 166'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; commitStage_rg_just_after_reset = 1'h0; + commitStage_rg_old_mip_csr_val = 64'hAAAAAAAAAAAAAAAA; commitStage_rg_run_state = 1'h0; commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA; coreFix_doStatsReg = 1'h0; @@ -41554,14 +41612,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4635_BIT_181_4710_T_ETC___d15285 == 6'd6) + IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - next_pc__h730647 != - rob_deqPort_0_deq_data__4635_BITS_425_TO_362_4_ETC___d15485) + next_pc__h731630 != + rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -41698,7 +41756,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] != 5'd19 && rob$deqPort_1_deq_data[329:325] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_serial_num_4820_PLUS_IF_rob_deq_ETC___d15758, + commitStage_rg_serial_num_4635_PLUS_IF_rob_deq_ETC___d15770, rob$deqPort_1_deq_data[425:362], rob$deqPort_1_deq_data[361:330], " iType:"); @@ -41901,7 +41959,7 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12137[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626399)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626401)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -41918,7 +41976,7 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12839[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h649113)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h649115)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -42013,6 +42071,15 @@ module mkCore(CLK, coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && coreFix_memExe_lsq$firstSt[158:157] != 2'd2) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && + coreFix_memExe_lsq$firstSt[158:157] != 2'd2) + $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && + coreFix_memExe_lsq$firstSt[4]) + $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && (coreFix_memExe_lsq$firstSt[158:157] != 2'd1 && @@ -42023,15 +42090,6 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && coreFix_memExe_lsq$firstSt[4]) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && - coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && - coreFix_memExe_lsq$firstSt[158:157] != 2'd2) - $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq && - coreFix_memExe_lsq$firstSt[4]) - $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault && coreFix_memExe_lsq$firstSt[158:157] != 2'd0 && @@ -42235,7 +42293,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609133 == 2'd0) + v__h609134 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index 55f3e6a..ea0a6ee 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -1247,7 +1247,7 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip; // ports of submodule proc - wire [784 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get; + wire [861 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get; wire [76 : 0] proc$hart0_csr_mem_server_request_put; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; @@ -1424,7 +1424,7 @@ module mkCoreW(RST_N_dm_power_on_reset, tv_encode$RDY_v_cpu_in_1_put; // ports of submodule v_td2_to_td_0 - wire [784 : 0] v_td2_to_td_0$in_put; + wire [861 : 0] v_td2_to_td_0$in_put; wire [490 : 0] v_td2_to_td_0$out_get; wire v_td2_to_td_0$EN_in_put, v_td2_to_td_0$EN_out_get, @@ -1432,7 +1432,7 @@ module mkCoreW(RST_N_dm_power_on_reset, v_td2_to_td_0$RDY_out_get; // ports of submodule v_td2_to_td_1 - wire [784 : 0] v_td2_to_td_1$in_put; + wire [861 : 0] v_td2_to_td_1$in_put; wire [490 : 0] v_td2_to_td_1$out_get; wire v_td2_to_td_1$EN_in_put, v_td2_to_td_1$EN_out_get, @@ -1611,10 +1611,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // synopsys translate_off reg [31 : 0] v__h5047; reg [31 : 0] v__h5190; - reg [31 : 0] v__h15736; + reg [31 : 0] v__h15930; reg [31 : 0] v__h5041; reg [31 : 0] v__h5184; - reg [31 : 0] v__h15730; + reg [31 : 0] v__h15924; // synopsys translate_on // remaining internal signals @@ -3422,7 +3422,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule v_td2_to_td_0 assign v_td2_to_td_0$in_put = - { proc$v_to_TV_0_get[784:619], + { proc$v_to_TV_0_get[861:797], + proc$v_to_TV_0_get[797] ? + proc$v_to_TV_0_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + proc$v_to_TV_0_get[720:619], proc$v_to_TV_0_get[619] ? proc$v_to_TV_0_get[618:613] : 6'h2A, proc$v_to_TV_0_get[612:476], proc$v_to_TV_0_get[476] ? @@ -3443,7 +3447,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule v_td2_to_td_1 assign v_td2_to_td_1$in_put = - { proc$v_to_TV_1_get[784:619], + { proc$v_to_TV_1_get[861:797], + proc$v_to_TV_1_get[797] ? + proc$v_to_TV_1_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + proc$v_to_TV_1_get[720:619], proc$v_to_TV_1_get[619] ? proc$v_to_TV_1_get[618:613] : 6'h2A, proc$v_to_TV_1_get[612:476], proc$v_to_TV_1_get[476] ? @@ -3726,15 +3734,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15736 = $stime; + v__h15930 = $stime; #0; end - v__h15730 = v__h15736 / 32'd10; + v__h15924 = v__h15930 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15730, + v__h15924, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFabric_2x3.v b/src_SSITH_P3/Verilog_RTL_sim/mkFabric_2x3.v index feb4788..8a1a6a7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFabric_2x3.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFabric_2x3.v @@ -3328,17 +3328,17 @@ module mkFabric_2x3(CLK, 8'd0 : x__h12338 ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_0$D_OUT[3:0], 66'd3, @@ -3749,23 +3749,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_xactors_from_masters_0_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: @@ -3776,9 +3776,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && @@ -3877,23 +3877,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_xactors_from_masters_1_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: @@ -3904,9 +3904,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index 7008f06..797685c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -88,9 +88,9 @@ // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg // RDY_hart0_put_other_req_put O 1 const -// v_to_TV_0_get O 785 +// v_to_TV_0_get O 862 // RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 785 +// v_to_TV_1_get O 862 // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset @@ -818,16 +818,16 @@ module mkProc(CLK, // actionvalue method v_to_TV_0_get input EN_v_to_TV_0_get; - output [784 : 0] v_to_TV_0_get; + output [861 : 0] v_to_TV_0_get; output RDY_v_to_TV_0_get; // actionvalue method v_to_TV_1_get input EN_v_to_TV_1_get; - output [784 : 0] v_to_TV_1_get; + output [861 : 0] v_to_TV_1_get; output RDY_v_to_TV_1_get; // signals for module outputs - wire [784 : 0] v_to_TV_0_get, v_to_TV_1_get; + wire [861 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; @@ -1357,7 +1357,7 @@ module mkProc(CLK, // ports of submodule core_0 reg [66 : 0] core_0$mmioToPlatform_pRs_enq_x; reg [38 : 0] core_0$mmioToPlatform_pRq_enq_x; - wire [784 : 0] core_0$v_to_TV_0_get, core_0$v_to_TV_1_get; + wire [861 : 0] core_0$v_to_TV_0_get, core_0$v_to_TV_1_get; wire [582 : 0] core_0$dCacheToParent_fromP_enq_x, core_0$iCacheToParent_fromP_enq_x; wire [578 : 0] core_0$dCacheToParent_rsToP_first, @@ -2205,9 +2205,9 @@ module mkProc(CLK, wire [511 : 0] IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1301, SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1451, new_cline__h135307; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1589, + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1588, SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1434; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1584, + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1583, SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1417; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__190_THE_ETC___d1400; wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__70_BITS_14_ETC___d393; @@ -2347,8 +2347,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1271, IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1291, IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1307, - IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657, + IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656, IF_mmioPlatform_mtimecmp_0_48_ULE_IF_NOT_mmioP_ETC___d613, IF_mmioPlatform_reqFunc_28_BITS_5_TO_4_29_EQ_0_ETC___d445, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__83__ETC___d192, @@ -2363,8 +2363,8 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__008_THEN_propDstId_ETC___d1011, NOT_enqDst_0_dummy2_0_read__075_076_OR_NOT_enq_ETC___d1091, NOT_enqDst_1_0_dummy2_0_read__349_350_OR_NOT_e_ETC___d1365, - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707, + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d742, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d750, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d755, @@ -2383,8 +2383,8 @@ module mkProc(CLK, NOT_propDstData_1_1_dummy2_1_read__368_379_OR__ETC___d1380, NOT_propDstIdx_0_dummy2_1_read__054_055_OR_IF__ETC___d1088, NOT_propDstIdx_1_0_dummy2_1_read__318_319_OR_I_ETC___d1362, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522, mmioPlatform_cycle_39_ULT_99___d340, mmioPlatform_fetchingWay_61_ULT_mmioPlatform_r_ETC___d971, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d323, @@ -2785,7 +2785,11 @@ module mkProc(CLK, // actionvalue method v_to_TV_0_get assign v_to_TV_0_get = - { core_0$v_to_TV_0_get[784:619], + { core_0$v_to_TV_0_get[861:797], + core_0$v_to_TV_0_get[797] ? + core_0$v_to_TV_0_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + core_0$v_to_TV_0_get[720:619], core_0$v_to_TV_0_get[619] ? core_0$v_to_TV_0_get[618:613] : 6'h2A, @@ -2809,7 +2813,11 @@ module mkProc(CLK, // actionvalue method v_to_TV_1_get assign v_to_TV_1_get = - { core_0$v_to_TV_1_get[784:619], + { core_0$v_to_TV_1_get[861:797], + core_0$v_to_TV_1_get[797] ? + core_0$v_to_TV_1_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + core_0$v_to_TV_1_get[720:619], core_0$v_to_TV_1_get[619] ? core_0$v_to_TV_1_get[618:613] : 6'h2A, @@ -3559,32 +3567,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3924,7 +3936,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3942,7 +3954,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3960,7 +3972,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3970,7 +3982,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3979,7 +3991,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3990,7 +4002,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3999,7 +4011,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4007,7 +4019,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -4031,7 +4043,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4048,15 +4060,15 @@ module mkProc(CLK, // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -4290,7 +4302,7 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1589, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1588, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? new_dword__h90002 : @@ -4694,10 +4706,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674, + IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4711,8 +4723,8 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr @@ -5588,7 +5600,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5618,11 +5630,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5970,7 +5982,7 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__266_THEN_enqDst_1_0__ETC___d1286, IF_enqDst_1_0_lat_1_whas__263_THEN_enqDst_1_0__ETC___d1309 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1584 = + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1583 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? new_dword__h90002 : @@ -5987,8 +5999,8 @@ module mkProc(CLK, 3'd4) ? new_dword__h90002 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1589 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1584, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1588 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1583, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? new_dword__h90002 : @@ -5997,11 +6009,11 @@ module mkProc(CLK, 3'd2) ? new_dword__h90002 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__669_THE_ETC___d1674 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__668_THE_ETC___d1673 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_curReq_23_BITS_2_TO_0_73_EQ_0x_ETC___d821 = @@ -6241,14 +6253,14 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__318_AND__ETC___d1359 || IF_NOT_propDstIdx_1_0_dummy2_1_read__318_319_O_ETC___d1363) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__654_ETC___d1657 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__653_ETC___d1656 ; assign NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d742 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && @@ -6425,9 +6437,9 @@ module mkProc(CLK, assign line_addr__h102461 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1601 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1600 = line_addr__h102461 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1523 = + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1522 = line_addr__h102375 == llc_mem_server_rg_cacheline_cache_addr ; assign mask__h89998 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? @@ -6995,14 +7007,14 @@ module mkProc(CLK, always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h148444 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h148444 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h148444 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h148444 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h148444 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h148444 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h148444 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h148444 = llc$to_mem_toM_first[511:448]; + 3'd0: strb8__h148445 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h148445 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h148445 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h148445 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h148445 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h148445 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h148445 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h148445 = llc$to_mem_toM_first[575:568]; endcase end always@(llc$dma_respLd_first) @@ -7021,14 +7033,14 @@ module mkProc(CLK, always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h148445 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h148445 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h148445 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h148445 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h148445 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h148445 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h148445 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h148445 = llc$to_mem_toM_first[575:568]; + 3'd0: data64__h148444 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h148444 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h148444 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h148444 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h148444 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h148444 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h148444 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h148444 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or @@ -9857,7 +9869,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd1) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__700_ETC___d1707 && + if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__699_ETC___d1706 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -9866,7 +9878,7 @@ module mkProc(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) begin v__h135004 = $stime; #0; @@ -9874,63 +9886,63 @@ module mkProc(CLK, v__h134998 = v__h135004 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h134998, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -10006,119 +10018,119 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791 && + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && @@ -11346,139 +11358,139 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", mem_req_wr_addr_awaddr__h148529); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", data64__h148444); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", strb8__h148445); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11565,103 +11577,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", mem_req_rd_addr_araddr__h134605); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) begin v__h161312 = $stime; #0; @@ -11669,41 +11681,41 @@ module mkProc(CLK, v__h161306 = v__h161312 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", v__h161306, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__774_U_ETC___d1791) + NOT_llc_axi4_adapter_cfg_verbosity_read__772_U_ETC___d1789) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v b/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v index 6910a82..90c7ef6 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTrace_Data2_to_Trace_Data.v @@ -11,7 +11,7 @@ // RDY_out_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// in_put I 785 +// in_put I 862 // EN_in_put I 1 // EN_out_get I 1 // @@ -46,7 +46,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, input RST_N; // action method in_put - input [784 : 0] in_put; + input [861 : 0] in_put; input EN_in_put; output RDY_in_put; @@ -60,7 +60,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, wire RDY_in_put, RDY_out_get; // ports of submodule f_in - wire [784 : 0] f_in$D_IN, f_in$D_OUT; + wire [861 : 0] f_in$D_IN, f_in$D_OUT; wire f_in$CLR, f_in$DEQ, f_in$EMPTY_N, f_in$ENQ, f_in$FULL_N; // ports of submodule f_out @@ -76,51 +76,54 @@ module mkTrace_Data2_to_Trace_Data(CLK, WILL_FIRE_out_get; // remaining internal signals - reg [63 : 0] x1_avValue_pc__h3456, x1_avValue_word1__h3460; - reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, - csr_addr__h5126; - reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1, - x1_avValue_rd__h3459; - reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4; - reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5; - wire [63 : 0] td_word2__h3496, - td_word2__h3647, - td_word3__h3497, - td_word4__h3384, - x1_avValue_pc__h3420, - x1_avValue_pc__h3726, - x1_avValue_pc__h3793, - x1_avValue_word1__h3506, - x1_avValue_word1__h3543, - x1_avValue_word1__h3619, - x1_avValue_word1__h3696, - x1_avValue_word1__h3797, - x1_avValue_word2__h3507, - x1_avValue_word2__h3620, - x1_avValue_word2__h3798, - x1_avValue_word3__h3508, - x1_avValue_word3__h3799, - x1_avValue_word4__h3463, - x1_avValue_word4__h3583, - x1_avValue_word4__h3800, - x__h4701, - x__h4967, - x__h5065, - x__h5274, - x__h5697; - wire [11 : 0] csraddr__h3479; - wire [4 : 0] td_rd__h3380, - td_rd__h3448, - x1_avValue_rd__h3423, - x1_avValue_rd__h3542, - x1_avValue_rd__h3579, - x1_avValue_rd__h3618, - x1_avValue_rd__h3656, - x1_avValue_rd__h3695, - x1_avValue_rd__h3796, - x1_avValue_rd__h3866; - wire [2 : 0] st_funct3__h346; + reg [63 : 0] x1_avValue_pc__h3546, x1_avValue_word1__h3550; + reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, + csr_addr__h5294; + reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5, + x1_avValue_rd__h3549; + reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3; + reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4; + wire [63 : 0] td_word2__h3586, + td_word2__h3737, + td_word3__h3587, + td_word3__h3951, + td_word4__h3474, + x1_avValue_pc__h3510, + x1_avValue_pc__h3816, + x1_avValue_pc__h3883, + x1_avValue_word1__h3596, + x1_avValue_word1__h3633, + x1_avValue_word1__h3709, + x1_avValue_word1__h3786, + x1_avValue_word1__h3887, + x1_avValue_word2__h3597, + x1_avValue_word2__h3710, + x1_avValue_word2__h3888, + x1_avValue_word3__h3598, + x1_avValue_word3__h3889, + x1_avValue_word3__h3931, + x1_avValue_word4__h3553, + x1_avValue_word4__h3673, + x1_avValue_word4__h3890, + x1_avValue_word4__h3932, + x__h4843, + x__h5134, + x__h5233, + x__h5443, + x__h5875; + wire [11 : 0] csraddr__h3569; + wire [4 : 0] td_rd__h3470, + td_rd__h3538, + x1_avValue_rd__h3513, + x1_avValue_rd__h3632, + x1_avValue_rd__h3669, + x1_avValue_rd__h3708, + x1_avValue_rd__h3746, + x1_avValue_rd__h3785, + x1_avValue_rd__h3886, + x1_avValue_rd__h3987; + wire [2 : 0] st_funct3__h348; // action method in_put assign RDY_in_put = f_in$FULL_N ; @@ -134,7 +137,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, assign WILL_FIRE_out_get = EN_out_get ; // submodule f_in - FIFO2 #(.width(32'd785), .guarded(32'd1)) f_in(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) f_in(.RST(RST_N), .CLK(CLK), .D_IN(f_in$D_IN), .ENQ(f_in$ENQ), @@ -161,14 +164,14 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_in assign f_in$D_IN = - { in_put[784:476], - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + { in_put[861:476], + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, in_put[463:462], in_put[462] ? - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 : - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 : + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, in_put[457:394], - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5, + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4, in_put[391:0] } ; assign f_in$ENQ = EN_in_put ; assign f_in$DEQ = CAN_FIRE_RL_rl_td2_to_td ; @@ -176,68 +179,70 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_out assign f_out$D_IN = - { f_in$D_OUT[784:721], - (f_in$D_OUT[784:721] == 64'd0) ? + { f_in$D_OUT[861:798], + (f_in$D_OUT[861:798] == 64'd0) ? 5'd0 : - (f_in$D_OUT[463] ? - 5'd14 : - ((f_in$D_OUT[393:392] == 2'd0 && - f_in$D_OUT[624:620] == 5'd10) ? - 5'd5 : + (f_in$D_OUT[797] ? + 5'd3 : + (f_in$D_OUT[463] ? + 5'd14 : ((f_in$D_OUT[393:392] == 2'd0 && - (f_in$D_OUT[624:620] == 5'd8 || - f_in$D_OUT[624:620] == 5'd9) || - f_in$D_OUT[624:620] == 5'd3 || - f_in$D_OUT[624:620] == 5'd11) ? - 5'd6 : - ((f_in$D_OUT[619] && f_in$D_OUT[618] && - f_in$D_OUT[624:620] == 5'd12) ? - 5'd8 : - ((f_in$D_OUT[624:620] == 5'd12) ? - 5'd7 : - ((f_in$D_OUT[393:392] == 2'd1 && - f_in$D_OUT[619] && - f_in$D_OUT[618] && - f_in$D_OUT[624:620] == 5'd4) ? - 5'd10 : + f_in$D_OUT[624:620] == 5'd10) ? + 5'd5 : + ((f_in$D_OUT[393:392] == 2'd0 && + (f_in$D_OUT[624:620] == 5'd8 || + f_in$D_OUT[624:620] == 5'd9) || + f_in$D_OUT[624:620] == 5'd3 || + f_in$D_OUT[624:620] == 5'd11) ? + 5'd6 : + ((f_in$D_OUT[619] && f_in$D_OUT[618] && + f_in$D_OUT[624:620] == 5'd12) ? + 5'd8 : + ((f_in$D_OUT[624:620] == 5'd12) ? + 5'd7 : ((f_in$D_OUT[393:392] == 2'd1 && + f_in$D_OUT[619] && + f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? - 5'd9 : + 5'd10 : ((f_in$D_OUT[393:392] == 2'd1 && - f_in$D_OUT[624:620] == 5'd5) ? - 5'd11 : - ((f_in$D_OUT[393:392] != 2'd0 && - f_in$D_OUT[393:392] != 2'd1 && - f_in$D_OUT[624:620] == 5'd13) ? - 5'd16 : - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1))))))))), - x__h4701, + f_in$D_OUT[624:620] == 5'd4) ? + 5'd9 : + ((f_in$D_OUT[393:392] == 2'd1 && + f_in$D_OUT[624:620] == 5'd5) ? + 5'd11 : + ((f_in$D_OUT[393:392] != 2'd0 && + f_in$D_OUT[393:392] != 2'd1 && + f_in$D_OUT[624:620] == 5'd13) ? + 5'd16 : + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5)))))))))), + x__h4843, f_in$D_OUT[626:625] == 2'b11, f_in$D_OUT[656:625], - x1_avValue_rd__h3866, - x__h4967, - x__h5065, - x__h5274, - x__h5697, + x1_avValue_rd__h3987, + x__h5134, + x__h5233, + x__h5443, + x__h5875, f_in$D_OUT[612:549] } ; - assign f_out$ENQ = f_in$EMPTY_N && f_out$FULL_N ; + assign f_out$ENQ = CAN_FIRE_RL_rl_td2_to_td ; assign f_out$DEQ = EN_out_get ; assign f_out$CLR = 1'b0 ; // remaining internal signals - assign csraddr__h3479 = f_in$D_OUT[476] ? csr_addr__h5126 : 12'd0 ; - assign st_funct3__h346 = + assign csraddr__h3569 = f_in$D_OUT[476] ? csr_addr__h5294 : 12'd0 ; + assign st_funct3__h348 = f_in$D_OUT[484] ? 3'b011 : (f_in$D_OUT[480] ? 3'b010 : (f_in$D_OUT[478] ? 3'b001 : 3'b0)) ; - assign td_rd__h3380 = + assign td_rd__h3470 = (f_in$D_OUT[619] && !f_in$D_OUT[618]) ? f_in$D_OUT[617:613] : 5'd0 ; - assign td_rd__h3448 = { 3'd0, f_in$D_OUT[257:256] } ; - assign td_word2__h3496 = + assign td_rd__h3538 = { 3'd0, f_in$D_OUT[257:256] } ; + assign td_word2__h3586 = (f_in$D_OUT[476] && (f_in$D_OUT[638:637] == 2'b01 || (f_in$D_OUT[638:637] == 2'b10 || @@ -245,150 +250,155 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[644:640] != 5'd0)) ? 64'd1 : 64'd0 ; - assign td_word2__h3647 = { 59'd0, f_in$D_OUT[327:323] } ; - assign td_word3__h3497 = { 52'd0, csraddr__h3479 } ; - assign td_word4__h3384 = { 61'd0, st_funct3__h346 } ; - assign x1_avValue_pc__h3420 = + assign td_word2__h3737 = { 59'd0, f_in$D_OUT[327:323] } ; + assign td_word3__h3587 = { 52'd0, csraddr__h3569 } ; + assign td_word3__h3951 = { 52'd0, f_in$D_OUT[796:785] } ; + assign td_word4__h3474 = { 61'd0, st_funct3__h348 } ; + assign x1_avValue_pc__h3510 = f_in$D_OUT[720:657] + ((f_in$D_OUT[626:625] == 2'b11) ? 64'd4 : 64'd2) ; - assign x1_avValue_pc__h3726 = + assign x1_avValue_pc__h3816 = (f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11 || f_in$D_OUT[624:620] == 5'd12 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5 || f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - x1_avValue_pc__h3420 : - x1_avValue_pc__h3456 ; - assign x1_avValue_pc__h3793 = + x1_avValue_pc__h3510 : + x1_avValue_pc__h3546 ; + assign x1_avValue_pc__h3883 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd10 || f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9)) ? f_in$D_OUT[391:328] : - x1_avValue_pc__h3726 ; - assign x1_avValue_rd__h3423 = td_rd__h3380 ; - assign x1_avValue_rd__h3542 = + x1_avValue_pc__h3816 ; + assign x1_avValue_rd__h3513 = td_rd__h3470 ; + assign x1_avValue_rd__h3632 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_rd__h3380 : - x1_avValue_rd__h3459 ; - assign x1_avValue_rd__h3579 = + td_rd__h3470 : + x1_avValue_rd__h3549 ; + assign x1_avValue_rd__h3669 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4) ? - td_rd__h3380 : - x1_avValue_rd__h3542 ; - assign x1_avValue_rd__h3618 = + td_rd__h3470 : + x1_avValue_rd__h3632 ; + assign x1_avValue_rd__h3708 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[617:613] : - x1_avValue_rd__h3579 ; - assign x1_avValue_rd__h3656 = + x1_avValue_rd__h3669 ; + assign x1_avValue_rd__h3746 = (f_in$D_OUT[624:620] == 5'd12) ? - td_rd__h3380 : - x1_avValue_rd__h3618 ; - assign x1_avValue_rd__h3695 = + td_rd__h3470 : + x1_avValue_rd__h3708 ; + assign x1_avValue_rd__h3785 = (f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd12) ? f_in$D_OUT[617:613] : - x1_avValue_rd__h3656 ; - assign x1_avValue_rd__h3796 = + x1_avValue_rd__h3746 ; + assign x1_avValue_rd__h3886 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9) || f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11) ? - td_rd__h3380 : - x1_avValue_rd__h3695 ; - assign x1_avValue_rd__h3866 = - f_in$D_OUT[463] ? td_rd__h3448 : x1_avValue_rd__h3796 ; - assign x1_avValue_word1__h3506 = + td_rd__h3470 : + x1_avValue_rd__h3785 ; + assign x1_avValue_rd__h3987 = + f_in$D_OUT[463] ? td_rd__h3538 : x1_avValue_rd__h3886 ; + assign x1_avValue_word1__h3596 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3460 ; - assign x1_avValue_word1__h3543 = + x1_avValue_word1__h3550 ; + assign x1_avValue_word1__h3633 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5) ? - td_word4__h3384 : - x1_avValue_word1__h3506 ; - assign x1_avValue_word1__h3619 = + td_word4__h3474 : + x1_avValue_word1__h3596 ; + assign x1_avValue_word1__h3709 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3543 ; - assign x1_avValue_word1__h3696 = + x1_avValue_word1__h3633 ; + assign x1_avValue_word1__h3786 = (f_in$D_OUT[624:620] == 5'd12) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3619 ; - assign x1_avValue_word1__h3797 = + x1_avValue_word1__h3709 ; + assign x1_avValue_word1__h3887 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9) || f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3696 ; - assign x1_avValue_word2__h3507 = + x1_avValue_word1__h3786 ; + assign x1_avValue_word2__h3597 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_word2__h3496 : + td_word2__h3586 : f_in$D_OUT[548:485] ; - assign x1_avValue_word2__h3620 = + assign x1_avValue_word2__h3710 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5) ? f_in$D_OUT[548:485] : - x1_avValue_word2__h3507 ; - assign x1_avValue_word2__h3798 = + x1_avValue_word2__h3597 ; + assign x1_avValue_word2__h3888 = (f_in$D_OUT[624:620] == 5'd12) ? - td_word2__h3647 : - x1_avValue_word2__h3620 ; - assign x1_avValue_word3__h3508 = + td_word2__h3737 : + x1_avValue_word2__h3710 ; + assign x1_avValue_word3__h3598 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_word3__h3497 : + td_word3__h3587 : f_in$D_OUT[391:328] ; - assign x1_avValue_word3__h3799 = + assign x1_avValue_word3__h3889 = (f_in$D_OUT[393:392] == 2'd1 && (f_in$D_OUT[624:620] == 5'd4 || f_in$D_OUT[624:620] == 5'd5)) ? f_in$D_OUT[391:328] : - x1_avValue_word3__h3508 ; - assign x1_avValue_word4__h3463 = td_word4__h3384 ; - assign x1_avValue_word4__h3583 = + x1_avValue_word3__h3598 ; + assign x1_avValue_word3__h3931 = + f_in$D_OUT[463] ? f_in$D_OUT[63:0] : x1_avValue_word3__h3889 ; + assign x1_avValue_word4__h3553 = td_word4__h3474 ; + assign x1_avValue_word4__h3673 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? f_in$D_OUT[391:328] : - x1_avValue_word4__h3463 ; - assign x1_avValue_word4__h3800 = + x1_avValue_word4__h3553 ; + assign x1_avValue_word4__h3890 = (f_in$D_OUT[624:620] == 5'd12 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[321:258] : - x1_avValue_word4__h3583 ; - assign x__h4701 = - f_in$D_OUT[463] ? f_in$D_OUT[255:192] : x1_avValue_pc__h3793 ; - assign x__h4967 = - f_in$D_OUT[463] ? f_in$D_OUT[191:128] : x1_avValue_word1__h3797 ; - assign x__h5065 = - f_in$D_OUT[463] ? f_in$D_OUT[127:64] : x1_avValue_word2__h3798 ; - assign x__h5274 = - f_in$D_OUT[463] ? f_in$D_OUT[63:0] : x1_avValue_word3__h3799 ; - assign x__h5697 = - f_in$D_OUT[463] ? f_in$D_OUT[457:394] : x1_avValue_word4__h3800 ; + x1_avValue_word4__h3673 ; + assign x1_avValue_word4__h3932 = + f_in$D_OUT[463] ? f_in$D_OUT[457:394] : x1_avValue_word4__h3890 ; + assign x__h4843 = + f_in$D_OUT[463] ? f_in$D_OUT[255:192] : x1_avValue_pc__h3883 ; + assign x__h5134 = + f_in$D_OUT[463] ? f_in$D_OUT[191:128] : x1_avValue_word1__h3887 ; + assign x__h5233 = + f_in$D_OUT[463] ? f_in$D_OUT[127:64] : x1_avValue_word2__h3888 ; + assign x__h5443 = + f_in$D_OUT[797] ? td_word3__h3951 : x1_avValue_word3__h3931 ; + assign x__h5875 = + f_in$D_OUT[797] ? f_in$D_OUT[784:721] : x1_avValue_word4__h3932 ; always@(f_in$D_OUT) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_word1__h3460 = f_in$D_OUT[191:128]; - default: x1_avValue_word1__h3460 = f_in$D_OUT[612:549]; + 5'd19, 5'd20: x1_avValue_word1__h3550 = f_in$D_OUT[191:128]; + default: x1_avValue_word1__h3550 = f_in$D_OUT[612:549]; endcase end - always@(f_in$D_OUT or x1_avValue_pc__h3420) + always@(f_in$D_OUT or x1_avValue_pc__h3510) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_pc__h3456 = f_in$D_OUT[720:657]; - default: x1_avValue_pc__h3456 = x1_avValue_pc__h3420; + 5'd19, 5'd20: x1_avValue_pc__h3546 = f_in$D_OUT[720:657]; + default: x1_avValue_pc__h3546 = x1_avValue_pc__h3510; endcase end - always@(f_in$D_OUT or x1_avValue_rd__h3423 or td_rd__h3448) + always@(f_in$D_OUT or x1_avValue_rd__h3513 or td_rd__h3538) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_rd__h3459 = td_rd__h3448; - default: x1_avValue_rd__h3459 = x1_avValue_rd__h3423; + 5'd19, 5'd20: x1_avValue_rd__h3549 = td_rd__h3538; + default: x1_avValue_rd__h3549 = x1_avValue_rd__h3513; endcase end always@(f_in$D_OUT) @@ -438,24 +448,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - csr_addr__h5126 = f_in$D_OUT[475:464]; - default: csr_addr__h5126 = 12'd2303; - endcase - end - always@(f_in$D_OUT) - begin - case (f_in$D_OUT[624:620]) - 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd5; - 5'd19, 5'd20: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd15; - default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = - (f_in$D_OUT[393:392] == 2'd1 && - (f_in$D_OUT[624:620] == 5'd2 || - f_in$D_OUT[624:620] == 5'd6 || - f_in$D_OUT[624:620] == 5'd7)) ? - 5'd13 : - 5'd5; + csr_addr__h5294 = f_in$D_OUT[475:464]; + default: csr_addr__h5294 = 12'd2303; endcase end always@(in_put) @@ -505,9 +499,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = in_put[475:464]; - default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = 12'd2303; endcase end @@ -515,9 +509,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin case (in_put[461:458]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = 4'd15; endcase end always@(in_put) @@ -536,18 +530,34 @@ module mkTrace_Data2_to_Trace_Data(CLK, 4'd11, 4'd12, 4'd13: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; endcase end always@(in_put) begin case (in_put[393:392]) 2'd0, 2'd1: - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = in_put[393:392]; - default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = 2'd2; + default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = 2'd2; + endcase + end + always@(f_in$D_OUT) + begin + case (f_in$D_OUT[624:620]) + 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd5; + 5'd19, 5'd20: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd15; + default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = + (f_in$D_OUT[393:392] == 2'd1 && + (f_in$D_OUT[624:620] == 5'd2 || + f_in$D_OUT[624:620] == 5'd6 || + f_in$D_OUT[624:620] == 5'd7)) ? + 5'd13 : + 5'd5; endcase end @@ -558,7 +568,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -588,7 +599,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $display(" fav_td2_to_td: TBD: Unknown iType: Using mkTrace_OTHER for now"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -618,7 +630,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -648,7 +661,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("Trace_Data2 { ", "serial_num: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -676,9 +690,196 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd0 && f_in$D_OUT[624:620] != 5'd1 && f_in$D_OUT[624:620] != 5'd21) - $write("'h%h", f_in$D_OUT[784:721]); + $write("'h%h", f_in$D_OUT[861:798]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(", ", "maybe_csr_upd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -708,7 +909,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "pc: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -738,7 +940,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[720:657]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -768,7 +971,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "orig_inst: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -798,7 +1002,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[656:625]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -828,13 +1033,15 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "iType: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd2) $write("Amo"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || !f_in$D_OUT[618]) && @@ -842,49 +1049,57 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] == 5'd4) $write("Ld"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd5) $write("St"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd6) $write("Lr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd7) $write("Sc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd8) $write("J"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd9) $write("Jr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd10) $write("Br"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1) && f_in$D_OUT[624:620] == 5'd13) $write("Csr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -910,7 +1125,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd13) $write("Interrupt"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -940,7 +1156,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "dst: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -970,7 +1187,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[619]) $write("tagged Valid "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -998,7 +1216,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[619]) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1027,7 +1246,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[618]) $write("tagged Fpu ", "'h%h", f_in$D_OUT[617:613]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1056,7 +1276,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[618]) $write("tagged Gpr ", "'h%h", f_in$D_OUT[617:613]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1084,7 +1305,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[619]) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1114,7 +1336,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "dst_data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1144,7 +1367,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[612:549]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1174,7 +1398,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "store_data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1204,7 +1429,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[548:485]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1234,7 +1460,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "store_data_BE: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1264,7 +1491,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2090,7 +2344,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "csr: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2121,7 +2376,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[476]) $write("tagged Valid "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2152,7 +2408,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[476]) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2184,7 +2441,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1) $write("CSRfflags"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2216,7 +2474,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2) $write("CSRfrm"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2248,7 +2507,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3) $write("CSRfcsr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2280,7 +2540,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3072) $write("CSRcycle"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2312,7 +2573,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3073) $write("CSRtime"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2344,7 +2606,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3074) $write("CSRinstret"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2376,7 +2639,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2048) $write("CSRterminate"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2408,7 +2672,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2049) $write("CSRstats"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2440,7 +2705,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd256) $write("CSRsstatus"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2472,7 +2738,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd260) $write("CSRsie"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2504,7 +2771,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd261) $write("CSRstvec"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2536,7 +2804,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd262) $write("CSRscounteren"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2568,7 +2837,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd320) $write("CSRsscratch"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2600,7 +2870,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd321) $write("CSRsepc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2632,7 +2903,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd322) $write("CSRscause"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2664,7 +2936,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd323) $write("CSRstval"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2696,7 +2969,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd324) $write("CSRsip"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2728,7 +3002,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd384) $write("CSRsatp"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2760,7 +3035,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd768) $write("CSRmstatus"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2792,7 +3068,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd769) $write("CSRmisa"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2824,7 +3101,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd770) $write("CSRmedeleg"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2856,7 +3134,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd771) $write("CSRmideleg"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2888,7 +3167,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd772) $write("CSRmie"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2920,7 +3200,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd773) $write("CSRmtvec"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2952,7 +3233,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd774) $write("CSRmcounteren"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2984,7 +3266,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd832) $write("CSRmscratch"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3016,7 +3299,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd833) $write("CSRmepc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3048,7 +3332,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd834) $write("CSRmcause"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3080,7 +3365,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd835) $write("CSRmtval"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3112,7 +3398,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd836) $write("CSRmip"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3144,7 +3431,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2816) $write("CSRmcycle"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3176,7 +3464,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2818) $write("CSRminstret"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3208,7 +3497,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3857) $write("CSRmvendorid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3240,7 +3530,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3858) $write("CSRmarchid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3272,7 +3563,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3859) $write("CSRmimpid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3304,7 +3596,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3860) $write("CSRmhartid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3336,7 +3629,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1952) $write("CSRtselect"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3368,7 +3662,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1953) $write("CSRtdata1"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3400,7 +3695,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1954) $write("CSRtdata2"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3432,7 +3728,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1955) $write("CSRtdata3"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3464,7 +3761,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1968) $write("CSRdcsr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3496,7 +3794,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1969) $write("CSRdpc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3528,7 +3827,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1970) $write("CSRdscratch0"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3560,7 +3860,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1971) $write("CSRdscratch1"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3635,7 +3936,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] != 12'd1971) $write("CSRnone"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3666,7 +3968,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[476]) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3696,7 +3999,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "trap: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3726,7 +4030,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3756,7 +4061,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3786,7 +4092,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3816,7 +4123,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3846,7 +4154,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "tval: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3876,7 +4185,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[457:394]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3906,7 +4216,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "ppc_vaddr_csrData: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd10 && f_in$D_OUT[624:620] != 5'd8 && @@ -3927,7 +4238,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] == 2'd0) $write("tagged PPC ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -3952,7 +4264,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] == 2'd1) $write("tagged VAddr ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -3972,7 +4285,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] != 2'd1) $write("tagged CSRData ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4002,7 +4316,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "fflags: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4032,7 +4347,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[327:323]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4062,7 +4378,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "will_dirty_fpu_state: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4093,7 +4410,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[322]) $write("True"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4124,7 +4442,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[322]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4154,7 +4473,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "mstatus: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4184,7 +4504,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[321:258]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4214,7 +4535,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "prv: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4244,7 +4566,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[257:256]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4274,7 +4597,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "tvec: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4304,7 +4628,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[255:192]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4334,7 +4659,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "status: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4364,7 +4690,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[191:128]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4394,7 +4721,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "cause: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4424,7 +4752,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[127:64]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4454,7 +4783,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "epc: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4484,7 +4814,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[63:0], " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 07e8558..4a78ad7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -98,9 +98,9 @@ // RDY_hart0_csr_mem_server_request_put O 1 reg // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg -// v_to_TV_0_get O 785 +// v_to_TV_0_get O 862 // RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 785 +// v_to_TV_1_get O 862 // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset @@ -668,16 +668,16 @@ module mkCore(CLK, // actionvalue method v_to_TV_0_get input EN_v_to_TV_0_get; - output [784 : 0] v_to_TV_0_get; + output [861 : 0] v_to_TV_0_get; output RDY_v_to_TV_0_get; // actionvalue method v_to_TV_1_get input EN_v_to_TV_1_get; - output [784 : 0] v_to_TV_1_get; + output [861 : 0] v_to_TV_1_get; output RDY_v_to_TV_1_get; // signals for module outputs - wire [784 : 0] v_to_TV_0_get, v_to_TV_1_get; + wire [861 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first; wire [162 : 0] deadlock_commitInstStuck_get, deadlock_commitUserInstStuck_get; @@ -845,6 +845,11 @@ module mkCore(CLK, wire commitStage_rg_just_after_reset$D_IN, commitStage_rg_just_after_reset$EN; + // register commitStage_rg_old_mip_csr_val + reg [63 : 0] commitStage_rg_old_mip_csr_val; + wire [63 : 0] commitStage_rg_old_mip_csr_val$D_IN; + wire commitStage_rg_old_mip_csr_val$EN; + // register commitStage_rg_run_state reg commitStage_rg_run_state; wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN; @@ -3747,8 +3752,8 @@ module mkCore(CLK, specTagManager$specUpdate_incorrectSpeculation_kill_all; // ports of submodule v_f_to_TV_0 - reg [784 : 0] v_f_to_TV_0$D_IN; - wire [784 : 0] v_f_to_TV_0$D_OUT; + reg [861 : 0] v_f_to_TV_0$D_IN; + wire [861 : 0] v_f_to_TV_0$D_OUT; wire v_f_to_TV_0$CLR, v_f_to_TV_0$DEQ, v_f_to_TV_0$EMPTY_N, @@ -3756,7 +3761,7 @@ module mkCore(CLK, v_f_to_TV_0$FULL_N; // ports of submodule v_f_to_TV_1 - wire [784 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT; + wire [861 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT; wire v_f_to_TV_1$CLR, v_f_to_TV_1$DEQ, v_f_to_TV_1$EMPTY_N, @@ -3772,6 +3777,7 @@ module mkCore(CLK, CAN_FIRE_RL_commitStage_doSetLSQAtCommit, CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1, CAN_FIRE_RL_commitStage_notifyLSQCommit, + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv, CAN_FIRE_RL_commitStage_rl_send_tv_reset, CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu, CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu, @@ -4008,6 +4014,7 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doSetLSQAtCommit, WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1, WILL_FIRE_RL_commitStage_notifyLSQCommit, + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv, WILL_FIRE_RL_commitStage_rl_send_tv_reset, WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu, WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu, @@ -4244,9 +4251,10 @@ module mkCore(CLK, reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1, MUX_coreFix_memExe_lsq$respLd_1__VAL_2; reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3; - wire [784 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1, + wire [861 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1, MUX_v_f_to_TV_0$enq_1__VAL_2, - MUX_v_f_to_TV_0$enq_1__VAL_4; + MUX_v_f_to_TV_0$enq_1__VAL_4, + MUX_v_f_to_TV_0$enq_1__VAL_5; wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2, MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3, @@ -4324,7 +4332,7 @@ module mkCore(CLK, MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3; wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1; wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1, - MUX_rob$setExecuted_deqLSQ_2__VAL_3, + MUX_rob$setExecuted_deqLSQ_2__VAL_2, MUX_rob$setExecuted_deqLSQ_2__VAL_6, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2, MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3, @@ -4339,6 +4347,7 @@ module mkCore(CLK, MUX_csrf_prv_reg$write_1__VAL_1; wire MUX_commitStage_rg_run_state$write_1__SEL_1, MUX_commitStage_rg_serial_num$write_1__SEL_1, + MUX_commitStage_rg_serial_num$write_1__SEL_2, MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1, MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3, MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1, @@ -4455,7 +4464,7 @@ module mkCore(CLK, MUX_csrf_stvec_base_hi_reg$write_1__SEL_1, MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2, MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2, - MUX_flush_reservation$write_1__SEL_2, + MUX_flush_reservation$write_1__SEL_1, MUX_flush_tlbs$write_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_1, MUX_regRenamingTable$rename_0_getRename_1__SEL_2, @@ -4471,7 +4480,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__SEL_5, MUX_rf$write_3_wr_2__SEL_5, MUX_rg_core_run_state$write_1__SEL_4, - MUX_rob$setExecuted_deqLSQ_1__SEL_5, + MUX_rob$setExecuted_deqLSQ_1__SEL_1, MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5, MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5, MUX_sbAggr$setReady_4_put_1__SEL_1, @@ -4479,7 +4488,6 @@ module mkCore(CLK, MUX_sbCons$setReady_3_put_1__SEL_1, MUX_sbCons$setReady_3_put_1__SEL_2, MUX_sbCons$setReady_3_put_1__SEL_3, - MUX_started$write_1__SEL_1, MUX_v_f_to_TV_0$enq_1__SEL_2; // remaining internal signals @@ -4490,52 +4498,52 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875, - addr__h290066, - curData__h192915, - data_out__h736609, - data_warl_xformed__h721446, - rVal1__h609049, - rVal1__h633777, - trap_val__h709502, - x__h197125, - x__h722034; - reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, + addr__h290067, + curData__h192916, + data_out__h737644, + data_warl_xformed__h722429, + rVal1__h609051, + rVal1__h633779, + trap_val__h710482, + x__h197126, + x__h723033; + reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217, - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218, - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219, - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220, - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205, - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206, - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207, - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208, - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209, - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210, - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221, - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222, - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223, - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224, - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225, - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226, - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215, - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216, + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217, + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218, + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219, + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220, + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205, + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206, + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209, + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210, + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221, + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222, + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223, + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224, + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225, + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226, + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215, + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4547,50 +4555,50 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82, - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83, - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86, - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87, - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88, - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89, - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119, - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120, - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49, - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50, - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117, - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118, - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47, - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48, - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121, - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122, - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51, - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52, - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124, - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125, - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53, - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54, - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84, - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85, - _theResult___fst_sfd__h346067, - _theResult___fst_sfd__h354790, - _theResult___fst_sfd__h363372, - _theResult___fst_sfd__h372556, - _theResult___fst_sfd__h381192, - _theResult___fst_sfd__h391766, - _theResult___fst_sfd__h400487, - _theResult___fst_sfd__h409069, - _theResult___fst_sfd__h418253, - _theResult___fst_sfd__h426889, - _theResult___fst_sfd__h437461, - _theResult___fst_sfd__h446182, - _theResult___fst_sfd__h454764, - _theResult___fst_sfd__h463948, - _theResult___fst_sfd__h472584; + reg [22 : 0] CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82, + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83, + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86, + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87, + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88, + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89, + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119, + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120, + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49, + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50, + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117, + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118, + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47, + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48, + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121, + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122, + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51, + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52, + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123, + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124, + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53, + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54, + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84, + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85, + _theResult___fst_sfd__h346068, + _theResult___fst_sfd__h354791, + _theResult___fst_sfd__h363373, + _theResult___fst_sfd__h372557, + _theResult___fst_sfd__h381193, + _theResult___fst_sfd__h391767, + _theResult___fst_sfd__h400488, + _theResult___fst_sfd__h409070, + _theResult___fst_sfd__h418254, + _theResult___fst_sfd__h426890, + _theResult___fst_sfd__h437462, + _theResult___fst_sfd__h446183, + _theResult___fst_sfd__h454765, + _theResult___fst_sfd__h463949, + _theResult___fst_sfd__h472585; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294, @@ -4598,40 +4606,40 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407; - reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277, + reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289, CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235, - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255, + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246, CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973; - reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, + reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211, - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212, - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213, - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214, - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183, - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184, - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185, - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186, - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187, - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188, - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160, - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161, - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189, - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190, - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191, - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192, - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143, - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144, + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211, + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212, + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213, + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214, + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183, + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184, + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185, + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186, + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187, + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188, + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160, + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161, + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189, + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190, + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191, + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192, + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143, + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573, @@ -4641,62 +4649,62 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803; - reg [7 : 0] CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67, - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68, - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75, - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76, - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80, - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81, - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104, - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105, - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34, - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35, - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102, - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103, - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32, - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33, - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110, - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111, - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40, - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41, - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115, - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116, - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45, - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46, - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69, - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70, + reg [7 : 0] CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67, + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68, + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75, + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76, + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80, + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81, + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104, + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105, + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34, + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35, + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102, + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103, + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32, + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33, + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110, + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111, + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40, + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41, + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115, + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116, + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45, + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46, + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69, + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h346066, - _theResult___fst_exp__h354789, - _theResult___fst_exp__h363371, - _theResult___fst_exp__h372555, - _theResult___fst_exp__h381191, - _theResult___fst_exp__h391765, - _theResult___fst_exp__h400486, - _theResult___fst_exp__h409068, - _theResult___fst_exp__h418252, - _theResult___fst_exp__h426888, - _theResult___fst_exp__h437460, - _theResult___fst_exp__h446181, - _theResult___fst_exp__h454763, - _theResult___fst_exp__h463947, - _theResult___fst_exp__h472583; + _theResult___fst_exp__h346067, + _theResult___fst_exp__h354790, + _theResult___fst_exp__h363372, + _theResult___fst_exp__h372556, + _theResult___fst_exp__h381192, + _theResult___fst_exp__h391766, + _theResult___fst_exp__h400487, + _theResult___fst_exp__h409069, + _theResult___fst_exp__h418253, + _theResult___fst_exp__h426889, + _theResult___fst_exp__h437461, + _theResult___fst_exp__h446182, + _theResult___fst_exp__h454764, + _theResult___fst_exp__h463948, + _theResult___fst_exp__h472584; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274, - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973; + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983; reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14128, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14261; reg [3 : 0] CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234, - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278, - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279, + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250, + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20, CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252, - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253, + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278, + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247, + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6, CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7, CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2, @@ -4704,30 +4712,30 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262, - i__h708478, - i__h708638; + i__h709458, + i__h709618; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284, - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227, + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290, - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287, CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297, - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717, - x__h285845, - x__h291615; - reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265, + x__h285846, + x__h291616; + reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, + CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8, CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4; @@ -4746,58 +4754,58 @@ module mkCore(CLK, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244, - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243, + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244, CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241, CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126, - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123, - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127, - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463, @@ -4869,23 +4877,24 @@ module mkCore(CLK, wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945; wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057; - wire [457 : 0] IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070; + wire [463 : 0] commitStage_f_rob_data_first__4755_BIT_167_485_ETC___d14927; + wire [457 : 0] rob_deqPort_0_deq_data__4339_BITS_161_TO_98_43_ETC___d15292; wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008; - wire [393 : 0] IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281; + wire [393 : 0] IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926; wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061; wire [321 : 0] basicExec___d11943, basicExec___d12617; wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003; wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16052; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706; wire [68 : 0] execFpuSimple___d11056; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627, - IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501; + IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448, @@ -4917,167 +4926,167 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180, - _theResult___fst__h603369, - _theResult___snd__h603370, - a___1__h603088, - a___1__h603374, - a__h602947, + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191, + _theResult___fst__h603370, + _theResult___snd__h603371, + a___1__h603089, + a___1__h603375, + a__h602948, amoExec___d880, - b___1__h603089, - b___1__h603419, - b__h602948, - base__h711423, - base__h711443, - commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438, - data___1__h475007, - data___1__h475815, - data__h475281, - fcsr_csr__read__h609375, - fflags_csr__read__h609350, - frm_csr__read__h609361, - mcause_csr__read__h611017, - mcounteren_csr__read__h610762, - medeleg_csr__read__h610369, - mideleg_csr__read__h610464, - mie_csr__read__h610588, - mip_csr__read__h611250, - mstatus_csr__read__h610221, - mtvec_csr__read__h610670, - n___1__h198528, - n__h194453, - n__read__h611354, - n__read__h611545, + b___1__h603090, + b___1__h603420, + b__h602949, + base__h712403, + base__h712423, + commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450, + data___1__h475008, + data___1__h475816, + data__h475282, + fcsr_csr__read__h609377, + fflags_csr__read__h609352, + frm_csr__read__h609363, + mcause_csr__read__h611019, + mcounteren_csr__read__h610764, + medeleg_csr__read__h610371, + mideleg_csr__read__h610466, + mie_csr__read__h610590, + mip_csr__read__h611252, + mstatus_csr__read__h610223, + mtvec_csr__read__h610672, + n___1__h198529, + n__h194454, + n__read__h611356, + n__read__h611547, n__read__h6759, - n__read__h725937, - next_pc__h721469, - pc__h711407, - q___1__h475880, - rVal1__h481760, - rVal2__h481761, - r___1__h475906, - res_data__h337868, - res_data__h337873, - res_data__h383570, - res_data__h383575, - res_data__h429265, - res_data__h429270, - resp_addr__h291970, - rg_tdata1__read__h612205, + n__read__h726937, + next_pc__h722452, + pc__h712387, + q___1__h475881, + rVal1__h481761, + rVal2__h481762, + r___1__h475907, + res_data__h337869, + res_data__h337874, + res_data__h383571, + res_data__h383576, + res_data__h429266, + res_data__h429271, + resp_addr__h291971, + rg_tdata1__read__h612207, robdeqPort_0_deq_data_BITS_95_TO_32__q245, - satp_csr__read__h610078, - scause_csr__read__h609875, - scounteren_csr__read__h609737, - shiftData__h181566, - sie_csr__read__h609641, - sip_csr__read__h610015, - sstatus_csr__read__h609571, - stvec_csr__read__h609684, - trap_val__h708464, + satp_csr__read__h610080, + scause_csr__read__h609877, + scounteren_csr__read__h609739, + shiftData__h181567, + sie_csr__read__h609643, + sip_csr__read__h610017, + sstatus_csr__read__h609573, + stvec_csr__read__h609686, + trap_val__h709444, upd__h3993, upd__h5310, upd__h6873, - upd__h726048, - v__h607933, - v__h632816, - x__h153730, - x__h157277, - x__h160091, - x__h161939, - x__h181475, + upd__h727048, + v__h607935, + v__h632818, + x__h153731, + x__h157278, + x__h160092, + x__h161940, x__h181476, - x__h18384, - x__h183901, - x__h20922, - x__h287290, - x__h289144, - x__h46291, - x__h481669, + x__h181477, + x__h18385, + x__h183902, + x__h20923, + x__h287291, + x__h289145, + x__h46292, x__h481670, x__h481671, - x__h48827, - x__h617230, - x__h617231, - x__h639739, - x__h639740, - x__h701397, - x__h713649, - x__h713841, - x__h725432, - x__h728883, - x__h732011, - x_addr__h314073, - x_quotient__h475195, - x_reg_ifc__read__h609480, - x_remainder__h475196, - y__h729714, - y__h732518, - y_avValue__h180563, - y_avValue__h181169, - y_avValue__h478805, - y_avValue__h479413, - y_avValue__h480015, - y_avValue__h608839, - y_avValue__h615055, - y_avValue__h633569, - y_avValue__h637574, - y_avValue_new_pc__h711199, - y_avValue_new_pc__h711385, - y_avValue_snd_snd_snd_snd_snd_fst__h729737, - y_avValue_snd_snd_snd_snd_snd_fst__h732579, - y_avValue_snd_snd_snd_snd_snd_fst__h732615, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993; + x__h481672, + x__h48828, + x__h617232, + x__h617233, + x__h639741, + x__h639742, + x__h702377, + x__h714645, + x__h714837, + x__h726431, + x__h729900, + x__h733045, + x_addr__h314074, + x_quotient__h475196, + x_reg_ifc__read__h609482, + x_remainder__h475197, + y__h730732, + y__h733553, + y_avValue__h180564, + y_avValue__h181170, + y_avValue__h478806, + y_avValue__h479414, + y_avValue__h480016, + y_avValue__h608841, + y_avValue__h615057, + y_avValue__h633571, + y_avValue__h637576, + y_avValue_new_pc__h712179, + y_avValue_new_pc__h712365, + y_avValue_snd_snd_snd_snd_snd_fst__h730755, + y_avValue_snd_snd_snd_snd_snd_fst__h733614, + y_avValue_snd_snd_snd_snd_snd_fst__h733650, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882, - IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909, - r1__read__h613048, - r1__read__h613452, - r1__read__h613962, - r1__read__h613967, - r1__read__h613986, - r1__read__h614219, - r1__read__h614385, - r1__read__h614478, - r1__read__h614483, - r1__read__h614502; - wire [61 : 0] r1__read__h613050, + IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920, + r1__read__h613050, r1__read__h613454, + r1__read__h613964, r1__read__h613969, r1__read__h613988, r1__read__h614221, - r1__read__h614361, r1__read__h614387, + r1__read__h614480, r1__read__h614485, r1__read__h614504; - wire [60 : 0] r1__read__h614223, + wire [61 : 0] r1__read__h613052, + r1__read__h613456, + r1__read__h613971, + r1__read__h613990, + r1__read__h614223, r1__read__h614363, r1__read__h614389, + r1__read__h614487, r1__read__h614506; - wire [59 : 0] r1__read__h613052, - r1__read__h613456, - r1__read__h613980, - r1__read__h613990, - r1__read__h614225, + wire [60 : 0] r1__read__h614225, + r1__read__h614365, r1__read__h614391, - r1__read__h614496, r1__read__h614508; - wire [58 : 0] r1__read__h613054, + wire [59 : 0] r1__read__h613054, r1__read__h613458, + r1__read__h613982, r1__read__h613992, r1__read__h614227, r1__read__h614393, + r1__read__h614498, r1__read__h614510; - wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550, - IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012, - IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, - r1__read__h613056, + wire [58 : 0] r1__read__h613056, r1__read__h613460, r1__read__h613994, r1__read__h614229, - r1__read__h614365, r1__read__h614395, - r1__read__h614512, - y__h254802; + r1__read__h614512; + wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550, + IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012, + IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, + r1__read__h613058, + r1__read__h613462, + r1__read__h613996, + r1__read__h614231, + r1__read__h614367, + r1__read__h614397, + r1__read__h614514, + y__h254803; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98, @@ -5105,187 +5114,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342, - _theResult____h346084, - _theResult____h363723, - _theResult____h391783, - _theResult____h409420, - _theResult____h437478, - _theResult____h455115, - _theResult____h502868, - _theResult____h541721, - _theResult____h581025, - _theResult___snd__h354206, - _theResult___snd__h354217, - _theResult___snd__h354219, - _theResult___snd__h354229, - _theResult___snd__h354235, - _theResult___snd__h354258, - _theResult___snd__h362802, - _theResult___snd__h362804, - _theResult___snd__h362811, - _theResult___snd__h362817, - _theResult___snd__h362840, - _theResult___snd__h371972, - _theResult___snd__h371983, - _theResult___snd__h371985, - _theResult___snd__h371995, - _theResult___snd__h372001, - _theResult___snd__h372024, - _theResult___snd__h380592, - _theResult___snd__h380606, - _theResult___snd__h380612, - _theResult___snd__h380630, - _theResult___snd__h399903, - _theResult___snd__h399914, - _theResult___snd__h399916, - _theResult___snd__h399926, - _theResult___snd__h399932, - _theResult___snd__h399955, - _theResult___snd__h408499, - _theResult___snd__h408501, - _theResult___snd__h408508, - _theResult___snd__h408514, - _theResult___snd__h408537, - _theResult___snd__h417669, - _theResult___snd__h417680, - _theResult___snd__h417682, - _theResult___snd__h417692, - _theResult___snd__h417698, - _theResult___snd__h417721, - _theResult___snd__h426289, - _theResult___snd__h426303, - _theResult___snd__h426309, - _theResult___snd__h426327, - _theResult___snd__h445598, - _theResult___snd__h445609, - _theResult___snd__h445611, - _theResult___snd__h445621, - _theResult___snd__h445627, - _theResult___snd__h445650, - _theResult___snd__h454194, - _theResult___snd__h454196, - _theResult___snd__h454203, - _theResult___snd__h454209, - _theResult___snd__h454232, - _theResult___snd__h463364, - _theResult___snd__h463375, - _theResult___snd__h463377, - _theResult___snd__h463387, - _theResult___snd__h463393, - _theResult___snd__h463416, - _theResult___snd__h471984, - _theResult___snd__h471998, - _theResult___snd__h472004, - _theResult___snd__h472022, - _theResult___snd__h501478, - _theResult___snd__h501480, - _theResult___snd__h501487, - _theResult___snd__h501493, - _theResult___snd__h501516, - _theResult___snd__h511115, - _theResult___snd__h511126, - _theResult___snd__h511128, - _theResult___snd__h511138, - _theResult___snd__h511144, - _theResult___snd__h511167, - _theResult___snd__h519883, - _theResult___snd__h519897, - _theResult___snd__h519903, - _theResult___snd__h519921, - _theResult___snd__h540331, - _theResult___snd__h540333, - _theResult___snd__h540340, - _theResult___snd__h540346, - _theResult___snd__h540369, - _theResult___snd__h549968, - _theResult___snd__h549979, - _theResult___snd__h549981, - _theResult___snd__h549991, - _theResult___snd__h549997, - _theResult___snd__h550020, - _theResult___snd__h558736, - _theResult___snd__h558750, - _theResult___snd__h558756, - _theResult___snd__h558774, - _theResult___snd__h579635, - _theResult___snd__h579637, - _theResult___snd__h579644, - _theResult___snd__h579650, - _theResult___snd__h579673, - _theResult___snd__h589272, - _theResult___snd__h589283, - _theResult___snd__h589285, - _theResult___snd__h589295, - _theResult___snd__h589301, - _theResult___snd__h589324, - _theResult___snd__h598040, - _theResult___snd__h598054, - _theResult___snd__h598060, - _theResult___snd__h598078, - r1__read__h614231, - r1__read__h614367, - r1__read__h614397, - r1__read__h614514, - result__h364336, - result__h410033, - result__h455728, - result__h503481, - result__h542334, - result__h581638, - sfd__h338479, - sfd__h384181, - sfd__h429876, - sfd__h482501, - sfd__h521495, - sfd__h560799, - sfdin__h354189, - sfdin__h371955, - sfdin__h399886, - sfdin__h417652, - sfdin__h445581, - sfdin__h463347, - sfdin__h511098, - sfdin__h549951, - sfdin__h589255, - x__h364433, - x__h410130, - x__h455825, - x__h503576, - x__h542429, - x__h581733; - wire [55 : 0] r1__read__h613058, - r1__read__h613462, - r1__read__h613996, + _theResult____h346085, + _theResult____h363724, + _theResult____h391784, + _theResult____h409421, + _theResult____h437479, + _theResult____h455116, + _theResult____h502869, + _theResult____h541722, + _theResult____h581026, + _theResult___snd__h354207, + _theResult___snd__h354218, + _theResult___snd__h354220, + _theResult___snd__h354230, + _theResult___snd__h354236, + _theResult___snd__h354259, + _theResult___snd__h362803, + _theResult___snd__h362805, + _theResult___snd__h362812, + _theResult___snd__h362818, + _theResult___snd__h362841, + _theResult___snd__h371973, + _theResult___snd__h371984, + _theResult___snd__h371986, + _theResult___snd__h371996, + _theResult___snd__h372002, + _theResult___snd__h372025, + _theResult___snd__h380593, + _theResult___snd__h380607, + _theResult___snd__h380613, + _theResult___snd__h380631, + _theResult___snd__h399904, + _theResult___snd__h399915, + _theResult___snd__h399917, + _theResult___snd__h399927, + _theResult___snd__h399933, + _theResult___snd__h399956, + _theResult___snd__h408500, + _theResult___snd__h408502, + _theResult___snd__h408509, + _theResult___snd__h408515, + _theResult___snd__h408538, + _theResult___snd__h417670, + _theResult___snd__h417681, + _theResult___snd__h417683, + _theResult___snd__h417693, + _theResult___snd__h417699, + _theResult___snd__h417722, + _theResult___snd__h426290, + _theResult___snd__h426304, + _theResult___snd__h426310, + _theResult___snd__h426328, + _theResult___snd__h445599, + _theResult___snd__h445610, + _theResult___snd__h445612, + _theResult___snd__h445622, + _theResult___snd__h445628, + _theResult___snd__h445651, + _theResult___snd__h454195, + _theResult___snd__h454197, + _theResult___snd__h454204, + _theResult___snd__h454210, + _theResult___snd__h454233, + _theResult___snd__h463365, + _theResult___snd__h463376, + _theResult___snd__h463378, + _theResult___snd__h463388, + _theResult___snd__h463394, + _theResult___snd__h463417, + _theResult___snd__h471985, + _theResult___snd__h471999, + _theResult___snd__h472005, + _theResult___snd__h472023, + _theResult___snd__h501479, + _theResult___snd__h501481, + _theResult___snd__h501488, + _theResult___snd__h501494, + _theResult___snd__h501517, + _theResult___snd__h511116, + _theResult___snd__h511127, + _theResult___snd__h511129, + _theResult___snd__h511139, + _theResult___snd__h511145, + _theResult___snd__h511168, + _theResult___snd__h519884, + _theResult___snd__h519898, + _theResult___snd__h519904, + _theResult___snd__h519922, + _theResult___snd__h540332, + _theResult___snd__h540334, + _theResult___snd__h540341, + _theResult___snd__h540347, + _theResult___snd__h540370, + _theResult___snd__h549969, + _theResult___snd__h549980, + _theResult___snd__h549982, + _theResult___snd__h549992, + _theResult___snd__h549998, + _theResult___snd__h550021, + _theResult___snd__h558737, + _theResult___snd__h558751, + _theResult___snd__h558757, + _theResult___snd__h558775, + _theResult___snd__h579636, + _theResult___snd__h579638, + _theResult___snd__h579645, + _theResult___snd__h579651, + _theResult___snd__h579674, + _theResult___snd__h589273, + _theResult___snd__h589284, + _theResult___snd__h589286, + _theResult___snd__h589296, + _theResult___snd__h589302, + _theResult___snd__h589325, + _theResult___snd__h598041, + _theResult___snd__h598055, + _theResult___snd__h598061, + _theResult___snd__h598079, r1__read__h614233, + r1__read__h614369, r1__read__h614399, - r1__read__h614516; - wire [54 : 0] r1__read__h613060, + r1__read__h614516, + result__h364337, + result__h410034, + result__h455729, + result__h503482, + result__h542335, + result__h581639, + sfd__h338480, + sfd__h384182, + sfd__h429877, + sfd__h482502, + sfd__h521496, + sfd__h560800, + sfdin__h354190, + sfdin__h371956, + sfdin__h399887, + sfdin__h417653, + sfdin__h445582, + sfdin__h463348, + sfdin__h511099, + sfdin__h549952, + sfdin__h589256, + x__h364434, + x__h410131, + x__h455826, + x__h503577, + x__h542430, + x__h581734; + wire [55 : 0] r1__read__h613060, r1__read__h613464, r1__read__h613998, r1__read__h614235, r1__read__h614401, r1__read__h614518; - wire [53 : 0] r1__read__h614344, - r1__read__h614369, + wire [54 : 0] r1__read__h613062, + r1__read__h613466, + r1__read__h614000, + r1__read__h614237, r1__read__h614403, - r1__read__h614520, - sfd__h501545, - sfd__h511196, - sfd__h519956, - sfd__h540398, - sfd__h550049, - sfd__h558809, - sfd__h579702, - sfd__h589353, - sfd__h598113, - value__h346706, - value__h392403, - value__h438098; - wire [52 : 0] r1__read__h614237, - r1__read__h614346, + r1__read__h614520; + wire [53 : 0] r1__read__h614346, r1__read__h614371, r1__read__h614405, - r1__read__h614522; + r1__read__h614522, + sfd__h501546, + sfd__h511197, + sfd__h519957, + sfd__h540399, + sfd__h550050, + sfd__h558810, + sfd__h579703, + sfd__h589354, + sfd__h598114, + value__h346707, + value__h392404, + value__h438099; + wire [52 : 0] r1__read__h614239, + r1__read__h614348, + r1__read__h614373, + r1__read__h614407, + r1__read__h614524; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140, @@ -5307,111 +5316,111 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881, - _theResult___fst_sfd__h486455, - _theResult___fst_sfd__h502283, - _theResult___fst_sfd__h502286, - _theResult___fst_sfd__h511934, - _theResult___fst_sfd__h511937, - _theResult___fst_sfd__h520718, - _theResult___fst_sfd__h520721, - _theResult___fst_sfd__h520730, - _theResult___fst_sfd__h520736, - _theResult___fst_sfd__h525308, - _theResult___fst_sfd__h541136, - _theResult___fst_sfd__h541139, - _theResult___fst_sfd__h550787, - _theResult___fst_sfd__h550790, - _theResult___fst_sfd__h559571, - _theResult___fst_sfd__h559574, - _theResult___fst_sfd__h559583, - _theResult___fst_sfd__h559589, - _theResult___fst_sfd__h564612, - _theResult___fst_sfd__h580440, - _theResult___fst_sfd__h580443, - _theResult___fst_sfd__h590091, - _theResult___fst_sfd__h590094, - _theResult___fst_sfd__h598875, - _theResult___fst_sfd__h598878, - _theResult___fst_sfd__h598887, - _theResult___fst_sfd__h598893, - _theResult___sfd__h502183, - _theResult___sfd__h511834, - _theResult___sfd__h520618, - _theResult___sfd__h541036, - _theResult___sfd__h550687, - _theResult___sfd__h559471, - _theResult___sfd__h580340, - _theResult___sfd__h589991, - _theResult___sfd__h598775, - _theResult___snd_fst_sfd__h482455, - _theResult___snd_fst_sfd__h502289, - _theResult___snd_fst_sfd__h520724, - _theResult___snd_fst_sfd__h521449, - _theResult___snd_fst_sfd__h541142, - _theResult___snd_fst_sfd__h559577, - _theResult___snd_fst_sfd__h560753, - _theResult___snd_fst_sfd__h580446, - _theResult___snd_fst_sfd__h598881, - out___1_sfd__h482203, - out___1_sfd__h521197, - out___1_sfd__h560501, - out_sfd__h502186, - out_sfd__h511837, - out_sfd__h520621, - out_sfd__h541039, - out_sfd__h550690, - out_sfd__h559474, - out_sfd__h580343, - out_sfd__h589994, - out_sfd__h598778; - wire [50 : 0] r1__read__h613062, r1__read__h614239; - wire [49 : 0] r1__read__h614348; - wire [48 : 0] r1__read_BITS_62_TO_14___h728903, - r1__read__h613064, - r1__read__h614350; - wire [46 : 0] r1__read__h613066, r1__read__h614243; - wire [45 : 0] r1__read__h613068, r1__read__h614245; - wire [44 : 0] r1__read__h613070, r1__read__h614247; - wire [43 : 0] r1__read__h613072, r1__read__h614249; - wire [42 : 0] r1__read__h614251; - wire [41 : 0] r1__read__h614253; - wire [40 : 0] r1__read__h614255; + _theResult___fst_sfd__h486456, + _theResult___fst_sfd__h502284, + _theResult___fst_sfd__h502287, + _theResult___fst_sfd__h511935, + _theResult___fst_sfd__h511938, + _theResult___fst_sfd__h520719, + _theResult___fst_sfd__h520722, + _theResult___fst_sfd__h520731, + _theResult___fst_sfd__h520737, + _theResult___fst_sfd__h525309, + _theResult___fst_sfd__h541137, + _theResult___fst_sfd__h541140, + _theResult___fst_sfd__h550788, + _theResult___fst_sfd__h550791, + _theResult___fst_sfd__h559572, + _theResult___fst_sfd__h559575, + _theResult___fst_sfd__h559584, + _theResult___fst_sfd__h559590, + _theResult___fst_sfd__h564613, + _theResult___fst_sfd__h580441, + _theResult___fst_sfd__h580444, + _theResult___fst_sfd__h590092, + _theResult___fst_sfd__h590095, + _theResult___fst_sfd__h598876, + _theResult___fst_sfd__h598879, + _theResult___fst_sfd__h598888, + _theResult___fst_sfd__h598894, + _theResult___sfd__h502184, + _theResult___sfd__h511835, + _theResult___sfd__h520619, + _theResult___sfd__h541037, + _theResult___sfd__h550688, + _theResult___sfd__h559472, + _theResult___sfd__h580341, + _theResult___sfd__h589992, + _theResult___sfd__h598776, + _theResult___snd_fst_sfd__h482456, + _theResult___snd_fst_sfd__h502290, + _theResult___snd_fst_sfd__h520725, + _theResult___snd_fst_sfd__h521450, + _theResult___snd_fst_sfd__h541143, + _theResult___snd_fst_sfd__h559578, + _theResult___snd_fst_sfd__h560754, + _theResult___snd_fst_sfd__h580447, + _theResult___snd_fst_sfd__h598882, + out___1_sfd__h482204, + out___1_sfd__h521198, + out___1_sfd__h560502, + out_sfd__h502187, + out_sfd__h511838, + out_sfd__h520622, + out_sfd__h541040, + out_sfd__h550691, + out_sfd__h559475, + out_sfd__h580344, + out_sfd__h589995, + out_sfd__h598779; + wire [50 : 0] r1__read__h613064, r1__read__h614241; + wire [49 : 0] r1__read__h614350; + wire [48 : 0] r1__read_BITS_62_TO_14___h729920, + r1__read__h613066, + r1__read__h614352; + wire [46 : 0] r1__read__h613068, r1__read__h614245; + wire [45 : 0] r1__read__h613070, r1__read__h614247; + wire [44 : 0] r1__read__h613072, r1__read__h614249; + wire [43 : 0] r1__read__h613074, r1__read__h614251; + wire [42 : 0] r1__read__h614253; + wire [41 : 0] r1__read__h614255; + wire [40 : 0] r1__read__h614257; wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14134, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data75281_BITS_31_TO_0__q14, - imm__h655327, - r1__read__h613074, - r1__read__h614257, - x__h193678, - x__h337883, - x__h383585, - x__h429280, - x__h76236, - x_data__h66085, - x_data_imm__h676655, - x_data_imm__h692709; - wire [29 : 0] r1__read__h613076, r1__read__h614259; - wire [27 : 0] r1__read__h614261; + data75282_BITS_31_TO_0__q13, + imm__h655329, + r1__read__h613076, + r1__read__h614259, + x__h193679, + x__h337884, + x__h383586, + x__h429281, + x__h76237, + x_data__h66086, + x_data_imm__h676657, + x_data_imm__h692711; + wire [29 : 0] r1__read__h613078, r1__read__h614261; + wire [27 : 0] r1__read__h614263; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14166, - sfd__h354287, - sfd__h362869, - sfd__h372053, - sfd__h380665, - sfd__h399984, - sfd__h408566, - sfd__h417750, - sfd__h426362, - sfd__h445679, - sfd__h454261, - sfd__h463445, - sfd__h472057, - value__h487084, - value__h525937, - value__h565241; + sfd__h354288, + sfd__h362870, + sfd__h372054, + sfd__h380666, + sfd__h399985, + sfd__h408567, + sfd__h417751, + sfd__h426363, + sfd__h445680, + sfd__h454262, + sfd__h463446, + sfd__h472058, + value__h487085, + value__h525938, + value__h565242; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349, @@ -5436,77 +5445,77 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808, - _theResult___fst_sfd__h354793, - _theResult___fst_sfd__h363375, - _theResult___fst_sfd__h372559, - _theResult___fst_sfd__h381195, - _theResult___fst_sfd__h381204, - _theResult___fst_sfd__h381210, - _theResult___fst_sfd__h400490, - _theResult___fst_sfd__h409072, - _theResult___fst_sfd__h418256, - _theResult___fst_sfd__h426892, - _theResult___fst_sfd__h426901, - _theResult___fst_sfd__h426907, - _theResult___fst_sfd__h446185, - _theResult___fst_sfd__h454767, - _theResult___fst_sfd__h463951, - _theResult___fst_sfd__h472587, - _theResult___fst_sfd__h472596, - _theResult___fst_sfd__h472602, - _theResult___sfd__h354712, - _theResult___sfd__h363294, - _theResult___sfd__h372478, - _theResult___sfd__h381114, - _theResult___sfd__h381216, - _theResult___sfd__h400409, - _theResult___sfd__h408991, - _theResult___sfd__h418175, - _theResult___sfd__h426811, - _theResult___sfd__h426913, - _theResult___sfd__h446104, - _theResult___sfd__h454686, - _theResult___sfd__h463870, - _theResult___sfd__h472506, - _theResult___sfd__h472608, - _theResult___snd_fst_sfd__h338429, - _theResult___snd_fst_sfd__h363378, - _theResult___snd_fst_sfd__h381198, - _theResult___snd_fst_sfd__h384131, - _theResult___snd_fst_sfd__h409075, - _theResult___snd_fst_sfd__h426895, - _theResult___snd_fst_sfd__h429826, - _theResult___snd_fst_sfd__h454770, - _theResult___snd_fst_sfd__h472590, - f1_sfd__h482140, - f2_sfd__h521134, - f3_sfd__h560438, - out_f_sfd__h381493, - out_f_sfd__h427190, - out_f_sfd__h472885, - out_sfd__h354715, - out_sfd__h363297, - out_sfd__h372481, - out_sfd__h381117, - out_sfd__h400412, - out_sfd__h408994, - out_sfd__h418178, - out_sfd__h426814, - out_sfd__h446107, - out_sfd__h454689, - out_sfd__h463873, - out_sfd__h472509; - wire [19 : 0] r1__read__h614196; + _theResult___fst_sfd__h354794, + _theResult___fst_sfd__h363376, + _theResult___fst_sfd__h372560, + _theResult___fst_sfd__h381196, + _theResult___fst_sfd__h381205, + _theResult___fst_sfd__h381211, + _theResult___fst_sfd__h400491, + _theResult___fst_sfd__h409073, + _theResult___fst_sfd__h418257, + _theResult___fst_sfd__h426893, + _theResult___fst_sfd__h426902, + _theResult___fst_sfd__h426908, + _theResult___fst_sfd__h446186, + _theResult___fst_sfd__h454768, + _theResult___fst_sfd__h463952, + _theResult___fst_sfd__h472588, + _theResult___fst_sfd__h472597, + _theResult___fst_sfd__h472603, + _theResult___sfd__h354713, + _theResult___sfd__h363295, + _theResult___sfd__h372479, + _theResult___sfd__h381115, + _theResult___sfd__h381217, + _theResult___sfd__h400410, + _theResult___sfd__h408992, + _theResult___sfd__h418176, + _theResult___sfd__h426812, + _theResult___sfd__h426914, + _theResult___sfd__h446105, + _theResult___sfd__h454687, + _theResult___sfd__h463871, + _theResult___sfd__h472507, + _theResult___sfd__h472609, + _theResult___snd_fst_sfd__h338430, + _theResult___snd_fst_sfd__h363379, + _theResult___snd_fst_sfd__h381199, + _theResult___snd_fst_sfd__h384132, + _theResult___snd_fst_sfd__h409076, + _theResult___snd_fst_sfd__h426896, + _theResult___snd_fst_sfd__h429827, + _theResult___snd_fst_sfd__h454771, + _theResult___snd_fst_sfd__h472591, + f1_sfd__h482141, + f2_sfd__h521135, + f3_sfd__h560439, + out_f_sfd__h381494, + out_f_sfd__h427191, + out_f_sfd__h472886, + out_sfd__h354716, + out_sfd__h363298, + out_sfd__h372482, + out_sfd__h381118, + out_sfd__h400413, + out_sfd__h408995, + out_sfd__h418179, + out_sfd__h426815, + out_sfd__h446108, + out_sfd__h454690, + out_sfd__h463874, + out_sfd__h472510; + wire [19 : 0] r1__read__h614198; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824, - _theResult____h651116, - enabled_ints___1__h651641, - enabled_ints__h651687, - pend_ints__h651114, - y__h651653; - wire [13 : 0] r1__read_BITS_13_TO_0___h651663; - wire [12 : 0] IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271, + _theResult____h651118, + enabled_ints___1__h651643, + enabled_ints__h651689, + pend_ints__h651116, + y__h651655; + wire [13 : 0] r1__read_BITS_13_TO_0___h651665; + wire [12 : 0] IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15282, fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494; + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505; wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661, @@ -5536,25 +5545,25 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338, - csr_addr__h655325, - renaming_spec_bits__h685237, - result__h646693, - result__h646744, - spec_bits__h688396, - w__h646688, - x__h364466, - x__h410163, - x__h455858, - x__h503609, - x__h542462, - x__h581766, - x__h646692, - x__h646743, - y__h646722, - y__h688409, - y_avValue_fst__h681569, - y_avValue_fst__h681598, - y_avValue_fst__h681632; + csr_addr__h655327, + renaming_spec_bits__h685239, + result__h646695, + result__h646746, + spec_bits__h688398, + w__h646690, + x__h364467, + x__h410164, + x__h455859, + x__h503610, + x__h542463, + x__h581767, + x__h646694, + x__h646745, + y__h646724, + y__h688411, + y_avValue_fst__h681571, + y_avValue_fst__h681600, + y_avValue_fst__h681634; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056, @@ -5576,102 +5585,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h502182, - _theResult___exp__h511833, - _theResult___exp__h520617, - _theResult___exp__h541035, - _theResult___exp__h550686, - _theResult___exp__h559470, - _theResult___exp__h580339, - _theResult___exp__h589990, - _theResult___exp__h598774, - _theResult___fst_exp__h486454, - _theResult___fst_exp__h501518, - _theResult___fst_exp__h501524, - _theResult___fst_exp__h501527, - _theResult___fst_exp__h502282, - _theResult___fst_exp__h502285, - _theResult___fst_exp__h511104, - _theResult___fst_exp__h511169, - _theResult___fst_exp__h511175, - _theResult___fst_exp__h511178, - _theResult___fst_exp__h511933, - _theResult___fst_exp__h511936, - _theResult___fst_exp__h519889, - _theResult___fst_exp__h519928, - _theResult___fst_exp__h519934, - _theResult___fst_exp__h519937, - _theResult___fst_exp__h520717, - _theResult___fst_exp__h520720, - _theResult___fst_exp__h520729, - _theResult___fst_exp__h520732, - _theResult___fst_exp__h525307, - _theResult___fst_exp__h540371, - _theResult___fst_exp__h540377, - _theResult___fst_exp__h540380, - _theResult___fst_exp__h541135, - _theResult___fst_exp__h541138, - _theResult___fst_exp__h549957, - _theResult___fst_exp__h550022, - _theResult___fst_exp__h550028, - _theResult___fst_exp__h550031, - _theResult___fst_exp__h550786, - _theResult___fst_exp__h550789, - _theResult___fst_exp__h558742, - _theResult___fst_exp__h558781, - _theResult___fst_exp__h558787, - _theResult___fst_exp__h558790, - _theResult___fst_exp__h559570, - _theResult___fst_exp__h559573, - _theResult___fst_exp__h559582, - _theResult___fst_exp__h559585, - _theResult___fst_exp__h564611, - _theResult___fst_exp__h579675, - _theResult___fst_exp__h579681, - _theResult___fst_exp__h579684, - _theResult___fst_exp__h580439, - _theResult___fst_exp__h580442, - _theResult___fst_exp__h589261, - _theResult___fst_exp__h589326, - _theResult___fst_exp__h589332, - _theResult___fst_exp__h589335, - _theResult___fst_exp__h590090, - _theResult___fst_exp__h590093, - _theResult___fst_exp__h598046, - _theResult___fst_exp__h598085, - _theResult___fst_exp__h598091, - _theResult___fst_exp__h598094, - _theResult___fst_exp__h598874, - _theResult___fst_exp__h598877, - _theResult___fst_exp__h598886, - _theResult___fst_exp__h598889, - _theResult___snd_fst_exp__h502288, - _theResult___snd_fst_exp__h520723, - _theResult___snd_fst_exp__h541141, - _theResult___snd_fst_exp__h559576, - _theResult___snd_fst_exp__h580445, - _theResult___snd_fst_exp__h598880, + _theResult___exp__h502183, + _theResult___exp__h511834, + _theResult___exp__h520618, + _theResult___exp__h541036, + _theResult___exp__h550687, + _theResult___exp__h559471, + _theResult___exp__h580340, + _theResult___exp__h589991, + _theResult___exp__h598775, + _theResult___fst_exp__h486455, + _theResult___fst_exp__h501519, + _theResult___fst_exp__h501525, + _theResult___fst_exp__h501528, + _theResult___fst_exp__h502283, + _theResult___fst_exp__h502286, + _theResult___fst_exp__h511105, + _theResult___fst_exp__h511170, + _theResult___fst_exp__h511176, + _theResult___fst_exp__h511179, + _theResult___fst_exp__h511934, + _theResult___fst_exp__h511937, + _theResult___fst_exp__h519890, + _theResult___fst_exp__h519929, + _theResult___fst_exp__h519935, + _theResult___fst_exp__h519938, + _theResult___fst_exp__h520718, + _theResult___fst_exp__h520721, + _theResult___fst_exp__h520730, + _theResult___fst_exp__h520733, + _theResult___fst_exp__h525308, + _theResult___fst_exp__h540372, + _theResult___fst_exp__h540378, + _theResult___fst_exp__h540381, + _theResult___fst_exp__h541136, + _theResult___fst_exp__h541139, + _theResult___fst_exp__h549958, + _theResult___fst_exp__h550023, + _theResult___fst_exp__h550029, + _theResult___fst_exp__h550032, + _theResult___fst_exp__h550787, + _theResult___fst_exp__h550790, + _theResult___fst_exp__h558743, + _theResult___fst_exp__h558782, + _theResult___fst_exp__h558788, + _theResult___fst_exp__h558791, + _theResult___fst_exp__h559571, + _theResult___fst_exp__h559574, + _theResult___fst_exp__h559583, + _theResult___fst_exp__h559586, + _theResult___fst_exp__h564612, + _theResult___fst_exp__h579676, + _theResult___fst_exp__h579682, + _theResult___fst_exp__h579685, + _theResult___fst_exp__h580440, + _theResult___fst_exp__h580443, + _theResult___fst_exp__h589262, + _theResult___fst_exp__h589327, + _theResult___fst_exp__h589333, + _theResult___fst_exp__h589336, + _theResult___fst_exp__h590091, + _theResult___fst_exp__h590094, + _theResult___fst_exp__h598047, + _theResult___fst_exp__h598086, + _theResult___fst_exp__h598092, + _theResult___fst_exp__h598095, + _theResult___fst_exp__h598875, + _theResult___fst_exp__h598878, + _theResult___fst_exp__h598887, + _theResult___fst_exp__h598890, + _theResult___snd_fst_exp__h502289, + _theResult___snd_fst_exp__h520724, + _theResult___snd_fst_exp__h541142, + _theResult___snd_fst_exp__h559577, + _theResult___snd_fst_exp__h580446, + _theResult___snd_fst_exp__h598881, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106, - din_inc___2_exp__h520777, - din_inc___2_exp__h520812, - din_inc___2_exp__h520838, - din_inc___2_exp__h559630, - din_inc___2_exp__h559665, - din_inc___2_exp__h559691, - din_inc___2_exp__h598934, - din_inc___2_exp__h598969, - din_inc___2_exp__h598995, - out_exp__h502185, - out_exp__h511836, - out_exp__h520620, - out_exp__h541038, - out_exp__h550689, - out_exp__h559473, - out_exp__h580342, - out_exp__h589993, - out_exp__h598777; + din_inc___2_exp__h520778, + din_inc___2_exp__h520813, + din_inc___2_exp__h520839, + din_inc___2_exp__h559631, + din_inc___2_exp__h559666, + din_inc___2_exp__h559692, + din_inc___2_exp__h598935, + din_inc___2_exp__h598970, + din_inc___2_exp__h598996, + out_exp__h502186, + out_exp__h511837, + out_exp__h520621, + out_exp__h541039, + out_exp__h550690, + out_exp__h559474, + out_exp__h580343, + out_exp__h589994, + out_exp__h598778; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656; @@ -5702,124 +5711,124 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112, - _theResult___exp__h354711, - _theResult___exp__h363293, - _theResult___exp__h372477, - _theResult___exp__h381113, - _theResult___exp__h381215, - _theResult___exp__h400408, - _theResult___exp__h408990, - _theResult___exp__h418174, - _theResult___exp__h426810, - _theResult___exp__h426912, - _theResult___exp__h446103, - _theResult___exp__h454685, - _theResult___exp__h463869, - _theResult___exp__h472505, - _theResult___exp__h472607, - _theResult___fst_exp__h354195, - _theResult___fst_exp__h354260, - _theResult___fst_exp__h354266, - _theResult___fst_exp__h354269, - _theResult___fst_exp__h354792, - _theResult___fst_exp__h362842, - _theResult___fst_exp__h362848, - _theResult___fst_exp__h362851, - _theResult___fst_exp__h363374, - _theResult___fst_exp__h371961, - _theResult___fst_exp__h372026, - _theResult___fst_exp__h372032, - _theResult___fst_exp__h372035, - _theResult___fst_exp__h372558, - _theResult___fst_exp__h380598, - _theResult___fst_exp__h380637, - _theResult___fst_exp__h380643, - _theResult___fst_exp__h380646, - _theResult___fst_exp__h381194, - _theResult___fst_exp__h381203, - _theResult___fst_exp__h381206, - _theResult___fst_exp__h399892, - _theResult___fst_exp__h399957, - _theResult___fst_exp__h399963, - _theResult___fst_exp__h399966, - _theResult___fst_exp__h400489, - _theResult___fst_exp__h408539, - _theResult___fst_exp__h408545, - _theResult___fst_exp__h408548, - _theResult___fst_exp__h409071, - _theResult___fst_exp__h417658, - _theResult___fst_exp__h417723, - _theResult___fst_exp__h417729, - _theResult___fst_exp__h417732, - _theResult___fst_exp__h418255, - _theResult___fst_exp__h426295, - _theResult___fst_exp__h426334, - _theResult___fst_exp__h426340, - _theResult___fst_exp__h426343, - _theResult___fst_exp__h426891, - _theResult___fst_exp__h426900, - _theResult___fst_exp__h426903, - _theResult___fst_exp__h445587, - _theResult___fst_exp__h445652, - _theResult___fst_exp__h445658, - _theResult___fst_exp__h445661, - _theResult___fst_exp__h446184, - _theResult___fst_exp__h454234, - _theResult___fst_exp__h454240, - _theResult___fst_exp__h454243, - _theResult___fst_exp__h454766, - _theResult___fst_exp__h463353, - _theResult___fst_exp__h463418, - _theResult___fst_exp__h463424, - _theResult___fst_exp__h463427, - _theResult___fst_exp__h463950, - _theResult___fst_exp__h471990, - _theResult___fst_exp__h472029, - _theResult___fst_exp__h472035, - _theResult___fst_exp__h472038, - _theResult___fst_exp__h472586, - _theResult___fst_exp__h472595, - _theResult___fst_exp__h472598, - _theResult___snd_fst_exp__h363377, - _theResult___snd_fst_exp__h381197, - _theResult___snd_fst_exp__h409074, - _theResult___snd_fst_exp__h426894, - _theResult___snd_fst_exp__h454769, - _theResult___snd_fst_exp__h472589, - din_inc___2_exp__h381228, - din_inc___2_exp__h381252, - din_inc___2_exp__h381282, - din_inc___2_exp__h381306, - din_inc___2_exp__h426925, - din_inc___2_exp__h426949, - din_inc___2_exp__h426979, - din_inc___2_exp__h427003, - din_inc___2_exp__h472620, - din_inc___2_exp__h472644, - din_inc___2_exp__h472674, - din_inc___2_exp__h472698, - f1_exp82139_MINUS_127__q136, - f1_exp__h482139, - f2_exp21133_MINUS_127__q176, - f2_exp__h521133, - f3_exp60437_MINUS_127__q153, - f3_exp__h560437, - out_exp__h354714, - out_exp__h363296, - out_exp__h372480, - out_exp__h381116, - out_exp__h400411, - out_exp__h408993, - out_exp__h418177, - out_exp__h426813, - out_exp__h446106, - out_exp__h454688, - out_exp__h463872, - out_exp__h472508, - out_f_exp__h381492, - out_f_exp__h427189, - out_f_exp__h472884, - x__h613033; + _theResult___exp__h354712, + _theResult___exp__h363294, + _theResult___exp__h372478, + _theResult___exp__h381114, + _theResult___exp__h381216, + _theResult___exp__h400409, + _theResult___exp__h408991, + _theResult___exp__h418175, + _theResult___exp__h426811, + _theResult___exp__h426913, + _theResult___exp__h446104, + _theResult___exp__h454686, + _theResult___exp__h463870, + _theResult___exp__h472506, + _theResult___exp__h472608, + _theResult___fst_exp__h354196, + _theResult___fst_exp__h354261, + _theResult___fst_exp__h354267, + _theResult___fst_exp__h354270, + _theResult___fst_exp__h354793, + _theResult___fst_exp__h362843, + _theResult___fst_exp__h362849, + _theResult___fst_exp__h362852, + _theResult___fst_exp__h363375, + _theResult___fst_exp__h371962, + _theResult___fst_exp__h372027, + _theResult___fst_exp__h372033, + _theResult___fst_exp__h372036, + _theResult___fst_exp__h372559, + _theResult___fst_exp__h380599, + _theResult___fst_exp__h380638, + _theResult___fst_exp__h380644, + _theResult___fst_exp__h380647, + _theResult___fst_exp__h381195, + _theResult___fst_exp__h381204, + _theResult___fst_exp__h381207, + _theResult___fst_exp__h399893, + _theResult___fst_exp__h399958, + _theResult___fst_exp__h399964, + _theResult___fst_exp__h399967, + _theResult___fst_exp__h400490, + _theResult___fst_exp__h408540, + _theResult___fst_exp__h408546, + _theResult___fst_exp__h408549, + _theResult___fst_exp__h409072, + _theResult___fst_exp__h417659, + _theResult___fst_exp__h417724, + _theResult___fst_exp__h417730, + _theResult___fst_exp__h417733, + _theResult___fst_exp__h418256, + _theResult___fst_exp__h426296, + _theResult___fst_exp__h426335, + _theResult___fst_exp__h426341, + _theResult___fst_exp__h426344, + _theResult___fst_exp__h426892, + _theResult___fst_exp__h426901, + _theResult___fst_exp__h426904, + _theResult___fst_exp__h445588, + _theResult___fst_exp__h445653, + _theResult___fst_exp__h445659, + _theResult___fst_exp__h445662, + _theResult___fst_exp__h446185, + _theResult___fst_exp__h454235, + _theResult___fst_exp__h454241, + _theResult___fst_exp__h454244, + _theResult___fst_exp__h454767, + _theResult___fst_exp__h463354, + _theResult___fst_exp__h463419, + _theResult___fst_exp__h463425, + _theResult___fst_exp__h463428, + _theResult___fst_exp__h463951, + _theResult___fst_exp__h471991, + _theResult___fst_exp__h472030, + _theResult___fst_exp__h472036, + _theResult___fst_exp__h472039, + _theResult___fst_exp__h472587, + _theResult___fst_exp__h472596, + _theResult___fst_exp__h472599, + _theResult___snd_fst_exp__h363378, + _theResult___snd_fst_exp__h381198, + _theResult___snd_fst_exp__h409075, + _theResult___snd_fst_exp__h426895, + _theResult___snd_fst_exp__h454770, + _theResult___snd_fst_exp__h472590, + din_inc___2_exp__h381229, + din_inc___2_exp__h381253, + din_inc___2_exp__h381283, + din_inc___2_exp__h381307, + din_inc___2_exp__h426926, + din_inc___2_exp__h426950, + din_inc___2_exp__h426980, + din_inc___2_exp__h427004, + din_inc___2_exp__h472621, + din_inc___2_exp__h472645, + din_inc___2_exp__h472675, + din_inc___2_exp__h472699, + f1_exp82140_MINUS_127__q136, + f1_exp__h482140, + f2_exp21134_MINUS_127__q176, + f2_exp__h521134, + f3_exp60438_MINUS_127__q153, + f3_exp__h560438, + out_exp__h354715, + out_exp__h363297, + out_exp__h372481, + out_exp__h381117, + out_exp__h400412, + out_exp__h408994, + out_exp__h418178, + out_exp__h426814, + out_exp__h446107, + out_exp__h454689, + out_exp__h463873, + out_exp__h472509, + out_f_exp__h381493, + out_f_exp__h427190, + out_f_exp__h472885, + x__h613035; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031, @@ -5839,11 +5848,11 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083, - x__h181698, - x__h711438; + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16096, + x__h181699, + x__h712418; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651, + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953, @@ -5861,25 +5870,25 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965, checkForException___d13008, checkForException___d13698, - fflags__h727255, - fflags__h729891, - fflags__h732495, - old_fflags__h731983, - po_fflags__h727241, - po_fflags__h729877, - r1__read__h614599, - res_fflags__h337869, - res_fflags__h383571, - res_fflags__h429266, - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, - rs1__h655326, - x__h153724, - x__h157271, - x__h160087, - x__h287278, - y_avValue_fst__h729252, - y_avValue_fst__h732400, - y_avValue_fst__h732432; + fflags__h728257, + fflags__h730910, + fflags__h733530, + old_fflags__h733017, + po_fflags__h728242, + po_fflags__h730895, + r1__read__h614601, + res_fflags__h337870, + res_fflags__h383572, + res_fflags__h429267, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, + rs1__h655328, + x__h153725, + x__h157272, + x__h160088, + x__h287279, + y_avValue_fst__h730270, + y_avValue_fst__h733435, + y_avValue_fst__h733467; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855, @@ -5906,77 +5915,77 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h708463, - vm_mode_reg__read__h614202; + cause_code__h709443, + vm_mode_reg__read__h614204; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h296520, - dcsr_cause__h707982, - next_deqP___1__h296799, - v__h295940, - v__h296171, - x__h302150, - x_decodeInfo_frm__h655010; + _theResult_____2__h296521, + dcsr_cause__h708962, + next_deqP___1__h296800, + v__h295941, + v__h296172, + x__h302151, + x_decodeInfo_frm__h655012; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670, - IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74, - IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99, - IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29, - IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109, - IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39, - IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156, - IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64, - IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135, - IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66, - IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79, - IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101, - IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31, - IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114, - IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44, - IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159, - guard__h346094, - guard__h354803, - guard__h363733, - guard__h372569, - guard__h391793, - guard__h400500, - guard__h409430, - guard__h418266, - guard__h437488, - guard__h446195, - guard__h455125, - guard__h463961, - guard__h493566, - guard__h502878, - guard__h511947, - guard__h532419, - guard__h541731, - guard__h550800, - guard__h571723, - guard__h581035, - guard__h590104, - prv__h734164, - prv__h734208, - r1__read_BITS_13_TO_12___h655195, - sbIdx__h157150, - v__h603882, - v__h603892, - v__h604527, - x__h721573, - x__h732759, - x_prv__h711506, - x_prv__h722029, - y_avValue_snd_snd_snd_fst__h729727, - y_avValue_snd_snd_snd_fst__h732569, - y_avValue_snd_snd_snd_fst__h732605; + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683, + IF_sfdin11099_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin17653_BIT_33_THEN_2_ELSE_0__q74, + IF_sfdin45582_BIT_33_THEN_2_ELSE_0__q99, + IF_sfdin49952_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin54190_BIT_33_THEN_2_ELSE_0__q29, + IF_sfdin63348_BIT_33_THEN_2_ELSE_0__q109, + IF_sfdin71956_BIT_33_THEN_2_ELSE_0__q39, + IF_sfdin89256_BIT_4_THEN_2_ELSE_0__q156, + IF_sfdin99887_BIT_33_THEN_2_ELSE_0__q64, + IF_theResult___snd01479_BIT_4_THEN_2_ELSE_0__q135, + IF_theResult___snd08500_BIT_33_THEN_2_ELSE_0__q66, + IF_theResult___snd19884_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd26290_BIT_33_THEN_2_ELSE_0__q79, + IF_theResult___snd40332_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd54195_BIT_33_THEN_2_ELSE_0__q101, + IF_theResult___snd58737_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd62803_BIT_33_THEN_2_ELSE_0__q31, + IF_theResult___snd71985_BIT_33_THEN_2_ELSE_0__q114, + IF_theResult___snd79636_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd80593_BIT_33_THEN_2_ELSE_0__q44, + IF_theResult___snd98041_BIT_4_THEN_2_ELSE_0__q159, + guard__h346095, + guard__h354804, + guard__h363734, + guard__h372570, + guard__h391794, + guard__h400501, + guard__h409431, + guard__h418267, + guard__h437489, + guard__h446196, + guard__h455126, + guard__h463962, + guard__h493567, + guard__h502879, + guard__h511948, + guard__h532420, + guard__h541732, + guard__h550801, + guard__h571724, + guard__h581036, + guard__h590105, + prv__h735199, + prv__h735243, + r1__read_BITS_13_TO_12___h655197, + sbIdx__h157151, + v__h603883, + v__h603893, + v__h604528, + x__h722556, + x__h733794, + x_prv__h712487, + x_prv__h723013, + y_avValue_snd_snd_snd_fst__h730745, + y_avValue_snd_snd_snd_fst__h733604, + y_avValue_snd_snd_snd_fst__h733640; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461, @@ -6056,7 +6065,7 @@ module mkCore(CLK, IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13916, IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13831, IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13915, - IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661, + IF_NOT_rob_deqPort_1_deq_data__5322_BIT_25_532_ETC___d15674, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900, @@ -6179,7 +6188,7 @@ module mkCore(CLK, IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201, IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642, IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491, - IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662, + IF_rob_deqPort_1_canDeq__5319_THEN_IF_NOT_rob__ETC___d15675, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249, NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613, @@ -6189,25 +6198,27 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13422, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725, - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667, + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964, - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992, + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286, NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484, - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614, - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621, - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684, - NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995, + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14624, + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14631, + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695, + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005, + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15016, + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15368, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229, NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257, NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369, @@ -6263,7 +6274,7 @@ module mkCore(CLK, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420, NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723, - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731, + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13527, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13814, @@ -6315,10 +6326,10 @@ module mkCore(CLK, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13736, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13878, NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13896, - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345, - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645, - NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983, - NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342, + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_RDY_ETC___d15356, + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658, + NOT_rob_deqPort_0_deq_data__4339_BITS_329_TO_3_ETC___d14993, + NOT_rob_deqPort_1_deq_data__5322_BIT_25_5323_5_ETC___d15353, NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14007, NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14074, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132, @@ -6357,8 +6368,9 @@ module mkCore(CLK, _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928, _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829, _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14020, - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705, - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687, + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324, + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716, + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013, _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184, @@ -6384,7 +6396,7 @@ module mkCore(CLK, _dfoo16, _dfoo18, _dfoo2, - _dfoo20, + _dfoo22, _dfoo24, _dfoo26, _dfoo32, @@ -6413,12 +6425,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h304516, - _theResult_____2__h310510, - _theResult_____2__h318364, - _theResult_____2__h328708, - _theResult_____2__h331933, - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644, + _theResult_____2__h304517, + _theResult_____2__h310511, + _theResult_____2__h318365, + _theResult_____2__h328709, + _theResult_____2__h331934, + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244, coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218, @@ -6517,18 +6529,18 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574, - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646, + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14656, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502, csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791, - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707, - csrf_prv_reg_read__2787_ULE_1___d14685, + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718, + csrf_prv_reg_read__2787_ULE_1___d14696, csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040, csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13876, epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13894, - f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880, + f_csr_rsps_i_notFull__5790_AND_f_csr_reqs_firs_ETC___d15893, fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14018, fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100, @@ -6553,14 +6565,14 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13835, fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13973, fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13985, - guard__h364331, - guard__h410028, - guard__h455723, - guard__h503476, - guard__h542329, - guard__h581633, - idx__h685368, - k__h669623, + guard__h364332, + guard__h410029, + guard__h455724, + guard__h503477, + guard__h542330, + guard__h581634, + idx__h685370, + k__h669625, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6573,14 +6585,15 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14094, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h76121, - next_deqP___1__h304795, - next_deqP___1__h311076, - next_deqP___1__h318930, - next_deqP___1__h328987, - next_deqP___1__h332212, - r1__read_BIT_20___h655891, - regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941, + msip__h76122, + next_deqP___1__h304796, + next_deqP___1__h311077, + next_deqP___1__h318931, + next_deqP___1__h328988, + next_deqP___1__h332213, + r1__read_BIT_20___h655893, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941, regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022, regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429, regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479, @@ -6603,26 +6616,24 @@ module mkCore(CLK, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13799, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840, renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920, - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716, - rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988, - rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309, + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15729, + rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, - tsr_val__h725552, - tvm_val__h725554, - v__h299285, - v__h299803, - v__h309799, - v__h310030, - v__h313675, - v__h313906, - v__h328276, - v__h328507, - v__h331501, - v__h331732, - value_BIT_23___h494224, - x__h603383; + tsr_val__h726551, + tvm_val__h726553, + v__h299286, + v__h299804, + v__h309800, + v__h310031, + v__h313676, + v__h313907, + v__h328277, + v__h328508, + v__h331502, + v__h331733, + x__h603384; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -6660,10 +6671,10 @@ module mkCore(CLK, // value method dCacheToParent_rsToP_first assign dCacheToParent_rsToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 } ; assign RDY_dCacheToParent_rsToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ; @@ -6681,9 +6692,9 @@ module mkCore(CLK, // value method dCacheToParent_rqToP_first assign dCacheToParent_rqToP_first = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, - SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083 } ; + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273, + SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16096 } ; assign RDY_dCacheToParent_rqToP_first = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ; @@ -6970,7 +6981,7 @@ module mkCore(CLK, // actionvalue method v_to_TV_0_get assign v_to_TV_0_get = - { v_f_to_TV_0$D_OUT[784:476], + { v_f_to_TV_0$D_OUT[861:476], CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5, v_f_to_TV_0$D_OUT[463:462], v_f_to_TV_0$D_OUT[462] ? @@ -6985,7 +6996,7 @@ module mkCore(CLK, // actionvalue method v_to_TV_1_get assign v_to_TV_1_get = - { v_f_to_TV_1$D_OUT[784:476], + { v_f_to_TV_1$D_OUT[861:476], CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1, v_f_to_TV_1$D_OUT[463:462], v_f_to_TV_1$D_OUT[462] ? @@ -9790,7 +9801,7 @@ module mkCore(CLK, .RDY_isFull_ehrPort0()); // submodule v_f_to_TV_0 - FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N), .CLK(CLK), .D_IN(v_f_to_TV_0$D_IN), .ENQ(v_f_to_TV_0$ENQ), @@ -9801,7 +9812,7 @@ module mkCore(CLK, .EMPTY_N(v_f_to_TV_0$EMPTY_N)); // submodule v_f_to_TV_1 - FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N), .CLK(CLK), .D_IN(v_f_to_TV_1$D_IN), .ENQ(v_f_to_TV_1$ENQ), @@ -9817,32 +9828,32 @@ module mkCore(CLK, // rule RL_sendDTlbReq assign CAN_FIRE_RL_sendDTlbReq = - coreFix_memExe_dTlb$RDY_toParent_rqToP_first && coreFix_memExe_dTlb$RDY_toParent_rqToP_deq && + coreFix_memExe_dTlb$RDY_toParent_rqToP_first && l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ; // rule RL_sendITlbReq assign CAN_FIRE_RL_sendITlbReq = - l2Tlb$RDY_toChildren_rqFromC_put && + fetchStage$RDY_iTlbIfc_toParent_rqToP_deq && fetchStage$RDY_iTlbIfc_toParent_rqToP_first && - fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ; + l2Tlb$RDY_toChildren_rqFromC_put ; assign WILL_FIRE_RL_sendITlbReq = CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ; // rule RL_sendRsToDTlb assign CAN_FIRE_RL_sendRsToDTlb = - l2Tlb$RDY_toChildren_rsToC_first && l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq && l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ; // rule RL_sendRsToITlb assign CAN_FIRE_RL_sendRsToITlb = - l2Tlb$RDY_toChildren_rsToC_first && - l2Tlb$RDY_toChildren_rsToC_deq && fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq && + l2Tlb$RDY_toChildren_rsToC_deq && + l2Tlb$RDY_toChildren_rsToC_first && !l2Tlb$toChildren_rsToC_first[83] ; assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ; @@ -9854,16 +9865,16 @@ module mkCore(CLK, // rule RL_mkConnectionGetPut_1 assign CAN_FIRE_RL_mkConnectionGetPut_1 = - l2Tlb$RDY_toChildren_iTlbReqFlush_put && - fetchStage$RDY_iTlbIfc_toParent_flush_request_get ; + fetchStage$RDY_iTlbIfc_toParent_flush_request_get && + l2Tlb$RDY_toChildren_iTlbReqFlush_put ; assign WILL_FIRE_RL_mkConnectionGetPut_1 = CAN_FIRE_RL_mkConnectionGetPut_1 ; // rule RL_sendFlushDone assign CAN_FIRE_RL_sendFlushDone = + fetchStage$RDY_iTlbIfc_toParent_flush_response_put && coreFix_memExe_dTlb$RDY_toParent_flush_response_put && - l2Tlb$RDY_toChildren_flushDone_get && - fetchStage$RDY_iTlbIfc_toParent_flush_response_put ; + l2Tlb$RDY_toChildren_flushDone_get ; assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ; // rule RL_sendRobEnqTime @@ -9884,7 +9895,7 @@ module mkCore(CLK, // rule RL_readyToFetch assign CAN_FIRE_RL_readyToFetch = fetchStage$RDY_done_flushing && - rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716 && + rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15729 && !flush_brpred && fetchStage$iMemIfc_flush_done && fetchStage$flush_predictors_done ; @@ -9981,7 +9992,7 @@ module mkCore(CLK, // rule RL_rl_debug_csr_write assign CAN_FIRE_RL_rl_debug_csr_write = f_csr_reqs$EMPTY_N && - f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880 && + f_csr_rsps_i_notFull__5790_AND_f_csr_reqs_firs_ETC___d15893 && rg_core_run_state == 2'd1 && f_csr_reqs$D_OUT[76] ; assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ; @@ -10001,9 +10012,9 @@ module mkCore(CLK, // rule RL_mmio_sendInstReq assign CAN_FIRE_RL_mmio_sendInstReq = - !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd && + !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq && fetchStage$RDY_mmioIfc_instReq_first_fst && - fetchStage$RDY_mmioIfc_instReq_deq ; + fetchStage$RDY_mmioIfc_instReq_first_snd ; assign WILL_FIRE_RL_mmio_sendInstReq = CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ; @@ -10295,7 +10306,7 @@ module mkCore(CLK, // rule RL_commitStage_doCommitTrap_flush assign CAN_FIRE_RL_commitStage_doCommitTrap_flush = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && commitStage_f_rob_data$FULL_N && (rob$deqPort_0_deq_data[12] || epochManager$RDY_incrementEpoch) && @@ -10311,12 +10322,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10336,14 +10347,22 @@ module mkCore(CLK, assign WILL_FIRE_RL_commitStage_rl_send_tv_reset = CAN_FIRE_RL_commitStage_rl_send_tv_reset ; + // rule RL_commitStage_rl_send_mip_csr_change_to_tv + assign CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = + v_f_to_TV_0$FULL_N && !commitStage_rg_just_after_reset && + !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; + assign WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv = + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; + // rule RL_commitStage_doCommitTrap_handle assign CAN_FIRE_RL_commitStage_doCommitTrap_handle = commitStage_f_rob_data$EMPTY_N && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621 && - (commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || - coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646) && + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14631 && + (commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || + coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14656) && + commitStage_commitTrap[165] && !commitStage_rg_run_state && - commitStage_commitTrap[165] ; + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; assign WILL_FIRE_RL_commitStage_doCommitTrap_handle = CAN_FIRE_RL_commitStage_doCommitTrap_handle && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10355,8 +10374,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitKilledLd assign CAN_FIRE_RL_commitStage_doCommitKilledLd = - epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data && - rob$RDY_deqPort_0_deq && + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && + epochManager$RDY_incrementEpoch && !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && @@ -10370,12 +10389,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10392,17 +10411,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitSystemInst assign CAN_FIRE_RL_commitStage_doCommitSystemInst = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && - rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988 && - NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 && - (rob$deqPort_0_deq_data[329:325] == 5'd0 || - rob$deqPort_0_deq_data[329:325] == 5'd21 || - rob$deqPort_0_deq_data[329:325] == 5'd17 || - rob$deqPort_0_deq_data[329:325] == 5'd18 || - rob$deqPort_0_deq_data[329:325] == 5'd13 || - rob$deqPort_0_deq_data[329:325] == 5'd16 || - rob$deqPort_0_deq_data[329:325] == 5'd15 || - rob$deqPort_0_deq_data[329:325] == 5'd19 || - rob$deqPort_0_deq_data[329:325] == 5'd20) ; + rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998 && + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15016 ; assign WILL_FIRE_RL_commitStage_doCommitSystemInst = CAN_FIRE_RL_commitStage_doCommitSystemInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset && @@ -10436,17 +10446,8 @@ module mkCore(CLK, // rule RL_commitStage_doCommitNormalInst assign CAN_FIRE_RL_commitStage_doCommitNormalInst = rob$RDY_deqPort_0_deq_data && - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345 && - NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 && - rob$deqPort_0_deq_data[329:325] != 5'd0 && - rob$deqPort_0_deq_data[329:325] != 5'd21 && - rob$deqPort_0_deq_data[329:325] != 5'd17 && - rob$deqPort_0_deq_data[329:325] != 5'd18 && - rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[329:325] != 5'd16 && - rob$deqPort_0_deq_data[329:325] != 5'd15 && - rob$deqPort_0_deq_data[329:325] != 5'd19 && - rob$deqPort_0_deq_data[329:325] != 5'd20 ; + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_RDY_ETC___d15356 && + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15368 ; assign WILL_FIRE_RL_commitStage_doCommitNormalInst = CAN_FIRE_RL_commitStage_doCommitNormalInst && !WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -10465,12 +10466,12 @@ module mkCore(CLK, coreFix_trainBPQ_1$FULL_N ; assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T = CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10497,12 +10498,12 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10595,8 +10596,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_0_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = coreFix_aluExe_0_dispToRegQ$RDY_enq && - coreFix_aluExe_0_rsAlu$RDY_doDispatch && - coreFix_aluExe_0_rsAlu$RDY_dispatchData ; + coreFix_aluExe_0_rsAlu$RDY_dispatchData && + coreFix_aluExe_0_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10607,8 +10608,8 @@ module mkCore(CLK, // rule RL_coreFix_aluExe_1_doDispatchAlu assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = coreFix_aluExe_1_dispToRegQ$RDY_enq && - coreFix_aluExe_1_rsAlu$RDY_doDispatch && - coreFix_aluExe_1_rsAlu$RDY_dispatchData ; + coreFix_aluExe_1_rsAlu$RDY_dispatchData && + coreFix_aluExe_1_rsAlu$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu = CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -10620,8 +10621,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq && @@ -10649,6 +10650,8 @@ module mkCore(CLK, rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10660,7 +10663,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10672,8 +10675,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10686,8 +10690,9 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10701,8 +10706,9 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10714,11 +10720,6 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103 ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && !WILL_FIRE_RL_coreFix_memExe_doRespLdForward && !WILL_FIRE_RL_coreFix_memExe_doRespLdMem && !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq && @@ -10726,16 +10727,16 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqLdQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && coreFix_memExe_lsq$firstLd[7] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ; // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd && !coreFix_memExe_lsq$firstLd[7] && !coreFix_memExe_lsq$firstLd[101] && !coreFix_memExe_lsq$firstLd[16] ; @@ -10759,8 +10760,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doFinishMem assign CAN_FIRE_RL_coreFix_memExe_doFinishMem = rob$RDY_setExecuted_doFinishMem && - coreFix_memExe_dTlb$RDY_deqProcResp && - coreFix_memExe_dTlb$RDY_procResp ; + coreFix_memExe_dTlb$RDY_procResp && + coreFix_memExe_dTlb$RDY_deqProcResp ; assign WILL_FIRE_RL_coreFix_memExe_doFinishMem = CAN_FIRE_RL_coreFix_memExe_doFinishMem ; @@ -10857,8 +10858,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_fault assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$firstSt[4] ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault && @@ -10875,8 +10876,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_Fence assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence = - rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd3 && (!coreFix_memExe_lsq$firstSt[151] || @@ -10898,8 +10899,8 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = !coreFix_memExe_respLrScAmoQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ; assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq = CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq && @@ -10911,12 +10912,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -10944,12 +10945,12 @@ module mkCore(CLK, !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F && !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv && - !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma && + !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && !WILL_FIRE_RL_coreFix_memExe_doFinishMem && @@ -11062,8 +11063,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDeqStQ_St_Mem assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem = - coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt && !coreFix_memExe_lsq$firstSt[4] && coreFix_memExe_lsq$firstSt[158:157] == 2'd0 && !coreFix_memExe_lsq$firstSt[77] && @@ -11123,16 +11124,16 @@ module mkCore(CLK, // rule RL_prepareCachesAndTlbs assign CAN_FIRE_RL_prepareCachesAndTlbs = (!flush_tlbs || - coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush) && + fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush) && (flush_reservation || flush_tlbs || update_vm_info) ; assign WILL_FIRE_RL_prepareCachesAndTlbs = CAN_FIRE_RL_prepareCachesAndTlbs ; // rule RL_rl_debug_resume assign CAN_FIRE_RL_rl_debug_resume = - commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush && - fetchStage$RDY_iTlbIfc_flush && + commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush && + coreFix_memExe_dTlb$RDY_flush && f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd1 && @@ -11140,7 +11141,9 @@ module mkCore(CLK, !f_gpr_reqs$EMPTY_N && !f_fpr_reqs$EMPTY_N && !f_csr_reqs$EMPTY_N ; - assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ; + assign WILL_FIRE_RL_rl_debug_resume = + CAN_FIRE_RL_rl_debug_resume && + !WILL_FIRE_RL_prepareCachesAndTlbs ; // rule RL_coreFix_memExe_doRegReadMem assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem = @@ -11158,8 +11161,8 @@ module mkCore(CLK, // rule RL_coreFix_memExe_doDispatchMem assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem = coreFix_memExe_dispToRegQ$RDY_enq && - coreFix_memExe_rsMem$RDY_doDispatch && - coreFix_memExe_rsMem$RDY_dispatchData ; + coreFix_memExe_rsMem$RDY_dispatchData && + coreFix_memExe_rsMem$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem = CAN_FIRE_RL_coreFix_memExe_doDispatchMem && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11172,7 +11175,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ; @@ -11203,7 +11206,7 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty && coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send && - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 ; assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer = CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ; @@ -11279,10 +11282,6 @@ module mkCore(CLK, assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon = 1'd1 ; - // rule RL_coreFix_memExe_memRespLdQ_canonicalize - assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; - assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; - // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ; @@ -11299,6 +11298,10 @@ module mkCore(CLK, assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ; + // rule RL_coreFix_memExe_memRespLdQ_canonicalize + assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; + assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ; + // rule RL_coreFix_memExe_memRespLdQ_clearReq_canon assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ; assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ; @@ -11391,8 +11394,8 @@ module mkCore(CLK, // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch && - coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ; + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData && + coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ; assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv && !WILL_FIRE_RL_commitStage_doCommitKilledLd && @@ -11412,9 +11415,9 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_Trap assign CAN_FIRE_RL_renameStage_doRenaming_Trap = - epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq && + rob$RDY_enqPort_0_enq && fetchStage$RDY_pipelines_0_deq && fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && + epochManager$RDY_incrementEpoch && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 && rob$isEmpty && rg_core_run_state == 2'd2 ; @@ -11426,8 +11429,8 @@ module mkCore(CLK, // rule RL_renameStage_doRenaming_SystemInst assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst = - epochManager$RDY_incrementEpoch && - rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309 && + rob$RDY_enqPort_0_enq && + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 && mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 && rg_core_run_state == 2'd2 ; assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst = @@ -11513,10 +11516,13 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_fpr_read ; assign MUX_commitStage_rg_run_state$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ; + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 ; assign MUX_commitStage_rg_serial_num$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 ; + assign MUX_commitStage_rg_serial_num$write_1__SEL_2 = + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || + WILL_FIRE_RL_commitStage_doCommitSystemInst ; assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq && @@ -11525,7 +11531,8 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitKilledLd || WILL_FIRE_RL_commitStage_doCommitTrap_flush ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; + WILL_FIRE_RL_renameStage_doRenaming_SystemInst && + fetchStage$pipelines_0_first[194:192] == 3'd0 ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple && coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ; @@ -11708,9 +11715,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd9 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22) ; assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11718,9 +11725,9 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd16 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29) ; assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11729,20 +11736,20 @@ module mkCore(CLK, assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29 ; assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd836 ; assign MUX_csrf_fflags_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 ; + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 ; assign MUX_csrf_fflags_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd0 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) ; assign MUX_csrf_fflags_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11751,22 +11758,22 @@ module mkCore(CLK, assign MUX_csrf_frm_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) ; assign MUX_csrf_fs_reg$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd0 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ; assign MUX_csrf_fs_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11778,9 +11785,9 @@ module mkCore(CLK, assign MUX_csrf_ie_vec_0$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ; assign MUX_csrf_ie_vec_0$write_1__SEL_2 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11790,21 +11797,21 @@ module mkCore(CLK, WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; assign MUX_csrf_ie_vec_1$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ; assign MUX_csrf_ie_vec_3$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; assign MUX_csrf_ie_vec_3$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 ; assign MUX_csrf_ie_vec_3$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd27 ; assign MUX_csrf_mcause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11818,7 +11825,7 @@ module mkCore(CLK, assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd30 ; assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11826,7 +11833,7 @@ module mkCore(CLK, assign MUX_csrf_mepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd26 ; assign MUX_csrf_mepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11840,7 +11847,7 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd31 ; assign MUX_csrf_mpp_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; @@ -11850,7 +11857,7 @@ module mkCore(CLK, assign MUX_csrf_mtval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd28 ; assign MUX_csrf_mtval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11873,12 +11880,12 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40 ; assign MUX_csrf_rg_dpc$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd41 ; assign MUX_csrf_rg_dpc$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11904,7 +11911,7 @@ module mkCore(CLK, assign MUX_csrf_scause_code_reg$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd14 ; assign MUX_csrf_scause_code_reg$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11915,7 +11922,7 @@ module mkCore(CLK, assign MUX_csrf_sepc_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd13 ; assign MUX_csrf_sepc_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11935,7 +11942,7 @@ module mkCore(CLK, assign MUX_csrf_stval_csr$write_1__SEL_1 = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd15 ; assign MUX_csrf_stval_csr$write_1__SEL_3 = WILL_FIRE_RL_rl_debug_csr_write && @@ -11953,7 +11960,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 && NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205 && IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 ; - assign MUX_flush_reservation$write_1__SEL_2 = + assign MUX_flush_reservation$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ; assign MUX_flush_tlbs$write_1__SEL_1 = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ; @@ -11988,7 +11995,7 @@ module mkCore(CLK, MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ; assign MUX_rg_core_run_state$write_1__SEL_4 = WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ; - assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 = + assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 = WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ; @@ -12010,9 +12017,6 @@ module mkCore(CLK, coreFix_memExe_lsq$firstLd[89] ; assign MUX_sbCons$setReady_3_put_1__SEL_3 = MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ; - assign MUX_started$write_1__SEL_1 = - CAN_FIRE_RL_rl_debug_resume && - !WILL_FIRE_RL_prepareCachesAndTlbs ; assign MUX_v_f_to_TV_0$enq_1__SEL_2 = WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq ; @@ -12023,15 +12027,27 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h701397, - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, + x__h702377, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h732518 ; + commitStage_rg_serial_num + y__h733553 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h669623 == 1'd0 && + { fetchStage$pipelines_0_first[199:195], + IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, + fetchStage$pipelines_0_first[173], + IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, + fetchStage$pipelines_0_first[160:128], + fetchStage$pipelines_0_first[255:232], + regRenamingTable$rename_0_getRename, + rob$enqPort_0_getEnqInstTag, + specTagManager$currentSpecBits, + 5'd10, + sbAggr$eagerLookup_0_get } ; + assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = + (k__h669625 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12052,22 +12068,10 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; - assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - { fetchStage$pipelines_0_first[199:195], - IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, - fetchStage$pipelines_0_first[173], - IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973, - fetchStage$pipelines_0_first[160:128], - fetchStage$pipelines_0_first[255:232], - regRenamingTable$rename_0_getRename, - rob$enqPort_0_getEnqInstTag, - specTagManager$currentSpecBits, - 5'd10, - sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 = { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ; assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 = @@ -12155,7 +12159,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, @@ -12169,10 +12173,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h285845 } ; + x__h285846 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h287290, + x__h287291, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12180,7 +12184,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h290066, + addr__h290067, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12193,12 +12197,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h153724, x__h153730, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h153725, x__h153731, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h157271, x__h157277, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h157272, x__h157278, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h160087, - x__h160091, + { x__h160088, + x__h160092, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -12209,7 +12213,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161939, + x__h161940, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -12222,7 +12226,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h291970, + resp_addr__h291971, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -12230,8 +12234,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h734208, - prv__h734208 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h735243, + prv__h735243 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12308,7 +12312,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h197125 } ; + x__h197126 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12343,8 +12347,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h192915 : - { {32{x__h193678[31]}}, x__h193678 } } ; + curData__h192916 : + { {32{x__h193679[31]}}, x__h193679 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12377,9 +12381,9 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h732495 ; + csrf_fflags_reg | fflags__h733530 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] : robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ; @@ -12387,10 +12391,10 @@ module mkCore(CLK, (f_csr_reqs$D_OUT[75:64] == 12'd2) ? f_csr_reqs$D_OUT[2:0] : f_csr_reqs$D_OUT[7:5] ; - always@(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 or + always@(IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973) + case (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983) 6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11; default: MUX_csrf_fs_reg$write_1__VAL_2 = robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13]; @@ -12405,55 +12409,55 @@ module mkCore(CLK, end assign MUX_csrf_ie_vec_1$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18)) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] : csrf_prev_ie_vec_1 ; assign MUX_csrf_ie_vec_3$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ? robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] : csrf_prev_ie_vec_3 ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h725937 + 64'd1 ; + n__read__h726937 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h725937 + { 62'd0, x__h732759 } ; + n__read__h726937 + { 62'd0, x__h733794 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) ? MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd8 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[5] ; assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd18 || MUX_csrf_mtval_csr$write_1__VAL_1[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h721573 : + x__h722556 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h707982, + dcsr_cause__h708962, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12463,13 +12467,13 @@ module mkCore(CLK, amoExec___d880[0] ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h736609 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h737644 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12478,12 +12482,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h721469 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h722452 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h721469; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h722452; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12495,7 +12499,7 @@ module mkCore(CLK, assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, mmio_dataReqQ_data_0[141:78], - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274, + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, mmio_dataReqQ_data_0[71:0] } ; assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 = { 1'd1, @@ -12518,24 +12522,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h337873 : - res_data__h337868 ; + res_data__h337874 : + res_data__h337869 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h383575 : - res_data__h383570 ; + res_data__h383576 : + res_data__h383571 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h429270 : - res_data__h429265 ; + res_data__h429271 : + res_data__h429266 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h475007 : + data___1__h475008 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h475815 : - data__h475281 ; + data___1__h475816 : + data__h475282 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -12595,54 +12599,57 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd0, 13'h1521, specTagManager$currentSpecBits } ; - assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 = + assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 = { 1'd1, - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 } ; + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 } ; assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 = { 1'd1, - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 } ; + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 } ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h337869 ; + res_fflags__h337870 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h383571 ; + res_fflags__h383572 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h429266 ; + res_fflags__h429267 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, commitStage_f_rob_data$D_OUT[425:181], - CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277, - commitStage_f_rob_data$D_OUT[167:166], - commitStage_f_rob_data$D_OUT[166] ? - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 : - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279, - IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916 } ; + CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279, + commitStage_f_rob_data_first__4755_BIT_167_485_ETC___d14927 } ; assign MUX_v_f_to_TV_0$enq_1__VAL_2 = { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494, + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501, - fflags__h727255, + IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512, + fflags__h728257, rob$deqPort_0_deq_data[26], - x__h728883, + x__h729900, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, - x__h722034, + 13'd4932, + mip_csr__read__h611252, + 721'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign MUX_v_f_to_TV_0$enq_1__VAL_5 = + { commitStage_rg_serial_num, + 77'h0AAAAAAAAAAAAAAAAAAA, + x__h723033, rob$deqPort_0_deq_data[361:182], - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494, + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[167], - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, - rob$deqPort_0_deq_data[161:98], - IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281 } ; + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, + rob_deqPort_0_deq_data__4339_BITS_161_TO_98_43_ETC___d15292 } ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -12932,18 +12939,23 @@ module mkCore(CLK, assign commitStage_rg_just_after_reset$EN = CAN_FIRE_RL_commitStage_rl_send_tv_reset ; + // register commitStage_rg_old_mip_csr_val + assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h611252 ; + assign commitStage_rg_old_mip_csr_val$EN = + CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; + // register commitStage_rg_run_state assign commitStage_rg_run_state$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign commitStage_rg_run_state$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_rl_debug_resume ; // register commitStage_rg_serial_num always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_commitStage_rg_serial_num$write_1__VAL_1 or - WILL_FIRE_RL_commitStage_doCommitSystemInst or + MUX_commitStage_rg_serial_num$write_1__SEL_2 or WILL_FIRE_RL_commitStage_doCommitNormalInst or MUX_commitStage_rg_serial_num$write_1__VAL_3 or WILL_FIRE_RL_commitStage_rl_send_tv_reset) @@ -12952,7 +12964,7 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_1; - WILL_FIRE_RL_commitStage_doCommitSystemInst: + MUX_commitStage_rg_serial_num$write_1__SEL_2: commitStage_rg_serial_num$D_IN = MUX_commitStage_rg_serial_num$write_1__VAL_1; WILL_FIRE_RL_commitStage_doCommitNormalInst: @@ -12966,7 +12978,8 @@ module mkCore(CLK, end assign commitStage_rg_serial_num$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst || WILL_FIRE_RL_commitStage_doCommitNormalInst || WILL_FIRE_RL_commitStage_rl_send_tv_reset ; @@ -12990,8 +13003,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h604527 : - v__h603882 ; + v__h604528 : + v__h603883 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -13013,7 +13026,9 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd0 && @@ -13023,9 +13038,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ? - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] : - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd1 && @@ -13035,7 +13048,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd2 && @@ -13045,7 +13058,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd3 && @@ -13055,7 +13068,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd4 && @@ -13065,7 +13078,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd5 && @@ -13075,7 +13088,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd6 && @@ -13085,7 +13098,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN = - coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ; + coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7 && @@ -13098,7 +13111,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h296520 ; + _theResult_____2__h296521 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -13120,7 +13133,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h295940 ; + v__h295941 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -13166,7 +13179,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - _theResult_____2__h304516 ; + _theResult_____2__h304517 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -13184,7 +13197,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - v__h299285 ; + v__h299286 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13284,7 +13297,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - _theResult_____2__h310510 ; + _theResult_____2__h310511 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13302,7 +13315,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - v__h309799 ; + v__h309800 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13323,7 +13336,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h314073, + { x_addr__h314074, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13353,7 +13366,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - _theResult_____2__h318364 ; + _theResult_____2__h318365 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13371,7 +13384,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - v__h313675 ; + v__h313676 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13448,7 +13461,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - _theResult_____2__h331933 ; + _theResult_____2__h331934 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13466,7 +13479,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - v__h331501 ; + v__h331502 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13509,7 +13522,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - _theResult_____2__h328708 ; + _theResult_____2__h328709 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13527,7 +13540,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - v__h328276 ; + v__h328277 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13707,7 +13720,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22 ; // register csrf_external_int_pend_vec_0 @@ -13756,7 +13769,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd836 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29 || EN_setMEIP ; @@ -13778,12 +13791,12 @@ module mkCore(CLK, assign csrf_fflags_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd0 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd3) ; @@ -13796,9 +13809,9 @@ module mkCore(CLK, assign csrf_frm_reg$EN = WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd2) || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13820,7 +13833,7 @@ module mkCore(CLK, assign csrf_fs_reg$EN = MUX_csrf_fs_reg$write_1__SEL_2 || WILL_FIRE_RL_commitStage_doCommitNormalInst && - NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 || + NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd1 || f_csr_reqs$D_OUT[75:64] == 12'd2 || @@ -13853,13 +13866,13 @@ module mkCore(CLK, default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_ie_vec_3 always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or @@ -13875,24 +13888,24 @@ module mkCore(CLK, default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mcause_code_reg always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h708463 or + cause_code__h709443 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h708463; + csrf_mcause_code_reg$D_IN = cause_code__h709443; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -13901,11 +13914,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd27 ; // register csrf_mcause_interrupt_reg @@ -13928,11 +13941,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd834 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd27 ; // register csrf_mcounteren_cy_reg @@ -13945,7 +13958,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd24 ; // register csrf_mcounteren_ir_reg @@ -13958,7 +13971,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd24 ; // register csrf_mcounteren_tm_reg @@ -13971,7 +13984,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd774 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd24 ; // register csrf_mcycle_ehr_data_rl @@ -13988,7 +14001,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd20 ; // register csrf_medeleg_15_reg @@ -14001,7 +14014,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd20 ; // register csrf_medeleg_9_0_reg @@ -14014,7 +14027,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd770 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd20 ; // register csrf_mepc_csr @@ -14037,11 +14050,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd833 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd26 ; // register csrf_mideleg_11_reg @@ -14054,7 +14067,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_mideleg_1_0_reg @@ -14067,7 +14080,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_mideleg_5_3_reg @@ -14080,7 +14093,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_mideleg_9_7_reg @@ -14093,7 +14106,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd771 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd21 ; // register csrf_minstret_ehr_data_rl @@ -14118,12 +14131,12 @@ module mkCore(CLK, default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_mpp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_mprv_reg assign csrf_mprv_reg$D_IN = @@ -14135,7 +14148,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_mscratch_csr @@ -14148,19 +14161,19 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd832 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd25 ; // register csrf_mtval_csr always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h708464 or + trap_val__h709444 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h708464; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h709444; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14170,11 +14183,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd835 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd28 ; // register csrf_mtvec_base_hi_reg @@ -14187,7 +14200,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd23 ; // register csrf_mtvec_mode_low_reg @@ -14200,7 +14213,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd773 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd23 ; // register csrf_mxr_reg @@ -14224,7 +14237,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd17 ; // register csrf_prev_ie_vec_0 @@ -14253,13 +14266,13 @@ module mkCore(CLK, default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_1$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_prev_ie_vec_3 always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or @@ -14276,34 +14289,34 @@ module mkCore(CLK, default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_prev_ie_vec_3$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ; + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ; // register csrf_prv_reg always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h711506 or + x_prv__h712487 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h711506; + csrf_prv_reg$D_IN = x_prv__h712487; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; endcase assign csrf_prv_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || WILL_FIRE_RL_rl_debug_csr_write && - f_csr_reqs$D_OUT[75:64] == 12'd1968 ; + f_csr_reqs$D_OUT[75:64] == 12'd1968 || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ; // register csrf_rg_dcsr always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or @@ -14323,12 +14336,12 @@ module mkCore(CLK, endcase assign csrf_rg_dcsr$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1968 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40 ; // register csrf_rg_dpc @@ -14347,12 +14360,12 @@ module mkCore(CLK, endcase assign csrf_rg_dpc$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd1969 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd41 ; // register csrf_rg_dscratch0 @@ -14365,7 +14378,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1970 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd42 ; // register csrf_rg_dscratch1 @@ -14378,7 +14391,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1971 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd43 ; // register csrf_rg_tdata1_data @@ -14391,7 +14404,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd37 ; // register csrf_rg_tdata1_dmode @@ -14404,7 +14417,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1953 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd37 ; // register csrf_rg_tdata2 @@ -14417,7 +14430,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1954 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd38 ; // register csrf_rg_tdata3 @@ -14430,7 +14443,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1955 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd39 ; // register csrf_rg_tselect @@ -14443,20 +14456,20 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd1952 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd36 ; // register csrf_scause_code_reg always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h708463 or + cause_code__h709443 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h708463; + csrf_scause_code_reg$D_IN = cause_code__h709443; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14465,11 +14478,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd14 ; // register csrf_scause_interrupt_reg @@ -14492,11 +14505,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd322 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd14 ; // register csrf_scounteren_cy_reg @@ -14509,7 +14522,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd11 ; // register csrf_scounteren_ir_reg @@ -14522,7 +14535,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd11 ; // register csrf_scounteren_tm_reg @@ -14535,7 +14548,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd262 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd11 ; // register csrf_sepc_csr @@ -14558,11 +14571,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd321 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd13 ; // register csrf_software_int_en_vec_0 @@ -14590,7 +14603,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22 ; // register csrf_software_int_pend_vec_0 @@ -14634,7 +14647,7 @@ module mkCore(CLK, mmio_pRqQ_data_0[37:36] != 2'd1 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd29 ; // register csrf_spp_reg @@ -14651,13 +14664,13 @@ module mkCore(CLK, default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_spp_reg$EN = - WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_rl_debug_csr_write && (f_csr_reqs$D_OUT[75:64] == 12'd256 || - f_csr_reqs$D_OUT[75:64] == 12'd768) ; + f_csr_reqs$D_OUT[75:64] == 12'd768) || + WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ; // register csrf_sscratch_csr assign csrf_sscratch_csr$D_IN = @@ -14669,7 +14682,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd320 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd12 ; // register csrf_stats_module_doStats @@ -14680,12 +14693,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h708464 or + trap_val__h709444 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h708464; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h709444; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14695,11 +14708,11 @@ module mkCore(CLK, WILL_FIRE_RL_rl_debug_csr_write && f_csr_reqs$D_OUT[75:64] == 12'd323 || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 && - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 && + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd15 ; // register csrf_stvec_base_hi_reg @@ -14712,7 +14725,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd10 ; // register csrf_stvec_mode_low_reg @@ -14725,7 +14738,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd261 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd10 ; // register csrf_sum_reg @@ -14768,7 +14781,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd772 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd22 ; // register csrf_timer_int_pend_vec_0 @@ -14802,7 +14815,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_tvm_reg @@ -14815,7 +14828,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_tw_reg @@ -14828,7 +14841,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd768 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 ; // register csrf_vm_mode_sv39_reg @@ -14841,28 +14854,28 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd384 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd17 ; // register flush_brpred assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_brpred$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_flushBrPred ; // register flush_caches assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ; assign flush_caches$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_flushCaches ; // register flush_reservation - assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ; + assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ; assign flush_reservation$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // register flush_tlbs @@ -14870,11 +14883,11 @@ module mkCore(CLK, assign flush_tlbs$EN = WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs || WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_commitStage_doCommitSystemInst && (rob$deqPort_0_deq_data[329:325] == 5'd16 || rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd17) ; // register mmio_cRqQ_clearReq_rl @@ -14883,7 +14896,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46291, + { x__h46292, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14895,7 +14908,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48827 } ; + x__h48828 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -14988,7 +15001,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18384, + { x__h18385, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15000,7 +15013,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20922 } ; + x__h20923 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -15084,7 +15097,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h66085 } ; + x_data__h66086 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -15207,18 +15220,18 @@ module mkCore(CLK, assign update_vm_info$D_IN = !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ; assign update_vm_info$EN = - WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 || WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info || + WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo22 || WILL_FIRE_RL_commitStage_doCommitSystemInst ; // submodule commitStage_f_rob_data assign commitStage_f_rob_data$D_IN = { rob$deqPort_0_deq_data[425:182], - rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494, + rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[168:167], - rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393, + rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[161:98], - IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501, + IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512, rob$deqPort_0_deq_data[31:0] } ; assign commitStage_f_rob_data$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_flush ; @@ -15327,8 +15340,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h639739, - x__h639740, + x__h639741, + x__h639742, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -15466,9 +15479,9 @@ module mkCore(CLK, endcase end assign coreFix_aluExe_0_rsAlu$EN_enq = - WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 || WILL_FIRE_RL_renameStage_doRenaming_SystemInst && - fetchStage$pipelines_0_first[194:192] == 3'd0 ; + fetchStage$pipelines_0_first[194:192] == 3'd0 || + WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ; assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ; assign coreFix_aluExe_0_rsAlu$EN_doDispatch = WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ; @@ -15618,8 +15631,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h617230, - x__h617231, + x__h617232, + x__h617233, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -15661,7 +15674,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h669623 == 1'd1 && + (k__h669625 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -15682,7 +15695,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16161,19 +16174,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h603369 : - a__h602947 ; + _theResult___fst__h603370 : + a__h602948 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h602948 == 64'd0, - a__h602947, + { b__h602949 == 64'd0, + a__h602948, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h603383, - a__h602947[63], + x__h603384, + a__h602948[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h603370 : - b__h602948 ; + _theResult___snd__h603371 : + b__h602949 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -16234,20 +16247,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602947 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602948 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602948 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602949 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h602947 ; + a__h602948 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h602948 ; + b__h602949 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h602947 ; + a__h602948 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h602948 ; + b__h602949 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -16276,9 +16289,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h481669, x__h481670, x__h481671, + x__h481672, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -16330,7 +16343,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16484,8 +16497,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h287278, - x__h287290, + { x__h287279, + x__h287291, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797, @@ -16496,13 +16509,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828, - x__h289144, + x__h289145, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h285845 ; + x__h285846 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -16725,7 +16738,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN = 1'd1 ; assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN = - MUX_flush_reservation$write_1__SEL_2 ; + MUX_flush_reservation$write_1__SEL_1 ; // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r = @@ -17296,7 +17309,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685237 ; + renaming_spec_bits__h685239 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? @@ -17316,7 +17329,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685237 ; + renaming_spec_bits__h685239 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17396,7 +17409,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h181566 ; + shiftData__h181567 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17496,8 +17509,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h181475, x__h181476, + x__h181477, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -17761,7 +17774,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685237, + renaming_spec_bits__h685239, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17989,7 +18002,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2816 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd30 ; // submodule csrf_mcycle_ehr_data_dummy2_1 @@ -18003,7 +18016,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2818 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd31 ; // submodule csrf_minstret_ehr_data_dummy2_1 @@ -18021,7 +18034,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2049 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd7 ; assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ; assign csrf_stats_module_writeQ$CLR = 1'b0 ; @@ -18032,7 +18045,7 @@ module mkCore(CLK, f_csr_reqs$D_OUT[75:64] == 12'd2048 || WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd6 ; assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ; assign csrf_terminate_module_terminateQ$CLR = 1'b0 ; @@ -18209,7 +18222,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h711407 or + pc__h712387 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18223,7 +18236,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h711407; + fetchStage$redirect_pc = pc__h712387; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18322,14 +18335,14 @@ module mkCore(CLK, assign fetchStage$EN_stop = 1'b0 ; assign fetchStage$EN_setWaitRedirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || WILL_FIRE_RL_commitStage_doCommitTrap_flush && !rob$deqPort_0_deq_data[12] || WILL_FIRE_RL_renameStage_doRenaming_SystemInst || WILL_FIRE_RL_renameStage_doRenaming_Trap ; assign fetchStage$EN_redirect = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T || WILL_FIRE_RL_commitStage_doCommitKilledLd || @@ -18643,7 +18656,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h685237 ; + renaming_spec_bits__h685239 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -18915,7 +18928,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, 7'd32, - renaming_spec_bits__h685237 } ; + renaming_spec_bits__h685239 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18925,24 +18938,24 @@ module mkCore(CLK, coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; - always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or - MUX_rob$setExecuted_deqLSQ_2__VAL_3 or - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or + MUX_rob$setExecuted_deqLSQ_2__VAL_2 or + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or MUX_rob$setExecuted_deqLSQ_2__VAL_6 or + MUX_rob$setExecuted_deqLSQ_1__SEL_1 or MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or - MUX_rob$setExecuted_deqLSQ_1__SEL_5 or WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: - rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3; WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault: + rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2; + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault: rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6; + MUX_rob$setExecuted_deqLSQ_1__SEL_1 || MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - MUX_rob$setExecuted_deqLSQ_1__SEL_5: + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem: rob$setExecuted_deqLSQ_cause = 5'd10; WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault: rob$setExecuted_deqLSQ_cause = 5'd21; @@ -19231,16 +19244,16 @@ module mkCore(CLK, assign rob$EN_setLSQAtCommitNotified = CAN_FIRE_RL_commitStage_notifyLSQCommit ; assign rob$EN_setExecuted_deqLSQ = - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence || WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault || - WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ; + WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault || + WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ; assign rob$EN_setExecuted_doFinishAlu_0_set = WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ; @@ -19533,8 +19546,10 @@ module mkCore(CLK, MUX_v_f_to_TV_0$enq_1__SEL_2 or MUX_v_f_to_TV_0$enq_1__VAL_2 or WILL_FIRE_RL_commitStage_rl_send_tv_reset or + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv or + MUX_v_f_to_TV_0$enq_1__VAL_4 or WILL_FIRE_RL_commitStage_doCommitSystemInst or - MUX_v_f_to_TV_0$enq_1__VAL_4) + MUX_v_f_to_TV_0$enq_1__VAL_5) begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: @@ -19543,35 +19558,39 @@ module mkCore(CLK, v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_2; WILL_FIRE_RL_commitStage_rl_send_tv_reset: v_f_to_TV_0$D_IN = - 785'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - WILL_FIRE_RL_commitStage_doCommitSystemInst: + 862'h000000000000000015555555555555555554AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv: v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_4; + WILL_FIRE_RL_commitStage_doCommitSystemInst: + v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_5; default: v_f_to_TV_0$D_IN = - 785'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + 862'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign v_f_to_TV_0$ENQ = WILL_FIRE_RL_commitStage_doCommitTrap_handle && - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 || WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq || WILL_FIRE_RL_commitStage_rl_send_tv_reset || + WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv || WILL_FIRE_RL_commitStage_doCommitSystemInst ; assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ; assign v_f_to_TV_0$CLR = 1'b0 ; // submodule v_f_to_TV_1 assign v_f_to_TV_1$D_IN = - { commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438, + { commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450, + 77'h0AAAAAAAAAAAAAAAAAAA, rob$deqPort_1_deq_data[425:181], CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300, 6'd10, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, rob$deqPort_1_deq_data[95:32], - fflags__h729891, + fflags__h730910, rob$deqPort_1_deq_data[26], - x__h732011, + x__h733045, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19593,33 +19612,21 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h192915), + .amoExec_current_data(curData__h192916), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h194453)); + .amoExec(n__h194454)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h76121 }), - .amoExec_in_data({ 32'd0, x__h76236 }), + msip__h76122 }), + .amoExec_in_data({ 32'd0, x__h76237 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d880)); - module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228, - { coreFix_aluExe_0_regToExeQ$first[395], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229, - coreFix_aluExe_0_regToExeQ$first[382], - coreFix_aluExe_0_regToExeQ$first[381:350] } }), - .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), - .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), - .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), - .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), - .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), - .basicExec(basicExec___d12617)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228, { coreFix_aluExe_1_regToExeQ$first[395], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229, coreFix_aluExe_1_regToExeQ$first[382], coreFix_aluExe_1_regToExeQ$first[381:350] } }), .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]), @@ -19628,12 +19635,24 @@ module mkCore(CLK, .basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]), .basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]), .basicExec(basicExec___d11943)); + module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, + { coreFix_aluExe_0_regToExeQ$first[395], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232, + coreFix_aluExe_0_regToExeQ$first[382], + coreFix_aluExe_0_regToExeQ$first[381:350] } }), + .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]), + .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]), + .basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]), + .basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]), + .basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]), + .basicExec(basicExec___d12617)); module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 }, fetchStage$pipelines_0_first[160], - x_data_imm__h676655 } }), + x_data_imm__h676657 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19642,13 +19661,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655010, - r1__read_BITS_13_TO_12___h655195 != + .checkForException_csrState({ x_decodeInfo_frm__h655012, + r1__read_BITS_13_TO_12___h655197 != 2'd0, - { prv__h734164, - tvm_val__h725554, - { r1__read_BIT_20___h655891, - tsr_val__h725552, + { prv__h735199, + tvm_val__h726553, + { r1__read_BIT_20___h655893, + tsr_val__h726551, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19663,7 +19682,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, { fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, fetchStage$pipelines_1_first[160], - x_data_imm__h692709 } }), + x_data_imm__h692711 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19672,13 +19691,13 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655010, - r1__read_BITS_13_TO_12___h655195 != + .checkForException_csrState({ x_decodeInfo_frm__h655012, + r1__read_BITS_13_TO_12___h655197 != 2'd0, - { prv__h734164, - tvm_val__h725554, - { r1__read_BIT_20___h655891, - tsr_val__h725552, + { prv__h735199, + tvm_val__h726553, + { r1__read_BIT_20___h655893, + tsr_val__h726551, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19690,1198 +19709,1198 @@ module mkCore(CLK, csrf_scounteren_tm_reg } } } } } }), .checkForException(checkForException___d13698)); module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254, + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h481760), - .execFpuSimple_rVal2(rVal2__h481761), + .execFpuSimple_rVal1(rVal1__h481761), + .execFpuSimple_rVal2(rVal2__h481762), .execFpuSimple(execFpuSimple___d11056)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 ? - _theResult___snd__h354258 : - _theResult____h346084 ; + _theResult___snd__h354259 : + _theResult____h346085 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 ? - _theResult___snd__h399955 : - _theResult____h391783 ; + _theResult___snd__h399956 : + _theResult____h391784 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 ? - _theResult___snd__h445650 : - _theResult____h437478 ; + _theResult___snd__h445651 : + _theResult____h437479 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 ? - _theResult___snd__h511167 : - _theResult____h502868 ; + _theResult___snd__h511168 : + _theResult____h502869 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 ? - _theResult___snd__h589324 : - _theResult____h581025 ; + _theResult___snd__h589325 : + _theResult____h581026 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 ? - _theResult___snd__h550020 : - _theResult____h541721 ; + _theResult___snd__h550021 : + _theResult____h541722 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 ? - _theResult___snd__h463416 : - _theResult____h455115 ; + _theResult___snd__h463417 : + _theResult____h455116 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 ? - _theResult___snd__h372024 : - _theResult____h363723 ; + _theResult___snd__h372025 : + _theResult____h363724 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 ? - _theResult___snd__h417721 : - _theResult____h409420 ; + _theResult___snd__h417722 : + _theResult____h409421 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 ? - _theResult___snd__h501516 : + _theResult___snd__h501517 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 ? - _theResult___snd__h501516 : - _theResult___snd__h519921 ; + _theResult___snd__h501517 : + _theResult___snd__h519922 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 ? - _theResult___snd__h579673 : + _theResult___snd__h579674 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 ? - _theResult___snd__h579673 : - _theResult___snd__h598078 ; + _theResult___snd__h579674 : + _theResult___snd__h598079 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 ? - _theResult___snd__h540369 : + _theResult___snd__h540370 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 ? - _theResult___snd__h540369 : - _theResult___snd__h558774 ; + _theResult___snd__h540370 : + _theResult___snd__h558775 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 ? - _theResult___snd__h454232 : + _theResult___snd__h454233 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 ? - _theResult___snd__h454232 : - _theResult___snd__h472022 ; + _theResult___snd__h454233 : + _theResult___snd__h472023 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 ? - _theResult___snd__h362840 : + _theResult___snd__h362841 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 ? - _theResult___snd__h362840 : - _theResult___snd__h380630 ; + _theResult___snd__h362841 : + _theResult___snd__h380631 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 ? - _theResult___snd__h408537 : + _theResult___snd__h408538 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 ? - _theResult___snd__h408537 : - _theResult___snd__h426327 ; + _theResult___snd__h408538 : + _theResult___snd__h426328 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354195 == 8'd255) ? + ((_theResult___fst_exp__h354196 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054) : - ((_theResult___fst_exp__h362851 == 8'd255) ? + ((_theResult___fst_exp__h362852 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354195 == 8'd255) ? + ((_theResult___fst_exp__h354196 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110) : - ((_theResult___fst_exp__h362851 == 8'd255) ? + ((_theResult___fst_exp__h362852 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399892 == 8'd255) ? + ((_theResult___fst_exp__h399893 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446) : - ((_theResult___fst_exp__h408548 == 8'd255) ? + ((_theResult___fst_exp__h408549 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399892 == 8'd255) ? + ((_theResult___fst_exp__h399893 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502) : - ((_theResult___fst_exp__h408548 == 8'd255) ? + ((_theResult___fst_exp__h408549 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445587 == 8'd255) ? + ((_theResult___fst_exp__h445588 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838) : - ((_theResult___fst_exp__h454243 == 8'd255) ? + ((_theResult___fst_exp__h454244 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445587 == 8'd255) ? + ((_theResult___fst_exp__h445588 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894) : - ((_theResult___fst_exp__h454243 == 8'd255) ? + ((_theResult___fst_exp__h454244 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 = - (_theResult____h346084[56] ? + (_theResult____h346085[56] ? 6'd0 : - (_theResult____h346084[55] ? + (_theResult____h346085[55] ? 6'd1 : - (_theResult____h346084[54] ? + (_theResult____h346085[54] ? 6'd2 : - (_theResult____h346084[53] ? + (_theResult____h346085[53] ? 6'd3 : - (_theResult____h346084[52] ? + (_theResult____h346085[52] ? 6'd4 : - (_theResult____h346084[51] ? + (_theResult____h346085[51] ? 6'd5 : - (_theResult____h346084[50] ? + (_theResult____h346085[50] ? 6'd6 : - (_theResult____h346084[49] ? + (_theResult____h346085[49] ? 6'd7 : - (_theResult____h346084[48] ? + (_theResult____h346085[48] ? 6'd8 : - (_theResult____h346084[47] ? + (_theResult____h346085[47] ? 6'd9 : - (_theResult____h346084[46] ? + (_theResult____h346085[46] ? 6'd10 : - (_theResult____h346084[45] ? + (_theResult____h346085[45] ? 6'd11 : - (_theResult____h346084[44] ? + (_theResult____h346085[44] ? 6'd12 : - (_theResult____h346084[43] ? + (_theResult____h346085[43] ? 6'd13 : - (_theResult____h346084[42] ? + (_theResult____h346085[42] ? 6'd14 : - (_theResult____h346084[41] ? + (_theResult____h346085[41] ? 6'd15 : - (_theResult____h346084[40] ? + (_theResult____h346085[40] ? 6'd16 : - (_theResult____h346084[39] ? + (_theResult____h346085[39] ? 6'd17 : - (_theResult____h346084[38] ? + (_theResult____h346085[38] ? 6'd18 : - (_theResult____h346084[37] ? + (_theResult____h346085[37] ? 6'd19 : - (_theResult____h346084[36] ? + (_theResult____h346085[36] ? 6'd20 : - (_theResult____h346084[35] ? + (_theResult____h346085[35] ? 6'd21 : - (_theResult____h346084[34] ? + (_theResult____h346085[34] ? 6'd22 : - (_theResult____h346084[33] ? + (_theResult____h346085[33] ? 6'd23 : - (_theResult____h346084[32] ? + (_theResult____h346085[32] ? 6'd24 : - (_theResult____h346084[31] ? + (_theResult____h346085[31] ? 6'd25 : - (_theResult____h346084[30] ? + (_theResult____h346085[30] ? 6'd26 : - (_theResult____h346084[29] ? + (_theResult____h346085[29] ? 6'd27 : - (_theResult____h346084[28] ? + (_theResult____h346085[28] ? 6'd28 : - (_theResult____h346084[27] ? + (_theResult____h346085[27] ? 6'd29 : - (_theResult____h346084[26] ? + (_theResult____h346085[26] ? 6'd30 : - (_theResult____h346084[25] ? + (_theResult____h346085[25] ? 6'd31 : - (_theResult____h346084[24] ? + (_theResult____h346085[24] ? 6'd32 : - (_theResult____h346084[23] ? + (_theResult____h346085[23] ? 6'd33 : - (_theResult____h346084[22] ? + (_theResult____h346085[22] ? 6'd34 : - (_theResult____h346084[21] ? + (_theResult____h346085[21] ? 6'd35 : - (_theResult____h346084[20] ? + (_theResult____h346085[20] ? 6'd36 : - (_theResult____h346084[19] ? + (_theResult____h346085[19] ? 6'd37 : - (_theResult____h346084[18] ? + (_theResult____h346085[18] ? 6'd38 : - (_theResult____h346084[17] ? + (_theResult____h346085[17] ? 6'd39 : - (_theResult____h346084[16] ? + (_theResult____h346085[16] ? 6'd40 : - (_theResult____h346084[15] ? + (_theResult____h346085[15] ? 6'd41 : - (_theResult____h346084[14] ? + (_theResult____h346085[14] ? 6'd42 : - (_theResult____h346084[13] ? + (_theResult____h346085[13] ? 6'd43 : - (_theResult____h346084[12] ? + (_theResult____h346085[12] ? 6'd44 : - (_theResult____h346084[11] ? + (_theResult____h346085[11] ? 6'd45 : - (_theResult____h346084[10] ? + (_theResult____h346085[10] ? 6'd46 : - (_theResult____h346084[9] ? + (_theResult____h346085[9] ? 6'd47 : - (_theResult____h346084[8] ? + (_theResult____h346085[8] ? 6'd48 : - (_theResult____h346084[7] ? + (_theResult____h346085[7] ? 6'd49 : - (_theResult____h346084[6] ? + (_theResult____h346085[6] ? 6'd50 : - (_theResult____h346084[5] ? + (_theResult____h346085[5] ? 6'd51 : - (_theResult____h346084[4] ? + (_theResult____h346085[4] ? 6'd52 : - (_theResult____h346084[3] ? + (_theResult____h346085[3] ? 6'd53 : - (_theResult____h346084[2] ? + (_theResult____h346085[2] ? 6'd54 : - (_theResult____h346084[1] ? + (_theResult____h346085[1] ? 6'd55 : - (_theResult____h346084[0] ? + (_theResult____h346085[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 = - (_theResult____h391783[56] ? + (_theResult____h391784[56] ? 6'd0 : - (_theResult____h391783[55] ? + (_theResult____h391784[55] ? 6'd1 : - (_theResult____h391783[54] ? + (_theResult____h391784[54] ? 6'd2 : - (_theResult____h391783[53] ? + (_theResult____h391784[53] ? 6'd3 : - (_theResult____h391783[52] ? + (_theResult____h391784[52] ? 6'd4 : - (_theResult____h391783[51] ? + (_theResult____h391784[51] ? 6'd5 : - (_theResult____h391783[50] ? + (_theResult____h391784[50] ? 6'd6 : - (_theResult____h391783[49] ? + (_theResult____h391784[49] ? 6'd7 : - (_theResult____h391783[48] ? + (_theResult____h391784[48] ? 6'd8 : - (_theResult____h391783[47] ? + (_theResult____h391784[47] ? 6'd9 : - (_theResult____h391783[46] ? + (_theResult____h391784[46] ? 6'd10 : - (_theResult____h391783[45] ? + (_theResult____h391784[45] ? 6'd11 : - (_theResult____h391783[44] ? + (_theResult____h391784[44] ? 6'd12 : - (_theResult____h391783[43] ? + (_theResult____h391784[43] ? 6'd13 : - (_theResult____h391783[42] ? + (_theResult____h391784[42] ? 6'd14 : - (_theResult____h391783[41] ? + (_theResult____h391784[41] ? 6'd15 : - (_theResult____h391783[40] ? + (_theResult____h391784[40] ? 6'd16 : - (_theResult____h391783[39] ? + (_theResult____h391784[39] ? 6'd17 : - (_theResult____h391783[38] ? + (_theResult____h391784[38] ? 6'd18 : - (_theResult____h391783[37] ? + (_theResult____h391784[37] ? 6'd19 : - (_theResult____h391783[36] ? + (_theResult____h391784[36] ? 6'd20 : - (_theResult____h391783[35] ? + (_theResult____h391784[35] ? 6'd21 : - (_theResult____h391783[34] ? + (_theResult____h391784[34] ? 6'd22 : - (_theResult____h391783[33] ? + (_theResult____h391784[33] ? 6'd23 : - (_theResult____h391783[32] ? + (_theResult____h391784[32] ? 6'd24 : - (_theResult____h391783[31] ? + (_theResult____h391784[31] ? 6'd25 : - (_theResult____h391783[30] ? + (_theResult____h391784[30] ? 6'd26 : - (_theResult____h391783[29] ? + (_theResult____h391784[29] ? 6'd27 : - (_theResult____h391783[28] ? + (_theResult____h391784[28] ? 6'd28 : - (_theResult____h391783[27] ? + (_theResult____h391784[27] ? 6'd29 : - (_theResult____h391783[26] ? + (_theResult____h391784[26] ? 6'd30 : - (_theResult____h391783[25] ? + (_theResult____h391784[25] ? 6'd31 : - (_theResult____h391783[24] ? + (_theResult____h391784[24] ? 6'd32 : - (_theResult____h391783[23] ? + (_theResult____h391784[23] ? 6'd33 : - (_theResult____h391783[22] ? + (_theResult____h391784[22] ? 6'd34 : - (_theResult____h391783[21] ? + (_theResult____h391784[21] ? 6'd35 : - (_theResult____h391783[20] ? + (_theResult____h391784[20] ? 6'd36 : - (_theResult____h391783[19] ? + (_theResult____h391784[19] ? 6'd37 : - (_theResult____h391783[18] ? + (_theResult____h391784[18] ? 6'd38 : - (_theResult____h391783[17] ? + (_theResult____h391784[17] ? 6'd39 : - (_theResult____h391783[16] ? + (_theResult____h391784[16] ? 6'd40 : - (_theResult____h391783[15] ? + (_theResult____h391784[15] ? 6'd41 : - (_theResult____h391783[14] ? + (_theResult____h391784[14] ? 6'd42 : - (_theResult____h391783[13] ? + (_theResult____h391784[13] ? 6'd43 : - (_theResult____h391783[12] ? + (_theResult____h391784[12] ? 6'd44 : - (_theResult____h391783[11] ? + (_theResult____h391784[11] ? 6'd45 : - (_theResult____h391783[10] ? + (_theResult____h391784[10] ? 6'd46 : - (_theResult____h391783[9] ? + (_theResult____h391784[9] ? 6'd47 : - (_theResult____h391783[8] ? + (_theResult____h391784[8] ? 6'd48 : - (_theResult____h391783[7] ? + (_theResult____h391784[7] ? 6'd49 : - (_theResult____h391783[6] ? + (_theResult____h391784[6] ? 6'd50 : - (_theResult____h391783[5] ? + (_theResult____h391784[5] ? 6'd51 : - (_theResult____h391783[4] ? + (_theResult____h391784[4] ? 6'd52 : - (_theResult____h391783[3] ? + (_theResult____h391784[3] ? 6'd53 : - (_theResult____h391783[2] ? + (_theResult____h391784[2] ? 6'd54 : - (_theResult____h391783[1] ? + (_theResult____h391784[1] ? 6'd55 : - (_theResult____h391783[0] ? + (_theResult____h391784[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 = - (_theResult____h437478[56] ? + (_theResult____h437479[56] ? 6'd0 : - (_theResult____h437478[55] ? + (_theResult____h437479[55] ? 6'd1 : - (_theResult____h437478[54] ? + (_theResult____h437479[54] ? 6'd2 : - (_theResult____h437478[53] ? + (_theResult____h437479[53] ? 6'd3 : - (_theResult____h437478[52] ? + (_theResult____h437479[52] ? 6'd4 : - (_theResult____h437478[51] ? + (_theResult____h437479[51] ? 6'd5 : - (_theResult____h437478[50] ? + (_theResult____h437479[50] ? 6'd6 : - (_theResult____h437478[49] ? + (_theResult____h437479[49] ? 6'd7 : - (_theResult____h437478[48] ? + (_theResult____h437479[48] ? 6'd8 : - (_theResult____h437478[47] ? + (_theResult____h437479[47] ? 6'd9 : - (_theResult____h437478[46] ? + (_theResult____h437479[46] ? 6'd10 : - (_theResult____h437478[45] ? + (_theResult____h437479[45] ? 6'd11 : - (_theResult____h437478[44] ? + (_theResult____h437479[44] ? 6'd12 : - (_theResult____h437478[43] ? + (_theResult____h437479[43] ? 6'd13 : - (_theResult____h437478[42] ? + (_theResult____h437479[42] ? 6'd14 : - (_theResult____h437478[41] ? + (_theResult____h437479[41] ? 6'd15 : - (_theResult____h437478[40] ? + (_theResult____h437479[40] ? 6'd16 : - (_theResult____h437478[39] ? + (_theResult____h437479[39] ? 6'd17 : - (_theResult____h437478[38] ? + (_theResult____h437479[38] ? 6'd18 : - (_theResult____h437478[37] ? + (_theResult____h437479[37] ? 6'd19 : - (_theResult____h437478[36] ? + (_theResult____h437479[36] ? 6'd20 : - (_theResult____h437478[35] ? + (_theResult____h437479[35] ? 6'd21 : - (_theResult____h437478[34] ? + (_theResult____h437479[34] ? 6'd22 : - (_theResult____h437478[33] ? + (_theResult____h437479[33] ? 6'd23 : - (_theResult____h437478[32] ? + (_theResult____h437479[32] ? 6'd24 : - (_theResult____h437478[31] ? + (_theResult____h437479[31] ? 6'd25 : - (_theResult____h437478[30] ? + (_theResult____h437479[30] ? 6'd26 : - (_theResult____h437478[29] ? + (_theResult____h437479[29] ? 6'd27 : - (_theResult____h437478[28] ? + (_theResult____h437479[28] ? 6'd28 : - (_theResult____h437478[27] ? + (_theResult____h437479[27] ? 6'd29 : - (_theResult____h437478[26] ? + (_theResult____h437479[26] ? 6'd30 : - (_theResult____h437478[25] ? + (_theResult____h437479[25] ? 6'd31 : - (_theResult____h437478[24] ? + (_theResult____h437479[24] ? 6'd32 : - (_theResult____h437478[23] ? + (_theResult____h437479[23] ? 6'd33 : - (_theResult____h437478[22] ? + (_theResult____h437479[22] ? 6'd34 : - (_theResult____h437478[21] ? + (_theResult____h437479[21] ? 6'd35 : - (_theResult____h437478[20] ? + (_theResult____h437479[20] ? 6'd36 : - (_theResult____h437478[19] ? + (_theResult____h437479[19] ? 6'd37 : - (_theResult____h437478[18] ? + (_theResult____h437479[18] ? 6'd38 : - (_theResult____h437478[17] ? + (_theResult____h437479[17] ? 6'd39 : - (_theResult____h437478[16] ? + (_theResult____h437479[16] ? 6'd40 : - (_theResult____h437478[15] ? + (_theResult____h437479[15] ? 6'd41 : - (_theResult____h437478[14] ? + (_theResult____h437479[14] ? 6'd42 : - (_theResult____h437478[13] ? + (_theResult____h437479[13] ? 6'd43 : - (_theResult____h437478[12] ? + (_theResult____h437479[12] ? 6'd44 : - (_theResult____h437478[11] ? + (_theResult____h437479[11] ? 6'd45 : - (_theResult____h437478[10] ? + (_theResult____h437479[10] ? 6'd46 : - (_theResult____h437478[9] ? + (_theResult____h437479[9] ? 6'd47 : - (_theResult____h437478[8] ? + (_theResult____h437479[8] ? 6'd48 : - (_theResult____h437478[7] ? + (_theResult____h437479[7] ? 6'd49 : - (_theResult____h437478[6] ? + (_theResult____h437479[6] ? 6'd50 : - (_theResult____h437478[5] ? + (_theResult____h437479[5] ? 6'd51 : - (_theResult____h437478[4] ? + (_theResult____h437479[4] ? 6'd52 : - (_theResult____h437478[3] ? + (_theResult____h437479[3] ? 6'd53 : - (_theResult____h437478[2] ? + (_theResult____h437479[2] ? 6'd54 : - (_theResult____h437478[1] ? + (_theResult____h437479[1] ? 6'd55 : - (_theResult____h437478[0] ? + (_theResult____h437479[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 = - (_theResult____h541721[56] ? + (_theResult____h541722[56] ? 6'd0 : - (_theResult____h541721[55] ? + (_theResult____h541722[55] ? 6'd1 : - (_theResult____h541721[54] ? + (_theResult____h541722[54] ? 6'd2 : - (_theResult____h541721[53] ? + (_theResult____h541722[53] ? 6'd3 : - (_theResult____h541721[52] ? + (_theResult____h541722[52] ? 6'd4 : - (_theResult____h541721[51] ? + (_theResult____h541722[51] ? 6'd5 : - (_theResult____h541721[50] ? + (_theResult____h541722[50] ? 6'd6 : - (_theResult____h541721[49] ? + (_theResult____h541722[49] ? 6'd7 : - (_theResult____h541721[48] ? + (_theResult____h541722[48] ? 6'd8 : - (_theResult____h541721[47] ? + (_theResult____h541722[47] ? 6'd9 : - (_theResult____h541721[46] ? + (_theResult____h541722[46] ? 6'd10 : - (_theResult____h541721[45] ? + (_theResult____h541722[45] ? 6'd11 : - (_theResult____h541721[44] ? + (_theResult____h541722[44] ? 6'd12 : - (_theResult____h541721[43] ? + (_theResult____h541722[43] ? 6'd13 : - (_theResult____h541721[42] ? + (_theResult____h541722[42] ? 6'd14 : - (_theResult____h541721[41] ? + (_theResult____h541722[41] ? 6'd15 : - (_theResult____h541721[40] ? + (_theResult____h541722[40] ? 6'd16 : - (_theResult____h541721[39] ? + (_theResult____h541722[39] ? 6'd17 : - (_theResult____h541721[38] ? + (_theResult____h541722[38] ? 6'd18 : - (_theResult____h541721[37] ? + (_theResult____h541722[37] ? 6'd19 : - (_theResult____h541721[36] ? + (_theResult____h541722[36] ? 6'd20 : - (_theResult____h541721[35] ? + (_theResult____h541722[35] ? 6'd21 : - (_theResult____h541721[34] ? + (_theResult____h541722[34] ? 6'd22 : - (_theResult____h541721[33] ? + (_theResult____h541722[33] ? 6'd23 : - (_theResult____h541721[32] ? + (_theResult____h541722[32] ? 6'd24 : - (_theResult____h541721[31] ? + (_theResult____h541722[31] ? 6'd25 : - (_theResult____h541721[30] ? + (_theResult____h541722[30] ? 6'd26 : - (_theResult____h541721[29] ? + (_theResult____h541722[29] ? 6'd27 : - (_theResult____h541721[28] ? + (_theResult____h541722[28] ? 6'd28 : - (_theResult____h541721[27] ? + (_theResult____h541722[27] ? 6'd29 : - (_theResult____h541721[26] ? + (_theResult____h541722[26] ? 6'd30 : - (_theResult____h541721[25] ? + (_theResult____h541722[25] ? 6'd31 : - (_theResult____h541721[24] ? + (_theResult____h541722[24] ? 6'd32 : - (_theResult____h541721[23] ? + (_theResult____h541722[23] ? 6'd33 : - (_theResult____h541721[22] ? + (_theResult____h541722[22] ? 6'd34 : - (_theResult____h541721[21] ? + (_theResult____h541722[21] ? 6'd35 : - (_theResult____h541721[20] ? + (_theResult____h541722[20] ? 6'd36 : - (_theResult____h541721[19] ? + (_theResult____h541722[19] ? 6'd37 : - (_theResult____h541721[18] ? + (_theResult____h541722[18] ? 6'd38 : - (_theResult____h541721[17] ? + (_theResult____h541722[17] ? 6'd39 : - (_theResult____h541721[16] ? + (_theResult____h541722[16] ? 6'd40 : - (_theResult____h541721[15] ? + (_theResult____h541722[15] ? 6'd41 : - (_theResult____h541721[14] ? + (_theResult____h541722[14] ? 6'd42 : - (_theResult____h541721[13] ? + (_theResult____h541722[13] ? 6'd43 : - (_theResult____h541721[12] ? + (_theResult____h541722[12] ? 6'd44 : - (_theResult____h541721[11] ? + (_theResult____h541722[11] ? 6'd45 : - (_theResult____h541721[10] ? + (_theResult____h541722[10] ? 6'd46 : - (_theResult____h541721[9] ? + (_theResult____h541722[9] ? 6'd47 : - (_theResult____h541721[8] ? + (_theResult____h541722[8] ? 6'd48 : - (_theResult____h541721[7] ? + (_theResult____h541722[7] ? 6'd49 : - (_theResult____h541721[6] ? + (_theResult____h541722[6] ? 6'd50 : - (_theResult____h541721[5] ? + (_theResult____h541722[5] ? 6'd51 : - (_theResult____h541721[4] ? + (_theResult____h541722[4] ? 6'd52 : - (_theResult____h541721[3] ? + (_theResult____h541722[3] ? 6'd53 : - (_theResult____h541721[2] ? + (_theResult____h541722[2] ? 6'd54 : - (_theResult____h541721[1] ? + (_theResult____h541722[1] ? 6'd55 : - (_theResult____h541721[0] ? + (_theResult____h541722[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 = - (_theResult____h502868[56] ? + (_theResult____h502869[56] ? 6'd0 : - (_theResult____h502868[55] ? + (_theResult____h502869[55] ? 6'd1 : - (_theResult____h502868[54] ? + (_theResult____h502869[54] ? 6'd2 : - (_theResult____h502868[53] ? + (_theResult____h502869[53] ? 6'd3 : - (_theResult____h502868[52] ? + (_theResult____h502869[52] ? 6'd4 : - (_theResult____h502868[51] ? + (_theResult____h502869[51] ? 6'd5 : - (_theResult____h502868[50] ? + (_theResult____h502869[50] ? 6'd6 : - (_theResult____h502868[49] ? + (_theResult____h502869[49] ? 6'd7 : - (_theResult____h502868[48] ? + (_theResult____h502869[48] ? 6'd8 : - (_theResult____h502868[47] ? + (_theResult____h502869[47] ? 6'd9 : - (_theResult____h502868[46] ? + (_theResult____h502869[46] ? 6'd10 : - (_theResult____h502868[45] ? + (_theResult____h502869[45] ? 6'd11 : - (_theResult____h502868[44] ? + (_theResult____h502869[44] ? 6'd12 : - (_theResult____h502868[43] ? + (_theResult____h502869[43] ? 6'd13 : - (_theResult____h502868[42] ? + (_theResult____h502869[42] ? 6'd14 : - (_theResult____h502868[41] ? + (_theResult____h502869[41] ? 6'd15 : - (_theResult____h502868[40] ? + (_theResult____h502869[40] ? 6'd16 : - (_theResult____h502868[39] ? + (_theResult____h502869[39] ? 6'd17 : - (_theResult____h502868[38] ? + (_theResult____h502869[38] ? 6'd18 : - (_theResult____h502868[37] ? + (_theResult____h502869[37] ? 6'd19 : - (_theResult____h502868[36] ? + (_theResult____h502869[36] ? 6'd20 : - (_theResult____h502868[35] ? + (_theResult____h502869[35] ? 6'd21 : - (_theResult____h502868[34] ? + (_theResult____h502869[34] ? 6'd22 : - (_theResult____h502868[33] ? + (_theResult____h502869[33] ? 6'd23 : - (_theResult____h502868[32] ? + (_theResult____h502869[32] ? 6'd24 : - (_theResult____h502868[31] ? + (_theResult____h502869[31] ? 6'd25 : - (_theResult____h502868[30] ? + (_theResult____h502869[30] ? 6'd26 : - (_theResult____h502868[29] ? + (_theResult____h502869[29] ? 6'd27 : - (_theResult____h502868[28] ? + (_theResult____h502869[28] ? 6'd28 : - (_theResult____h502868[27] ? + (_theResult____h502869[27] ? 6'd29 : - (_theResult____h502868[26] ? + (_theResult____h502869[26] ? 6'd30 : - (_theResult____h502868[25] ? + (_theResult____h502869[25] ? 6'd31 : - (_theResult____h502868[24] ? + (_theResult____h502869[24] ? 6'd32 : - (_theResult____h502868[23] ? + (_theResult____h502869[23] ? 6'd33 : - (_theResult____h502868[22] ? + (_theResult____h502869[22] ? 6'd34 : - (_theResult____h502868[21] ? + (_theResult____h502869[21] ? 6'd35 : - (_theResult____h502868[20] ? + (_theResult____h502869[20] ? 6'd36 : - (_theResult____h502868[19] ? + (_theResult____h502869[19] ? 6'd37 : - (_theResult____h502868[18] ? + (_theResult____h502869[18] ? 6'd38 : - (_theResult____h502868[17] ? + (_theResult____h502869[17] ? 6'd39 : - (_theResult____h502868[16] ? + (_theResult____h502869[16] ? 6'd40 : - (_theResult____h502868[15] ? + (_theResult____h502869[15] ? 6'd41 : - (_theResult____h502868[14] ? + (_theResult____h502869[14] ? 6'd42 : - (_theResult____h502868[13] ? + (_theResult____h502869[13] ? 6'd43 : - (_theResult____h502868[12] ? + (_theResult____h502869[12] ? 6'd44 : - (_theResult____h502868[11] ? + (_theResult____h502869[11] ? 6'd45 : - (_theResult____h502868[10] ? + (_theResult____h502869[10] ? 6'd46 : - (_theResult____h502868[9] ? + (_theResult____h502869[9] ? 6'd47 : - (_theResult____h502868[8] ? + (_theResult____h502869[8] ? 6'd48 : - (_theResult____h502868[7] ? + (_theResult____h502869[7] ? 6'd49 : - (_theResult____h502868[6] ? + (_theResult____h502869[6] ? 6'd50 : - (_theResult____h502868[5] ? + (_theResult____h502869[5] ? 6'd51 : - (_theResult____h502868[4] ? + (_theResult____h502869[4] ? 6'd52 : - (_theResult____h502868[3] ? + (_theResult____h502869[3] ? 6'd53 : - (_theResult____h502868[2] ? + (_theResult____h502869[2] ? 6'd54 : - (_theResult____h502868[1] ? + (_theResult____h502869[1] ? 6'd55 : - (_theResult____h502868[0] ? + (_theResult____h502869[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 = - (_theResult____h581025[56] ? + (_theResult____h581026[56] ? 6'd0 : - (_theResult____h581025[55] ? + (_theResult____h581026[55] ? 6'd1 : - (_theResult____h581025[54] ? + (_theResult____h581026[54] ? 6'd2 : - (_theResult____h581025[53] ? + (_theResult____h581026[53] ? 6'd3 : - (_theResult____h581025[52] ? + (_theResult____h581026[52] ? 6'd4 : - (_theResult____h581025[51] ? + (_theResult____h581026[51] ? 6'd5 : - (_theResult____h581025[50] ? + (_theResult____h581026[50] ? 6'd6 : - (_theResult____h581025[49] ? + (_theResult____h581026[49] ? 6'd7 : - (_theResult____h581025[48] ? + (_theResult____h581026[48] ? 6'd8 : - (_theResult____h581025[47] ? + (_theResult____h581026[47] ? 6'd9 : - (_theResult____h581025[46] ? + (_theResult____h581026[46] ? 6'd10 : - (_theResult____h581025[45] ? + (_theResult____h581026[45] ? 6'd11 : - (_theResult____h581025[44] ? + (_theResult____h581026[44] ? 6'd12 : - (_theResult____h581025[43] ? + (_theResult____h581026[43] ? 6'd13 : - (_theResult____h581025[42] ? + (_theResult____h581026[42] ? 6'd14 : - (_theResult____h581025[41] ? + (_theResult____h581026[41] ? 6'd15 : - (_theResult____h581025[40] ? + (_theResult____h581026[40] ? 6'd16 : - (_theResult____h581025[39] ? + (_theResult____h581026[39] ? 6'd17 : - (_theResult____h581025[38] ? + (_theResult____h581026[38] ? 6'd18 : - (_theResult____h581025[37] ? + (_theResult____h581026[37] ? 6'd19 : - (_theResult____h581025[36] ? + (_theResult____h581026[36] ? 6'd20 : - (_theResult____h581025[35] ? + (_theResult____h581026[35] ? 6'd21 : - (_theResult____h581025[34] ? + (_theResult____h581026[34] ? 6'd22 : - (_theResult____h581025[33] ? + (_theResult____h581026[33] ? 6'd23 : - (_theResult____h581025[32] ? + (_theResult____h581026[32] ? 6'd24 : - (_theResult____h581025[31] ? + (_theResult____h581026[31] ? 6'd25 : - (_theResult____h581025[30] ? + (_theResult____h581026[30] ? 6'd26 : - (_theResult____h581025[29] ? + (_theResult____h581026[29] ? 6'd27 : - (_theResult____h581025[28] ? + (_theResult____h581026[28] ? 6'd28 : - (_theResult____h581025[27] ? + (_theResult____h581026[27] ? 6'd29 : - (_theResult____h581025[26] ? + (_theResult____h581026[26] ? 6'd30 : - (_theResult____h581025[25] ? + (_theResult____h581026[25] ? 6'd31 : - (_theResult____h581025[24] ? + (_theResult____h581026[24] ? 6'd32 : - (_theResult____h581025[23] ? + (_theResult____h581026[23] ? 6'd33 : - (_theResult____h581025[22] ? + (_theResult____h581026[22] ? 6'd34 : - (_theResult____h581025[21] ? + (_theResult____h581026[21] ? 6'd35 : - (_theResult____h581025[20] ? + (_theResult____h581026[20] ? 6'd36 : - (_theResult____h581025[19] ? + (_theResult____h581026[19] ? 6'd37 : - (_theResult____h581025[18] ? + (_theResult____h581026[18] ? 6'd38 : - (_theResult____h581025[17] ? + (_theResult____h581026[17] ? 6'd39 : - (_theResult____h581025[16] ? + (_theResult____h581026[16] ? 6'd40 : - (_theResult____h581025[15] ? + (_theResult____h581026[15] ? 6'd41 : - (_theResult____h581025[14] ? + (_theResult____h581026[14] ? 6'd42 : - (_theResult____h581025[13] ? + (_theResult____h581026[13] ? 6'd43 : - (_theResult____h581025[12] ? + (_theResult____h581026[12] ? 6'd44 : - (_theResult____h581025[11] ? + (_theResult____h581026[11] ? 6'd45 : - (_theResult____h581025[10] ? + (_theResult____h581026[10] ? 6'd46 : - (_theResult____h581025[9] ? + (_theResult____h581026[9] ? 6'd47 : - (_theResult____h581025[8] ? + (_theResult____h581026[8] ? 6'd48 : - (_theResult____h581025[7] ? + (_theResult____h581026[7] ? 6'd49 : - (_theResult____h581025[6] ? + (_theResult____h581026[6] ? 6'd50 : - (_theResult____h581025[5] ? + (_theResult____h581026[5] ? 6'd51 : - (_theResult____h581025[4] ? + (_theResult____h581026[4] ? 6'd52 : - (_theResult____h581025[3] ? + (_theResult____h581026[3] ? 6'd53 : - (_theResult____h581025[2] ? + (_theResult____h581026[2] ? 6'd54 : - (_theResult____h581025[1] ? + (_theResult____h581026[1] ? 6'd55 : - (_theResult____h581025[0] ? + (_theResult____h581026[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 = - (_theResult____h363723[56] ? + (_theResult____h363724[56] ? 6'd0 : - (_theResult____h363723[55] ? + (_theResult____h363724[55] ? 6'd1 : - (_theResult____h363723[54] ? + (_theResult____h363724[54] ? 6'd2 : - (_theResult____h363723[53] ? + (_theResult____h363724[53] ? 6'd3 : - (_theResult____h363723[52] ? + (_theResult____h363724[52] ? 6'd4 : - (_theResult____h363723[51] ? + (_theResult____h363724[51] ? 6'd5 : - (_theResult____h363723[50] ? + (_theResult____h363724[50] ? 6'd6 : - (_theResult____h363723[49] ? + (_theResult____h363724[49] ? 6'd7 : - (_theResult____h363723[48] ? + (_theResult____h363724[48] ? 6'd8 : - (_theResult____h363723[47] ? + (_theResult____h363724[47] ? 6'd9 : - (_theResult____h363723[46] ? + (_theResult____h363724[46] ? 6'd10 : - (_theResult____h363723[45] ? + (_theResult____h363724[45] ? 6'd11 : - (_theResult____h363723[44] ? + (_theResult____h363724[44] ? 6'd12 : - (_theResult____h363723[43] ? + (_theResult____h363724[43] ? 6'd13 : - (_theResult____h363723[42] ? + (_theResult____h363724[42] ? 6'd14 : - (_theResult____h363723[41] ? + (_theResult____h363724[41] ? 6'd15 : - (_theResult____h363723[40] ? + (_theResult____h363724[40] ? 6'd16 : - (_theResult____h363723[39] ? + (_theResult____h363724[39] ? 6'd17 : - (_theResult____h363723[38] ? + (_theResult____h363724[38] ? 6'd18 : - (_theResult____h363723[37] ? + (_theResult____h363724[37] ? 6'd19 : - (_theResult____h363723[36] ? + (_theResult____h363724[36] ? 6'd20 : - (_theResult____h363723[35] ? + (_theResult____h363724[35] ? 6'd21 : - (_theResult____h363723[34] ? + (_theResult____h363724[34] ? 6'd22 : - (_theResult____h363723[33] ? + (_theResult____h363724[33] ? 6'd23 : - (_theResult____h363723[32] ? + (_theResult____h363724[32] ? 6'd24 : - (_theResult____h363723[31] ? + (_theResult____h363724[31] ? 6'd25 : - (_theResult____h363723[30] ? + (_theResult____h363724[30] ? 6'd26 : - (_theResult____h363723[29] ? + (_theResult____h363724[29] ? 6'd27 : - (_theResult____h363723[28] ? + (_theResult____h363724[28] ? 6'd28 : - (_theResult____h363723[27] ? + (_theResult____h363724[27] ? 6'd29 : - (_theResult____h363723[26] ? + (_theResult____h363724[26] ? 6'd30 : - (_theResult____h363723[25] ? + (_theResult____h363724[25] ? 6'd31 : - (_theResult____h363723[24] ? + (_theResult____h363724[24] ? 6'd32 : - (_theResult____h363723[23] ? + (_theResult____h363724[23] ? 6'd33 : - (_theResult____h363723[22] ? + (_theResult____h363724[22] ? 6'd34 : - (_theResult____h363723[21] ? + (_theResult____h363724[21] ? 6'd35 : - (_theResult____h363723[20] ? + (_theResult____h363724[20] ? 6'd36 : - (_theResult____h363723[19] ? + (_theResult____h363724[19] ? 6'd37 : - (_theResult____h363723[18] ? + (_theResult____h363724[18] ? 6'd38 : - (_theResult____h363723[17] ? + (_theResult____h363724[17] ? 6'd39 : - (_theResult____h363723[16] ? + (_theResult____h363724[16] ? 6'd40 : - (_theResult____h363723[15] ? + (_theResult____h363724[15] ? 6'd41 : - (_theResult____h363723[14] ? + (_theResult____h363724[14] ? 6'd42 : - (_theResult____h363723[13] ? + (_theResult____h363724[13] ? 6'd43 : - (_theResult____h363723[12] ? + (_theResult____h363724[12] ? 6'd44 : - (_theResult____h363723[11] ? + (_theResult____h363724[11] ? 6'd45 : - (_theResult____h363723[10] ? + (_theResult____h363724[10] ? 6'd46 : - (_theResult____h363723[9] ? + (_theResult____h363724[9] ? 6'd47 : - (_theResult____h363723[8] ? + (_theResult____h363724[8] ? 6'd48 : - (_theResult____h363723[7] ? + (_theResult____h363724[7] ? 6'd49 : - (_theResult____h363723[6] ? + (_theResult____h363724[6] ? 6'd50 : - (_theResult____h363723[5] ? + (_theResult____h363724[5] ? 6'd51 : - (_theResult____h363723[4] ? + (_theResult____h363724[4] ? 6'd52 : - (_theResult____h363723[3] ? + (_theResult____h363724[3] ? 6'd53 : - (_theResult____h363723[2] ? + (_theResult____h363724[2] ? 6'd54 : - (_theResult____h363723[1] ? + (_theResult____h363724[1] ? 6'd55 : - (_theResult____h363723[0] ? + (_theResult____h363724[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 = - (_theResult____h409420[56] ? + (_theResult____h409421[56] ? 6'd0 : - (_theResult____h409420[55] ? + (_theResult____h409421[55] ? 6'd1 : - (_theResult____h409420[54] ? + (_theResult____h409421[54] ? 6'd2 : - (_theResult____h409420[53] ? + (_theResult____h409421[53] ? 6'd3 : - (_theResult____h409420[52] ? + (_theResult____h409421[52] ? 6'd4 : - (_theResult____h409420[51] ? + (_theResult____h409421[51] ? 6'd5 : - (_theResult____h409420[50] ? + (_theResult____h409421[50] ? 6'd6 : - (_theResult____h409420[49] ? + (_theResult____h409421[49] ? 6'd7 : - (_theResult____h409420[48] ? + (_theResult____h409421[48] ? 6'd8 : - (_theResult____h409420[47] ? + (_theResult____h409421[47] ? 6'd9 : - (_theResult____h409420[46] ? + (_theResult____h409421[46] ? 6'd10 : - (_theResult____h409420[45] ? + (_theResult____h409421[45] ? 6'd11 : - (_theResult____h409420[44] ? + (_theResult____h409421[44] ? 6'd12 : - (_theResult____h409420[43] ? + (_theResult____h409421[43] ? 6'd13 : - (_theResult____h409420[42] ? + (_theResult____h409421[42] ? 6'd14 : - (_theResult____h409420[41] ? + (_theResult____h409421[41] ? 6'd15 : - (_theResult____h409420[40] ? + (_theResult____h409421[40] ? 6'd16 : - (_theResult____h409420[39] ? + (_theResult____h409421[39] ? 6'd17 : - (_theResult____h409420[38] ? + (_theResult____h409421[38] ? 6'd18 : - (_theResult____h409420[37] ? + (_theResult____h409421[37] ? 6'd19 : - (_theResult____h409420[36] ? + (_theResult____h409421[36] ? 6'd20 : - (_theResult____h409420[35] ? + (_theResult____h409421[35] ? 6'd21 : - (_theResult____h409420[34] ? + (_theResult____h409421[34] ? 6'd22 : - (_theResult____h409420[33] ? + (_theResult____h409421[33] ? 6'd23 : - (_theResult____h409420[32] ? + (_theResult____h409421[32] ? 6'd24 : - (_theResult____h409420[31] ? + (_theResult____h409421[31] ? 6'd25 : - (_theResult____h409420[30] ? + (_theResult____h409421[30] ? 6'd26 : - (_theResult____h409420[29] ? + (_theResult____h409421[29] ? 6'd27 : - (_theResult____h409420[28] ? + (_theResult____h409421[28] ? 6'd28 : - (_theResult____h409420[27] ? + (_theResult____h409421[27] ? 6'd29 : - (_theResult____h409420[26] ? + (_theResult____h409421[26] ? 6'd30 : - (_theResult____h409420[25] ? + (_theResult____h409421[25] ? 6'd31 : - (_theResult____h409420[24] ? + (_theResult____h409421[24] ? 6'd32 : - (_theResult____h409420[23] ? + (_theResult____h409421[23] ? 6'd33 : - (_theResult____h409420[22] ? + (_theResult____h409421[22] ? 6'd34 : - (_theResult____h409420[21] ? + (_theResult____h409421[21] ? 6'd35 : - (_theResult____h409420[20] ? + (_theResult____h409421[20] ? 6'd36 : - (_theResult____h409420[19] ? + (_theResult____h409421[19] ? 6'd37 : - (_theResult____h409420[18] ? + (_theResult____h409421[18] ? 6'd38 : - (_theResult____h409420[17] ? + (_theResult____h409421[17] ? 6'd39 : - (_theResult____h409420[16] ? + (_theResult____h409421[16] ? 6'd40 : - (_theResult____h409420[15] ? + (_theResult____h409421[15] ? 6'd41 : - (_theResult____h409420[14] ? + (_theResult____h409421[14] ? 6'd42 : - (_theResult____h409420[13] ? + (_theResult____h409421[13] ? 6'd43 : - (_theResult____h409420[12] ? + (_theResult____h409421[12] ? 6'd44 : - (_theResult____h409420[11] ? + (_theResult____h409421[11] ? 6'd45 : - (_theResult____h409420[10] ? + (_theResult____h409421[10] ? 6'd46 : - (_theResult____h409420[9] ? + (_theResult____h409421[9] ? 6'd47 : - (_theResult____h409420[8] ? + (_theResult____h409421[8] ? 6'd48 : - (_theResult____h409420[7] ? + (_theResult____h409421[7] ? 6'd49 : - (_theResult____h409420[6] ? + (_theResult____h409421[6] ? 6'd50 : - (_theResult____h409420[5] ? + (_theResult____h409421[5] ? 6'd51 : - (_theResult____h409420[4] ? + (_theResult____h409421[4] ? 6'd52 : - (_theResult____h409420[3] ? + (_theResult____h409421[3] ? 6'd53 : - (_theResult____h409420[2] ? + (_theResult____h409421[2] ? 6'd54 : - (_theResult____h409420[1] ? + (_theResult____h409421[1] ? 6'd55 : - (_theResult____h409420[0] ? + (_theResult____h409421[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 = - (_theResult____h455115[56] ? + (_theResult____h455116[56] ? 6'd0 : - (_theResult____h455115[55] ? + (_theResult____h455116[55] ? 6'd1 : - (_theResult____h455115[54] ? + (_theResult____h455116[54] ? 6'd2 : - (_theResult____h455115[53] ? + (_theResult____h455116[53] ? 6'd3 : - (_theResult____h455115[52] ? + (_theResult____h455116[52] ? 6'd4 : - (_theResult____h455115[51] ? + (_theResult____h455116[51] ? 6'd5 : - (_theResult____h455115[50] ? + (_theResult____h455116[50] ? 6'd6 : - (_theResult____h455115[49] ? + (_theResult____h455116[49] ? 6'd7 : - (_theResult____h455115[48] ? + (_theResult____h455116[48] ? 6'd8 : - (_theResult____h455115[47] ? + (_theResult____h455116[47] ? 6'd9 : - (_theResult____h455115[46] ? + (_theResult____h455116[46] ? 6'd10 : - (_theResult____h455115[45] ? + (_theResult____h455116[45] ? 6'd11 : - (_theResult____h455115[44] ? + (_theResult____h455116[44] ? 6'd12 : - (_theResult____h455115[43] ? + (_theResult____h455116[43] ? 6'd13 : - (_theResult____h455115[42] ? + (_theResult____h455116[42] ? 6'd14 : - (_theResult____h455115[41] ? + (_theResult____h455116[41] ? 6'd15 : - (_theResult____h455115[40] ? + (_theResult____h455116[40] ? 6'd16 : - (_theResult____h455115[39] ? + (_theResult____h455116[39] ? 6'd17 : - (_theResult____h455115[38] ? + (_theResult____h455116[38] ? 6'd18 : - (_theResult____h455115[37] ? + (_theResult____h455116[37] ? 6'd19 : - (_theResult____h455115[36] ? + (_theResult____h455116[36] ? 6'd20 : - (_theResult____h455115[35] ? + (_theResult____h455116[35] ? 6'd21 : - (_theResult____h455115[34] ? + (_theResult____h455116[34] ? 6'd22 : - (_theResult____h455115[33] ? + (_theResult____h455116[33] ? 6'd23 : - (_theResult____h455115[32] ? + (_theResult____h455116[32] ? 6'd24 : - (_theResult____h455115[31] ? + (_theResult____h455116[31] ? 6'd25 : - (_theResult____h455115[30] ? + (_theResult____h455116[30] ? 6'd26 : - (_theResult____h455115[29] ? + (_theResult____h455116[29] ? 6'd27 : - (_theResult____h455115[28] ? + (_theResult____h455116[28] ? 6'd28 : - (_theResult____h455115[27] ? + (_theResult____h455116[27] ? 6'd29 : - (_theResult____h455115[26] ? + (_theResult____h455116[26] ? 6'd30 : - (_theResult____h455115[25] ? + (_theResult____h455116[25] ? 6'd31 : - (_theResult____h455115[24] ? + (_theResult____h455116[24] ? 6'd32 : - (_theResult____h455115[23] ? + (_theResult____h455116[23] ? 6'd33 : - (_theResult____h455115[22] ? + (_theResult____h455116[22] ? 6'd34 : - (_theResult____h455115[21] ? + (_theResult____h455116[21] ? 6'd35 : - (_theResult____h455115[20] ? + (_theResult____h455116[20] ? 6'd36 : - (_theResult____h455115[19] ? + (_theResult____h455116[19] ? 6'd37 : - (_theResult____h455115[18] ? + (_theResult____h455116[18] ? 6'd38 : - (_theResult____h455115[17] ? + (_theResult____h455116[17] ? 6'd39 : - (_theResult____h455115[16] ? + (_theResult____h455116[16] ? 6'd40 : - (_theResult____h455115[15] ? + (_theResult____h455116[15] ? 6'd41 : - (_theResult____h455115[14] ? + (_theResult____h455116[14] ? 6'd42 : - (_theResult____h455115[13] ? + (_theResult____h455116[13] ? 6'd43 : - (_theResult____h455115[12] ? + (_theResult____h455116[12] ? 6'd44 : - (_theResult____h455115[11] ? + (_theResult____h455116[11] ? 6'd45 : - (_theResult____h455115[10] ? + (_theResult____h455116[10] ? 6'd46 : - (_theResult____h455115[9] ? + (_theResult____h455116[9] ? 6'd47 : - (_theResult____h455115[8] ? + (_theResult____h455116[8] ? 6'd48 : - (_theResult____h455115[7] ? + (_theResult____h455116[7] ? 6'd49 : - (_theResult____h455115[6] ? + (_theResult____h455116[6] ? 6'd50 : - (_theResult____h455115[5] ? + (_theResult____h455116[5] ? 6'd51 : - (_theResult____h455115[4] ? + (_theResult____h455116[4] ? 6'd52 : - (_theResult____h455115[3] ? + (_theResult____h455116[3] ? 6'd53 : - (_theResult____h455115[2] ? + (_theResult____h455116[2] ? 6'd54 : - (_theResult____h455115[1] ? + (_theResult____h455116[1] ? 6'd55 : - (_theResult____h455115[0] ? + (_theResult____h455116[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 = - (_theResult___fst_exp__h549957 == 11'd2047) ? + (_theResult___fst_exp__h549958 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20889,10 +20908,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = - (_theResult___fst_exp__h549957 == 11'd2047) ? + (_theResult___fst_exp__h549958 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20900,10 +20919,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 = - (_theResult___fst_exp__h511104 == 11'd2047) ? + (_theResult___fst_exp__h511105 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20911,10 +20930,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 = - (_theResult___fst_exp__h589261 == 11'd2047) ? + (_theResult___fst_exp__h589262 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20922,10 +20941,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = - (_theResult___fst_exp__h589261 == 11'd2047) ? + (_theResult___fst_exp__h589262 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20933,538 +20952,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 = - (guard__h346094 == 2'b0 || + (guard__h346095 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h354195 : - _theResult___exp__h354711 ; + _theResult___fst_exp__h354196 : + _theResult___exp__h354712 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 = - (guard__h346094 == 2'b0) ? - _theResult___fst_exp__h354195 : + (guard__h346095 == 2'b0) ? + _theResult___fst_exp__h354196 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h354711 : - _theResult___fst_exp__h354195) ; + _theResult___exp__h354712 : + _theResult___fst_exp__h354196) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 = - (guard__h346094 == 2'b0 || + (guard__h346095 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h354189[56:34] : - _theResult___sfd__h354712 ; + sfdin__h354190[56:34] : + _theResult___sfd__h354713 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 = - (guard__h346094 == 2'b0) ? - sfdin__h354189[56:34] : + (guard__h346095 == 2'b0) ? + sfdin__h354190[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h354712 : - sfdin__h354189[56:34]) ; + _theResult___sfd__h354713 : + sfdin__h354190[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 = - (guard__h391793 == 2'b0 || + (guard__h391794 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h399892 : - _theResult___exp__h400408 ; + _theResult___fst_exp__h399893 : + _theResult___exp__h400409 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 = - (guard__h391793 == 2'b0) ? - _theResult___fst_exp__h399892 : + (guard__h391794 == 2'b0) ? + _theResult___fst_exp__h399893 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h400408 : - _theResult___fst_exp__h399892) ; + _theResult___exp__h400409 : + _theResult___fst_exp__h399893) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 = - (guard__h391793 == 2'b0 || + (guard__h391794 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h399886[56:34] : - _theResult___sfd__h400409 ; + sfdin__h399887[56:34] : + _theResult___sfd__h400410 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 = - (guard__h391793 == 2'b0) ? - sfdin__h399886[56:34] : + (guard__h391794 == 2'b0) ? + sfdin__h399887[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h400409 : - sfdin__h399886[56:34]) ; + _theResult___sfd__h400410 : + sfdin__h399887[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 = - (guard__h437488 == 2'b0 || + (guard__h437489 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h445587 : - _theResult___exp__h446103 ; + _theResult___fst_exp__h445588 : + _theResult___exp__h446104 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 = - (guard__h437488 == 2'b0) ? - _theResult___fst_exp__h445587 : + (guard__h437489 == 2'b0) ? + _theResult___fst_exp__h445588 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h446103 : - _theResult___fst_exp__h445587) ; + _theResult___exp__h446104 : + _theResult___fst_exp__h445588) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 = - (guard__h437488 == 2'b0 || + (guard__h437489 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h445581[56:34] : - _theResult___sfd__h446104 ; + sfdin__h445582[56:34] : + _theResult___sfd__h446105 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 = - (guard__h437488 == 2'b0) ? - sfdin__h445581[56:34] : + (guard__h437489 == 2'b0) ? + sfdin__h445582[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h446104 : - sfdin__h445581[56:34]) ; + _theResult___sfd__h446105 : + sfdin__h445582[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 = - (guard__h541731 == 2'b0 || + (guard__h541732 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h549957 : - _theResult___exp__h550686 ; + _theResult___fst_exp__h549958 : + _theResult___exp__h550687 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 = - (guard__h541731 == 2'b0) ? - _theResult___fst_exp__h549957 : + (guard__h541732 == 2'b0) ? + _theResult___fst_exp__h549958 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h550686 : - _theResult___fst_exp__h549957) ; + _theResult___exp__h550687 : + _theResult___fst_exp__h549958) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 = - (guard__h541731 == 2'b0 || + (guard__h541732 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h549951[56:5] : - _theResult___sfd__h550687 ; + sfdin__h549952[56:5] : + _theResult___sfd__h550688 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 = - (guard__h541731 == 2'b0) ? - sfdin__h549951[56:5] : + (guard__h541732 == 2'b0) ? + sfdin__h549952[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h550687 : - sfdin__h549951[56:5]) ; + _theResult___sfd__h550688 : + sfdin__h549952[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 = - (guard__h502878 == 2'b0 || + (guard__h502879 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h511104 : - _theResult___exp__h511833 ; + _theResult___fst_exp__h511105 : + _theResult___exp__h511834 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 = - (guard__h502878 == 2'b0) ? - _theResult___fst_exp__h511104 : + (guard__h502879 == 2'b0) ? + _theResult___fst_exp__h511105 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h511833 : - _theResult___fst_exp__h511104) ; + _theResult___exp__h511834 : + _theResult___fst_exp__h511105) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 = - (guard__h502878 == 2'b0 || + (guard__h502879 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h511098[56:5] : - _theResult___sfd__h511834 ; + sfdin__h511099[56:5] : + _theResult___sfd__h511835 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 = - (guard__h502878 == 2'b0) ? - sfdin__h511098[56:5] : + (guard__h502879 == 2'b0) ? + sfdin__h511099[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h511834 : - sfdin__h511098[56:5]) ; + _theResult___sfd__h511835 : + sfdin__h511099[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 = - (guard__h581035 == 2'b0 || + (guard__h581036 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h589261 : - _theResult___exp__h589990 ; + _theResult___fst_exp__h589262 : + _theResult___exp__h589991 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 = - (guard__h581035 == 2'b0) ? - _theResult___fst_exp__h589261 : + (guard__h581036 == 2'b0) ? + _theResult___fst_exp__h589262 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h589990 : - _theResult___fst_exp__h589261) ; + _theResult___exp__h589991 : + _theResult___fst_exp__h589262) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 = - (guard__h581035 == 2'b0 || + (guard__h581036 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h589255[56:5] : - _theResult___sfd__h589991 ; + sfdin__h589256[56:5] : + _theResult___sfd__h589992 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 = - (guard__h581035 == 2'b0) ? - sfdin__h589255[56:5] : + (guard__h581036 == 2'b0) ? + sfdin__h589256[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h589991 : - sfdin__h589255[56:5]) ; + _theResult___sfd__h589992 : + sfdin__h589256[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 = - (guard__h363733 == 2'b0 || + (guard__h363734 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h371961 : - _theResult___exp__h372477 ; + _theResult___fst_exp__h371962 : + _theResult___exp__h372478 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 = - (guard__h363733 == 2'b0) ? - _theResult___fst_exp__h371961 : + (guard__h363734 == 2'b0) ? + _theResult___fst_exp__h371962 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h372477 : - _theResult___fst_exp__h371961) ; + _theResult___exp__h372478 : + _theResult___fst_exp__h371962) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 = - (guard__h363733 == 2'b0 || + (guard__h363734 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h371955[56:34] : - _theResult___sfd__h372478 ; + sfdin__h371956[56:34] : + _theResult___sfd__h372479 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 = - (guard__h363733 == 2'b0) ? - sfdin__h371955[56:34] : + (guard__h363734 == 2'b0) ? + sfdin__h371956[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h372478 : - sfdin__h371955[56:34]) ; + _theResult___sfd__h372479 : + sfdin__h371956[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 = - (guard__h409430 == 2'b0 || + (guard__h409431 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h417658 : - _theResult___exp__h418174 ; + _theResult___fst_exp__h417659 : + _theResult___exp__h418175 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 = - (guard__h409430 == 2'b0) ? - _theResult___fst_exp__h417658 : + (guard__h409431 == 2'b0) ? + _theResult___fst_exp__h417659 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h418174 : - _theResult___fst_exp__h417658) ; + _theResult___exp__h418175 : + _theResult___fst_exp__h417659) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 = - (guard__h409430 == 2'b0 || + (guard__h409431 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h417652[56:34] : - _theResult___sfd__h418175 ; + sfdin__h417653[56:34] : + _theResult___sfd__h418176 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 = - (guard__h409430 == 2'b0) ? - sfdin__h417652[56:34] : + (guard__h409431 == 2'b0) ? + sfdin__h417653[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h418175 : - sfdin__h417652[56:34]) ; + _theResult___sfd__h418176 : + sfdin__h417653[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 = - (guard__h455125 == 2'b0 || + (guard__h455126 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h463353 : - _theResult___exp__h463869 ; + _theResult___fst_exp__h463354 : + _theResult___exp__h463870 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 = - (guard__h455125 == 2'b0) ? - _theResult___fst_exp__h463353 : + (guard__h455126 == 2'b0) ? + _theResult___fst_exp__h463354 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h463869 : - _theResult___fst_exp__h463353) ; + _theResult___exp__h463870 : + _theResult___fst_exp__h463354) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 = - (guard__h455125 == 2'b0 || + (guard__h455126 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h463347[56:34] : - _theResult___sfd__h463870 ; + sfdin__h463348[56:34] : + _theResult___sfd__h463871 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 = - (guard__h455125 == 2'b0) ? - sfdin__h463347[56:34] : + (guard__h455126 == 2'b0) ? + sfdin__h463348[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h463870 : - sfdin__h463347[56:34]) ; + _theResult___sfd__h463871 : + sfdin__h463348[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 = - (guard__h532419 == 2'b0 || + (guard__h532420 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h540380 : - _theResult___exp__h541035 ; + _theResult___fst_exp__h540381 : + _theResult___exp__h541036 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 = - (guard__h532419 == 2'b0) ? - _theResult___fst_exp__h540380 : + (guard__h532420 == 2'b0) ? + _theResult___fst_exp__h540381 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h541035 : - _theResult___fst_exp__h540380) ; + _theResult___exp__h541036 : + _theResult___fst_exp__h540381) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 = - (guard__h550800 == 2'b0 || + (guard__h550801 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h558790 : - _theResult___exp__h559470 ; + _theResult___fst_exp__h558791 : + _theResult___exp__h559471 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 = - (guard__h550800 == 2'b0) ? - _theResult___fst_exp__h558790 : + (guard__h550801 == 2'b0) ? + _theResult___fst_exp__h558791 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h559470 : - _theResult___fst_exp__h558790) ; + _theResult___exp__h559471 : + _theResult___fst_exp__h558791) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 = - (guard__h532419 == 2'b0 || + (guard__h532420 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h540331[56:5] : - _theResult___sfd__h541036 ; + _theResult___snd__h540332[56:5] : + _theResult___sfd__h541037 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 = - (guard__h532419 == 2'b0) ? - _theResult___snd__h540331[56:5] : + (guard__h532420 == 2'b0) ? + _theResult___snd__h540332[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h541036 : - _theResult___snd__h540331[56:5]) ; + _theResult___sfd__h541037 : + _theResult___snd__h540332[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 = - (guard__h550800 == 2'b0 || + (guard__h550801 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h558736[56:5] : - _theResult___sfd__h559471 ; + _theResult___snd__h558737[56:5] : + _theResult___sfd__h559472 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 = - (guard__h550800 == 2'b0) ? - _theResult___snd__h558736[56:5] : + (guard__h550801 == 2'b0) ? + _theResult___snd__h558737[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h559471 : - _theResult___snd__h558736[56:5]) ; + _theResult___sfd__h559472 : + _theResult___snd__h558737[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 = - (guard__h493566 == 2'b0 || + (guard__h493567 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h501527 : - _theResult___exp__h502182 ; + _theResult___fst_exp__h501528 : + _theResult___exp__h502183 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 = - (guard__h493566 == 2'b0) ? - _theResult___fst_exp__h501527 : + (guard__h493567 == 2'b0) ? + _theResult___fst_exp__h501528 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h502182 : - _theResult___fst_exp__h501527) ; + _theResult___exp__h502183 : + _theResult___fst_exp__h501528) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 = - (guard__h511947 == 2'b0 || + (guard__h511948 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h519937 : - _theResult___exp__h520617 ; + _theResult___fst_exp__h519938 : + _theResult___exp__h520618 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 = - (guard__h511947 == 2'b0) ? - _theResult___fst_exp__h519937 : + (guard__h511948 == 2'b0) ? + _theResult___fst_exp__h519938 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h520617 : - _theResult___fst_exp__h519937) ; + _theResult___exp__h520618 : + _theResult___fst_exp__h519938) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 = - (guard__h493566 == 2'b0 || + (guard__h493567 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h501478[56:5] : - _theResult___sfd__h502183 ; + _theResult___snd__h501479[56:5] : + _theResult___sfd__h502184 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 = - (guard__h493566 == 2'b0) ? - _theResult___snd__h501478[56:5] : + (guard__h493567 == 2'b0) ? + _theResult___snd__h501479[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h502183 : - _theResult___snd__h501478[56:5]) ; + _theResult___sfd__h502184 : + _theResult___snd__h501479[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 = - (guard__h511947 == 2'b0 || + (guard__h511948 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h519883[56:5] : - _theResult___sfd__h520618 ; + _theResult___snd__h519884[56:5] : + _theResult___sfd__h520619 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 = - (guard__h511947 == 2'b0) ? - _theResult___snd__h519883[56:5] : + (guard__h511948 == 2'b0) ? + _theResult___snd__h519884[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h520618 : - _theResult___snd__h519883[56:5]) ; + _theResult___sfd__h520619 : + _theResult___snd__h519884[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 = - (guard__h571723 == 2'b0 || + (guard__h571724 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h579684 : - _theResult___exp__h580339 ; + _theResult___fst_exp__h579685 : + _theResult___exp__h580340 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 = - (guard__h571723 == 2'b0) ? - _theResult___fst_exp__h579684 : + (guard__h571724 == 2'b0) ? + _theResult___fst_exp__h579685 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h580339 : - _theResult___fst_exp__h579684) ; + _theResult___exp__h580340 : + _theResult___fst_exp__h579685) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 = - (guard__h590104 == 2'b0 || + (guard__h590105 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h598094 : - _theResult___exp__h598774 ; + _theResult___fst_exp__h598095 : + _theResult___exp__h598775 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 = - (guard__h590104 == 2'b0) ? - _theResult___fst_exp__h598094 : + (guard__h590105 == 2'b0) ? + _theResult___fst_exp__h598095 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h598774 : - _theResult___fst_exp__h598094) ; + _theResult___exp__h598775 : + _theResult___fst_exp__h598095) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 = - (guard__h571723 == 2'b0 || + (guard__h571724 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h579635[56:5] : - _theResult___sfd__h580340 ; + _theResult___snd__h579636[56:5] : + _theResult___sfd__h580341 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 = - (guard__h571723 == 2'b0) ? - _theResult___snd__h579635[56:5] : + (guard__h571724 == 2'b0) ? + _theResult___snd__h579636[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h580340 : - _theResult___snd__h579635[56:5]) ; + _theResult___sfd__h580341 : + _theResult___snd__h579636[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 = - (guard__h590104 == 2'b0 || + (guard__h590105 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h598040[56:5] : - _theResult___sfd__h598775 ; + _theResult___snd__h598041[56:5] : + _theResult___sfd__h598776 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 = - (guard__h590104 == 2'b0) ? - _theResult___snd__h598040[56:5] : + (guard__h590105 == 2'b0) ? + _theResult___snd__h598041[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h598775 : - _theResult___snd__h598040[56:5]) ; + _theResult___sfd__h598776 : + _theResult___snd__h598041[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 = - (guard__h354803 == 2'b0 || + (guard__h354804 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h362851 : - _theResult___exp__h363293 ; + _theResult___fst_exp__h362852 : + _theResult___exp__h363294 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 = - (guard__h354803 == 2'b0) ? - _theResult___fst_exp__h362851 : + (guard__h354804 == 2'b0) ? + _theResult___fst_exp__h362852 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h363293 : - _theResult___fst_exp__h362851) ; + _theResult___exp__h363294 : + _theResult___fst_exp__h362852) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 = - (guard__h372569 == 2'b0 || + (guard__h372570 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h380646 : - _theResult___exp__h381113 ; + _theResult___fst_exp__h380647 : + _theResult___exp__h381114 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 = - (guard__h372569 == 2'b0) ? - _theResult___fst_exp__h380646 : + (guard__h372570 == 2'b0) ? + _theResult___fst_exp__h380647 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h381113 : - _theResult___fst_exp__h380646) ; + _theResult___exp__h381114 : + _theResult___fst_exp__h380647) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 = - (guard__h354803 == 2'b0 || + (guard__h354804 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h362802[56:34] : - _theResult___sfd__h363294 ; + _theResult___snd__h362803[56:34] : + _theResult___sfd__h363295 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 = - (guard__h354803 == 2'b0) ? - _theResult___snd__h362802[56:34] : + (guard__h354804 == 2'b0) ? + _theResult___snd__h362803[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h363294 : - _theResult___snd__h362802[56:34]) ; + _theResult___sfd__h363295 : + _theResult___snd__h362803[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h372569 == 2'b0 || + (guard__h372570 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h380592[56:34] : - _theResult___sfd__h381114 ; + _theResult___snd__h380593[56:34] : + _theResult___sfd__h381115 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h372569 == 2'b0) ? - _theResult___snd__h380592[56:34] : + (guard__h372570 == 2'b0) ? + _theResult___snd__h380593[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h381114 : - _theResult___snd__h380592[56:34]) ; + _theResult___sfd__h381115 : + _theResult___snd__h380593[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 = - (guard__h400500 == 2'b0 || + (guard__h400501 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h408548 : - _theResult___exp__h408990 ; + _theResult___fst_exp__h408549 : + _theResult___exp__h408991 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 = - (guard__h400500 == 2'b0) ? - _theResult___fst_exp__h408548 : + (guard__h400501 == 2'b0) ? + _theResult___fst_exp__h408549 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h408990 : - _theResult___fst_exp__h408548) ; + _theResult___exp__h408991 : + _theResult___fst_exp__h408549) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 = - (guard__h418266 == 2'b0 || + (guard__h418267 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h426343 : - _theResult___exp__h426810 ; + _theResult___fst_exp__h426344 : + _theResult___exp__h426811 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 = - (guard__h418266 == 2'b0) ? - _theResult___fst_exp__h426343 : + (guard__h418267 == 2'b0) ? + _theResult___fst_exp__h426344 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h426810 : - _theResult___fst_exp__h426343) ; + _theResult___exp__h426811 : + _theResult___fst_exp__h426344) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 = - (guard__h400500 == 2'b0 || + (guard__h400501 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h408499[56:34] : - _theResult___sfd__h408991 ; + _theResult___snd__h408500[56:34] : + _theResult___sfd__h408992 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 = - (guard__h400500 == 2'b0) ? - _theResult___snd__h408499[56:34] : + (guard__h400501 == 2'b0) ? + _theResult___snd__h408500[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h408991 : - _theResult___snd__h408499[56:34]) ; + _theResult___sfd__h408992 : + _theResult___snd__h408500[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h418266 == 2'b0 || + (guard__h418267 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h426289[56:34] : - _theResult___sfd__h426811 ; + _theResult___snd__h426290[56:34] : + _theResult___sfd__h426812 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h418266 == 2'b0) ? - _theResult___snd__h426289[56:34] : + (guard__h418267 == 2'b0) ? + _theResult___snd__h426290[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h426811 : - _theResult___snd__h426289[56:34]) ; + _theResult___sfd__h426812 : + _theResult___snd__h426290[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 = - (guard__h446195 == 2'b0 || + (guard__h446196 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h454243 : - _theResult___exp__h454685 ; + _theResult___fst_exp__h454244 : + _theResult___exp__h454686 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 = - (guard__h446195 == 2'b0) ? - _theResult___fst_exp__h454243 : + (guard__h446196 == 2'b0) ? + _theResult___fst_exp__h454244 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h454685 : - _theResult___fst_exp__h454243) ; + _theResult___exp__h454686 : + _theResult___fst_exp__h454244) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 = - (guard__h463961 == 2'b0 || + (guard__h463962 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h472038 : - _theResult___exp__h472505 ; + _theResult___fst_exp__h472039 : + _theResult___exp__h472506 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 = - (guard__h463961 == 2'b0) ? - _theResult___fst_exp__h472038 : + (guard__h463962 == 2'b0) ? + _theResult___fst_exp__h472039 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h472505 : - _theResult___fst_exp__h472038) ; + _theResult___exp__h472506 : + _theResult___fst_exp__h472039) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 = - (guard__h446195 == 2'b0 || + (guard__h446196 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h454194[56:34] : - _theResult___sfd__h454686 ; + _theResult___snd__h454195[56:34] : + _theResult___sfd__h454687 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 = - (guard__h446195 == 2'b0) ? - _theResult___snd__h454194[56:34] : + (guard__h446196 == 2'b0) ? + _theResult___snd__h454195[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h454686 : - _theResult___snd__h454194[56:34]) ; + _theResult___sfd__h454687 : + _theResult___snd__h454195[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h463961 == 2'b0 || + (guard__h463962 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h471984[56:34] : - _theResult___sfd__h472506 ; + _theResult___snd__h471985[56:34] : + _theResult___sfd__h472507 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h463961 == 2'b0) ? - _theResult___snd__h471984[56:34] : + (guard__h463962 == 2'b0) ? + _theResult___snd__h471985[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h472506 : - _theResult___snd__h471984[56:34]) ; + _theResult___sfd__h472507 : + _theResult___snd__h471985[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470 = - (_theResult___fst_exp__h558790 == 11'd2047) ? + (_theResult___fst_exp__h558791 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21472,10 +21491,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676 = - (_theResult___fst_exp__h540380 == 11'd2047) ? + (_theResult___fst_exp__h540381 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21483,10 +21502,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = - (_theResult___fst_exp__h558790 == 11'd2047) ? + (_theResult___fst_exp__h558791 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21494,10 +21513,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = - (_theResult___fst_exp__h519937 == 11'd2047) ? + (_theResult___fst_exp__h519938 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21505,10 +21524,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 = - (_theResult___fst_exp__h598094 == 11'd2047) ? + (_theResult___fst_exp__h598095 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21516,10 +21535,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907 = - (_theResult___fst_exp__h579684 == 11'd2047) ? + (_theResult___fst_exp__h579685 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21527,10 +21546,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 = - (_theResult___fst_exp__h598094 == 11'd2047) ? + (_theResult___fst_exp__h598095 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21538,14 +21557,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 = - (_theResult____h651116 == 16'd0 && + (_theResult____h651118 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h651687 : - _theResult____h651116 ; + enabled_ints__h651689 : + _theResult____h651118 ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || @@ -21607,77 +21626,77 @@ module mkCore(CLK, checkForException___d13698[4] || csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 = - ((f2_exp__h521133 == 8'd0) ? - (f2_sfd__h521134[22] ? + ((f2_exp__h521134 == 8'd0) ? + (f2_sfd__h521135[22] ? 6'd2 : - (f2_sfd__h521134[21] ? + (f2_sfd__h521135[21] ? 6'd3 : - (f2_sfd__h521134[20] ? + (f2_sfd__h521135[20] ? 6'd4 : - (f2_sfd__h521134[19] ? + (f2_sfd__h521135[19] ? 6'd5 : - (f2_sfd__h521134[18] ? + (f2_sfd__h521135[18] ? 6'd6 : - (f2_sfd__h521134[17] ? + (f2_sfd__h521135[17] ? 6'd7 : - (f2_sfd__h521134[16] ? + (f2_sfd__h521135[16] ? 6'd8 : - (f2_sfd__h521134[15] ? + (f2_sfd__h521135[15] ? 6'd9 : - (f2_sfd__h521134[14] ? + (f2_sfd__h521135[14] ? 6'd10 : - (f2_sfd__h521134[13] ? + (f2_sfd__h521135[13] ? 6'd11 : - (f2_sfd__h521134[12] ? + (f2_sfd__h521135[12] ? 6'd12 : - (f2_sfd__h521134[11] ? + (f2_sfd__h521135[11] ? 6'd13 : - (f2_sfd__h521134[10] ? + (f2_sfd__h521135[10] ? 6'd14 : - (f2_sfd__h521134[9] ? + (f2_sfd__h521135[9] ? 6'd15 : - (f2_sfd__h521134[8] ? + (f2_sfd__h521135[8] ? 6'd16 : - (f2_sfd__h521134[7] ? + (f2_sfd__h521135[7] ? 6'd17 : - (f2_sfd__h521134[6] ? + (f2_sfd__h521135[6] ? 6'd18 : - (f2_sfd__h521134[5] ? + (f2_sfd__h521135[5] ? 6'd19 : - (f2_sfd__h521134[4] ? + (f2_sfd__h521135[4] ? 6'd20 : - (f2_sfd__h521134[3] ? + (f2_sfd__h521135[3] ? 6'd21 : - (f2_sfd__h521134[2] ? + (f2_sfd__h521135[2] ? 6'd22 : - (f2_sfd__h521134[1] ? + (f2_sfd__h521135[1] ? 6'd23 : - (f2_sfd__h521134[0] ? + (f2_sfd__h521135[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474 = - (f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0 || - (f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) && - f2_sfd__h521134 == 23'd0) ? + (f2_exp__h521134 == 8'd255 && f2_sfd__h521135 != 23'd0 || + (f2_exp__h521134 == 8'd255 || f2_exp__h521134 == 8'd0) && + f2_sfd__h521135 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h521133 == 8'd0) ? + ((f2_exp__h521134 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 = - (f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0) ? - _theResult___snd_fst_sfd__h521449 : - _theResult___fst_sfd__h559589 ; + (f2_exp__h521134 == 8'd255 && f2_sfd__h521135 != 23'd0) ? + _theResult___snd_fst_sfd__h521450 : + _theResult___fst_sfd__h559590 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 = - { (f2_exp__h521133 == 8'd255) ? + { (f2_exp__h521134 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h559585, + _theResult___fst_exp__h559586, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21687,15 +21706,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 = - (f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0 || - (f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) && - f2_sfd__h521134 == 23'd0) ? + (f2_exp__h521134 == 8'd255 && f2_sfd__h521135 != 23'd0 || + (f2_exp__h521134 == 8'd255 || f2_exp__h521134 == 8'd0) && + f2_sfd__h521135 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[4] : @@ -21703,7 +21722,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[4] : @@ -21711,7 +21730,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[4] : @@ -21719,7 +21738,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[3] : @@ -21727,7 +21746,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[3] : @@ -21735,7 +21754,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[3] : @@ -21743,211 +21762,211 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 = - (f1_exp__h482139 == 8'd0) ? + (f1_exp__h482140 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002 = - (f2_exp__h521133 == 8'd0) ? + (f2_exp__h521134 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 = - ((f1_exp__h482139 == 8'd0) ? - (f1_sfd__h482140[22] ? + ((f1_exp__h482140 == 8'd0) ? + (f1_sfd__h482141[22] ? 6'd2 : - (f1_sfd__h482140[21] ? + (f1_sfd__h482141[21] ? 6'd3 : - (f1_sfd__h482140[20] ? + (f1_sfd__h482141[20] ? 6'd4 : - (f1_sfd__h482140[19] ? + (f1_sfd__h482141[19] ? 6'd5 : - (f1_sfd__h482140[18] ? + (f1_sfd__h482141[18] ? 6'd6 : - (f1_sfd__h482140[17] ? + (f1_sfd__h482141[17] ? 6'd7 : - (f1_sfd__h482140[16] ? + (f1_sfd__h482141[16] ? 6'd8 : - (f1_sfd__h482140[15] ? + (f1_sfd__h482141[15] ? 6'd9 : - (f1_sfd__h482140[14] ? + (f1_sfd__h482141[14] ? 6'd10 : - (f1_sfd__h482140[13] ? + (f1_sfd__h482141[13] ? 6'd11 : - (f1_sfd__h482140[12] ? + (f1_sfd__h482141[12] ? 6'd12 : - (f1_sfd__h482140[11] ? + (f1_sfd__h482141[11] ? 6'd13 : - (f1_sfd__h482140[10] ? + (f1_sfd__h482141[10] ? 6'd14 : - (f1_sfd__h482140[9] ? + (f1_sfd__h482141[9] ? 6'd15 : - (f1_sfd__h482140[8] ? + (f1_sfd__h482141[8] ? 6'd16 : - (f1_sfd__h482140[7] ? + (f1_sfd__h482141[7] ? 6'd17 : - (f1_sfd__h482140[6] ? + (f1_sfd__h482141[6] ? 6'd18 : - (f1_sfd__h482140[5] ? + (f1_sfd__h482141[5] ? 6'd19 : - (f1_sfd__h482140[4] ? + (f1_sfd__h482141[4] ? 6'd20 : - (f1_sfd__h482140[3] ? + (f1_sfd__h482141[3] ? 6'd21 : - (f1_sfd__h482140[2] ? + (f1_sfd__h482141[2] ? 6'd22 : - (f1_sfd__h482140[1] ? + (f1_sfd__h482141[1] ? 6'd23 : - (f1_sfd__h482140[0] ? + (f1_sfd__h482141[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989 = - (f1_exp__h482139 == 8'd255 && f1_sfd__h482140 != 23'd0 || - (f1_exp__h482139 == 8'd255 || f1_exp__h482139 == 8'd0) && - f1_sfd__h482140 == 23'd0) ? + (f1_exp__h482140 == 8'd255 && f1_sfd__h482141 != 23'd0 || + (f1_exp__h482140 == 8'd255 || f1_exp__h482140 == 8'd0) && + f1_sfd__h482141 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h482139 == 8'd0) ? + ((f1_exp__h482140 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 = - (f1_exp__h482139 == 8'd255 && f1_sfd__h482140 != 23'd0) ? - _theResult___snd_fst_sfd__h482455 : - _theResult___fst_sfd__h520736 ; + (f1_exp__h482140 == 8'd255 && f1_sfd__h482141 != 23'd0) ? + _theResult___snd_fst_sfd__h482456 : + _theResult___fst_sfd__h520737 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989, - (f1_exp__h482139 == 8'd255) ? + (f1_exp__h482140 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h520732, + _theResult___fst_exp__h520733, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 = - ((f3_exp__h560437 == 8'd0) ? - (f3_sfd__h560438[22] ? + ((f3_exp__h560438 == 8'd0) ? + (f3_sfd__h560439[22] ? 6'd2 : - (f3_sfd__h560438[21] ? + (f3_sfd__h560439[21] ? 6'd3 : - (f3_sfd__h560438[20] ? + (f3_sfd__h560439[20] ? 6'd4 : - (f3_sfd__h560438[19] ? + (f3_sfd__h560439[19] ? 6'd5 : - (f3_sfd__h560438[18] ? + (f3_sfd__h560439[18] ? 6'd6 : - (f3_sfd__h560438[17] ? + (f3_sfd__h560439[17] ? 6'd7 : - (f3_sfd__h560438[16] ? + (f3_sfd__h560439[16] ? 6'd8 : - (f3_sfd__h560438[15] ? + (f3_sfd__h560439[15] ? 6'd9 : - (f3_sfd__h560438[14] ? + (f3_sfd__h560439[14] ? 6'd10 : - (f3_sfd__h560438[13] ? + (f3_sfd__h560439[13] ? 6'd11 : - (f3_sfd__h560438[12] ? + (f3_sfd__h560439[12] ? 6'd12 : - (f3_sfd__h560438[11] ? + (f3_sfd__h560439[11] ? 6'd13 : - (f3_sfd__h560438[10] ? + (f3_sfd__h560439[10] ? 6'd14 : - (f3_sfd__h560438[9] ? + (f3_sfd__h560439[9] ? 6'd15 : - (f3_sfd__h560438[8] ? + (f3_sfd__h560439[8] ? 6'd16 : - (f3_sfd__h560438[7] ? + (f3_sfd__h560439[7] ? 6'd17 : - (f3_sfd__h560438[6] ? + (f3_sfd__h560439[6] ? 6'd18 : - (f3_sfd__h560438[5] ? + (f3_sfd__h560439[5] ? 6'd19 : - (f3_sfd__h560438[4] ? + (f3_sfd__h560439[4] ? 6'd20 : - (f3_sfd__h560438[3] ? + (f3_sfd__h560439[3] ? 6'd21 : - (f3_sfd__h560438[2] ? + (f3_sfd__h560439[2] ? 6'd22 : - (f3_sfd__h560438[1] ? + (f3_sfd__h560439[1] ? 6'd23 : - (f3_sfd__h560438[0] ? + (f3_sfd__h560439[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704 = - (f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0 || - (f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) && - f3_sfd__h560438 == 23'd0) ? + (f3_exp__h560438 == 8'd255 && f3_sfd__h560439 != 23'd0 || + (f3_exp__h560438 == 8'd255 || f3_exp__h560438 == 8'd0) && + f3_sfd__h560439 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h560437 == 8'd0) ? + ((f3_exp__h560438 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 = - (f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0) ? - _theResult___snd_fst_sfd__h560753 : - _theResult___fst_sfd__h598893 ; + (f3_exp__h560438 == 8'd255 && f3_sfd__h560439 != 23'd0) ? + _theResult___snd_fst_sfd__h560754 : + _theResult___fst_sfd__h598894 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 = - { (f3_exp__h560437 == 8'd255) ? + { (f3_exp__h560438 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h598889, + _theResult___fst_exp__h598890, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 = - (f3_exp__h560437 == 8'd0) ? + (f3_exp__h560438 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21957,9 +21976,9 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938 = - (f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0 || - (f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) && - f3_sfd__h560438 == 23'd0) ? + (f3_exp__h560438 == 8'd255 && f3_sfd__h560439 != 23'd0 || + (f3_exp__h560438 == 8'd255 || f3_exp__h560438 == 8'd0) && + f3_sfd__h560439 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22168,7 +22187,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || - _theResult___fst_exp__h540380 == 11'd2047) ? + _theResult___fst_exp__h540381 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22176,12 +22195,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || - _theResult___fst_exp__h501527 == 11'd2047) ? + _theResult___fst_exp__h501528 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -22189,12 +22208,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || - _theResult___fst_exp__h579684 == 11'd2047) ? + _theResult___fst_exp__h579685 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22202,7 +22221,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? @@ -22687,25 +22706,7 @@ module mkCore(CLK, 4'd9) ? 4'd14 : 4'd15)))))))))) ; - assign IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281 = - { (rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[97:96] == 2'd0) ? - { 2'd0, rob$deqPort_0_deq_data[95:32] } : - ((rob$deqPort_0_deq_data[329:325] != 5'd13 && - rob$deqPort_0_deq_data[97:96] == 2'd1) ? - { 2'd1, rob$deqPort_0_deq_data[95:32] } : - { 2'd2, - (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h721446 : - rob$deqPort_0_deq_data[95:32] }), - 5'h0A, - rob$deqPort_0_deq_data[26], - 64'hAAAAAAAAAAAAAAAA, - x_prv__h722029, - 64'hAAAAAAAAAAAAAAAA, - x__h725432, - 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; - assign IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661 = + assign IF_NOT_rob_deqPort_1_deq_data__5322_BIT_25_532_ETC___d15674 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -22744,48 +22745,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[2] : - _theResult___fst_exp__h520720 == 11'd2047 && - _theResult___fst_sfd__h520721 == 52'd0 ; + _theResult___fst_exp__h520721 == 11'd2047 && + _theResult___fst_sfd__h520722 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[2] : - _theResult___fst_exp__h559573 == 11'd2047 && - _theResult___fst_sfd__h559574 == 52'd0 ; + _theResult___fst_exp__h559574 == 11'd2047 && + _theResult___fst_sfd__h559575 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[2] : - _theResult___fst_exp__h598877 == 11'd2047 && - _theResult___fst_sfd__h598878 == 52'd0 ; + _theResult___fst_exp__h598878 == 11'd2047 && + _theResult___fst_sfd__h598879 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[1] : - _theResult___fst_exp__h519937 == 11'd0 && - guard__h511947 != 2'b0 ; + _theResult___fst_exp__h519938 == 11'd0 && + guard__h511948 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[1] : - _theResult___fst_exp__h558790 == 11'd0 && - guard__h550800 != 2'b0 ; + _theResult___fst_exp__h558791 == 11'd0 && + guard__h550801 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[1] : - _theResult___fst_exp__h598094 == 11'd0 && - guard__h590104 != 2'b0 ; + _theResult___fst_exp__h598095 == 11'd0 && + guard__h590105 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[0] : - _theResult___fst_exp__h519937 != 11'd2047 && - guard__h511947 != 2'b0 ; + _theResult___fst_exp__h519938 != 11'd2047 && + guard__h511948 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[0] : - _theResult___fst_exp__h558790 != 11'd2047 && - guard__h550800 != 2'b0 ; + _theResult___fst_exp__h558791 != 11'd2047 && + guard__h550801 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[0] : - _theResult___fst_exp__h598094 != 11'd2047 && - guard__h590104 != 2'b0 ; + _theResult___fst_exp__h598095 != 11'd2047 && + guard__h590105 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -22831,35 +22832,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371961 == 8'd255) ? + ((_theResult___fst_exp__h371962 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084) : - ((_theResult___fst_exp__h380646 == 8'd255) ? + ((_theResult___fst_exp__h380647 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371961 == 8'd255) ? + ((_theResult___fst_exp__h371962 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127) : - ((_theResult___fst_exp__h380646 == 8'd255) ? + ((_theResult___fst_exp__h380647 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[2] : - _theResult___fst_exp__h381194 == 8'd255 && - _theResult___fst_sfd__h381195 == 23'd0 ; + _theResult___fst_exp__h381195 == 8'd255 && + _theResult___fst_sfd__h381196 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[1] : - _theResult___fst_exp__h380646 == 8'd0 && - guard__h372569 != 2'b0 ; + _theResult___fst_exp__h380647 == 8'd0 && + guard__h372570 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[0] : - _theResult___fst_exp__h380646 != 8'd255 && - guard__h372569 != 2'b0 ; + _theResult___fst_exp__h380647 != 8'd255 && + guard__h372570 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? @@ -22869,35 +22870,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417658 == 8'd255) ? + ((_theResult___fst_exp__h417659 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476) : - ((_theResult___fst_exp__h426343 == 8'd255) ? + ((_theResult___fst_exp__h426344 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417658 == 8'd255) ? + ((_theResult___fst_exp__h417659 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519) : - ((_theResult___fst_exp__h426343 == 8'd255) ? + ((_theResult___fst_exp__h426344 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[2] : - _theResult___fst_exp__h426891 == 8'd255 && - _theResult___fst_sfd__h426892 == 23'd0 ; + _theResult___fst_exp__h426892 == 8'd255 && + _theResult___fst_sfd__h426893 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[1] : - _theResult___fst_exp__h426343 == 8'd0 && - guard__h418266 != 2'b0 ; + _theResult___fst_exp__h426344 == 8'd0 && + guard__h418267 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[0] : - _theResult___fst_exp__h426343 != 8'd255 && - guard__h418266 != 2'b0 ; + _theResult___fst_exp__h426344 != 8'd255 && + guard__h418267 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? @@ -22907,50 +22908,49 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463353 == 8'd255) ? + ((_theResult___fst_exp__h463354 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868) : - ((_theResult___fst_exp__h472038 == 8'd255) ? + ((_theResult___fst_exp__h472039 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463353 == 8'd255) ? + ((_theResult___fst_exp__h463354 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911) : - ((_theResult___fst_exp__h472038 == 8'd255) ? + ((_theResult___fst_exp__h472039 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[2] : - _theResult___fst_exp__h472586 == 8'd255 && - _theResult___fst_sfd__h472587 == 23'd0 ; + _theResult___fst_exp__h472587 == 8'd255 && + _theResult___fst_sfd__h472588 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[1] : - _theResult___fst_exp__h472038 == 8'd0 && - guard__h463961 != 2'b0 ; + _theResult___fst_exp__h472039 == 8'd0 && + guard__h463962 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[0] : - _theResult___fst_exp__h472038 != 8'd255 && - guard__h463961 != 2'b0 ; + _theResult___fst_exp__h472039 != 8'd255 && + guard__h463962 != 2'b0 ; assign IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 = checkForException___d13008[4] ? CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 : 4'd2 ; - assign IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916 = - { trap_val__h708464, - CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257, + assign IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926 = + { CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, commitStage_f_rob_data$D_OUT[95:32], 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h711506, - pc__h711407, - x__h713649, - x__h713841, + x_prv__h712487, + pc__h712387, + x__h714645, + x__h714837, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -23608,8 +23608,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h646693 : - w__h646688 ; + result__h646695 : + w__h646690 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23631,39 +23631,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h198528 : + n___1__h198529 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23716,7 +23716,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h197125 : + x__h197126 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ? 64'd0 : 64'd1) ; @@ -23728,7 +23728,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 = - _theResult_____2__h296520 == v__h295940 ; + _theResult_____2__h296521 == v__h295941 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23737,7 +23737,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 = - _theResult_____2__h304516 == v__h299285 ; + _theResult_____2__h304517 == v__h299286 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23766,14 +23766,14 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h302150 } ; + x__h302151 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 = - !MUX_flush_reservation$write_1__SEL_2 && + !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] : coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 = - MUX_flush_reservation$write_1__SEL_2 ? + MUX_flush_reservation$write_1__SEL_1 ? 58'h2AAAAAAAAAAAAAA : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] : @@ -23864,35 +23864,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h194453 : + n__h194454 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -23920,7 +23920,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 = - _theResult_____2__h310510 == v__h309799 ; + _theResult_____2__h310511 == v__h309800 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23929,7 +23929,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 = - _theResult_____2__h318364 == v__h313675 ; + _theResult_____2__h318365 == v__h313676 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24081,7 +24081,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 = - _theResult_____2__h331933 == v__h331501 ; + _theResult_____2__h331934 == v__h331502 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -24130,7 +24130,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 = - _theResult_____2__h328708 == v__h328276 ; + _theResult_____2__h328709 == v__h328277 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -24162,10 +24162,10 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h726048 : + upd__h727048 : csrf_minstret_ehr_data_rl ; - assign IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909 = - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ? + assign IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 = + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? { 43'd8192, csrf_mxr_reg, csrf_sum_reg, @@ -24230,8 +24230,8 @@ module mkCore(CLK, assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13954 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 || rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && fetchStage$RDY_pipelines_0_deq && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_claimSpecTag) ; @@ -24247,8 +24247,8 @@ module mkCore(CLK, IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13833 && (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14068 || rob$RDY_enqPort_1_enq && - regRenamingTable$RDY_rename_1_claimRename && regRenamingTable$RDY_rename_1_getRename && + regRenamingTable$RDY_rename_1_claimRename && fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078) ; assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306 = (fetchStage$pipelines_1_first[194:192] == 3'd2 && @@ -24288,17 +24288,17 @@ module mkCore(CLK, EN_mmioToPlatform_pRs_enq ? mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; - assign IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 = - rob$deqPort_0_canDeq ? y_avValue_fst__h729252 : 5'd0 ; - assign IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 = + assign IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 = + rob$deqPort_0_canDeq ? y_avValue_fst__h730270 : 5'd0 ; + assign IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h729727 : + y_avValue_snd_snd_snd_fst__h730745 : 2'd0 ; - assign IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180 = + assign IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? csrf_sepc_csr : csrf_mepc_csr ; - assign IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271 = + assign IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15282 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? { csrf_mpp_reg, 3'd0, @@ -24318,55 +24318,55 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501 = - { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256, + assign IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512 = + { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252, rob$deqPort_0_deq_data[95:32] } ; - assign IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662 = + assign IF_rob_deqPort_1_canDeq__5319_THEN_IF_NOT_rob__ETC___d15675 = rob$deqPort_1_canDeq ? - IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661 : + IF_NOT_rob_deqPort_1_deq_data__5322_BIT_25_532_ETC___d15674 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h511098[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74 = - sfdin__h417652[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99 = - sfdin__h445581[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h549951[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29 = - sfdin__h354189[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109 = - sfdin__h463347[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39 = - sfdin__h371955[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h589255[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64 = - sfdin__h399886[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h501478[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66 = - _theResult___snd__h408499[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h519883[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79 = - _theResult___snd__h426289[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h540331[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101 = - _theResult___snd__h454194[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h558736[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31 = - _theResult___snd__h362802[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114 = - _theResult___snd__h471984[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h579635[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44 = - _theResult___snd__h380592[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h598040[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin11099_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h511099[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin17653_BIT_33_THEN_2_ELSE_0__q74 = + sfdin__h417653[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin45582_BIT_33_THEN_2_ELSE_0__q99 = + sfdin__h445582[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin49952_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h549952[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin54190_BIT_33_THEN_2_ELSE_0__q29 = + sfdin__h354190[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin63348_BIT_33_THEN_2_ELSE_0__q109 = + sfdin__h463348[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin71956_BIT_33_THEN_2_ELSE_0__q39 = + sfdin__h371956[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin89256_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h589256[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin99887_BIT_33_THEN_2_ELSE_0__q64 = + sfdin__h399887[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd01479_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h501479[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd08500_BIT_33_THEN_2_ELSE_0__q66 = + _theResult___snd__h408500[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd19884_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h519884[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd26290_BIT_33_THEN_2_ELSE_0__q79 = + _theResult___snd__h426290[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd40332_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h540332[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd54195_BIT_33_THEN_2_ELSE_0__q101 = + _theResult___snd__h454195[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58737_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h558737[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd62803_BIT_33_THEN_2_ELSE_0__q31 = + _theResult___snd__h362803[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd71985_BIT_33_THEN_2_ELSE_0__q114 = + _theResult___snd__h471985[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd79636_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h579636[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd80593_BIT_33_THEN_2_ELSE_0__q44 = + _theResult___snd__h380593[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98041_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h598041[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? @@ -24457,138 +24457,138 @@ module mkCore(CLK, !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] && !checkForException___d13698[4] && NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723 ; - assign NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 = - (fflags__h732495 & csrf_fflags_reg) != fflags__h732495 || + assign NOT_IF_NOT_rob_deqPort_0_canDeq__5314_5315_OR__ETC___d15680 = + (fflags__h733530 & csrf_fflags_reg) != fflags__h733530 || csrf_fs_reg != 2'b11 && - (IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662 || - fflags__h732495 != 5'd0) ; + (IF_rob_deqPort_1_canDeq__5319_THEN_IF_NOT_rob__ETC___d15675 || + fflags__h733530 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 = - !f2_sfd__h521134[21] && !f2_sfd__h521134[20] && - !f2_sfd__h521134[19] && - !f2_sfd__h521134[18] && - !f2_sfd__h521134[17] && - !f2_sfd__h521134[16] && - !f2_sfd__h521134[15] && - !f2_sfd__h521134[14] && - !f2_sfd__h521134[13] && - !f2_sfd__h521134[12] && - !f2_sfd__h521134[11] && - !f2_sfd__h521134[10] && - !f2_sfd__h521134[9] && - !f2_sfd__h521134[8] && - !f2_sfd__h521134[7] && - !f2_sfd__h521134[6] && - !f2_sfd__h521134[5] && - !f2_sfd__h521134[4] && - !f2_sfd__h521134[3] && - !f2_sfd__h521134[2] && - !f2_sfd__h521134[1] && - !f2_sfd__h521134[0] ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + !f2_sfd__h521135[21] && !f2_sfd__h521135[20] && + !f2_sfd__h521135[19] && + !f2_sfd__h521135[18] && + !f2_sfd__h521135[17] && + !f2_sfd__h521135[16] && + !f2_sfd__h521135[15] && + !f2_sfd__h521135[14] && + !f2_sfd__h521135[13] && + !f2_sfd__h521135[12] && + !f2_sfd__h521135[11] && + !f2_sfd__h521135[10] && + !f2_sfd__h521135[9] && + !f2_sfd__h521135[8] && + !f2_sfd__h521135[7] && + !f2_sfd__h521135[6] && + !f2_sfd__h521135[5] && + !f2_sfd__h521135[4] && + !f2_sfd__h521135[3] && + !f2_sfd__h521135[2] && + !f2_sfd__h521135[1] && + !f2_sfd__h521135[0] ; + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960) ; - assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) && - (value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) && + assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 = + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 == 23'd0) && + (f1_exp__h482140 != 8'd255 || f1_sfd__h482141 != 23'd0) && + (f1_exp__h482140 != 8'd0 || f1_sfd__h482141 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 = - ((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992) | - ((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) && - (f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) && - (f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) && + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 | + ((f2_exp__h521134 != 8'd255 || f2_sfd__h521135 == 23'd0) && + (f2_exp__h521134 != 8'd255 || f2_sfd__h521135 != 23'd0) && + (f2_exp__h521134 != 8'd0 || f2_sfd__h521135 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 = - !f1_sfd__h482140[21] && !f1_sfd__h482140[20] && - !f1_sfd__h482140[19] && - !f1_sfd__h482140[18] && - !f1_sfd__h482140[17] && - !f1_sfd__h482140[16] && - !f1_sfd__h482140[15] && - !f1_sfd__h482140[14] && - !f1_sfd__h482140[13] && - !f1_sfd__h482140[12] && - !f1_sfd__h482140[11] && - !f1_sfd__h482140[10] && - !f1_sfd__h482140[9] && - !f1_sfd__h482140[8] && - !f1_sfd__h482140[7] && - !f1_sfd__h482140[6] && - !f1_sfd__h482140[5] && - !f1_sfd__h482140[4] && - !f1_sfd__h482140[3] && - !f1_sfd__h482140[2] && - !f1_sfd__h482140[1] && - !f1_sfd__h482140[0] ; + !f1_sfd__h482141[21] && !f1_sfd__h482141[20] && + !f1_sfd__h482141[19] && + !f1_sfd__h482141[18] && + !f1_sfd__h482141[17] && + !f1_sfd__h482141[16] && + !f1_sfd__h482141[15] && + !f1_sfd__h482141[14] && + !f1_sfd__h482141[13] && + !f1_sfd__h482141[12] && + !f1_sfd__h482141[11] && + !f1_sfd__h482141[10] && + !f1_sfd__h482141[9] && + !f1_sfd__h482141[8] && + !f1_sfd__h482141[7] && + !f1_sfd__h482141[6] && + !f1_sfd__h482141[5] && + !f1_sfd__h482141[4] && + !f1_sfd__h482141[3] && + !f1_sfd__h482141[2] && + !f1_sfd__h482141[1] && + !f1_sfd__h482141[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 = - !f3_sfd__h560438[21] && !f3_sfd__h560438[20] && - !f3_sfd__h560438[19] && - !f3_sfd__h560438[18] && - !f3_sfd__h560438[17] && - !f3_sfd__h560438[16] && - !f3_sfd__h560438[15] && - !f3_sfd__h560438[14] && - !f3_sfd__h560438[13] && - !f3_sfd__h560438[12] && - !f3_sfd__h560438[11] && - !f3_sfd__h560438[10] && - !f3_sfd__h560438[9] && - !f3_sfd__h560438[8] && - !f3_sfd__h560438[7] && - !f3_sfd__h560438[6] && - !f3_sfd__h560438[5] && - !f3_sfd__h560438[4] && - !f3_sfd__h560438[3] && - !f3_sfd__h560438[2] && - !f3_sfd__h560438[1] && - !f3_sfd__h560438[0] ; + !f3_sfd__h560439[21] && !f3_sfd__h560439[20] && + !f3_sfd__h560439[19] && + !f3_sfd__h560439[18] && + !f3_sfd__h560439[17] && + !f3_sfd__h560439[16] && + !f3_sfd__h560439[15] && + !f3_sfd__h560439[14] && + !f3_sfd__h560439[13] && + !f3_sfd__h560439[12] && + !f3_sfd__h560439[11] && + !f3_sfd__h560439[10] && + !f3_sfd__h560439[9] && + !f3_sfd__h560439[8] && + !f3_sfd__h560439[7] && + !f3_sfd__h560439[6] && + !f3_sfd__h560439[5] && + !f3_sfd__h560439[4] && + !f3_sfd__h560439[3] && + !f3_sfd__h560439[2] && + !f3_sfd__h560439[1] && + !f3_sfd__h560439[0] ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 ; - assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614 = + assign NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14624 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] == 4'd0 || commitStage_commitTrap[35:32] == 4'd1 || @@ -24601,13 +24601,13 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd11) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; - assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621 = - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614 || + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + assign NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14631 = + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14624 || coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 = + assign NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 = (!commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd14) && (!commitStage_commitTrap[36] || @@ -24623,12 +24623,36 @@ module mkCore(CLK, commitStage_commitTrap[35:32] == 4'd14) && (commitStage_commitTrap[36] || commitStage_commitTrap[35:32] != 4'd3 || - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ; - assign NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 = + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ; + assign NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005 = !commitStage_rg_run_state && !commitStage_commitTrap[165] && !rob$deqPort_0_deq_data[167] && !rob$deqPort_0_deq_data[18] && rob$deqPort_0_deq_data[25] ; + assign NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15016 = + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005 && + (rob$deqPort_0_deq_data[329:325] == 5'd0 || + rob$deqPort_0_deq_data[329:325] == 5'd21 || + rob$deqPort_0_deq_data[329:325] == 5'd17 || + rob$deqPort_0_deq_data[329:325] == 5'd18 || + rob$deqPort_0_deq_data[329:325] == 5'd13 || + rob$deqPort_0_deq_data[329:325] == 5'd16 || + rob$deqPort_0_deq_data[329:325] == 5'd15 || + rob$deqPort_0_deq_data[329:325] == 5'd19 || + rob$deqPort_0_deq_data[329:325] == 5'd20) && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; + assign NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15368 = + NOT_commitStage_rg_run_state_4345_4346_AND_NOT_ETC___d15005 && + rob$deqPort_0_deq_data[329:325] != 5'd0 && + rob$deqPort_0_deq_data[329:325] != 5'd21 && + rob$deqPort_0_deq_data[329:325] != 5'd17 && + rob$deqPort_0_deq_data[329:325] != 5'd18 && + rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[329:325] != 5'd16 && + rob$deqPort_0_deq_data[329:325] != 5'd15 && + rob$deqPort_0_deq_data[329:325] != 5'd19 && + rob$deqPort_0_deq_data[329:325] != 5'd20 && + _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 ; assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 = (!coreFix_aluExe_0_bypassWire_0$whas || !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) && @@ -25133,7 +25157,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 && !csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 && - csr_addr__h655325 != 12'h8FF) ; + csr_addr__h655327 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -25158,11 +25182,11 @@ module mkCore(CLK, (fetchStage$pipelines_1_first[231:200] != 32'h10500073 || !csrf_tw_reg || csrf_prv_reg == 2'd3) ; - assign NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 = - !csrf_prv_reg_read__2787_ULE_1___d14685 || + assign NOT_csrf_prv_reg_read__2787_ULE_1_4696_4738_OR_ETC___d14742 = + !csrf_prv_reg_read__2787_ULE_1___d14696 || (commitStage_commitTrap[36] ? - !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 : - !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705) ; + !_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 : + !_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716) ; assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13527 = !fetchStage$pipelines_0_canDeq || !regRenamingTable$rename_0_canRename || @@ -25258,9 +25282,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h655326 == 5'd0 && - imm__h655327 == 32'd0 || - csr_addr__h655325[11:10] != 2'b11 ; + rs1__h655328 == 5'd0 && + imm__h655329 == 32'd0 || + csr_addr__h655327[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && @@ -25371,12 +25395,12 @@ module mkCore(CLK, mmio_cRsQ_empty) ; assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqSt && - coreFix_memExe_lsq$RDY_firstSt ; + coreFix_memExe_lsq$RDY_firstSt && + coreFix_memExe_lsq$RDY_deqSt ; assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 = !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ && - coreFix_memExe_lsq$RDY_deqLd && - coreFix_memExe_lsq$RDY_firstLd ; + coreFix_memExe_lsq$RDY_firstLd && + coreFix_memExe_lsq$RDY_deqLd ; assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 = (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT || !mmio_dataPendQ_enqReq_lat_0$whas && @@ -25513,14 +25537,14 @@ module mkCore(CLK, NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725 && rob$enqPort_1_canEnq && epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13894 ; - assign NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345 = + assign NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_RDY_ETC___d15356 = (!rob$deqPort_0_canDeq || rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N) && (!rob$deqPort_1_canDeq || rob$RDY_deqPort_1_deq_data && - NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342) ; - assign NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 = + NOT_rob_deqPort_1_deq_data__5322_BIT_25_5323_5_ETC___d15353) ; + assign NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 = (!rob$deqPort_0_canDeq || rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] && !rob$deqPort_0_deq_data[167] && @@ -25534,15 +25558,15 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] != 5'd19 && rob$deqPort_0_deq_data[329:325] != 5'd20) && rob$deqPort_1_canDeq ; - assign NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983 = + assign NOT_rob_deqPort_0_deq_data__4339_BITS_329_TO_3_ETC___d14993 = rob$deqPort_0_deq_data[329:325] != 5'd13 || - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd7 || csrf_stats_module_writeQ$FULL_N) && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 != + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 != 6'd6 || csrf_terminate_module_terminateQ$FULL_N) ; - assign NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342 = + assign NOT_rob_deqPort_1_deq_data__5322_BIT_25_5323_5_ETC___d15353 = !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -25581,33 +25605,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938 = { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258, - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 } ; + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260, + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265, - !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266, + { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, + !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - x__h291615 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039 = - { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 } ; - assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057 = - { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260, - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 } ; + x__h291616 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16096 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16052 = + { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16052, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ; + assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16070 = + { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16061, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = - { {4{f2_exp21133_MINUS_127__q176[7]}}, - f2_exp21133_MINUS_127__q176 } ; + { {4{f2_exp21134_MINUS_127__q176[7]}}, + f2_exp21134_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^ 12'h800) <= @@ -25617,8 +25641,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 = - { {4{f1_exp82139_MINUS_127__q136[7]}}, - f1_exp82139_MINUS_127__q136 } ; + { {4{f1_exp82140_MINUS_127__q136[7]}}, + f1_exp82140_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^ 12'h800) <= @@ -25628,8 +25652,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 = - { {4{f3_exp60437_MINUS_127__q153[7]}}, - f3_exp60437_MINUS_127__q153 } ; + { {4{f3_exp60438_MINUS_127__q153[7]}}, + f3_exp60438_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^ 12'h800) <= @@ -25714,15 +25738,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169 = { 3'd0, - _theResult___fst_exp__h354195 == 8'd0 && - (sfdin__h354189[56:34] == 23'd0 || guard__h346094 != 2'b0), + _theResult___fst_exp__h354196 == 8'd0 && + (sfdin__h354190[56:34] == 23'd0 || guard__h346095 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h354792 == 8'd255 && - _theResult___fst_sfd__h354793 == 23'd0, + _theResult___fst_exp__h354793 == 8'd255 && + _theResult___fst_sfd__h354794 == 23'd0, 1'd0, - _theResult___fst_exp__h354195 != 8'd255 && - guard__h346094 != 2'b0 } ; + _theResult___fst_exp__h354196 != 8'd255 && + guard__h346095 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ^ @@ -25730,15 +25754,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561 = { 3'd0, - _theResult___fst_exp__h399892 == 8'd0 && - (sfdin__h399886[56:34] == 23'd0 || guard__h391793 != 2'b0), + _theResult___fst_exp__h399893 == 8'd0 && + (sfdin__h399887[56:34] == 23'd0 || guard__h391794 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h400489 == 8'd255 && - _theResult___fst_sfd__h400490 == 23'd0, + _theResult___fst_exp__h400490 == 8'd255 && + _theResult___fst_sfd__h400491 == 23'd0, 1'd0, - _theResult___fst_exp__h399892 != 8'd255 && - guard__h391793 != 2'b0 } ; + _theResult___fst_exp__h399893 != 8'd255 && + guard__h391794 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ^ @@ -25746,15 +25770,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953 = { 3'd0, - _theResult___fst_exp__h445587 == 8'd0 && - (sfdin__h445581[56:34] == 23'd0 || guard__h437488 != 2'b0), + _theResult___fst_exp__h445588 == 8'd0 && + (sfdin__h445582[56:34] == 23'd0 || guard__h437489 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h446184 == 8'd255 && - _theResult___fst_sfd__h446185 == 23'd0, + _theResult___fst_exp__h446185 == 8'd255 && + _theResult___fst_sfd__h446186 == 23'd0, 1'd0, - _theResult___fst_exp__h445587 != 8'd255 && - guard__h437488 != 2'b0 } ; + _theResult___fst_exp__h445588 != 8'd255 && + guard__h437489 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ^ @@ -25762,37 +25786,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758 = { 3'd0, - _theResult___fst_exp__h511104 == 11'd0 && - (sfdin__h511098[56:5] == 52'd0 || guard__h502878 != 2'b0), + _theResult___fst_exp__h511105 == 11'd0 && + (sfdin__h511099[56:5] == 52'd0 || guard__h502879 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h511936 == 11'd2047 && - _theResult___fst_sfd__h511937 == 52'd0, + _theResult___fst_exp__h511937 == 11'd2047 && + _theResult___fst_sfd__h511938 == 52'd0, 1'd0, - _theResult___fst_exp__h511104 != 11'd2047 && - guard__h502878 != 2'b0 } ; + _theResult___fst_exp__h511105 != 11'd2047 && + guard__h502879 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799 = { 3'd0, - _theResult___fst_exp__h549957 == 11'd0 && - (sfdin__h549951[56:5] == 52'd0 || guard__h541731 != 2'b0), + _theResult___fst_exp__h549958 == 11'd0 && + (sfdin__h549952[56:5] == 52'd0 || guard__h541732 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h550789 == 11'd2047 && - _theResult___fst_sfd__h550790 == 52'd0, + _theResult___fst_exp__h550790 == 11'd2047 && + _theResult___fst_sfd__h550791 == 52'd0, 1'd0, - _theResult___fst_exp__h549957 != 11'd2047 && - guard__h541731 != 2'b0 } ; + _theResult___fst_exp__h549958 != 11'd2047 && + guard__h541732 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843 = { 3'd0, - _theResult___fst_exp__h589261 == 11'd0 && - (sfdin__h589255[56:5] == 52'd0 || guard__h581035 != 2'b0), + _theResult___fst_exp__h589262 == 11'd0 && + (sfdin__h589256[56:5] == 52'd0 || guard__h581036 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h590093 == 11'd2047 && - _theResult___fst_sfd__h590094 == 52'd0, + _theResult___fst_exp__h590094 == 11'd2047 && + _theResult___fst_sfd__h590095 == 52'd0, 1'd0, - _theResult___fst_exp__h589261 != 11'd2047 && - guard__h581035 != 2'b0 } ; + _theResult___fst_exp__h589262 != 11'd2047 && + guard__h581036 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ^ @@ -25810,15 +25834,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198 = { 3'd0, - _theResult___fst_exp__h371961 == 8'd0 && - (sfdin__h371955[56:34] == 23'd0 || guard__h363733 != 2'b0), + _theResult___fst_exp__h371962 == 8'd0 && + (sfdin__h371956[56:34] == 23'd0 || guard__h363734 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h372558 == 8'd255 && - _theResult___fst_sfd__h372559 == 23'd0, + _theResult___fst_exp__h372559 == 8'd255 && + _theResult___fst_sfd__h372560 == 23'd0, 1'd0, - _theResult___fst_exp__h371961 != 8'd255 && - guard__h363733 != 2'b0 } ; + _theResult___fst_exp__h371962 != 8'd255 && + guard__h363734 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ^ @@ -25826,15 +25850,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590 = { 3'd0, - _theResult___fst_exp__h417658 == 8'd0 && - (sfdin__h417652[56:34] == 23'd0 || guard__h409430 != 2'b0), + _theResult___fst_exp__h417659 == 8'd0 && + (sfdin__h417653[56:34] == 23'd0 || guard__h409431 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h418255 == 8'd255 && - _theResult___fst_sfd__h418256 == 23'd0, + _theResult___fst_exp__h418256 == 8'd255 && + _theResult___fst_sfd__h418257 == 23'd0, 1'd0, - _theResult___fst_exp__h417658 != 8'd255 && - guard__h409430 != 2'b0 } ; + _theResult___fst_exp__h417659 != 8'd255 && + guard__h409431 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ^ @@ -25842,15 +25866,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982 = { 3'd0, - _theResult___fst_exp__h463353 == 8'd0 && - (sfdin__h463347[56:34] == 23'd0 || guard__h455125 != 2'b0), + _theResult___fst_exp__h463354 == 8'd0 && + (sfdin__h463348[56:34] == 23'd0 || guard__h455126 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h463950 == 8'd255 && - _theResult___fst_sfd__h463951 == 23'd0, + _theResult___fst_exp__h463951 == 8'd255 && + _theResult___fst_sfd__h463952 == 23'd0, 1'd0, - _theResult___fst_exp__h463353 != 8'd255 && - guard__h455125 != 2'b0 } ; + _theResult___fst_exp__h463354 != 8'd255 && + guard__h455126 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^ @@ -25864,37 +25888,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741 = { 3'd0, - _theResult___fst_exp__h501527 == 11'd0 && - guard__h493566 != 2'b0, + _theResult___fst_exp__h501528 == 11'd0 && + guard__h493567 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h502285 == 11'd2047 && - _theResult___fst_sfd__h502286 == 52'd0, + _theResult___fst_exp__h502286 == 11'd2047 && + _theResult___fst_sfd__h502287 == 52'd0, 1'd0, - _theResult___fst_exp__h501527 != 11'd2047 && - guard__h493566 != 2'b0 } ; + _theResult___fst_exp__h501528 != 11'd2047 && + guard__h493567 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782 = { 3'd0, - _theResult___fst_exp__h540380 == 11'd0 && - guard__h532419 != 2'b0, + _theResult___fst_exp__h540381 == 11'd0 && + guard__h532420 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h541138 == 11'd2047 && - _theResult___fst_sfd__h541139 == 52'd0, + _theResult___fst_exp__h541139 == 11'd2047 && + _theResult___fst_sfd__h541140 == 52'd0, 1'd0, - _theResult___fst_exp__h540380 != 11'd2047 && - guard__h532419 != 2'b0 } ; + _theResult___fst_exp__h540381 != 11'd2047 && + guard__h532420 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826 = { 3'd0, - _theResult___fst_exp__h579684 == 11'd0 && - guard__h571723 != 2'b0, + _theResult___fst_exp__h579685 == 11'd0 && + guard__h571724 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h580442 == 11'd2047 && - _theResult___fst_sfd__h580443 == 52'd0, + _theResult___fst_exp__h580443 == 11'd2047 && + _theResult___fst_sfd__h580444 == 52'd0, 1'd0, - _theResult___fst_exp__h579684 != 11'd2047 && - guard__h571723 != 2'b0 } ; + _theResult___fst_exp__h579685 != 11'd2047 && + guard__h571724 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^ @@ -25930,15 +25954,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181 = { 3'd0, - _theResult___fst_exp__h362851 == 8'd0 && - guard__h354803 != 2'b0, + _theResult___fst_exp__h362852 == 8'd0 && + guard__h354804 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h363374 == 8'd255 && - _theResult___fst_sfd__h363375 == 23'd0, + _theResult___fst_exp__h363375 == 8'd255 && + _theResult___fst_sfd__h363376 == 23'd0, 1'd0, - _theResult___fst_exp__h362851 != 8'd255 && - guard__h354803 != 2'b0 } ; + _theResult___fst_exp__h362852 != 8'd255 && + guard__h354804 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^ @@ -25952,15 +25976,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573 = { 3'd0, - _theResult___fst_exp__h408548 == 8'd0 && - guard__h400500 != 2'b0, + _theResult___fst_exp__h408549 == 8'd0 && + guard__h400501 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h409071 == 8'd255 && - _theResult___fst_sfd__h409072 == 23'd0, + _theResult___fst_exp__h409072 == 8'd255 && + _theResult___fst_sfd__h409073 == 23'd0, 1'd0, - _theResult___fst_exp__h408548 != 8'd255 && - guard__h400500 != 2'b0 } ; + _theResult___fst_exp__h408549 != 8'd255 && + guard__h400501 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^ @@ -25974,15 +25998,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965 = { 3'd0, - _theResult___fst_exp__h454243 == 8'd0 && - guard__h446195 != 2'b0, + _theResult___fst_exp__h454244 == 8'd0 && + guard__h446196 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h454766 == 8'd255 && - _theResult___fst_sfd__h454767 == 23'd0, + _theResult___fst_exp__h454767 == 8'd255 && + _theResult___fst_sfd__h454768 == 23'd0, 1'd0, - _theResult___fst_exp__h454243 != 8'd255 && - guard__h446195 != 2'b0 } ; + _theResult___fst_exp__h454244 != 8'd255 && + guard__h446196 != 2'b0 } ; assign _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798 = { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, @@ -25996,7 +26020,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -26010,33 +26034,35 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138 = - sfd__h521495 >> + sfd__h521496 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653 = - sfd__h482501 >> + sfd__h482502 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368 = - sfd__h560799 >> + sfd__h560800 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558 = - sfd__h338479 >> + sfd__h338480 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950 = - sfd__h384181 >> + sfd__h384182 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342 = - sfd__h429876 >> + sfd__h429877 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ; - assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705 = - medeleg_csr__read__h610369[i__h708478] ; - assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 = - mideleg_csr__read__h610464[i__h708638] ; + assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 = + mip_csr__read__h611252 == commitStage_rg_old_mip_csr_val ; + assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716 = + medeleg_csr__read__h610371[i__h709458] ; + assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 = + mideleg_csr__read__h610466[i__h709618] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 = 12'd3074 - { 6'd0, @@ -26442,51 +26468,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 = 12'd3970 - { 7'd0, - f2_sfd__h521134[22] ? + f2_sfd__h521135[22] ? 5'd0 : - (f2_sfd__h521134[21] ? + (f2_sfd__h521135[21] ? 5'd1 : - (f2_sfd__h521134[20] ? + (f2_sfd__h521135[20] ? 5'd2 : - (f2_sfd__h521134[19] ? + (f2_sfd__h521135[19] ? 5'd3 : - (f2_sfd__h521134[18] ? + (f2_sfd__h521135[18] ? 5'd4 : - (f2_sfd__h521134[17] ? + (f2_sfd__h521135[17] ? 5'd5 : - (f2_sfd__h521134[16] ? + (f2_sfd__h521135[16] ? 5'd6 : - (f2_sfd__h521134[15] ? + (f2_sfd__h521135[15] ? 5'd7 : - (f2_sfd__h521134[14] ? + (f2_sfd__h521135[14] ? 5'd8 : - (f2_sfd__h521134[13] ? + (f2_sfd__h521135[13] ? 5'd9 : - (f2_sfd__h521134[12] ? + (f2_sfd__h521135[12] ? 5'd10 : - (f2_sfd__h521134[11] ? + (f2_sfd__h521135[11] ? 5'd11 : - (f2_sfd__h521134[10] ? + (f2_sfd__h521135[10] ? 5'd12 : - (f2_sfd__h521134[9] ? + (f2_sfd__h521135[9] ? 5'd13 : - (f2_sfd__h521134[8] ? + (f2_sfd__h521135[8] ? 5'd14 : - (f2_sfd__h521134[7] ? + (f2_sfd__h521135[7] ? 5'd15 : - (f2_sfd__h521134[6] ? + (f2_sfd__h521135[6] ? 5'd16 : - (f2_sfd__h521134[5] ? + (f2_sfd__h521135[5] ? 5'd17 : - (f2_sfd__h521134[4] ? + (f2_sfd__h521135[4] ? 5'd18 : - (f2_sfd__h521134[3] ? + (f2_sfd__h521135[3] ? 5'd19 : - (f2_sfd__h521134[2] ? + (f2_sfd__h521135[2] ? 5'd20 : - (f2_sfd__h521134[1] ? + (f2_sfd__h521135[1] ? 5'd21 : - (f2_sfd__h521134[0] ? + (f2_sfd__h521135[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 = @@ -26500,51 +26526,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 = 12'd3970 - { 7'd0, - f1_sfd__h482140[22] ? + f1_sfd__h482141[22] ? 5'd0 : - (f1_sfd__h482140[21] ? + (f1_sfd__h482141[21] ? 5'd1 : - (f1_sfd__h482140[20] ? + (f1_sfd__h482141[20] ? 5'd2 : - (f1_sfd__h482140[19] ? + (f1_sfd__h482141[19] ? 5'd3 : - (f1_sfd__h482140[18] ? + (f1_sfd__h482141[18] ? 5'd4 : - (f1_sfd__h482140[17] ? + (f1_sfd__h482141[17] ? 5'd5 : - (f1_sfd__h482140[16] ? + (f1_sfd__h482141[16] ? 5'd6 : - (f1_sfd__h482140[15] ? + (f1_sfd__h482141[15] ? 5'd7 : - (f1_sfd__h482140[14] ? + (f1_sfd__h482141[14] ? 5'd8 : - (f1_sfd__h482140[13] ? + (f1_sfd__h482141[13] ? 5'd9 : - (f1_sfd__h482140[12] ? + (f1_sfd__h482141[12] ? 5'd10 : - (f1_sfd__h482140[11] ? + (f1_sfd__h482141[11] ? 5'd11 : - (f1_sfd__h482140[10] ? + (f1_sfd__h482141[10] ? 5'd12 : - (f1_sfd__h482140[9] ? + (f1_sfd__h482141[9] ? 5'd13 : - (f1_sfd__h482140[8] ? + (f1_sfd__h482141[8] ? 5'd14 : - (f1_sfd__h482140[7] ? + (f1_sfd__h482141[7] ? 5'd15 : - (f1_sfd__h482140[6] ? + (f1_sfd__h482141[6] ? 5'd16 : - (f1_sfd__h482140[5] ? + (f1_sfd__h482141[5] ? 5'd17 : - (f1_sfd__h482140[4] ? + (f1_sfd__h482141[4] ? 5'd18 : - (f1_sfd__h482140[3] ? + (f1_sfd__h482141[3] ? 5'd19 : - (f1_sfd__h482140[2] ? + (f1_sfd__h482141[2] ? 5'd20 : - (f1_sfd__h482140[1] ? + (f1_sfd__h482141[1] ? 5'd21 : - (f1_sfd__h482140[0] ? + (f1_sfd__h482141[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 = @@ -26558,51 +26584,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 = 12'd3970 - { 7'd0, - f3_sfd__h560438[22] ? + f3_sfd__h560439[22] ? 5'd0 : - (f3_sfd__h560438[21] ? + (f3_sfd__h560439[21] ? 5'd1 : - (f3_sfd__h560438[20] ? + (f3_sfd__h560439[20] ? 5'd2 : - (f3_sfd__h560438[19] ? + (f3_sfd__h560439[19] ? 5'd3 : - (f3_sfd__h560438[18] ? + (f3_sfd__h560439[18] ? 5'd4 : - (f3_sfd__h560438[17] ? + (f3_sfd__h560439[17] ? 5'd5 : - (f3_sfd__h560438[16] ? + (f3_sfd__h560439[16] ? 5'd6 : - (f3_sfd__h560438[15] ? + (f3_sfd__h560439[15] ? 5'd7 : - (f3_sfd__h560438[14] ? + (f3_sfd__h560439[14] ? 5'd8 : - (f3_sfd__h560438[13] ? + (f3_sfd__h560439[13] ? 5'd9 : - (f3_sfd__h560438[12] ? + (f3_sfd__h560439[12] ? 5'd10 : - (f3_sfd__h560438[11] ? + (f3_sfd__h560439[11] ? 5'd11 : - (f3_sfd__h560438[10] ? + (f3_sfd__h560439[10] ? 5'd12 : - (f3_sfd__h560438[9] ? + (f3_sfd__h560439[9] ? 5'd13 : - (f3_sfd__h560438[8] ? + (f3_sfd__h560439[8] ? 5'd14 : - (f3_sfd__h560438[7] ? + (f3_sfd__h560439[7] ? 5'd15 : - (f3_sfd__h560438[6] ? + (f3_sfd__h560439[6] ? 5'd16 : - (f3_sfd__h560438[5] ? + (f3_sfd__h560439[5] ? 5'd17 : - (f3_sfd__h560438[4] ? + (f3_sfd__h560439[4] ? 5'd18 : - (f3_sfd__h560438[3] ? + (f3_sfd__h560439[3] ? 5'd19 : - (f3_sfd__h560438[2] ? + (f3_sfd__h560439[2] ? 5'd20 : - (f3_sfd__h560438[1] ? + (f3_sfd__h560439[1] ? 5'd21 : - (f3_sfd__h560438[0] ? + (f3_sfd__h560439[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 = @@ -26631,14 +26657,14 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h669623 == 1'd1 && + k__h669625 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == 1'd1 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208 ; assign _dfoo18 = - k__h669623 == 1'd0 && + k__h669625 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == @@ -26653,25 +26679,25 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 && fetchStage$pipelines_1_first[191:189] != 3'd0 && fetchStage$pipelines_1_first[191:189] != 3'd2 ; - assign _dfoo20 = - commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 || - NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ; + assign _dfoo22 = + commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 || + NOT_commitStage_commitTrap_4347_BIT_36_4589_45_ETC___d14695 ; assign _dfoo24 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd40 || rob$deqPort_0_deq_data[329:325] == 5'd19 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo26 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18 || rob$deqPort_0_deq_data[329:325] == 5'd20 ; assign _dfoo32 = rob$deqPort_0_deq_data[329:325] == 5'd13 && - (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd8 || - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd18) || rob$deqPort_0_deq_data[329:325] == 5'd19 ; assign _dfoo7 = @@ -26755,1421 +26781,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h296520 = + assign _theResult_____2__h296521 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046) ? - next_deqP___1__h296799 : + next_deqP___1__h296800 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h304516 = + assign _theResult_____2__h304517 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153) ? - next_deqP___1__h304795 : + next_deqP___1__h304796 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h310510 = + assign _theResult_____2__h310511 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324) ? - next_deqP___1__h311076 : + next_deqP___1__h311077 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h318364 = + assign _theResult_____2__h318365 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420) ? - next_deqP___1__h318930 : + next_deqP___1__h318931 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h328708 = + assign _theResult_____2__h328709 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649) ? - next_deqP___1__h328987 : + next_deqP___1__h328988 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h331933 = + assign _theResult_____2__h331934 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743) ? - next_deqP___1__h332212 : + next_deqP___1__h332213 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h346084 = - (value__h346706 == 54'd0) ? sfd__h338479 : 57'd1 ; - assign _theResult____h363723 = + assign _theResult____h346085 = + (value__h346707 == 54'd0) ? sfd__h338480 : 57'd1 ; + assign _theResult____h363724 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ^ 12'h800) < 12'd2105) ? - result__h364336 : - _theResult____h346084 ; - assign _theResult____h391783 = - (value__h392403 == 54'd0) ? sfd__h384181 : 57'd1 ; - assign _theResult____h409420 = + result__h364337 : + _theResult____h346085 ; + assign _theResult____h391784 = + (value__h392404 == 54'd0) ? sfd__h384182 : 57'd1 ; + assign _theResult____h409421 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ^ 12'h800) < 12'd2105) ? - result__h410033 : - _theResult____h391783 ; - assign _theResult____h437478 = - (value__h438098 == 54'd0) ? sfd__h429876 : 57'd1 ; - assign _theResult____h455115 = + result__h410034 : + _theResult____h391784 ; + assign _theResult____h437479 = + (value__h438099 == 54'd0) ? sfd__h429877 : 57'd1 ; + assign _theResult____h455116 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ^ 12'h800) < 12'd2105) ? - result__h455728 : - _theResult____h437478 ; - assign _theResult____h502868 = + result__h455729 : + _theResult____h437479 ; + assign _theResult____h502869 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ^ 12'h800) < 12'd2105) ? - result__h503481 : - ((value__h487084 == 25'd0) ? sfd__h482501 : 57'd1) ; - assign _theResult____h541721 = + result__h503482 : + ((value__h487085 == 25'd0) ? sfd__h482502 : 57'd1) ; + assign _theResult____h541722 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ^ 12'h800) < 12'd2105) ? - result__h542334 : - ((value__h525937 == 25'd0) ? sfd__h521495 : 57'd1) ; - assign _theResult____h581025 = + result__h542335 : + ((value__h525938 == 25'd0) ? sfd__h521496 : 57'd1) ; + assign _theResult____h581026 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ^ 12'h800) < 12'd2105) ? - result__h581638 : - ((value__h565241 == 25'd0) ? sfd__h560799 : 57'd1) ; - assign _theResult____h651116 = + result__h581639 : + ((value__h565242 == 25'd0) ? sfd__h560800 : 57'd1) ; + assign _theResult____h651118 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h651641 : + enabled_ints___1__h651643 : 16'd0 ; - assign _theResult___exp__h354711 = - sfd__h354287[24] ? - ((_theResult___fst_exp__h354195 == 8'd254) ? + assign _theResult___exp__h354712 = + sfd__h354288[24] ? + ((_theResult___fst_exp__h354196 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381228) : - ((_theResult___fst_exp__h354195 == 8'd0 && - sfd__h354287[24:23] == 2'b01) ? + din_inc___2_exp__h381229) : + ((_theResult___fst_exp__h354196 == 8'd0 && + sfd__h354288[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h354195) ; - assign _theResult___exp__h363293 = - sfd__h362869[24] ? - ((_theResult___fst_exp__h362851 == 8'd254) ? + _theResult___fst_exp__h354196) ; + assign _theResult___exp__h363294 = + sfd__h362870[24] ? + ((_theResult___fst_exp__h362852 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381252) : - ((_theResult___fst_exp__h362851 == 8'd0 && - sfd__h362869[24:23] == 2'b01) ? + din_inc___2_exp__h381253) : + ((_theResult___fst_exp__h362852 == 8'd0 && + sfd__h362870[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h362851) ; - assign _theResult___exp__h372477 = - sfd__h372053[24] ? - ((_theResult___fst_exp__h371961 == 8'd254) ? + _theResult___fst_exp__h362852) ; + assign _theResult___exp__h372478 = + sfd__h372054[24] ? + ((_theResult___fst_exp__h371962 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381282) : - ((_theResult___fst_exp__h371961 == 8'd0 && - sfd__h372053[24:23] == 2'b01) ? + din_inc___2_exp__h381283) : + ((_theResult___fst_exp__h371962 == 8'd0 && + sfd__h372054[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h371961) ; - assign _theResult___exp__h381113 = - sfd__h380665[24] ? - ((_theResult___fst_exp__h380646 == 8'd254) ? + _theResult___fst_exp__h371962) ; + assign _theResult___exp__h381114 = + sfd__h380666[24] ? + ((_theResult___fst_exp__h380647 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381306) : - ((_theResult___fst_exp__h380646 == 8'd0 && - sfd__h380665[24:23] == 2'b01) ? + din_inc___2_exp__h381307) : + ((_theResult___fst_exp__h380647 == 8'd0 && + sfd__h380666[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h380646) ; - assign _theResult___exp__h381215 = + _theResult___fst_exp__h380647) ; + assign _theResult___exp__h381216 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381206 ; - assign _theResult___exp__h400408 = - sfd__h399984[24] ? - ((_theResult___fst_exp__h399892 == 8'd254) ? + _theResult___fst_exp__h381207 ; + assign _theResult___exp__h400409 = + sfd__h399985[24] ? + ((_theResult___fst_exp__h399893 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426925) : - ((_theResult___fst_exp__h399892 == 8'd0 && - sfd__h399984[24:23] == 2'b01) ? + din_inc___2_exp__h426926) : + ((_theResult___fst_exp__h399893 == 8'd0 && + sfd__h399985[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h399892) ; - assign _theResult___exp__h408990 = - sfd__h408566[24] ? - ((_theResult___fst_exp__h408548 == 8'd254) ? + _theResult___fst_exp__h399893) ; + assign _theResult___exp__h408991 = + sfd__h408567[24] ? + ((_theResult___fst_exp__h408549 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426949) : - ((_theResult___fst_exp__h408548 == 8'd0 && - sfd__h408566[24:23] == 2'b01) ? + din_inc___2_exp__h426950) : + ((_theResult___fst_exp__h408549 == 8'd0 && + sfd__h408567[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h408548) ; - assign _theResult___exp__h418174 = - sfd__h417750[24] ? - ((_theResult___fst_exp__h417658 == 8'd254) ? + _theResult___fst_exp__h408549) ; + assign _theResult___exp__h418175 = + sfd__h417751[24] ? + ((_theResult___fst_exp__h417659 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426979) : - ((_theResult___fst_exp__h417658 == 8'd0 && - sfd__h417750[24:23] == 2'b01) ? + din_inc___2_exp__h426980) : + ((_theResult___fst_exp__h417659 == 8'd0 && + sfd__h417751[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h417658) ; - assign _theResult___exp__h426810 = - sfd__h426362[24] ? - ((_theResult___fst_exp__h426343 == 8'd254) ? + _theResult___fst_exp__h417659) ; + assign _theResult___exp__h426811 = + sfd__h426363[24] ? + ((_theResult___fst_exp__h426344 == 8'd254) ? 8'd255 : - din_inc___2_exp__h427003) : - ((_theResult___fst_exp__h426343 == 8'd0 && - sfd__h426362[24:23] == 2'b01) ? + din_inc___2_exp__h427004) : + ((_theResult___fst_exp__h426344 == 8'd0 && + sfd__h426363[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h426343) ; - assign _theResult___exp__h426912 = + _theResult___fst_exp__h426344) ; + assign _theResult___exp__h426913 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426903 ; - assign _theResult___exp__h446103 = - sfd__h445679[24] ? - ((_theResult___fst_exp__h445587 == 8'd254) ? + _theResult___fst_exp__h426904 ; + assign _theResult___exp__h446104 = + sfd__h445680[24] ? + ((_theResult___fst_exp__h445588 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472620) : - ((_theResult___fst_exp__h445587 == 8'd0 && - sfd__h445679[24:23] == 2'b01) ? + din_inc___2_exp__h472621) : + ((_theResult___fst_exp__h445588 == 8'd0 && + sfd__h445680[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h445587) ; - assign _theResult___exp__h454685 = - sfd__h454261[24] ? - ((_theResult___fst_exp__h454243 == 8'd254) ? + _theResult___fst_exp__h445588) ; + assign _theResult___exp__h454686 = + sfd__h454262[24] ? + ((_theResult___fst_exp__h454244 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472644) : - ((_theResult___fst_exp__h454243 == 8'd0 && - sfd__h454261[24:23] == 2'b01) ? + din_inc___2_exp__h472645) : + ((_theResult___fst_exp__h454244 == 8'd0 && + sfd__h454262[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h454243) ; - assign _theResult___exp__h463869 = - sfd__h463445[24] ? - ((_theResult___fst_exp__h463353 == 8'd254) ? + _theResult___fst_exp__h454244) ; + assign _theResult___exp__h463870 = + sfd__h463446[24] ? + ((_theResult___fst_exp__h463354 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472674) : - ((_theResult___fst_exp__h463353 == 8'd0 && - sfd__h463445[24:23] == 2'b01) ? + din_inc___2_exp__h472675) : + ((_theResult___fst_exp__h463354 == 8'd0 && + sfd__h463446[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h463353) ; - assign _theResult___exp__h472505 = - sfd__h472057[24] ? - ((_theResult___fst_exp__h472038 == 8'd254) ? + _theResult___fst_exp__h463354) ; + assign _theResult___exp__h472506 = + sfd__h472058[24] ? + ((_theResult___fst_exp__h472039 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472698) : - ((_theResult___fst_exp__h472038 == 8'd0 && - sfd__h472057[24:23] == 2'b01) ? + din_inc___2_exp__h472699) : + ((_theResult___fst_exp__h472039 == 8'd0 && + sfd__h472058[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h472038) ; - assign _theResult___exp__h472607 = + _theResult___fst_exp__h472039) ; + assign _theResult___exp__h472608 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472598 ; - assign _theResult___exp__h502182 = - sfd__h501545[53] ? - ((_theResult___fst_exp__h501527 == 11'd2046) ? + _theResult___fst_exp__h472599 ; + assign _theResult___exp__h502183 = + sfd__h501546[53] ? + ((_theResult___fst_exp__h501528 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520777) : - ((_theResult___fst_exp__h501527 == 11'd0 && - sfd__h501545[53:52] == 2'b01) ? + din_inc___2_exp__h520778) : + ((_theResult___fst_exp__h501528 == 11'd0 && + sfd__h501546[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h501527) ; - assign _theResult___exp__h511833 = - sfd__h511196[53] ? - ((_theResult___fst_exp__h511104 == 11'd2046) ? + _theResult___fst_exp__h501528) ; + assign _theResult___exp__h511834 = + sfd__h511197[53] ? + ((_theResult___fst_exp__h511105 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520812) : - ((_theResult___fst_exp__h511104 == 11'd0 && - sfd__h511196[53:52] == 2'b01) ? + din_inc___2_exp__h520813) : + ((_theResult___fst_exp__h511105 == 11'd0 && + sfd__h511197[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h511104) ; - assign _theResult___exp__h520617 = - sfd__h519956[53] ? - ((_theResult___fst_exp__h519937 == 11'd2046) ? + _theResult___fst_exp__h511105) ; + assign _theResult___exp__h520618 = + sfd__h519957[53] ? + ((_theResult___fst_exp__h519938 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520838) : - ((_theResult___fst_exp__h519937 == 11'd0 && - sfd__h519956[53:52] == 2'b01) ? + din_inc___2_exp__h520839) : + ((_theResult___fst_exp__h519938 == 11'd0 && + sfd__h519957[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h519937) ; - assign _theResult___exp__h541035 = - sfd__h540398[53] ? - ((_theResult___fst_exp__h540380 == 11'd2046) ? + _theResult___fst_exp__h519938) ; + assign _theResult___exp__h541036 = + sfd__h540399[53] ? + ((_theResult___fst_exp__h540381 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559630) : - ((_theResult___fst_exp__h540380 == 11'd0 && - sfd__h540398[53:52] == 2'b01) ? + din_inc___2_exp__h559631) : + ((_theResult___fst_exp__h540381 == 11'd0 && + sfd__h540399[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h540380) ; - assign _theResult___exp__h550686 = - sfd__h550049[53] ? - ((_theResult___fst_exp__h549957 == 11'd2046) ? + _theResult___fst_exp__h540381) ; + assign _theResult___exp__h550687 = + sfd__h550050[53] ? + ((_theResult___fst_exp__h549958 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559665) : - ((_theResult___fst_exp__h549957 == 11'd0 && - sfd__h550049[53:52] == 2'b01) ? + din_inc___2_exp__h559666) : + ((_theResult___fst_exp__h549958 == 11'd0 && + sfd__h550050[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h549957) ; - assign _theResult___exp__h559470 = - sfd__h558809[53] ? - ((_theResult___fst_exp__h558790 == 11'd2046) ? + _theResult___fst_exp__h549958) ; + assign _theResult___exp__h559471 = + sfd__h558810[53] ? + ((_theResult___fst_exp__h558791 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559691) : - ((_theResult___fst_exp__h558790 == 11'd0 && - sfd__h558809[53:52] == 2'b01) ? + din_inc___2_exp__h559692) : + ((_theResult___fst_exp__h558791 == 11'd0 && + sfd__h558810[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h558790) ; - assign _theResult___exp__h580339 = - sfd__h579702[53] ? - ((_theResult___fst_exp__h579684 == 11'd2046) ? + _theResult___fst_exp__h558791) ; + assign _theResult___exp__h580340 = + sfd__h579703[53] ? + ((_theResult___fst_exp__h579685 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598934) : - ((_theResult___fst_exp__h579684 == 11'd0 && - sfd__h579702[53:52] == 2'b01) ? + din_inc___2_exp__h598935) : + ((_theResult___fst_exp__h579685 == 11'd0 && + sfd__h579703[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h579684) ; - assign _theResult___exp__h589990 = - sfd__h589353[53] ? - ((_theResult___fst_exp__h589261 == 11'd2046) ? + _theResult___fst_exp__h579685) ; + assign _theResult___exp__h589991 = + sfd__h589354[53] ? + ((_theResult___fst_exp__h589262 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598969) : - ((_theResult___fst_exp__h589261 == 11'd0 && - sfd__h589353[53:52] == 2'b01) ? + din_inc___2_exp__h598970) : + ((_theResult___fst_exp__h589262 == 11'd0 && + sfd__h589354[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h589261) ; - assign _theResult___exp__h598774 = - sfd__h598113[53] ? - ((_theResult___fst_exp__h598094 == 11'd2046) ? + _theResult___fst_exp__h589262) ; + assign _theResult___exp__h598775 = + sfd__h598114[53] ? + ((_theResult___fst_exp__h598095 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598995) : - ((_theResult___fst_exp__h598094 == 11'd0 && - sfd__h598113[53:52] == 2'b01) ? + din_inc___2_exp__h598996) : + ((_theResult___fst_exp__h598095 == 11'd0 && + sfd__h598114[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h598094) ; - assign _theResult___fst__h603369 = - a__h602947[63] ? a___1__h603374 : a__h602947 ; - assign _theResult___fst_exp__h354195 = - _theResult____h346084[56] ? + _theResult___fst_exp__h598095) ; + assign _theResult___fst__h603370 = + a__h602948[63] ? a___1__h603375 : a__h602948 ; + assign _theResult___fst_exp__h354196 = + _theResult____h346085[56] ? 8'd2 : - _theResult___fst_exp__h354269 ; - assign _theResult___fst_exp__h354260 = + _theResult___fst_exp__h354270 ; + assign _theResult___fst_exp__h354261 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ; - assign _theResult___fst_exp__h354266 = - (!_theResult____h346084[56] && !_theResult____h346084[55] && - !_theResult____h346084[54] && - !_theResult____h346084[53] && - !_theResult____h346084[52] && - !_theResult____h346084[51] && - !_theResult____h346084[50] && - !_theResult____h346084[49] && - !_theResult____h346084[48] && - !_theResult____h346084[47] && - !_theResult____h346084[46] && - !_theResult____h346084[45] && - !_theResult____h346084[44] && - !_theResult____h346084[43] && - !_theResult____h346084[42] && - !_theResult____h346084[41] && - !_theResult____h346084[40] && - !_theResult____h346084[39] && - !_theResult____h346084[38] && - !_theResult____h346084[37] && - !_theResult____h346084[36] && - !_theResult____h346084[35] && - !_theResult____h346084[34] && - !_theResult____h346084[33] && - !_theResult____h346084[32] && - !_theResult____h346084[31] && - !_theResult____h346084[30] && - !_theResult____h346084[29] && - !_theResult____h346084[28] && - !_theResult____h346084[27] && - !_theResult____h346084[26] && - !_theResult____h346084[25] && - !_theResult____h346084[24] && - !_theResult____h346084[23] && - !_theResult____h346084[22] && - !_theResult____h346084[21] && - !_theResult____h346084[20] && - !_theResult____h346084[19] && - !_theResult____h346084[18] && - !_theResult____h346084[17] && - !_theResult____h346084[16] && - !_theResult____h346084[15] && - !_theResult____h346084[14] && - !_theResult____h346084[13] && - !_theResult____h346084[12] && - !_theResult____h346084[11] && - !_theResult____h346084[10] && - !_theResult____h346084[9] && - !_theResult____h346084[8] && - !_theResult____h346084[7] && - !_theResult____h346084[6] && - !_theResult____h346084[5] && - !_theResult____h346084[4] && - !_theResult____h346084[3] && - !_theResult____h346084[2] && - !_theResult____h346084[1] && - !_theResult____h346084[0] || + assign _theResult___fst_exp__h354267 = + (!_theResult____h346085[56] && !_theResult____h346085[55] && + !_theResult____h346085[54] && + !_theResult____h346085[53] && + !_theResult____h346085[52] && + !_theResult____h346085[51] && + !_theResult____h346085[50] && + !_theResult____h346085[49] && + !_theResult____h346085[48] && + !_theResult____h346085[47] && + !_theResult____h346085[46] && + !_theResult____h346085[45] && + !_theResult____h346085[44] && + !_theResult____h346085[43] && + !_theResult____h346085[42] && + !_theResult____h346085[41] && + !_theResult____h346085[40] && + !_theResult____h346085[39] && + !_theResult____h346085[38] && + !_theResult____h346085[37] && + !_theResult____h346085[36] && + !_theResult____h346085[35] && + !_theResult____h346085[34] && + !_theResult____h346085[33] && + !_theResult____h346085[32] && + !_theResult____h346085[31] && + !_theResult____h346085[30] && + !_theResult____h346085[29] && + !_theResult____h346085[28] && + !_theResult____h346085[27] && + !_theResult____h346085[26] && + !_theResult____h346085[25] && + !_theResult____h346085[24] && + !_theResult____h346085[23] && + !_theResult____h346085[22] && + !_theResult____h346085[21] && + !_theResult____h346085[20] && + !_theResult____h346085[19] && + !_theResult____h346085[18] && + !_theResult____h346085[17] && + !_theResult____h346085[16] && + !_theResult____h346085[15] && + !_theResult____h346085[14] && + !_theResult____h346085[13] && + !_theResult____h346085[12] && + !_theResult____h346085[11] && + !_theResult____h346085[10] && + !_theResult____h346085[9] && + !_theResult____h346085[8] && + !_theResult____h346085[7] && + !_theResult____h346085[6] && + !_theResult____h346085[5] && + !_theResult____h346085[4] && + !_theResult____h346085[3] && + !_theResult____h346085[2] && + !_theResult____h346085[1] && + !_theResult____h346085[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249) ? 8'd0 : - _theResult___fst_exp__h354260 ; - assign _theResult___fst_exp__h354269 = - (!_theResult____h346084[56] && _theResult____h346084[55]) ? + _theResult___fst_exp__h354261 ; + assign _theResult___fst_exp__h354270 = + (!_theResult____h346085[56] && _theResult____h346085[55]) ? 8'd1 : - _theResult___fst_exp__h354266 ; - assign _theResult___fst_exp__h354792 = - (_theResult___fst_exp__h354195 == 8'd255) ? - _theResult___fst_exp__h354195 : - _theResult___fst_exp__h354789 ; - assign _theResult___fst_exp__h362842 = + _theResult___fst_exp__h354267 ; + assign _theResult___fst_exp__h354793 = + (_theResult___fst_exp__h354196 == 8'd255) ? + _theResult___fst_exp__h354196 : + _theResult___fst_exp__h354790 ; + assign _theResult___fst_exp__h362843 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h362848 = + assign _theResult___fst_exp__h362849 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480) ? 8'd0 : - _theResult___fst_exp__h362842 ; - assign _theResult___fst_exp__h362851 = + _theResult___fst_exp__h362843 ; + assign _theResult___fst_exp__h362852 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h362848 : + _theResult___fst_exp__h362849 : 8'd129 ; - assign _theResult___fst_exp__h363374 = - (_theResult___fst_exp__h362851 == 8'd255) ? - _theResult___fst_exp__h362851 : - _theResult___fst_exp__h363371 ; - assign _theResult___fst_exp__h371961 = - _theResult____h363723[56] ? + assign _theResult___fst_exp__h363375 = + (_theResult___fst_exp__h362852 == 8'd255) ? + _theResult___fst_exp__h362852 : + _theResult___fst_exp__h363372 ; + assign _theResult___fst_exp__h371962 = + _theResult____h363724[56] ? 8'd2 : - _theResult___fst_exp__h372035 ; - assign _theResult___fst_exp__h372026 = + _theResult___fst_exp__h372036 ; + assign _theResult___fst_exp__h372027 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ; - assign _theResult___fst_exp__h372032 = - (!_theResult____h363723[56] && !_theResult____h363723[55] && - !_theResult____h363723[54] && - !_theResult____h363723[53] && - !_theResult____h363723[52] && - !_theResult____h363723[51] && - !_theResult____h363723[50] && - !_theResult____h363723[49] && - !_theResult____h363723[48] && - !_theResult____h363723[47] && - !_theResult____h363723[46] && - !_theResult____h363723[45] && - !_theResult____h363723[44] && - !_theResult____h363723[43] && - !_theResult____h363723[42] && - !_theResult____h363723[41] && - !_theResult____h363723[40] && - !_theResult____h363723[39] && - !_theResult____h363723[38] && - !_theResult____h363723[37] && - !_theResult____h363723[36] && - !_theResult____h363723[35] && - !_theResult____h363723[34] && - !_theResult____h363723[33] && - !_theResult____h363723[32] && - !_theResult____h363723[31] && - !_theResult____h363723[30] && - !_theResult____h363723[29] && - !_theResult____h363723[28] && - !_theResult____h363723[27] && - !_theResult____h363723[26] && - !_theResult____h363723[25] && - !_theResult____h363723[24] && - !_theResult____h363723[23] && - !_theResult____h363723[22] && - !_theResult____h363723[21] && - !_theResult____h363723[20] && - !_theResult____h363723[19] && - !_theResult____h363723[18] && - !_theResult____h363723[17] && - !_theResult____h363723[16] && - !_theResult____h363723[15] && - !_theResult____h363723[14] && - !_theResult____h363723[13] && - !_theResult____h363723[12] && - !_theResult____h363723[11] && - !_theResult____h363723[10] && - !_theResult____h363723[9] && - !_theResult____h363723[8] && - !_theResult____h363723[7] && - !_theResult____h363723[6] && - !_theResult____h363723[5] && - !_theResult____h363723[4] && - !_theResult____h363723[3] && - !_theResult____h363723[2] && - !_theResult____h363723[1] && - !_theResult____h363723[0] || + assign _theResult___fst_exp__h372033 = + (!_theResult____h363724[56] && !_theResult____h363724[55] && + !_theResult____h363724[54] && + !_theResult____h363724[53] && + !_theResult____h363724[52] && + !_theResult____h363724[51] && + !_theResult____h363724[50] && + !_theResult____h363724[49] && + !_theResult____h363724[48] && + !_theResult____h363724[47] && + !_theResult____h363724[46] && + !_theResult____h363724[45] && + !_theResult____h363724[44] && + !_theResult____h363724[43] && + !_theResult____h363724[42] && + !_theResult____h363724[41] && + !_theResult____h363724[40] && + !_theResult____h363724[39] && + !_theResult____h363724[38] && + !_theResult____h363724[37] && + !_theResult____h363724[36] && + !_theResult____h363724[35] && + !_theResult____h363724[34] && + !_theResult____h363724[33] && + !_theResult____h363724[32] && + !_theResult____h363724[31] && + !_theResult____h363724[30] && + !_theResult____h363724[29] && + !_theResult____h363724[28] && + !_theResult____h363724[27] && + !_theResult____h363724[26] && + !_theResult____h363724[25] && + !_theResult____h363724[24] && + !_theResult____h363724[23] && + !_theResult____h363724[22] && + !_theResult____h363724[21] && + !_theResult____h363724[20] && + !_theResult____h363724[19] && + !_theResult____h363724[18] && + !_theResult____h363724[17] && + !_theResult____h363724[16] && + !_theResult____h363724[15] && + !_theResult____h363724[14] && + !_theResult____h363724[13] && + !_theResult____h363724[12] && + !_theResult____h363724[11] && + !_theResult____h363724[10] && + !_theResult____h363724[9] && + !_theResult____h363724[8] && + !_theResult____h363724[7] && + !_theResult____h363724[6] && + !_theResult____h363724[5] && + !_theResult____h363724[4] && + !_theResult____h363724[3] && + !_theResult____h363724[2] && + !_theResult____h363724[1] && + !_theResult____h363724[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800) ? 8'd0 : - _theResult___fst_exp__h372026 ; - assign _theResult___fst_exp__h372035 = - (!_theResult____h363723[56] && _theResult____h363723[55]) ? + _theResult___fst_exp__h372027 ; + assign _theResult___fst_exp__h372036 = + (!_theResult____h363724[56] && _theResult____h363724[55]) ? 8'd1 : - _theResult___fst_exp__h372032 ; - assign _theResult___fst_exp__h372558 = - (_theResult___fst_exp__h371961 == 8'd255) ? - _theResult___fst_exp__h371961 : - _theResult___fst_exp__h372555 ; - assign _theResult___fst_exp__h380598 = + _theResult___fst_exp__h372033 ; + assign _theResult___fst_exp__h372559 = + (_theResult___fst_exp__h371962 == 8'd255) ? + _theResult___fst_exp__h371962 : + _theResult___fst_exp__h372556 ; + assign _theResult___fst_exp__h380599 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ; - assign _theResult___fst_exp__h380637 = + assign _theResult___fst_exp__h380638 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h380643 = + assign _theResult___fst_exp__h380644 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873) ? 8'd0 : - _theResult___fst_exp__h380637 ; - assign _theResult___fst_exp__h380646 = + _theResult___fst_exp__h380638 ; + assign _theResult___fst_exp__h380647 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h380643 : - _theResult___fst_exp__h380598 ; - assign _theResult___fst_exp__h381194 = - (_theResult___fst_exp__h380646 == 8'd255) ? - _theResult___fst_exp__h380646 : - _theResult___fst_exp__h381191 ; - assign _theResult___fst_exp__h381203 = + _theResult___fst_exp__h380644 : + _theResult___fst_exp__h380599 ; + assign _theResult___fst_exp__h381195 = + (_theResult___fst_exp__h380647 == 8'd255) ? + _theResult___fst_exp__h380647 : + _theResult___fst_exp__h381192 ; + assign _theResult___fst_exp__h381204 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_exp__h363377 : - _theResult___fst_exp__h346066) : + _theResult___snd_fst_exp__h363378 : + _theResult___fst_exp__h346067) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_exp__h381197 : - _theResult___fst_exp__h346066) ; - assign _theResult___fst_exp__h381206 = + _theResult___snd_fst_exp__h381198 : + _theResult___fst_exp__h346067) ; + assign _theResult___fst_exp__h381207 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h381203 ; - assign _theResult___fst_exp__h399892 = - _theResult____h391783[56] ? + _theResult___fst_exp__h381204 ; + assign _theResult___fst_exp__h399893 = + _theResult____h391784[56] ? 8'd2 : - _theResult___fst_exp__h399966 ; - assign _theResult___fst_exp__h399957 = + _theResult___fst_exp__h399967 ; + assign _theResult___fst_exp__h399958 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ; - assign _theResult___fst_exp__h399963 = - (!_theResult____h391783[56] && !_theResult____h391783[55] && - !_theResult____h391783[54] && - !_theResult____h391783[53] && - !_theResult____h391783[52] && - !_theResult____h391783[51] && - !_theResult____h391783[50] && - !_theResult____h391783[49] && - !_theResult____h391783[48] && - !_theResult____h391783[47] && - !_theResult____h391783[46] && - !_theResult____h391783[45] && - !_theResult____h391783[44] && - !_theResult____h391783[43] && - !_theResult____h391783[42] && - !_theResult____h391783[41] && - !_theResult____h391783[40] && - !_theResult____h391783[39] && - !_theResult____h391783[38] && - !_theResult____h391783[37] && - !_theResult____h391783[36] && - !_theResult____h391783[35] && - !_theResult____h391783[34] && - !_theResult____h391783[33] && - !_theResult____h391783[32] && - !_theResult____h391783[31] && - !_theResult____h391783[30] && - !_theResult____h391783[29] && - !_theResult____h391783[28] && - !_theResult____h391783[27] && - !_theResult____h391783[26] && - !_theResult____h391783[25] && - !_theResult____h391783[24] && - !_theResult____h391783[23] && - !_theResult____h391783[22] && - !_theResult____h391783[21] && - !_theResult____h391783[20] && - !_theResult____h391783[19] && - !_theResult____h391783[18] && - !_theResult____h391783[17] && - !_theResult____h391783[16] && - !_theResult____h391783[15] && - !_theResult____h391783[14] && - !_theResult____h391783[13] && - !_theResult____h391783[12] && - !_theResult____h391783[11] && - !_theResult____h391783[10] && - !_theResult____h391783[9] && - !_theResult____h391783[8] && - !_theResult____h391783[7] && - !_theResult____h391783[6] && - !_theResult____h391783[5] && - !_theResult____h391783[4] && - !_theResult____h391783[3] && - !_theResult____h391783[2] && - !_theResult____h391783[1] && - !_theResult____h391783[0] || + assign _theResult___fst_exp__h399964 = + (!_theResult____h391784[56] && !_theResult____h391784[55] && + !_theResult____h391784[54] && + !_theResult____h391784[53] && + !_theResult____h391784[52] && + !_theResult____h391784[51] && + !_theResult____h391784[50] && + !_theResult____h391784[49] && + !_theResult____h391784[48] && + !_theResult____h391784[47] && + !_theResult____h391784[46] && + !_theResult____h391784[45] && + !_theResult____h391784[44] && + !_theResult____h391784[43] && + !_theResult____h391784[42] && + !_theResult____h391784[41] && + !_theResult____h391784[40] && + !_theResult____h391784[39] && + !_theResult____h391784[38] && + !_theResult____h391784[37] && + !_theResult____h391784[36] && + !_theResult____h391784[35] && + !_theResult____h391784[34] && + !_theResult____h391784[33] && + !_theResult____h391784[32] && + !_theResult____h391784[31] && + !_theResult____h391784[30] && + !_theResult____h391784[29] && + !_theResult____h391784[28] && + !_theResult____h391784[27] && + !_theResult____h391784[26] && + !_theResult____h391784[25] && + !_theResult____h391784[24] && + !_theResult____h391784[23] && + !_theResult____h391784[22] && + !_theResult____h391784[21] && + !_theResult____h391784[20] && + !_theResult____h391784[19] && + !_theResult____h391784[18] && + !_theResult____h391784[17] && + !_theResult____h391784[16] && + !_theResult____h391784[15] && + !_theResult____h391784[14] && + !_theResult____h391784[13] && + !_theResult____h391784[12] && + !_theResult____h391784[11] && + !_theResult____h391784[10] && + !_theResult____h391784[9] && + !_theResult____h391784[8] && + !_theResult____h391784[7] && + !_theResult____h391784[6] && + !_theResult____h391784[5] && + !_theResult____h391784[4] && + !_theResult____h391784[3] && + !_theResult____h391784[2] && + !_theResult____h391784[1] && + !_theResult____h391784[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641) ? 8'd0 : - _theResult___fst_exp__h399957 ; - assign _theResult___fst_exp__h399966 = - (!_theResult____h391783[56] && _theResult____h391783[55]) ? + _theResult___fst_exp__h399958 ; + assign _theResult___fst_exp__h399967 = + (!_theResult____h391784[56] && _theResult____h391784[55]) ? 8'd1 : - _theResult___fst_exp__h399963 ; - assign _theResult___fst_exp__h400489 = - (_theResult___fst_exp__h399892 == 8'd255) ? - _theResult___fst_exp__h399892 : - _theResult___fst_exp__h400486 ; - assign _theResult___fst_exp__h408539 = + _theResult___fst_exp__h399964 ; + assign _theResult___fst_exp__h400490 = + (_theResult___fst_exp__h399893 == 8'd255) ? + _theResult___fst_exp__h399893 : + _theResult___fst_exp__h400487 ; + assign _theResult___fst_exp__h408540 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h408545 = + assign _theResult___fst_exp__h408546 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872) ? 8'd0 : - _theResult___fst_exp__h408539 ; - assign _theResult___fst_exp__h408548 = + _theResult___fst_exp__h408540 ; + assign _theResult___fst_exp__h408549 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h408545 : + _theResult___fst_exp__h408546 : 8'd129 ; - assign _theResult___fst_exp__h409071 = - (_theResult___fst_exp__h408548 == 8'd255) ? - _theResult___fst_exp__h408548 : - _theResult___fst_exp__h409068 ; - assign _theResult___fst_exp__h417658 = - _theResult____h409420[56] ? + assign _theResult___fst_exp__h409072 = + (_theResult___fst_exp__h408549 == 8'd255) ? + _theResult___fst_exp__h408549 : + _theResult___fst_exp__h409069 ; + assign _theResult___fst_exp__h417659 = + _theResult____h409421[56] ? 8'd2 : - _theResult___fst_exp__h417732 ; - assign _theResult___fst_exp__h417723 = + _theResult___fst_exp__h417733 ; + assign _theResult___fst_exp__h417724 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ; - assign _theResult___fst_exp__h417729 = - (!_theResult____h409420[56] && !_theResult____h409420[55] && - !_theResult____h409420[54] && - !_theResult____h409420[53] && - !_theResult____h409420[52] && - !_theResult____h409420[51] && - !_theResult____h409420[50] && - !_theResult____h409420[49] && - !_theResult____h409420[48] && - !_theResult____h409420[47] && - !_theResult____h409420[46] && - !_theResult____h409420[45] && - !_theResult____h409420[44] && - !_theResult____h409420[43] && - !_theResult____h409420[42] && - !_theResult____h409420[41] && - !_theResult____h409420[40] && - !_theResult____h409420[39] && - !_theResult____h409420[38] && - !_theResult____h409420[37] && - !_theResult____h409420[36] && - !_theResult____h409420[35] && - !_theResult____h409420[34] && - !_theResult____h409420[33] && - !_theResult____h409420[32] && - !_theResult____h409420[31] && - !_theResult____h409420[30] && - !_theResult____h409420[29] && - !_theResult____h409420[28] && - !_theResult____h409420[27] && - !_theResult____h409420[26] && - !_theResult____h409420[25] && - !_theResult____h409420[24] && - !_theResult____h409420[23] && - !_theResult____h409420[22] && - !_theResult____h409420[21] && - !_theResult____h409420[20] && - !_theResult____h409420[19] && - !_theResult____h409420[18] && - !_theResult____h409420[17] && - !_theResult____h409420[16] && - !_theResult____h409420[15] && - !_theResult____h409420[14] && - !_theResult____h409420[13] && - !_theResult____h409420[12] && - !_theResult____h409420[11] && - !_theResult____h409420[10] && - !_theResult____h409420[9] && - !_theResult____h409420[8] && - !_theResult____h409420[7] && - !_theResult____h409420[6] && - !_theResult____h409420[5] && - !_theResult____h409420[4] && - !_theResult____h409420[3] && - !_theResult____h409420[2] && - !_theResult____h409420[1] && - !_theResult____h409420[0] || + assign _theResult___fst_exp__h417730 = + (!_theResult____h409421[56] && !_theResult____h409421[55] && + !_theResult____h409421[54] && + !_theResult____h409421[53] && + !_theResult____h409421[52] && + !_theResult____h409421[51] && + !_theResult____h409421[50] && + !_theResult____h409421[49] && + !_theResult____h409421[48] && + !_theResult____h409421[47] && + !_theResult____h409421[46] && + !_theResult____h409421[45] && + !_theResult____h409421[44] && + !_theResult____h409421[43] && + !_theResult____h409421[42] && + !_theResult____h409421[41] && + !_theResult____h409421[40] && + !_theResult____h409421[39] && + !_theResult____h409421[38] && + !_theResult____h409421[37] && + !_theResult____h409421[36] && + !_theResult____h409421[35] && + !_theResult____h409421[34] && + !_theResult____h409421[33] && + !_theResult____h409421[32] && + !_theResult____h409421[31] && + !_theResult____h409421[30] && + !_theResult____h409421[29] && + !_theResult____h409421[28] && + !_theResult____h409421[27] && + !_theResult____h409421[26] && + !_theResult____h409421[25] && + !_theResult____h409421[24] && + !_theResult____h409421[23] && + !_theResult____h409421[22] && + !_theResult____h409421[21] && + !_theResult____h409421[20] && + !_theResult____h409421[19] && + !_theResult____h409421[18] && + !_theResult____h409421[17] && + !_theResult____h409421[16] && + !_theResult____h409421[15] && + !_theResult____h409421[14] && + !_theResult____h409421[13] && + !_theResult____h409421[12] && + !_theResult____h409421[11] && + !_theResult____h409421[10] && + !_theResult____h409421[9] && + !_theResult____h409421[8] && + !_theResult____h409421[7] && + !_theResult____h409421[6] && + !_theResult____h409421[5] && + !_theResult____h409421[4] && + !_theResult____h409421[3] && + !_theResult____h409421[2] && + !_theResult____h409421[1] && + !_theResult____h409421[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192) ? 8'd0 : - _theResult___fst_exp__h417723 ; - assign _theResult___fst_exp__h417732 = - (!_theResult____h409420[56] && _theResult____h409420[55]) ? + _theResult___fst_exp__h417724 ; + assign _theResult___fst_exp__h417733 = + (!_theResult____h409421[56] && _theResult____h409421[55]) ? 8'd1 : - _theResult___fst_exp__h417729 ; - assign _theResult___fst_exp__h418255 = - (_theResult___fst_exp__h417658 == 8'd255) ? - _theResult___fst_exp__h417658 : - _theResult___fst_exp__h418252 ; - assign _theResult___fst_exp__h426295 = + _theResult___fst_exp__h417730 ; + assign _theResult___fst_exp__h418256 = + (_theResult___fst_exp__h417659 == 8'd255) ? + _theResult___fst_exp__h417659 : + _theResult___fst_exp__h418253 ; + assign _theResult___fst_exp__h426296 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ; - assign _theResult___fst_exp__h426334 = + assign _theResult___fst_exp__h426335 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h426340 = + assign _theResult___fst_exp__h426341 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265) ? 8'd0 : - _theResult___fst_exp__h426334 ; - assign _theResult___fst_exp__h426343 = + _theResult___fst_exp__h426335 ; + assign _theResult___fst_exp__h426344 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h426340 : - _theResult___fst_exp__h426295 ; - assign _theResult___fst_exp__h426891 = - (_theResult___fst_exp__h426343 == 8'd255) ? - _theResult___fst_exp__h426343 : - _theResult___fst_exp__h426888 ; - assign _theResult___fst_exp__h426900 = + _theResult___fst_exp__h426341 : + _theResult___fst_exp__h426296 ; + assign _theResult___fst_exp__h426892 = + (_theResult___fst_exp__h426344 == 8'd255) ? + _theResult___fst_exp__h426344 : + _theResult___fst_exp__h426889 ; + assign _theResult___fst_exp__h426901 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_exp__h409074 : - _theResult___fst_exp__h391765) : + _theResult___snd_fst_exp__h409075 : + _theResult___fst_exp__h391766) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_exp__h426894 : - _theResult___fst_exp__h391765) ; - assign _theResult___fst_exp__h426903 = + _theResult___snd_fst_exp__h426895 : + _theResult___fst_exp__h391766) ; + assign _theResult___fst_exp__h426904 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h426900 ; - assign _theResult___fst_exp__h445587 = - _theResult____h437478[56] ? + _theResult___fst_exp__h426901 ; + assign _theResult___fst_exp__h445588 = + _theResult____h437479[56] ? 8'd2 : - _theResult___fst_exp__h445661 ; - assign _theResult___fst_exp__h445652 = + _theResult___fst_exp__h445662 ; + assign _theResult___fst_exp__h445653 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ; - assign _theResult___fst_exp__h445658 = - (!_theResult____h437478[56] && !_theResult____h437478[55] && - !_theResult____h437478[54] && - !_theResult____h437478[53] && - !_theResult____h437478[52] && - !_theResult____h437478[51] && - !_theResult____h437478[50] && - !_theResult____h437478[49] && - !_theResult____h437478[48] && - !_theResult____h437478[47] && - !_theResult____h437478[46] && - !_theResult____h437478[45] && - !_theResult____h437478[44] && - !_theResult____h437478[43] && - !_theResult____h437478[42] && - !_theResult____h437478[41] && - !_theResult____h437478[40] && - !_theResult____h437478[39] && - !_theResult____h437478[38] && - !_theResult____h437478[37] && - !_theResult____h437478[36] && - !_theResult____h437478[35] && - !_theResult____h437478[34] && - !_theResult____h437478[33] && - !_theResult____h437478[32] && - !_theResult____h437478[31] && - !_theResult____h437478[30] && - !_theResult____h437478[29] && - !_theResult____h437478[28] && - !_theResult____h437478[27] && - !_theResult____h437478[26] && - !_theResult____h437478[25] && - !_theResult____h437478[24] && - !_theResult____h437478[23] && - !_theResult____h437478[22] && - !_theResult____h437478[21] && - !_theResult____h437478[20] && - !_theResult____h437478[19] && - !_theResult____h437478[18] && - !_theResult____h437478[17] && - !_theResult____h437478[16] && - !_theResult____h437478[15] && - !_theResult____h437478[14] && - !_theResult____h437478[13] && - !_theResult____h437478[12] && - !_theResult____h437478[11] && - !_theResult____h437478[10] && - !_theResult____h437478[9] && - !_theResult____h437478[8] && - !_theResult____h437478[7] && - !_theResult____h437478[6] && - !_theResult____h437478[5] && - !_theResult____h437478[4] && - !_theResult____h437478[3] && - !_theResult____h437478[2] && - !_theResult____h437478[1] && - !_theResult____h437478[0] || + assign _theResult___fst_exp__h445659 = + (!_theResult____h437479[56] && !_theResult____h437479[55] && + !_theResult____h437479[54] && + !_theResult____h437479[53] && + !_theResult____h437479[52] && + !_theResult____h437479[51] && + !_theResult____h437479[50] && + !_theResult____h437479[49] && + !_theResult____h437479[48] && + !_theResult____h437479[47] && + !_theResult____h437479[46] && + !_theResult____h437479[45] && + !_theResult____h437479[44] && + !_theResult____h437479[43] && + !_theResult____h437479[42] && + !_theResult____h437479[41] && + !_theResult____h437479[40] && + !_theResult____h437479[39] && + !_theResult____h437479[38] && + !_theResult____h437479[37] && + !_theResult____h437479[36] && + !_theResult____h437479[35] && + !_theResult____h437479[34] && + !_theResult____h437479[33] && + !_theResult____h437479[32] && + !_theResult____h437479[31] && + !_theResult____h437479[30] && + !_theResult____h437479[29] && + !_theResult____h437479[28] && + !_theResult____h437479[27] && + !_theResult____h437479[26] && + !_theResult____h437479[25] && + !_theResult____h437479[24] && + !_theResult____h437479[23] && + !_theResult____h437479[22] && + !_theResult____h437479[21] && + !_theResult____h437479[20] && + !_theResult____h437479[19] && + !_theResult____h437479[18] && + !_theResult____h437479[17] && + !_theResult____h437479[16] && + !_theResult____h437479[15] && + !_theResult____h437479[14] && + !_theResult____h437479[13] && + !_theResult____h437479[12] && + !_theResult____h437479[11] && + !_theResult____h437479[10] && + !_theResult____h437479[9] && + !_theResult____h437479[8] && + !_theResult____h437479[7] && + !_theResult____h437479[6] && + !_theResult____h437479[5] && + !_theResult____h437479[4] && + !_theResult____h437479[3] && + !_theResult____h437479[2] && + !_theResult____h437479[1] && + !_theResult____h437479[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033) ? 8'd0 : - _theResult___fst_exp__h445652 ; - assign _theResult___fst_exp__h445661 = - (!_theResult____h437478[56] && _theResult____h437478[55]) ? + _theResult___fst_exp__h445653 ; + assign _theResult___fst_exp__h445662 = + (!_theResult____h437479[56] && _theResult____h437479[55]) ? 8'd1 : - _theResult___fst_exp__h445658 ; - assign _theResult___fst_exp__h446184 = - (_theResult___fst_exp__h445587 == 8'd255) ? - _theResult___fst_exp__h445587 : - _theResult___fst_exp__h446181 ; - assign _theResult___fst_exp__h454234 = + _theResult___fst_exp__h445659 ; + assign _theResult___fst_exp__h446185 = + (_theResult___fst_exp__h445588 == 8'd255) ? + _theResult___fst_exp__h445588 : + _theResult___fst_exp__h446182 ; + assign _theResult___fst_exp__h454235 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h454240 = + assign _theResult___fst_exp__h454241 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264) ? 8'd0 : - _theResult___fst_exp__h454234 ; - assign _theResult___fst_exp__h454243 = + _theResult___fst_exp__h454235 ; + assign _theResult___fst_exp__h454244 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h454240 : + _theResult___fst_exp__h454241 : 8'd129 ; - assign _theResult___fst_exp__h454766 = - (_theResult___fst_exp__h454243 == 8'd255) ? - _theResult___fst_exp__h454243 : - _theResult___fst_exp__h454763 ; - assign _theResult___fst_exp__h463353 = - _theResult____h455115[56] ? + assign _theResult___fst_exp__h454767 = + (_theResult___fst_exp__h454244 == 8'd255) ? + _theResult___fst_exp__h454244 : + _theResult___fst_exp__h454764 ; + assign _theResult___fst_exp__h463354 = + _theResult____h455116[56] ? 8'd2 : - _theResult___fst_exp__h463427 ; - assign _theResult___fst_exp__h463418 = + _theResult___fst_exp__h463428 ; + assign _theResult___fst_exp__h463419 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ; - assign _theResult___fst_exp__h463424 = - (!_theResult____h455115[56] && !_theResult____h455115[55] && - !_theResult____h455115[54] && - !_theResult____h455115[53] && - !_theResult____h455115[52] && - !_theResult____h455115[51] && - !_theResult____h455115[50] && - !_theResult____h455115[49] && - !_theResult____h455115[48] && - !_theResult____h455115[47] && - !_theResult____h455115[46] && - !_theResult____h455115[45] && - !_theResult____h455115[44] && - !_theResult____h455115[43] && - !_theResult____h455115[42] && - !_theResult____h455115[41] && - !_theResult____h455115[40] && - !_theResult____h455115[39] && - !_theResult____h455115[38] && - !_theResult____h455115[37] && - !_theResult____h455115[36] && - !_theResult____h455115[35] && - !_theResult____h455115[34] && - !_theResult____h455115[33] && - !_theResult____h455115[32] && - !_theResult____h455115[31] && - !_theResult____h455115[30] && - !_theResult____h455115[29] && - !_theResult____h455115[28] && - !_theResult____h455115[27] && - !_theResult____h455115[26] && - !_theResult____h455115[25] && - !_theResult____h455115[24] && - !_theResult____h455115[23] && - !_theResult____h455115[22] && - !_theResult____h455115[21] && - !_theResult____h455115[20] && - !_theResult____h455115[19] && - !_theResult____h455115[18] && - !_theResult____h455115[17] && - !_theResult____h455115[16] && - !_theResult____h455115[15] && - !_theResult____h455115[14] && - !_theResult____h455115[13] && - !_theResult____h455115[12] && - !_theResult____h455115[11] && - !_theResult____h455115[10] && - !_theResult____h455115[9] && - !_theResult____h455115[8] && - !_theResult____h455115[7] && - !_theResult____h455115[6] && - !_theResult____h455115[5] && - !_theResult____h455115[4] && - !_theResult____h455115[3] && - !_theResult____h455115[2] && - !_theResult____h455115[1] && - !_theResult____h455115[0] || + assign _theResult___fst_exp__h463425 = + (!_theResult____h455116[56] && !_theResult____h455116[55] && + !_theResult____h455116[54] && + !_theResult____h455116[53] && + !_theResult____h455116[52] && + !_theResult____h455116[51] && + !_theResult____h455116[50] && + !_theResult____h455116[49] && + !_theResult____h455116[48] && + !_theResult____h455116[47] && + !_theResult____h455116[46] && + !_theResult____h455116[45] && + !_theResult____h455116[44] && + !_theResult____h455116[43] && + !_theResult____h455116[42] && + !_theResult____h455116[41] && + !_theResult____h455116[40] && + !_theResult____h455116[39] && + !_theResult____h455116[38] && + !_theResult____h455116[37] && + !_theResult____h455116[36] && + !_theResult____h455116[35] && + !_theResult____h455116[34] && + !_theResult____h455116[33] && + !_theResult____h455116[32] && + !_theResult____h455116[31] && + !_theResult____h455116[30] && + !_theResult____h455116[29] && + !_theResult____h455116[28] && + !_theResult____h455116[27] && + !_theResult____h455116[26] && + !_theResult____h455116[25] && + !_theResult____h455116[24] && + !_theResult____h455116[23] && + !_theResult____h455116[22] && + !_theResult____h455116[21] && + !_theResult____h455116[20] && + !_theResult____h455116[19] && + !_theResult____h455116[18] && + !_theResult____h455116[17] && + !_theResult____h455116[16] && + !_theResult____h455116[15] && + !_theResult____h455116[14] && + !_theResult____h455116[13] && + !_theResult____h455116[12] && + !_theResult____h455116[11] && + !_theResult____h455116[10] && + !_theResult____h455116[9] && + !_theResult____h455116[8] && + !_theResult____h455116[7] && + !_theResult____h455116[6] && + !_theResult____h455116[5] && + !_theResult____h455116[4] && + !_theResult____h455116[3] && + !_theResult____h455116[2] && + !_theResult____h455116[1] && + !_theResult____h455116[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584) ? 8'd0 : - _theResult___fst_exp__h463418 ; - assign _theResult___fst_exp__h463427 = - (!_theResult____h455115[56] && _theResult____h455115[55]) ? + _theResult___fst_exp__h463419 ; + assign _theResult___fst_exp__h463428 = + (!_theResult____h455116[56] && _theResult____h455116[55]) ? 8'd1 : - _theResult___fst_exp__h463424 ; - assign _theResult___fst_exp__h463950 = - (_theResult___fst_exp__h463353 == 8'd255) ? - _theResult___fst_exp__h463353 : - _theResult___fst_exp__h463947 ; - assign _theResult___fst_exp__h471990 = + _theResult___fst_exp__h463425 ; + assign _theResult___fst_exp__h463951 = + (_theResult___fst_exp__h463354 == 8'd255) ? + _theResult___fst_exp__h463354 : + _theResult___fst_exp__h463948 ; + assign _theResult___fst_exp__h471991 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ; - assign _theResult___fst_exp__h472029 = + assign _theResult___fst_exp__h472030 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h472035 = + assign _theResult___fst_exp__h472036 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657) ? 8'd0 : - _theResult___fst_exp__h472029 ; - assign _theResult___fst_exp__h472038 = + _theResult___fst_exp__h472030 ; + assign _theResult___fst_exp__h472039 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h472035 : - _theResult___fst_exp__h471990 ; - assign _theResult___fst_exp__h472586 = - (_theResult___fst_exp__h472038 == 8'd255) ? - _theResult___fst_exp__h472038 : - _theResult___fst_exp__h472583 ; - assign _theResult___fst_exp__h472595 = + _theResult___fst_exp__h472036 : + _theResult___fst_exp__h471991 ; + assign _theResult___fst_exp__h472587 = + (_theResult___fst_exp__h472039 == 8'd255) ? + _theResult___fst_exp__h472039 : + _theResult___fst_exp__h472584 ; + assign _theResult___fst_exp__h472596 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_exp__h454769 : - _theResult___fst_exp__h437460) : + _theResult___snd_fst_exp__h454770 : + _theResult___fst_exp__h437461) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_exp__h472589 : - _theResult___fst_exp__h437460) ; - assign _theResult___fst_exp__h472598 = + _theResult___snd_fst_exp__h472590 : + _theResult___fst_exp__h437461) ; + assign _theResult___fst_exp__h472599 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h472595 ; - assign _theResult___fst_exp__h486454 = + _theResult___fst_exp__h472596 ; + assign _theResult___fst_exp__h486455 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_exp__h501518 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; + assign _theResult___fst_exp__h501519 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h501524 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___fst_exp__h501525 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585) ? 11'd0 : - _theResult___fst_exp__h501518 ; - assign _theResult___fst_exp__h501527 = - (f1_exp__h482139 == 8'd0) ? - _theResult___fst_exp__h501524 : + _theResult___fst_exp__h501519 ; + assign _theResult___fst_exp__h501528 = + (f1_exp__h482140 == 8'd0) ? + _theResult___fst_exp__h501525 : 11'd897 ; - assign _theResult___fst_exp__h502282 = + assign _theResult___fst_exp__h502283 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 : + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 ; - assign _theResult___fst_exp__h502285 = - (_theResult___fst_exp__h501527 == 11'd2047) ? - _theResult___fst_exp__h501527 : - _theResult___fst_exp__h502282 ; - assign _theResult___fst_exp__h511104 = - _theResult____h502868[56] ? + assign _theResult___fst_exp__h502286 = + (_theResult___fst_exp__h501528 == 11'd2047) ? + _theResult___fst_exp__h501528 : + _theResult___fst_exp__h502283 ; + assign _theResult___fst_exp__h511105 = + _theResult____h502869[56] ? 11'd2 : - _theResult___fst_exp__h511178 ; - assign _theResult___fst_exp__h511169 = + _theResult___fst_exp__h511179 ; + assign _theResult___fst_exp__h511170 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ; - assign _theResult___fst_exp__h511175 = - (!_theResult____h502868[56] && !_theResult____h502868[55] && - !_theResult____h502868[54] && - !_theResult____h502868[53] && - !_theResult____h502868[52] && - !_theResult____h502868[51] && - !_theResult____h502868[50] && - !_theResult____h502868[49] && - !_theResult____h502868[48] && - !_theResult____h502868[47] && - !_theResult____h502868[46] && - !_theResult____h502868[45] && - !_theResult____h502868[44] && - !_theResult____h502868[43] && - !_theResult____h502868[42] && - !_theResult____h502868[41] && - !_theResult____h502868[40] && - !_theResult____h502868[39] && - !_theResult____h502868[38] && - !_theResult____h502868[37] && - !_theResult____h502868[36] && - !_theResult____h502868[35] && - !_theResult____h502868[34] && - !_theResult____h502868[33] && - !_theResult____h502868[32] && - !_theResult____h502868[31] && - !_theResult____h502868[30] && - !_theResult____h502868[29] && - !_theResult____h502868[28] && - !_theResult____h502868[27] && - !_theResult____h502868[26] && - !_theResult____h502868[25] && - !_theResult____h502868[24] && - !_theResult____h502868[23] && - !_theResult____h502868[22] && - !_theResult____h502868[21] && - !_theResult____h502868[20] && - !_theResult____h502868[19] && - !_theResult____h502868[18] && - !_theResult____h502868[17] && - !_theResult____h502868[16] && - !_theResult____h502868[15] && - !_theResult____h502868[14] && - !_theResult____h502868[13] && - !_theResult____h502868[12] && - !_theResult____h502868[11] && - !_theResult____h502868[10] && - !_theResult____h502868[9] && - !_theResult____h502868[8] && - !_theResult____h502868[7] && - !_theResult____h502868[6] && - !_theResult____h502868[5] && - !_theResult____h502868[4] && - !_theResult____h502868[3] && - !_theResult____h502868[2] && - !_theResult____h502868[1] && - !_theResult____h502868[0] || + assign _theResult___fst_exp__h511176 = + (!_theResult____h502869[56] && !_theResult____h502869[55] && + !_theResult____h502869[54] && + !_theResult____h502869[53] && + !_theResult____h502869[52] && + !_theResult____h502869[51] && + !_theResult____h502869[50] && + !_theResult____h502869[49] && + !_theResult____h502869[48] && + !_theResult____h502869[47] && + !_theResult____h502869[46] && + !_theResult____h502869[45] && + !_theResult____h502869[44] && + !_theResult____h502869[43] && + !_theResult____h502869[42] && + !_theResult____h502869[41] && + !_theResult____h502869[40] && + !_theResult____h502869[39] && + !_theResult____h502869[38] && + !_theResult____h502869[37] && + !_theResult____h502869[36] && + !_theResult____h502869[35] && + !_theResult____h502869[34] && + !_theResult____h502869[33] && + !_theResult____h502869[32] && + !_theResult____h502869[31] && + !_theResult____h502869[30] && + !_theResult____h502869[29] && + !_theResult____h502869[28] && + !_theResult____h502869[27] && + !_theResult____h502869[26] && + !_theResult____h502869[25] && + !_theResult____h502869[24] && + !_theResult____h502869[23] && + !_theResult____h502869[22] && + !_theResult____h502869[21] && + !_theResult____h502869[20] && + !_theResult____h502869[19] && + !_theResult____h502869[18] && + !_theResult____h502869[17] && + !_theResult____h502869[16] && + !_theResult____h502869[15] && + !_theResult____h502869[14] && + !_theResult____h502869[13] && + !_theResult____h502869[12] && + !_theResult____h502869[11] && + !_theResult____h502869[10] && + !_theResult____h502869[9] && + !_theResult____h502869[8] && + !_theResult____h502869[7] && + !_theResult____h502869[6] && + !_theResult____h502869[5] && + !_theResult____h502869[4] && + !_theResult____h502869[3] && + !_theResult____h502869[2] && + !_theResult____h502869[1] && + !_theResult____h502869[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897) ? 11'd0 : - _theResult___fst_exp__h511169 ; - assign _theResult___fst_exp__h511178 = - (!_theResult____h502868[56] && _theResult____h502868[55]) ? + _theResult___fst_exp__h511170 ; + assign _theResult___fst_exp__h511179 = + (!_theResult____h502869[56] && _theResult____h502869[55]) ? 11'd1 : - _theResult___fst_exp__h511175 ; - assign _theResult___fst_exp__h511933 = + _theResult___fst_exp__h511176 ; + assign _theResult___fst_exp__h511934 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 : + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 ; - assign _theResult___fst_exp__h511936 = - (_theResult___fst_exp__h511104 == 11'd2047) ? - _theResult___fst_exp__h511104 : - _theResult___fst_exp__h511933 ; - assign _theResult___fst_exp__h519889 = + assign _theResult___fst_exp__h511937 = + (_theResult___fst_exp__h511105 == 11'd2047) ? + _theResult___fst_exp__h511105 : + _theResult___fst_exp__h511934 ; + assign _theResult___fst_exp__h519890 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h519928 = + assign _theResult___fst_exp__h519929 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h519934 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___fst_exp__h519935 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947) ? 11'd0 : - _theResult___fst_exp__h519928 ; - assign _theResult___fst_exp__h519937 = - (f1_exp__h482139 == 8'd0) ? - _theResult___fst_exp__h519934 : - _theResult___fst_exp__h519889 ; - assign _theResult___fst_exp__h520717 = + _theResult___fst_exp__h519929 ; + assign _theResult___fst_exp__h519938 = + (f1_exp__h482140 == 8'd0) ? + _theResult___fst_exp__h519935 : + _theResult___fst_exp__h519890 ; + assign _theResult___fst_exp__h520718 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 : + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 ; - assign _theResult___fst_exp__h520720 = - (_theResult___fst_exp__h519937 == 11'd2047) ? - _theResult___fst_exp__h519937 : - _theResult___fst_exp__h520717 ; - assign _theResult___fst_exp__h520729 = - (f1_exp__h482139 == 8'd0) ? + assign _theResult___fst_exp__h520721 = + (_theResult___fst_exp__h519938 == 11'd2047) ? + _theResult___fst_exp__h519938 : + _theResult___fst_exp__h520718 ; + assign _theResult___fst_exp__h520730 = + (f1_exp__h482140 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_exp__h502288 : - _theResult___fst_exp__h486454) : + _theResult___snd_fst_exp__h502289 : + _theResult___fst_exp__h486455) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_exp__h520723 : - _theResult___fst_exp__h486454) ; - assign _theResult___fst_exp__h520732 = - (f1_exp__h482139 == 8'd0 && f1_sfd__h482140 == 23'd0) ? + _theResult___snd_fst_exp__h520724 : + _theResult___fst_exp__h486455) ; + assign _theResult___fst_exp__h520733 = + (f1_exp__h482140 == 8'd0 && f1_sfd__h482141 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h520729 ; - assign _theResult___fst_exp__h525307 = + _theResult___fst_exp__h520730 ; + assign _theResult___fst_exp__h525308 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 ; - assign _theResult___fst_exp__h540371 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; + assign _theResult___fst_exp__h540372 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h540377 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___fst_exp__h540378 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085) ? 11'd0 : - _theResult___fst_exp__h540371 ; - assign _theResult___fst_exp__h540380 = - (f2_exp__h521133 == 8'd0) ? - _theResult___fst_exp__h540377 : + _theResult___fst_exp__h540372 ; + assign _theResult___fst_exp__h540381 = + (f2_exp__h521134 == 8'd0) ? + _theResult___fst_exp__h540378 : 11'd897 ; - assign _theResult___fst_exp__h541135 = + assign _theResult___fst_exp__h541136 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 : + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 ; - assign _theResult___fst_exp__h541138 = - (_theResult___fst_exp__h540380 == 11'd2047) ? - _theResult___fst_exp__h540380 : - _theResult___fst_exp__h541135 ; - assign _theResult___fst_exp__h549957 = - _theResult____h541721[56] ? + assign _theResult___fst_exp__h541139 = + (_theResult___fst_exp__h540381 == 11'd2047) ? + _theResult___fst_exp__h540381 : + _theResult___fst_exp__h541136 ; + assign _theResult___fst_exp__h549958 = + _theResult____h541722[56] ? 11'd2 : - _theResult___fst_exp__h550031 ; - assign _theResult___fst_exp__h550022 = + _theResult___fst_exp__h550032 ; + assign _theResult___fst_exp__h550023 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ; - assign _theResult___fst_exp__h550028 = - (!_theResult____h541721[56] && !_theResult____h541721[55] && - !_theResult____h541721[54] && - !_theResult____h541721[53] && - !_theResult____h541721[52] && - !_theResult____h541721[51] && - !_theResult____h541721[50] && - !_theResult____h541721[49] && - !_theResult____h541721[48] && - !_theResult____h541721[47] && - !_theResult____h541721[46] && - !_theResult____h541721[45] && - !_theResult____h541721[44] && - !_theResult____h541721[43] && - !_theResult____h541721[42] && - !_theResult____h541721[41] && - !_theResult____h541721[40] && - !_theResult____h541721[39] && - !_theResult____h541721[38] && - !_theResult____h541721[37] && - !_theResult____h541721[36] && - !_theResult____h541721[35] && - !_theResult____h541721[34] && - !_theResult____h541721[33] && - !_theResult____h541721[32] && - !_theResult____h541721[31] && - !_theResult____h541721[30] && - !_theResult____h541721[29] && - !_theResult____h541721[28] && - !_theResult____h541721[27] && - !_theResult____h541721[26] && - !_theResult____h541721[25] && - !_theResult____h541721[24] && - !_theResult____h541721[23] && - !_theResult____h541721[22] && - !_theResult____h541721[21] && - !_theResult____h541721[20] && - !_theResult____h541721[19] && - !_theResult____h541721[18] && - !_theResult____h541721[17] && - !_theResult____h541721[16] && - !_theResult____h541721[15] && - !_theResult____h541721[14] && - !_theResult____h541721[13] && - !_theResult____h541721[12] && - !_theResult____h541721[11] && - !_theResult____h541721[10] && - !_theResult____h541721[9] && - !_theResult____h541721[8] && - !_theResult____h541721[7] && - !_theResult____h541721[6] && - !_theResult____h541721[5] && - !_theResult____h541721[4] && - !_theResult____h541721[3] && - !_theResult____h541721[2] && - !_theResult____h541721[1] && - !_theResult____h541721[0] || + assign _theResult___fst_exp__h550029 = + (!_theResult____h541722[56] && !_theResult____h541722[55] && + !_theResult____h541722[54] && + !_theResult____h541722[53] && + !_theResult____h541722[52] && + !_theResult____h541722[51] && + !_theResult____h541722[50] && + !_theResult____h541722[49] && + !_theResult____h541722[48] && + !_theResult____h541722[47] && + !_theResult____h541722[46] && + !_theResult____h541722[45] && + !_theResult____h541722[44] && + !_theResult____h541722[43] && + !_theResult____h541722[42] && + !_theResult____h541722[41] && + !_theResult____h541722[40] && + !_theResult____h541722[39] && + !_theResult____h541722[38] && + !_theResult____h541722[37] && + !_theResult____h541722[36] && + !_theResult____h541722[35] && + !_theResult____h541722[34] && + !_theResult____h541722[33] && + !_theResult____h541722[32] && + !_theResult____h541722[31] && + !_theResult____h541722[30] && + !_theResult____h541722[29] && + !_theResult____h541722[28] && + !_theResult____h541722[27] && + !_theResult____h541722[26] && + !_theResult____h541722[25] && + !_theResult____h541722[24] && + !_theResult____h541722[23] && + !_theResult____h541722[22] && + !_theResult____h541722[21] && + !_theResult____h541722[20] && + !_theResult____h541722[19] && + !_theResult____h541722[18] && + !_theResult____h541722[17] && + !_theResult____h541722[16] && + !_theResult____h541722[15] && + !_theResult____h541722[14] && + !_theResult____h541722[13] && + !_theResult____h541722[12] && + !_theResult____h541722[11] && + !_theResult____h541722[10] && + !_theResult____h541722[9] && + !_theResult____h541722[8] && + !_theResult____h541722[7] && + !_theResult____h541722[6] && + !_theResult____h541722[5] && + !_theResult____h541722[4] && + !_theResult____h541722[3] && + !_theResult____h541722[2] && + !_theResult____h541722[1] && + !_theResult____h541722[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382) ? 11'd0 : - _theResult___fst_exp__h550022 ; - assign _theResult___fst_exp__h550031 = - (!_theResult____h541721[56] && _theResult____h541721[55]) ? + _theResult___fst_exp__h550023 ; + assign _theResult___fst_exp__h550032 = + (!_theResult____h541722[56] && _theResult____h541722[55]) ? 11'd1 : - _theResult___fst_exp__h550028 ; - assign _theResult___fst_exp__h550786 = + _theResult___fst_exp__h550029 ; + assign _theResult___fst_exp__h550787 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 : + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 ; - assign _theResult___fst_exp__h550789 = - (_theResult___fst_exp__h549957 == 11'd2047) ? - _theResult___fst_exp__h549957 : - _theResult___fst_exp__h550786 ; - assign _theResult___fst_exp__h558742 = + assign _theResult___fst_exp__h550790 = + (_theResult___fst_exp__h549958 == 11'd2047) ? + _theResult___fst_exp__h549958 : + _theResult___fst_exp__h550787 ; + assign _theResult___fst_exp__h558743 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h558781 = + assign _theResult___fst_exp__h558782 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h558787 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___fst_exp__h558788 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432) ? 11'd0 : - _theResult___fst_exp__h558781 ; - assign _theResult___fst_exp__h558790 = - (f2_exp__h521133 == 8'd0) ? - _theResult___fst_exp__h558787 : - _theResult___fst_exp__h558742 ; - assign _theResult___fst_exp__h559570 = + _theResult___fst_exp__h558782 ; + assign _theResult___fst_exp__h558791 = + (f2_exp__h521134 == 8'd0) ? + _theResult___fst_exp__h558788 : + _theResult___fst_exp__h558743 ; + assign _theResult___fst_exp__h559571 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 : + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ; - assign _theResult___fst_exp__h559573 = - (_theResult___fst_exp__h558790 == 11'd2047) ? - _theResult___fst_exp__h558790 : - _theResult___fst_exp__h559570 ; - assign _theResult___fst_exp__h559582 = - (f2_exp__h521133 == 8'd0) ? + assign _theResult___fst_exp__h559574 = + (_theResult___fst_exp__h558791 == 11'd2047) ? + _theResult___fst_exp__h558791 : + _theResult___fst_exp__h559571 ; + assign _theResult___fst_exp__h559583 = + (f2_exp__h521134 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_exp__h541141 : - _theResult___fst_exp__h525307) : + _theResult___snd_fst_exp__h541142 : + _theResult___fst_exp__h525308) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_exp__h559576 : - _theResult___fst_exp__h525307) ; - assign _theResult___fst_exp__h559585 = - (f2_exp__h521133 == 8'd0 && f2_sfd__h521134 == 23'd0) ? + _theResult___snd_fst_exp__h559577 : + _theResult___fst_exp__h525308) ; + assign _theResult___fst_exp__h559586 = + (f2_exp__h521134 == 8'd0 && f2_sfd__h521135 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h559582 ; - assign _theResult___fst_exp__h564611 = + _theResult___fst_exp__h559583 ; + assign _theResult___fst_exp__h564612 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_exp__h579675 = + assign _theResult___fst_exp__h579676 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h579681 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___fst_exp__h579682 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315) ? 11'd0 : - _theResult___fst_exp__h579675 ; - assign _theResult___fst_exp__h579684 = - (f3_exp__h560437 == 8'd0) ? - _theResult___fst_exp__h579681 : + _theResult___fst_exp__h579676 ; + assign _theResult___fst_exp__h579685 = + (f3_exp__h560438 == 8'd0) ? + _theResult___fst_exp__h579682 : 11'd897 ; - assign _theResult___fst_exp__h580439 = + assign _theResult___fst_exp__h580440 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 : + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 ; - assign _theResult___fst_exp__h580442 = - (_theResult___fst_exp__h579684 == 11'd2047) ? - _theResult___fst_exp__h579684 : - _theResult___fst_exp__h580439 ; - assign _theResult___fst_exp__h589261 = - _theResult____h581025[56] ? + assign _theResult___fst_exp__h580443 = + (_theResult___fst_exp__h579685 == 11'd2047) ? + _theResult___fst_exp__h579685 : + _theResult___fst_exp__h580440 ; + assign _theResult___fst_exp__h589262 = + _theResult____h581026[56] ? 11'd2 : - _theResult___fst_exp__h589335 ; - assign _theResult___fst_exp__h589326 = + _theResult___fst_exp__h589336 ; + assign _theResult___fst_exp__h589327 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ; - assign _theResult___fst_exp__h589332 = - (!_theResult____h581025[56] && !_theResult____h581025[55] && - !_theResult____h581025[54] && - !_theResult____h581025[53] && - !_theResult____h581025[52] && - !_theResult____h581025[51] && - !_theResult____h581025[50] && - !_theResult____h581025[49] && - !_theResult____h581025[48] && - !_theResult____h581025[47] && - !_theResult____h581025[46] && - !_theResult____h581025[45] && - !_theResult____h581025[44] && - !_theResult____h581025[43] && - !_theResult____h581025[42] && - !_theResult____h581025[41] && - !_theResult____h581025[40] && - !_theResult____h581025[39] && - !_theResult____h581025[38] && - !_theResult____h581025[37] && - !_theResult____h581025[36] && - !_theResult____h581025[35] && - !_theResult____h581025[34] && - !_theResult____h581025[33] && - !_theResult____h581025[32] && - !_theResult____h581025[31] && - !_theResult____h581025[30] && - !_theResult____h581025[29] && - !_theResult____h581025[28] && - !_theResult____h581025[27] && - !_theResult____h581025[26] && - !_theResult____h581025[25] && - !_theResult____h581025[24] && - !_theResult____h581025[23] && - !_theResult____h581025[22] && - !_theResult____h581025[21] && - !_theResult____h581025[20] && - !_theResult____h581025[19] && - !_theResult____h581025[18] && - !_theResult____h581025[17] && - !_theResult____h581025[16] && - !_theResult____h581025[15] && - !_theResult____h581025[14] && - !_theResult____h581025[13] && - !_theResult____h581025[12] && - !_theResult____h581025[11] && - !_theResult____h581025[10] && - !_theResult____h581025[9] && - !_theResult____h581025[8] && - !_theResult____h581025[7] && - !_theResult____h581025[6] && - !_theResult____h581025[5] && - !_theResult____h581025[4] && - !_theResult____h581025[3] && - !_theResult____h581025[2] && - !_theResult____h581025[1] && - !_theResult____h581025[0] || + assign _theResult___fst_exp__h589333 = + (!_theResult____h581026[56] && !_theResult____h581026[55] && + !_theResult____h581026[54] && + !_theResult____h581026[53] && + !_theResult____h581026[52] && + !_theResult____h581026[51] && + !_theResult____h581026[50] && + !_theResult____h581026[49] && + !_theResult____h581026[48] && + !_theResult____h581026[47] && + !_theResult____h581026[46] && + !_theResult____h581026[45] && + !_theResult____h581026[44] && + !_theResult____h581026[43] && + !_theResult____h581026[42] && + !_theResult____h581026[41] && + !_theResult____h581026[40] && + !_theResult____h581026[39] && + !_theResult____h581026[38] && + !_theResult____h581026[37] && + !_theResult____h581026[36] && + !_theResult____h581026[35] && + !_theResult____h581026[34] && + !_theResult____h581026[33] && + !_theResult____h581026[32] && + !_theResult____h581026[31] && + !_theResult____h581026[30] && + !_theResult____h581026[29] && + !_theResult____h581026[28] && + !_theResult____h581026[27] && + !_theResult____h581026[26] && + !_theResult____h581026[25] && + !_theResult____h581026[24] && + !_theResult____h581026[23] && + !_theResult____h581026[22] && + !_theResult____h581026[21] && + !_theResult____h581026[20] && + !_theResult____h581026[19] && + !_theResult____h581026[18] && + !_theResult____h581026[17] && + !_theResult____h581026[16] && + !_theResult____h581026[15] && + !_theResult____h581026[14] && + !_theResult____h581026[13] && + !_theResult____h581026[12] && + !_theResult____h581026[11] && + !_theResult____h581026[10] && + !_theResult____h581026[9] && + !_theResult____h581026[8] && + !_theResult____h581026[7] && + !_theResult____h581026[6] && + !_theResult____h581026[5] && + !_theResult____h581026[4] && + !_theResult____h581026[3] && + !_theResult____h581026[2] && + !_theResult____h581026[1] && + !_theResult____h581026[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612) ? 11'd0 : - _theResult___fst_exp__h589326 ; - assign _theResult___fst_exp__h589335 = - (!_theResult____h581025[56] && _theResult____h581025[55]) ? + _theResult___fst_exp__h589327 ; + assign _theResult___fst_exp__h589336 = + (!_theResult____h581026[56] && _theResult____h581026[55]) ? 11'd1 : - _theResult___fst_exp__h589332 ; - assign _theResult___fst_exp__h590090 = + _theResult___fst_exp__h589333 ; + assign _theResult___fst_exp__h590091 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 : + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ; - assign _theResult___fst_exp__h590093 = - (_theResult___fst_exp__h589261 == 11'd2047) ? - _theResult___fst_exp__h589261 : - _theResult___fst_exp__h590090 ; - assign _theResult___fst_exp__h598046 = + assign _theResult___fst_exp__h590094 = + (_theResult___fst_exp__h589262 == 11'd2047) ? + _theResult___fst_exp__h589262 : + _theResult___fst_exp__h590091 ; + assign _theResult___fst_exp__h598047 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h598085 = + assign _theResult___fst_exp__h598086 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h598091 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___fst_exp__h598092 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662) ? 11'd0 : - _theResult___fst_exp__h598085 ; - assign _theResult___fst_exp__h598094 = - (f3_exp__h560437 == 8'd0) ? - _theResult___fst_exp__h598091 : - _theResult___fst_exp__h598046 ; - assign _theResult___fst_exp__h598874 = + _theResult___fst_exp__h598086 ; + assign _theResult___fst_exp__h598095 = + (f3_exp__h560438 == 8'd0) ? + _theResult___fst_exp__h598092 : + _theResult___fst_exp__h598047 ; + assign _theResult___fst_exp__h598875 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 : + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; - assign _theResult___fst_exp__h598877 = - (_theResult___fst_exp__h598094 == 11'd2047) ? - _theResult___fst_exp__h598094 : - _theResult___fst_exp__h598874 ; - assign _theResult___fst_exp__h598886 = - (f3_exp__h560437 == 8'd0) ? + assign _theResult___fst_exp__h598878 = + (_theResult___fst_exp__h598095 == 11'd2047) ? + _theResult___fst_exp__h598095 : + _theResult___fst_exp__h598875 ; + assign _theResult___fst_exp__h598887 = + (f3_exp__h560438 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_exp__h580445 : - _theResult___fst_exp__h564611) : + _theResult___snd_fst_exp__h580446 : + _theResult___fst_exp__h564612) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_exp__h598880 : - _theResult___fst_exp__h564611) ; - assign _theResult___fst_exp__h598889 = - (f3_exp__h560437 == 8'd0 && f3_sfd__h560438 == 23'd0) ? + _theResult___snd_fst_exp__h598881 : + _theResult___fst_exp__h564612) ; + assign _theResult___fst_exp__h598890 = + (f3_exp__h560438 == 8'd0 && f3_sfd__h560439 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h598886 ; - assign _theResult___fst_sfd__h354793 = - (_theResult___fst_exp__h354195 == 8'd255) ? - sfdin__h354189[56:34] : - _theResult___fst_sfd__h354790 ; - assign _theResult___fst_sfd__h363375 = - (_theResult___fst_exp__h362851 == 8'd255) ? - _theResult___snd__h362802[56:34] : - _theResult___fst_sfd__h363372 ; - assign _theResult___fst_sfd__h372559 = - (_theResult___fst_exp__h371961 == 8'd255) ? - sfdin__h371955[56:34] : - _theResult___fst_sfd__h372556 ; - assign _theResult___fst_sfd__h381195 = - (_theResult___fst_exp__h380646 == 8'd255) ? - _theResult___snd__h380592[56:34] : - _theResult___fst_sfd__h381192 ; - assign _theResult___fst_sfd__h381204 = + _theResult___fst_exp__h598887 ; + assign _theResult___fst_sfd__h354794 = + (_theResult___fst_exp__h354196 == 8'd255) ? + sfdin__h354190[56:34] : + _theResult___fst_sfd__h354791 ; + assign _theResult___fst_sfd__h363376 = + (_theResult___fst_exp__h362852 == 8'd255) ? + _theResult___snd__h362803[56:34] : + _theResult___fst_sfd__h363373 ; + assign _theResult___fst_sfd__h372560 = + (_theResult___fst_exp__h371962 == 8'd255) ? + sfdin__h371956[56:34] : + _theResult___fst_sfd__h372557 ; + assign _theResult___fst_sfd__h381196 = + (_theResult___fst_exp__h380647 == 8'd255) ? + _theResult___snd__h380593[56:34] : + _theResult___fst_sfd__h381193 ; + assign _theResult___fst_sfd__h381205 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_sfd__h363378 : - _theResult___fst_sfd__h346067) : + _theResult___snd_fst_sfd__h363379 : + _theResult___fst_sfd__h346068) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_sfd__h381198 : - _theResult___fst_sfd__h346067) ; - assign _theResult___fst_sfd__h381210 = + _theResult___snd_fst_sfd__h381199 : + _theResult___fst_sfd__h346068) ; + assign _theResult___fst_sfd__h381211 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -28177,33 +28203,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h381204 ; - assign _theResult___fst_sfd__h400490 = - (_theResult___fst_exp__h399892 == 8'd255) ? - sfdin__h399886[56:34] : - _theResult___fst_sfd__h400487 ; - assign _theResult___fst_sfd__h409072 = - (_theResult___fst_exp__h408548 == 8'd255) ? - _theResult___snd__h408499[56:34] : - _theResult___fst_sfd__h409069 ; - assign _theResult___fst_sfd__h418256 = - (_theResult___fst_exp__h417658 == 8'd255) ? - sfdin__h417652[56:34] : - _theResult___fst_sfd__h418253 ; - assign _theResult___fst_sfd__h426892 = - (_theResult___fst_exp__h426343 == 8'd255) ? - _theResult___snd__h426289[56:34] : - _theResult___fst_sfd__h426889 ; - assign _theResult___fst_sfd__h426901 = + _theResult___fst_sfd__h381205 ; + assign _theResult___fst_sfd__h400491 = + (_theResult___fst_exp__h399893 == 8'd255) ? + sfdin__h399887[56:34] : + _theResult___fst_sfd__h400488 ; + assign _theResult___fst_sfd__h409073 = + (_theResult___fst_exp__h408549 == 8'd255) ? + _theResult___snd__h408500[56:34] : + _theResult___fst_sfd__h409070 ; + assign _theResult___fst_sfd__h418257 = + (_theResult___fst_exp__h417659 == 8'd255) ? + sfdin__h417653[56:34] : + _theResult___fst_sfd__h418254 ; + assign _theResult___fst_sfd__h426893 = + (_theResult___fst_exp__h426344 == 8'd255) ? + _theResult___snd__h426290[56:34] : + _theResult___fst_sfd__h426890 ; + assign _theResult___fst_sfd__h426902 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_sfd__h409075 : - _theResult___fst_sfd__h391766) : + _theResult___snd_fst_sfd__h409076 : + _theResult___fst_sfd__h391767) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_sfd__h426895 : - _theResult___fst_sfd__h391766) ; - assign _theResult___fst_sfd__h426907 = + _theResult___snd_fst_sfd__h426896 : + _theResult___fst_sfd__h391767) ; + assign _theResult___fst_sfd__h426908 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -28211,33 +28237,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h426901 ; - assign _theResult___fst_sfd__h446185 = - (_theResult___fst_exp__h445587 == 8'd255) ? - sfdin__h445581[56:34] : - _theResult___fst_sfd__h446182 ; - assign _theResult___fst_sfd__h454767 = - (_theResult___fst_exp__h454243 == 8'd255) ? - _theResult___snd__h454194[56:34] : - _theResult___fst_sfd__h454764 ; - assign _theResult___fst_sfd__h463951 = - (_theResult___fst_exp__h463353 == 8'd255) ? - sfdin__h463347[56:34] : - _theResult___fst_sfd__h463948 ; - assign _theResult___fst_sfd__h472587 = - (_theResult___fst_exp__h472038 == 8'd255) ? - _theResult___snd__h471984[56:34] : - _theResult___fst_sfd__h472584 ; - assign _theResult___fst_sfd__h472596 = + _theResult___fst_sfd__h426902 ; + assign _theResult___fst_sfd__h446186 = + (_theResult___fst_exp__h445588 == 8'd255) ? + sfdin__h445582[56:34] : + _theResult___fst_sfd__h446183 ; + assign _theResult___fst_sfd__h454768 = + (_theResult___fst_exp__h454244 == 8'd255) ? + _theResult___snd__h454195[56:34] : + _theResult___fst_sfd__h454765 ; + assign _theResult___fst_sfd__h463952 = + (_theResult___fst_exp__h463354 == 8'd255) ? + sfdin__h463348[56:34] : + _theResult___fst_sfd__h463949 ; + assign _theResult___fst_sfd__h472588 = + (_theResult___fst_exp__h472039 == 8'd255) ? + _theResult___snd__h471985[56:34] : + _theResult___fst_sfd__h472585 ; + assign _theResult___fst_sfd__h472597 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_sfd__h454770 : - _theResult___fst_sfd__h437461) : + _theResult___snd_fst_sfd__h454771 : + _theResult___fst_sfd__h437462) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_sfd__h472590 : - _theResult___fst_sfd__h437461) ; - assign _theResult___fst_sfd__h472602 = + _theResult___snd_fst_sfd__h472591 : + _theResult___fst_sfd__h437462) ; + assign _theResult___fst_sfd__h472603 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -28245,1309 +28271,1309 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h472596 ; - assign _theResult___fst_sfd__h486455 = + _theResult___fst_sfd__h472597 ; + assign _theResult___fst_sfd__h486456 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_sfd__h502283 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; + assign _theResult___fst_sfd__h502284 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 : + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; - assign _theResult___fst_sfd__h502286 = - (_theResult___fst_exp__h501527 == 11'd2047) ? - _theResult___snd__h501478[56:5] : - _theResult___fst_sfd__h502283 ; - assign _theResult___fst_sfd__h511934 = + assign _theResult___fst_sfd__h502287 = + (_theResult___fst_exp__h501528 == 11'd2047) ? + _theResult___snd__h501479[56:5] : + _theResult___fst_sfd__h502284 ; + assign _theResult___fst_sfd__h511935 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; - assign _theResult___fst_sfd__h511937 = - (_theResult___fst_exp__h511104 == 11'd2047) ? - sfdin__h511098[56:5] : - _theResult___fst_sfd__h511934 ; - assign _theResult___fst_sfd__h520718 = + assign _theResult___fst_sfd__h511938 = + (_theResult___fst_exp__h511105 == 11'd2047) ? + sfdin__h511099[56:5] : + _theResult___fst_sfd__h511935 ; + assign _theResult___fst_sfd__h520719 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 : + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; - assign _theResult___fst_sfd__h520721 = - (_theResult___fst_exp__h519937 == 11'd2047) ? - _theResult___snd__h519883[56:5] : - _theResult___fst_sfd__h520718 ; - assign _theResult___fst_sfd__h520730 = - (f1_exp__h482139 == 8'd0) ? + assign _theResult___fst_sfd__h520722 = + (_theResult___fst_exp__h519938 == 11'd2047) ? + _theResult___snd__h519884[56:5] : + _theResult___fst_sfd__h520719 ; + assign _theResult___fst_sfd__h520731 = + (f1_exp__h482140 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_sfd__h502289 : - _theResult___fst_sfd__h486455) : + _theResult___snd_fst_sfd__h502290 : + _theResult___fst_sfd__h486456) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_sfd__h520724 : - _theResult___fst_sfd__h486455) ; - assign _theResult___fst_sfd__h520736 = - ((f1_exp__h482139 == 8'd255 || f1_exp__h482139 == 8'd0) && - f1_sfd__h482140 == 23'd0) ? + _theResult___snd_fst_sfd__h520725 : + _theResult___fst_sfd__h486456) ; + assign _theResult___fst_sfd__h520737 = + ((f1_exp__h482140 == 8'd255 || f1_exp__h482140 == 8'd0) && + f1_sfd__h482141 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h520730 ; - assign _theResult___fst_sfd__h525308 = + _theResult___fst_sfd__h520731 ; + assign _theResult___fst_sfd__h525309 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_sfd__h541136 = + assign _theResult___fst_sfd__h541137 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 : + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 ; - assign _theResult___fst_sfd__h541139 = - (_theResult___fst_exp__h540380 == 11'd2047) ? - _theResult___snd__h540331[56:5] : - _theResult___fst_sfd__h541136 ; - assign _theResult___fst_sfd__h550787 = + assign _theResult___fst_sfd__h541140 = + (_theResult___fst_exp__h540381 == 11'd2047) ? + _theResult___snd__h540332[56:5] : + _theResult___fst_sfd__h541137 ; + assign _theResult___fst_sfd__h550788 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; - assign _theResult___fst_sfd__h550790 = - (_theResult___fst_exp__h549957 == 11'd2047) ? - sfdin__h549951[56:5] : - _theResult___fst_sfd__h550787 ; - assign _theResult___fst_sfd__h559571 = + assign _theResult___fst_sfd__h550791 = + (_theResult___fst_exp__h549958 == 11'd2047) ? + sfdin__h549952[56:5] : + _theResult___fst_sfd__h550788 ; + assign _theResult___fst_sfd__h559572 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 : + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; - assign _theResult___fst_sfd__h559574 = - (_theResult___fst_exp__h558790 == 11'd2047) ? - _theResult___snd__h558736[56:5] : - _theResult___fst_sfd__h559571 ; - assign _theResult___fst_sfd__h559583 = - (f2_exp__h521133 == 8'd0) ? + assign _theResult___fst_sfd__h559575 = + (_theResult___fst_exp__h558791 == 11'd2047) ? + _theResult___snd__h558737[56:5] : + _theResult___fst_sfd__h559572 ; + assign _theResult___fst_sfd__h559584 = + (f2_exp__h521134 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_sfd__h541142 : - _theResult___fst_sfd__h525308) : + _theResult___snd_fst_sfd__h541143 : + _theResult___fst_sfd__h525309) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_sfd__h559577 : - _theResult___fst_sfd__h525308) ; - assign _theResult___fst_sfd__h559589 = - ((f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) && - f2_sfd__h521134 == 23'd0) ? + _theResult___snd_fst_sfd__h559578 : + _theResult___fst_sfd__h525309) ; + assign _theResult___fst_sfd__h559590 = + ((f2_exp__h521134 == 8'd255 || f2_exp__h521134 == 8'd0) && + f2_sfd__h521135 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h559583 ; - assign _theResult___fst_sfd__h564612 = + _theResult___fst_sfd__h559584 ; + assign _theResult___fst_sfd__h564613 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_sfd__h580440 = + assign _theResult___fst_sfd__h580441 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 : + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 ; - assign _theResult___fst_sfd__h580443 = - (_theResult___fst_exp__h579684 == 11'd2047) ? - _theResult___snd__h579635[56:5] : - _theResult___fst_sfd__h580440 ; - assign _theResult___fst_sfd__h590091 = + assign _theResult___fst_sfd__h580444 = + (_theResult___fst_exp__h579685 == 11'd2047) ? + _theResult___snd__h579636[56:5] : + _theResult___fst_sfd__h580441 ; + assign _theResult___fst_sfd__h590092 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 ; - assign _theResult___fst_sfd__h590094 = - (_theResult___fst_exp__h589261 == 11'd2047) ? - sfdin__h589255[56:5] : - _theResult___fst_sfd__h590091 ; - assign _theResult___fst_sfd__h598875 = + assign _theResult___fst_sfd__h590095 = + (_theResult___fst_exp__h589262 == 11'd2047) ? + sfdin__h589256[56:5] : + _theResult___fst_sfd__h590092 ; + assign _theResult___fst_sfd__h598876 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 : + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 ; - assign _theResult___fst_sfd__h598878 = - (_theResult___fst_exp__h598094 == 11'd2047) ? - _theResult___snd__h598040[56:5] : - _theResult___fst_sfd__h598875 ; - assign _theResult___fst_sfd__h598887 = - (f3_exp__h560437 == 8'd0) ? + assign _theResult___fst_sfd__h598879 = + (_theResult___fst_exp__h598095 == 11'd2047) ? + _theResult___snd__h598041[56:5] : + _theResult___fst_sfd__h598876 ; + assign _theResult___fst_sfd__h598888 = + (f3_exp__h560438 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_sfd__h580446 : - _theResult___fst_sfd__h564612) : + _theResult___snd_fst_sfd__h580447 : + _theResult___fst_sfd__h564613) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_sfd__h598881 : - _theResult___fst_sfd__h564612) ; - assign _theResult___fst_sfd__h598893 = - ((f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) && - f3_sfd__h560438 == 23'd0) ? + _theResult___snd_fst_sfd__h598882 : + _theResult___fst_sfd__h564613) ; + assign _theResult___fst_sfd__h598894 = + ((f3_exp__h560438 == 8'd255 || f3_exp__h560438 == 8'd0) && + f3_sfd__h560439 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h598887 ; - assign _theResult___sfd__h354712 = - sfd__h354287[24] ? - ((_theResult___fst_exp__h354195 == 8'd254) ? + _theResult___fst_sfd__h598888 ; + assign _theResult___sfd__h354713 = + sfd__h354288[24] ? + ((_theResult___fst_exp__h354196 == 8'd254) ? 23'd0 : - sfd__h354287[23:1]) : - sfd__h354287[22:0] ; - assign _theResult___sfd__h363294 = - sfd__h362869[24] ? - ((_theResult___fst_exp__h362851 == 8'd254) ? + sfd__h354288[23:1]) : + sfd__h354288[22:0] ; + assign _theResult___sfd__h363295 = + sfd__h362870[24] ? + ((_theResult___fst_exp__h362852 == 8'd254) ? 23'd0 : - sfd__h362869[23:1]) : - sfd__h362869[22:0] ; - assign _theResult___sfd__h372478 = - sfd__h372053[24] ? - ((_theResult___fst_exp__h371961 == 8'd254) ? + sfd__h362870[23:1]) : + sfd__h362870[22:0] ; + assign _theResult___sfd__h372479 = + sfd__h372054[24] ? + ((_theResult___fst_exp__h371962 == 8'd254) ? 23'd0 : - sfd__h372053[23:1]) : - sfd__h372053[22:0] ; - assign _theResult___sfd__h381114 = - sfd__h380665[24] ? - ((_theResult___fst_exp__h380646 == 8'd254) ? + sfd__h372054[23:1]) : + sfd__h372054[22:0] ; + assign _theResult___sfd__h381115 = + sfd__h380666[24] ? + ((_theResult___fst_exp__h380647 == 8'd254) ? 23'd0 : - sfd__h380665[23:1]) : - sfd__h380665[22:0] ; - assign _theResult___sfd__h381216 = + sfd__h380666[23:1]) : + sfd__h380666[22:0] ; + assign _theResult___sfd__h381217 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h338429 : - _theResult___fst_sfd__h381210 ; - assign _theResult___sfd__h400409 = - sfd__h399984[24] ? - ((_theResult___fst_exp__h399892 == 8'd254) ? + _theResult___snd_fst_sfd__h338430 : + _theResult___fst_sfd__h381211 ; + assign _theResult___sfd__h400410 = + sfd__h399985[24] ? + ((_theResult___fst_exp__h399893 == 8'd254) ? 23'd0 : - sfd__h399984[23:1]) : - sfd__h399984[22:0] ; - assign _theResult___sfd__h408991 = - sfd__h408566[24] ? - ((_theResult___fst_exp__h408548 == 8'd254) ? + sfd__h399985[23:1]) : + sfd__h399985[22:0] ; + assign _theResult___sfd__h408992 = + sfd__h408567[24] ? + ((_theResult___fst_exp__h408549 == 8'd254) ? 23'd0 : - sfd__h408566[23:1]) : - sfd__h408566[22:0] ; - assign _theResult___sfd__h418175 = - sfd__h417750[24] ? - ((_theResult___fst_exp__h417658 == 8'd254) ? + sfd__h408567[23:1]) : + sfd__h408567[22:0] ; + assign _theResult___sfd__h418176 = + sfd__h417751[24] ? + ((_theResult___fst_exp__h417659 == 8'd254) ? 23'd0 : - sfd__h417750[23:1]) : - sfd__h417750[22:0] ; - assign _theResult___sfd__h426811 = - sfd__h426362[24] ? - ((_theResult___fst_exp__h426343 == 8'd254) ? + sfd__h417751[23:1]) : + sfd__h417751[22:0] ; + assign _theResult___sfd__h426812 = + sfd__h426363[24] ? + ((_theResult___fst_exp__h426344 == 8'd254) ? 23'd0 : - sfd__h426362[23:1]) : - sfd__h426362[22:0] ; - assign _theResult___sfd__h426913 = + sfd__h426363[23:1]) : + sfd__h426363[22:0] ; + assign _theResult___sfd__h426914 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h384131 : - _theResult___fst_sfd__h426907 ; - assign _theResult___sfd__h446104 = - sfd__h445679[24] ? - ((_theResult___fst_exp__h445587 == 8'd254) ? + _theResult___snd_fst_sfd__h384132 : + _theResult___fst_sfd__h426908 ; + assign _theResult___sfd__h446105 = + sfd__h445680[24] ? + ((_theResult___fst_exp__h445588 == 8'd254) ? 23'd0 : - sfd__h445679[23:1]) : - sfd__h445679[22:0] ; - assign _theResult___sfd__h454686 = - sfd__h454261[24] ? - ((_theResult___fst_exp__h454243 == 8'd254) ? + sfd__h445680[23:1]) : + sfd__h445680[22:0] ; + assign _theResult___sfd__h454687 = + sfd__h454262[24] ? + ((_theResult___fst_exp__h454244 == 8'd254) ? 23'd0 : - sfd__h454261[23:1]) : - sfd__h454261[22:0] ; - assign _theResult___sfd__h463870 = - sfd__h463445[24] ? - ((_theResult___fst_exp__h463353 == 8'd254) ? + sfd__h454262[23:1]) : + sfd__h454262[22:0] ; + assign _theResult___sfd__h463871 = + sfd__h463446[24] ? + ((_theResult___fst_exp__h463354 == 8'd254) ? 23'd0 : - sfd__h463445[23:1]) : - sfd__h463445[22:0] ; - assign _theResult___sfd__h472506 = - sfd__h472057[24] ? - ((_theResult___fst_exp__h472038 == 8'd254) ? + sfd__h463446[23:1]) : + sfd__h463446[22:0] ; + assign _theResult___sfd__h472507 = + sfd__h472058[24] ? + ((_theResult___fst_exp__h472039 == 8'd254) ? 23'd0 : - sfd__h472057[23:1]) : - sfd__h472057[22:0] ; - assign _theResult___sfd__h472608 = + sfd__h472058[23:1]) : + sfd__h472058[22:0] ; + assign _theResult___sfd__h472609 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h429826 : - _theResult___fst_sfd__h472602 ; - assign _theResult___sfd__h502183 = - sfd__h501545[53] ? - ((_theResult___fst_exp__h501527 == 11'd2046) ? + _theResult___snd_fst_sfd__h429827 : + _theResult___fst_sfd__h472603 ; + assign _theResult___sfd__h502184 = + sfd__h501546[53] ? + ((_theResult___fst_exp__h501528 == 11'd2046) ? 52'd0 : - sfd__h501545[52:1]) : - sfd__h501545[51:0] ; - assign _theResult___sfd__h511834 = - sfd__h511196[53] ? - ((_theResult___fst_exp__h511104 == 11'd2046) ? + sfd__h501546[52:1]) : + sfd__h501546[51:0] ; + assign _theResult___sfd__h511835 = + sfd__h511197[53] ? + ((_theResult___fst_exp__h511105 == 11'd2046) ? 52'd0 : - sfd__h511196[52:1]) : - sfd__h511196[51:0] ; - assign _theResult___sfd__h520618 = - sfd__h519956[53] ? - ((_theResult___fst_exp__h519937 == 11'd2046) ? + sfd__h511197[52:1]) : + sfd__h511197[51:0] ; + assign _theResult___sfd__h520619 = + sfd__h519957[53] ? + ((_theResult___fst_exp__h519938 == 11'd2046) ? 52'd0 : - sfd__h519956[52:1]) : - sfd__h519956[51:0] ; - assign _theResult___sfd__h541036 = - sfd__h540398[53] ? - ((_theResult___fst_exp__h540380 == 11'd2046) ? + sfd__h519957[52:1]) : + sfd__h519957[51:0] ; + assign _theResult___sfd__h541037 = + sfd__h540399[53] ? + ((_theResult___fst_exp__h540381 == 11'd2046) ? 52'd0 : - sfd__h540398[52:1]) : - sfd__h540398[51:0] ; - assign _theResult___sfd__h550687 = - sfd__h550049[53] ? - ((_theResult___fst_exp__h549957 == 11'd2046) ? + sfd__h540399[52:1]) : + sfd__h540399[51:0] ; + assign _theResult___sfd__h550688 = + sfd__h550050[53] ? + ((_theResult___fst_exp__h549958 == 11'd2046) ? 52'd0 : - sfd__h550049[52:1]) : - sfd__h550049[51:0] ; - assign _theResult___sfd__h559471 = - sfd__h558809[53] ? - ((_theResult___fst_exp__h558790 == 11'd2046) ? + sfd__h550050[52:1]) : + sfd__h550050[51:0] ; + assign _theResult___sfd__h559472 = + sfd__h558810[53] ? + ((_theResult___fst_exp__h558791 == 11'd2046) ? 52'd0 : - sfd__h558809[52:1]) : - sfd__h558809[51:0] ; - assign _theResult___sfd__h580340 = - sfd__h579702[53] ? - ((_theResult___fst_exp__h579684 == 11'd2046) ? + sfd__h558810[52:1]) : + sfd__h558810[51:0] ; + assign _theResult___sfd__h580341 = + sfd__h579703[53] ? + ((_theResult___fst_exp__h579685 == 11'd2046) ? 52'd0 : - sfd__h579702[52:1]) : - sfd__h579702[51:0] ; - assign _theResult___sfd__h589991 = - sfd__h589353[53] ? - ((_theResult___fst_exp__h589261 == 11'd2046) ? + sfd__h579703[52:1]) : + sfd__h579703[51:0] ; + assign _theResult___sfd__h589992 = + sfd__h589354[53] ? + ((_theResult___fst_exp__h589262 == 11'd2046) ? 52'd0 : - sfd__h589353[52:1]) : - sfd__h589353[51:0] ; - assign _theResult___sfd__h598775 = - sfd__h598113[53] ? - ((_theResult___fst_exp__h598094 == 11'd2046) ? + sfd__h589354[52:1]) : + sfd__h589354[51:0] ; + assign _theResult___sfd__h598776 = + sfd__h598114[53] ? + ((_theResult___fst_exp__h598095 == 11'd2046) ? 52'd0 : - sfd__h598113[52:1]) : - sfd__h598113[51:0] ; - assign _theResult___snd__h354206 = { _theResult____h346084[55:0], 1'd0 } ; - assign _theResult___snd__h354217 = - (!_theResult____h346084[56] && _theResult____h346084[55]) ? - _theResult___snd__h354219 : - _theResult___snd__h354229 ; - assign _theResult___snd__h354219 = { _theResult____h346084[54:0], 2'd0 } ; - assign _theResult___snd__h354229 = - (!_theResult____h346084[56] && !_theResult____h346084[55] && - !_theResult____h346084[54] && - !_theResult____h346084[53] && - !_theResult____h346084[52] && - !_theResult____h346084[51] && - !_theResult____h346084[50] && - !_theResult____h346084[49] && - !_theResult____h346084[48] && - !_theResult____h346084[47] && - !_theResult____h346084[46] && - !_theResult____h346084[45] && - !_theResult____h346084[44] && - !_theResult____h346084[43] && - !_theResult____h346084[42] && - !_theResult____h346084[41] && - !_theResult____h346084[40] && - !_theResult____h346084[39] && - !_theResult____h346084[38] && - !_theResult____h346084[37] && - !_theResult____h346084[36] && - !_theResult____h346084[35] && - !_theResult____h346084[34] && - !_theResult____h346084[33] && - !_theResult____h346084[32] && - !_theResult____h346084[31] && - !_theResult____h346084[30] && - !_theResult____h346084[29] && - !_theResult____h346084[28] && - !_theResult____h346084[27] && - !_theResult____h346084[26] && - !_theResult____h346084[25] && - !_theResult____h346084[24] && - !_theResult____h346084[23] && - !_theResult____h346084[22] && - !_theResult____h346084[21] && - !_theResult____h346084[20] && - !_theResult____h346084[19] && - !_theResult____h346084[18] && - !_theResult____h346084[17] && - !_theResult____h346084[16] && - !_theResult____h346084[15] && - !_theResult____h346084[14] && - !_theResult____h346084[13] && - !_theResult____h346084[12] && - !_theResult____h346084[11] && - !_theResult____h346084[10] && - !_theResult____h346084[9] && - !_theResult____h346084[8] && - !_theResult____h346084[7] && - !_theResult____h346084[6] && - !_theResult____h346084[5] && - !_theResult____h346084[4] && - !_theResult____h346084[3] && - !_theResult____h346084[2] && - !_theResult____h346084[1] && - !_theResult____h346084[0]) ? - _theResult____h346084 : - _theResult___snd__h354235 ; - assign _theResult___snd__h354235 = + sfd__h598114[52:1]) : + sfd__h598114[51:0] ; + assign _theResult___snd__h354207 = { _theResult____h346085[55:0], 1'd0 } ; + assign _theResult___snd__h354218 = + (!_theResult____h346085[56] && _theResult____h346085[55]) ? + _theResult___snd__h354220 : + _theResult___snd__h354230 ; + assign _theResult___snd__h354220 = { _theResult____h346085[54:0], 2'd0 } ; + assign _theResult___snd__h354230 = + (!_theResult____h346085[56] && !_theResult____h346085[55] && + !_theResult____h346085[54] && + !_theResult____h346085[53] && + !_theResult____h346085[52] && + !_theResult____h346085[51] && + !_theResult____h346085[50] && + !_theResult____h346085[49] && + !_theResult____h346085[48] && + !_theResult____h346085[47] && + !_theResult____h346085[46] && + !_theResult____h346085[45] && + !_theResult____h346085[44] && + !_theResult____h346085[43] && + !_theResult____h346085[42] && + !_theResult____h346085[41] && + !_theResult____h346085[40] && + !_theResult____h346085[39] && + !_theResult____h346085[38] && + !_theResult____h346085[37] && + !_theResult____h346085[36] && + !_theResult____h346085[35] && + !_theResult____h346085[34] && + !_theResult____h346085[33] && + !_theResult____h346085[32] && + !_theResult____h346085[31] && + !_theResult____h346085[30] && + !_theResult____h346085[29] && + !_theResult____h346085[28] && + !_theResult____h346085[27] && + !_theResult____h346085[26] && + !_theResult____h346085[25] && + !_theResult____h346085[24] && + !_theResult____h346085[23] && + !_theResult____h346085[22] && + !_theResult____h346085[21] && + !_theResult____h346085[20] && + !_theResult____h346085[19] && + !_theResult____h346085[18] && + !_theResult____h346085[17] && + !_theResult____h346085[16] && + !_theResult____h346085[15] && + !_theResult____h346085[14] && + !_theResult____h346085[13] && + !_theResult____h346085[12] && + !_theResult____h346085[11] && + !_theResult____h346085[10] && + !_theResult____h346085[9] && + !_theResult____h346085[8] && + !_theResult____h346085[7] && + !_theResult____h346085[6] && + !_theResult____h346085[5] && + !_theResult____h346085[4] && + !_theResult____h346085[3] && + !_theResult____h346085[2] && + !_theResult____h346085[1] && + !_theResult____h346085[0]) ? + _theResult____h346085 : + _theResult___snd__h354236 ; + assign _theResult___snd__h354236 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0], 2'd0 } ; - assign _theResult___snd__h354258 = - _theResult____h346084 << + assign _theResult___snd__h354259 = + _theResult____h346085 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 ; - assign _theResult___snd__h362802 = + assign _theResult___snd__h362803 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h362811 : - _theResult___snd__h362804 ; - assign _theResult___snd__h362804 = + _theResult___snd__h362812 : + _theResult___snd__h362805 ; + assign _theResult___snd__h362805 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h362811 = + assign _theResult___snd__h362812 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338479 : - _theResult___snd__h362817 ; - assign _theResult___snd__h362817 = + sfd__h338480 : + _theResult___snd__h362818 ; + assign _theResult___snd__h362818 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h362840 = - sfd__h338479 << + assign _theResult___snd__h362841 = + sfd__h338480 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 ; - assign _theResult___snd__h371972 = { _theResult____h363723[55:0], 1'd0 } ; - assign _theResult___snd__h371983 = - (!_theResult____h363723[56] && _theResult____h363723[55]) ? - _theResult___snd__h371985 : - _theResult___snd__h371995 ; - assign _theResult___snd__h371985 = { _theResult____h363723[54:0], 2'd0 } ; - assign _theResult___snd__h371995 = - (!_theResult____h363723[56] && !_theResult____h363723[55] && - !_theResult____h363723[54] && - !_theResult____h363723[53] && - !_theResult____h363723[52] && - !_theResult____h363723[51] && - !_theResult____h363723[50] && - !_theResult____h363723[49] && - !_theResult____h363723[48] && - !_theResult____h363723[47] && - !_theResult____h363723[46] && - !_theResult____h363723[45] && - !_theResult____h363723[44] && - !_theResult____h363723[43] && - !_theResult____h363723[42] && - !_theResult____h363723[41] && - !_theResult____h363723[40] && - !_theResult____h363723[39] && - !_theResult____h363723[38] && - !_theResult____h363723[37] && - !_theResult____h363723[36] && - !_theResult____h363723[35] && - !_theResult____h363723[34] && - !_theResult____h363723[33] && - !_theResult____h363723[32] && - !_theResult____h363723[31] && - !_theResult____h363723[30] && - !_theResult____h363723[29] && - !_theResult____h363723[28] && - !_theResult____h363723[27] && - !_theResult____h363723[26] && - !_theResult____h363723[25] && - !_theResult____h363723[24] && - !_theResult____h363723[23] && - !_theResult____h363723[22] && - !_theResult____h363723[21] && - !_theResult____h363723[20] && - !_theResult____h363723[19] && - !_theResult____h363723[18] && - !_theResult____h363723[17] && - !_theResult____h363723[16] && - !_theResult____h363723[15] && - !_theResult____h363723[14] && - !_theResult____h363723[13] && - !_theResult____h363723[12] && - !_theResult____h363723[11] && - !_theResult____h363723[10] && - !_theResult____h363723[9] && - !_theResult____h363723[8] && - !_theResult____h363723[7] && - !_theResult____h363723[6] && - !_theResult____h363723[5] && - !_theResult____h363723[4] && - !_theResult____h363723[3] && - !_theResult____h363723[2] && - !_theResult____h363723[1] && - !_theResult____h363723[0]) ? - _theResult____h363723 : - _theResult___snd__h372001 ; - assign _theResult___snd__h372001 = + assign _theResult___snd__h371973 = { _theResult____h363724[55:0], 1'd0 } ; + assign _theResult___snd__h371984 = + (!_theResult____h363724[56] && _theResult____h363724[55]) ? + _theResult___snd__h371986 : + _theResult___snd__h371996 ; + assign _theResult___snd__h371986 = { _theResult____h363724[54:0], 2'd0 } ; + assign _theResult___snd__h371996 = + (!_theResult____h363724[56] && !_theResult____h363724[55] && + !_theResult____h363724[54] && + !_theResult____h363724[53] && + !_theResult____h363724[52] && + !_theResult____h363724[51] && + !_theResult____h363724[50] && + !_theResult____h363724[49] && + !_theResult____h363724[48] && + !_theResult____h363724[47] && + !_theResult____h363724[46] && + !_theResult____h363724[45] && + !_theResult____h363724[44] && + !_theResult____h363724[43] && + !_theResult____h363724[42] && + !_theResult____h363724[41] && + !_theResult____h363724[40] && + !_theResult____h363724[39] && + !_theResult____h363724[38] && + !_theResult____h363724[37] && + !_theResult____h363724[36] && + !_theResult____h363724[35] && + !_theResult____h363724[34] && + !_theResult____h363724[33] && + !_theResult____h363724[32] && + !_theResult____h363724[31] && + !_theResult____h363724[30] && + !_theResult____h363724[29] && + !_theResult____h363724[28] && + !_theResult____h363724[27] && + !_theResult____h363724[26] && + !_theResult____h363724[25] && + !_theResult____h363724[24] && + !_theResult____h363724[23] && + !_theResult____h363724[22] && + !_theResult____h363724[21] && + !_theResult____h363724[20] && + !_theResult____h363724[19] && + !_theResult____h363724[18] && + !_theResult____h363724[17] && + !_theResult____h363724[16] && + !_theResult____h363724[15] && + !_theResult____h363724[14] && + !_theResult____h363724[13] && + !_theResult____h363724[12] && + !_theResult____h363724[11] && + !_theResult____h363724[10] && + !_theResult____h363724[9] && + !_theResult____h363724[8] && + !_theResult____h363724[7] && + !_theResult____h363724[6] && + !_theResult____h363724[5] && + !_theResult____h363724[4] && + !_theResult____h363724[3] && + !_theResult____h363724[2] && + !_theResult____h363724[1] && + !_theResult____h363724[0]) ? + _theResult____h363724 : + _theResult___snd__h372002 ; + assign _theResult___snd__h372002 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0], 2'd0 } ; - assign _theResult___snd__h372024 = - _theResult____h363723 << + assign _theResult___snd__h372025 = + _theResult____h363724 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 ; - assign _theResult___snd__h380592 = + assign _theResult___snd__h380593 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h380606 : - _theResult___snd__h362804 ; - assign _theResult___snd__h380606 = + _theResult___snd__h380607 : + _theResult___snd__h362805 ; + assign _theResult___snd__h380607 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338479 : - _theResult___snd__h380612 ; - assign _theResult___snd__h380612 = + sfd__h338480 : + _theResult___snd__h380613 ; + assign _theResult___snd__h380613 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0], 2'd0 } ; - assign _theResult___snd__h380630 = - sfd__h338479 << + assign _theResult___snd__h380631 = + sfd__h338480 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872) ; - assign _theResult___snd__h399903 = { _theResult____h391783[55:0], 1'd0 } ; - assign _theResult___snd__h399914 = - (!_theResult____h391783[56] && _theResult____h391783[55]) ? - _theResult___snd__h399916 : - _theResult___snd__h399926 ; - assign _theResult___snd__h399916 = { _theResult____h391783[54:0], 2'd0 } ; - assign _theResult___snd__h399926 = - (!_theResult____h391783[56] && !_theResult____h391783[55] && - !_theResult____h391783[54] && - !_theResult____h391783[53] && - !_theResult____h391783[52] && - !_theResult____h391783[51] && - !_theResult____h391783[50] && - !_theResult____h391783[49] && - !_theResult____h391783[48] && - !_theResult____h391783[47] && - !_theResult____h391783[46] && - !_theResult____h391783[45] && - !_theResult____h391783[44] && - !_theResult____h391783[43] && - !_theResult____h391783[42] && - !_theResult____h391783[41] && - !_theResult____h391783[40] && - !_theResult____h391783[39] && - !_theResult____h391783[38] && - !_theResult____h391783[37] && - !_theResult____h391783[36] && - !_theResult____h391783[35] && - !_theResult____h391783[34] && - !_theResult____h391783[33] && - !_theResult____h391783[32] && - !_theResult____h391783[31] && - !_theResult____h391783[30] && - !_theResult____h391783[29] && - !_theResult____h391783[28] && - !_theResult____h391783[27] && - !_theResult____h391783[26] && - !_theResult____h391783[25] && - !_theResult____h391783[24] && - !_theResult____h391783[23] && - !_theResult____h391783[22] && - !_theResult____h391783[21] && - !_theResult____h391783[20] && - !_theResult____h391783[19] && - !_theResult____h391783[18] && - !_theResult____h391783[17] && - !_theResult____h391783[16] && - !_theResult____h391783[15] && - !_theResult____h391783[14] && - !_theResult____h391783[13] && - !_theResult____h391783[12] && - !_theResult____h391783[11] && - !_theResult____h391783[10] && - !_theResult____h391783[9] && - !_theResult____h391783[8] && - !_theResult____h391783[7] && - !_theResult____h391783[6] && - !_theResult____h391783[5] && - !_theResult____h391783[4] && - !_theResult____h391783[3] && - !_theResult____h391783[2] && - !_theResult____h391783[1] && - !_theResult____h391783[0]) ? - _theResult____h391783 : - _theResult___snd__h399932 ; - assign _theResult___snd__h399932 = + assign _theResult___snd__h399904 = { _theResult____h391784[55:0], 1'd0 } ; + assign _theResult___snd__h399915 = + (!_theResult____h391784[56] && _theResult____h391784[55]) ? + _theResult___snd__h399917 : + _theResult___snd__h399927 ; + assign _theResult___snd__h399917 = { _theResult____h391784[54:0], 2'd0 } ; + assign _theResult___snd__h399927 = + (!_theResult____h391784[56] && !_theResult____h391784[55] && + !_theResult____h391784[54] && + !_theResult____h391784[53] && + !_theResult____h391784[52] && + !_theResult____h391784[51] && + !_theResult____h391784[50] && + !_theResult____h391784[49] && + !_theResult____h391784[48] && + !_theResult____h391784[47] && + !_theResult____h391784[46] && + !_theResult____h391784[45] && + !_theResult____h391784[44] && + !_theResult____h391784[43] && + !_theResult____h391784[42] && + !_theResult____h391784[41] && + !_theResult____h391784[40] && + !_theResult____h391784[39] && + !_theResult____h391784[38] && + !_theResult____h391784[37] && + !_theResult____h391784[36] && + !_theResult____h391784[35] && + !_theResult____h391784[34] && + !_theResult____h391784[33] && + !_theResult____h391784[32] && + !_theResult____h391784[31] && + !_theResult____h391784[30] && + !_theResult____h391784[29] && + !_theResult____h391784[28] && + !_theResult____h391784[27] && + !_theResult____h391784[26] && + !_theResult____h391784[25] && + !_theResult____h391784[24] && + !_theResult____h391784[23] && + !_theResult____h391784[22] && + !_theResult____h391784[21] && + !_theResult____h391784[20] && + !_theResult____h391784[19] && + !_theResult____h391784[18] && + !_theResult____h391784[17] && + !_theResult____h391784[16] && + !_theResult____h391784[15] && + !_theResult____h391784[14] && + !_theResult____h391784[13] && + !_theResult____h391784[12] && + !_theResult____h391784[11] && + !_theResult____h391784[10] && + !_theResult____h391784[9] && + !_theResult____h391784[8] && + !_theResult____h391784[7] && + !_theResult____h391784[6] && + !_theResult____h391784[5] && + !_theResult____h391784[4] && + !_theResult____h391784[3] && + !_theResult____h391784[2] && + !_theResult____h391784[1] && + !_theResult____h391784[0]) ? + _theResult____h391784 : + _theResult___snd__h399933 ; + assign _theResult___snd__h399933 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0], 2'd0 } ; - assign _theResult___snd__h399955 = - _theResult____h391783 << + assign _theResult___snd__h399956 = + _theResult____h391784 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 ; - assign _theResult___snd__h408499 = + assign _theResult___snd__h408500 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h408508 : - _theResult___snd__h408501 ; - assign _theResult___snd__h408501 = + _theResult___snd__h408509 : + _theResult___snd__h408502 ; + assign _theResult___snd__h408502 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h408508 = + assign _theResult___snd__h408509 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384181 : - _theResult___snd__h408514 ; - assign _theResult___snd__h408514 = + sfd__h384182 : + _theResult___snd__h408515 ; + assign _theResult___snd__h408515 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h408537 = - sfd__h384181 << + assign _theResult___snd__h408538 = + sfd__h384182 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 ; - assign _theResult___snd__h417669 = { _theResult____h409420[55:0], 1'd0 } ; - assign _theResult___snd__h417680 = - (!_theResult____h409420[56] && _theResult____h409420[55]) ? - _theResult___snd__h417682 : - _theResult___snd__h417692 ; - assign _theResult___snd__h417682 = { _theResult____h409420[54:0], 2'd0 } ; - assign _theResult___snd__h417692 = - (!_theResult____h409420[56] && !_theResult____h409420[55] && - !_theResult____h409420[54] && - !_theResult____h409420[53] && - !_theResult____h409420[52] && - !_theResult____h409420[51] && - !_theResult____h409420[50] && - !_theResult____h409420[49] && - !_theResult____h409420[48] && - !_theResult____h409420[47] && - !_theResult____h409420[46] && - !_theResult____h409420[45] && - !_theResult____h409420[44] && - !_theResult____h409420[43] && - !_theResult____h409420[42] && - !_theResult____h409420[41] && - !_theResult____h409420[40] && - !_theResult____h409420[39] && - !_theResult____h409420[38] && - !_theResult____h409420[37] && - !_theResult____h409420[36] && - !_theResult____h409420[35] && - !_theResult____h409420[34] && - !_theResult____h409420[33] && - !_theResult____h409420[32] && - !_theResult____h409420[31] && - !_theResult____h409420[30] && - !_theResult____h409420[29] && - !_theResult____h409420[28] && - !_theResult____h409420[27] && - !_theResult____h409420[26] && - !_theResult____h409420[25] && - !_theResult____h409420[24] && - !_theResult____h409420[23] && - !_theResult____h409420[22] && - !_theResult____h409420[21] && - !_theResult____h409420[20] && - !_theResult____h409420[19] && - !_theResult____h409420[18] && - !_theResult____h409420[17] && - !_theResult____h409420[16] && - !_theResult____h409420[15] && - !_theResult____h409420[14] && - !_theResult____h409420[13] && - !_theResult____h409420[12] && - !_theResult____h409420[11] && - !_theResult____h409420[10] && - !_theResult____h409420[9] && - !_theResult____h409420[8] && - !_theResult____h409420[7] && - !_theResult____h409420[6] && - !_theResult____h409420[5] && - !_theResult____h409420[4] && - !_theResult____h409420[3] && - !_theResult____h409420[2] && - !_theResult____h409420[1] && - !_theResult____h409420[0]) ? - _theResult____h409420 : - _theResult___snd__h417698 ; - assign _theResult___snd__h417698 = + assign _theResult___snd__h417670 = { _theResult____h409421[55:0], 1'd0 } ; + assign _theResult___snd__h417681 = + (!_theResult____h409421[56] && _theResult____h409421[55]) ? + _theResult___snd__h417683 : + _theResult___snd__h417693 ; + assign _theResult___snd__h417683 = { _theResult____h409421[54:0], 2'd0 } ; + assign _theResult___snd__h417693 = + (!_theResult____h409421[56] && !_theResult____h409421[55] && + !_theResult____h409421[54] && + !_theResult____h409421[53] && + !_theResult____h409421[52] && + !_theResult____h409421[51] && + !_theResult____h409421[50] && + !_theResult____h409421[49] && + !_theResult____h409421[48] && + !_theResult____h409421[47] && + !_theResult____h409421[46] && + !_theResult____h409421[45] && + !_theResult____h409421[44] && + !_theResult____h409421[43] && + !_theResult____h409421[42] && + !_theResult____h409421[41] && + !_theResult____h409421[40] && + !_theResult____h409421[39] && + !_theResult____h409421[38] && + !_theResult____h409421[37] && + !_theResult____h409421[36] && + !_theResult____h409421[35] && + !_theResult____h409421[34] && + !_theResult____h409421[33] && + !_theResult____h409421[32] && + !_theResult____h409421[31] && + !_theResult____h409421[30] && + !_theResult____h409421[29] && + !_theResult____h409421[28] && + !_theResult____h409421[27] && + !_theResult____h409421[26] && + !_theResult____h409421[25] && + !_theResult____h409421[24] && + !_theResult____h409421[23] && + !_theResult____h409421[22] && + !_theResult____h409421[21] && + !_theResult____h409421[20] && + !_theResult____h409421[19] && + !_theResult____h409421[18] && + !_theResult____h409421[17] && + !_theResult____h409421[16] && + !_theResult____h409421[15] && + !_theResult____h409421[14] && + !_theResult____h409421[13] && + !_theResult____h409421[12] && + !_theResult____h409421[11] && + !_theResult____h409421[10] && + !_theResult____h409421[9] && + !_theResult____h409421[8] && + !_theResult____h409421[7] && + !_theResult____h409421[6] && + !_theResult____h409421[5] && + !_theResult____h409421[4] && + !_theResult____h409421[3] && + !_theResult____h409421[2] && + !_theResult____h409421[1] && + !_theResult____h409421[0]) ? + _theResult____h409421 : + _theResult___snd__h417699 ; + assign _theResult___snd__h417699 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0], 2'd0 } ; - assign _theResult___snd__h417721 = - _theResult____h409420 << + assign _theResult___snd__h417722 = + _theResult____h409421 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 ; - assign _theResult___snd__h426289 = + assign _theResult___snd__h426290 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h426303 : - _theResult___snd__h408501 ; - assign _theResult___snd__h426303 = + _theResult___snd__h426304 : + _theResult___snd__h408502 ; + assign _theResult___snd__h426304 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384181 : - _theResult___snd__h426309 ; - assign _theResult___snd__h426309 = + sfd__h384182 : + _theResult___snd__h426310 ; + assign _theResult___snd__h426310 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0], 2'd0 } ; - assign _theResult___snd__h426327 = - sfd__h384181 << + assign _theResult___snd__h426328 = + sfd__h384182 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264) ; - assign _theResult___snd__h445598 = { _theResult____h437478[55:0], 1'd0 } ; - assign _theResult___snd__h445609 = - (!_theResult____h437478[56] && _theResult____h437478[55]) ? - _theResult___snd__h445611 : - _theResult___snd__h445621 ; - assign _theResult___snd__h445611 = { _theResult____h437478[54:0], 2'd0 } ; - assign _theResult___snd__h445621 = - (!_theResult____h437478[56] && !_theResult____h437478[55] && - !_theResult____h437478[54] && - !_theResult____h437478[53] && - !_theResult____h437478[52] && - !_theResult____h437478[51] && - !_theResult____h437478[50] && - !_theResult____h437478[49] && - !_theResult____h437478[48] && - !_theResult____h437478[47] && - !_theResult____h437478[46] && - !_theResult____h437478[45] && - !_theResult____h437478[44] && - !_theResult____h437478[43] && - !_theResult____h437478[42] && - !_theResult____h437478[41] && - !_theResult____h437478[40] && - !_theResult____h437478[39] && - !_theResult____h437478[38] && - !_theResult____h437478[37] && - !_theResult____h437478[36] && - !_theResult____h437478[35] && - !_theResult____h437478[34] && - !_theResult____h437478[33] && - !_theResult____h437478[32] && - !_theResult____h437478[31] && - !_theResult____h437478[30] && - !_theResult____h437478[29] && - !_theResult____h437478[28] && - !_theResult____h437478[27] && - !_theResult____h437478[26] && - !_theResult____h437478[25] && - !_theResult____h437478[24] && - !_theResult____h437478[23] && - !_theResult____h437478[22] && - !_theResult____h437478[21] && - !_theResult____h437478[20] && - !_theResult____h437478[19] && - !_theResult____h437478[18] && - !_theResult____h437478[17] && - !_theResult____h437478[16] && - !_theResult____h437478[15] && - !_theResult____h437478[14] && - !_theResult____h437478[13] && - !_theResult____h437478[12] && - !_theResult____h437478[11] && - !_theResult____h437478[10] && - !_theResult____h437478[9] && - !_theResult____h437478[8] && - !_theResult____h437478[7] && - !_theResult____h437478[6] && - !_theResult____h437478[5] && - !_theResult____h437478[4] && - !_theResult____h437478[3] && - !_theResult____h437478[2] && - !_theResult____h437478[1] && - !_theResult____h437478[0]) ? - _theResult____h437478 : - _theResult___snd__h445627 ; - assign _theResult___snd__h445627 = + assign _theResult___snd__h445599 = { _theResult____h437479[55:0], 1'd0 } ; + assign _theResult___snd__h445610 = + (!_theResult____h437479[56] && _theResult____h437479[55]) ? + _theResult___snd__h445612 : + _theResult___snd__h445622 ; + assign _theResult___snd__h445612 = { _theResult____h437479[54:0], 2'd0 } ; + assign _theResult___snd__h445622 = + (!_theResult____h437479[56] && !_theResult____h437479[55] && + !_theResult____h437479[54] && + !_theResult____h437479[53] && + !_theResult____h437479[52] && + !_theResult____h437479[51] && + !_theResult____h437479[50] && + !_theResult____h437479[49] && + !_theResult____h437479[48] && + !_theResult____h437479[47] && + !_theResult____h437479[46] && + !_theResult____h437479[45] && + !_theResult____h437479[44] && + !_theResult____h437479[43] && + !_theResult____h437479[42] && + !_theResult____h437479[41] && + !_theResult____h437479[40] && + !_theResult____h437479[39] && + !_theResult____h437479[38] && + !_theResult____h437479[37] && + !_theResult____h437479[36] && + !_theResult____h437479[35] && + !_theResult____h437479[34] && + !_theResult____h437479[33] && + !_theResult____h437479[32] && + !_theResult____h437479[31] && + !_theResult____h437479[30] && + !_theResult____h437479[29] && + !_theResult____h437479[28] && + !_theResult____h437479[27] && + !_theResult____h437479[26] && + !_theResult____h437479[25] && + !_theResult____h437479[24] && + !_theResult____h437479[23] && + !_theResult____h437479[22] && + !_theResult____h437479[21] && + !_theResult____h437479[20] && + !_theResult____h437479[19] && + !_theResult____h437479[18] && + !_theResult____h437479[17] && + !_theResult____h437479[16] && + !_theResult____h437479[15] && + !_theResult____h437479[14] && + !_theResult____h437479[13] && + !_theResult____h437479[12] && + !_theResult____h437479[11] && + !_theResult____h437479[10] && + !_theResult____h437479[9] && + !_theResult____h437479[8] && + !_theResult____h437479[7] && + !_theResult____h437479[6] && + !_theResult____h437479[5] && + !_theResult____h437479[4] && + !_theResult____h437479[3] && + !_theResult____h437479[2] && + !_theResult____h437479[1] && + !_theResult____h437479[0]) ? + _theResult____h437479 : + _theResult___snd__h445628 ; + assign _theResult___snd__h445628 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0], 2'd0 } ; - assign _theResult___snd__h445650 = - _theResult____h437478 << + assign _theResult___snd__h445651 = + _theResult____h437479 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 ; - assign _theResult___snd__h454194 = + assign _theResult___snd__h454195 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h454203 : - _theResult___snd__h454196 ; - assign _theResult___snd__h454196 = + _theResult___snd__h454204 : + _theResult___snd__h454197 ; + assign _theResult___snd__h454197 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h454203 = + assign _theResult___snd__h454204 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429876 : - _theResult___snd__h454209 ; - assign _theResult___snd__h454209 = + sfd__h429877 : + _theResult___snd__h454210 ; + assign _theResult___snd__h454210 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h454232 = - sfd__h429876 << + assign _theResult___snd__h454233 = + sfd__h429877 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 ; - assign _theResult___snd__h463364 = { _theResult____h455115[55:0], 1'd0 } ; - assign _theResult___snd__h463375 = - (!_theResult____h455115[56] && _theResult____h455115[55]) ? - _theResult___snd__h463377 : - _theResult___snd__h463387 ; - assign _theResult___snd__h463377 = { _theResult____h455115[54:0], 2'd0 } ; - assign _theResult___snd__h463387 = - (!_theResult____h455115[56] && !_theResult____h455115[55] && - !_theResult____h455115[54] && - !_theResult____h455115[53] && - !_theResult____h455115[52] && - !_theResult____h455115[51] && - !_theResult____h455115[50] && - !_theResult____h455115[49] && - !_theResult____h455115[48] && - !_theResult____h455115[47] && - !_theResult____h455115[46] && - !_theResult____h455115[45] && - !_theResult____h455115[44] && - !_theResult____h455115[43] && - !_theResult____h455115[42] && - !_theResult____h455115[41] && - !_theResult____h455115[40] && - !_theResult____h455115[39] && - !_theResult____h455115[38] && - !_theResult____h455115[37] && - !_theResult____h455115[36] && - !_theResult____h455115[35] && - !_theResult____h455115[34] && - !_theResult____h455115[33] && - !_theResult____h455115[32] && - !_theResult____h455115[31] && - !_theResult____h455115[30] && - !_theResult____h455115[29] && - !_theResult____h455115[28] && - !_theResult____h455115[27] && - !_theResult____h455115[26] && - !_theResult____h455115[25] && - !_theResult____h455115[24] && - !_theResult____h455115[23] && - !_theResult____h455115[22] && - !_theResult____h455115[21] && - !_theResult____h455115[20] && - !_theResult____h455115[19] && - !_theResult____h455115[18] && - !_theResult____h455115[17] && - !_theResult____h455115[16] && - !_theResult____h455115[15] && - !_theResult____h455115[14] && - !_theResult____h455115[13] && - !_theResult____h455115[12] && - !_theResult____h455115[11] && - !_theResult____h455115[10] && - !_theResult____h455115[9] && - !_theResult____h455115[8] && - !_theResult____h455115[7] && - !_theResult____h455115[6] && - !_theResult____h455115[5] && - !_theResult____h455115[4] && - !_theResult____h455115[3] && - !_theResult____h455115[2] && - !_theResult____h455115[1] && - !_theResult____h455115[0]) ? - _theResult____h455115 : - _theResult___snd__h463393 ; - assign _theResult___snd__h463393 = + assign _theResult___snd__h463365 = { _theResult____h455116[55:0], 1'd0 } ; + assign _theResult___snd__h463376 = + (!_theResult____h455116[56] && _theResult____h455116[55]) ? + _theResult___snd__h463378 : + _theResult___snd__h463388 ; + assign _theResult___snd__h463378 = { _theResult____h455116[54:0], 2'd0 } ; + assign _theResult___snd__h463388 = + (!_theResult____h455116[56] && !_theResult____h455116[55] && + !_theResult____h455116[54] && + !_theResult____h455116[53] && + !_theResult____h455116[52] && + !_theResult____h455116[51] && + !_theResult____h455116[50] && + !_theResult____h455116[49] && + !_theResult____h455116[48] && + !_theResult____h455116[47] && + !_theResult____h455116[46] && + !_theResult____h455116[45] && + !_theResult____h455116[44] && + !_theResult____h455116[43] && + !_theResult____h455116[42] && + !_theResult____h455116[41] && + !_theResult____h455116[40] && + !_theResult____h455116[39] && + !_theResult____h455116[38] && + !_theResult____h455116[37] && + !_theResult____h455116[36] && + !_theResult____h455116[35] && + !_theResult____h455116[34] && + !_theResult____h455116[33] && + !_theResult____h455116[32] && + !_theResult____h455116[31] && + !_theResult____h455116[30] && + !_theResult____h455116[29] && + !_theResult____h455116[28] && + !_theResult____h455116[27] && + !_theResult____h455116[26] && + !_theResult____h455116[25] && + !_theResult____h455116[24] && + !_theResult____h455116[23] && + !_theResult____h455116[22] && + !_theResult____h455116[21] && + !_theResult____h455116[20] && + !_theResult____h455116[19] && + !_theResult____h455116[18] && + !_theResult____h455116[17] && + !_theResult____h455116[16] && + !_theResult____h455116[15] && + !_theResult____h455116[14] && + !_theResult____h455116[13] && + !_theResult____h455116[12] && + !_theResult____h455116[11] && + !_theResult____h455116[10] && + !_theResult____h455116[9] && + !_theResult____h455116[8] && + !_theResult____h455116[7] && + !_theResult____h455116[6] && + !_theResult____h455116[5] && + !_theResult____h455116[4] && + !_theResult____h455116[3] && + !_theResult____h455116[2] && + !_theResult____h455116[1] && + !_theResult____h455116[0]) ? + _theResult____h455116 : + _theResult___snd__h463394 ; + assign _theResult___snd__h463394 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0], 2'd0 } ; - assign _theResult___snd__h463416 = - _theResult____h455115 << + assign _theResult___snd__h463417 = + _theResult____h455116 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 ; - assign _theResult___snd__h471984 = + assign _theResult___snd__h471985 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h471998 : - _theResult___snd__h454196 ; - assign _theResult___snd__h471998 = + _theResult___snd__h471999 : + _theResult___snd__h454197 ; + assign _theResult___snd__h471999 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429876 : - _theResult___snd__h472004 ; - assign _theResult___snd__h472004 = + sfd__h429877 : + _theResult___snd__h472005 ; + assign _theResult___snd__h472005 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0], 2'd0 } ; - assign _theResult___snd__h472022 = - sfd__h429876 << + assign _theResult___snd__h472023 = + sfd__h429877 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656) ; - assign _theResult___snd__h501478 = - (f1_exp__h482139 == 8'd0) ? - _theResult___snd__h501487 : - _theResult___snd__h501480 ; - assign _theResult___snd__h501480 = { f1_sfd__h482140, 34'd0 } ; - assign _theResult___snd__h501487 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___snd__h501479 = + (f1_exp__h482140 == 8'd0) ? + _theResult___snd__h501488 : + _theResult___snd__h501481 ; + assign _theResult___snd__h501481 = { f1_sfd__h482141, 34'd0 } ; + assign _theResult___snd__h501488 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482501 : - _theResult___snd__h501493 ; - assign _theResult___snd__h501493 = + sfd__h482502 : + _theResult___snd__h501494 ; + assign _theResult___snd__h501494 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h501516 = - sfd__h482501 << + assign _theResult___snd__h501517 = + sfd__h482502 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 ; - assign _theResult___snd__h511115 = { _theResult____h502868[55:0], 1'd0 } ; - assign _theResult___snd__h511126 = - (!_theResult____h502868[56] && _theResult____h502868[55]) ? - _theResult___snd__h511128 : - _theResult___snd__h511138 ; - assign _theResult___snd__h511128 = { _theResult____h502868[54:0], 2'd0 } ; - assign _theResult___snd__h511138 = - (!_theResult____h502868[56] && !_theResult____h502868[55] && - !_theResult____h502868[54] && - !_theResult____h502868[53] && - !_theResult____h502868[52] && - !_theResult____h502868[51] && - !_theResult____h502868[50] && - !_theResult____h502868[49] && - !_theResult____h502868[48] && - !_theResult____h502868[47] && - !_theResult____h502868[46] && - !_theResult____h502868[45] && - !_theResult____h502868[44] && - !_theResult____h502868[43] && - !_theResult____h502868[42] && - !_theResult____h502868[41] && - !_theResult____h502868[40] && - !_theResult____h502868[39] && - !_theResult____h502868[38] && - !_theResult____h502868[37] && - !_theResult____h502868[36] && - !_theResult____h502868[35] && - !_theResult____h502868[34] && - !_theResult____h502868[33] && - !_theResult____h502868[32] && - !_theResult____h502868[31] && - !_theResult____h502868[30] && - !_theResult____h502868[29] && - !_theResult____h502868[28] && - !_theResult____h502868[27] && - !_theResult____h502868[26] && - !_theResult____h502868[25] && - !_theResult____h502868[24] && - !_theResult____h502868[23] && - !_theResult____h502868[22] && - !_theResult____h502868[21] && - !_theResult____h502868[20] && - !_theResult____h502868[19] && - !_theResult____h502868[18] && - !_theResult____h502868[17] && - !_theResult____h502868[16] && - !_theResult____h502868[15] && - !_theResult____h502868[14] && - !_theResult____h502868[13] && - !_theResult____h502868[12] && - !_theResult____h502868[11] && - !_theResult____h502868[10] && - !_theResult____h502868[9] && - !_theResult____h502868[8] && - !_theResult____h502868[7] && - !_theResult____h502868[6] && - !_theResult____h502868[5] && - !_theResult____h502868[4] && - !_theResult____h502868[3] && - !_theResult____h502868[2] && - !_theResult____h502868[1] && - !_theResult____h502868[0]) ? - _theResult____h502868 : - _theResult___snd__h511144 ; - assign _theResult___snd__h511144 = + assign _theResult___snd__h511116 = { _theResult____h502869[55:0], 1'd0 } ; + assign _theResult___snd__h511127 = + (!_theResult____h502869[56] && _theResult____h502869[55]) ? + _theResult___snd__h511129 : + _theResult___snd__h511139 ; + assign _theResult___snd__h511129 = { _theResult____h502869[54:0], 2'd0 } ; + assign _theResult___snd__h511139 = + (!_theResult____h502869[56] && !_theResult____h502869[55] && + !_theResult____h502869[54] && + !_theResult____h502869[53] && + !_theResult____h502869[52] && + !_theResult____h502869[51] && + !_theResult____h502869[50] && + !_theResult____h502869[49] && + !_theResult____h502869[48] && + !_theResult____h502869[47] && + !_theResult____h502869[46] && + !_theResult____h502869[45] && + !_theResult____h502869[44] && + !_theResult____h502869[43] && + !_theResult____h502869[42] && + !_theResult____h502869[41] && + !_theResult____h502869[40] && + !_theResult____h502869[39] && + !_theResult____h502869[38] && + !_theResult____h502869[37] && + !_theResult____h502869[36] && + !_theResult____h502869[35] && + !_theResult____h502869[34] && + !_theResult____h502869[33] && + !_theResult____h502869[32] && + !_theResult____h502869[31] && + !_theResult____h502869[30] && + !_theResult____h502869[29] && + !_theResult____h502869[28] && + !_theResult____h502869[27] && + !_theResult____h502869[26] && + !_theResult____h502869[25] && + !_theResult____h502869[24] && + !_theResult____h502869[23] && + !_theResult____h502869[22] && + !_theResult____h502869[21] && + !_theResult____h502869[20] && + !_theResult____h502869[19] && + !_theResult____h502869[18] && + !_theResult____h502869[17] && + !_theResult____h502869[16] && + !_theResult____h502869[15] && + !_theResult____h502869[14] && + !_theResult____h502869[13] && + !_theResult____h502869[12] && + !_theResult____h502869[11] && + !_theResult____h502869[10] && + !_theResult____h502869[9] && + !_theResult____h502869[8] && + !_theResult____h502869[7] && + !_theResult____h502869[6] && + !_theResult____h502869[5] && + !_theResult____h502869[4] && + !_theResult____h502869[3] && + !_theResult____h502869[2] && + !_theResult____h502869[1] && + !_theResult____h502869[0]) ? + _theResult____h502869 : + _theResult___snd__h511145 ; + assign _theResult___snd__h511145 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h511167 = - _theResult____h502868 << + assign _theResult___snd__h511168 = + _theResult____h502869 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 ; - assign _theResult___snd__h519883 = - (f1_exp__h482139 == 8'd0) ? - _theResult___snd__h519897 : - _theResult___snd__h501480 ; - assign _theResult___snd__h519897 = - (f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] && + assign _theResult___snd__h519884 = + (f1_exp__h482140 == 8'd0) ? + _theResult___snd__h519898 : + _theResult___snd__h501481 ; + assign _theResult___snd__h519898 = + (f1_exp__h482140 == 8'd0 && !f1_sfd__h482141[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482501 : - _theResult___snd__h519903 ; - assign _theResult___snd__h519903 = + sfd__h482502 : + _theResult___snd__h519904 ; + assign _theResult___snd__h519904 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h519921 = - sfd__h482501 << + assign _theResult___snd__h519922 = + sfd__h482502 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ; - assign _theResult___snd__h540331 = - (f2_exp__h521133 == 8'd0) ? - _theResult___snd__h540340 : - _theResult___snd__h540333 ; - assign _theResult___snd__h540333 = { f2_sfd__h521134, 34'd0 } ; - assign _theResult___snd__h540340 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___snd__h540332 = + (f2_exp__h521134 == 8'd0) ? + _theResult___snd__h540341 : + _theResult___snd__h540334 ; + assign _theResult___snd__h540334 = { f2_sfd__h521135, 34'd0 } ; + assign _theResult___snd__h540341 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521495 : - _theResult___snd__h540346 ; - assign _theResult___snd__h540346 = + sfd__h521496 : + _theResult___snd__h540347 ; + assign _theResult___snd__h540347 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h540369 = - sfd__h521495 << + assign _theResult___snd__h540370 = + sfd__h521496 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 ; - assign _theResult___snd__h549968 = { _theResult____h541721[55:0], 1'd0 } ; - assign _theResult___snd__h549979 = - (!_theResult____h541721[56] && _theResult____h541721[55]) ? - _theResult___snd__h549981 : - _theResult___snd__h549991 ; - assign _theResult___snd__h549981 = { _theResult____h541721[54:0], 2'd0 } ; - assign _theResult___snd__h549991 = - (!_theResult____h541721[56] && !_theResult____h541721[55] && - !_theResult____h541721[54] && - !_theResult____h541721[53] && - !_theResult____h541721[52] && - !_theResult____h541721[51] && - !_theResult____h541721[50] && - !_theResult____h541721[49] && - !_theResult____h541721[48] && - !_theResult____h541721[47] && - !_theResult____h541721[46] && - !_theResult____h541721[45] && - !_theResult____h541721[44] && - !_theResult____h541721[43] && - !_theResult____h541721[42] && - !_theResult____h541721[41] && - !_theResult____h541721[40] && - !_theResult____h541721[39] && - !_theResult____h541721[38] && - !_theResult____h541721[37] && - !_theResult____h541721[36] && - !_theResult____h541721[35] && - !_theResult____h541721[34] && - !_theResult____h541721[33] && - !_theResult____h541721[32] && - !_theResult____h541721[31] && - !_theResult____h541721[30] && - !_theResult____h541721[29] && - !_theResult____h541721[28] && - !_theResult____h541721[27] && - !_theResult____h541721[26] && - !_theResult____h541721[25] && - !_theResult____h541721[24] && - !_theResult____h541721[23] && - !_theResult____h541721[22] && - !_theResult____h541721[21] && - !_theResult____h541721[20] && - !_theResult____h541721[19] && - !_theResult____h541721[18] && - !_theResult____h541721[17] && - !_theResult____h541721[16] && - !_theResult____h541721[15] && - !_theResult____h541721[14] && - !_theResult____h541721[13] && - !_theResult____h541721[12] && - !_theResult____h541721[11] && - !_theResult____h541721[10] && - !_theResult____h541721[9] && - !_theResult____h541721[8] && - !_theResult____h541721[7] && - !_theResult____h541721[6] && - !_theResult____h541721[5] && - !_theResult____h541721[4] && - !_theResult____h541721[3] && - !_theResult____h541721[2] && - !_theResult____h541721[1] && - !_theResult____h541721[0]) ? - _theResult____h541721 : - _theResult___snd__h549997 ; - assign _theResult___snd__h549997 = + assign _theResult___snd__h549969 = { _theResult____h541722[55:0], 1'd0 } ; + assign _theResult___snd__h549980 = + (!_theResult____h541722[56] && _theResult____h541722[55]) ? + _theResult___snd__h549982 : + _theResult___snd__h549992 ; + assign _theResult___snd__h549982 = { _theResult____h541722[54:0], 2'd0 } ; + assign _theResult___snd__h549992 = + (!_theResult____h541722[56] && !_theResult____h541722[55] && + !_theResult____h541722[54] && + !_theResult____h541722[53] && + !_theResult____h541722[52] && + !_theResult____h541722[51] && + !_theResult____h541722[50] && + !_theResult____h541722[49] && + !_theResult____h541722[48] && + !_theResult____h541722[47] && + !_theResult____h541722[46] && + !_theResult____h541722[45] && + !_theResult____h541722[44] && + !_theResult____h541722[43] && + !_theResult____h541722[42] && + !_theResult____h541722[41] && + !_theResult____h541722[40] && + !_theResult____h541722[39] && + !_theResult____h541722[38] && + !_theResult____h541722[37] && + !_theResult____h541722[36] && + !_theResult____h541722[35] && + !_theResult____h541722[34] && + !_theResult____h541722[33] && + !_theResult____h541722[32] && + !_theResult____h541722[31] && + !_theResult____h541722[30] && + !_theResult____h541722[29] && + !_theResult____h541722[28] && + !_theResult____h541722[27] && + !_theResult____h541722[26] && + !_theResult____h541722[25] && + !_theResult____h541722[24] && + !_theResult____h541722[23] && + !_theResult____h541722[22] && + !_theResult____h541722[21] && + !_theResult____h541722[20] && + !_theResult____h541722[19] && + !_theResult____h541722[18] && + !_theResult____h541722[17] && + !_theResult____h541722[16] && + !_theResult____h541722[15] && + !_theResult____h541722[14] && + !_theResult____h541722[13] && + !_theResult____h541722[12] && + !_theResult____h541722[11] && + !_theResult____h541722[10] && + !_theResult____h541722[9] && + !_theResult____h541722[8] && + !_theResult____h541722[7] && + !_theResult____h541722[6] && + !_theResult____h541722[5] && + !_theResult____h541722[4] && + !_theResult____h541722[3] && + !_theResult____h541722[2] && + !_theResult____h541722[1] && + !_theResult____h541722[0]) ? + _theResult____h541722 : + _theResult___snd__h549998 ; + assign _theResult___snd__h549998 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h550020 = - _theResult____h541721 << + assign _theResult___snd__h550021 = + _theResult____h541722 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 ; - assign _theResult___snd__h558736 = - (f2_exp__h521133 == 8'd0) ? - _theResult___snd__h558750 : - _theResult___snd__h540333 ; - assign _theResult___snd__h558750 = - (f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] && + assign _theResult___snd__h558737 = + (f2_exp__h521134 == 8'd0) ? + _theResult___snd__h558751 : + _theResult___snd__h540334 ; + assign _theResult___snd__h558751 = + (f2_exp__h521134 == 8'd0 && !f2_sfd__h521135[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521495 : - _theResult___snd__h558756 ; - assign _theResult___snd__h558756 = + sfd__h521496 : + _theResult___snd__h558757 ; + assign _theResult___snd__h558757 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h558774 = - sfd__h521495 << + assign _theResult___snd__h558775 = + sfd__h521496 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ; - assign _theResult___snd__h579635 = - (f3_exp__h560437 == 8'd0) ? - _theResult___snd__h579644 : - _theResult___snd__h579637 ; - assign _theResult___snd__h579637 = { f3_sfd__h560438, 34'd0 } ; - assign _theResult___snd__h579644 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___snd__h579636 = + (f3_exp__h560438 == 8'd0) ? + _theResult___snd__h579645 : + _theResult___snd__h579638 ; + assign _theResult___snd__h579638 = { f3_sfd__h560439, 34'd0 } ; + assign _theResult___snd__h579645 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560799 : - _theResult___snd__h579650 ; - assign _theResult___snd__h579650 = + sfd__h560800 : + _theResult___snd__h579651 ; + assign _theResult___snd__h579651 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h579673 = - sfd__h560799 << + assign _theResult___snd__h579674 = + sfd__h560800 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 ; - assign _theResult___snd__h589272 = { _theResult____h581025[55:0], 1'd0 } ; - assign _theResult___snd__h589283 = - (!_theResult____h581025[56] && _theResult____h581025[55]) ? - _theResult___snd__h589285 : - _theResult___snd__h589295 ; - assign _theResult___snd__h589285 = { _theResult____h581025[54:0], 2'd0 } ; - assign _theResult___snd__h589295 = - (!_theResult____h581025[56] && !_theResult____h581025[55] && - !_theResult____h581025[54] && - !_theResult____h581025[53] && - !_theResult____h581025[52] && - !_theResult____h581025[51] && - !_theResult____h581025[50] && - !_theResult____h581025[49] && - !_theResult____h581025[48] && - !_theResult____h581025[47] && - !_theResult____h581025[46] && - !_theResult____h581025[45] && - !_theResult____h581025[44] && - !_theResult____h581025[43] && - !_theResult____h581025[42] && - !_theResult____h581025[41] && - !_theResult____h581025[40] && - !_theResult____h581025[39] && - !_theResult____h581025[38] && - !_theResult____h581025[37] && - !_theResult____h581025[36] && - !_theResult____h581025[35] && - !_theResult____h581025[34] && - !_theResult____h581025[33] && - !_theResult____h581025[32] && - !_theResult____h581025[31] && - !_theResult____h581025[30] && - !_theResult____h581025[29] && - !_theResult____h581025[28] && - !_theResult____h581025[27] && - !_theResult____h581025[26] && - !_theResult____h581025[25] && - !_theResult____h581025[24] && - !_theResult____h581025[23] && - !_theResult____h581025[22] && - !_theResult____h581025[21] && - !_theResult____h581025[20] && - !_theResult____h581025[19] && - !_theResult____h581025[18] && - !_theResult____h581025[17] && - !_theResult____h581025[16] && - !_theResult____h581025[15] && - !_theResult____h581025[14] && - !_theResult____h581025[13] && - !_theResult____h581025[12] && - !_theResult____h581025[11] && - !_theResult____h581025[10] && - !_theResult____h581025[9] && - !_theResult____h581025[8] && - !_theResult____h581025[7] && - !_theResult____h581025[6] && - !_theResult____h581025[5] && - !_theResult____h581025[4] && - !_theResult____h581025[3] && - !_theResult____h581025[2] && - !_theResult____h581025[1] && - !_theResult____h581025[0]) ? - _theResult____h581025 : - _theResult___snd__h589301 ; - assign _theResult___snd__h589301 = + assign _theResult___snd__h589273 = { _theResult____h581026[55:0], 1'd0 } ; + assign _theResult___snd__h589284 = + (!_theResult____h581026[56] && _theResult____h581026[55]) ? + _theResult___snd__h589286 : + _theResult___snd__h589296 ; + assign _theResult___snd__h589286 = { _theResult____h581026[54:0], 2'd0 } ; + assign _theResult___snd__h589296 = + (!_theResult____h581026[56] && !_theResult____h581026[55] && + !_theResult____h581026[54] && + !_theResult____h581026[53] && + !_theResult____h581026[52] && + !_theResult____h581026[51] && + !_theResult____h581026[50] && + !_theResult____h581026[49] && + !_theResult____h581026[48] && + !_theResult____h581026[47] && + !_theResult____h581026[46] && + !_theResult____h581026[45] && + !_theResult____h581026[44] && + !_theResult____h581026[43] && + !_theResult____h581026[42] && + !_theResult____h581026[41] && + !_theResult____h581026[40] && + !_theResult____h581026[39] && + !_theResult____h581026[38] && + !_theResult____h581026[37] && + !_theResult____h581026[36] && + !_theResult____h581026[35] && + !_theResult____h581026[34] && + !_theResult____h581026[33] && + !_theResult____h581026[32] && + !_theResult____h581026[31] && + !_theResult____h581026[30] && + !_theResult____h581026[29] && + !_theResult____h581026[28] && + !_theResult____h581026[27] && + !_theResult____h581026[26] && + !_theResult____h581026[25] && + !_theResult____h581026[24] && + !_theResult____h581026[23] && + !_theResult____h581026[22] && + !_theResult____h581026[21] && + !_theResult____h581026[20] && + !_theResult____h581026[19] && + !_theResult____h581026[18] && + !_theResult____h581026[17] && + !_theResult____h581026[16] && + !_theResult____h581026[15] && + !_theResult____h581026[14] && + !_theResult____h581026[13] && + !_theResult____h581026[12] && + !_theResult____h581026[11] && + !_theResult____h581026[10] && + !_theResult____h581026[9] && + !_theResult____h581026[8] && + !_theResult____h581026[7] && + !_theResult____h581026[6] && + !_theResult____h581026[5] && + !_theResult____h581026[4] && + !_theResult____h581026[3] && + !_theResult____h581026[2] && + !_theResult____h581026[1] && + !_theResult____h581026[0]) ? + _theResult____h581026 : + _theResult___snd__h589302 ; + assign _theResult___snd__h589302 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h589324 = - _theResult____h581025 << + assign _theResult___snd__h589325 = + _theResult____h581026 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 ; - assign _theResult___snd__h598040 = - (f3_exp__h560437 == 8'd0) ? - _theResult___snd__h598054 : - _theResult___snd__h579637 ; - assign _theResult___snd__h598054 = - (f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] && + assign _theResult___snd__h598041 = + (f3_exp__h560438 == 8'd0) ? + _theResult___snd__h598055 : + _theResult___snd__h579638 ; + assign _theResult___snd__h598055 = + (f3_exp__h560438 == 8'd0 && !f3_sfd__h560439[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560799 : - _theResult___snd__h598060 ; - assign _theResult___snd__h598060 = + sfd__h560800 : + _theResult___snd__h598061 ; + assign _theResult___snd__h598061 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h598078 = - sfd__h560799 << + assign _theResult___snd__h598079 = + sfd__h560800 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ; - assign _theResult___snd__h603370 = - b__h602948[63] ? b___1__h603419 : b__h602948 ; - assign _theResult___snd_fst_exp__h363377 = + assign _theResult___snd__h603371 = + b__h602949[63] ? b___1__h603420 : b__h602949 ; + assign _theResult___snd_fst_exp__h363378 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_exp__h354792 : - _theResult___fst_exp__h363374 ; - assign _theResult___snd_fst_exp__h381197 = + _theResult___fst_exp__h354793 : + _theResult___fst_exp__h363375 ; + assign _theResult___snd_fst_exp__h381198 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_exp__h372558 : - _theResult___fst_exp__h381194 ; - assign _theResult___snd_fst_exp__h409074 = + _theResult___fst_exp__h372559 : + _theResult___fst_exp__h381195 ; + assign _theResult___snd_fst_exp__h409075 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_exp__h400489 : - _theResult___fst_exp__h409071 ; - assign _theResult___snd_fst_exp__h426894 = + _theResult___fst_exp__h400490 : + _theResult___fst_exp__h409072 ; + assign _theResult___snd_fst_exp__h426895 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_exp__h418255 : - _theResult___fst_exp__h426891 ; - assign _theResult___snd_fst_exp__h454769 = + _theResult___fst_exp__h418256 : + _theResult___fst_exp__h426892 ; + assign _theResult___snd_fst_exp__h454770 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_exp__h446184 : - _theResult___fst_exp__h454766 ; - assign _theResult___snd_fst_exp__h472589 = + _theResult___fst_exp__h446185 : + _theResult___fst_exp__h454767 ; + assign _theResult___snd_fst_exp__h472590 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_exp__h463950 : - _theResult___fst_exp__h472586 ; - assign _theResult___snd_fst_exp__h502288 = + _theResult___fst_exp__h463951 : + _theResult___fst_exp__h472587 ; + assign _theResult___snd_fst_exp__h502289 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 11'd0 : - _theResult___fst_exp__h502285 ; - assign _theResult___snd_fst_exp__h520723 = + _theResult___fst_exp__h502286 ; + assign _theResult___snd_fst_exp__h520724 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_exp__h511936 : - _theResult___fst_exp__h520720 ; - assign _theResult___snd_fst_exp__h541141 = + _theResult___fst_exp__h511937 : + _theResult___fst_exp__h520721 ; + assign _theResult___snd_fst_exp__h541142 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 11'd0 : - _theResult___fst_exp__h541138 ; - assign _theResult___snd_fst_exp__h559576 = + _theResult___fst_exp__h541139 ; + assign _theResult___snd_fst_exp__h559577 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_exp__h550789 : - _theResult___fst_exp__h559573 ; - assign _theResult___snd_fst_exp__h580445 = + _theResult___fst_exp__h550790 : + _theResult___fst_exp__h559574 ; + assign _theResult___snd_fst_exp__h580446 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 11'd0 : - _theResult___fst_exp__h580442 ; - assign _theResult___snd_fst_exp__h598880 = + _theResult___fst_exp__h580443 ; + assign _theResult___snd_fst_exp__h598881 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_exp__h590093 : - _theResult___fst_exp__h598877 ; - assign _theResult___snd_fst_sfd__h338429 = + _theResult___fst_exp__h590094 : + _theResult___fst_exp__h598878 ; + assign _theResult___snd_fst_sfd__h338430 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h363378 = + assign _theResult___snd_fst_sfd__h363379 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_sfd__h354793 : - _theResult___fst_sfd__h363375 ; - assign _theResult___snd_fst_sfd__h381198 = + _theResult___fst_sfd__h354794 : + _theResult___fst_sfd__h363376 ; + assign _theResult___snd_fst_sfd__h381199 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_sfd__h372559 : - _theResult___fst_sfd__h381195 ; - assign _theResult___snd_fst_sfd__h384131 = + _theResult___fst_sfd__h372560 : + _theResult___fst_sfd__h381196 ; + assign _theResult___snd_fst_sfd__h384132 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h409075 = + assign _theResult___snd_fst_sfd__h409076 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_sfd__h400490 : - _theResult___fst_sfd__h409072 ; - assign _theResult___snd_fst_sfd__h426895 = + _theResult___fst_sfd__h400491 : + _theResult___fst_sfd__h409073 ; + assign _theResult___snd_fst_sfd__h426896 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_sfd__h418256 : - _theResult___fst_sfd__h426892 ; - assign _theResult___snd_fst_sfd__h429826 = + _theResult___fst_sfd__h418257 : + _theResult___fst_sfd__h426893 ; + assign _theResult___snd_fst_sfd__h429827 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h454770 = + assign _theResult___snd_fst_sfd__h454771 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_sfd__h446185 : - _theResult___fst_sfd__h454767 ; - assign _theResult___snd_fst_sfd__h472590 = + _theResult___fst_sfd__h446186 : + _theResult___fst_sfd__h454768 ; + assign _theResult___snd_fst_sfd__h472591 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_sfd__h463951 : - _theResult___fst_sfd__h472587 ; - assign _theResult___snd_fst_sfd__h482455 = - (f1_sfd__h482140 == 23'd0) ? + _theResult___fst_sfd__h463952 : + _theResult___fst_sfd__h472588 ; + assign _theResult___snd_fst_sfd__h482456 = + (f1_sfd__h482141 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h482203 ; - assign _theResult___snd_fst_sfd__h502289 = + out___1_sfd__h482204 ; + assign _theResult___snd_fst_sfd__h502290 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 52'd0 : - _theResult___fst_sfd__h502286 ; - assign _theResult___snd_fst_sfd__h520724 = + _theResult___fst_sfd__h502287 ; + assign _theResult___snd_fst_sfd__h520725 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_sfd__h511937 : - _theResult___fst_sfd__h520721 ; - assign _theResult___snd_fst_sfd__h521449 = - (f2_sfd__h521134 == 23'd0) ? + _theResult___fst_sfd__h511938 : + _theResult___fst_sfd__h520722 ; + assign _theResult___snd_fst_sfd__h521450 = + (f2_sfd__h521135 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h521197 ; - assign _theResult___snd_fst_sfd__h541142 = + out___1_sfd__h521198 ; + assign _theResult___snd_fst_sfd__h541143 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 52'd0 : - _theResult___fst_sfd__h541139 ; - assign _theResult___snd_fst_sfd__h559577 = + _theResult___fst_sfd__h541140 ; + assign _theResult___snd_fst_sfd__h559578 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_sfd__h550790 : - _theResult___fst_sfd__h559574 ; - assign _theResult___snd_fst_sfd__h560753 = - (f3_sfd__h560438 == 23'd0) ? + _theResult___fst_sfd__h550791 : + _theResult___fst_sfd__h559575 ; + assign _theResult___snd_fst_sfd__h560754 = + (f3_sfd__h560439 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h560501 ; - assign _theResult___snd_fst_sfd__h580446 = + out___1_sfd__h560502 ; + assign _theResult___snd_fst_sfd__h580447 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 52'd0 : - _theResult___fst_sfd__h580443 ; - assign _theResult___snd_fst_sfd__h598881 = + _theResult___fst_sfd__h580444 ; + assign _theResult___snd_fst_sfd__h598882 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_sfd__h590094 : - _theResult___fst_sfd__h598878 ; - assign a___1__h603088 = + _theResult___fst_sfd__h590095 : + _theResult___fst_sfd__h598879 ; + assign a___1__h603089 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ; - assign a___1__h603374 = 64'd0 - a__h602947 ; - assign a__h602947 = + assign a___1__h603375 = 64'd0 - a__h602948 ; + assign a__h602948 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h603088 : + a___1__h603089 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h603089 = + assign b___1__h603090 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h603419 = 64'd0 - b__h602948 ; - assign b__h602948 = + assign b___1__h603420 = 64'd0 - b__h602949 ; + assign b__h602949 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h603089 : + b___1__h603090 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h711423 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h711443 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h708463 = - commitStage_commitTrap[36] ? i__h708638 : i__h708478 ; - assign commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 = + assign base__h712403 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h712423 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h709443 = + commitStage_commitTrap[36] ? i__h709618 : i__h709458 ; + assign commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && commitStage_commitTrap[35:32] != 4'd1 && @@ -29560,9 +29586,16 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd11 || !commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd3 && - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 ; - assign commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438 = - commitStage_rg_serial_num + y__h729714 ; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ; + assign commitStage_f_rob_data_first__4755_BIT_167_485_ETC___d14927 = + { commitStage_f_rob_data$D_OUT[167:166], + commitStage_f_rob_data$D_OUT[166] ? + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, + trap_val__h709444, + IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926 } ; + assign commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450 = + commitStage_rg_serial_num + y__h730732 ; assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29710,9 +29743,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29720,9 +29753,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29730,9 +29763,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29740,9 +29773,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29750,9 +29783,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 | - ((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) && - (f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) && - (f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) && + ((f3_exp__h560438 != 8'd255 || f3_sfd__h560439 == 23'd0) && + (f3_exp__h560438 != 8'd255 || f3_sfd__h560439 != 23'd0) && + (f3_exp__h560438 != 8'd0 || f3_sfd__h560439 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -29792,7 +29825,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h254802 ; + y__h254803 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 || @@ -30010,15 +30043,15 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_deqReq_rl) && coreFix_memExe_forwardQ_full ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706 = - { coreFix_memExe_lsq$getOrigBE << x__h183901[2:0], - x__h183901, + { coreFix_memExe_lsq$getOrigBE << x__h183902[2:0], + x__h183902, coreFix_memExe_regToExeQ$first[75:12], coreFix_memExe_lsq$getOrigBE, coreFix_memExe_lsq$getOrigBE[7] ? - x__h183901[2:0] != 3'd0 : + x__h183902[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - x__h183901[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && x__h183901[0]) } ; + x__h183902[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && x__h183902[0]) } ; assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 = coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 || @@ -30090,12 +30123,12 @@ module mkCore(CLK, !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas && !coreFix_memExe_respLrScAmoQ_deqReq_rl) && coreFix_memExe_respLrScAmoQ_full ; - assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646 = + assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14656 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign csr_addr__h655325 = + assign csr_addr__h655327 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 : 12'hCFF ; @@ -30111,7 +30144,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 || csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 || - csr_addr__h655325 == 12'h8FF) ; + csr_addr__h655327 == 12'h8FF) ; assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -30136,31 +30169,31 @@ module mkCore(CLK, fetchStage$pipelines_1_first[231:200] == 32'h10500073 && csrf_tw_reg && csrf_prv_reg != 2'd3 ; - assign csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 = - csrf_prv_reg_read__2787_ULE_1___d14685 && + assign csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 = + csrf_prv_reg_read__2787_ULE_1___d14696 && (commitStage_commitTrap[36] ? - _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 : - _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705) ; - assign csrf_prv_reg_read__2787_ULE_1___d14685 = csrf_prv_reg <= 2'd1 ; + _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 : + _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716) ; + assign csrf_prv_reg_read__2787_ULE_1___d14696 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 = - csrf_prv_reg < csr_addr__h655325[9:8] ; + csrf_prv_reg < csr_addr__h655327[9:8] ; assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435 ; - assign data75281_BITS_31_TO_0__q14 = data__h475281[31:0] ; - assign data___1__h475007 = + assign data75282_BITS_31_TO_0__q13 = data__h475282[31:0] ; + assign data___1__h475008 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; - assign data___1__h475815 = - { {32{data75281_BITS_31_TO_0__q14[31]}}, - data75281_BITS_31_TO_0__q14 } ; - assign data__h475281 = + assign data___1__h475816 = + { {32{data75282_BITS_31_TO_0__q13[31]}}, + data75282_BITS_31_TO_0__q13 } ; + assign data__h475282 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h475195 : - x_remainder__h475196 ; - assign dcsr_cause__h707982 = + x_quotient__h475196 : + x_remainder__h475197 ; + assign dcsr_cause__h708962 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30177,31 +30210,31 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h381228 = _theResult___fst_exp__h354195 + 8'd1 ; - assign din_inc___2_exp__h381252 = _theResult___fst_exp__h362851 + 8'd1 ; - assign din_inc___2_exp__h381282 = _theResult___fst_exp__h371961 + 8'd1 ; - assign din_inc___2_exp__h381306 = _theResult___fst_exp__h380646 + 8'd1 ; - assign din_inc___2_exp__h426925 = _theResult___fst_exp__h399892 + 8'd1 ; - assign din_inc___2_exp__h426949 = _theResult___fst_exp__h408548 + 8'd1 ; - assign din_inc___2_exp__h426979 = _theResult___fst_exp__h417658 + 8'd1 ; - assign din_inc___2_exp__h427003 = _theResult___fst_exp__h426343 + 8'd1 ; - assign din_inc___2_exp__h472620 = _theResult___fst_exp__h445587 + 8'd1 ; - assign din_inc___2_exp__h472644 = _theResult___fst_exp__h454243 + 8'd1 ; - assign din_inc___2_exp__h472674 = _theResult___fst_exp__h463353 + 8'd1 ; - assign din_inc___2_exp__h472698 = _theResult___fst_exp__h472038 + 8'd1 ; - assign din_inc___2_exp__h520777 = _theResult___fst_exp__h501527 + 11'd1 ; - assign din_inc___2_exp__h520812 = _theResult___fst_exp__h511104 + 11'd1 ; - assign din_inc___2_exp__h520838 = _theResult___fst_exp__h519937 + 11'd1 ; - assign din_inc___2_exp__h559630 = _theResult___fst_exp__h540380 + 11'd1 ; - assign din_inc___2_exp__h559665 = _theResult___fst_exp__h549957 + 11'd1 ; - assign din_inc___2_exp__h559691 = _theResult___fst_exp__h558790 + 11'd1 ; - assign din_inc___2_exp__h598934 = _theResult___fst_exp__h579684 + 11'd1 ; - assign din_inc___2_exp__h598969 = _theResult___fst_exp__h589261 + 11'd1 ; - assign din_inc___2_exp__h598995 = _theResult___fst_exp__h598094 + 11'd1 ; - assign enabled_ints___1__h651641 = pend_ints__h651114 & y__h651653 ; - assign enabled_ints__h651687 = - pend_ints__h651114 & - { r1__read_BITS_13_TO_0___h651663, csrf_mideleg_1_0_reg } ; + assign din_inc___2_exp__h381229 = _theResult___fst_exp__h354196 + 8'd1 ; + assign din_inc___2_exp__h381253 = _theResult___fst_exp__h362852 + 8'd1 ; + assign din_inc___2_exp__h381283 = _theResult___fst_exp__h371962 + 8'd1 ; + assign din_inc___2_exp__h381307 = _theResult___fst_exp__h380647 + 8'd1 ; + assign din_inc___2_exp__h426926 = _theResult___fst_exp__h399893 + 8'd1 ; + assign din_inc___2_exp__h426950 = _theResult___fst_exp__h408549 + 8'd1 ; + assign din_inc___2_exp__h426980 = _theResult___fst_exp__h417659 + 8'd1 ; + assign din_inc___2_exp__h427004 = _theResult___fst_exp__h426344 + 8'd1 ; + assign din_inc___2_exp__h472621 = _theResult___fst_exp__h445588 + 8'd1 ; + assign din_inc___2_exp__h472645 = _theResult___fst_exp__h454244 + 8'd1 ; + assign din_inc___2_exp__h472675 = _theResult___fst_exp__h463354 + 8'd1 ; + assign din_inc___2_exp__h472699 = _theResult___fst_exp__h472039 + 8'd1 ; + assign din_inc___2_exp__h520778 = _theResult___fst_exp__h501528 + 11'd1 ; + assign din_inc___2_exp__h520813 = _theResult___fst_exp__h511105 + 11'd1 ; + assign din_inc___2_exp__h520839 = _theResult___fst_exp__h519938 + 11'd1 ; + assign din_inc___2_exp__h559631 = _theResult___fst_exp__h540381 + 11'd1 ; + assign din_inc___2_exp__h559666 = _theResult___fst_exp__h549958 + 11'd1 ; + assign din_inc___2_exp__h559692 = _theResult___fst_exp__h558791 + 11'd1 ; + assign din_inc___2_exp__h598935 = _theResult___fst_exp__h579685 + 11'd1 ; + assign din_inc___2_exp__h598970 = _theResult___fst_exp__h589262 + 11'd1 ; + assign din_inc___2_exp__h598996 = _theResult___fst_exp__h598095 + 11'd1 ; + assign enabled_ints___1__h651643 = pend_ints__h651116 & y__h651655 ; + assign enabled_ints__h651689 = + pend_ints__h651116 & + { r1__read_BITS_13_TO_0___h651665, csrf_mideleg_1_0_reg } ; assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || @@ -30223,44 +30256,44 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 && IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890) ; - assign f1_exp82139_MINUS_127__q136 = f1_exp__h482139 - 8'd127 ; - assign f1_exp__h482139 = + assign f1_exp82140_MINUS_127__q136 = f1_exp__h482140 - 8'd127 ; + assign f1_exp__h482140 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h482140 = + assign f1_sfd__h482141 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp21133_MINUS_127__q176 = f2_exp__h521133 - 8'd127 ; - assign f2_exp__h521133 = + assign f2_exp21134_MINUS_127__q176 = f2_exp__h521134 - 8'd127 ; + assign f2_exp__h521134 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h521134 = + assign f2_sfd__h521135 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp60437_MINUS_127__q153 = f3_exp__h560437 - 8'd127 ; - assign f3_exp__h560437 = + assign f3_exp60438_MINUS_127__q153 = f3_exp__h560438 - 8'd127 ; + assign f3_exp__h560438 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h560438 = + assign f3_sfd__h560439 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880 = + assign f_csr_rsps_i_notFull__5790_AND_f_csr_reqs_firs_ETC___d15893 = f_csr_rsps$FULL_N && (f_csr_reqs$D_OUT[75:64] != 12'd2049 || csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h609375 = { 56'd0, x__h613033 } ; + assign fcsr_csr__read__h609377 = { 56'd0, x__h613035 } ; assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || @@ -30341,9 +30374,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h655326 != 5'd0 || - imm__h655327 != 32'd0) && - csr_addr__h655325[11:10] == 2'b11 ; + rs1__h655328 != 5'd0 || + imm__h655329 != 32'd0) && + csr_addr__h655327[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -30450,7 +30483,7 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h727255 = + assign fflags__h728257 = ({ rob$deqPort_0_deq_data[361:356], 1'd0, rob$deqPort_0_deq_data[354:350], @@ -30460,8 +30493,8 @@ module mkCore(CLK, rob$deqPort_0_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h727241 ; - assign fflags__h729891 = + po_fflags__h728242 ; + assign fflags__h730910 = ({ rob$deqPort_1_deq_data[361:356], 1'd0, rob$deqPort_1_deq_data[354:350], @@ -30471,105 +30504,105 @@ module mkCore(CLK, rob$deqPort_1_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h729877 ; - assign fflags__h732495 = - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ? - y_avValue_fst__h732432 : - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 ; - assign fflags_csr__read__h609350 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h609361 = { 61'd0, csrf_frm_reg } ; - assign guard__h346094 = - { IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29[1], - { sfdin__h354189[32:0], 23'd0 } != 56'd0 } ; - assign guard__h354803 = - { IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31[1], - { _theResult___snd__h362802[32:0], 23'd0 } != 56'd0 } ; - assign guard__h363733 = - { IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39[1], - { sfdin__h371955[32:0], 23'd0 } != 56'd0 } ; - assign guard__h364331 = x__h364433 != 57'd0 ; - assign guard__h372569 = - { IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44[1], - { _theResult___snd__h380592[32:0], 23'd0 } != 56'd0 } ; - assign guard__h391793 = - { IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64[1], - { sfdin__h399886[32:0], 23'd0 } != 56'd0 } ; - assign guard__h400500 = - { IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66[1], - { _theResult___snd__h408499[32:0], 23'd0 } != 56'd0 } ; - assign guard__h409430 = - { IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74[1], - { sfdin__h417652[32:0], 23'd0 } != 56'd0 } ; - assign guard__h410028 = x__h410130 != 57'd0 ; - assign guard__h418266 = - { IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79[1], - { _theResult___snd__h426289[32:0], 23'd0 } != 56'd0 } ; - assign guard__h437488 = - { IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99[1], - { sfdin__h445581[32:0], 23'd0 } != 56'd0 } ; - assign guard__h446195 = - { IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h454194[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455125 = - { IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109[1], - { sfdin__h463347[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455723 = x__h455825 != 57'd0 ; - assign guard__h463961 = - { IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114[1], - { _theResult___snd__h471984[32:0], 23'd0 } != 56'd0 } ; - assign guard__h493566 = - { IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h501478[3:0], 52'd0 } != 56'd0 } ; - assign guard__h502878 = - { IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h511098[3:0], 52'd0 } != 56'd0 } ; - assign guard__h503476 = x__h503576 != 57'd0 ; - assign guard__h511947 = - { IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h519883[3:0], 52'd0 } != 56'd0 } ; - assign guard__h532419 = - { IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h540331[3:0], 52'd0 } != 56'd0 } ; - assign guard__h541731 = - { IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h549951[3:0], 52'd0 } != 56'd0 } ; - assign guard__h542329 = x__h542429 != 57'd0 ; - assign guard__h550800 = - { IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h558736[3:0], 52'd0 } != 56'd0 } ; - assign guard__h571723 = - { IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h579635[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581035 = - { IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h589255[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581633 = x__h581733 != 57'd0 ; - assign guard__h590104 = - { IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h598040[3:0], 52'd0 } != 56'd0 } ; - assign idx__h685368 = + po_fflags__h730895 ; + assign fflags__h733530 = + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 ? + y_avValue_fst__h733467 : + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 ; + assign fflags_csr__read__h609352 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h609363 = { 61'd0, csrf_frm_reg } ; + assign guard__h346095 = + { IF_sfdin54190_BIT_33_THEN_2_ELSE_0__q29[1], + { sfdin__h354190[32:0], 23'd0 } != 56'd0 } ; + assign guard__h354804 = + { IF_theResult___snd62803_BIT_33_THEN_2_ELSE_0__q31[1], + { _theResult___snd__h362803[32:0], 23'd0 } != 56'd0 } ; + assign guard__h363734 = + { IF_sfdin71956_BIT_33_THEN_2_ELSE_0__q39[1], + { sfdin__h371956[32:0], 23'd0 } != 56'd0 } ; + assign guard__h364332 = x__h364434 != 57'd0 ; + assign guard__h372570 = + { IF_theResult___snd80593_BIT_33_THEN_2_ELSE_0__q44[1], + { _theResult___snd__h380593[32:0], 23'd0 } != 56'd0 } ; + assign guard__h391794 = + { IF_sfdin99887_BIT_33_THEN_2_ELSE_0__q64[1], + { sfdin__h399887[32:0], 23'd0 } != 56'd0 } ; + assign guard__h400501 = + { IF_theResult___snd08500_BIT_33_THEN_2_ELSE_0__q66[1], + { _theResult___snd__h408500[32:0], 23'd0 } != 56'd0 } ; + assign guard__h409431 = + { IF_sfdin17653_BIT_33_THEN_2_ELSE_0__q74[1], + { sfdin__h417653[32:0], 23'd0 } != 56'd0 } ; + assign guard__h410029 = x__h410131 != 57'd0 ; + assign guard__h418267 = + { IF_theResult___snd26290_BIT_33_THEN_2_ELSE_0__q79[1], + { _theResult___snd__h426290[32:0], 23'd0 } != 56'd0 } ; + assign guard__h437489 = + { IF_sfdin45582_BIT_33_THEN_2_ELSE_0__q99[1], + { sfdin__h445582[32:0], 23'd0 } != 56'd0 } ; + assign guard__h446196 = + { IF_theResult___snd54195_BIT_33_THEN_2_ELSE_0__q101[1], + { _theResult___snd__h454195[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455126 = + { IF_sfdin63348_BIT_33_THEN_2_ELSE_0__q109[1], + { sfdin__h463348[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455724 = x__h455826 != 57'd0 ; + assign guard__h463962 = + { IF_theResult___snd71985_BIT_33_THEN_2_ELSE_0__q114[1], + { _theResult___snd__h471985[32:0], 23'd0 } != 56'd0 } ; + assign guard__h493567 = + { IF_theResult___snd01479_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h501479[3:0], 52'd0 } != 56'd0 } ; + assign guard__h502879 = + { IF_sfdin11099_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h511099[3:0], 52'd0 } != 56'd0 } ; + assign guard__h503477 = x__h503577 != 57'd0 ; + assign guard__h511948 = + { IF_theResult___snd19884_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h519884[3:0], 52'd0 } != 56'd0 } ; + assign guard__h532420 = + { IF_theResult___snd40332_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h540332[3:0], 52'd0 } != 56'd0 } ; + assign guard__h541732 = + { IF_sfdin49952_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h549952[3:0], 52'd0 } != 56'd0 } ; + assign guard__h542330 = x__h542430 != 57'd0 ; + assign guard__h550801 = + { IF_theResult___snd58737_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h558737[3:0], 52'd0 } != 56'd0 } ; + assign guard__h571724 = + { IF_theResult___snd79636_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h579636[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581036 = + { IF_sfdin89256_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h589256[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581634 = x__h581734 != 57'd0 ; + assign guard__h590105 = + { IF_theResult___snd98041_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h598041[3:0], 52'd0 } != 56'd0 } ; + assign idx__h685370 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 || !coreFix_aluExe_0_rsAlu$canEnq || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770 ; - assign imm__h655327 = + assign imm__h655329 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h669623 = + assign k__h669625 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ; - assign mcause_csr__read__h611017 = - { r1__read__h614496, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h610762 = - { r1__read__h614483, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h610369 = - { r1__read__h614344, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h610464 = - { r1__read__h614361, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h610588 = { r1__read__h614385, 1'b0 } ; - assign mip_csr__read__h611250 = { r1__read__h614502, 1'b0 } ; + assign mcause_csr__read__h611019 = + { r1__read__h614498, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h610764 = + { r1__read__h614485, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h610371 = + { r1__read__h614346, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h610466 = + { r1__read__h614363, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h610590 = { r1__read__h614387, 1'b0 } ; + assign mip_csr__read__h611252 = { r1__read__h614504, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30653,41 +30686,41 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h76121 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h610221 = { r1__read__h614219, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h610670 = - { r1__read__h614478, csrf_mtvec_mode_low_reg } ; - assign n___1__h198528 = + assign msip__h76122 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h610223 = { r1__read__h614221, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h610672 = + { r1__read__h614480, csrf_mtvec_mode_low_reg } ; + assign n___1__h198529 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h197125[63:56], + x__h197126[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h197125[55:48], + x__h197126[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h197125[47:40], + x__h197126[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h197125[39:32], + x__h197126[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h197125[31:24], + x__h197126[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h197125[23:16], + x__h197126[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h197125[15:8], + x__h197126[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h197125[7:0] } ; - assign n__read__h611354 = + x__h197126[7:0] } ; + assign n__read__h611356 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h611545 = + assign n__read__h611547 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : @@ -30698,257 +30731,257 @@ module mkCore(CLK, upd__h6873 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h725937 = + assign n__read__h726937 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h296799 = + assign next_deqP___1__h296800 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h304795 = + assign next_deqP___1__h304796 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h311076 = + assign next_deqP___1__h311077 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h318930 = + assign next_deqP___1__h318931 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h328987 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h332212 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h721469 = + assign next_deqP___1__h328988 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h332213 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h722452 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign old_fflags__h731983 = + assign old_fflags__h733017 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; - assign out___1_sfd__h482203 = { f1_sfd__h482140, 29'd0 } ; - assign out___1_sfd__h521197 = { f2_sfd__h521134, 29'd0 } ; - assign out___1_sfd__h560501 = { f3_sfd__h560438, 29'd0 } ; - assign out_exp__h354714 = - sfdin__h354189[34] ? - _theResult___exp__h354711 : - _theResult___fst_exp__h354195 ; - assign out_exp__h363296 = - _theResult___snd__h362802[34] ? - _theResult___exp__h363293 : - _theResult___fst_exp__h362851 ; - assign out_exp__h372480 = - sfdin__h371955[34] ? - _theResult___exp__h372477 : - _theResult___fst_exp__h371961 ; - assign out_exp__h381116 = - _theResult___snd__h380592[34] ? - _theResult___exp__h381113 : - _theResult___fst_exp__h380646 ; - assign out_exp__h400411 = - sfdin__h399886[34] ? - _theResult___exp__h400408 : - _theResult___fst_exp__h399892 ; - assign out_exp__h408993 = - _theResult___snd__h408499[34] ? - _theResult___exp__h408990 : - _theResult___fst_exp__h408548 ; - assign out_exp__h418177 = - sfdin__h417652[34] ? - _theResult___exp__h418174 : - _theResult___fst_exp__h417658 ; - assign out_exp__h426813 = - _theResult___snd__h426289[34] ? - _theResult___exp__h426810 : - _theResult___fst_exp__h426343 ; - assign out_exp__h446106 = - sfdin__h445581[34] ? - _theResult___exp__h446103 : - _theResult___fst_exp__h445587 ; - assign out_exp__h454688 = - _theResult___snd__h454194[34] ? - _theResult___exp__h454685 : - _theResult___fst_exp__h454243 ; - assign out_exp__h463872 = - sfdin__h463347[34] ? - _theResult___exp__h463869 : - _theResult___fst_exp__h463353 ; - assign out_exp__h472508 = - _theResult___snd__h471984[34] ? - _theResult___exp__h472505 : - _theResult___fst_exp__h472038 ; - assign out_exp__h502185 = - _theResult___snd__h501478[5] ? - _theResult___exp__h502182 : - _theResult___fst_exp__h501527 ; - assign out_exp__h511836 = - sfdin__h511098[5] ? - _theResult___exp__h511833 : - _theResult___fst_exp__h511104 ; - assign out_exp__h520620 = - _theResult___snd__h519883[5] ? - _theResult___exp__h520617 : - _theResult___fst_exp__h519937 ; - assign out_exp__h541038 = - _theResult___snd__h540331[5] ? - _theResult___exp__h541035 : - _theResult___fst_exp__h540380 ; - assign out_exp__h550689 = - sfdin__h549951[5] ? - _theResult___exp__h550686 : - _theResult___fst_exp__h549957 ; - assign out_exp__h559473 = - _theResult___snd__h558736[5] ? - _theResult___exp__h559470 : - _theResult___fst_exp__h558790 ; - assign out_exp__h580342 = - _theResult___snd__h579635[5] ? - _theResult___exp__h580339 : - _theResult___fst_exp__h579684 ; - assign out_exp__h589993 = - sfdin__h589255[5] ? - _theResult___exp__h589990 : - _theResult___fst_exp__h589261 ; - assign out_exp__h598777 = - _theResult___snd__h598040[5] ? - _theResult___exp__h598774 : - _theResult___fst_exp__h598094 ; - assign out_f_exp__h381492 = - (_theResult___exp__h381215 == 8'd255 && - _theResult___sfd__h381216 != 23'd0 || + assign out___1_sfd__h482204 = { f1_sfd__h482141, 29'd0 } ; + assign out___1_sfd__h521198 = { f2_sfd__h521135, 29'd0 } ; + assign out___1_sfd__h560502 = { f3_sfd__h560439, 29'd0 } ; + assign out_exp__h354715 = + sfdin__h354190[34] ? + _theResult___exp__h354712 : + _theResult___fst_exp__h354196 ; + assign out_exp__h363297 = + _theResult___snd__h362803[34] ? + _theResult___exp__h363294 : + _theResult___fst_exp__h362852 ; + assign out_exp__h372481 = + sfdin__h371956[34] ? + _theResult___exp__h372478 : + _theResult___fst_exp__h371962 ; + assign out_exp__h381117 = + _theResult___snd__h380593[34] ? + _theResult___exp__h381114 : + _theResult___fst_exp__h380647 ; + assign out_exp__h400412 = + sfdin__h399887[34] ? + _theResult___exp__h400409 : + _theResult___fst_exp__h399893 ; + assign out_exp__h408994 = + _theResult___snd__h408500[34] ? + _theResult___exp__h408991 : + _theResult___fst_exp__h408549 ; + assign out_exp__h418178 = + sfdin__h417653[34] ? + _theResult___exp__h418175 : + _theResult___fst_exp__h417659 ; + assign out_exp__h426814 = + _theResult___snd__h426290[34] ? + _theResult___exp__h426811 : + _theResult___fst_exp__h426344 ; + assign out_exp__h446107 = + sfdin__h445582[34] ? + _theResult___exp__h446104 : + _theResult___fst_exp__h445588 ; + assign out_exp__h454689 = + _theResult___snd__h454195[34] ? + _theResult___exp__h454686 : + _theResult___fst_exp__h454244 ; + assign out_exp__h463873 = + sfdin__h463348[34] ? + _theResult___exp__h463870 : + _theResult___fst_exp__h463354 ; + assign out_exp__h472509 = + _theResult___snd__h471985[34] ? + _theResult___exp__h472506 : + _theResult___fst_exp__h472039 ; + assign out_exp__h502186 = + _theResult___snd__h501479[5] ? + _theResult___exp__h502183 : + _theResult___fst_exp__h501528 ; + assign out_exp__h511837 = + sfdin__h511099[5] ? + _theResult___exp__h511834 : + _theResult___fst_exp__h511105 ; + assign out_exp__h520621 = + _theResult___snd__h519884[5] ? + _theResult___exp__h520618 : + _theResult___fst_exp__h519938 ; + assign out_exp__h541039 = + _theResult___snd__h540332[5] ? + _theResult___exp__h541036 : + _theResult___fst_exp__h540381 ; + assign out_exp__h550690 = + sfdin__h549952[5] ? + _theResult___exp__h550687 : + _theResult___fst_exp__h549958 ; + assign out_exp__h559474 = + _theResult___snd__h558737[5] ? + _theResult___exp__h559471 : + _theResult___fst_exp__h558791 ; + assign out_exp__h580343 = + _theResult___snd__h579636[5] ? + _theResult___exp__h580340 : + _theResult___fst_exp__h579685 ; + assign out_exp__h589994 = + sfdin__h589256[5] ? + _theResult___exp__h589991 : + _theResult___fst_exp__h589262 ; + assign out_exp__h598778 = + _theResult___snd__h598041[5] ? + _theResult___exp__h598775 : + _theResult___fst_exp__h598095 ; + assign out_f_exp__h381493 = + (_theResult___exp__h381216 == 8'd255 && + _theResult___sfd__h381217 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381206 ; - assign out_f_exp__h427189 = - (_theResult___exp__h426912 == 8'd255 && - _theResult___sfd__h426913 != 23'd0 || + _theResult___fst_exp__h381207 ; + assign out_f_exp__h427190 = + (_theResult___exp__h426913 == 8'd255 && + _theResult___sfd__h426914 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426903 ; - assign out_f_exp__h472884 = - (_theResult___exp__h472607 == 8'd255 && - _theResult___sfd__h472608 != 23'd0 || + _theResult___fst_exp__h426904 ; + assign out_f_exp__h472885 = + (_theResult___exp__h472608 == 8'd255 && + _theResult___sfd__h472609 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472598 ; - assign out_f_sfd__h381493 = - (_theResult___exp__h381215 == 8'd255 && - _theResult___sfd__h381216 != 23'd0) ? + _theResult___fst_exp__h472599 ; + assign out_f_sfd__h381494 = + (_theResult___exp__h381216 == 8'd255 && + _theResult___sfd__h381217 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h381216 ; - assign out_f_sfd__h427190 = - (_theResult___exp__h426912 == 8'd255 && - _theResult___sfd__h426913 != 23'd0) ? + _theResult___sfd__h381217 ; + assign out_f_sfd__h427191 = + (_theResult___exp__h426913 == 8'd255 && + _theResult___sfd__h426914 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h426913 ; - assign out_f_sfd__h472885 = - (_theResult___exp__h472607 == 8'd255 && - _theResult___sfd__h472608 != 23'd0) ? + _theResult___sfd__h426914 ; + assign out_f_sfd__h472886 = + (_theResult___exp__h472608 == 8'd255 && + _theResult___sfd__h472609 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h472608 ; - assign out_sfd__h354715 = - sfdin__h354189[34] ? - _theResult___sfd__h354712 : - sfdin__h354189[56:34] ; - assign out_sfd__h363297 = - _theResult___snd__h362802[34] ? - _theResult___sfd__h363294 : - _theResult___snd__h362802[56:34] ; - assign out_sfd__h372481 = - sfdin__h371955[34] ? - _theResult___sfd__h372478 : - sfdin__h371955[56:34] ; - assign out_sfd__h381117 = - _theResult___snd__h380592[34] ? - _theResult___sfd__h381114 : - _theResult___snd__h380592[56:34] ; - assign out_sfd__h400412 = - sfdin__h399886[34] ? - _theResult___sfd__h400409 : - sfdin__h399886[56:34] ; - assign out_sfd__h408994 = - _theResult___snd__h408499[34] ? - _theResult___sfd__h408991 : - _theResult___snd__h408499[56:34] ; - assign out_sfd__h418178 = - sfdin__h417652[34] ? - _theResult___sfd__h418175 : - sfdin__h417652[56:34] ; - assign out_sfd__h426814 = - _theResult___snd__h426289[34] ? - _theResult___sfd__h426811 : - _theResult___snd__h426289[56:34] ; - assign out_sfd__h446107 = - sfdin__h445581[34] ? - _theResult___sfd__h446104 : - sfdin__h445581[56:34] ; - assign out_sfd__h454689 = - _theResult___snd__h454194[34] ? - _theResult___sfd__h454686 : - _theResult___snd__h454194[56:34] ; - assign out_sfd__h463873 = - sfdin__h463347[34] ? - _theResult___sfd__h463870 : - sfdin__h463347[56:34] ; - assign out_sfd__h472509 = - _theResult___snd__h471984[34] ? - _theResult___sfd__h472506 : - _theResult___snd__h471984[56:34] ; - assign out_sfd__h502186 = - _theResult___snd__h501478[5] ? - _theResult___sfd__h502183 : - _theResult___snd__h501478[56:5] ; - assign out_sfd__h511837 = - sfdin__h511098[5] ? - _theResult___sfd__h511834 : - sfdin__h511098[56:5] ; - assign out_sfd__h520621 = - _theResult___snd__h519883[5] ? - _theResult___sfd__h520618 : - _theResult___snd__h519883[56:5] ; - assign out_sfd__h541039 = - _theResult___snd__h540331[5] ? - _theResult___sfd__h541036 : - _theResult___snd__h540331[56:5] ; - assign out_sfd__h550690 = - sfdin__h549951[5] ? - _theResult___sfd__h550687 : - sfdin__h549951[56:5] ; - assign out_sfd__h559474 = - _theResult___snd__h558736[5] ? - _theResult___sfd__h559471 : - _theResult___snd__h558736[56:5] ; - assign out_sfd__h580343 = - _theResult___snd__h579635[5] ? - _theResult___sfd__h580340 : - _theResult___snd__h579635[56:5] ; - assign out_sfd__h589994 = - sfdin__h589255[5] ? - _theResult___sfd__h589991 : - sfdin__h589255[56:5] ; - assign out_sfd__h598778 = - _theResult___snd__h598040[5] ? - _theResult___sfd__h598775 : - _theResult___snd__h598040[56:5] ; - assign pc__h711407 = - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ? - y_avValue_new_pc__h711199 : - y_avValue_new_pc__h711385 ; - assign pend_ints__h651114 = + _theResult___sfd__h472609 ; + assign out_sfd__h354716 = + sfdin__h354190[34] ? + _theResult___sfd__h354713 : + sfdin__h354190[56:34] ; + assign out_sfd__h363298 = + _theResult___snd__h362803[34] ? + _theResult___sfd__h363295 : + _theResult___snd__h362803[56:34] ; + assign out_sfd__h372482 = + sfdin__h371956[34] ? + _theResult___sfd__h372479 : + sfdin__h371956[56:34] ; + assign out_sfd__h381118 = + _theResult___snd__h380593[34] ? + _theResult___sfd__h381115 : + _theResult___snd__h380593[56:34] ; + assign out_sfd__h400413 = + sfdin__h399887[34] ? + _theResult___sfd__h400410 : + sfdin__h399887[56:34] ; + assign out_sfd__h408995 = + _theResult___snd__h408500[34] ? + _theResult___sfd__h408992 : + _theResult___snd__h408500[56:34] ; + assign out_sfd__h418179 = + sfdin__h417653[34] ? + _theResult___sfd__h418176 : + sfdin__h417653[56:34] ; + assign out_sfd__h426815 = + _theResult___snd__h426290[34] ? + _theResult___sfd__h426812 : + _theResult___snd__h426290[56:34] ; + assign out_sfd__h446108 = + sfdin__h445582[34] ? + _theResult___sfd__h446105 : + sfdin__h445582[56:34] ; + assign out_sfd__h454690 = + _theResult___snd__h454195[34] ? + _theResult___sfd__h454687 : + _theResult___snd__h454195[56:34] ; + assign out_sfd__h463874 = + sfdin__h463348[34] ? + _theResult___sfd__h463871 : + sfdin__h463348[56:34] ; + assign out_sfd__h472510 = + _theResult___snd__h471985[34] ? + _theResult___sfd__h472507 : + _theResult___snd__h471985[56:34] ; + assign out_sfd__h502187 = + _theResult___snd__h501479[5] ? + _theResult___sfd__h502184 : + _theResult___snd__h501479[56:5] ; + assign out_sfd__h511838 = + sfdin__h511099[5] ? + _theResult___sfd__h511835 : + sfdin__h511099[56:5] ; + assign out_sfd__h520622 = + _theResult___snd__h519884[5] ? + _theResult___sfd__h520619 : + _theResult___snd__h519884[56:5] ; + assign out_sfd__h541040 = + _theResult___snd__h540332[5] ? + _theResult___sfd__h541037 : + _theResult___snd__h540332[56:5] ; + assign out_sfd__h550691 = + sfdin__h549952[5] ? + _theResult___sfd__h550688 : + sfdin__h549952[56:5] ; + assign out_sfd__h559475 = + _theResult___snd__h558737[5] ? + _theResult___sfd__h559472 : + _theResult___snd__h558737[56:5] ; + assign out_sfd__h580344 = + _theResult___snd__h579636[5] ? + _theResult___sfd__h580341 : + _theResult___snd__h579636[56:5] ; + assign out_sfd__h589995 = + sfdin__h589256[5] ? + _theResult___sfd__h589992 : + sfdin__h589256[56:5] ; + assign out_sfd__h598779 = + _theResult___snd__h598041[5] ? + _theResult___sfd__h598776 : + _theResult___snd__h598041[56:5] ; + assign pc__h712387 = + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? + y_avValue_new_pc__h712179 : + y_avValue_new_pc__h712365 ; + assign pend_ints__h651116 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h727241 = old_fflags__h731983 ; - assign po_fflags__h729877 = - old_fflags__h731983 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h734164 = csrf_prv_reg ; - assign prv__h734208 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h475880 = + assign po_fflags__h728242 = old_fflags__h733017 ; + assign po_fflags__h730895 = + old_fflags__h733017 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h735199 = csrf_prv_reg ; + assign prv__h735243 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h475881 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h651663 = + assign r1__read_BITS_13_TO_0___h651665 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -30956,119 +30989,127 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h655195 = csrf_fs_reg ; - assign r1__read_BITS_62_TO_14___h728903 = { r1__read__h614243, 2'd0 } ; - assign r1__read_BIT_20___h655891 = csrf_tw_reg ; - assign r1__read__h613048 = { r1__read__h613050, csrf_ie_vec_1 } ; - assign r1__read__h613050 = { r1__read__h613052, 2'b0 } ; - assign r1__read__h613052 = { r1__read__h613054, csrf_prev_ie_vec_0 } ; - assign r1__read__h613054 = { r1__read__h613056, csrf_prev_ie_vec_1 } ; - assign r1__read__h613056 = { r1__read__h613058, 2'b0 } ; - assign r1__read__h613058 = { r1__read__h613060, csrf_spp_reg } ; - assign r1__read__h613060 = { r1__read__h613062, 4'b0 } ; - assign r1__read__h613062 = { r1__read__h613064, csrf_fs_reg } ; - assign r1__read__h613064 = { r1__read__h613066, 2'd0 } ; - assign r1__read__h613066 = { r1__read__h613068, 1'b0 } ; - assign r1__read__h613068 = { r1__read__h613070, csrf_sum_reg } ; - assign r1__read__h613070 = { r1__read__h613072, csrf_mxr_reg } ; - assign r1__read__h613072 = { r1__read__h613074, 12'b0 } ; - assign r1__read__h613074 = { r1__read__h613076, 2'b10 } ; - assign r1__read__h613076 = { csrf_fs_reg == 2'b11, 29'b0 } ; - assign r1__read__h613452 = - { r1__read__h613454, csrf_software_int_en_vec_1 } ; - assign r1__read__h613454 = { r1__read__h613456, 2'b0 } ; - assign r1__read__h613456 = { r1__read__h613458, 1'b0 } ; - assign r1__read__h613458 = { r1__read__h613460, csrf_timer_int_en_vec_1 } ; - assign r1__read__h613460 = { r1__read__h613462, 2'b0 } ; - assign r1__read__h613462 = { r1__read__h613464, 1'b0 } ; - assign r1__read__h613464 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h613962 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h613967 = { r1__read__h613969, csrf_scounteren_tm_reg } ; - assign r1__read__h613969 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h613980 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h613986 = - { r1__read__h613988, csrf_software_int_pend_vec_1 } ; - assign r1__read__h613988 = { r1__read__h613990, 2'b0 } ; - assign r1__read__h613990 = { r1__read__h613992, 1'b0 } ; - assign r1__read__h613992 = - { r1__read__h613994, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h613994 = { r1__read__h613996, 2'b0 } ; - assign r1__read__h613996 = { r1__read__h613998, 1'b0 } ; - assign r1__read__h613998 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614196 = { vm_mode_reg__read__h614202, 16'd0 } ; - assign r1__read__h614219 = { r1__read__h614221, csrf_ie_vec_1 } ; - assign r1__read__h614221 = { r1__read__h614223, 1'b0 } ; - assign r1__read__h614223 = { r1__read__h614225, csrf_ie_vec_3 } ; - assign r1__read__h614225 = { r1__read__h614227, csrf_prev_ie_vec_0 } ; - assign r1__read__h614227 = { r1__read__h614229, csrf_prev_ie_vec_1 } ; - assign r1__read__h614229 = { r1__read__h614231, 1'b0 } ; - assign r1__read__h614231 = { r1__read__h614233, csrf_prev_ie_vec_3 } ; - assign r1__read__h614233 = { r1__read__h614235, csrf_spp_reg } ; - assign r1__read__h614235 = { r1__read__h614237, 2'b0 } ; - assign r1__read__h614237 = { r1__read__h614239, csrf_mpp_reg } ; - assign r1__read__h614239 = - { r1__read_BITS_62_TO_14___h728903, csrf_fs_reg } ; - assign r1__read__h614243 = { r1__read__h614245, csrf_mprv_reg } ; - assign r1__read__h614245 = { r1__read__h614247, csrf_sum_reg } ; - assign r1__read__h614247 = { r1__read__h614249, csrf_mxr_reg } ; - assign r1__read__h614249 = { r1__read__h614251, csrf_tvm_reg } ; - assign r1__read__h614251 = { r1__read__h614253, csrf_tw_reg } ; - assign r1__read__h614253 = { r1__read__h614255, csrf_tsr_reg } ; - assign r1__read__h614255 = { r1__read__h614257, 9'b0 } ; - assign r1__read__h614257 = { r1__read__h614259, 2'b10 } ; + assign r1__read_BITS_13_TO_12___h655197 = csrf_fs_reg ; + assign r1__read_BITS_62_TO_14___h729920 = { r1__read__h614245, 2'd0 } ; + assign r1__read_BIT_20___h655893 = csrf_tw_reg ; + assign r1__read__h613050 = { r1__read__h613052, csrf_ie_vec_1 } ; + assign r1__read__h613052 = { r1__read__h613054, 2'b0 } ; + assign r1__read__h613054 = { r1__read__h613056, csrf_prev_ie_vec_0 } ; + assign r1__read__h613056 = { r1__read__h613058, csrf_prev_ie_vec_1 } ; + assign r1__read__h613058 = { r1__read__h613060, 2'b0 } ; + assign r1__read__h613060 = { r1__read__h613062, csrf_spp_reg } ; + assign r1__read__h613062 = { r1__read__h613064, 4'b0 } ; + assign r1__read__h613064 = { r1__read__h613066, csrf_fs_reg } ; + assign r1__read__h613066 = { r1__read__h613068, 2'd0 } ; + assign r1__read__h613068 = { r1__read__h613070, 1'b0 } ; + assign r1__read__h613070 = { r1__read__h613072, csrf_sum_reg } ; + assign r1__read__h613072 = { r1__read__h613074, csrf_mxr_reg } ; + assign r1__read__h613074 = { r1__read__h613076, 12'b0 } ; + assign r1__read__h613076 = { r1__read__h613078, 2'b10 } ; + assign r1__read__h613078 = { csrf_fs_reg == 2'b11, 29'b0 } ; + assign r1__read__h613454 = + { r1__read__h613456, csrf_software_int_en_vec_1 } ; + assign r1__read__h613456 = { r1__read__h613458, 2'b0 } ; + assign r1__read__h613458 = { r1__read__h613460, 1'b0 } ; + assign r1__read__h613460 = { r1__read__h613462, csrf_timer_int_en_vec_1 } ; + assign r1__read__h613462 = { r1__read__h613464, 2'b0 } ; + assign r1__read__h613464 = { r1__read__h613466, 1'b0 } ; + assign r1__read__h613466 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h613964 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h613969 = { r1__read__h613971, csrf_scounteren_tm_reg } ; + assign r1__read__h613971 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h613982 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h613988 = + { r1__read__h613990, csrf_software_int_pend_vec_1 } ; + assign r1__read__h613990 = { r1__read__h613992, 2'b0 } ; + assign r1__read__h613992 = { r1__read__h613994, 1'b0 } ; + assign r1__read__h613994 = + { r1__read__h613996, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h613996 = { r1__read__h613998, 2'b0 } ; + assign r1__read__h613998 = { r1__read__h614000, 1'b0 } ; + assign r1__read__h614000 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614198 = { vm_mode_reg__read__h614204, 16'd0 } ; + assign r1__read__h614221 = { r1__read__h614223, csrf_ie_vec_1 } ; + assign r1__read__h614223 = { r1__read__h614225, 1'b0 } ; + assign r1__read__h614225 = { r1__read__h614227, csrf_ie_vec_3 } ; + assign r1__read__h614227 = { r1__read__h614229, csrf_prev_ie_vec_0 } ; + assign r1__read__h614229 = { r1__read__h614231, csrf_prev_ie_vec_1 } ; + assign r1__read__h614231 = { r1__read__h614233, 1'b0 } ; + assign r1__read__h614233 = { r1__read__h614235, csrf_prev_ie_vec_3 } ; + assign r1__read__h614235 = { r1__read__h614237, csrf_spp_reg } ; + assign r1__read__h614237 = { r1__read__h614239, 2'b0 } ; + assign r1__read__h614239 = { r1__read__h614241, csrf_mpp_reg } ; + assign r1__read__h614241 = + { r1__read_BITS_62_TO_14___h729920, csrf_fs_reg } ; + assign r1__read__h614245 = { r1__read__h614247, csrf_mprv_reg } ; + assign r1__read__h614247 = { r1__read__h614249, csrf_sum_reg } ; + assign r1__read__h614249 = { r1__read__h614251, csrf_mxr_reg } ; + assign r1__read__h614251 = { r1__read__h614253, csrf_tvm_reg } ; + assign r1__read__h614253 = { r1__read__h614255, csrf_tw_reg } ; + assign r1__read__h614255 = { r1__read__h614257, csrf_tsr_reg } ; + assign r1__read__h614257 = { r1__read__h614259, 9'b0 } ; assign r1__read__h614259 = { r1__read__h614261, 2'b10 } ; - assign r1__read__h614261 = { csrf_fs_reg == 2'b11, 27'b0 } ; - assign r1__read__h614344 = { r1__read__h614346, 1'b0 } ; - assign r1__read__h614346 = { r1__read__h614348, csrf_medeleg_13_11_reg } ; - assign r1__read__h614348 = { r1__read__h614350, 1'b0 } ; - assign r1__read__h614350 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h614361 = { r1__read__h614363, 1'b0 } ; - assign r1__read__h614363 = { r1__read__h614365, csrf_mideleg_5_3_reg } ; - assign r1__read__h614365 = { r1__read__h614367, 1'b0 } ; - assign r1__read__h614367 = { r1__read__h614369, csrf_mideleg_9_7_reg } ; - assign r1__read__h614369 = { r1__read__h614371, 1'b0 } ; - assign r1__read__h614371 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h614385 = - { r1__read__h614387, csrf_software_int_en_vec_1 } ; - assign r1__read__h614387 = { r1__read__h614389, 1'b0 } ; - assign r1__read__h614389 = - { r1__read__h614391, csrf_software_int_en_vec_3 } ; - assign r1__read__h614391 = { r1__read__h614393, 1'b0 } ; - assign r1__read__h614393 = { r1__read__h614395, csrf_timer_int_en_vec_1 } ; - assign r1__read__h614395 = { r1__read__h614397, 1'b0 } ; - assign r1__read__h614397 = { r1__read__h614399, csrf_timer_int_en_vec_3 } ; - assign r1__read__h614399 = { r1__read__h614401, 1'b0 } ; - assign r1__read__h614401 = - { r1__read__h614403, csrf_external_int_en_vec_1 } ; - assign r1__read__h614403 = { r1__read__h614405, 1'b0 } ; - assign r1__read__h614405 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h614478 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h614483 = { r1__read__h614485, csrf_mcounteren_tm_reg } ; - assign r1__read__h614485 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h614496 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h614502 = - { r1__read__h614504, csrf_software_int_pend_vec_1 } ; - assign r1__read__h614504 = { r1__read__h614506, 1'b0 } ; - assign r1__read__h614506 = - { r1__read__h614508, csrf_software_int_pend_vec_3 } ; - assign r1__read__h614508 = { r1__read__h614510, 1'b0 } ; - assign r1__read__h614510 = - { r1__read__h614512, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h614512 = { r1__read__h614514, 1'b0 } ; - assign r1__read__h614514 = - { r1__read__h614516, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h614516 = { r1__read__h614518, 1'b0 } ; - assign r1__read__h614518 = - { r1__read__h614520, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614520 = { r1__read__h614522, 1'b0 } ; - assign r1__read__h614522 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h614599 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h481760 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h481761 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h475906 = + assign r1__read__h614261 = { r1__read__h614263, 2'b10 } ; + assign r1__read__h614263 = { csrf_fs_reg == 2'b11, 27'b0 } ; + assign r1__read__h614346 = { r1__read__h614348, 1'b0 } ; + assign r1__read__h614348 = { r1__read__h614350, csrf_medeleg_13_11_reg } ; + assign r1__read__h614350 = { r1__read__h614352, 1'b0 } ; + assign r1__read__h614352 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h614363 = { r1__read__h614365, 1'b0 } ; + assign r1__read__h614365 = { r1__read__h614367, csrf_mideleg_5_3_reg } ; + assign r1__read__h614367 = { r1__read__h614369, 1'b0 } ; + assign r1__read__h614369 = { r1__read__h614371, csrf_mideleg_9_7_reg } ; + assign r1__read__h614371 = { r1__read__h614373, 1'b0 } ; + assign r1__read__h614373 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h614387 = + { r1__read__h614389, csrf_software_int_en_vec_1 } ; + assign r1__read__h614389 = { r1__read__h614391, 1'b0 } ; + assign r1__read__h614391 = + { r1__read__h614393, csrf_software_int_en_vec_3 } ; + assign r1__read__h614393 = { r1__read__h614395, 1'b0 } ; + assign r1__read__h614395 = { r1__read__h614397, csrf_timer_int_en_vec_1 } ; + assign r1__read__h614397 = { r1__read__h614399, 1'b0 } ; + assign r1__read__h614399 = { r1__read__h614401, csrf_timer_int_en_vec_3 } ; + assign r1__read__h614401 = { r1__read__h614403, 1'b0 } ; + assign r1__read__h614403 = + { r1__read__h614405, csrf_external_int_en_vec_1 } ; + assign r1__read__h614405 = { r1__read__h614407, 1'b0 } ; + assign r1__read__h614407 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h614480 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h614485 = { r1__read__h614487, csrf_mcounteren_tm_reg } ; + assign r1__read__h614487 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h614498 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h614504 = + { r1__read__h614506, csrf_software_int_pend_vec_1 } ; + assign r1__read__h614506 = { r1__read__h614508, 1'b0 } ; + assign r1__read__h614508 = + { r1__read__h614510, csrf_software_int_pend_vec_3 } ; + assign r1__read__h614510 = { r1__read__h614512, 1'b0 } ; + assign r1__read__h614512 = + { r1__read__h614514, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h614514 = { r1__read__h614516, 1'b0 } ; + assign r1__read__h614516 = + { r1__read__h614518, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h614518 = { r1__read__h614520, 1'b0 } ; + assign r1__read__h614520 = + { r1__read__h614522, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614522 = { r1__read__h614524, 1'b0 } ; + assign r1__read__h614524 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h614601 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h481761 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h481762 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h475907 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941 = + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = + regRenamingTable$RDY_rename_0_getRename && + regRenamingTable$RDY_rename_0_claimRename && + fetchStage$RDY_pipelines_0_deq && + fetchStage$RDY_pipelines_0_first && + epochManager$RDY_incrementEpoch && + (fetchStage$pipelines_0_first[194:192] != 3'd0 || + coreFix_aluExe_0_rsAlu$RDY_enq) ; + assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941 = regRenamingTable$RDY_rename_0_getRename && CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 && (fetchStage$pipelines_0_first[199:195] == 5'd14 || @@ -31278,12 +31319,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h685237 = + assign renaming_spec_bits__h685239 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h681632 : + y_avValue_fst__h681634 : specTagManager$currentSpecBits ; - assign res_data__h337868 = { 32'hFFFFFFFF, x__h337883 } ; - assign res_data__h337873 = + assign res_data__h337869 = { 32'hFFFFFFFF, x__h337884 } ; + assign res_data__h337874 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -31296,8 +31337,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h383570 = { 32'hFFFFFFFF, x__h383585 } ; - assign res_data__h383575 = + assign res_data__h383571 = { 32'hFFFFFFFF, x__h383586 } ; + assign res_data__h383576 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -31310,8 +31351,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h429265 = { 32'hFFFFFFFF, x__h429280 } ; - assign res_data__h429270 = + assign res_data__h429266 = { 32'hFFFFFFFF, x__h429281 } ; + assign res_data__h429271 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -31324,7 +31365,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h337869 = + assign res_fflags__h337870 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -31392,7 +31433,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 } ; - assign res_fflags__h383571 = + assign res_fflags__h383572 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -31460,7 +31501,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 } ; - assign res_fflags__h429266 = + assign res_fflags__h429267 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31528,74 +31569,85 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 } ; - assign resp_addr__h291970 = + assign resp_addr__h291971 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h364336 = + assign result__h364337 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[0] | - guard__h364331 } ; - assign result__h410033 = + guard__h364332 } ; + assign result__h410034 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[0] | - guard__h410028 } ; - assign result__h455728 = + guard__h410029 } ; + assign result__h455729 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[0] | - guard__h455723 } ; - assign result__h503481 = + guard__h455724 } ; + assign result__h503482 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[0] | - guard__h503476 } ; - assign result__h542334 = + guard__h503477 } ; + assign result__h542335 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[0] | - guard__h542329 } ; - assign result__h581638 = + guard__h542330 } ; + assign result__h581639 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[0] | - guard__h581633 } ; - assign result__h646693 = w__h646688 & y__h646722 ; - assign result__h646744 = ~x__h646743 ; - assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716 = + guard__h581634 } ; + assign result__h646695 = w__h646690 & y__h646724 ; + assign result__h646746 = ~x__h646745 ; + assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15729 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h612205 = - { r1__read__h614599, csrf_rg_tdata1_data } ; - assign rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988 = - rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq && + assign rg_tdata1__read__h612207 = + { r1__read__h614601, csrf_rg_tdata1_data } ; + assign rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998 = + rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && - NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983 ; - assign rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309 = - rob$RDY_enqPort_0_enq && - regRenamingTable$RDY_rename_0_claimRename && - regRenamingTable$RDY_rename_0_getRename && - fetchStage$RDY_pipelines_0_first && - fetchStage$RDY_pipelines_0_deq && - (fetchStage$pipelines_0_first[194:192] != 3'd0 || - coreFix_aluExe_0_rsAlu$RDY_enq) ; - assign rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393 = + NOT_rob_deqPort_0_deq_data__4339_BITS_329_TO_3_ETC___d14993 ; + assign rob_deqPort_0_deq_data__4339_BITS_161_TO_98_43_ETC___d15292 = + { rob$deqPort_0_deq_data[161:98], + (rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[97:96] == 2'd0) ? + { 2'd0, rob$deqPort_0_deq_data[95:32] } : + ((rob$deqPort_0_deq_data[329:325] != 5'd13 && + rob$deqPort_0_deq_data[97:96] == 2'd1) ? + { 2'd1, rob$deqPort_0_deq_data[95:32] } : + { 2'd2, + (rob$deqPort_0_deq_data[329:325] == 5'd13) ? + data_warl_xformed__h722429 : + rob$deqPort_0_deq_data[95:32] }), + 5'h0A, + rob$deqPort_0_deq_data[26], + 64'hAAAAAAAAAAAAAAAA, + x_prv__h723013, + 64'hAAAAAAAAAAAAAAAA, + x__h726431, + 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404 = { rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 : - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 } ; - assign rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494 = + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 : + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ; + assign rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505 = { rob$deqPort_0_deq_data[181], - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 } ; + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h655326 = + assign rs1__h655328 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h610078 = { r1__read__h614196, csrf_ppn_reg } ; + assign satp_csr__read__h610080 = { r1__read__h614198, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 && @@ -31615,175 +31667,175 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 && IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629) ; - assign sbIdx__h157150 = + assign sbIdx__h157151 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h609875 = - { r1__read__h613980, csrf_scause_code_reg } ; - assign scounteren_csr__read__h609737 = - { r1__read__h613967, csrf_scounteren_cy_reg } ; - assign sfd__h338479 = { value__h346706, 3'd0 } ; - assign sfd__h354287 = + assign scause_csr__read__h609877 = + { r1__read__h613982, csrf_scause_code_reg } ; + assign scounteren_csr__read__h609739 = + { r1__read__h613969, csrf_scounteren_cy_reg } ; + assign sfd__h338480 = { value__h346707, 3'd0 } ; + assign sfd__h354288 = { 1'b0, - _theResult___fst_exp__h354195 != 8'd0, - sfdin__h354189[56:34] } + + _theResult___fst_exp__h354196 != 8'd0, + sfdin__h354190[56:34] } + 25'd1 ; - assign sfd__h362869 = + assign sfd__h362870 = { 1'b0, - _theResult___fst_exp__h362851 != 8'd0, - _theResult___snd__h362802[56:34] } + + _theResult___fst_exp__h362852 != 8'd0, + _theResult___snd__h362803[56:34] } + 25'd1 ; - assign sfd__h372053 = + assign sfd__h372054 = { 1'b0, - _theResult___fst_exp__h371961 != 8'd0, - sfdin__h371955[56:34] } + + _theResult___fst_exp__h371962 != 8'd0, + sfdin__h371956[56:34] } + 25'd1 ; - assign sfd__h380665 = + assign sfd__h380666 = { 1'b0, - _theResult___fst_exp__h380646 != 8'd0, - _theResult___snd__h380592[56:34] } + + _theResult___fst_exp__h380647 != 8'd0, + _theResult___snd__h380593[56:34] } + 25'd1 ; - assign sfd__h384181 = { value__h392403, 3'd0 } ; - assign sfd__h399984 = + assign sfd__h384182 = { value__h392404, 3'd0 } ; + assign sfd__h399985 = { 1'b0, - _theResult___fst_exp__h399892 != 8'd0, - sfdin__h399886[56:34] } + + _theResult___fst_exp__h399893 != 8'd0, + sfdin__h399887[56:34] } + 25'd1 ; - assign sfd__h408566 = + assign sfd__h408567 = { 1'b0, - _theResult___fst_exp__h408548 != 8'd0, - _theResult___snd__h408499[56:34] } + + _theResult___fst_exp__h408549 != 8'd0, + _theResult___snd__h408500[56:34] } + 25'd1 ; - assign sfd__h417750 = + assign sfd__h417751 = { 1'b0, - _theResult___fst_exp__h417658 != 8'd0, - sfdin__h417652[56:34] } + + _theResult___fst_exp__h417659 != 8'd0, + sfdin__h417653[56:34] } + 25'd1 ; - assign sfd__h426362 = + assign sfd__h426363 = { 1'b0, - _theResult___fst_exp__h426343 != 8'd0, - _theResult___snd__h426289[56:34] } + + _theResult___fst_exp__h426344 != 8'd0, + _theResult___snd__h426290[56:34] } + 25'd1 ; - assign sfd__h429876 = { value__h438098, 3'd0 } ; - assign sfd__h445679 = + assign sfd__h429877 = { value__h438099, 3'd0 } ; + assign sfd__h445680 = { 1'b0, - _theResult___fst_exp__h445587 != 8'd0, - sfdin__h445581[56:34] } + + _theResult___fst_exp__h445588 != 8'd0, + sfdin__h445582[56:34] } + 25'd1 ; - assign sfd__h454261 = + assign sfd__h454262 = { 1'b0, - _theResult___fst_exp__h454243 != 8'd0, - _theResult___snd__h454194[56:34] } + + _theResult___fst_exp__h454244 != 8'd0, + _theResult___snd__h454195[56:34] } + 25'd1 ; - assign sfd__h463445 = + assign sfd__h463446 = { 1'b0, - _theResult___fst_exp__h463353 != 8'd0, - sfdin__h463347[56:34] } + + _theResult___fst_exp__h463354 != 8'd0, + sfdin__h463348[56:34] } + 25'd1 ; - assign sfd__h472057 = + assign sfd__h472058 = { 1'b0, - _theResult___fst_exp__h472038 != 8'd0, - _theResult___snd__h471984[56:34] } + + _theResult___fst_exp__h472039 != 8'd0, + _theResult___snd__h471985[56:34] } + 25'd1 ; - assign sfd__h482501 = { value__h487084, 32'd0 } ; - assign sfd__h501545 = + assign sfd__h482502 = { value__h487085, 32'd0 } ; + assign sfd__h501546 = { 1'b0, - _theResult___fst_exp__h501527 != 11'd0, - _theResult___snd__h501478[56:5] } + + _theResult___fst_exp__h501528 != 11'd0, + _theResult___snd__h501479[56:5] } + 54'd1 ; - assign sfd__h511196 = + assign sfd__h511197 = { 1'b0, - _theResult___fst_exp__h511104 != 11'd0, - sfdin__h511098[56:5] } + + _theResult___fst_exp__h511105 != 11'd0, + sfdin__h511099[56:5] } + 54'd1 ; - assign sfd__h519956 = + assign sfd__h519957 = { 1'b0, - _theResult___fst_exp__h519937 != 11'd0, - _theResult___snd__h519883[56:5] } + + _theResult___fst_exp__h519938 != 11'd0, + _theResult___snd__h519884[56:5] } + 54'd1 ; - assign sfd__h521495 = { value__h525937, 32'd0 } ; - assign sfd__h540398 = + assign sfd__h521496 = { value__h525938, 32'd0 } ; + assign sfd__h540399 = { 1'b0, - _theResult___fst_exp__h540380 != 11'd0, - _theResult___snd__h540331[56:5] } + + _theResult___fst_exp__h540381 != 11'd0, + _theResult___snd__h540332[56:5] } + 54'd1 ; - assign sfd__h550049 = + assign sfd__h550050 = { 1'b0, - _theResult___fst_exp__h549957 != 11'd0, - sfdin__h549951[56:5] } + + _theResult___fst_exp__h549958 != 11'd0, + sfdin__h549952[56:5] } + 54'd1 ; - assign sfd__h558809 = + assign sfd__h558810 = { 1'b0, - _theResult___fst_exp__h558790 != 11'd0, - _theResult___snd__h558736[56:5] } + + _theResult___fst_exp__h558791 != 11'd0, + _theResult___snd__h558737[56:5] } + 54'd1 ; - assign sfd__h560799 = { value__h565241, 32'd0 } ; - assign sfd__h579702 = + assign sfd__h560800 = { value__h565242, 32'd0 } ; + assign sfd__h579703 = { 1'b0, - _theResult___fst_exp__h579684 != 11'd0, - _theResult___snd__h579635[56:5] } + + _theResult___fst_exp__h579685 != 11'd0, + _theResult___snd__h579636[56:5] } + 54'd1 ; - assign sfd__h589353 = + assign sfd__h589354 = { 1'b0, - _theResult___fst_exp__h589261 != 11'd0, - sfdin__h589255[56:5] } + + _theResult___fst_exp__h589262 != 11'd0, + sfdin__h589256[56:5] } + 54'd1 ; - assign sfd__h598113 = + assign sfd__h598114 = { 1'b0, - _theResult___fst_exp__h598094 != 11'd0, - _theResult___snd__h598040[56:5] } + + _theResult___fst_exp__h598095 != 11'd0, + _theResult___snd__h598041[56:5] } + 54'd1 ; - assign sfdin__h354189 = - _theResult____h346084[56] ? - _theResult___snd__h354206 : - _theResult___snd__h354217 ; - assign sfdin__h371955 = - _theResult____h363723[56] ? - _theResult___snd__h371972 : - _theResult___snd__h371983 ; - assign sfdin__h399886 = - _theResult____h391783[56] ? - _theResult___snd__h399903 : - _theResult___snd__h399914 ; - assign sfdin__h417652 = - _theResult____h409420[56] ? - _theResult___snd__h417669 : - _theResult___snd__h417680 ; - assign sfdin__h445581 = - _theResult____h437478[56] ? - _theResult___snd__h445598 : - _theResult___snd__h445609 ; - assign sfdin__h463347 = - _theResult____h455115[56] ? - _theResult___snd__h463364 : - _theResult___snd__h463375 ; - assign sfdin__h511098 = - _theResult____h502868[56] ? - _theResult___snd__h511115 : - _theResult___snd__h511126 ; - assign sfdin__h549951 = - _theResult____h541721[56] ? - _theResult___snd__h549968 : - _theResult___snd__h549979 ; - assign sfdin__h589255 = - _theResult____h581025[56] ? - _theResult___snd__h589272 : - _theResult___snd__h589283 ; - assign shiftData__h181566 = - coreFix_memExe_regToExeQ$first[75:12] << x__h181698 ; - assign sie_csr__read__h609641 = { r1__read__h613452, 1'b0 } ; - assign sip_csr__read__h610015 = { r1__read__h613986, 1'b0 } ; - assign spec_bits__h688396 = specTagManager$currentSpecBits | y__h688409 ; - assign sstatus_csr__read__h609571 = { r1__read__h613048, csrf_ie_vec_0 } ; - assign stvec_csr__read__h609684 = - { r1__read__h613962, csrf_stvec_mode_low_reg } ; - assign trap_val__h708464 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h709502 ; - assign tsr_val__h725552 = csrf_tsr_reg ; - assign tvm_val__h725554 = csrf_tvm_reg ; + assign sfdin__h354190 = + _theResult____h346085[56] ? + _theResult___snd__h354207 : + _theResult___snd__h354218 ; + assign sfdin__h371956 = + _theResult____h363724[56] ? + _theResult___snd__h371973 : + _theResult___snd__h371984 ; + assign sfdin__h399887 = + _theResult____h391784[56] ? + _theResult___snd__h399904 : + _theResult___snd__h399915 ; + assign sfdin__h417653 = + _theResult____h409421[56] ? + _theResult___snd__h417670 : + _theResult___snd__h417681 ; + assign sfdin__h445582 = + _theResult____h437479[56] ? + _theResult___snd__h445599 : + _theResult___snd__h445610 ; + assign sfdin__h463348 = + _theResult____h455116[56] ? + _theResult___snd__h463365 : + _theResult___snd__h463376 ; + assign sfdin__h511099 = + _theResult____h502869[56] ? + _theResult___snd__h511116 : + _theResult___snd__h511127 ; + assign sfdin__h549952 = + _theResult____h541722[56] ? + _theResult___snd__h549969 : + _theResult___snd__h549980 ; + assign sfdin__h589256 = + _theResult____h581026[56] ? + _theResult___snd__h589273 : + _theResult___snd__h589284 ; + assign shiftData__h181567 = + coreFix_memExe_regToExeQ$first[75:12] << x__h181699 ; + assign sie_csr__read__h609643 = { r1__read__h613454, 1'b0 } ; + assign sip_csr__read__h610017 = { r1__read__h613988, 1'b0 } ; + assign spec_bits__h688398 = specTagManager$currentSpecBits | y__h688411 ; + assign sstatus_csr__read__h609573 = { r1__read__h613050, csrf_ie_vec_0 } ; + assign stvec_csr__read__h609686 = + { r1__read__h613964, csrf_stvec_mode_low_reg } ; + assign trap_val__h709444 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h710482 ; + assign tsr_val__h726551 = csrf_tsr_reg ; + assign tvm_val__h726553 = csrf_tvm_reg ; assign upd__h3993 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : @@ -31793,255 +31845,254 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h726048 = + assign upd__h727048 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h295940 = + assign v__h295941 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031) ? - v__h296171 : + v__h296172 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h296171 = + assign v__h296172 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h299285 = + assign v__h299286 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138) ? - v__h299803 : + v__h299804 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h299803 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h309799 = + assign v__h299804 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h309800 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309) ? - v__h310030 : + v__h310031 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h310030 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h313675 = + assign v__h310031 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h313676 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405) ? - v__h313906 : + v__h313907 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h313906 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h328276 = + assign v__h313907 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h328277 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634) ? - v__h328507 : + v__h328508 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h328507 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h331501 = + assign v__h328508 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h331502 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728) ? - v__h331732 : + v__h331733 : coreFix_memExe_forwardQ_enqP ; - assign v__h331732 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h603882 = + assign v__h331733 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h603883 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h603892 : + v__h603893 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h603892 = + assign v__h603893 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h604527 = v__h603882 - 2'd1 ; - assign v__h607933 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608839 ; - assign v__h632816 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633569 ; - assign value_BIT_23___h494224 = f1_exp__h482139 != 8'd0 ; - assign value__h346706 = + assign v__h604528 = v__h603883 - 2'd1 ; + assign v__h607935 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608841 ; + assign v__h632818 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633571 ; + assign value__h346707 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h392403 = + assign value__h392404 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h438098 = + assign value__h438099 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h487084 = { 1'b0, value_BIT_23___h494224, f1_sfd__h482140 } ; - assign value__h525937 = { 1'b0, f2_exp__h521133 != 8'd0, f2_sfd__h521134 } ; - assign value__h565241 = { 1'b0, f3_exp__h560437 != 8'd0, f3_sfd__h560438 } ; - assign vm_mode_reg__read__h614202 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h646688 = + assign value__h487085 = { 1'b0, f1_exp__h482140 != 8'd0, f1_sfd__h482141 } ; + assign value__h525938 = { 1'b0, f2_exp__h521134 != 8'd0, f2_sfd__h521135 } ; + assign value__h565242 = { 1'b0, f3_exp__h560438 != 8'd0, f3_sfd__h560439 } ; + assign vm_mode_reg__read__h614204 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h646690 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h646744 : + result__h646746 : 12'd4095 ; - assign x__h153724 = + assign x__h153725 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h153730 = + assign x__h153731 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h157271 = { 3'd0, sbIdx__h157150 } ; - assign x__h157277 = + assign x__h157272 = { 3'd0, sbIdx__h157151 } ; + assign x__h157278 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h160087 = + assign x__h160088 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h160091 = + assign x__h160092 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161939 = + assign x__h161940 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h181475 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180563 ; assign x__h181476 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181169 ; - assign x__h181698 = { x__h183901[2:0], 3'b0 } ; - assign x__h18384 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180564 ; + assign x__h181477 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181170 ; + assign x__h181699 = { x__h183902[2:0], 3'b0 } ; + assign x__h18385 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h183901 = + assign x__h183902 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ; - assign x__h193678 = + assign x__h193679 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h192915[63:32] : - curData__h192915[31:0] ; - assign x__h20922 = + curData__h192916[63:32] : + curData__h192916[31:0] ; + assign x__h20923 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h287278 = + assign x__h287279 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h287290 = + assign x__h287291 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h289144 = + assign x__h289145 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h302150 = + assign x__h302151 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h337883 = - { (_theResult___exp__h381215 != 8'd255 || - _theResult___sfd__h381216 == 23'd0) && + assign x__h337884 = + { (_theResult___exp__h381216 != 8'd255 || + _theResult___sfd__h381217 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140, - out_f_exp__h381492, - out_f_sfd__h381493 } ; - assign x__h364433 = - sfd__h338479 << (x__h364466[11] ? 12'hAAA : x__h364466) ; - assign x__h364466 = + out_f_exp__h381493, + out_f_sfd__h381494 } ; + assign x__h364434 = + sfd__h338480 << (x__h364467[11] ? 12'hAAA : x__h364467) ; + assign x__h364467 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ; - assign x__h383585 = - { (_theResult___exp__h426912 != 8'd255 || - _theResult___sfd__h426913 == 23'd0) && + assign x__h383586 = + { (_theResult___exp__h426913 != 8'd255 || + _theResult___sfd__h426914 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532, - out_f_exp__h427189, - out_f_sfd__h427190 } ; - assign x__h410130 = - sfd__h384181 << (x__h410163[11] ? 12'hAAA : x__h410163) ; - assign x__h410163 = + out_f_exp__h427190, + out_f_sfd__h427191 } ; + assign x__h410131 = + sfd__h384182 << (x__h410164[11] ? 12'hAAA : x__h410164) ; + assign x__h410164 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ; - assign x__h429280 = - { (_theResult___exp__h472607 != 8'd255 || - _theResult___sfd__h472608 == 23'd0) && + assign x__h429281 = + { (_theResult___exp__h472608 != 8'd255 || + _theResult___sfd__h472609 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924, - out_f_exp__h472884, - out_f_sfd__h472885 } ; - assign x__h455825 = - sfd__h429876 << (x__h455858[11] ? 12'hAAA : x__h455858) ; - assign x__h455858 = + out_f_exp__h472885, + out_f_sfd__h472886 } ; + assign x__h455826 = + sfd__h429877 << (x__h455859[11] ? 12'hAAA : x__h455859) ; + assign x__h455859 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ; - assign x__h46291 = + assign x__h46292 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h481669 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478805 ; assign x__h481670 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479413 ; + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478806 ; assign x__h481671 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480015 ; - assign x__h48827 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479414 ; + assign x__h481672 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480016 ; + assign x__h48828 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h503576 = sfd__h482501 << x__h503609 ; - assign x__h503609 = + assign x__h503577 = sfd__h482502 << x__h503610 ; + assign x__h503610 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; - assign x__h542429 = sfd__h521495 << x__h542462 ; - assign x__h542462 = + assign x__h542430 = sfd__h521496 << x__h542463 ; + assign x__h542463 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; - assign x__h581733 = sfd__h560799 << x__h581766 ; - assign x__h581766 = + assign x__h581734 = sfd__h560800 << x__h581767 ; + assign x__h581767 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; - assign x__h603383 = a__h602947[63] ^ b__h602948[63] ; - assign x__h613033 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h617230 = + assign x__h603384 = a__h602948[63] ^ b__h602949[63] ; + assign x__h613035 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h617232 = coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h609049 : - v__h607933 ; - assign x__h617231 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615055 ; - assign x__h639739 = + rVal1__h609051 : + v__h607935 ; + assign x__h617233 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615057 ; + assign x__h639741 = coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h633777 : - v__h632816 ; - assign x__h639740 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637574 ; - assign x__h646692 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h646743 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h701397 = + rVal1__h633779 : + v__h632818 ; + assign x__h639742 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637576 ; + assign x__h646694 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h646745 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h702377 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h711438 = { cause_code__h708463, 2'b0 } ; - assign x__h713649 = + assign x__h712418 = { cause_code__h709443, 2'b0 } ; + assign x__h714645 = { csrf_fs_reg == 2'b11, - IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909 } ; - assign x__h713841 = - { commitStage_commitTrap[36], 59'b0, cause_code__h708463 } ; - assign x__h721573 = { 1'b0, csrf_spp_reg } ; - assign x__h725432 = + IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 } ; + assign x__h714837 = + { commitStage_commitTrap[36], 59'b0, cause_code__h709443 } ; + assign x__h722556 = { 1'b0, csrf_spp_reg } ; + assign x__h726431 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32052,9 +32103,9 @@ module mkCore(CLK, csrf_mprv_reg, 2'd0, csrf_fs_reg, - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271 } ; - assign x__h728883 = - { r1__read_BITS_62_TO_14___h728903, + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15282 } ; + assign x__h729900 = + { r1__read_BITS_62_TO_14___h729920, 2'b11, csrf_mpp_reg, 2'b0, @@ -32067,54 +32118,54 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h732011 = - { y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993[63:15], + assign x__h733045 = + { y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027[63:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993[12:0] } ; - assign x__h732759 = - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ? - y_avValue_snd_snd_snd_fst__h732569 : - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 ; - assign x__h76236 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h314073 = + y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027[12:0] } ; + assign x__h733794 = + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 ? + y_avValue_snd_snd_snd_fst__h733604 : + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 ; + assign x__h76237 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h314074 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h66085 = + assign x_data__h66086 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h676655 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h692709 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h655010 = csrf_frm_reg ; - assign x_prv__h711506 = - csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ? + assign x_data_imm__h676657 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h692711 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h655012 = csrf_frm_reg ; + assign x_prv__h712487 = + csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? 2'd1 : 2'd3 ; - assign x_prv__h722029 = + assign x_prv__h723013 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h721573 : + x__h722556 : csrf_mpp_reg ; - assign x_quotient__h475195 = + assign x_quotient__h475196 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h475880 : + q___1__h475881 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h609480 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h475196 = + assign x_reg_ifc__read__h609482 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h475197 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h475906 : + r___1__h475907 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h254802 = + assign y__h254803 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h646722 = ~x__h646692 ; - assign y__h651653 = + assign y__h646724 = ~x__h646694 ; + assign y__h651655 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -32123,66 +32174,66 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h688409 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h729714 = + assign y__h688411 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h730732 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h729737 : + y_avValue_snd_snd_snd_snd_snd_fst__h730755 : 64'd0 ; - assign y__h732518 = - NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ? - y_avValue_snd_snd_snd_snd_snd_fst__h732579 : - y__h729714 ; - assign y_avValue__h180563 = + assign y__h733553 = + NOT_rob_deqPort_0_canDeq__5314_5315_OR_rob_deq_ETC___d15658 ? + y_avValue_snd_snd_snd_snd_snd_fst__h733614 : + y__h730732 ; + assign y_avValue__h180564 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 ; - assign y_avValue__h181169 = + assign y_avValue__h181170 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 ; - assign y_avValue__h478805 = + assign y_avValue__h478806 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 ; - assign y_avValue__h479413 = + assign y_avValue__h479414 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 ; - assign y_avValue__h480015 = + assign y_avValue__h480016 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 ; - assign y_avValue__h608839 = + assign y_avValue__h608841 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 ; - assign y_avValue__h615055 = + assign y_avValue__h615057 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 ; - assign y_avValue__h633569 = + assign y_avValue__h633571 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 ; - assign y_avValue__h637574 = + assign y_avValue__h637576 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ; - assign y_avValue_fst__h681569 = + assign y_avValue_fst__h681571 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h688396 : + spec_bits__h688398 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681598 = + assign y_avValue_fst__h681600 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ? - y_avValue_fst__h681569 : + y_avValue_fst__h681571 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681632 = + assign y_avValue_fst__h681634 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429) ? - y_avValue_fst__h681598 : + y_avValue_fst__h681600 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h729252 = + assign y_avValue_fst__h730270 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32196,10 +32247,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h732400 = - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 | + assign y_avValue_fst__h733435 = + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h732432 = + assign y_avValue_fst__h733467 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32211,17 +32262,17 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 : - y_avValue_fst__h732400 ; - assign y_avValue_new_pc__h711199 = + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15664 : + y_avValue_fst__h733435 ; + assign y_avValue_new_pc__h712179 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h711423 + { 58'd0, x__h711438 } : - base__h711423 ; - assign y_avValue_new_pc__h711385 = + base__h712403 + { 58'd0, x__h712418 } : + base__h712403 ; + assign y_avValue_new_pc__h712365 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h711443 + { 58'd0, x__h711438 } : - base__h711443 ; - assign y_avValue_snd_snd_snd_fst__h729727 = + base__h712423 + { 58'd0, x__h712418 } : + base__h712423 ; + assign y_avValue_snd_snd_snd_fst__h730745 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32235,7 +32286,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h732569 = + assign y_avValue_snd_snd_snd_fst__h733604 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32247,12 +32298,12 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 : - y_avValue_snd_snd_snd_fst__h732605 ; - assign y_avValue_snd_snd_snd_fst__h732605 = - IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 + + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 : + y_avValue_snd_snd_snd_fst__h733640 ; + assign y_avValue_snd_snd_snd_fst__h733640 = + IF_rob_deqPort_0_canDeq__5314_THEN_IF_NOT_rob__ETC___d15683 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h729737 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h730755 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32266,7 +32317,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h732579 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h733614 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32278,10 +32329,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h729714 : - y_avValue_snd_snd_snd_snd_snd_fst__h732615 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h732615 = y__h729714 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993 = x__h728883 ; + y__h730732 : + y_avValue_snd_snd_snd_snd_snd_fst__h733650 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h733650 = y__h730732 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h733027 = x__h729900 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32482,28 +32533,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h197125 = + x__h197126 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -32519,28 +32570,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h285845 = + x__h285846 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -32550,10 +32601,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h290066 = + addr__h290067 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h290066 = + addr__h290067 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -32562,37 +32613,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h192915 = + curData__h192916 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h709502 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h709502 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h709502 = + 4'd0, 4'd3: trap_val__h710482 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h710482 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h710482 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -32606,425 +32657,425 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h291615 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h291616 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h291615 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h291616 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h609350 or - frm_csr__read__h609361 or - fcsr_csr__read__h609375 or - sstatus_csr__read__h609571 or - sie_csr__read__h609641 or - stvec_csr__read__h609684 or - scounteren_csr__read__h609737 or + fflags_csr__read__h609352 or + frm_csr__read__h609363 or + fcsr_csr__read__h609377 or + sstatus_csr__read__h609573 or + sie_csr__read__h609643 or + stvec_csr__read__h609686 or + scounteren_csr__read__h609739 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609875 or + scause_csr__read__h609877 or csrf_stval_csr or - sip_csr__read__h610015 or - satp_csr__read__h610078 or - mstatus_csr__read__h610221 or - medeleg_csr__read__h610369 or - mideleg_csr__read__h610464 or - mie_csr__read__h610588 or - mtvec_csr__read__h610670 or - mcounteren_csr__read__h610762 or + sip_csr__read__h610017 or + satp_csr__read__h610080 or + mstatus_csr__read__h610223 or + medeleg_csr__read__h610371 or + mideleg_csr__read__h610466 or + mie_csr__read__h610590 or + mtvec_csr__read__h610672 or + mcounteren_csr__read__h610764 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611017 or + mcause_csr__read__h611019 or csrf_mtval_csr or - mip_csr__read__h611250 or + mip_csr__read__h611252 or csrf_rg_tselect or - rg_tdata1__read__h612205 or + rg_tdata1__read__h612207 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609480 or - n__read__h611354 or n__read__h611545 or csrf_time_reg) + x_reg_ifc__read__h609482 or + n__read__h611356 or n__read__h611547 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h736609 = fflags_csr__read__h609350; - 12'd2: data_out__h736609 = frm_csr__read__h609361; - 12'd3: data_out__h736609 = fcsr_csr__read__h609375; - 12'd256: data_out__h736609 = sstatus_csr__read__h609571; - 12'd260: data_out__h736609 = sie_csr__read__h609641; - 12'd261: data_out__h736609 = stvec_csr__read__h609684; - 12'd262: data_out__h736609 = scounteren_csr__read__h609737; - 12'd320: data_out__h736609 = csrf_sscratch_csr; - 12'd321: data_out__h736609 = csrf_sepc_csr; - 12'd322: data_out__h736609 = scause_csr__read__h609875; - 12'd323: data_out__h736609 = csrf_stval_csr; - 12'd324: data_out__h736609 = sip_csr__read__h610015; - 12'd384: data_out__h736609 = satp_csr__read__h610078; - 12'd768: data_out__h736609 = mstatus_csr__read__h610221; - 12'd769: data_out__h736609 = 64'h800000000014112D; - 12'd770: data_out__h736609 = medeleg_csr__read__h610369; - 12'd771: data_out__h736609 = mideleg_csr__read__h610464; - 12'd772: data_out__h736609 = mie_csr__read__h610588; - 12'd773: data_out__h736609 = mtvec_csr__read__h610670; - 12'd774: data_out__h736609 = mcounteren_csr__read__h610762; - 12'd832: data_out__h736609 = csrf_mscratch_csr; - 12'd833: data_out__h736609 = csrf_mepc_csr; - 12'd834: data_out__h736609 = mcause_csr__read__h611017; - 12'd835: data_out__h736609 = csrf_mtval_csr; - 12'd836: data_out__h736609 = mip_csr__read__h611250; - 12'd1952: data_out__h736609 = csrf_rg_tselect; - 12'd1953: data_out__h736609 = rg_tdata1__read__h612205; - 12'd1954: data_out__h736609 = csrf_rg_tdata2; - 12'd1955: data_out__h736609 = csrf_rg_tdata3; - 12'd1968: data_out__h736609 = csrf_rg_dcsr; - 12'd1969: data_out__h736609 = csrf_rg_dpc; - 12'd1970: data_out__h736609 = csrf_rg_dscratch0; - 12'd1971: data_out__h736609 = csrf_rg_dscratch1; + 12'd1: data_out__h737644 = fflags_csr__read__h609352; + 12'd2: data_out__h737644 = frm_csr__read__h609363; + 12'd3: data_out__h737644 = fcsr_csr__read__h609377; + 12'd256: data_out__h737644 = sstatus_csr__read__h609573; + 12'd260: data_out__h737644 = sie_csr__read__h609643; + 12'd261: data_out__h737644 = stvec_csr__read__h609686; + 12'd262: data_out__h737644 = scounteren_csr__read__h609739; + 12'd320: data_out__h737644 = csrf_sscratch_csr; + 12'd321: data_out__h737644 = csrf_sepc_csr; + 12'd322: data_out__h737644 = scause_csr__read__h609877; + 12'd323: data_out__h737644 = csrf_stval_csr; + 12'd324: data_out__h737644 = sip_csr__read__h610017; + 12'd384: data_out__h737644 = satp_csr__read__h610080; + 12'd768: data_out__h737644 = mstatus_csr__read__h610223; + 12'd769: data_out__h737644 = 64'h800000000014112D; + 12'd770: data_out__h737644 = medeleg_csr__read__h610371; + 12'd771: data_out__h737644 = mideleg_csr__read__h610466; + 12'd772: data_out__h737644 = mie_csr__read__h610590; + 12'd773: data_out__h737644 = mtvec_csr__read__h610672; + 12'd774: data_out__h737644 = mcounteren_csr__read__h610764; + 12'd832: data_out__h737644 = csrf_mscratch_csr; + 12'd833: data_out__h737644 = csrf_mepc_csr; + 12'd834: data_out__h737644 = mcause_csr__read__h611019; + 12'd835: data_out__h737644 = csrf_mtval_csr; + 12'd836: data_out__h737644 = mip_csr__read__h611252; + 12'd1952: data_out__h737644 = csrf_rg_tselect; + 12'd1953: data_out__h737644 = rg_tdata1__read__h612207; + 12'd1954: data_out__h737644 = csrf_rg_tdata2; + 12'd1955: data_out__h737644 = csrf_rg_tdata3; + 12'd1968: data_out__h737644 = csrf_rg_dcsr; + 12'd1969: data_out__h737644 = csrf_rg_dpc; + 12'd1970: data_out__h737644 = csrf_rg_dscratch0; + 12'd1971: data_out__h737644 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h736609 = 64'd0; - 12'd2049: data_out__h736609 = x_reg_ifc__read__h609480; - 12'd2816, 12'd3072: data_out__h736609 = n__read__h611354; - 12'd2818, 12'd3074: data_out__h736609 = n__read__h611545; - 12'd3073: data_out__h736609 = csrf_time_reg; - default: data_out__h736609 = 64'b0; + data_out__h737644 = 64'd0; + 12'd2049: data_out__h737644 = x_reg_ifc__read__h609482; + 12'd2816, 12'd3072: data_out__h737644 = n__read__h611356; + 12'd2818, 12'd3074: data_out__h737644 = n__read__h611547; + 12'd3073: data_out__h737644 = csrf_time_reg; + default: data_out__h737644 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h609350 or - frm_csr__read__h609361 or - fcsr_csr__read__h609375 or - sstatus_csr__read__h609571 or - sie_csr__read__h609641 or - stvec_csr__read__h609684 or - scounteren_csr__read__h609737 or + fflags_csr__read__h609352 or + frm_csr__read__h609363 or + fcsr_csr__read__h609377 or + sstatus_csr__read__h609573 or + sie_csr__read__h609643 or + stvec_csr__read__h609686 or + scounteren_csr__read__h609739 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609875 or + scause_csr__read__h609877 or csrf_stval_csr or - sip_csr__read__h610015 or - satp_csr__read__h610078 or - mstatus_csr__read__h610221 or - medeleg_csr__read__h610369 or - mideleg_csr__read__h610464 or - mie_csr__read__h610588 or - mtvec_csr__read__h610670 or - mcounteren_csr__read__h610762 or + sip_csr__read__h610017 or + satp_csr__read__h610080 or + mstatus_csr__read__h610223 or + medeleg_csr__read__h610371 or + mideleg_csr__read__h610466 or + mie_csr__read__h610590 or + mtvec_csr__read__h610672 or + mcounteren_csr__read__h610764 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611017 or + mcause_csr__read__h611019 or csrf_mtval_csr or - mip_csr__read__h611250 or + mip_csr__read__h611252 or csrf_rg_tselect or - rg_tdata1__read__h612205 or + rg_tdata1__read__h612207 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609480 or - n__read__h611354 or n__read__h611545 or csrf_time_reg) + x_reg_ifc__read__h609482 or + n__read__h611356 or n__read__h611547 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h609049 = fflags_csr__read__h609350; - 12'd2: rVal1__h609049 = frm_csr__read__h609361; - 12'd3: rVal1__h609049 = fcsr_csr__read__h609375; - 12'd256: rVal1__h609049 = sstatus_csr__read__h609571; - 12'd260: rVal1__h609049 = sie_csr__read__h609641; - 12'd261: rVal1__h609049 = stvec_csr__read__h609684; - 12'd262: rVal1__h609049 = scounteren_csr__read__h609737; - 12'd320: rVal1__h609049 = csrf_sscratch_csr; - 12'd321: rVal1__h609049 = csrf_sepc_csr; - 12'd322: rVal1__h609049 = scause_csr__read__h609875; - 12'd323: rVal1__h609049 = csrf_stval_csr; - 12'd324: rVal1__h609049 = sip_csr__read__h610015; - 12'd384: rVal1__h609049 = satp_csr__read__h610078; - 12'd768: rVal1__h609049 = mstatus_csr__read__h610221; - 12'd769: rVal1__h609049 = 64'h800000000014112D; - 12'd770: rVal1__h609049 = medeleg_csr__read__h610369; - 12'd771: rVal1__h609049 = mideleg_csr__read__h610464; - 12'd772: rVal1__h609049 = mie_csr__read__h610588; - 12'd773: rVal1__h609049 = mtvec_csr__read__h610670; - 12'd774: rVal1__h609049 = mcounteren_csr__read__h610762; - 12'd832: rVal1__h609049 = csrf_mscratch_csr; - 12'd833: rVal1__h609049 = csrf_mepc_csr; - 12'd834: rVal1__h609049 = mcause_csr__read__h611017; - 12'd835: rVal1__h609049 = csrf_mtval_csr; - 12'd836: rVal1__h609049 = mip_csr__read__h611250; - 12'd1952: rVal1__h609049 = csrf_rg_tselect; - 12'd1953: rVal1__h609049 = rg_tdata1__read__h612205; - 12'd1954: rVal1__h609049 = csrf_rg_tdata2; - 12'd1955: rVal1__h609049 = csrf_rg_tdata3; - 12'd1968: rVal1__h609049 = csrf_rg_dcsr; - 12'd1969: rVal1__h609049 = csrf_rg_dpc; - 12'd1970: rVal1__h609049 = csrf_rg_dscratch0; - 12'd1971: rVal1__h609049 = csrf_rg_dscratch1; + 12'd1: rVal1__h609051 = fflags_csr__read__h609352; + 12'd2: rVal1__h609051 = frm_csr__read__h609363; + 12'd3: rVal1__h609051 = fcsr_csr__read__h609377; + 12'd256: rVal1__h609051 = sstatus_csr__read__h609573; + 12'd260: rVal1__h609051 = sie_csr__read__h609643; + 12'd261: rVal1__h609051 = stvec_csr__read__h609686; + 12'd262: rVal1__h609051 = scounteren_csr__read__h609739; + 12'd320: rVal1__h609051 = csrf_sscratch_csr; + 12'd321: rVal1__h609051 = csrf_sepc_csr; + 12'd322: rVal1__h609051 = scause_csr__read__h609877; + 12'd323: rVal1__h609051 = csrf_stval_csr; + 12'd324: rVal1__h609051 = sip_csr__read__h610017; + 12'd384: rVal1__h609051 = satp_csr__read__h610080; + 12'd768: rVal1__h609051 = mstatus_csr__read__h610223; + 12'd769: rVal1__h609051 = 64'h800000000014112D; + 12'd770: rVal1__h609051 = medeleg_csr__read__h610371; + 12'd771: rVal1__h609051 = mideleg_csr__read__h610466; + 12'd772: rVal1__h609051 = mie_csr__read__h610590; + 12'd773: rVal1__h609051 = mtvec_csr__read__h610672; + 12'd774: rVal1__h609051 = mcounteren_csr__read__h610764; + 12'd832: rVal1__h609051 = csrf_mscratch_csr; + 12'd833: rVal1__h609051 = csrf_mepc_csr; + 12'd834: rVal1__h609051 = mcause_csr__read__h611019; + 12'd835: rVal1__h609051 = csrf_mtval_csr; + 12'd836: rVal1__h609051 = mip_csr__read__h611252; + 12'd1952: rVal1__h609051 = csrf_rg_tselect; + 12'd1953: rVal1__h609051 = rg_tdata1__read__h612207; + 12'd1954: rVal1__h609051 = csrf_rg_tdata2; + 12'd1955: rVal1__h609051 = csrf_rg_tdata3; + 12'd1968: rVal1__h609051 = csrf_rg_dcsr; + 12'd1969: rVal1__h609051 = csrf_rg_dpc; + 12'd1970: rVal1__h609051 = csrf_rg_dscratch0; + 12'd1971: rVal1__h609051 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h609049 = 64'd0; - 12'd2049: rVal1__h609049 = x_reg_ifc__read__h609480; - 12'd2816, 12'd3072: rVal1__h609049 = n__read__h611354; - 12'd2818, 12'd3074: rVal1__h609049 = n__read__h611545; - 12'd3073: rVal1__h609049 = csrf_time_reg; - default: rVal1__h609049 = 64'b0; + rVal1__h609051 = 64'd0; + 12'd2049: rVal1__h609051 = x_reg_ifc__read__h609482; + 12'd2816, 12'd3072: rVal1__h609051 = n__read__h611356; + 12'd2818, 12'd3074: rVal1__h609051 = n__read__h611547; + 12'd3073: rVal1__h609051 = csrf_time_reg; + default: rVal1__h609051 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h609350 or - frm_csr__read__h609361 or - fcsr_csr__read__h609375 or - sstatus_csr__read__h609571 or - sie_csr__read__h609641 or - stvec_csr__read__h609684 or - scounteren_csr__read__h609737 or + fflags_csr__read__h609352 or + frm_csr__read__h609363 or + fcsr_csr__read__h609377 or + sstatus_csr__read__h609573 or + sie_csr__read__h609643 or + stvec_csr__read__h609686 or + scounteren_csr__read__h609739 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609875 or + scause_csr__read__h609877 or csrf_stval_csr or - sip_csr__read__h610015 or - satp_csr__read__h610078 or - mstatus_csr__read__h610221 or - medeleg_csr__read__h610369 or - mideleg_csr__read__h610464 or - mie_csr__read__h610588 or - mtvec_csr__read__h610670 or - mcounteren_csr__read__h610762 or + sip_csr__read__h610017 or + satp_csr__read__h610080 or + mstatus_csr__read__h610223 or + medeleg_csr__read__h610371 or + mideleg_csr__read__h610466 or + mie_csr__read__h610590 or + mtvec_csr__read__h610672 or + mcounteren_csr__read__h610764 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611017 or + mcause_csr__read__h611019 or csrf_mtval_csr or - mip_csr__read__h611250 or + mip_csr__read__h611252 or csrf_rg_tselect or - rg_tdata1__read__h612205 or + rg_tdata1__read__h612207 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609480 or - n__read__h611354 or n__read__h611545 or csrf_time_reg) + x_reg_ifc__read__h609482 or + n__read__h611356 or n__read__h611547 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h633777 = fflags_csr__read__h609350; - 12'd2: rVal1__h633777 = frm_csr__read__h609361; - 12'd3: rVal1__h633777 = fcsr_csr__read__h609375; - 12'd256: rVal1__h633777 = sstatus_csr__read__h609571; - 12'd260: rVal1__h633777 = sie_csr__read__h609641; - 12'd261: rVal1__h633777 = stvec_csr__read__h609684; - 12'd262: rVal1__h633777 = scounteren_csr__read__h609737; - 12'd320: rVal1__h633777 = csrf_sscratch_csr; - 12'd321: rVal1__h633777 = csrf_sepc_csr; - 12'd322: rVal1__h633777 = scause_csr__read__h609875; - 12'd323: rVal1__h633777 = csrf_stval_csr; - 12'd324: rVal1__h633777 = sip_csr__read__h610015; - 12'd384: rVal1__h633777 = satp_csr__read__h610078; - 12'd768: rVal1__h633777 = mstatus_csr__read__h610221; - 12'd769: rVal1__h633777 = 64'h800000000014112D; - 12'd770: rVal1__h633777 = medeleg_csr__read__h610369; - 12'd771: rVal1__h633777 = mideleg_csr__read__h610464; - 12'd772: rVal1__h633777 = mie_csr__read__h610588; - 12'd773: rVal1__h633777 = mtvec_csr__read__h610670; - 12'd774: rVal1__h633777 = mcounteren_csr__read__h610762; - 12'd832: rVal1__h633777 = csrf_mscratch_csr; - 12'd833: rVal1__h633777 = csrf_mepc_csr; - 12'd834: rVal1__h633777 = mcause_csr__read__h611017; - 12'd835: rVal1__h633777 = csrf_mtval_csr; - 12'd836: rVal1__h633777 = mip_csr__read__h611250; - 12'd1952: rVal1__h633777 = csrf_rg_tselect; - 12'd1953: rVal1__h633777 = rg_tdata1__read__h612205; - 12'd1954: rVal1__h633777 = csrf_rg_tdata2; - 12'd1955: rVal1__h633777 = csrf_rg_tdata3; - 12'd1968: rVal1__h633777 = csrf_rg_dcsr; - 12'd1969: rVal1__h633777 = csrf_rg_dpc; - 12'd1970: rVal1__h633777 = csrf_rg_dscratch0; - 12'd1971: rVal1__h633777 = csrf_rg_dscratch1; + 12'd1: rVal1__h633779 = fflags_csr__read__h609352; + 12'd2: rVal1__h633779 = frm_csr__read__h609363; + 12'd3: rVal1__h633779 = fcsr_csr__read__h609377; + 12'd256: rVal1__h633779 = sstatus_csr__read__h609573; + 12'd260: rVal1__h633779 = sie_csr__read__h609643; + 12'd261: rVal1__h633779 = stvec_csr__read__h609686; + 12'd262: rVal1__h633779 = scounteren_csr__read__h609739; + 12'd320: rVal1__h633779 = csrf_sscratch_csr; + 12'd321: rVal1__h633779 = csrf_sepc_csr; + 12'd322: rVal1__h633779 = scause_csr__read__h609877; + 12'd323: rVal1__h633779 = csrf_stval_csr; + 12'd324: rVal1__h633779 = sip_csr__read__h610017; + 12'd384: rVal1__h633779 = satp_csr__read__h610080; + 12'd768: rVal1__h633779 = mstatus_csr__read__h610223; + 12'd769: rVal1__h633779 = 64'h800000000014112D; + 12'd770: rVal1__h633779 = medeleg_csr__read__h610371; + 12'd771: rVal1__h633779 = mideleg_csr__read__h610466; + 12'd772: rVal1__h633779 = mie_csr__read__h610590; + 12'd773: rVal1__h633779 = mtvec_csr__read__h610672; + 12'd774: rVal1__h633779 = mcounteren_csr__read__h610764; + 12'd832: rVal1__h633779 = csrf_mscratch_csr; + 12'd833: rVal1__h633779 = csrf_mepc_csr; + 12'd834: rVal1__h633779 = mcause_csr__read__h611019; + 12'd835: rVal1__h633779 = csrf_mtval_csr; + 12'd836: rVal1__h633779 = mip_csr__read__h611252; + 12'd1952: rVal1__h633779 = csrf_rg_tselect; + 12'd1953: rVal1__h633779 = rg_tdata1__read__h612207; + 12'd1954: rVal1__h633779 = csrf_rg_tdata2; + 12'd1955: rVal1__h633779 = csrf_rg_tdata3; + 12'd1968: rVal1__h633779 = csrf_rg_dcsr; + 12'd1969: rVal1__h633779 = csrf_rg_dpc; + 12'd1970: rVal1__h633779 = csrf_rg_dscratch0; + 12'd1971: rVal1__h633779 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h633777 = 64'd0; - 12'd2049: rVal1__h633777 = x_reg_ifc__read__h609480; - 12'd2816, 12'd3072: rVal1__h633777 = n__read__h611354; - 12'd2818, 12'd3074: rVal1__h633777 = n__read__h611545; - 12'd3073: rVal1__h633777 = csrf_time_reg; - default: rVal1__h633777 = 64'b0; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd2046; - 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2047 : - 11'd2046; - 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = - (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == - 32'hFFFFFFFF && - coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - 11'd2046 : - 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd0; + rVal1__h633779 = 64'd0; + 12'd2049: rVal1__h633779 = x_reg_ifc__read__h609482; + 12'd2816, 12'd3072: rVal1__h633779 = n__read__h611356; + 12'd2818, 12'd3074: rVal1__h633779 = n__read__h611547; + 12'd3073: rVal1__h633779 = csrf_time_reg; + default: rVal1__h633779 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h346066 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h346067 = 8'd255; 3'd2: - _theResult___fst_exp__h346066 = + _theResult___fst_exp__h346067 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h346066 = + _theResult___fst_exp__h346067 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h346066 = 8'd254; - default: _theResult___fst_exp__h346066 = 8'd0; + 3'd4: _theResult___fst_exp__h346067 = 8'd254; + default: _theResult___fst_exp__h346067 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h346067 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h346068 = 23'd0; 3'd2: - _theResult___fst_sfd__h346067 = + _theResult___fst_sfd__h346068 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h346067 = + _theResult___fst_sfd__h346068 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h346067 = 23'd8388607; - default: _theResult___fst_sfd__h346067 = 23'd0; + 3'd4: _theResult___fst_sfd__h346068 = 23'd8388607; + default: _theResult___fst_sfd__h346068 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h391765 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h391766 = 8'd255; 3'd2: - _theResult___fst_exp__h391765 = + _theResult___fst_exp__h391766 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h391765 = + _theResult___fst_exp__h391766 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h391765 = 8'd254; - default: _theResult___fst_exp__h391765 = 8'd0; + 3'd4: _theResult___fst_exp__h391766 = 8'd254; + default: _theResult___fst_exp__h391766 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h391766 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h391767 = 23'd0; 3'd2: - _theResult___fst_sfd__h391766 = + _theResult___fst_sfd__h391767 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h391766 = + _theResult___fst_sfd__h391767 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h391766 = 23'd8388607; - default: _theResult___fst_sfd__h391766 = 23'd0; + 3'd4: _theResult___fst_sfd__h391767 = 23'd8388607; + default: _theResult___fst_sfd__h391767 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h437460 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h437461 = 8'd255; 3'd2: - _theResult___fst_exp__h437460 = + _theResult___fst_exp__h437461 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h437460 = + _theResult___fst_exp__h437461 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h437460 = 8'd254; - default: _theResult___fst_exp__h437460 = 8'd0; + 3'd4: _theResult___fst_exp__h437461 = 8'd254; + default: _theResult___fst_exp__h437461 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h437461 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h437462 = 23'd0; 3'd2: - _theResult___fst_sfd__h437461 = + _theResult___fst_sfd__h437462 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h437461 = + _theResult___fst_sfd__h437462 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h437461 = 23'd8388607; - default: _theResult___fst_sfd__h437461 = 23'd0; + 3'd4: _theResult___fst_sfd__h437462 = 23'd8388607; + default: _theResult___fst_sfd__h437462 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046; + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2047 : 11'd2046; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 11'd2046 : 11'd2047; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'hFFFFFFFFFFFFF; 3'd2: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'd0 : 52'hFFFFFFFFFFFFF; 3'd3: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? 52'hFFFFFFFFFFFFF : 52'd0; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046; + 3'd2: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2047 : + 11'd2046; + 3'd3: + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = + (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == + 32'hFFFFFFFF && + coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? + 11'd2046 : + 11'd2047; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33110,16 +33161,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h708478 = commitStage_commitTrap[35:32]; - default: i__h708478 = 4'd15; + i__h709458 = commitStage_commitTrap[35:32]; + default: i__h709458 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h708638 = commitStage_commitTrap[35:32]; - default: i__h708638 = 4'd15; + i__h709618 = commitStage_commitTrap[35:32]; + default: i__h709618 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -33180,17 +33231,6 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) - begin - case (coreFix_memExe_lsq$firstLd[19]) - 1'd0: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[31:0]; - 1'd1: - SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = - mmio_dataRespQ_data_0[63:32]; - endcase - end - always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:18]) 2'd0: @@ -33208,6 +33248,17 @@ module mkCore(CLK, endcase end always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) + begin + case (coreFix_memExe_lsq$firstLd[19]) + 1'd0: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[31:0]; + 1'd1: + SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 = + mmio_dataRespQ_data_0[63:32]; + endcase + end + always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0) begin case (coreFix_memExe_lsq$firstLd[19:17]) 3'd0: @@ -33347,446 +33398,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h354803 or - _theResult___fst_exp__h362851 or - out_exp__h363296 or _theResult___exp__h363293) + always@(guard__h354804 or + _theResult___fst_exp__h362852 or + out_exp__h363297 or _theResult___exp__h363294) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 = - _theResult___fst_exp__h362851; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 = + _theResult___fst_exp__h362852; 2'b10: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 = - out_exp__h363296; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 = + out_exp__h363297; 2'b11: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 = - _theResult___exp__h363293; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 = + _theResult___exp__h363294; endcase end - always@(guard__h354803 or - _theResult___fst_exp__h362851 or _theResult___exp__h363293) + always@(guard__h354804 or + _theResult___fst_exp__h362852 or _theResult___exp__h363294) begin - case (guard__h354803) + case (guard__h354804) 2'b0: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 = - _theResult___fst_exp__h362851; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33 = + _theResult___fst_exp__h362852; 2'b01, 2'b10, 2'b11: - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 = - _theResult___exp__h363293; + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33 = + _theResult___exp__h363294; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 or - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 or + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32 or + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 or - _theResult___fst_exp__h362851) + _theResult___fst_exp__h362852) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h363371 = - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32; + _theResult___fst_exp__h363372 = + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q32; 3'd1: - _theResult___fst_exp__h363371 = - CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33; + _theResult___fst_exp__h363372 = + CASE_guard54804_0b0_theResult___fst_exp62852_0_ETC__q33; 3'd2: - _theResult___fst_exp__h363371 = + _theResult___fst_exp__h363372 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532; 3'd3: - _theResult___fst_exp__h363371 = + _theResult___fst_exp__h363372 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534; - 3'd4: _theResult___fst_exp__h363371 = _theResult___fst_exp__h362851; - default: _theResult___fst_exp__h363371 = 8'd0; + 3'd4: _theResult___fst_exp__h363372 = _theResult___fst_exp__h362852; + default: _theResult___fst_exp__h363372 = 8'd0; endcase end - always@(guard__h346094 or - _theResult___fst_exp__h354195 or - out_exp__h354714 or _theResult___exp__h354711) + always@(guard__h346095 or + _theResult___fst_exp__h354196 or + out_exp__h354715 or _theResult___exp__h354712) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 = - _theResult___fst_exp__h354195; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 = + _theResult___fst_exp__h354196; 2'b10: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 = - out_exp__h354714; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 = + out_exp__h354715; 2'b11: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 = - _theResult___exp__h354711; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 = + _theResult___exp__h354712; endcase end - always@(guard__h346094 or - _theResult___fst_exp__h354195 or _theResult___exp__h354711) + always@(guard__h346095 or + _theResult___fst_exp__h354196 or _theResult___exp__h354712) begin - case (guard__h346094) + case (guard__h346095) 2'b0: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 = - _theResult___fst_exp__h354195; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35 = + _theResult___fst_exp__h354196; 2'b01, 2'b10, 2'b11: - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 = - _theResult___exp__h354711; + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35 = + _theResult___exp__h354712; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 or - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 or + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34 or + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 or - _theResult___fst_exp__h354195) + _theResult___fst_exp__h354196) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h354789 = - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34; + _theResult___fst_exp__h354790 = + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q34; 3'd1: - _theResult___fst_exp__h354789 = - CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35; + _theResult___fst_exp__h354790 = + CASE_guard46095_0b0_theResult___fst_exp54196_0_ETC__q35; 3'd2: - _theResult___fst_exp__h354789 = + _theResult___fst_exp__h354790 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310; 3'd3: - _theResult___fst_exp__h354789 = + _theResult___fst_exp__h354790 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313; - 3'd4: _theResult___fst_exp__h354789 = _theResult___fst_exp__h354195; - default: _theResult___fst_exp__h354789 = 8'd0; + 3'd4: _theResult___fst_exp__h354790 = _theResult___fst_exp__h354196; + default: _theResult___fst_exp__h354790 = 8'd0; endcase end - always@(guard__h363733 or - _theResult___fst_exp__h371961 or - out_exp__h372480 or _theResult___exp__h372477) + always@(guard__h363734 or + _theResult___fst_exp__h371962 or + out_exp__h372481 or _theResult___exp__h372478) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 = - _theResult___fst_exp__h371961; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 = + _theResult___fst_exp__h371962; 2'b10: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 = - out_exp__h372480; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 = + out_exp__h372481; 2'b11: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 = - _theResult___exp__h372477; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 = + _theResult___exp__h372478; endcase end - always@(guard__h363733 or - _theResult___fst_exp__h371961 or _theResult___exp__h372477) + always@(guard__h363734 or + _theResult___fst_exp__h371962 or _theResult___exp__h372478) begin - case (guard__h363733) + case (guard__h363734) 2'b0: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 = - _theResult___fst_exp__h371961; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41 = + _theResult___fst_exp__h371962; 2'b01, 2'b10, 2'b11: - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 = - _theResult___exp__h372477; + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41 = + _theResult___exp__h372478; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 or - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 or + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40 or + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 or - _theResult___fst_exp__h371961) + _theResult___fst_exp__h371962) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h372555 = - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40; + _theResult___fst_exp__h372556 = + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q40; 3'd1: - _theResult___fst_exp__h372555 = - CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41; + _theResult___fst_exp__h372556 = + CASE_guard63734_0b0_theResult___fst_exp71962_0_ETC__q41; 3'd2: - _theResult___fst_exp__h372555 = + _theResult___fst_exp__h372556 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857; 3'd3: - _theResult___fst_exp__h372555 = + _theResult___fst_exp__h372556 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859; - 3'd4: _theResult___fst_exp__h372555 = _theResult___fst_exp__h371961; - default: _theResult___fst_exp__h372555 = 8'd0; + 3'd4: _theResult___fst_exp__h372556 = _theResult___fst_exp__h371962; + default: _theResult___fst_exp__h372556 = 8'd0; endcase end - always@(guard__h372569 or - _theResult___fst_exp__h380646 or - out_exp__h381116 or _theResult___exp__h381113) + always@(guard__h372570 or + _theResult___fst_exp__h380647 or + out_exp__h381117 or _theResult___exp__h381114) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 = - _theResult___fst_exp__h380646; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 = + _theResult___fst_exp__h380647; 2'b10: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 = - out_exp__h381116; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 = + out_exp__h381117; 2'b11: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 = - _theResult___exp__h381113; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 = + _theResult___exp__h381114; endcase end - always@(guard__h372569 or - _theResult___fst_exp__h380646 or _theResult___exp__h381113) + always@(guard__h372570 or + _theResult___fst_exp__h380647 or _theResult___exp__h381114) begin - case (guard__h372569) + case (guard__h372570) 2'b0: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 = - _theResult___fst_exp__h380646; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46 = + _theResult___fst_exp__h380647; 2'b01, 2'b10, 2'b11: - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 = - _theResult___exp__h381113; + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46 = + _theResult___exp__h381114; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 or - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 or + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45 or + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 or - _theResult___fst_exp__h380646) + _theResult___fst_exp__h380647) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h381191 = - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45; + _theResult___fst_exp__h381192 = + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q45; 3'd1: - _theResult___fst_exp__h381191 = - CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46; + _theResult___fst_exp__h381192 = + CASE_guard72570_0b0_theResult___fst_exp80647_0_ETC__q46; 3'd2: - _theResult___fst_exp__h381191 = + _theResult___fst_exp__h381192 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926; 3'd3: - _theResult___fst_exp__h381191 = + _theResult___fst_exp__h381192 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928; - 3'd4: _theResult___fst_exp__h381191 = _theResult___fst_exp__h380646; - default: _theResult___fst_exp__h381191 = 8'd0; + 3'd4: _theResult___fst_exp__h381192 = _theResult___fst_exp__h380647; + default: _theResult___fst_exp__h381192 = 8'd0; endcase end - always@(guard__h354803 or - _theResult___snd__h362802 or - out_sfd__h363297 or _theResult___sfd__h363294) + always@(guard__h354804 or + _theResult___snd__h362803 or + out_sfd__h363298 or _theResult___sfd__h363295) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 = - _theResult___snd__h362802[56:34]; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 = + _theResult___snd__h362803[56:34]; 2'b10: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 = - out_sfd__h363297; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 = + out_sfd__h363298; 2'b11: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 = - _theResult___sfd__h363294; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 = + _theResult___sfd__h363295; endcase end - always@(guard__h354803 or - _theResult___snd__h362802 or _theResult___sfd__h363294) + always@(guard__h354804 or + _theResult___snd__h362803 or _theResult___sfd__h363295) begin - case (guard__h354803) + case (guard__h354804) 2'b0: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 = - _theResult___snd__h362802[56:34]; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48 = + _theResult___snd__h362803[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 = - _theResult___sfd__h363294; + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48 = + _theResult___sfd__h363295; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 or - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 or + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47 or + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or - _theResult___snd__h362802) + _theResult___snd__h362803) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h363372 = - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47; + _theResult___fst_sfd__h363373 = + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q47; 3'd1: - _theResult___fst_sfd__h363372 = - CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48; + _theResult___fst_sfd__h363373 = + CASE_guard54804_0b0_theResult___snd62803_BITS__ETC__q48; 3'd2: - _theResult___fst_sfd__h363372 = + _theResult___fst_sfd__h363373 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; 3'd3: - _theResult___fst_sfd__h363372 = + _theResult___fst_sfd__h363373 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978; - 3'd4: _theResult___fst_sfd__h363372 = _theResult___snd__h362802[56:34]; - default: _theResult___fst_sfd__h363372 = 23'd0; + 3'd4: _theResult___fst_sfd__h363373 = _theResult___snd__h362803[56:34]; + default: _theResult___fst_sfd__h363373 = 23'd0; endcase end - always@(guard__h346094 or - sfdin__h354189 or out_sfd__h354715 or _theResult___sfd__h354712) + always@(guard__h346095 or + sfdin__h354190 or out_sfd__h354716 or _theResult___sfd__h354713) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 = - sfdin__h354189[56:34]; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354190[56:34]; 2'b10: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 = - out_sfd__h354715; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354716; 2'b11: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 = - _theResult___sfd__h354712; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354713; endcase end - always@(guard__h346094 or sfdin__h354189 or _theResult___sfd__h354712) + always@(guard__h346095 or sfdin__h354190 or _theResult___sfd__h354713) begin - case (guard__h346094) + case (guard__h346095) 2'b0: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 = - sfdin__h354189[56:34]; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354190[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h354712; + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354713; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 or - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 or + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354189) + sfdin__h354190) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h354790 = - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49; + _theResult___fst_sfd__h354791 = + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q49; 3'd1: - _theResult___fst_sfd__h354790 = - CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h354791 = + CASE_guard46095_0b0_sfdin54190_BITS_56_TO_34_0_ETC__q50; 3'd2: - _theResult___fst_sfd__h354790 = + _theResult___fst_sfd__h354791 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; 3'd3: - _theResult___fst_sfd__h354790 = + _theResult___fst_sfd__h354791 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354790 = sfdin__h354189[56:34]; - default: _theResult___fst_sfd__h354790 = 23'd0; + 3'd4: _theResult___fst_sfd__h354791 = sfdin__h354190[56:34]; + default: _theResult___fst_sfd__h354791 = 23'd0; endcase end - always@(guard__h363733 or - sfdin__h371955 or out_sfd__h372481 or _theResult___sfd__h372478) + always@(guard__h363734 or + sfdin__h371956 or out_sfd__h372482 or _theResult___sfd__h372479) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 = - sfdin__h371955[56:34]; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 = + sfdin__h371956[56:34]; 2'b10: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 = - out_sfd__h372481; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 = + out_sfd__h372482; 2'b11: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h372478; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h372479; endcase end - always@(guard__h363733 or sfdin__h371955 or _theResult___sfd__h372478) + always@(guard__h363734 or sfdin__h371956 or _theResult___sfd__h372479) begin - case (guard__h363733) + case (guard__h363734) 2'b0: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 = - sfdin__h371955[56:34]; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52 = + sfdin__h371956[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h372478; + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h372479; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 or - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 or + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51 or + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 or - sfdin__h371955) + sfdin__h371956) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h372556 = - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h372557 = + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q51; 3'd1: - _theResult___fst_sfd__h372556 = - CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h372557 = + CASE_guard63734_0b0_sfdin71956_BITS_56_TO_34_0_ETC__q52; 3'd2: - _theResult___fst_sfd__h372556 = + _theResult___fst_sfd__h372557 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003; 3'd3: - _theResult___fst_sfd__h372556 = + _theResult___fst_sfd__h372557 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005; - 3'd4: _theResult___fst_sfd__h372556 = sfdin__h371955[56:34]; - default: _theResult___fst_sfd__h372556 = 23'd0; + 3'd4: _theResult___fst_sfd__h372557 = sfdin__h371956[56:34]; + default: _theResult___fst_sfd__h372557 = 23'd0; endcase end - always@(guard__h372569 or - _theResult___snd__h380592 or - out_sfd__h381117 or _theResult___sfd__h381114) + always@(guard__h372570 or + _theResult___snd__h380593 or + out_sfd__h381118 or _theResult___sfd__h381115) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 = - _theResult___snd__h380592[56:34]; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 = + _theResult___snd__h380593[56:34]; 2'b10: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 = - out_sfd__h381117; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 = + out_sfd__h381118; 2'b11: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 = - _theResult___sfd__h381114; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 = + _theResult___sfd__h381115; endcase end - always@(guard__h372569 or - _theResult___snd__h380592 or _theResult___sfd__h381114) + always@(guard__h372570 or + _theResult___snd__h380593 or _theResult___sfd__h381115) begin - case (guard__h372569) + case (guard__h372570) 2'b0: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 = - _theResult___snd__h380592[56:34]; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54 = + _theResult___snd__h380593[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 = - _theResult___sfd__h381114; + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54 = + _theResult___sfd__h381115; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 or - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 or + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53 or + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___snd__h380592) + _theResult___snd__h380593) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h381192 = - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53; + _theResult___fst_sfd__h381193 = + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q53; 3'd1: - _theResult___fst_sfd__h381192 = - CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54; + _theResult___fst_sfd__h381193 = + CASE_guard72570_0b0_theResult___snd80593_BITS__ETC__q54; 3'd2: - _theResult___fst_sfd__h381192 = + _theResult___fst_sfd__h381193 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_sfd__h381192 = + _theResult___fst_sfd__h381193 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_sfd__h381192 = _theResult___snd__h380592[56:34]; - default: _theResult___fst_sfd__h381192 = 23'd0; + 3'd4: _theResult___fst_sfd__h381193 = _theResult___snd__h380593[56:34]; + default: _theResult___fst_sfd__h381193 = 23'd0; endcase end - always@(guard__h346094 or + always@(guard__h346095 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01, 2'b10: - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = - guard__h346094 == 2'b11 && + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + guard__h346095 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or - guard__h346094) + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or + guard__h346095) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; + CASE_guard46095_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - (guard__h346094 == 2'b0) ? + (guard__h346095 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h346094 == 2'b01 || guard__h346094 == 2'b10 || - guard__h346094 == 2'b11) && + (guard__h346095 == 2'b01 || guard__h346095 == 2'b10 || + guard__h346095 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = @@ -33797,34 +33848,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h346094 or + always@(guard__h346095 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346094) + case (guard__h346095) 2'b0, 2'b01, 2'b10: - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - guard__h346094 != 2'b11 || + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + guard__h346095 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or - guard__h346094) + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or + guard__h346095) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; + CASE_guard46095_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - (guard__h346094 == 2'b0) ? + (guard__h346095 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h346094 != 2'b01 && guard__h346094 != 2'b10 && - guard__h346094 != 2'b11 || + guard__h346095 != 2'b01 && guard__h346095 != 2'b10 && + guard__h346095 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = @@ -33835,34 +33886,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354803 or + always@(guard__h354804 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01, 2'b10: - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = - guard__h354803 == 2'b11 && + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354804 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or - guard__h354803) + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354804) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + CASE_guard54804_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354803 == 2'b0) ? + (guard__h354804 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354803 == 2'b01 || guard__h354803 == 2'b10 || - guard__h354803 == 2'b11) && + (guard__h354804 == 2'b01 || guard__h354804 == 2'b10 || + guard__h354804 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = @@ -33873,34 +33924,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354803 or + always@(guard__h354804 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354803) + case (guard__h354804) 2'b0, 2'b01, 2'b10: - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = - guard__h354803 != 2'b11 || + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + guard__h354804 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or - guard__h354803) + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or + guard__h354804) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; + CASE_guard54804_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - (guard__h354803 == 2'b0) ? + (guard__h354804 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h354803 != 2'b01 && guard__h354803 != 2'b10 && - guard__h354803 != 2'b11 || + guard__h354804 != 2'b01 && guard__h354804 != 2'b10 && + guard__h354804 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = @@ -33911,34 +33962,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363733 or + always@(guard__h363734 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01, 2'b10: - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = - guard__h363733 == 2'b11 && + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + guard__h363734 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or - guard__h363733) + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or + guard__h363734) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; + CASE_guard63734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - (guard__h363733 == 2'b0) ? + (guard__h363734 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h363733 == 2'b01 || guard__h363733 == 2'b10 || - guard__h363733 == 2'b11) && + (guard__h363734 == 2'b01 || guard__h363734 == 2'b10 || + guard__h363734 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = @@ -33949,34 +34000,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363733 or + always@(guard__h363734 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363733) + case (guard__h363734) 2'b0, 2'b01, 2'b10: - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = - guard__h363733 != 2'b11 || + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + guard__h363734 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or - guard__h363733) + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or + guard__h363734) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; + CASE_guard63734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - (guard__h363733 == 2'b0) ? + (guard__h363734 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h363733 != 2'b01 && guard__h363733 != 2'b10 && - guard__h363733 != 2'b11 || + guard__h363734 != 2'b01 && guard__h363734 != 2'b10 && + guard__h363734 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = @@ -33987,34 +34038,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372569 or + always@(guard__h372570 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01, 2'b10: - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - guard__h372569 == 2'b11 && + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + guard__h372570 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or - guard__h372569) + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or + guard__h372570) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; + CASE_guard72570_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - (guard__h372569 == 2'b0) ? + (guard__h372570 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h372569 == 2'b01 || guard__h372569 == 2'b10 || - guard__h372569 == 2'b11) && + (guard__h372570 == 2'b01 || guard__h372570 == 2'b10 || + guard__h372570 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = @@ -34025,34 +34076,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372569 or + always@(guard__h372570 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372569) + case (guard__h372570) 2'b0, 2'b01, 2'b10: - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = - guard__h372569 != 2'b11 || + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + guard__h372570 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or - guard__h372569) + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or + guard__h372570) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; + CASE_guard72570_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - (guard__h372569 == 2'b0) ? + (guard__h372570 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h372569 != 2'b01 && guard__h372569 != 2'b10 && - guard__h372569 != 2'b11 || + guard__h372570 != 2'b01 && guard__h372570 != 2'b10 && + guard__h372570 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = @@ -34089,446 +34140,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h400500 or - _theResult___fst_exp__h408548 or - out_exp__h408993 or _theResult___exp__h408990) + always@(guard__h400501 or + _theResult___fst_exp__h408549 or + out_exp__h408994 or _theResult___exp__h408991) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 = - _theResult___fst_exp__h408548; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 = + _theResult___fst_exp__h408549; 2'b10: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 = - out_exp__h408993; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 = + out_exp__h408994; 2'b11: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 = - _theResult___exp__h408990; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 = + _theResult___exp__h408991; endcase end - always@(guard__h400500 or - _theResult___fst_exp__h408548 or _theResult___exp__h408990) + always@(guard__h400501 or + _theResult___fst_exp__h408549 or _theResult___exp__h408991) begin - case (guard__h400500) + case (guard__h400501) 2'b0: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 = - _theResult___fst_exp__h408548; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68 = + _theResult___fst_exp__h408549; 2'b01, 2'b10, 2'b11: - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 = - _theResult___exp__h408990; + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68 = + _theResult___exp__h408991; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 or - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 or + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67 or + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 or - _theResult___fst_exp__h408548) + _theResult___fst_exp__h408549) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h409068 = - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67; + _theResult___fst_exp__h409069 = + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q67; 3'd1: - _theResult___fst_exp__h409068 = - CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68; + _theResult___fst_exp__h409069 = + CASE_guard00501_0b0_theResult___fst_exp08549_0_ETC__q68; 3'd2: - _theResult___fst_exp__h409068 = + _theResult___fst_exp__h409069 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924; 3'd3: - _theResult___fst_exp__h409068 = + _theResult___fst_exp__h409069 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926; - 3'd4: _theResult___fst_exp__h409068 = _theResult___fst_exp__h408548; - default: _theResult___fst_exp__h409068 = 8'd0; + 3'd4: _theResult___fst_exp__h409069 = _theResult___fst_exp__h408549; + default: _theResult___fst_exp__h409069 = 8'd0; endcase end - always@(guard__h391793 or - _theResult___fst_exp__h399892 or - out_exp__h400411 or _theResult___exp__h400408) + always@(guard__h391794 or + _theResult___fst_exp__h399893 or + out_exp__h400412 or _theResult___exp__h400409) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 = - _theResult___fst_exp__h399892; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 = + _theResult___fst_exp__h399893; 2'b10: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 = - out_exp__h400411; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 = + out_exp__h400412; 2'b11: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 = - _theResult___exp__h400408; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 = + _theResult___exp__h400409; endcase end - always@(guard__h391793 or - _theResult___fst_exp__h399892 or _theResult___exp__h400408) + always@(guard__h391794 or + _theResult___fst_exp__h399893 or _theResult___exp__h400409) begin - case (guard__h391793) + case (guard__h391794) 2'b0: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 = - _theResult___fst_exp__h399892; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70 = + _theResult___fst_exp__h399893; 2'b01, 2'b10, 2'b11: - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 = - _theResult___exp__h400408; + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70 = + _theResult___exp__h400409; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 or - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 or + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69 or + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 or - _theResult___fst_exp__h399892) + _theResult___fst_exp__h399893) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h400486 = - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69; + _theResult___fst_exp__h400487 = + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q69; 3'd1: - _theResult___fst_exp__h400486 = - CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70; + _theResult___fst_exp__h400487 = + CASE_guard91794_0b0_theResult___fst_exp99893_0_ETC__q70; 3'd2: - _theResult___fst_exp__h400486 = + _theResult___fst_exp__h400487 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702; 3'd3: - _theResult___fst_exp__h400486 = + _theResult___fst_exp__h400487 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705; - 3'd4: _theResult___fst_exp__h400486 = _theResult___fst_exp__h399892; - default: _theResult___fst_exp__h400486 = 8'd0; + 3'd4: _theResult___fst_exp__h400487 = _theResult___fst_exp__h399893; + default: _theResult___fst_exp__h400487 = 8'd0; endcase end - always@(guard__h409430 or - _theResult___fst_exp__h417658 or - out_exp__h418177 or _theResult___exp__h418174) + always@(guard__h409431 or + _theResult___fst_exp__h417659 or + out_exp__h418178 or _theResult___exp__h418175) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 = - _theResult___fst_exp__h417658; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 = + _theResult___fst_exp__h417659; 2'b10: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 = - out_exp__h418177; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 = + out_exp__h418178; 2'b11: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 = - _theResult___exp__h418174; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 = + _theResult___exp__h418175; endcase end - always@(guard__h409430 or - _theResult___fst_exp__h417658 or _theResult___exp__h418174) + always@(guard__h409431 or + _theResult___fst_exp__h417659 or _theResult___exp__h418175) begin - case (guard__h409430) + case (guard__h409431) 2'b0: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 = - _theResult___fst_exp__h417658; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76 = + _theResult___fst_exp__h417659; 2'b01, 2'b10, 2'b11: - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 = - _theResult___exp__h418174; + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76 = + _theResult___exp__h418175; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 or - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 or + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75 or + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 or - _theResult___fst_exp__h417658) + _theResult___fst_exp__h417659) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h418252 = - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75; + _theResult___fst_exp__h418253 = + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q75; 3'd1: - _theResult___fst_exp__h418252 = - CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76; + _theResult___fst_exp__h418253 = + CASE_guard09431_0b0_theResult___fst_exp17659_0_ETC__q76; 3'd2: - _theResult___fst_exp__h418252 = + _theResult___fst_exp__h418253 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249; 3'd3: - _theResult___fst_exp__h418252 = + _theResult___fst_exp__h418253 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251; - 3'd4: _theResult___fst_exp__h418252 = _theResult___fst_exp__h417658; - default: _theResult___fst_exp__h418252 = 8'd0; + 3'd4: _theResult___fst_exp__h418253 = _theResult___fst_exp__h417659; + default: _theResult___fst_exp__h418253 = 8'd0; endcase end - always@(guard__h418266 or - _theResult___fst_exp__h426343 or - out_exp__h426813 or _theResult___exp__h426810) + always@(guard__h418267 or + _theResult___fst_exp__h426344 or + out_exp__h426814 or _theResult___exp__h426811) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 = - _theResult___fst_exp__h426343; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 = + _theResult___fst_exp__h426344; 2'b10: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 = - out_exp__h426813; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 = + out_exp__h426814; 2'b11: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 = - _theResult___exp__h426810; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 = + _theResult___exp__h426811; endcase end - always@(guard__h418266 or - _theResult___fst_exp__h426343 or _theResult___exp__h426810) + always@(guard__h418267 or + _theResult___fst_exp__h426344 or _theResult___exp__h426811) begin - case (guard__h418266) + case (guard__h418267) 2'b0: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 = - _theResult___fst_exp__h426343; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81 = + _theResult___fst_exp__h426344; 2'b01, 2'b10, 2'b11: - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 = - _theResult___exp__h426810; + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81 = + _theResult___exp__h426811; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 or - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 or + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80 or + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 or - _theResult___fst_exp__h426343) + _theResult___fst_exp__h426344) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h426888 = - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80; + _theResult___fst_exp__h426889 = + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q80; 3'd1: - _theResult___fst_exp__h426888 = - CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81; + _theResult___fst_exp__h426889 = + CASE_guard18267_0b0_theResult___fst_exp26344_0_ETC__q81; 3'd2: - _theResult___fst_exp__h426888 = + _theResult___fst_exp__h426889 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318; 3'd3: - _theResult___fst_exp__h426888 = + _theResult___fst_exp__h426889 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320; - 3'd4: _theResult___fst_exp__h426888 = _theResult___fst_exp__h426343; - default: _theResult___fst_exp__h426888 = 8'd0; + 3'd4: _theResult___fst_exp__h426889 = _theResult___fst_exp__h426344; + default: _theResult___fst_exp__h426889 = 8'd0; endcase end - always@(guard__h400500 or - _theResult___snd__h408499 or - out_sfd__h408994 or _theResult___sfd__h408991) + always@(guard__h400501 or + _theResult___snd__h408500 or + out_sfd__h408995 or _theResult___sfd__h408992) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 = - _theResult___snd__h408499[56:34]; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 = + _theResult___snd__h408500[56:34]; 2'b10: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 = - out_sfd__h408994; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 = + out_sfd__h408995; 2'b11: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 = - _theResult___sfd__h408991; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 = + _theResult___sfd__h408992; endcase end - always@(guard__h400500 or - _theResult___snd__h408499 or _theResult___sfd__h408991) + always@(guard__h400501 or + _theResult___snd__h408500 or _theResult___sfd__h408992) begin - case (guard__h400500) + case (guard__h400501) 2'b0: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 = - _theResult___snd__h408499[56:34]; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83 = + _theResult___snd__h408500[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 = - _theResult___sfd__h408991; + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83 = + _theResult___sfd__h408992; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 or - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 or + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82 or + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or - _theResult___snd__h408499) + _theResult___snd__h408500) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h409069 = - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82; + _theResult___fst_sfd__h409070 = + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q82; 3'd1: - _theResult___fst_sfd__h409069 = - CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83; + _theResult___fst_sfd__h409070 = + CASE_guard00501_0b0_theResult___snd08500_BITS__ETC__q83; 3'd2: - _theResult___fst_sfd__h409069 = + _theResult___fst_sfd__h409070 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; 3'd3: - _theResult___fst_sfd__h409069 = + _theResult___fst_sfd__h409070 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370; - 3'd4: _theResult___fst_sfd__h409069 = _theResult___snd__h408499[56:34]; - default: _theResult___fst_sfd__h409069 = 23'd0; + 3'd4: _theResult___fst_sfd__h409070 = _theResult___snd__h408500[56:34]; + default: _theResult___fst_sfd__h409070 = 23'd0; endcase end - always@(guard__h391793 or - sfdin__h399886 or out_sfd__h400412 or _theResult___sfd__h400409) + always@(guard__h391794 or + sfdin__h399887 or out_sfd__h400413 or _theResult___sfd__h400410) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 = - sfdin__h399886[56:34]; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399887[56:34]; 2'b10: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 = - out_sfd__h400412; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400413; 2'b11: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 = - _theResult___sfd__h400409; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400410; endcase end - always@(guard__h391793 or sfdin__h399886 or _theResult___sfd__h400409) + always@(guard__h391794 or sfdin__h399887 or _theResult___sfd__h400410) begin - case (guard__h391793) + case (guard__h391794) 2'b0: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 = - sfdin__h399886[56:34]; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399887[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 = - _theResult___sfd__h400409; + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400410; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 or - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 or + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399886) + sfdin__h399887) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h400487 = - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84; + _theResult___fst_sfd__h400488 = + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q84; 3'd1: - _theResult___fst_sfd__h400487 = - CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85; + _theResult___fst_sfd__h400488 = + CASE_guard91794_0b0_sfdin99887_BITS_56_TO_34_0_ETC__q85; 3'd2: - _theResult___fst_sfd__h400487 = + _theResult___fst_sfd__h400488 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; 3'd3: - _theResult___fst_sfd__h400487 = + _theResult___fst_sfd__h400488 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400487 = sfdin__h399886[56:34]; - default: _theResult___fst_sfd__h400487 = 23'd0; + 3'd4: _theResult___fst_sfd__h400488 = sfdin__h399887[56:34]; + default: _theResult___fst_sfd__h400488 = 23'd0; endcase end - always@(guard__h409430 or - sfdin__h417652 or out_sfd__h418178 or _theResult___sfd__h418175) + always@(guard__h409431 or + sfdin__h417653 or out_sfd__h418179 or _theResult___sfd__h418176) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 = - sfdin__h417652[56:34]; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 = + sfdin__h417653[56:34]; 2'b10: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 = - out_sfd__h418178; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 = + out_sfd__h418179; 2'b11: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h418175; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h418176; endcase end - always@(guard__h409430 or sfdin__h417652 or _theResult___sfd__h418175) + always@(guard__h409431 or sfdin__h417653 or _theResult___sfd__h418176) begin - case (guard__h409430) + case (guard__h409431) 2'b0: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 = - sfdin__h417652[56:34]; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87 = + sfdin__h417653[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h418175; + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h418176; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 or - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 or + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86 or + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 or - sfdin__h417652) + sfdin__h417653) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h418253 = - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h418254 = + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q86; 3'd1: - _theResult___fst_sfd__h418253 = - CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h418254 = + CASE_guard09431_0b0_sfdin17653_BITS_56_TO_34_0_ETC__q87; 3'd2: - _theResult___fst_sfd__h418253 = + _theResult___fst_sfd__h418254 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395; 3'd3: - _theResult___fst_sfd__h418253 = + _theResult___fst_sfd__h418254 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397; - 3'd4: _theResult___fst_sfd__h418253 = sfdin__h417652[56:34]; - default: _theResult___fst_sfd__h418253 = 23'd0; + 3'd4: _theResult___fst_sfd__h418254 = sfdin__h417653[56:34]; + default: _theResult___fst_sfd__h418254 = 23'd0; endcase end - always@(guard__h418266 or - _theResult___snd__h426289 or - out_sfd__h426814 or _theResult___sfd__h426811) + always@(guard__h418267 or + _theResult___snd__h426290 or + out_sfd__h426815 or _theResult___sfd__h426812) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 = - _theResult___snd__h426289[56:34]; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 = + _theResult___snd__h426290[56:34]; 2'b10: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 = - out_sfd__h426814; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 = + out_sfd__h426815; 2'b11: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 = - _theResult___sfd__h426811; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 = + _theResult___sfd__h426812; endcase end - always@(guard__h418266 or - _theResult___snd__h426289 or _theResult___sfd__h426811) + always@(guard__h418267 or + _theResult___snd__h426290 or _theResult___sfd__h426812) begin - case (guard__h418266) + case (guard__h418267) 2'b0: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 = - _theResult___snd__h426289[56:34]; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89 = + _theResult___snd__h426290[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 = - _theResult___sfd__h426811; + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89 = + _theResult___sfd__h426812; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 or - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 or + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88 or + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___snd__h426289) + _theResult___snd__h426290) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h426889 = - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88; + _theResult___fst_sfd__h426890 = + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q88; 3'd1: - _theResult___fst_sfd__h426889 = - CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89; + _theResult___fst_sfd__h426890 = + CASE_guard18267_0b0_theResult___snd26290_BITS__ETC__q89; 3'd2: - _theResult___fst_sfd__h426889 = + _theResult___fst_sfd__h426890 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_sfd__h426889 = + _theResult___fst_sfd__h426890 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_sfd__h426889 = _theResult___snd__h426289[56:34]; - default: _theResult___fst_sfd__h426889 = 23'd0; + 3'd4: _theResult___fst_sfd__h426890 = _theResult___snd__h426290[56:34]; + default: _theResult___fst_sfd__h426890 = 23'd0; endcase end - always@(guard__h391793 or + always@(guard__h391794 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01, 2'b10: - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = - guard__h391793 == 2'b11 && + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + guard__h391794 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or - guard__h391793) + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or + guard__h391794) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; + CASE_guard91794_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - (guard__h391793 == 2'b0) ? + (guard__h391794 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h391793 == 2'b01 || guard__h391793 == 2'b10 || - guard__h391793 == 2'b11) && + (guard__h391794 == 2'b01 || guard__h391794 == 2'b10 || + guard__h391794 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = @@ -34539,34 +34590,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h391793 or + always@(guard__h391794 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391793) + case (guard__h391794) 2'b0, 2'b01, 2'b10: - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = - guard__h391793 != 2'b11 || + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + guard__h391794 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or - guard__h391793) + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or + guard__h391794) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; + CASE_guard91794_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - (guard__h391793 == 2'b0) ? + (guard__h391794 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h391793 != 2'b01 && guard__h391793 != 2'b10 && - guard__h391793 != 2'b11 || + guard__h391794 != 2'b01 && guard__h391794 != 2'b10 && + guard__h391794 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = @@ -34577,34 +34628,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400500 or + always@(guard__h400501 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01, 2'b10: - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = - guard__h400500 == 2'b11 && + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + guard__h400501 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or - guard__h400500) + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or + guard__h400501) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; + CASE_guard00501_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - (guard__h400500 == 2'b0) ? + (guard__h400501 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h400500 == 2'b01 || guard__h400500 == 2'b10 || - guard__h400500 == 2'b11) && + (guard__h400501 == 2'b01 || guard__h400501 == 2'b10 || + guard__h400501 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = @@ -34615,34 +34666,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400500 or + always@(guard__h400501 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400500) + case (guard__h400501) 2'b0, 2'b01, 2'b10: - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = - guard__h400500 != 2'b11 || + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + guard__h400501 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or - guard__h400500) + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or + guard__h400501) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; + CASE_guard00501_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - (guard__h400500 == 2'b0) ? + (guard__h400501 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h400500 != 2'b01 && guard__h400500 != 2'b10 && - guard__h400500 != 2'b11 || + guard__h400501 != 2'b01 && guard__h400501 != 2'b10 && + guard__h400501 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = @@ -34653,34 +34704,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409430 or + always@(guard__h409431 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01, 2'b10: - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = - guard__h409430 == 2'b11 && + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + guard__h409431 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or - guard__h409430) + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or + guard__h409431) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; + CASE_guard09431_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - (guard__h409430 == 2'b0) ? + (guard__h409431 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h409430 == 2'b01 || guard__h409430 == 2'b10 || - guard__h409430 == 2'b11) && + (guard__h409431 == 2'b01 || guard__h409431 == 2'b10 || + guard__h409431 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = @@ -34691,34 +34742,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409430 or + always@(guard__h409431 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409430) + case (guard__h409431) 2'b0, 2'b01, 2'b10: - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = - guard__h409430 != 2'b11 || + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + guard__h409431 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or - guard__h409430) + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or + guard__h409431) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; + CASE_guard09431_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - (guard__h409430 == 2'b0) ? + (guard__h409431 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h409430 != 2'b01 && guard__h409430 != 2'b10 && - guard__h409430 != 2'b11 || + guard__h409431 != 2'b01 && guard__h409431 != 2'b10 && + guard__h409431 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = @@ -34729,34 +34780,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418266 or + always@(guard__h418267 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01, 2'b10: - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = - guard__h418266 == 2'b11 && + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + guard__h418267 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or - guard__h418266) + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or + guard__h418267) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; + CASE_guard18267_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - (guard__h418266 == 2'b0) ? + (guard__h418267 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h418266 == 2'b01 || guard__h418266 == 2'b10 || - guard__h418266 == 2'b11) && + (guard__h418267 == 2'b01 || guard__h418267 == 2'b10 || + guard__h418267 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = @@ -34767,34 +34818,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418266 or + always@(guard__h418267 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418266) + case (guard__h418267) 2'b0, 2'b01, 2'b10: - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = - guard__h418266 != 2'b11 || + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418267 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or - guard__h418266) + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418267) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + CASE_guard18267_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418266 == 2'b0) ? + (guard__h418267 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418266 != 2'b01 && guard__h418266 != 2'b10 && - guard__h418266 != 2'b11 || + guard__h418267 != 2'b01 && guard__h418267 != 2'b10 && + guard__h418267 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = @@ -34831,394 +34882,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h446195 or - _theResult___fst_exp__h454243 or - out_exp__h454688 or _theResult___exp__h454685) + always@(guard__h446196 or + _theResult___fst_exp__h454244 or + out_exp__h454689 or _theResult___exp__h454686) begin - case (guard__h446195) + case (guard__h446196) 2'b0, 2'b01: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 = - _theResult___fst_exp__h454243; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 = + _theResult___fst_exp__h454244; 2'b10: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 = - out_exp__h454688; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 = + out_exp__h454689; 2'b11: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 = - _theResult___exp__h454685; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 = + _theResult___exp__h454686; endcase end - always@(guard__h446195 or - _theResult___fst_exp__h454243 or _theResult___exp__h454685) + always@(guard__h446196 or + _theResult___fst_exp__h454244 or _theResult___exp__h454686) begin - case (guard__h446195) + case (guard__h446196) 2'b0: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 = - _theResult___fst_exp__h454243; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103 = + _theResult___fst_exp__h454244; 2'b01, 2'b10, 2'b11: - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 = - _theResult___exp__h454685; + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103 = + _theResult___exp__h454686; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 or - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 or + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102 or + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 or - _theResult___fst_exp__h454243) + _theResult___fst_exp__h454244) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h454763 = - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102; + _theResult___fst_exp__h454764 = + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q102; 3'd1: - _theResult___fst_exp__h454763 = - CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103; + _theResult___fst_exp__h454764 = + CASE_guard46196_0b0_theResult___fst_exp54244_0_ETC__q103; 3'd2: - _theResult___fst_exp__h454763 = + _theResult___fst_exp__h454764 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316; 3'd3: - _theResult___fst_exp__h454763 = + _theResult___fst_exp__h454764 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318; - 3'd4: _theResult___fst_exp__h454763 = _theResult___fst_exp__h454243; - default: _theResult___fst_exp__h454763 = 8'd0; + 3'd4: _theResult___fst_exp__h454764 = _theResult___fst_exp__h454244; + default: _theResult___fst_exp__h454764 = 8'd0; endcase end - always@(guard__h437488 or - _theResult___fst_exp__h445587 or - out_exp__h446106 or _theResult___exp__h446103) + always@(guard__h437489 or + _theResult___fst_exp__h445588 or + out_exp__h446107 or _theResult___exp__h446104) begin - case (guard__h437488) + case (guard__h437489) 2'b0, 2'b01: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 = - _theResult___fst_exp__h445587; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 = + _theResult___fst_exp__h445588; 2'b10: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 = - out_exp__h446106; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 = + out_exp__h446107; 2'b11: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 = - _theResult___exp__h446103; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 = + _theResult___exp__h446104; endcase end - always@(guard__h437488 or - _theResult___fst_exp__h445587 or _theResult___exp__h446103) + always@(guard__h437489 or + _theResult___fst_exp__h445588 or _theResult___exp__h446104) begin - case (guard__h437488) + case (guard__h437489) 2'b0: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 = - _theResult___fst_exp__h445587; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105 = + _theResult___fst_exp__h445588; 2'b01, 2'b10, 2'b11: - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 = - _theResult___exp__h446103; + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105 = + _theResult___exp__h446104; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 or - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 or + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104 or + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 or - _theResult___fst_exp__h445587) + _theResult___fst_exp__h445588) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h446181 = - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104; + _theResult___fst_exp__h446182 = + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q104; 3'd1: - _theResult___fst_exp__h446181 = - CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105; + _theResult___fst_exp__h446182 = + CASE_guard37489_0b0_theResult___fst_exp45588_0_ETC__q105; 3'd2: - _theResult___fst_exp__h446181 = + _theResult___fst_exp__h446182 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094; 3'd3: - _theResult___fst_exp__h446181 = + _theResult___fst_exp__h446182 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097; - 3'd4: _theResult___fst_exp__h446181 = _theResult___fst_exp__h445587; - default: _theResult___fst_exp__h446181 = 8'd0; + 3'd4: _theResult___fst_exp__h446182 = _theResult___fst_exp__h445588; + default: _theResult___fst_exp__h446182 = 8'd0; endcase end - always@(guard__h455125 or - _theResult___fst_exp__h463353 or - out_exp__h463872 or _theResult___exp__h463869) + always@(guard__h455126 or + _theResult___fst_exp__h463354 or + out_exp__h463873 or _theResult___exp__h463870) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 = - _theResult___fst_exp__h463353; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 = + _theResult___fst_exp__h463354; 2'b10: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 = - out_exp__h463872; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 = + out_exp__h463873; 2'b11: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 = - _theResult___exp__h463869; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 = + _theResult___exp__h463870; endcase end - always@(guard__h455125 or - _theResult___fst_exp__h463353 or _theResult___exp__h463869) + always@(guard__h455126 or + _theResult___fst_exp__h463354 or _theResult___exp__h463870) begin - case (guard__h455125) + case (guard__h455126) 2'b0: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 = - _theResult___fst_exp__h463353; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111 = + _theResult___fst_exp__h463354; 2'b01, 2'b10, 2'b11: - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 = - _theResult___exp__h463869; + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111 = + _theResult___exp__h463870; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 or - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 or + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110 or + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 or - _theResult___fst_exp__h463353) + _theResult___fst_exp__h463354) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h463947 = - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110; + _theResult___fst_exp__h463948 = + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q110; 3'd1: - _theResult___fst_exp__h463947 = - CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111; + _theResult___fst_exp__h463948 = + CASE_guard55126_0b0_theResult___fst_exp63354_0_ETC__q111; 3'd2: - _theResult___fst_exp__h463947 = + _theResult___fst_exp__h463948 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641; 3'd3: - _theResult___fst_exp__h463947 = + _theResult___fst_exp__h463948 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643; - 3'd4: _theResult___fst_exp__h463947 = _theResult___fst_exp__h463353; - default: _theResult___fst_exp__h463947 = 8'd0; + 3'd4: _theResult___fst_exp__h463948 = _theResult___fst_exp__h463354; + default: _theResult___fst_exp__h463948 = 8'd0; endcase end - always@(guard__h463961 or - _theResult___fst_exp__h472038 or - out_exp__h472508 or _theResult___exp__h472505) + always@(guard__h463962 or + _theResult___fst_exp__h472039 or + out_exp__h472509 or _theResult___exp__h472506) begin - case (guard__h463961) + case (guard__h463962) 2'b0, 2'b01: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 = - _theResult___fst_exp__h472038; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 = + _theResult___fst_exp__h472039; 2'b10: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 = - out_exp__h472508; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 = + out_exp__h472509; 2'b11: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 = - _theResult___exp__h472505; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 = + _theResult___exp__h472506; endcase end - always@(guard__h463961 or - _theResult___fst_exp__h472038 or _theResult___exp__h472505) + always@(guard__h463962 or + _theResult___fst_exp__h472039 or _theResult___exp__h472506) begin - case (guard__h463961) + case (guard__h463962) 2'b0: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 = - _theResult___fst_exp__h472038; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116 = + _theResult___fst_exp__h472039; 2'b01, 2'b10, 2'b11: - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 = - _theResult___exp__h472505; + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116 = + _theResult___exp__h472506; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 or - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 or + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115 or + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 or - _theResult___fst_exp__h472038) + _theResult___fst_exp__h472039) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h472583 = - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115; + _theResult___fst_exp__h472584 = + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q115; 3'd1: - _theResult___fst_exp__h472583 = - CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116; + _theResult___fst_exp__h472584 = + CASE_guard63962_0b0_theResult___fst_exp72039_0_ETC__q116; 3'd2: - _theResult___fst_exp__h472583 = + _theResult___fst_exp__h472584 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710; 3'd3: - _theResult___fst_exp__h472583 = + _theResult___fst_exp__h472584 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712; - 3'd4: _theResult___fst_exp__h472583 = _theResult___fst_exp__h472038; - default: _theResult___fst_exp__h472583 = 8'd0; + 3'd4: _theResult___fst_exp__h472584 = _theResult___fst_exp__h472039; + default: _theResult___fst_exp__h472584 = 8'd0; endcase end - always@(guard__h446195 or - _theResult___snd__h454194 or - out_sfd__h454689 or _theResult___sfd__h454686) + always@(guard__h446196 or + _theResult___snd__h454195 or + out_sfd__h454690 or _theResult___sfd__h454687) begin - case (guard__h446195) + case (guard__h446196) 2'b0, 2'b01: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 = - _theResult___snd__h454194[56:34]; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 = + _theResult___snd__h454195[56:34]; 2'b10: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 = - out_sfd__h454689; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 = + out_sfd__h454690; 2'b11: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 = - _theResult___sfd__h454686; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 = + _theResult___sfd__h454687; endcase end - always@(guard__h446195 or - _theResult___snd__h454194 or _theResult___sfd__h454686) + always@(guard__h446196 or + _theResult___snd__h454195 or _theResult___sfd__h454687) begin - case (guard__h446195) + case (guard__h446196) 2'b0: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 = - _theResult___snd__h454194[56:34]; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118 = + _theResult___snd__h454195[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 = - _theResult___sfd__h454686; + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118 = + _theResult___sfd__h454687; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 or - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 or + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117 or + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 or - _theResult___snd__h454194) + _theResult___snd__h454195) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h454764 = - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117; + _theResult___fst_sfd__h454765 = + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q117; 3'd1: - _theResult___fst_sfd__h454764 = - CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118; + _theResult___fst_sfd__h454765 = + CASE_guard46196_0b0_theResult___snd54195_BITS__ETC__q118; 3'd2: - _theResult___fst_sfd__h454764 = + _theResult___fst_sfd__h454765 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760; 3'd3: - _theResult___fst_sfd__h454764 = + _theResult___fst_sfd__h454765 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762; - 3'd4: _theResult___fst_sfd__h454764 = _theResult___snd__h454194[56:34]; - default: _theResult___fst_sfd__h454764 = 23'd0; + 3'd4: _theResult___fst_sfd__h454765 = _theResult___snd__h454195[56:34]; + default: _theResult___fst_sfd__h454765 = 23'd0; endcase end - always@(guard__h437488 or - sfdin__h445581 or out_sfd__h446107 or _theResult___sfd__h446104) + always@(guard__h437489 or + sfdin__h445582 or out_sfd__h446108 or _theResult___sfd__h446105) begin - case (guard__h437488) + case (guard__h437489) 2'b0, 2'b01: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 = - sfdin__h445581[56:34]; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 = + sfdin__h445582[56:34]; 2'b10: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 = - out_sfd__h446107; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 = + out_sfd__h446108; 2'b11: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 = - _theResult___sfd__h446104; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 = + _theResult___sfd__h446105; endcase end - always@(guard__h437488 or sfdin__h445581 or _theResult___sfd__h446104) + always@(guard__h437489 or sfdin__h445582 or _theResult___sfd__h446105) begin - case (guard__h437488) + case (guard__h437489) 2'b0: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 = - sfdin__h445581[56:34]; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120 = + sfdin__h445582[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h446104; + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h446105; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 or - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 or + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119 or + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 or - sfdin__h445581) + sfdin__h445582) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h446182 = - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119; + _theResult___fst_sfd__h446183 = + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q119; 3'd1: - _theResult___fst_sfd__h446182 = - CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h446183 = + CASE_guard37489_0b0_sfdin45582_BITS_56_TO_34_0_ETC__q120; 3'd2: - _theResult___fst_sfd__h446182 = + _theResult___fst_sfd__h446183 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741; 3'd3: - _theResult___fst_sfd__h446182 = + _theResult___fst_sfd__h446183 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743; - 3'd4: _theResult___fst_sfd__h446182 = sfdin__h445581[56:34]; - default: _theResult___fst_sfd__h446182 = 23'd0; + 3'd4: _theResult___fst_sfd__h446183 = sfdin__h445582[56:34]; + default: _theResult___fst_sfd__h446183 = 23'd0; endcase end - always@(guard__h455125 or - sfdin__h463347 or out_sfd__h463873 or _theResult___sfd__h463870) + always@(guard__h455126 or + sfdin__h463348 or out_sfd__h463874 or _theResult___sfd__h463871) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 = - sfdin__h463347[56:34]; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 = + sfdin__h463348[56:34]; 2'b10: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 = - out_sfd__h463873; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 = + out_sfd__h463874; 2'b11: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h463870; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h463871; endcase end - always@(guard__h455125 or sfdin__h463347 or _theResult___sfd__h463870) + always@(guard__h455126 or sfdin__h463348 or _theResult___sfd__h463871) begin - case (guard__h455125) + case (guard__h455126) 2'b0: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 = - sfdin__h463347[56:34]; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122 = + sfdin__h463348[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h463870; + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h463871; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 or - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 or + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121 or + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 or - sfdin__h463347) + sfdin__h463348) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h463948 = - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h463949 = + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q121; 3'd1: - _theResult___fst_sfd__h463948 = - CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h463949 = + CASE_guard55126_0b0_sfdin63348_BITS_56_TO_34_0_ETC__q122; 3'd2: - _theResult___fst_sfd__h463948 = + _theResult___fst_sfd__h463949 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787; 3'd3: - _theResult___fst_sfd__h463948 = + _theResult___fst_sfd__h463949 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789; - 3'd4: _theResult___fst_sfd__h463948 = sfdin__h463347[56:34]; - default: _theResult___fst_sfd__h463948 = 23'd0; + 3'd4: _theResult___fst_sfd__h463949 = sfdin__h463348[56:34]; + default: _theResult___fst_sfd__h463949 = 23'd0; endcase end - always@(guard__h437488 or + always@(guard__h463962 or + _theResult___snd__h471985 or + out_sfd__h472510 or _theResult___sfd__h472507) + begin + case (guard__h463962) + 2'b0, 2'b01: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 = + _theResult___snd__h471985[56:34]; + 2'b10: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 = + out_sfd__h472510; + 2'b11: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 = + _theResult___sfd__h472507; + endcase + end + always@(guard__h463962 or + _theResult___snd__h471985 or _theResult___sfd__h472507) + begin + case (guard__h463962) + 2'b0: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124 = + _theResult___snd__h471985[56:34]; + 2'b01, 2'b10, 2'b11: + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124 = + _theResult___sfd__h472507; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123 or + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or + _theResult___snd__h471985) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + _theResult___fst_sfd__h472585 = + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q123; + 3'd1: + _theResult___fst_sfd__h472585 = + CASE_guard63962_0b0_theResult___snd71985_BITS__ETC__q124; + 3'd2: + _theResult___fst_sfd__h472585 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; + 3'd3: + _theResult___fst_sfd__h472585 = + IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; + 3'd4: _theResult___fst_sfd__h472585 = _theResult___snd__h471985[56:34]; + default: _theResult___fst_sfd__h472585 = 23'd0; + endcase + end + always@(guard__h437489 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437488) + case (guard__h437489) 2'b0, 2'b01, 2'b10: - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 = - guard__h437488 == 2'b11 && + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = + guard__h437489 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or - guard__h437488) + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or + guard__h437489) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123; + CASE_guard37489_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - (guard__h437488 == 2'b0) ? + (guard__h437489 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h437488 == 2'b01 || guard__h437488 == 2'b10 || - guard__h437488 == 2'b11) && + (guard__h437489 == 2'b01 || guard__h437489 == 2'b10 || + guard__h437489 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = @@ -35229,124 +35332,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463961 or - _theResult___snd__h471984 or - out_sfd__h472509 or _theResult___sfd__h472506) - begin - case (guard__h463961) - 2'b0, 2'b01: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 = - _theResult___snd__h471984[56:34]; - 2'b10: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 = - out_sfd__h472509; - 2'b11: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 = - _theResult___sfd__h472506; - endcase - end - always@(guard__h463961 or - _theResult___snd__h471984 or _theResult___sfd__h472506) - begin - case (guard__h463961) - 2'b0: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 = - _theResult___snd__h471984[56:34]; - 2'b01, 2'b10, 2'b11: - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 = - _theResult___sfd__h472506; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 or - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___snd__h471984) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - _theResult___fst_sfd__h472584 = - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124; - 3'd1: - _theResult___fst_sfd__h472584 = - CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125; - 3'd2: - _theResult___fst_sfd__h472584 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; - 3'd3: - _theResult___fst_sfd__h472584 = - IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_sfd__h472584 = _theResult___snd__h471984[56:34]; - default: _theResult___fst_sfd__h472584 = 23'd0; - endcase - end - always@(guard__h437488 or + always@(guard__h446196 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437488) + case (guard__h446196) 2'b0, 2'b01, 2'b10: - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 2'd3: - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 = - guard__h437488 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or - guard__h437488) - begin - case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126; - 3'd1: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - (guard__h437488 == 2'b0) ? - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h437488 != 2'b01 && guard__h437488 != 2'b10 && - guard__h437488 != 2'b11 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - 3'd2, 3'd3: - IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != - 3'd4 || - !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; - endcase - end - always@(guard__h446195 or - coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) - begin - case (guard__h446195) - 2'b0, 2'b01, 2'b10: - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 = - guard__h446195 == 2'b11 && + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h446196 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or - guard__h446195) + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h446196) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127; + CASE_guard46196_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - (guard__h446195 == 2'b0) ? + (guard__h446196 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h446195 == 2'b01 || guard__h446195 == 2'b10 || - guard__h446195 == 2'b11) && + (guard__h446196 == 2'b01 || guard__h446196 == 2'b10 || + guard__h446196 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = @@ -35357,34 +35370,72 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h446195 or + always@(guard__h437489 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h446195) + case (guard__h437489) 2'b0, 2'b01, 2'b10: - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = - guard__h446195 != 2'b11 || + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h437489 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or - guard__h446195) + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h437489) + begin + case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + CASE_guard37489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + 3'd1: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + (guard__h437489 == 2'b0) ? + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : + guard__h437489 != 2'b01 && guard__h437489 != 2'b10 && + guard__h437489 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 3'd2, 3'd3: + IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] != + 3'd4 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(guard__h446196 or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) + begin + case (guard__h446196) + 2'b0, 2'b01, 2'b10: + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + 2'd3: + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h446196 != 2'b11 || + !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; + endcase + end + always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or + coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h446196) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + CASE_guard46196_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - (guard__h446195 == 2'b0) ? + (guard__h446196 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h446195 != 2'b01 && guard__h446195 != 2'b10 && - guard__h446195 != 2'b11 || + guard__h446196 != 2'b01 && guard__h446196 != 2'b10 && + guard__h446196 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = @@ -35395,34 +35446,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455125 or + always@(guard__h455126 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01, 2'b10: - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = - guard__h455125 == 2'b11 && + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + guard__h455126 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or - guard__h455125) + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or + guard__h455126) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; + CASE_guard55126_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - (guard__h455125 == 2'b0) ? + (guard__h455126 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h455125 == 2'b01 || guard__h455125 == 2'b10 || - guard__h455125 == 2'b11) && + (guard__h455126 == 2'b01 || guard__h455126 == 2'b10 || + guard__h455126 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = @@ -35433,34 +35484,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455125 or + always@(guard__h455126 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455125) + case (guard__h455126) 2'b0, 2'b01, 2'b10: - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - guard__h455125 != 2'b11 || + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + guard__h455126 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or - guard__h455125) + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or + guard__h455126) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; + CASE_guard55126_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - (guard__h455125 == 2'b0) ? + (guard__h455126 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h455125 != 2'b01 && guard__h455125 != 2'b10 && - guard__h455125 != 2'b11 || + guard__h455126 != 2'b01 && guard__h455126 != 2'b10 && + guard__h455126 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = @@ -35471,34 +35522,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463961 or + always@(guard__h463962 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463961) + case (guard__h463962) 2'b0, 2'b01, 2'b10: - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = - guard__h463961 == 2'b11 && + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + guard__h463962 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or - guard__h463961) + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or + guard__h463962) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; + CASE_guard63962_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - (guard__h463961 == 2'b0) ? + (guard__h463962 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h463961 == 2'b01 || guard__h463961 == 2'b10 || - guard__h463961 == 2'b11) && + (guard__h463962 == 2'b01 || guard__h463962 == 2'b10 || + guard__h463962 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = @@ -35509,34 +35560,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463961 or + always@(guard__h463962 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463961) + case (guard__h463962) 2'b0, 2'b01, 2'b10: - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = - guard__h463961 != 2'b11 || + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + guard__h463962 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or - guard__h463961) + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or + guard__h463962) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; + CASE_guard63962_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - (guard__h463961 == 2'b0) ? + (guard__h463962 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h463961 != 2'b01 && guard__h463961 != 2'b10 && - guard__h463961 != 2'b11 || + guard__h463962 != 2'b01 && guard__h463962 != 2'b10 && + guard__h463962 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = @@ -35593,28 +35644,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h493566 or - _theResult___fst_exp__h501527 or _theResult___exp__h502182) + always@(guard__h493567 or + _theResult___fst_exp__h501528 or _theResult___exp__h502183) begin - case (guard__h493566) + case (guard__h493567) 2'b0: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143 = - _theResult___fst_exp__h501527; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143 = + _theResult___fst_exp__h501528; 2'b01, 2'b10, 2'b11: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143 = - _theResult___exp__h502182; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143 = + _theResult___exp__h502183; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h501527 or + _theResult___fst_exp__h501528 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 or - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143) + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - _theResult___fst_exp__h501527; + _theResult___fst_exp__h501528; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015; @@ -35623,44 +35674,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = 11'd0; endcase end - always@(guard__h493566 or - _theResult___fst_exp__h501527 or - out_exp__h502185 or _theResult___exp__h502182) + always@(guard__h493567 or + _theResult___fst_exp__h501528 or + out_exp__h502186 or _theResult___exp__h502183) begin - case (guard__h493566) + case (guard__h493567) 2'b0, 2'b01: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 = - _theResult___fst_exp__h501527; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 = + _theResult___fst_exp__h501528; 2'b10: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 = - out_exp__h502185; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 = + out_exp__h502186; 2'b11: - CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 = - _theResult___exp__h502182; + CASE_guard93567_0b0_theResult___fst_exp01528_0_ETC__q144 = + _theResult___exp__h502183; endcase end - always@(guard__h502878 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h493567 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h502878) + case (guard__h493567) 2'b0, 2'b01, 2'b10: - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h502878 == 2'b11 && + CASE_guard93567_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h493567 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502878) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493567) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35670,12 +35721,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h502878 == 2'b0) ? + (guard__h493567 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h502878 == 2'b01 || guard__h502878 == 2'b10 || - guard__h502878 == 2'b11) && + (guard__h493567 == 2'b01 || guard__h493567 == 2'b10 || + guard__h493567 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35686,23 +35737,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h493566 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h511948 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h493566) + case (guard__h511948) 2'b0, 2'b01, 2'b10: - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h493566 == 2'b11 && + CASE_guard11948_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h511948 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493566) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511948) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35712,12 +35763,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h493566 == 2'b0) ? + (guard__h511948 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h493566 == 2'b01 || guard__h493566 == 2'b10 || - guard__h493566 == 2'b11) && + (guard__h511948 == 2'b01 || guard__h511948 == 2'b10 || + guard__h511948 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35728,23 +35779,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h511947 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h502879 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h511947) + case (guard__h502879) 2'b0, 2'b01, 2'b10: - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h511947 == 2'b11 && + CASE_guard02879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h502879 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511947) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502879) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35754,12 +35805,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h511947 == 2'b0) ? + (guard__h502879 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h511947 == 2'b01 || guard__h511947 == 2'b10 || - guard__h511947 == 2'b11) && + (guard__h502879 == 2'b01 || guard__h502879 == 2'b10 || + guard__h502879 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35770,28 +35821,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h571723 or - _theResult___fst_exp__h579684 or _theResult___exp__h580339) + always@(guard__h571724 or + _theResult___fst_exp__h579685 or _theResult___exp__h580340) begin - case (guard__h571723) + case (guard__h571724) 2'b0: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160 = - _theResult___fst_exp__h579684; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160 = + _theResult___fst_exp__h579685; 2'b01, 2'b10, 2'b11: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160 = - _theResult___exp__h580339; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160 = + _theResult___exp__h580340; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h579684 or + _theResult___fst_exp__h579685 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 or - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160) + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - _theResult___fst_exp__h579684; + _theResult___fst_exp__h579685; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730; @@ -35800,42 +35851,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = 11'd0; endcase end - always@(guard__h571723 or - _theResult___fst_exp__h579684 or - out_exp__h580342 or _theResult___exp__h580339) + always@(guard__h571724 or + _theResult___fst_exp__h579685 or + out_exp__h580343 or _theResult___exp__h580340) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 = - _theResult___fst_exp__h579684; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 = + _theResult___fst_exp__h579685; 2'b10: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 = - out_exp__h580342; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 = + out_exp__h580343; 2'b11: - CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 = - _theResult___exp__h580339; + CASE_guard71724_0b0_theResult___fst_exp79685_0_ETC__q161 = + _theResult___exp__h580340; endcase end - always@(guard__h571723 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571724 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01, 2'b10: - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h571723 == 2'b11 && + CASE_guard71724_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571724 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571723) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571724) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35844,12 +35895,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h571723 == 2'b0) ? + (guard__h571724 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571723 == 2'b01 || guard__h571723 == 2'b10 || - guard__h571723 == 2'b11) && + (guard__h571724 == 2'b01 || guard__h571724 == 2'b10 || + guard__h571724 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35860,21 +35911,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581035 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01, 2'b10: - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h581035 == 2'b11 && + CASE_guard81036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581036 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581035) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35883,12 +35934,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h581035 == 2'b0) ? + (guard__h581036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581035 == 2'b01 || guard__h581035 == 2'b10 || - guard__h581035 == 2'b11) && + (guard__h581036 == 2'b01 || guard__h581036 == 2'b10 || + guard__h581036 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35899,21 +35950,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590104 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590105 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01, 2'b10: - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h590104 == 2'b11 && + CASE_guard90105_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h590105 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590104) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590105) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35922,12 +35973,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h590104 == 2'b0) ? + (guard__h590105 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h590104 == 2'b01 || guard__h590104 == 2'b10 || - guard__h590104 == 2'b11) && + (guard__h590105 == 2'b01 || guard__h590105 == 2'b10 || + guard__h590105 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35938,21 +35989,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581035 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01, 2'b10: - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h581035 != 2'b11 || + CASE_guard81036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h581036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581035) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35961,12 +36012,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h581035 == 2'b0) ? + (guard__h581036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h581035 != 2'b01 && guard__h581035 != 2'b10 && - guard__h581035 != 2'b11 || + guard__h581036 != 2'b01 && guard__h581036 != 2'b10 && + guard__h581036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35977,21 +36028,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590104 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590105 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01, 2'b10: - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h590104 != 2'b11 || + CASE_guard90105_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h590105 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590104) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590105) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36000,12 +36051,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h590104 == 2'b0) ? + (guard__h590105 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h590104 != 2'b01 && guard__h590104 != 2'b10 && - guard__h590104 != 2'b11 || + guard__h590105 != 2'b01 && guard__h590105 != 2'b10 && + guard__h590105 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36016,21 +36067,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571723 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571724 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01, 2'b10: - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h571723 != 2'b11 || + CASE_guard71724_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h571724 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571723) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571724) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36039,12 +36090,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h571723 == 2'b0) ? + (guard__h571724 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h571723 != 2'b01 && guard__h571723 != 2'b10 && - guard__h571723 != 2'b11 || + guard__h571724 != 2'b01 && guard__h571724 != 2'b10 && + guard__h571724 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36055,28 +36106,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h532419 or - _theResult___fst_exp__h540380 or _theResult___exp__h541035) + always@(guard__h532420 or + _theResult___fst_exp__h540381 or _theResult___exp__h541036) begin - case (guard__h532419) + case (guard__h532420) 2'b0: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183 = - _theResult___fst_exp__h540380; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183 = + _theResult___fst_exp__h540381; 2'b01, 2'b10, 2'b11: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183 = - _theResult___exp__h541035; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183 = + _theResult___exp__h541036; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h540380 or + _theResult___fst_exp__h540381 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 or - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183) + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - _theResult___fst_exp__h540380; + _theResult___fst_exp__h540381; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500; @@ -36085,49 +36136,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = 11'd0; endcase end - always@(guard__h532419 or - _theResult___fst_exp__h540380 or - out_exp__h541038 or _theResult___exp__h541035) + always@(guard__h532420 or + _theResult___fst_exp__h540381 or + out_exp__h541039 or _theResult___exp__h541036) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 = - _theResult___fst_exp__h540380; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 = + _theResult___fst_exp__h540381; 2'b10: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 = - out_exp__h541038; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 = + out_exp__h541039; 2'b11: - CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 = - _theResult___exp__h541035; + CASE_guard32420_0b0_theResult___fst_exp40381_0_ETC__q184 = + _theResult___exp__h541036; endcase end - always@(guard__h541731 or - _theResult___fst_exp__h549957 or _theResult___exp__h550686) + always@(guard__h541732 or + _theResult___fst_exp__h549958 or _theResult___exp__h550687) begin - case (guard__h541731) + case (guard__h541732) 2'b0: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185 = - _theResult___fst_exp__h549957; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185 = + _theResult___fst_exp__h549958; 2'b01, 2'b10, 2'b11: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185 = - _theResult___exp__h550686; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185 = + _theResult___exp__h550687; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h549957 or + _theResult___fst_exp__h549958 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 or - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185) + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - _theResult___fst_exp__h549957; + _theResult___fst_exp__h549958; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538; @@ -36136,49 +36187,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = 11'd0; endcase end - always@(guard__h541731 or - _theResult___fst_exp__h549957 or - out_exp__h550689 or _theResult___exp__h550686) + always@(guard__h541732 or + _theResult___fst_exp__h549958 or + out_exp__h550690 or _theResult___exp__h550687) begin - case (guard__h541731) + case (guard__h541732) 2'b0, 2'b01: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 = - _theResult___fst_exp__h549957; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 = + _theResult___fst_exp__h549958; 2'b10: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 = - out_exp__h550689; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 = + out_exp__h550690; 2'b11: - CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 = - _theResult___exp__h550686; + CASE_guard41732_0b0_theResult___fst_exp49958_0_ETC__q186 = + _theResult___exp__h550687; endcase end - always@(guard__h550800 or - _theResult___fst_exp__h558790 or _theResult___exp__h559470) + always@(guard__h550801 or + _theResult___fst_exp__h558791 or _theResult___exp__h559471) begin - case (guard__h550800) + case (guard__h550801) 2'b0: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187 = - _theResult___fst_exp__h558790; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187 = + _theResult___fst_exp__h558791; 2'b01, 2'b10, 2'b11: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187 = - _theResult___exp__h559470; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187 = + _theResult___exp__h559471; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h558790 or + _theResult___fst_exp__h558791 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187) + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - _theResult___fst_exp__h558790; + _theResult___fst_exp__h558791; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569; @@ -36187,49 +36238,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = 11'd0; endcase end - always@(guard__h550800 or - _theResult___fst_exp__h558790 or - out_exp__h559473 or _theResult___exp__h559470) + always@(guard__h550801 or + _theResult___fst_exp__h558791 or + out_exp__h559474 or _theResult___exp__h559471) begin - case (guard__h550800) + case (guard__h550801) 2'b0, 2'b01: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 = - _theResult___fst_exp__h558790; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 = + _theResult___fst_exp__h558791; 2'b10: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 = - out_exp__h559473; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 = + out_exp__h559474; 2'b11: - CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 = - _theResult___exp__h559470; + CASE_guard50801_0b0_theResult___fst_exp58791_0_ETC__q188 = + _theResult___exp__h559471; endcase end - always@(guard__h581035 or - _theResult___fst_exp__h589261 or _theResult___exp__h589990) + always@(guard__h581036 or + _theResult___fst_exp__h589262 or _theResult___exp__h589991) begin - case (guard__h581035) + case (guard__h581036) 2'b0: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189 = - _theResult___fst_exp__h589261; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189 = + _theResult___fst_exp__h589262; 2'b01, 2'b10, 2'b11: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189 = - _theResult___exp__h589990; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189 = + _theResult___exp__h589991; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h589261 or + _theResult___fst_exp__h589262 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189) + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - _theResult___fst_exp__h589261; + _theResult___fst_exp__h589262; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; @@ -36238,49 +36289,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = 11'd0; endcase end - always@(guard__h581035 or - _theResult___fst_exp__h589261 or - out_exp__h589993 or _theResult___exp__h589990) + always@(guard__h581036 or + _theResult___fst_exp__h589262 or + out_exp__h589994 or _theResult___exp__h589991) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 = - _theResult___fst_exp__h589261; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 = + _theResult___fst_exp__h589262; 2'b10: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 = - out_exp__h589993; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 = + out_exp__h589994; 2'b11: - CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 = - _theResult___exp__h589990; + CASE_guard81036_0b0_theResult___fst_exp89262_0_ETC__q190 = + _theResult___exp__h589991; endcase end - always@(guard__h590104 or - _theResult___fst_exp__h598094 or _theResult___exp__h598774) + always@(guard__h590105 or + _theResult___fst_exp__h598095 or _theResult___exp__h598775) begin - case (guard__h590104) + case (guard__h590105) 2'b0: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191 = - _theResult___fst_exp__h598094; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191 = + _theResult___fst_exp__h598095; 2'b01, 2'b10, 2'b11: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191 = - _theResult___exp__h598774; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191 = + _theResult___exp__h598775; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h598094 or + _theResult___fst_exp__h598095 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191) + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - _theResult___fst_exp__h598094; + _theResult___fst_exp__h598095; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799; @@ -36289,44 +36340,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase end - always@(guard__h590104 or - _theResult___fst_exp__h598094 or - out_exp__h598777 or _theResult___exp__h598774) + always@(guard__h590105 or + _theResult___fst_exp__h598095 or + out_exp__h598778 or _theResult___exp__h598775) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 = - _theResult___fst_exp__h598094; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 = + _theResult___fst_exp__h598095; 2'b10: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 = - out_exp__h598777; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 = + out_exp__h598778; 2'b11: - CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 = - _theResult___exp__h598774; + CASE_guard90105_0b0_theResult___fst_exp98095_0_ETC__q192 = + _theResult___exp__h598775; endcase end - always@(guard__h532419 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532420 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01, 2'b10: - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h532419 == 2'b11 && + CASE_guard32420_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h532420 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532419) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532420) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36336,12 +36387,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h532419 == 2'b0) ? + (guard__h532420 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532419 == 2'b01 || guard__h532419 == 2'b10 || - guard__h532419 == 2'b11) && + (guard__h532420 == 2'b01 || guard__h532420 == 2'b10 || + guard__h532420 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36352,23 +36403,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550800 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541732 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550800) + case (guard__h541732) 2'b0, 2'b01, 2'b10: - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h550800 == 2'b11 && + CASE_guard41732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h541732 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550800) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541732) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36378,12 +36429,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h550800 == 2'b0) ? + (guard__h541732 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h550800 == 2'b01 || guard__h550800 == 2'b10 || - guard__h550800 == 2'b11) && + (guard__h541732 == 2'b01 || guard__h541732 == 2'b10 || + guard__h541732 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36394,23 +36445,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541731 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550801 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541731) + case (guard__h550801) 2'b0, 2'b01, 2'b10: - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h541731 == 2'b11 && + CASE_guard50801_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h550801 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541731) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550801) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36420,12 +36471,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h541731 == 2'b0) ? + (guard__h550801 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h541731 == 2'b01 || guard__h541731 == 2'b10 || - guard__h541731 == 2'b11) && + (guard__h550801 == 2'b01 || guard__h550801 == 2'b10 || + guard__h550801 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36436,23 +36487,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541731 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541732 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541731) + case (guard__h541732) 2'b0, 2'b01, 2'b10: - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h541731 != 2'b11 || + CASE_guard41732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h541732 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541731) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541732) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36462,12 +36513,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h541731 == 2'b0) ? + (guard__h541732 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h541731 != 2'b01 && guard__h541731 != 2'b10 && - guard__h541731 != 2'b11 || + guard__h541732 != 2'b01 && guard__h541732 != 2'b10 && + guard__h541732 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36478,23 +36529,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550800 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550801 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550800) + case (guard__h550801) 2'b0, 2'b01, 2'b10: - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h550800 != 2'b11 || + CASE_guard50801_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h550801 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550800) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550801) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36504,12 +36555,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h550800 == 2'b0) ? + (guard__h550801 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h550800 != 2'b01 && guard__h550800 != 2'b10 && - guard__h550800 != 2'b11 || + guard__h550801 != 2'b01 && guard__h550801 != 2'b10 && + guard__h550801 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36520,23 +36571,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532419 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532420 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01, 2'b10: - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h532419 != 2'b11 || + CASE_guard32420_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532420 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532419) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532420) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36546,12 +36597,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h532419 == 2'b0) ? + (guard__h532420 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532419 != 2'b01 && guard__h532419 != 2'b10 && - guard__h532419 != 2'b11 || + guard__h532420 != 2'b01 && guard__h532420 != 2'b10 && + guard__h532420 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36562,28 +36613,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532419 or - _theResult___snd__h540331 or _theResult___sfd__h541036) + always@(guard__h532420 or + _theResult___snd__h540332 or _theResult___sfd__h541037) begin - case (guard__h532419) + case (guard__h532420) 2'b0: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205 = - _theResult___snd__h540331[56:5]; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205 = + _theResult___snd__h540332[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205 = - _theResult___sfd__h541036; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205 = + _theResult___sfd__h541037; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h540331 or + _theResult___snd__h540332 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 or - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205) + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - _theResult___snd__h540331[56:5]; + _theResult___snd__h540332[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595; @@ -36592,48 +36643,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = 52'd0; endcase end - always@(guard__h532419 or - _theResult___snd__h540331 or - out_sfd__h541039 or _theResult___sfd__h541036) + always@(guard__h532420 or + _theResult___snd__h540332 or + out_sfd__h541040 or _theResult___sfd__h541037) begin - case (guard__h532419) + case (guard__h532420) 2'b0, 2'b01: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 = - _theResult___snd__h540331[56:5]; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 = + _theResult___snd__h540332[56:5]; 2'b10: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 = - out_sfd__h541039; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 = + out_sfd__h541040; 2'b11: - CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 = - _theResult___sfd__h541036; + CASE_guard32420_0b0_theResult___snd40332_BITS__ETC__q206 = + _theResult___sfd__h541037; endcase end - always@(guard__h541731 or sfdin__h549951 or _theResult___sfd__h550687) + always@(guard__h541732 or sfdin__h549952 or _theResult___sfd__h550688) begin - case (guard__h541731) + case (guard__h541732) 2'b0: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h549951[56:5]; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h549952[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h550687; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h550688; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h549951 or + sfdin__h549952 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207) + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - sfdin__h549951[56:5]; + sfdin__h549952[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621; @@ -36642,48 +36693,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase end - always@(guard__h541731 or - sfdin__h549951 or out_sfd__h550690 or _theResult___sfd__h550687) + always@(guard__h541732 or + sfdin__h549952 or out_sfd__h550691 or _theResult___sfd__h550688) begin - case (guard__h541731) + case (guard__h541732) 2'b0, 2'b01: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h549951[56:5]; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h549952[56:5]; 2'b10: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h550690; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h550691; 2'b11: - CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h550687; + CASE_guard41732_0b0_sfdin49952_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h550688; endcase end - always@(guard__h550800 or - _theResult___snd__h558736 or _theResult___sfd__h559471) + always@(guard__h550801 or + _theResult___snd__h558737 or _theResult___sfd__h559472) begin - case (guard__h550800) + case (guard__h550801) 2'b0: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209 = - _theResult___snd__h558736[56:5]; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209 = + _theResult___snd__h558737[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209 = - _theResult___sfd__h559471; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209 = + _theResult___sfd__h559472; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558736 or + _theResult___snd__h558737 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209) + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558736[56:5]; + _theResult___snd__h558737[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; @@ -36692,49 +36743,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = 52'd0; endcase end - always@(guard__h550800 or - _theResult___snd__h558736 or - out_sfd__h559474 or _theResult___sfd__h559471) + always@(guard__h550801 or + _theResult___snd__h558737 or + out_sfd__h559475 or _theResult___sfd__h559472) begin - case (guard__h550800) + case (guard__h550801) 2'b0, 2'b01: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 = - _theResult___snd__h558736[56:5]; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 = + _theResult___snd__h558737[56:5]; 2'b10: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 = - out_sfd__h559474; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 = + out_sfd__h559475; 2'b11: - CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 = - _theResult___sfd__h559471; + CASE_guard50801_0b0_theResult___snd58737_BITS__ETC__q210 = + _theResult___sfd__h559472; endcase end - always@(guard__h502878 or - _theResult___fst_exp__h511104 or _theResult___exp__h511833) + always@(guard__h502879 or + _theResult___fst_exp__h511105 or _theResult___exp__h511834) begin - case (guard__h502878) + case (guard__h502879) 2'b0: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211 = - _theResult___fst_exp__h511104; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211 = + _theResult___fst_exp__h511105; 2'b01, 2'b10, 2'b11: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211 = - _theResult___exp__h511833; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211 = + _theResult___exp__h511834; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h511104 or + _theResult___fst_exp__h511105 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 or - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211) + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - _theResult___fst_exp__h511104; + _theResult___fst_exp__h511105; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058; @@ -36743,49 +36794,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = 11'd0; endcase end - always@(guard__h502878 or - _theResult___fst_exp__h511104 or - out_exp__h511836 or _theResult___exp__h511833) + always@(guard__h502879 or + _theResult___fst_exp__h511105 or + out_exp__h511837 or _theResult___exp__h511834) begin - case (guard__h502878) + case (guard__h502879) 2'b0, 2'b01: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 = - _theResult___fst_exp__h511104; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 = + _theResult___fst_exp__h511105; 2'b10: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 = - out_exp__h511836; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 = + out_exp__h511837; 2'b11: - CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 = - _theResult___exp__h511833; + CASE_guard02879_0b0_theResult___fst_exp11105_0_ETC__q212 = + _theResult___exp__h511834; endcase end - always@(guard__h511947 or - _theResult___fst_exp__h519937 or _theResult___exp__h520617) + always@(guard__h511948 or + _theResult___fst_exp__h519938 or _theResult___exp__h520618) begin - case (guard__h511947) + case (guard__h511948) 2'b0: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213 = - _theResult___fst_exp__h519937; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213 = + _theResult___fst_exp__h519938; 2'b01, 2'b10, 2'b11: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213 = - _theResult___exp__h520617; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213 = + _theResult___exp__h520618; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h519937 or + _theResult___fst_exp__h519938 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 or - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213) + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - _theResult___fst_exp__h519937; + _theResult___fst_exp__h519938; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089; @@ -36794,49 +36845,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = 11'd0; endcase end - always@(guard__h511947 or - _theResult___fst_exp__h519937 or - out_exp__h520620 or _theResult___exp__h520617) + always@(guard__h511948 or + _theResult___fst_exp__h519938 or + out_exp__h520621 or _theResult___exp__h520618) begin - case (guard__h511947) + case (guard__h511948) 2'b0, 2'b01: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 = - _theResult___fst_exp__h519937; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 = + _theResult___fst_exp__h519938; 2'b10: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 = - out_exp__h520620; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 = + out_exp__h520621; 2'b11: - CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 = - _theResult___exp__h520617; + CASE_guard11948_0b0_theResult___fst_exp19938_0_ETC__q214 = + _theResult___exp__h520618; endcase end - always@(guard__h493566 or - _theResult___snd__h501478 or _theResult___sfd__h502183) + always@(guard__h493567 or + _theResult___snd__h501479 or _theResult___sfd__h502184) begin - case (guard__h493566) + case (guard__h493567) 2'b0: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215 = - _theResult___snd__h501478[56:5]; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215 = + _theResult___snd__h501479[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215 = - _theResult___sfd__h502183; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215 = + _theResult___sfd__h502184; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h501478 or + _theResult___snd__h501479 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215) + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - _theResult___snd__h501478[56:5]; + _theResult___snd__h501479[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115; @@ -36845,48 +36896,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase end - always@(guard__h493566 or - _theResult___snd__h501478 or - out_sfd__h502186 or _theResult___sfd__h502183) + always@(guard__h493567 or + _theResult___snd__h501479 or + out_sfd__h502187 or _theResult___sfd__h502184) begin - case (guard__h493566) + case (guard__h493567) 2'b0, 2'b01: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 = - _theResult___snd__h501478[56:5]; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 = + _theResult___snd__h501479[56:5]; 2'b10: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 = - out_sfd__h502186; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 = + out_sfd__h502187; 2'b11: - CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 = - _theResult___sfd__h502183; + CASE_guard93567_0b0_theResult___snd01479_BITS__ETC__q216 = + _theResult___sfd__h502184; endcase end - always@(guard__h502878 or sfdin__h511098 or _theResult___sfd__h511834) + always@(guard__h502879 or sfdin__h511099 or _theResult___sfd__h511835) begin - case (guard__h502878) + case (guard__h502879) 2'b0: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h511098[56:5]; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h511099[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h511834; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h511835; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511098 or + sfdin__h511099 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217) + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511098[56:5]; + sfdin__h511099[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; @@ -36895,48 +36946,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = 52'd0; endcase end - always@(guard__h502878 or - sfdin__h511098 or out_sfd__h511837 or _theResult___sfd__h511834) + always@(guard__h502879 or + sfdin__h511099 or out_sfd__h511838 or _theResult___sfd__h511835) begin - case (guard__h502878) + case (guard__h502879) 2'b0, 2'b01: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h511098[56:5]; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h511099[56:5]; 2'b10: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h511837; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h511838; 2'b11: - CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h511834; + CASE_guard02879_0b0_sfdin11099_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h511835; endcase end - always@(guard__h511947 or - _theResult___snd__h519883 or _theResult___sfd__h520618) + always@(guard__h511948 or + _theResult___snd__h519884 or _theResult___sfd__h520619) begin - case (guard__h511947) + case (guard__h511948) 2'b0: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219 = - _theResult___snd__h519883[56:5]; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219 = + _theResult___snd__h519884[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219 = - _theResult___sfd__h520618; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219 = + _theResult___sfd__h520619; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h519883 or + _theResult___snd__h519884 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219) + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - _theResult___snd__h519883[56:5]; + _theResult___snd__h519884[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161; @@ -36945,49 +36996,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase end - always@(guard__h511947 or - _theResult___snd__h519883 or - out_sfd__h520621 or _theResult___sfd__h520618) + always@(guard__h511948 or + _theResult___snd__h519884 or + out_sfd__h520622 or _theResult___sfd__h520619) begin - case (guard__h511947) + case (guard__h511948) 2'b0, 2'b01: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 = - _theResult___snd__h519883[56:5]; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 = + _theResult___snd__h519884[56:5]; 2'b10: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 = - out_sfd__h520621; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 = + out_sfd__h520622; 2'b11: - CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 = - _theResult___sfd__h520618; + CASE_guard11948_0b0_theResult___snd19884_BITS__ETC__q220 = + _theResult___sfd__h520619; endcase end - always@(guard__h571723 or - _theResult___snd__h579635 or _theResult___sfd__h580340) + always@(guard__h571724 or + _theResult___snd__h579636 or _theResult___sfd__h580341) begin - case (guard__h571723) + case (guard__h571724) 2'b0: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221 = - _theResult___snd__h579635[56:5]; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221 = + _theResult___snd__h579636[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221 = - _theResult___sfd__h580340; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221 = + _theResult___sfd__h580341; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h579635 or + _theResult___snd__h579636 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 or - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221) + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - _theResult___snd__h579635[56:5]; + _theResult___snd__h579636[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825; @@ -36996,48 +37047,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = 52'd0; endcase end - always@(guard__h571723 or - _theResult___snd__h579635 or - out_sfd__h580343 or _theResult___sfd__h580340) + always@(guard__h571724 or + _theResult___snd__h579636 or + out_sfd__h580344 or _theResult___sfd__h580341) begin - case (guard__h571723) + case (guard__h571724) 2'b0, 2'b01: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 = - _theResult___snd__h579635[56:5]; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 = + _theResult___snd__h579636[56:5]; 2'b10: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 = - out_sfd__h580343; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 = + out_sfd__h580344; 2'b11: - CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 = - _theResult___sfd__h580340; + CASE_guard71724_0b0_theResult___snd79636_BITS__ETC__q222 = + _theResult___sfd__h580341; endcase end - always@(guard__h581035 or sfdin__h589255 or _theResult___sfd__h589991) + always@(guard__h581036 or sfdin__h589256 or _theResult___sfd__h589992) begin - case (guard__h581035) + case (guard__h581036) 2'b0: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h589255[56:5]; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h589256[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h589991; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h589992; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h589255 or + sfdin__h589256 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 or - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223) + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - sfdin__h589255[56:5]; + sfdin__h589256[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851; @@ -37046,32 +37097,30 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = 52'd0; endcase end - always@(guard__h581035 or - sfdin__h589255 or out_sfd__h589994 or _theResult___sfd__h589991) + always@(guard__h581036 or + sfdin__h589256 or out_sfd__h589995 or _theResult___sfd__h589992) begin - case (guard__h581035) + case (guard__h581036) 2'b0, 2'b01: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h589255[56:5]; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h589256[56:5]; 2'b10: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h589994; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h589995; 2'b11: - CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h589991; + CASE_guard81036_0b0_sfdin89256_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h589992; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37079,8 +37128,7 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888; endcase @@ -37088,9 +37136,7 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37098,34 +37144,33 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852; endcase end - always@(guard__h590104 or - _theResult___snd__h598040 or _theResult___sfd__h598775) + always@(guard__h590105 or + _theResult___snd__h598041 or _theResult___sfd__h598776) begin - case (guard__h590104) + case (guard__h590105) 2'b0: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225 = - _theResult___snd__h598040[56:5]; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225 = + _theResult___snd__h598041[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225 = - _theResult___sfd__h598775; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225 = + _theResult___sfd__h598776; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h598040 or + _theResult___snd__h598041 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 or - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225) + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - _theResult___snd__h598040[56:5]; + _theResult___snd__h598041[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870; @@ -37134,33 +37179,31 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = 52'd0; endcase end - always@(guard__h590104 or - _theResult___snd__h598040 or - out_sfd__h598778 or _theResult___sfd__h598775) + always@(guard__h590105 or + _theResult___snd__h598041 or + out_sfd__h598779 or _theResult___sfd__h598776) begin - case (guard__h590104) + case (guard__h590105) 2'b0, 2'b01: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 = - _theResult___snd__h598040[56:5]; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 = + _theResult___snd__h598041[56:5]; 2'b10: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 = - out_sfd__h598778; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 = + out_sfd__h598779; 2'b11: - CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 = - _theResult___sfd__h598775; + CASE_guard90105_0b0_theResult___snd98041_BITS__ETC__q226 = + _theResult___sfd__h598776; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37168,8 +37211,7 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936; endcase @@ -37177,9 +37219,7 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37187,8 +37227,7 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978; endcase @@ -37196,9 +37235,7 @@ module mkCore(CLK, always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 or NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 or - f1_exp__h482139 or - f1_sfd__h482140 or - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992) + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) 5'd0, 5'd1, 5'd2, 5'd3: @@ -37206,116 +37243,35 @@ module mkCore(CLK, NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006; 5'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 = - (f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) && - NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992; + NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 = coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020; endcase end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[399:397]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 = - coreFix_aluExe_0_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 = 3'd7; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first or - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227) - begin - case (coreFix_aluExe_0_regToExeQ$first[416:414]) - 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - coreFix_aluExe_0_regToExeQ$first[416:396]; - 3'd4: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - { coreFix_aluExe_0_regToExeQ$first[416:414], - 9'h0AA, - coreFix_aluExe_0_regToExeQ$first[404:400], - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227, - coreFix_aluExe_0_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 = - { 3'd5, 18'h2AAAA }; - endcase - end - always@(coreFix_aluExe_0_regToExeQ$first) - begin - case (coreFix_aluExe_0_regToExeQ$first[394:383]) - 12'd1971, - 12'd1970, - 12'd1969, - 12'd1968, - 12'd1955, - 12'd1954, - 12'd1953, - 12'd1952, - 12'd3860, - 12'd3859, - 12'd3858, - 12'd3857, - 12'd2818, - 12'd2816, - 12'd836, - 12'd835, - 12'd834, - 12'd833, - 12'd832, - 12'd774, - 12'd773, - 12'd772, - 12'd771, - 12'd770, - 12'd769, - 12'd768, - 12'd384, - 12'd324, - 12'd323, - 12'd322, - 12'd321, - 12'd320, - 12'd262, - 12'd261, - 12'd260, - 12'd256, - 12'd2049, - 12'd2048, - 12'd3074, - 12'd3073, - 12'd3072, - 12'd3, - 12'd2, - 12'd1: - CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 = - coreFix_aluExe_0_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 = - 12'd2303; - endcase - end always@(coreFix_aluExe_1_regToExeQ$first) begin case (coreFix_aluExe_1_regToExeQ$first[399:397]) 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = coreFix_aluExe_1_regToExeQ$first[399:397]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 = 3'd7; + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = 3'd7; endcase end always@(coreFix_aluExe_1_regToExeQ$first or - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230) + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227) begin case (coreFix_aluExe_1_regToExeQ$first[416:414]) 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = coreFix_aluExe_1_regToExeQ$first[416:396]; 3'd4: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = { coreFix_aluExe_1_regToExeQ$first[416:414], 9'h0AA, coreFix_aluExe_1_regToExeQ$first[404:400], - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230, + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227, coreFix_aluExe_1_regToExeQ$first[396] }; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 = { 3'd5, 18'h2AAAA }; endcase end @@ -37366,9 +37322,89 @@ module mkCore(CLK, 12'd3, 12'd2, 12'd1: - CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 = + CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = coreFix_aluExe_1_regToExeQ$first[394:383]; - default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 = + default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 = + 12'd2303; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[399:397]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = + coreFix_aluExe_0_regToExeQ$first[399:397]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = 3'd7; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first or + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230) + begin + case (coreFix_aluExe_0_regToExeQ$first[416:414]) + 3'd3, 3'd2, 3'd1, 3'd0: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + coreFix_aluExe_0_regToExeQ$first[416:396]; + 3'd4: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + { coreFix_aluExe_0_regToExeQ$first[416:414], + 9'h0AA, + coreFix_aluExe_0_regToExeQ$first[404:400], + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, + coreFix_aluExe_0_regToExeQ$first[396] }; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 = + { 3'd5, 18'h2AAAA }; + endcase + end + always@(coreFix_aluExe_0_regToExeQ$first) + begin + case (coreFix_aluExe_0_regToExeQ$first[394:383]) + 12'd1971, + 12'd1970, + 12'd1969, + 12'd1968, + 12'd1955, + 12'd1954, + 12'd1953, + 12'd1952, + 12'd3860, + 12'd3859, + 12'd3858, + 12'd3857, + 12'd2818, + 12'd2816, + 12'd836, + 12'd835, + 12'd834, + 12'd833, + 12'd832, + 12'd774, + 12'd773, + 12'd772, + 12'd771, + 12'd770, + 12'd769, + 12'd768, + 12'd384, + 12'd324, + 12'd323, + 12'd322, + 12'd321, + 12'd320, + 12'd262, + 12'd261, + 12'd260, + 12'd256, + 12'd2049, + 12'd2048, + 12'd3074, + 12'd3073, + 12'd3072, + 12'd3, + 12'd2, + 12'd1: + CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = + coreFix_aluExe_0_regToExeQ$first[394:383]; + default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 = 12'd2303; endcase end @@ -37481,10 +37517,10 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h669623 or + always@(k__h669625 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669623) + case (k__h669625) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 = coreFix_aluExe_0_rsAlu$canEnq; @@ -37523,10 +37559,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(k__h669623 or + always@(k__h669625 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669623) + case (k__h669625) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -37672,14 +37708,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h685368 or + always@(idx__h685370 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685368) + case (idx__h685370) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 = fetchStage$pipelines_0_canDeq && @@ -37800,29 +37836,18 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738; endcase end - always@(k__h669623 or + always@(k__h669625 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h669623) + case (k__h669625) 1'd0: - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end - always@(fetchStage$pipelines_0_first or - coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) - begin - case (fetchStage$pipelines_0_first[191:189]) - 3'd0, 3'd2: - CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqLd; - default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = - coreFix_memExe_lsq$RDY_enqSt; - endcase - end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or @@ -37842,10 +37867,21 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519); endcase end + always@(fetchStage$pipelines_0_first or + coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd) + begin + case (fetchStage$pipelines_0_first[191:189]) + 3'd0, 3'd2: + CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqLd; + default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 = + coreFix_memExe_lsq$RDY_enqSt; + endcase + end always@(fetchStage$pipelines_0_first or coreFix_memExe_rsMem$canEnq or IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or - regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941 or + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941 or SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 or regRenamingTable$RDY_rename_0_getRename or _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 or @@ -37867,7 +37903,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[194:192] != 3'd2 || !coreFix_memExe_rsMem$canEnq || IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 || - regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941; + regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941; endcase end always@(fetchStage$pipelines_0_first or @@ -37911,14 +37947,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(idx__h685368 or + always@(idx__h685370 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685368) + case (idx__h685370) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 = (!fetchStage$pipelines_0_canDeq || @@ -38122,138 +38158,138 @@ module mkCore(CLK, begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = - csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + !csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = - csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 = - csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + !csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 = + !csrf_rg_dcsr[12]; endcase end always@(csrf_prv_reg or csrf_rg_dcsr) begin case (csrf_prv_reg) 2'd1: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = - !csrf_rg_dcsr[13]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + csrf_rg_dcsr[13]; 2'd3: - CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = - !csrf_rg_dcsr[15]; - default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 = - !csrf_rg_dcsr[12]; + CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + csrf_rg_dcsr[15]; + default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 = + csrf_rg_dcsr[12]; endcase end always@(rob$deqPort_0_deq_data) begin case (rob$deqPort_0_deq_data[180:169]) 12'd1: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd0; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd0; 12'd2: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd1; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd1; 12'd3: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd2; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd2; 12'd256: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd8; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd8; 12'd260: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd9; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd9; 12'd261: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd10; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd10; 12'd262: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd11; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd11; 12'd320: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd12; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd12; 12'd321: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd13; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd13; 12'd322: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd14; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd14; 12'd323: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd15; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd15; 12'd324: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd16; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd16; 12'd384: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd17; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd17; 12'd768: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd18; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd18; 12'd769: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd19; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd19; 12'd770: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd20; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd20; 12'd771: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd21; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd21; 12'd772: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd22; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd22; 12'd773: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd23; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd23; 12'd774: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd24; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd24; 12'd832: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd25; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd25; 12'd833: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd26; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd26; 12'd834: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd27; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd27; 12'd835: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd28; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd28; 12'd836: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd29; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd29; 12'd1952: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd36; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd36; 12'd1953: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd37; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd37; 12'd1954: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd38; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd38; 12'd1955: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd39; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd39; 12'd1968: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd40; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd40; 12'd1969: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd41; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd41; 12'd1970: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd42; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd42; 12'd1971: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd43; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd43; 12'd2048: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd6; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd6; 12'd2049: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd7; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd7; 12'd2816: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd30; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd30; 12'd2818: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd31; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd31; 12'd3072: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd3; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd3; 12'd3073: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd4; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd4; 12'd3074: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd5; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd5; 12'd3857: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd32; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd32; 12'd3858: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd33; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd33; 12'd3859: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd34; + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd34; 12'd3860: - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd35; - default: IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd35; + default: IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 = 6'd44; endcase end - always@(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 or + always@(IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 or rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245) begin - case (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973) + case (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983) 6'd0: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38266,7 +38302,7 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 54'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8], 2'b0, @@ -38274,22 +38310,22 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd10, 6'd23: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38301,9 +38337,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h721446 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h722429 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38311,7 +38347,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21, 6'd22, 6'd29: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38320,12 +38356,12 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h721446 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h722429 = 64'd0; 6'd37: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h721446 = + data_warl_xformed__h722429 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38334,17 +38370,152 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h721446 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h722429 = rob$deqPort_0_deq_data[95:32]; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[180:169]) + 12'd1, + 12'd2, + 12'd3, + 12'd256, + 12'd260, + 12'd261, + 12'd262, + 12'd320, + 12'd321, + 12'd322, + 12'd323, + 12'd324, + 12'd384, + 12'd768, + 12'd769, + 12'd770, + 12'd771, + 12'd772, + 12'd773, + 12'd774, + 12'd832, + 12'd833, + 12'd834, + 12'd835, + 12'd836, + 12'd1952, + 12'd1953, + 12'd1954, + 12'd1955, + 12'd1968, + 12'd1969, + 12'd1970, + 12'd1971, + 12'd2048, + 12'd2049, + 12'd2816, + 12'd2818, + 12'd3072, + 12'd3073, + 12'd3074, + 12'd3857, + 12'd3858, + 12'd3859, + 12'd3860: + CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = + rob$deqPort_0_deq_data[180:169]; + default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 = + 12'd2303; endcase end always@(rob$deqPort_0_deq_data or - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180) + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h722034 = - IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180; - default: x__h722034 = rob$deqPort_0_deq_data[425:362]; + x__h723033 = + IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191; + default: x__h723033 = rob$deqPort_0_deq_data[425:362]; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + rob$deqPort_0_deq_data[165:162]; + default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 = + 4'd15; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[97:96]) + 2'd0, 2'd1: + CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 = + commitStage_f_rob_data$D_OUT[97:96]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 = 2'd2; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[165:162]) + 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 = + commitStage_f_rob_data$D_OUT[165:162]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 = + 4'd15; + endcase + end + always@(commitStage_f_rob_data$D_OUT) + begin + case (commitStage_f_rob_data$D_OUT[165:162]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 = + commitStage_f_rob_data$D_OUT[165:162]; + default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 = + 4'd15; + endcase + end + always@(rob$deqPort_0_deq_data) + begin + case (rob$deqPort_0_deq_data[97:96]) + 2'd0, 2'd1: + CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 = + rob$deqPort_0_deq_data[97:96]; + default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 = 2'd2; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or @@ -38353,10 +38524,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448]; endcase end @@ -38366,10 +38537,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384]; endcase end @@ -38379,10 +38550,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320]; endcase end @@ -38392,10 +38563,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256]; endcase end @@ -38405,10 +38576,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192]; endcase end @@ -38418,13 +38589,31 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = + 3'd0; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -38638,125 +38827,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0]; endcase end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 = - 4'd15; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 = - rob$deqPort_0_deq_data[165:162]; - default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 = - 4'd15; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd4, 3'd3, 3'd2, 3'd1, 3'd0: - CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254 = + CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254 = 3'd7; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[180:169]) - 12'd1, - 12'd2, - 12'd3, - 12'd256, - 12'd260, - 12'd261, - 12'd262, - 12'd320, - 12'd321, - 12'd322, - 12'd323, - 12'd324, - 12'd384, - 12'd768, - 12'd769, - 12'd770, - 12'd771, - 12'd772, - 12'd773, - 12'd774, - 12'd832, - 12'd833, - 12'd834, - 12'd835, - 12'd836, - 12'd1952, - 12'd1953, - 12'd1954, - 12'd1955, - 12'd1968, - 12'd1969, - 12'd1970, - 12'd1971, - 12'd2048, - 12'd2049, - 12'd2816, - 12'd2818, - 12'd3072, - 12'd3073, - 12'd3074, - 12'd3857, - 12'd3858, - 12'd3859, - 12'd3860: - CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 = - rob$deqPort_0_deq_data[180:169]; - default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 = - 12'd2303; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = - 3'd0; - endcase - end - always@(rob$deqPort_0_deq_data) - begin - case (rob$deqPort_0_deq_data[97:96]) - 2'd0, 2'd1: - CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 = - rob$deqPort_0_deq_data[97:96]; - default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 = 2'd2; + default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -38778,25 +38855,16 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884; endcase end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[97:96]) - 2'd0, 2'd1: - CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = - commitStage_f_rob_data$D_OUT[97:96]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = 2'd2; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67]; endcase end @@ -38806,10 +38874,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3]; endcase end @@ -38819,10 +38887,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64]; endcase end @@ -38832,10 +38900,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0]; endcase end @@ -38845,10 +38913,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515]; endcase end @@ -38858,10 +38926,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513]; endcase end @@ -38871,10 +38939,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512]; endcase end @@ -38884,10 +38952,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516]; endcase end @@ -38897,13 +38965,33 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515]; endcase end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) + 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq; + 5'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq; + 5'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = + coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready or coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready or @@ -38926,36 +39014,16 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229]) - 5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq; - 5'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq; - 5'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 = - coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1) begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4]; endcase end @@ -38965,10 +39033,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3]; endcase end @@ -38978,10 +39046,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0]; endcase end @@ -38991,10 +39059,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8]; endcase end @@ -39004,10 +39072,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6]; endcase end @@ -39017,10 +39085,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end @@ -39030,10 +39098,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582]; 1'd1: - CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 = + CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582]; endcase end @@ -39041,35 +39109,13 @@ module mkCore(CLK, begin case (mmio_dataReqQ_data_0[77:76]) 2'd0, 2'd1, 2'd2: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276 = mmio_dataReqQ_data_0[77:72]; 2'd3: - CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274 = + CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276 = { 2'd3, mmio_dataReqQ_data_0[75:72] }; endcase end - always@(coreFix_memExe_lsq$firstLd) - begin - case (coreFix_memExe_lsq$firstLd[6:3]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 = - coreFix_memExe_lsq$firstLd[6:3]; - default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 = - 4'd15; - endcase - end always@(coreFix_memExe_lsq$firstSt) begin case (coreFix_memExe_lsq$firstSt[3:0]) @@ -39086,9 +39132,31 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 = + CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 = coreFix_memExe_lsq$firstSt[3:0]; - default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 = + default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 = + 4'd15; + endcase + end + always@(coreFix_memExe_lsq$firstLd) + begin + case (coreFix_memExe_lsq$firstLd[6:3]) + 4'd0, + 4'd1, + 4'd2, + 4'd3, + 4'd4, + 4'd5, + 4'd6, + 4'd7, + 4'd8, + 4'd9, + 4'd11, + 4'd12, + 4'd13: + CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 = + coreFix_memExe_lsq$firstLd[6:3]; + default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 = 4'd15; endcase end @@ -39139,44 +39207,12 @@ module mkCore(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277 = + CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279 = commitStage_f_rob_data$D_OUT[180:169]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277 = + default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279 = 12'd2303; endcase end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[165:162]) - 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 = - commitStage_f_rob_data$D_OUT[165:162]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 = - 4'd15; - endcase - end - always@(commitStage_f_rob_data$D_OUT) - begin - case (commitStage_f_rob_data$D_OUT[165:162]) - 4'd0, - 4'd1, - 4'd2, - 4'd3, - 4'd4, - 4'd5, - 4'd6, - 4'd7, - 4'd8, - 4'd9, - 4'd11, - 4'd12, - 4'd13: - CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 = - commitStage_f_rob_data$D_OUT[165:162]; - default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 = - 4'd15; - endcase - end always@(mmioToPlatform_pRq_enq_x) begin case (mmioToPlatform_pRq_enq_x[37:36]) @@ -39679,6 +39715,7 @@ module mkCore(CLK, commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY 166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY 1'd1; + commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY 64'd0; commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0; commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0; coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -39974,6 +40011,9 @@ module mkCore(CLK, if (commitStage_rg_just_after_reset$EN) commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY commitStage_rg_just_after_reset$D_IN; + if (commitStage_rg_old_mip_csr_val$EN) + commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY + commitStage_rg_old_mip_csr_val$D_IN; if (commitStage_rg_run_state$EN) commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY commitStage_rg_run_state$D_IN; @@ -40604,6 +40644,7 @@ module mkCore(CLK, begin commitStage_commitTrap = 166'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; commitStage_rg_just_after_reset = 1'h0; + commitStage_rg_old_mip_csr_val = 64'hAAAAAAAAAAAAAAAA; commitStage_rg_run_state = 1'h0; commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA; coreFix_doStatsReg = 1'h0; @@ -41100,7 +41141,7 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && rob$deqPort_0_deq_data[329:325] == 5'd13 && - IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == 6'd6) + IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd6) $display("[Terminate CSR] being written (val = %x), ", "send terminate signal to host", rob$deqPort_0_deq_data[95:32]); @@ -41212,7 +41253,7 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] != 5'd19 && rob$deqPort_1_deq_data[329:325] != 5'd20) $write("instret:%0d PC:0x%0h instr:0x%08h", - commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438, + commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15450, rob$deqPort_1_deq_data[425:362], rob$deqPort_1_deq_data[361:330], " iType:"); @@ -41371,7 +41412,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h603882 == 2'd0) + v__h603883 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index 55f3e6a..ea0a6ee 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -1247,7 +1247,7 @@ module mkCoreW(RST_N_dm_power_on_reset, plic$v_targets_1_m_eip; // ports of submodule proc - wire [784 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get; + wire [861 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get; wire [76 : 0] proc$hart0_csr_mem_server_request_put; wire [69 : 0] proc$hart0_fpr_mem_server_request_put, proc$hart0_gpr_mem_server_request_put; @@ -1424,7 +1424,7 @@ module mkCoreW(RST_N_dm_power_on_reset, tv_encode$RDY_v_cpu_in_1_put; // ports of submodule v_td2_to_td_0 - wire [784 : 0] v_td2_to_td_0$in_put; + wire [861 : 0] v_td2_to_td_0$in_put; wire [490 : 0] v_td2_to_td_0$out_get; wire v_td2_to_td_0$EN_in_put, v_td2_to_td_0$EN_out_get, @@ -1432,7 +1432,7 @@ module mkCoreW(RST_N_dm_power_on_reset, v_td2_to_td_0$RDY_out_get; // ports of submodule v_td2_to_td_1 - wire [784 : 0] v_td2_to_td_1$in_put; + wire [861 : 0] v_td2_to_td_1$in_put; wire [490 : 0] v_td2_to_td_1$out_get; wire v_td2_to_td_1$EN_in_put, v_td2_to_td_1$EN_out_get, @@ -1611,10 +1611,10 @@ module mkCoreW(RST_N_dm_power_on_reset, // synopsys translate_off reg [31 : 0] v__h5047; reg [31 : 0] v__h5190; - reg [31 : 0] v__h15736; + reg [31 : 0] v__h15930; reg [31 : 0] v__h5041; reg [31 : 0] v__h5184; - reg [31 : 0] v__h15730; + reg [31 : 0] v__h15924; // synopsys translate_on // remaining internal signals @@ -3422,7 +3422,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule v_td2_to_td_0 assign v_td2_to_td_0$in_put = - { proc$v_to_TV_0_get[784:619], + { proc$v_to_TV_0_get[861:797], + proc$v_to_TV_0_get[797] ? + proc$v_to_TV_0_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + proc$v_to_TV_0_get[720:619], proc$v_to_TV_0_get[619] ? proc$v_to_TV_0_get[618:613] : 6'h2A, proc$v_to_TV_0_get[612:476], proc$v_to_TV_0_get[476] ? @@ -3443,7 +3447,11 @@ module mkCoreW(RST_N_dm_power_on_reset, // submodule v_td2_to_td_1 assign v_td2_to_td_1$in_put = - { proc$v_to_TV_1_get[784:619], + { proc$v_to_TV_1_get[861:797], + proc$v_to_TV_1_get[797] ? + proc$v_to_TV_1_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + proc$v_to_TV_1_get[720:619], proc$v_to_TV_1_get[619] ? proc$v_to_TV_1_get[618:613] : 6'h2A, proc$v_to_TV_1_get[612:476], proc$v_to_TV_1_get[476] ? @@ -3726,15 +3734,15 @@ module mkCoreW(RST_N_dm_power_on_reset, if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) begin - v__h15736 = $stime; + v__h15930 = $stime; #0; end - v__h15730 = v__h15736 / 32'd10; + v__h15924 = v__h15930 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (hart0_reset$RST_OUT != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)", - v__h15730, + v__h15924, 64'h0000000070000000, start_tohost_addr, start_fromhost_addr); diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v index feb4788..8a1a6a7 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFabric_2x3.v @@ -3328,17 +3328,17 @@ module mkFabric_2x3(CLK, 8'd0 : x__h12338 ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 = - { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], - IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, - fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_0_67_EQ_fabric_v_f_ETC___d396, fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ; - assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 = { fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3], IF_fabric_v_rg_r_beat_count_1_07_EQ_fabric_v_f_ETC___d435, fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ; + assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 = + { fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3], + IF_fabric_v_rg_r_beat_count_2_46_EQ_fabric_v_f_ETC___d474, + fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ; assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 = { fabric_v_f_rd_err_info_0$D_OUT[3:0], 66'd3, @@ -3749,23 +3749,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_0_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: - fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master: fabric_xactors_from_masters_0_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1: + fabric_xactors_from_masters_0_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2: fabric_xactors_from_masters_0_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master: @@ -3776,9 +3776,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_0_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ; assign fabric_xactors_from_masters_0_f_rd_data$DEQ = v_from_masters_0_rready && @@ -3877,23 +3877,23 @@ module mkFabric_2x3(CLK, assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ; // submodule fabric_xactors_from_masters_1_f_rd_data - always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or + always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: - fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3: fabric_xactors_from_masters_1_f_rd_data$D_IN = - MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1; WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4: + fabric_xactors_from_masters_1_f_rd_data$D_IN = + MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2; + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5: fabric_xactors_from_masters_1_f_rd_data$D_IN = MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3; WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1: @@ -3904,9 +3904,9 @@ module mkFabric_2x3(CLK, endcase end assign fabric_xactors_from_masters_1_f_rd_data$ENQ = - WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 || WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 || + WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 || WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ; assign fabric_xactors_from_masters_1_f_rd_data$DEQ = v_from_masters_1_rready && diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 5434ee4..4b6dec6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -88,9 +88,9 @@ // hart0_csr_mem_server_response_get O 65 reg // RDY_hart0_csr_mem_server_response_get O 1 reg // RDY_hart0_put_other_req_put O 1 const -// v_to_TV_0_get O 785 +// v_to_TV_0_get O 862 // RDY_v_to_TV_0_get O 1 reg -// v_to_TV_1_get O 785 +// v_to_TV_1_get O 862 // RDY_v_to_TV_1_get O 1 reg // CLK I 1 clock // RST_N I 1 reset @@ -818,16 +818,16 @@ module mkProc(CLK, // actionvalue method v_to_TV_0_get input EN_v_to_TV_0_get; - output [784 : 0] v_to_TV_0_get; + output [861 : 0] v_to_TV_0_get; output RDY_v_to_TV_0_get; // actionvalue method v_to_TV_1_get input EN_v_to_TV_1_get; - output [784 : 0] v_to_TV_1_get; + output [861 : 0] v_to_TV_1_get; output RDY_v_to_TV_1_get; // signals for module outputs - wire [784 : 0] v_to_TV_0_get, v_to_TV_1_get; + wire [861 : 0] v_to_TV_0_get, v_to_TV_1_get; wire [64 : 0] hart0_csr_mem_server_response_get, hart0_fpr_mem_server_response_get, hart0_gpr_mem_server_response_get; @@ -1357,7 +1357,7 @@ module mkProc(CLK, // ports of submodule core_0 reg [66 : 0] core_0$mmioToPlatform_pRs_enq_x; reg [38 : 0] core_0$mmioToPlatform_pRq_enq_x; - wire [784 : 0] core_0$v_to_TV_0_get, core_0$v_to_TV_1_get; + wire [861 : 0] core_0$v_to_TV_0_get, core_0$v_to_TV_1_get; wire [582 : 0] core_0$dCacheToParent_fromP_enq_x, core_0$iCacheToParent_fromP_enq_x; wire [578 : 0] core_0$dCacheToParent_rsToP_first, @@ -2205,9 +2205,9 @@ module mkProc(CLK, wire [511 : 0] IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1288, SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1438, new_cline__h134569; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1571, + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1570, SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1421; - wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1566, + wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1565, SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1404; wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__177_THE_ETC___d1387; wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__70_BITS_14_ETC___d393; @@ -2347,8 +2347,8 @@ module mkProc(CLK, IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1258, IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1278, IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1294, - IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639, + IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638, IF_mmioPlatform_mtimecmp_0_48_ULE_IF_NOT_mmioP_ETC___d613, IF_mmioPlatform_reqFunc_28_BITS_5_TO_4_29_EQ_0_ETC___d445, IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__83__ETC___d192, @@ -2363,8 +2363,8 @@ module mkProc(CLK, IF_propDstIdx_1_lat_0_whas__000_THEN_propDstId_ETC___d1003, NOT_enqDst_0_dummy2_0_read__067_068_OR_NOT_enq_ETC___d1083, NOT_enqDst_1_0_dummy2_0_read__336_337_OR_NOT_e_ETC___d1352, - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770, - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689, + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768, + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d734, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d742, NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d747, @@ -2383,8 +2383,8 @@ module mkProc(CLK, NOT_propDstData_1_1_dummy2_1_read__355_366_OR__ETC___d1367, NOT_propDstIdx_0_dummy2_1_read__046_047_OR_IF__ETC___d1080, NOT_propDstIdx_1_0_dummy2_1_read__305_306_OR_I_ETC___d1349, - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583, - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505, + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582, + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504, mmioPlatform_cycle_39_ULT_99___d340, mmioPlatform_fetchingWay_53_ULT_mmioPlatform_r_ETC___d963, mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d323, @@ -2785,7 +2785,11 @@ module mkProc(CLK, // actionvalue method v_to_TV_0_get assign v_to_TV_0_get = - { core_0$v_to_TV_0_get[784:619], + { core_0$v_to_TV_0_get[861:797], + core_0$v_to_TV_0_get[797] ? + core_0$v_to_TV_0_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + core_0$v_to_TV_0_get[720:619], core_0$v_to_TV_0_get[619] ? core_0$v_to_TV_0_get[618:613] : 6'h2A, @@ -2809,7 +2813,11 @@ module mkProc(CLK, // actionvalue method v_to_TV_1_get assign v_to_TV_1_get = - { core_0$v_to_TV_1_get[784:619], + { core_0$v_to_TV_1_get[861:797], + core_0$v_to_TV_1_get[797] ? + core_0$v_to_TV_1_get[796:721] : + 76'hAAAAAAAAAAAAAAAAAAA, + core_0$v_to_TV_1_get[720:619], core_0$v_to_TV_1_get[619] ? core_0$v_to_TV_1_get[618:613] : 6'h2A, @@ -3559,32 +3567,36 @@ module mkProc(CLK, // rule RL_sendPRq assign CAN_FIRE_RL_sendPRq = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && !llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ; // rule RL_sendPRs assign CAN_FIRE_RL_sendPRs = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_dCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && !llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ; // rule RL_sendPRq_1 assign CAN_FIRE_RL_sendPRq_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && !llc$to_child_toC_first[583] && llc$to_child_toC_first[0] ; assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ; // rule RL_sendPRs_1 assign CAN_FIRE_RL_sendPRs_1 = - llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq && core_0$RDY_iCacheToParent_fromP_enq && + llc$RDY_to_child_toC_deq && + llc$RDY_to_child_toC_first && llc$to_child_toC_first[583] && llc$to_child_toC_first[516] ; assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ; @@ -3924,7 +3936,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 ; + llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3942,7 +3954,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 ; + llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ; @@ -3960,7 +3972,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3970,7 +3982,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && @@ -3979,7 +3991,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && !llc$dma_respSt_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd1 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish = @@ -3990,7 +4002,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 ; + !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3999,7 +4011,7 @@ module mkProc(CLK, llc$RDY_dma_memReq_enq && llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 ; + !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st && @@ -4007,7 +4019,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first && !llc$dma_respLd_first[4] && llc_mem_server_rg_cacheline_cache_state == 3'd2 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish = @@ -4031,7 +4043,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && llc_mem_server_enqDst_0_dummy2_1$Q_OUT && - IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -4048,15 +4060,15 @@ module mkProc(CLK, // rule RL_llc_mem_server_sendLdRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb = - llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq && - core_0$RDY_tlbToMem_respLd_enq && + core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq && + llc$RDY_dma_respLd_first && llc$dma_respLd_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb = CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ; // rule RL_llc_mem_server_sendStRespToTlb assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb = - llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq && + llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first && llc$dma_respSt_first[4] ; assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb = CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ; @@ -4290,7 +4302,7 @@ module mkProc(CLK, llc_mem_server_tlbQ$D_OUT[0], llc_mem_server_tlbQ$D_OUT[6:4] } ; assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1571, + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1570, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd1) ? new_dword__h89402 : @@ -4694,10 +4706,10 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656, + IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : - (NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ? + (NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0]) } ; assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ; @@ -4711,8 +4723,8 @@ module mkProc(CLK, // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = - !NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639 ; + !NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr @@ -5588,7 +5600,7 @@ module mkProc(CLK, // submodule llc_mem_server_enqDst_0_dummy2_0 assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ; assign llc_mem_server_enqDst_0_dummy2_0$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ; // submodule llc_mem_server_enqDst_0_dummy2_1 assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ; @@ -5618,11 +5630,11 @@ module mkProc(CLK, // submodule llc_mem_server_propDstIdx_0_dummy2_1 assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ; assign llc_mem_server_propDstIdx_0_dummy2_1$EN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ; + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ; // submodule llc_mem_server_tlbQ assign llc_mem_server_tlbQ$D_IN = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ? + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ? llc_mem_server_enqDst_0_lat_0$wget[64:0] : llc_mem_server_enqDst_0_rl[64:0] ; assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -5970,7 +5982,7 @@ module mkProc(CLK, 2'b10 : IF_enqDst_1_0_lat_0_whas__253_THEN_enqDst_1_0__ETC___d1273, IF_enqDst_1_0_lat_1_whas__250_THEN_enqDst_1_0__ETC___d1296 } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1566 = + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1565 = { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd7) ? new_dword__h89402 : @@ -5987,8 +5999,8 @@ module mkProc(CLK, 3'd4) ? new_dword__h89402 : llc_mem_server_rg_cacheline_cache_data[319:256] } ; - assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1571 = - { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1566, + assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1570 = + { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1565, (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] == 3'd3) ? new_dword__h89402 : @@ -5997,11 +6009,11 @@ module mkProc(CLK, 3'd2) ? new_dword__h89402 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__651_THE_ETC___d1656 = - NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 ? + assign IF_llc_mem_server_enqDst_0_lat_0_whas__650_THE_ETC___d1655 = + NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; assign IF_mmioPlatform_curReq_23_BITS_2_TO_0_65_EQ_0x_ETC___d813 = @@ -6241,14 +6253,14 @@ module mkProc(CLK, !enqDst_1_0_rl[580]) && (SEL_ARR_propDstIdx_1_0_dummy2_1_read__305_AND__ETC___d1346 || IF_NOT_propDstIdx_1_0_dummy2_1_read__305_306_O_ETC___d1350) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__682_ETC___d1689 = + assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__681_ETC___d1688 = (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT || !llc_mem_server_enqDst_0_dummy2_1$Q_OUT || !llc_mem_server_enqDst_0_rl[65]) && llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__636_ETC___d1639 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__635_ETC___d1638 ; assign NOT_mmioPlatform_curReq_23_BITS_66_TO_64_24_EQ_ETC___d734 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && @@ -6425,9 +6437,9 @@ module mkProc(CLK, assign line_addr__h101861 = { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35], 6'b0 } ; - assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1583 = + assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1582 = line_addr__h101861 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1505 = + assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1504 = line_addr__h101775 == llc_mem_server_rg_cacheline_cache_addr ; assign mask__h89398 = { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ? @@ -6995,14 +7007,14 @@ module mkProc(CLK, always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: data64__h147706 = llc$to_mem_toM_first[63:0]; - 3'd1: data64__h147706 = llc$to_mem_toM_first[127:64]; - 3'd2: data64__h147706 = llc$to_mem_toM_first[191:128]; - 3'd3: data64__h147706 = llc$to_mem_toM_first[255:192]; - 3'd4: data64__h147706 = llc$to_mem_toM_first[319:256]; - 3'd5: data64__h147706 = llc$to_mem_toM_first[383:320]; - 3'd6: data64__h147706 = llc$to_mem_toM_first[447:384]; - 3'd7: data64__h147706 = llc$to_mem_toM_first[511:448]; + 3'd0: strb8__h147707 = llc$to_mem_toM_first[519:512]; + 3'd1: strb8__h147707 = llc$to_mem_toM_first[527:520]; + 3'd2: strb8__h147707 = llc$to_mem_toM_first[535:528]; + 3'd3: strb8__h147707 = llc$to_mem_toM_first[543:536]; + 3'd4: strb8__h147707 = llc$to_mem_toM_first[551:544]; + 3'd5: strb8__h147707 = llc$to_mem_toM_first[559:552]; + 3'd6: strb8__h147707 = llc$to_mem_toM_first[567:560]; + 3'd7: strb8__h147707 = llc$to_mem_toM_first[575:568]; endcase end always@(llc$dma_respLd_first) @@ -7021,14 +7033,14 @@ module mkProc(CLK, always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: strb8__h147707 = llc$to_mem_toM_first[519:512]; - 3'd1: strb8__h147707 = llc$to_mem_toM_first[527:520]; - 3'd2: strb8__h147707 = llc$to_mem_toM_first[535:528]; - 3'd3: strb8__h147707 = llc$to_mem_toM_first[543:536]; - 3'd4: strb8__h147707 = llc$to_mem_toM_first[551:544]; - 3'd5: strb8__h147707 = llc$to_mem_toM_first[559:552]; - 3'd6: strb8__h147707 = llc$to_mem_toM_first[567:560]; - 3'd7: strb8__h147707 = llc$to_mem_toM_first[575:568]; + 3'd0: data64__h147706 = llc$to_mem_toM_first[63:0]; + 3'd1: data64__h147706 = llc$to_mem_toM_first[127:64]; + 3'd2: data64__h147706 = llc$to_mem_toM_first[191:128]; + 3'd3: data64__h147706 = llc$to_mem_toM_first[255:192]; + 3'd4: data64__h147706 = llc$to_mem_toM_first[319:256]; + 3'd5: data64__h147706 = llc$to_mem_toM_first[383:320]; + 3'd6: data64__h147706 = llc$to_mem_toM_first[447:384]; + 3'd7: data64__h147706 = llc$to_mem_toM_first[511:448]; endcase end always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or @@ -9807,7 +9819,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) begin v__h134266 = $stime; #0; @@ -9815,63 +9827,63 @@ module mkProc(CLK, v__h134260 = v__h134266 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", v__h134260, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Rd_Data { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && !llc_axi4_adapter_master_xactor_rg_rd_data[0]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && @@ -9947,119 +9959,119 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770 && + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && @@ -11287,139 +11299,139 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" To fabric: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Wr_Addr { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", mem_req_wr_addr_awaddr__h147791); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Wr_Data { ", "wdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", data64__h147706); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "wstrb: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", strb8__h147707); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "wlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "wuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && @@ -11506,103 +11518,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Rd_Addr { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", mem_req_rd_addr_araddr__h133867); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 8'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'b011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 2'b01); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'h0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) begin v__h160574 = $stime; #0; @@ -11610,41 +11622,41 @@ module mkProc(CLK, v__h160568 = v__h160574 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", v__h160568, llc_axi4_adapter_rg_wr_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("AXI4_Wr_Resp { ", "bid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "bresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write(", ", "buser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && - NOT_llc_axi4_adapter_cfg_verbosity_read__753_U_ETC___d1770) + NOT_llc_axi4_adapter_cfg_verbosity_read__751_U_ETC___d1768) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v b/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v index 6910a82..90c7ef6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTrace_Data2_to_Trace_Data.v @@ -11,7 +11,7 @@ // RDY_out_get O 1 reg // CLK I 1 clock // RST_N I 1 reset -// in_put I 785 +// in_put I 862 // EN_in_put I 1 // EN_out_get I 1 // @@ -46,7 +46,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, input RST_N; // action method in_put - input [784 : 0] in_put; + input [861 : 0] in_put; input EN_in_put; output RDY_in_put; @@ -60,7 +60,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, wire RDY_in_put, RDY_out_get; // ports of submodule f_in - wire [784 : 0] f_in$D_IN, f_in$D_OUT; + wire [861 : 0] f_in$D_IN, f_in$D_OUT; wire f_in$CLR, f_in$DEQ, f_in$EMPTY_N, f_in$ENQ, f_in$FULL_N; // ports of submodule f_out @@ -76,51 +76,54 @@ module mkTrace_Data2_to_Trace_Data(CLK, WILL_FIRE_out_get; // remaining internal signals - reg [63 : 0] x1_avValue_pc__h3456, x1_avValue_word1__h3460; - reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, - csr_addr__h5126; - reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1, - x1_avValue_rd__h3459; - reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4; - reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5; - wire [63 : 0] td_word2__h3496, - td_word2__h3647, - td_word3__h3497, - td_word4__h3384, - x1_avValue_pc__h3420, - x1_avValue_pc__h3726, - x1_avValue_pc__h3793, - x1_avValue_word1__h3506, - x1_avValue_word1__h3543, - x1_avValue_word1__h3619, - x1_avValue_word1__h3696, - x1_avValue_word1__h3797, - x1_avValue_word2__h3507, - x1_avValue_word2__h3620, - x1_avValue_word2__h3798, - x1_avValue_word3__h3508, - x1_avValue_word3__h3799, - x1_avValue_word4__h3463, - x1_avValue_word4__h3583, - x1_avValue_word4__h3800, - x__h4701, - x__h4967, - x__h5065, - x__h5274, - x__h5697; - wire [11 : 0] csraddr__h3479; - wire [4 : 0] td_rd__h3380, - td_rd__h3448, - x1_avValue_rd__h3423, - x1_avValue_rd__h3542, - x1_avValue_rd__h3579, - x1_avValue_rd__h3618, - x1_avValue_rd__h3656, - x1_avValue_rd__h3695, - x1_avValue_rd__h3796, - x1_avValue_rd__h3866; - wire [2 : 0] st_funct3__h346; + reg [63 : 0] x1_avValue_pc__h3546, x1_avValue_word1__h3550; + reg [11 : 0] CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, + csr_addr__h5294; + reg [4 : 0] CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5, + x1_avValue_rd__h3549; + reg [3 : 0] CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3; + reg [1 : 0] CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4; + wire [63 : 0] td_word2__h3586, + td_word2__h3737, + td_word3__h3587, + td_word3__h3951, + td_word4__h3474, + x1_avValue_pc__h3510, + x1_avValue_pc__h3816, + x1_avValue_pc__h3883, + x1_avValue_word1__h3596, + x1_avValue_word1__h3633, + x1_avValue_word1__h3709, + x1_avValue_word1__h3786, + x1_avValue_word1__h3887, + x1_avValue_word2__h3597, + x1_avValue_word2__h3710, + x1_avValue_word2__h3888, + x1_avValue_word3__h3598, + x1_avValue_word3__h3889, + x1_avValue_word3__h3931, + x1_avValue_word4__h3553, + x1_avValue_word4__h3673, + x1_avValue_word4__h3890, + x1_avValue_word4__h3932, + x__h4843, + x__h5134, + x__h5233, + x__h5443, + x__h5875; + wire [11 : 0] csraddr__h3569; + wire [4 : 0] td_rd__h3470, + td_rd__h3538, + x1_avValue_rd__h3513, + x1_avValue_rd__h3632, + x1_avValue_rd__h3669, + x1_avValue_rd__h3708, + x1_avValue_rd__h3746, + x1_avValue_rd__h3785, + x1_avValue_rd__h3886, + x1_avValue_rd__h3987; + wire [2 : 0] st_funct3__h348; // action method in_put assign RDY_in_put = f_in$FULL_N ; @@ -134,7 +137,7 @@ module mkTrace_Data2_to_Trace_Data(CLK, assign WILL_FIRE_out_get = EN_out_get ; // submodule f_in - FIFO2 #(.width(32'd785), .guarded(32'd1)) f_in(.RST(RST_N), + FIFO2 #(.width(32'd862), .guarded(32'd1)) f_in(.RST(RST_N), .CLK(CLK), .D_IN(f_in$D_IN), .ENQ(f_in$ENQ), @@ -161,14 +164,14 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_in assign f_in$D_IN = - { in_put[784:476], - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2, + { in_put[861:476], + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1, in_put[463:462], in_put[462] ? - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 : - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4, + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 : + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3, in_put[457:394], - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5, + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4, in_put[391:0] } ; assign f_in$ENQ = EN_in_put ; assign f_in$DEQ = CAN_FIRE_RL_rl_td2_to_td ; @@ -176,68 +179,70 @@ module mkTrace_Data2_to_Trace_Data(CLK, // submodule f_out assign f_out$D_IN = - { f_in$D_OUT[784:721], - (f_in$D_OUT[784:721] == 64'd0) ? + { f_in$D_OUT[861:798], + (f_in$D_OUT[861:798] == 64'd0) ? 5'd0 : - (f_in$D_OUT[463] ? - 5'd14 : - ((f_in$D_OUT[393:392] == 2'd0 && - f_in$D_OUT[624:620] == 5'd10) ? - 5'd5 : + (f_in$D_OUT[797] ? + 5'd3 : + (f_in$D_OUT[463] ? + 5'd14 : ((f_in$D_OUT[393:392] == 2'd0 && - (f_in$D_OUT[624:620] == 5'd8 || - f_in$D_OUT[624:620] == 5'd9) || - f_in$D_OUT[624:620] == 5'd3 || - f_in$D_OUT[624:620] == 5'd11) ? - 5'd6 : - ((f_in$D_OUT[619] && f_in$D_OUT[618] && - f_in$D_OUT[624:620] == 5'd12) ? - 5'd8 : - ((f_in$D_OUT[624:620] == 5'd12) ? - 5'd7 : - ((f_in$D_OUT[393:392] == 2'd1 && - f_in$D_OUT[619] && - f_in$D_OUT[618] && - f_in$D_OUT[624:620] == 5'd4) ? - 5'd10 : + f_in$D_OUT[624:620] == 5'd10) ? + 5'd5 : + ((f_in$D_OUT[393:392] == 2'd0 && + (f_in$D_OUT[624:620] == 5'd8 || + f_in$D_OUT[624:620] == 5'd9) || + f_in$D_OUT[624:620] == 5'd3 || + f_in$D_OUT[624:620] == 5'd11) ? + 5'd6 : + ((f_in$D_OUT[619] && f_in$D_OUT[618] && + f_in$D_OUT[624:620] == 5'd12) ? + 5'd8 : + ((f_in$D_OUT[624:620] == 5'd12) ? + 5'd7 : ((f_in$D_OUT[393:392] == 2'd1 && + f_in$D_OUT[619] && + f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? - 5'd9 : + 5'd10 : ((f_in$D_OUT[393:392] == 2'd1 && - f_in$D_OUT[624:620] == 5'd5) ? - 5'd11 : - ((f_in$D_OUT[393:392] != 2'd0 && - f_in$D_OUT[393:392] != 2'd1 && - f_in$D_OUT[624:620] == 5'd13) ? - 5'd16 : - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1))))))))), - x__h4701, + f_in$D_OUT[624:620] == 5'd4) ? + 5'd9 : + ((f_in$D_OUT[393:392] == 2'd1 && + f_in$D_OUT[624:620] == 5'd5) ? + 5'd11 : + ((f_in$D_OUT[393:392] != 2'd0 && + f_in$D_OUT[393:392] != 2'd1 && + f_in$D_OUT[624:620] == 5'd13) ? + 5'd16 : + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5)))))))))), + x__h4843, f_in$D_OUT[626:625] == 2'b11, f_in$D_OUT[656:625], - x1_avValue_rd__h3866, - x__h4967, - x__h5065, - x__h5274, - x__h5697, + x1_avValue_rd__h3987, + x__h5134, + x__h5233, + x__h5443, + x__h5875, f_in$D_OUT[612:549] } ; - assign f_out$ENQ = f_in$EMPTY_N && f_out$FULL_N ; + assign f_out$ENQ = CAN_FIRE_RL_rl_td2_to_td ; assign f_out$DEQ = EN_out_get ; assign f_out$CLR = 1'b0 ; // remaining internal signals - assign csraddr__h3479 = f_in$D_OUT[476] ? csr_addr__h5126 : 12'd0 ; - assign st_funct3__h346 = + assign csraddr__h3569 = f_in$D_OUT[476] ? csr_addr__h5294 : 12'd0 ; + assign st_funct3__h348 = f_in$D_OUT[484] ? 3'b011 : (f_in$D_OUT[480] ? 3'b010 : (f_in$D_OUT[478] ? 3'b001 : 3'b0)) ; - assign td_rd__h3380 = + assign td_rd__h3470 = (f_in$D_OUT[619] && !f_in$D_OUT[618]) ? f_in$D_OUT[617:613] : 5'd0 ; - assign td_rd__h3448 = { 3'd0, f_in$D_OUT[257:256] } ; - assign td_word2__h3496 = + assign td_rd__h3538 = { 3'd0, f_in$D_OUT[257:256] } ; + assign td_word2__h3586 = (f_in$D_OUT[476] && (f_in$D_OUT[638:637] == 2'b01 || (f_in$D_OUT[638:637] == 2'b10 || @@ -245,150 +250,155 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[644:640] != 5'd0)) ? 64'd1 : 64'd0 ; - assign td_word2__h3647 = { 59'd0, f_in$D_OUT[327:323] } ; - assign td_word3__h3497 = { 52'd0, csraddr__h3479 } ; - assign td_word4__h3384 = { 61'd0, st_funct3__h346 } ; - assign x1_avValue_pc__h3420 = + assign td_word2__h3737 = { 59'd0, f_in$D_OUT[327:323] } ; + assign td_word3__h3587 = { 52'd0, csraddr__h3569 } ; + assign td_word3__h3951 = { 52'd0, f_in$D_OUT[796:785] } ; + assign td_word4__h3474 = { 61'd0, st_funct3__h348 } ; + assign x1_avValue_pc__h3510 = f_in$D_OUT[720:657] + ((f_in$D_OUT[626:625] == 2'b11) ? 64'd4 : 64'd2) ; - assign x1_avValue_pc__h3726 = + assign x1_avValue_pc__h3816 = (f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11 || f_in$D_OUT[624:620] == 5'd12 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5 || f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - x1_avValue_pc__h3420 : - x1_avValue_pc__h3456 ; - assign x1_avValue_pc__h3793 = + x1_avValue_pc__h3510 : + x1_avValue_pc__h3546 ; + assign x1_avValue_pc__h3883 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd10 || f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9)) ? f_in$D_OUT[391:328] : - x1_avValue_pc__h3726 ; - assign x1_avValue_rd__h3423 = td_rd__h3380 ; - assign x1_avValue_rd__h3542 = + x1_avValue_pc__h3816 ; + assign x1_avValue_rd__h3513 = td_rd__h3470 ; + assign x1_avValue_rd__h3632 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_rd__h3380 : - x1_avValue_rd__h3459 ; - assign x1_avValue_rd__h3579 = + td_rd__h3470 : + x1_avValue_rd__h3549 ; + assign x1_avValue_rd__h3669 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4) ? - td_rd__h3380 : - x1_avValue_rd__h3542 ; - assign x1_avValue_rd__h3618 = + td_rd__h3470 : + x1_avValue_rd__h3632 ; + assign x1_avValue_rd__h3708 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[617:613] : - x1_avValue_rd__h3579 ; - assign x1_avValue_rd__h3656 = + x1_avValue_rd__h3669 ; + assign x1_avValue_rd__h3746 = (f_in$D_OUT[624:620] == 5'd12) ? - td_rd__h3380 : - x1_avValue_rd__h3618 ; - assign x1_avValue_rd__h3695 = + td_rd__h3470 : + x1_avValue_rd__h3708 ; + assign x1_avValue_rd__h3785 = (f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd12) ? f_in$D_OUT[617:613] : - x1_avValue_rd__h3656 ; - assign x1_avValue_rd__h3796 = + x1_avValue_rd__h3746 ; + assign x1_avValue_rd__h3886 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9) || f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11) ? - td_rd__h3380 : - x1_avValue_rd__h3695 ; - assign x1_avValue_rd__h3866 = - f_in$D_OUT[463] ? td_rd__h3448 : x1_avValue_rd__h3796 ; - assign x1_avValue_word1__h3506 = + td_rd__h3470 : + x1_avValue_rd__h3785 ; + assign x1_avValue_rd__h3987 = + f_in$D_OUT[463] ? td_rd__h3538 : x1_avValue_rd__h3886 ; + assign x1_avValue_word1__h3596 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3460 ; - assign x1_avValue_word1__h3543 = + x1_avValue_word1__h3550 ; + assign x1_avValue_word1__h3633 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5) ? - td_word4__h3384 : - x1_avValue_word1__h3506 ; - assign x1_avValue_word1__h3619 = + td_word4__h3474 : + x1_avValue_word1__h3596 ; + assign x1_avValue_word1__h3709 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3543 ; - assign x1_avValue_word1__h3696 = + x1_avValue_word1__h3633 ; + assign x1_avValue_word1__h3786 = (f_in$D_OUT[624:620] == 5'd12) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3619 ; - assign x1_avValue_word1__h3797 = + x1_avValue_word1__h3709 ; + assign x1_avValue_word1__h3887 = (f_in$D_OUT[393:392] == 2'd0 && (f_in$D_OUT[624:620] == 5'd8 || f_in$D_OUT[624:620] == 5'd9) || f_in$D_OUT[624:620] == 5'd3 || f_in$D_OUT[624:620] == 5'd11) ? f_in$D_OUT[612:549] : - x1_avValue_word1__h3696 ; - assign x1_avValue_word2__h3507 = + x1_avValue_word1__h3786 ; + assign x1_avValue_word2__h3597 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_word2__h3496 : + td_word2__h3586 : f_in$D_OUT[548:485] ; - assign x1_avValue_word2__h3620 = + assign x1_avValue_word2__h3710 = (f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[624:620] == 5'd5) ? f_in$D_OUT[548:485] : - x1_avValue_word2__h3507 ; - assign x1_avValue_word2__h3798 = + x1_avValue_word2__h3597 ; + assign x1_avValue_word2__h3888 = (f_in$D_OUT[624:620] == 5'd12) ? - td_word2__h3647 : - x1_avValue_word2__h3620 ; - assign x1_avValue_word3__h3508 = + td_word2__h3737 : + x1_avValue_word2__h3710 ; + assign x1_avValue_word3__h3598 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? - td_word3__h3497 : + td_word3__h3587 : f_in$D_OUT[391:328] ; - assign x1_avValue_word3__h3799 = + assign x1_avValue_word3__h3889 = (f_in$D_OUT[393:392] == 2'd1 && (f_in$D_OUT[624:620] == 5'd4 || f_in$D_OUT[624:620] == 5'd5)) ? f_in$D_OUT[391:328] : - x1_avValue_word3__h3508 ; - assign x1_avValue_word4__h3463 = td_word4__h3384 ; - assign x1_avValue_word4__h3583 = + x1_avValue_word3__h3598 ; + assign x1_avValue_word3__h3931 = + f_in$D_OUT[463] ? f_in$D_OUT[63:0] : x1_avValue_word3__h3889 ; + assign x1_avValue_word4__h3553 = td_word4__h3474 ; + assign x1_avValue_word4__h3673 = (f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd13) ? f_in$D_OUT[391:328] : - x1_avValue_word4__h3463 ; - assign x1_avValue_word4__h3800 = + x1_avValue_word4__h3553 ; + assign x1_avValue_word4__h3890 = (f_in$D_OUT[624:620] == 5'd12 || f_in$D_OUT[393:392] == 2'd1 && f_in$D_OUT[619] && f_in$D_OUT[618] && f_in$D_OUT[624:620] == 5'd4) ? f_in$D_OUT[321:258] : - x1_avValue_word4__h3583 ; - assign x__h4701 = - f_in$D_OUT[463] ? f_in$D_OUT[255:192] : x1_avValue_pc__h3793 ; - assign x__h4967 = - f_in$D_OUT[463] ? f_in$D_OUT[191:128] : x1_avValue_word1__h3797 ; - assign x__h5065 = - f_in$D_OUT[463] ? f_in$D_OUT[127:64] : x1_avValue_word2__h3798 ; - assign x__h5274 = - f_in$D_OUT[463] ? f_in$D_OUT[63:0] : x1_avValue_word3__h3799 ; - assign x__h5697 = - f_in$D_OUT[463] ? f_in$D_OUT[457:394] : x1_avValue_word4__h3800 ; + x1_avValue_word4__h3673 ; + assign x1_avValue_word4__h3932 = + f_in$D_OUT[463] ? f_in$D_OUT[457:394] : x1_avValue_word4__h3890 ; + assign x__h4843 = + f_in$D_OUT[463] ? f_in$D_OUT[255:192] : x1_avValue_pc__h3883 ; + assign x__h5134 = + f_in$D_OUT[463] ? f_in$D_OUT[191:128] : x1_avValue_word1__h3887 ; + assign x__h5233 = + f_in$D_OUT[463] ? f_in$D_OUT[127:64] : x1_avValue_word2__h3888 ; + assign x__h5443 = + f_in$D_OUT[797] ? td_word3__h3951 : x1_avValue_word3__h3931 ; + assign x__h5875 = + f_in$D_OUT[797] ? f_in$D_OUT[784:721] : x1_avValue_word4__h3932 ; always@(f_in$D_OUT) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_word1__h3460 = f_in$D_OUT[191:128]; - default: x1_avValue_word1__h3460 = f_in$D_OUT[612:549]; + 5'd19, 5'd20: x1_avValue_word1__h3550 = f_in$D_OUT[191:128]; + default: x1_avValue_word1__h3550 = f_in$D_OUT[612:549]; endcase end - always@(f_in$D_OUT or x1_avValue_pc__h3420) + always@(f_in$D_OUT or x1_avValue_pc__h3510) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_pc__h3456 = f_in$D_OUT[720:657]; - default: x1_avValue_pc__h3456 = x1_avValue_pc__h3420; + 5'd19, 5'd20: x1_avValue_pc__h3546 = f_in$D_OUT[720:657]; + default: x1_avValue_pc__h3546 = x1_avValue_pc__h3510; endcase end - always@(f_in$D_OUT or x1_avValue_rd__h3423 or td_rd__h3448) + always@(f_in$D_OUT or x1_avValue_rd__h3513 or td_rd__h3538) begin case (f_in$D_OUT[624:620]) - 5'd19, 5'd20: x1_avValue_rd__h3459 = td_rd__h3448; - default: x1_avValue_rd__h3459 = x1_avValue_rd__h3423; + 5'd19, 5'd20: x1_avValue_rd__h3549 = td_rd__h3538; + default: x1_avValue_rd__h3549 = x1_avValue_rd__h3513; endcase end always@(f_in$D_OUT) @@ -438,24 +448,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - csr_addr__h5126 = f_in$D_OUT[475:464]; - default: csr_addr__h5126 = 12'd2303; - endcase - end - always@(f_in$D_OUT) - begin - case (f_in$D_OUT[624:620]) - 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd5; - 5'd19, 5'd20: - CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = 5'd15; - default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q1 = - (f_in$D_OUT[393:392] == 2'd1 && - (f_in$D_OUT[624:620] == 5'd2 || - f_in$D_OUT[624:620] == 5'd6 || - f_in$D_OUT[624:620] == 5'd7)) ? - 5'd13 : - 5'd5; + csr_addr__h5294 = f_in$D_OUT[475:464]; + default: csr_addr__h5294 = 12'd2303; endcase end always@(in_put) @@ -505,9 +499,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, 12'd3858, 12'd3859, 12'd3860: - CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = in_put[475:464]; - default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q2 = + default: CASE_in_put_BITS_475_TO_464_1_in_put_BITS_475__ETC__q1 = 12'd2303; endcase end @@ -515,9 +509,9 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin case (in_put[461:458]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q2 = 4'd15; endcase end always@(in_put) @@ -536,18 +530,34 @@ module mkTrace_Data2_to_Trace_Data(CLK, 4'd11, 4'd12, 4'd13: - CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = + CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = in_put[461:458]; - default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q4 = 4'd15; + default: CASE_in_put_BITS_461_TO_458_0_in_put_BITS_461__ETC__q3 = 4'd15; endcase end always@(in_put) begin case (in_put[393:392]) 2'd0, 2'd1: - CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = + CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = in_put[393:392]; - default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q5 = 2'd2; + default: CASE_in_put_BITS_393_TO_392_0_in_put_BITS_393__ETC__q4 = 2'd2; + endcase + end + always@(f_in$D_OUT) + begin + case (f_in$D_OUT[624:620]) + 5'd14, 5'd15, 5'd16, 5'd17, 5'd18: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd5; + 5'd19, 5'd20: + CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = 5'd15; + default: CASE_f_inD_OUT_BITS_624_TO_620_14_5_15_5_16_5_ETC__q5 = + (f_in$D_OUT[393:392] == 2'd1 && + (f_in$D_OUT[624:620] == 5'd2 || + f_in$D_OUT[624:620] == 5'd6 || + f_in$D_OUT[624:620] == 5'd7)) ? + 5'd13 : + 5'd5; endcase end @@ -558,7 +568,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -588,7 +599,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $display(" fav_td2_to_td: TBD: Unknown iType: Using mkTrace_OTHER for now"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -618,7 +630,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(" "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -648,7 +661,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("Trace_Data2 { ", "serial_num: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -676,9 +690,196 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd0 && f_in$D_OUT[624:620] != 5'd1 && f_in$D_OUT[624:620] != 5'd21) - $write("'h%h", f_in$D_OUT[784:721]); + $write("'h%h", f_in$D_OUT[861:798]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(", ", "maybe_csr_upd: "); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write("tagged Invalid ", ""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && + !f_in$D_OUT[463] && + (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && + (f_in$D_OUT[393:392] != 2'd0 || + f_in$D_OUT[624:620] != 5'd8 && f_in$D_OUT[624:620] != 5'd9) && + f_in$D_OUT[624:620] != 5'd3 && + f_in$D_OUT[624:620] != 5'd11 && + f_in$D_OUT[624:620] != 5'd12 && + (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || + !f_in$D_OUT[618] || + f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd4) && + (f_in$D_OUT[393:392] != 2'd1 || f_in$D_OUT[624:620] != 5'd5) && + (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1 || + f_in$D_OUT[624:620] != 5'd13) && + f_in$D_OUT[624:620] != 5'd20 && + f_in$D_OUT[624:620] != 5'd19 && + f_in$D_OUT[624:620] != 5'd14 && + f_in$D_OUT[624:620] != 5'd15 && + f_in$D_OUT[624:620] != 5'd16 && + f_in$D_OUT[624:620] != 5'd17 && + f_in$D_OUT[624:620] != 5'd18 && + (f_in$D_OUT[393:392] != 2'd1 || + f_in$D_OUT[624:620] != 5'd2 && f_in$D_OUT[624:620] != 5'd6 && + f_in$D_OUT[624:620] != 5'd7) && + f_in$D_OUT[624:620] != 5'd0 && + f_in$D_OUT[624:620] != 5'd1 && + f_in$D_OUT[624:620] != 5'd21) + $write(""); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -708,7 +909,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "pc: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -738,7 +940,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[720:657]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -768,7 +971,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "orig_inst: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -798,7 +1002,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[656:625]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -828,13 +1033,15 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "iType: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd2) $write("Amo"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd1 || !f_in$D_OUT[619] || !f_in$D_OUT[618]) && @@ -842,49 +1049,57 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] == 5'd4) $write("Ld"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd5) $write("St"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd6) $write("Lr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd1 && f_in$D_OUT[624:620] == 5'd7) $write("Sc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd8) $write("J"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd9) $write("Jr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[393:392] != 2'd0 && f_in$D_OUT[624:620] == 5'd10) $write("Br"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] == 2'd0 || f_in$D_OUT[393:392] == 2'd1) && f_in$D_OUT[624:620] == 5'd13) $write("Csr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -910,7 +1125,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd13) $write("Interrupt"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -940,7 +1156,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "dst: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -970,7 +1187,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[619]) $write("tagged Valid "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -998,7 +1216,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[619]) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1027,7 +1246,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[618]) $write("tagged Fpu ", "'h%h", f_in$D_OUT[617:613]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1056,7 +1276,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[618]) $write("tagged Gpr ", "'h%h", f_in$D_OUT[617:613]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1084,7 +1305,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[619]) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1114,7 +1336,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "dst_data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1144,7 +1367,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[612:549]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1174,7 +1398,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "store_data: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1204,7 +1429,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[548:485]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1234,7 +1460,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "store_data_BE: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -1264,7 +1491,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2090,7 +2344,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "csr: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2121,7 +2376,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[476]) $write("tagged Valid "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2152,7 +2408,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[476]) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2184,7 +2441,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1) $write("CSRfflags"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2216,7 +2474,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2) $write("CSRfrm"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2248,7 +2507,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3) $write("CSRfcsr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2280,7 +2540,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3072) $write("CSRcycle"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2312,7 +2573,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3073) $write("CSRtime"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2344,7 +2606,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3074) $write("CSRinstret"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2376,7 +2639,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2048) $write("CSRterminate"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2408,7 +2672,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2049) $write("CSRstats"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2440,7 +2705,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd256) $write("CSRsstatus"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2472,7 +2738,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd260) $write("CSRsie"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2504,7 +2771,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd261) $write("CSRstvec"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2536,7 +2804,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd262) $write("CSRscounteren"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2568,7 +2837,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd320) $write("CSRsscratch"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2600,7 +2870,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd321) $write("CSRsepc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2632,7 +2903,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd322) $write("CSRscause"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2664,7 +2936,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd323) $write("CSRstval"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2696,7 +2969,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd324) $write("CSRsip"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2728,7 +3002,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd384) $write("CSRsatp"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2760,7 +3035,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd768) $write("CSRmstatus"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2792,7 +3068,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd769) $write("CSRmisa"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2824,7 +3101,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd770) $write("CSRmedeleg"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2856,7 +3134,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd771) $write("CSRmideleg"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2888,7 +3167,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd772) $write("CSRmie"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2920,7 +3200,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd773) $write("CSRmtvec"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2952,7 +3233,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd774) $write("CSRmcounteren"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -2984,7 +3266,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd832) $write("CSRmscratch"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3016,7 +3299,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd833) $write("CSRmepc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3048,7 +3332,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd834) $write("CSRmcause"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3080,7 +3365,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd835) $write("CSRmtval"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3112,7 +3398,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd836) $write("CSRmip"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3144,7 +3431,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2816) $write("CSRmcycle"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3176,7 +3464,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd2818) $write("CSRminstret"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3208,7 +3497,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3857) $write("CSRmvendorid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3240,7 +3530,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3858) $write("CSRmarchid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3272,7 +3563,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3859) $write("CSRmimpid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3304,7 +3596,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd3860) $write("CSRmhartid"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3336,7 +3629,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1952) $write("CSRtselect"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3368,7 +3662,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1953) $write("CSRtdata1"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3400,7 +3695,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1954) $write("CSRtdata2"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3432,7 +3728,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1955) $write("CSRtdata3"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3464,7 +3761,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1968) $write("CSRdcsr"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3496,7 +3794,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1969) $write("CSRdpc"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3528,7 +3827,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1970) $write("CSRdscratch0"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3560,7 +3860,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] == 12'd1971) $write("CSRdscratch1"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3635,7 +3936,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[475:464] != 12'd1971) $write("CSRnone"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3666,7 +3968,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[476]) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3696,7 +3999,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "trap: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3726,7 +4030,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("tagged Invalid ", ""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3756,7 +4061,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3786,7 +4092,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3816,7 +4123,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(""); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3846,7 +4154,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "tval: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3876,7 +4185,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[457:394]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -3906,7 +4216,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "ppc_vaddr_csrData: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd10 && f_in$D_OUT[624:620] != 5'd8 && @@ -3927,7 +4238,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] == 2'd0) $write("tagged PPC ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -3952,7 +4264,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] == 2'd1) $write("tagged VAddr ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && f_in$D_OUT[624:620] != 5'd3 && f_in$D_OUT[624:620] != 5'd11 && @@ -3972,7 +4285,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[393:392] != 2'd1) $write("tagged CSRData ", "'h%h", f_in$D_OUT[391:328]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4002,7 +4316,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "fflags: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4032,7 +4347,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[327:323]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4062,7 +4378,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "will_dirty_fpu_state: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4093,7 +4410,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[322]) $write("True"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4124,7 +4442,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, !f_in$D_OUT[322]) $write("False"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4154,7 +4473,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "mstatus: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4184,7 +4504,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[321:258]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4214,7 +4535,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "prv: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4244,7 +4566,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[257:256]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4274,7 +4597,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "tvec: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4304,7 +4628,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[255:192]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4334,7 +4659,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "status: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4364,7 +4690,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[191:128]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4394,7 +4721,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "cause: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4424,7 +4752,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[127:64]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4454,7 +4783,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write(", ", "epc: "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 || @@ -4484,7 +4814,8 @@ module mkTrace_Data2_to_Trace_Data(CLK, f_in$D_OUT[624:620] != 5'd21) $write("'h%h", f_in$D_OUT[63:0], " }"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[784:721] != 64'd0 && + if (WILL_FIRE_RL_rl_td2_to_td && f_in$D_OUT[861:798] != 64'd0 && + !f_in$D_OUT[797] && !f_in$D_OUT[463] && (f_in$D_OUT[393:392] != 2'd0 || f_in$D_OUT[624:620] != 5'd10) && (f_in$D_OUT[393:392] != 2'd0 ||