From 40f810926367db2d86eb2dfb2abe9540cdfcfed1 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Mon, 6 Jul 2020 19:32:56 +0100 Subject: [PATCH] Regenerate verilog --- src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkBht.v | 2 +- src_SSITH_P3/Verilog_RTL/mkCore.v | 4536 ++++++++--------- src_SSITH_P3/Verilog_RTL/mkCoreW.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v | 2 +- .../Verilog_RTL/mkDM_Abstract_Commands.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDebug_Module.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDirPredictor.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDivExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v | 2 +- src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/Verilog_RTL/mkEpochManager.v | 2 +- src_SSITH_P3/Verilog_RTL/mkFetchStage.v | 2 +- src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v | 2 +- .../Verilog_RTL/mkFpuMulDivDispToRegFifo.v | 2 +- .../Verilog_RTL/mkFpuMulDivRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSelectPred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkGSharePred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkICoCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL/mkIPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkITlb.v | 2 +- src_SSITH_P3/Verilog_RTL/mkL2Tlb.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLLCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLLPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMMIOInst.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemLoader.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkMulExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkNullTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkP3_Core.v | 2 +- src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v | 2 +- src_SSITH_P3/Verilog_RTL/mkProc.v | 2851 ++++++----- src_SSITH_P3/Verilog_RTL/mkRFileSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRas.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v | 2 +- .../Verilog_RTL/mkReorderBufferSynth.v | 2 +- .../Verilog_RTL/mkReservationStationAlu.v | 2 +- .../mkReservationStationFpuMulDiv.v | 2 +- .../Verilog_RTL/mkReservationStationMem.v | 2 +- src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v | 2 +- src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSoC_Map.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v | 2 +- src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourPred.v | 2 +- src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v | 2 +- src_SSITH_P3/Verilog_RTL/module_alu.v | 2 +- src_SSITH_P3/Verilog_RTL/module_aluBr.v | 2 +- src_SSITH_P3/Verilog_RTL/module_amoExec.v | 2 +- src_SSITH_P3/Verilog_RTL/module_basicExec.v | 2 +- src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v | 2 +- src_SSITH_P3/Verilog_RTL/module_capChecks.v | 2 +- src_SSITH_P3/Verilog_RTL/module_capInspect.v | 2 +- src_SSITH_P3/Verilog_RTL/module_capModify.v | 2 +- .../Verilog_RTL/module_checkForException.v | 2 +- src_SSITH_P3/Verilog_RTL/module_decode.v | 2 +- .../Verilog_RTL/module_decodeBrPred.v | 2 +- .../Verilog_RTL/module_execFpuSimple.v | 2 +- .../Verilog_RTL/module_prepareBoundsCheck.v | 2 +- .../Verilog_RTL/module_setBoundsALU.v | 2 +- .../Verilog_RTL/module_specialRWALU.v | 2 +- .../Verilog_RTL_sim/mkAluDispToRegFifo.v | 2 +- .../Verilog_RTL_sim/mkAluExeToFinFifo.v | 2 +- .../Verilog_RTL_sim/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkBht.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkCore.v | 4416 ++++++++-------- src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v | 2 +- .../Verilog_RTL_sim/mkDCRqMshrWrapper.v | 2 +- .../Verilog_RTL_sim/mkDM_Abstract_Commands.v | 2 +- .../Verilog_RTL_sim/mkDM_Run_Control.v | 2 +- .../Verilog_RTL_sim/mkDM_System_Bus.v | 2 +- .../Verilog_RTL_sim/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v | 2 +- .../Verilog_RTL_sim/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v | 2 +- .../mkFpuMulDivDispToRegFifo.v | 2 +- .../Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v | 2 +- .../Verilog_RTL_sim/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v | 2 +- .../Verilog_RTL_sim/mkGShareGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v | 2 +- .../Verilog_RTL_sim/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v | 2 +- .../Verilog_RTL_sim/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkITlb.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v | 2 +- .../Verilog_RTL_sim/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v | 2 +- .../Verilog_RTL_sim/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v | 2 +- .../Verilog_RTL_sim/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v | 2 +- .../Verilog_RTL_sim/mkNullTransCache.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkProc.v | 2859 ++++++----- src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkRas.v | 2 +- .../Verilog_RTL_sim/mkRegRenamingTable.v | 2 +- .../Verilog_RTL_sim/mkReorderBufferSynth.v | 2 +- .../Verilog_RTL_sim/mkReservationStationAlu.v | 2 +- .../mkReservationStationFpuMulDiv.v | 2 +- .../Verilog_RTL_sim/mkReservationStationMem.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v | 2 +- .../Verilog_RTL_sim/mkScoreboardAggr.v | 2 +- .../Verilog_RTL_sim/mkScoreboardCons.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v | 2 +- .../Verilog_RTL_sim/mkSpecTagManager.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v | 2 +- .../Verilog_RTL_sim/mkSplitTransCache.v | 2 +- .../Verilog_RTL_sim/mkStoreBufferEhr.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v | 2 +- .../Verilog_RTL_sim/mkTourPredSecure.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_alu.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v | 2 +- .../Verilog_RTL_sim/module_basicExec.v | 2 +- .../Verilog_RTL_sim/module_brAddrCalc.v | 2 +- .../Verilog_RTL_sim/module_capChecks.v | 2 +- .../Verilog_RTL_sim/module_capInspect.v | 2 +- .../Verilog_RTL_sim/module_capModify.v | 2 +- .../module_checkForException.v | 2 +- src_SSITH_P3/Verilog_RTL_sim/module_decode.v | 2 +- .../Verilog_RTL_sim/module_decodeBrPred.v | 2 +- .../Verilog_RTL_sim/module_execFpuSimple.v | 2 +- .../module_prepareBoundsCheck.v | 2 +- .../Verilog_RTL_sim/module_setBoundsALU.v | 2 +- .../Verilog_RTL_sim/module_specialRWALU.v | 2 +- .../xilinx_ip/hdl/mkAluDispToRegFifo.v | 2 +- .../xilinx_ip/hdl/mkAluExeToFinFifo.v | 2 +- .../xilinx_ip/hdl/mkAluRegToExeFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkBht.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkCore.v | 4536 ++++++++--------- src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v | 2 +- .../xilinx_ip/hdl/mkDCRqMshrWrapper.v | 2 +- .../xilinx_ip/hdl/mkDM_Abstract_Commands.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v | 2 +- .../xilinx_ip/hdl/mkDPRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v | 2 +- .../xilinx_ip/hdl/mkDummyStoreBuffer.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v | 2 +- .../xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v | 2 +- .../xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v | 2 +- .../xilinx_ip/hdl/mkGSelectGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v | 2 +- .../xilinx_ip/hdl/mkICRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v | 2 +- .../xilinx_ip/hdl/mkIPRqMshrWrapper.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkITlb.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v | 2 +- .../xilinx_ip/hdl/mkMemDispToRegFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v | 2 +- .../xilinx_ip/hdl/mkMemRegToExeFifo.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkProc.v | 2851 ++++++----- src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkRas.v | 2 +- .../xilinx_ip/hdl/mkRegRenamingTable.v | 2 +- .../xilinx_ip/hdl/mkReorderBufferSynth.v | 2 +- .../xilinx_ip/hdl/mkReservationStationAlu.v | 2 +- .../hdl/mkReservationStationFpuMulDiv.v | 2 +- .../xilinx_ip/hdl/mkReservationStationMem.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v | 2 +- .../xilinx_ip/hdl/mkSplitTransCache.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_alu.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v | 2 +- .../xilinx_ip/hdl/module_brAddrCalc.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v | 2 +- .../xilinx_ip/hdl/module_capInspect.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_capModify.v | 2 +- .../xilinx_ip/hdl/module_checkForException.v | 2 +- src_SSITH_P3/xilinx_ip/hdl/module_decode.v | 2 +- .../xilinx_ip/hdl/module_decodeBrPred.v | 2 +- .../xilinx_ip/hdl/module_execFpuSimple.v | 2 +- .../xilinx_ip/hdl/module_prepareBoundsCheck.v | 2 +- .../xilinx_ip/hdl/module_setBoundsALU.v | 2 +- .../xilinx_ip/hdl/module_specialRWALU.v | 2 +- 252 files changed, 11317 insertions(+), 11224 deletions(-) diff --git a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v index 8168e5e..289231a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:11:05 BST 2020 +// On Mon Jul 6 19:24:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v index 8aa1b42..22e001b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:11:06 BST 2020 +// On Mon Jul 6 19:24:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v index 55ce50e..89c08ff 100644 --- a/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:11:05 BST 2020 +// On Mon Jul 6 19:24:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkBht.v b/src_SSITH_P3/Verilog_RTL/mkBht.v index 201d36e..c86db34 100644 --- a/src_SSITH_P3/Verilog_RTL/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:07 BST 2020 +// On Mon Jul 6 19:23:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 9839e9a..9405d27 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:12:07 BST 2020 +// On Mon Jul 6 19:25:12 BST 2020 // // // Ports: @@ -3721,17 +3721,17 @@ module mkCore(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h213411; - reg [63 : 0] v__h215680; - reg [63 : 0] v__h271938; - reg [63 : 0] v__h347456; - reg [63 : 0] v__h423782; + reg [63 : 0] v__h213412; + reg [63 : 0] v__h215681; + reg [63 : 0] v__h271939; + reg [63 : 0] v__h347457; + reg [63 : 0] v__h423783; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5488; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891; - reg [65 : 0] thin_address__h858472, thin_address__h899107; + reg [65 : 0] thin_address__h858470, thin_address__h899110; reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, @@ -3770,12 +3770,12 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151, - addr__h505614, - addr__h843948, - addr__h887458, - data_out__h1020024, - trap_val__h996922, - x__h264730; + addr__h505615, + addr__h843947, + addr__h887460, + data_out__h1020028, + trap_val__h996926, + x__h264732; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32, @@ -3810,7 +3810,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17257; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040, - x__h264885; + x__h264887; reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, @@ -3862,16 +3862,16 @@ module mkCore(CLK, _theResult___fst_sfd__h703056; reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, - thin_otype__h858477, - thin_otype__h899112; + thin_otype__h858475, + thin_otype__h899115; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052; - reg [13 : 0] thin_addrBits__h858473, - thin_addrBits__h899108, - thin_bounds_baseBits__h860421, - thin_bounds_baseBits__h900514, - thin_bounds_topBits__h860420, - thin_bounds_topBits__h900513; + reg [13 : 0] thin_addrBits__h858471, + thin_addrBits__h899111, + thin_bounds_baseBits__h860419, + thin_bounds_baseBits__h900517, + thin_bounds_topBits__h860418, + thin_bounds_topBits__h900516; reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341, CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328; @@ -3990,10 +3990,10 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332, IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d22045, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22190, - cause_code__h995318, - i__h995334, - t__h212839, - t__h215125; + cause_code__h995322, + i__h995338, + t__h212840, + t__h215126; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q248, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q250, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q246, @@ -4019,9 +4019,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_236_ETC___d21371, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22191, IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478, - i__h995534, - thin_perms_soft__h858712, - thin_perms_soft__h899287; + i__h995538, + thin_perms_soft__h858710, + thin_perms_soft__h899290; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q245, @@ -4051,15 +4051,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868, IF_fetchStage_pipelines_0_first__0256_BITS_232_ETC___d20442, IF_fetchStage_pipelines_1_first__0265_BITS_232_ETC___d21403, - x__h501096, - x__h508764; + x__h501097, + x__h508765; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, - thin_reserved__h858476, - thin_reserved__h899111; + thin_reserved__h858474, + thin_reserved__h899114; reg CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277, CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, @@ -4141,7 +4141,7 @@ module mkCore(CLK, CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19249, @@ -4272,20 +4272,20 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5560; wire [128 : 0] amoExec___d4922, amoExec___d773, - new_pc__h872924, - new_pc__h912071, - next_pc__h1012257, - pc__h963240, - v__h1012296, - v__h1013005, - x__h879902, - x__h914618; + new_pc__h872923, + new_pc__h912075, + next_pc__h1012261, + pc__h963244, + v__h1012300, + v__h1013009, + x__h879901, + x__h914622; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5165, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889, coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070, - x__h183397, - x__h199249; + x__h183398, + x__h199250; wire [109 : 0] IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, IF_fetchStage_pipelines_1_first__0265_BITS_238_ETC___d21583; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580; @@ -4311,91 +4311,91 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3417, - addTop__h239970, - addTop__h241127, - addTop__h254751, - address__h1000186, - address__h1000530, - address__h999529, - address__h999873, + addTop__h239972, + addTop__h241129, + addTop__h254753, + address__h1000190, + address__h1000534, + address__h999533, + address__h999877, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704, - cr_address__h866670, - cr_address__h867218, - cr_address__h906355, - cr_address__h906903, - data_address__h1018751, - data_address__h1019605, - in__h239801, - in__h240958, - in__h254582, - in__h854153, - in__h854458, - in__h855146, - in__h855450, - in__h855976, - in__h997691, - pc_address__h994737, - pointer__h242635, + cr_address__h866668, + cr_address__h867216, + cr_address__h906358, + cr_address__h906906, + data_address__h1018755, + data_address__h1019609, + in__h239803, + in__h240960, + in__h254584, + in__h854151, + in__h854456, + in__h855144, + in__h855448, + in__h855974, + in__h997695, + pc_address__h994741, + pointer__h242637, res_address__h126821, res_address__h139733, - res_address__h178896, - res_address__h197661, - res_address__h216420, - res_address__h235320, - res_address__h567343, + res_address__h178897, + res_address__h197662, + res_address__h216421, + res_address__h235322, + res_address__h567344, res_address__h568196, res_address__h613953, res_address__h659700, res_address__h705509, res_address__h706369, - res_address__h848642, - res_address__h892144, - result__h240597, - result__h241754, - result__h255378, - result_d_address__h1008601, - result_d_address__h1009004, - result_d_address__h1009421, - result_d_address__h1009824, - result_d_address__h1010493, - result_d_address__h1031651, - result_d_address__h1032054, - result_d_address__h1032471, - result_d_address__h1032874, - result_d_address__h1033541, - result_d_address__h242846, - ret__h239974, - ret__h241131, - ret__h254755, - x__h1000027, - x__h1000380, - x__h1000684, - x__h235743, - x__h239819, - x__h239967, - x__h240976, - x__h241124, - x__h248117, - x__h254600, - x__h254748, - x__h854171, - x__h854476, - x__h855164, - x__h855468, - x__h855994, - x__h997709, - x__h999723, - y__h239818, - y__h240975, - y__h254599, - y__h854170, - y__h854475, - y__h855163, - y__h855467, - y__h855993, - y__h997708; + res_address__h848641, + res_address__h892146, + result__h240599, + result__h241756, + result__h255380, + result_d_address__h1008605, + result_d_address__h1009008, + result_d_address__h1009425, + result_d_address__h1009828, + result_d_address__h1010497, + result_d_address__h1031655, + result_d_address__h1032058, + result_d_address__h1032475, + result_d_address__h1032878, + result_d_address__h1033545, + result_d_address__h242848, + ret__h239976, + ret__h241133, + ret__h254757, + x__h1000031, + x__h1000384, + x__h1000688, + x__h235745, + x__h239821, + x__h239969, + x__h240978, + x__h241126, + x__h248119, + x__h254602, + x__h254750, + x__h854169, + x__h854474, + x__h855162, + x__h855466, + x__h855992, + x__h997713, + x__h999727, + y__h239820, + y__h240977, + y__h254601, + y__h854168, + y__h854473, + y__h855161, + y__h855465, + y__h855991, + y__h997712; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13324, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12485, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12486, @@ -4431,31 +4431,31 @@ module mkCore(CLK, a___1__h835845, a___1__h836131, a__h835704, - addBase__h1008620, - addBase__h1009023, - addBase__h1009440, - addBase__h1009843, - addBase__h1010513, - addBase__h239861, - addBase__h241018, - addBase__h254642, + addBase__h1008624, + addBase__h1009027, + addBase__h1009444, + addBase__h1009847, + addBase__h1010517, + addBase__h239863, + addBase__h241020, + addBase__h254644, addr__h148438, addr__h152014, - addr__h235314, - addr__h989734, - address__h1013717, - address__h999463, - address__h999513, + addr__h235316, + addr__h989738, + address__h1013721, + address__h999467, + address__h999517, b___1__h835846, b___1__h836176, b__h835705, - base__h999424, - base__h999478, - bot__h1008623, - bot__h1009026, - bot__h1009443, - bot__h1009846, - bot__h1010516, + base__h999428, + base__h999482, + bot__h1008627, + bot__h1009030, + bot__h1009447, + bot__h1009850, + bot__h1010520, csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816, csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745, data___1__h705531, @@ -4466,25 +4466,25 @@ module mkCore(CLK, data__h704999, data__h705831, data__h705862, - fcsr_csr__read__h849218, - fflags_csr__read__h849193, - frm_csr__read__h849204, - mask__h1000192, - mask__h999535, - mcause_csr__read__h850885, - mcounteren_csr__read__h850619, - medeleg_csr__read__h850222, - mideleg_csr__read__h850320, - mie_csr__read__h850447, - mip_csr__read__h851124, - mstatus_csr__read__h850061, - n__read__h1014147, + fcsr_csr__read__h849216, + fflags_csr__read__h849191, + frm_csr__read__h849202, + mask__h1000196, + mask__h999539, + mcause_csr__read__h850883, + mcounteren_csr__read__h850617, + medeleg_csr__read__h850220, + mideleg_csr__read__h850318, + mie_csr__read__h850445, + mip_csr__read__h851122, + mstatus_csr__read__h850059, + n__read__h1014151, n__read__h7908, - newAddrDiff__h1000193, - newAddrDiff__h1000537, - newAddrDiff__h999536, - newAddrDiff__h999880, - offset__h242625, + newAddrDiff__h1000197, + newAddrDiff__h1000541, + newAddrDiff__h999540, + newAddrDiff__h999884, + offset__h242627, q___1__h706456, rVal1__h714517, rVal2__h714518, @@ -4495,134 +4495,134 @@ module mkCore(CLK, res_data__h613995, res_data__h659737, res_data__h659742, - resp_addr__h509110, - rg_tdata1__read__h852225, + resp_addr__h509111, + rg_tdata1__read__h852223, robdeqPort_0_deq_data_BITS_95_TO_32__q17, - satp_csr__read__h849915, - scause_csr__read__h849712, - scounteren_csr__read__h849572, - sie_csr__read__h849484, - sip_csr__read__h849852, - sstatus_csr__read__h849414, - thin_address__h999417, - tmpAddr__h242834, - trap_val__h997075, - upd__h1014223, + satp_csr__read__h849913, + scause_csr__read__h849710, + scounteren_csr__read__h849570, + sie_csr__read__h849482, + sip_csr__read__h849850, + sstatus_csr__read__h849412, + thin_address__h999421, + tmpAddr__h242836, + trap_val__h997079, + upd__h1014227, upd__h3066, upd__h3676, upd__h7977, - value__h239691, - value__h239855, - value__h240848, - value__h241012, - value__h254472, - value__h254636, - x__h1008531, - x__h1008934, - x__h1009351, - x__h1009754, - x__h1010423, - x__h1031581, - x__h1031984, - x__h1032401, - x__h1032804, - x__h1033471, + value__h239693, + value__h239857, + value__h240850, + value__h241014, + value__h254474, + value__h254638, + x__h1008535, + x__h1008938, + x__h1009355, + x__h1009758, + x__h1010427, + x__h1031585, + x__h1031988, + x__h1032405, + x__h1032808, + x__h1033475, x__h127302, x__h140218, - x__h183479, - x__h202230, - x__h216796, - x__h239709, + x__h183480, + x__h202231, + x__h216797, x__h239711, - x__h240866, + x__h239713, x__h240868, - x__h242774, - x__h254490, + x__h240870, + x__h242776, x__h254492, + x__h254494, x__h714426, x__h714427, x__h714428, + x__h854230, x__h854232, - x__h854234, + x__h855223, x__h855225, - x__h855227, - x__h866847, - x__h867395, - x__h895986, - x__h895988, - x__h896270, - x__h896272, - x__h896615, - x__h896617, - x__h906532, - x__h907080, - x__h994909, - x__h997622, - x__h997624, + x__h866845, + x__h867393, + x__h895989, + x__h895991, + x__h896273, + x__h896275, + x__h896618, + x__h896620, + x__h906535, + x__h907083, + x__h994913, + x__h997626, + x__h997628, x_addr__h19883, x_addr__h44252, - x_addr__h535372, + x_addr__h535373, x_quotient__h705745, - x_reg_ifc__read__h849323, + x_reg_ifc__read__h849321, x_remainder__h705746, - y__h1000309, - y__h1016374, - y__h999652, + y__h1000313, + y__h1016378, + y__h999656, y_avValue__h710472, y_avValue__h711105, y_avValue__h711732, - y_avValue_snd_snd_snd_snd_snd__h1015845, - y_avValue_snd_snd_snd_snd_snd__h1016427, - y_avValue_snd_snd_snd_snd_snd__h1016456; + y_avValue_snd_snd_snd_snd_snd__h1015849, + y_avValue_snd_snd_snd_snd_snd__h1016431, + y_avValue_snd_snd_snd_snd_snd__h1016460; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14033, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803, - r1__read__h853106, + r1__read__h853104, + r1__read__h853508, + r1__read__h854201, + r1__read__h854513, + r1__read__h854746, + r1__read__h854918, + r1__read__h855194, + r1__read__h855505; + wire [61 : 0] r1__read__h853106, r1__read__h853510, r1__read__h854203, r1__read__h854515, r1__read__h854748, + r1__read__h854894, r1__read__h854920, r1__read__h855196, r1__read__h855507; - wire [61 : 0] r1__read__h853108, - r1__read__h853512, - r1__read__h854205, - r1__read__h854517, - r1__read__h854750, + wire [60 : 0] r1__read__h854750, r1__read__h854896, r1__read__h854922, - r1__read__h855198, r1__read__h855509; - wire [60 : 0] r1__read__h854752, - r1__read__h854898, + wire [59 : 0] r1__read__h853108, + r1__read__h853512, + r1__read__h854517, + r1__read__h854752, r1__read__h854924, r1__read__h855511; - wire [59 : 0] r1__read__h853110, + wire [58 : 0] r1__read__h853110, r1__read__h853514, + r1__read__h854506, r1__read__h854519, r1__read__h854754, r1__read__h854926, + r1__read__h855498, r1__read__h855513; - wire [58 : 0] r1__read__h853112, - r1__read__h853516, - r1__read__h854508, - r1__read__h854521, - r1__read__h854756, - r1__read__h854928, - r1__read__h855500, - r1__read__h855515; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5496, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5538, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7211, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6974, - r1__read__h853114, - r1__read__h853518, - r1__read__h854523, - r1__read__h854758, - r1__read__h854900, - r1__read__h854930, - r1__read__h855517, - y__h422564; + r1__read__h853112, + r1__read__h853516, + r1__read__h854521, + r1__read__h854756, + r1__read__h854898, + r1__read__h854928, + r1__read__h855515, + y__h422565; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75, @@ -4767,10 +4767,10 @@ module mkCore(CLK, _theResult___snd__h830811, _theResult___snd__h830817, _theResult___snd__h830835, - r1__read__h854760, - r1__read__h854902, - r1__read__h854932, - r1__read__h855519, + r1__read__h854758, + r1__read__h854900, + r1__read__h854930, + r1__read__h855517, result__h594704, result__h640453, result__h686200, @@ -4799,24 +4799,24 @@ module mkCore(CLK, x__h775186, x__h814490; wire [55 : 0] coreFix_memExe_dispToRegQ_first__686_BIT_102_6_ETC___d3579, + r1__read__h853114, + r1__read__h853518, + r1__read__h854523, + r1__read__h854760, + r1__read__h854932, + r1__read__h855519; + wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394, + IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260, r1__read__h853116, r1__read__h853520, r1__read__h854525, r1__read__h854762, r1__read__h854934, r1__read__h855521; - wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394, - IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260, - r1__read__h853118, - r1__read__h853522, - r1__read__h854527, - r1__read__h854764, + wire [53 : 0] r1__read__h854871, + r1__read__h854902, r1__read__h854936, - r1__read__h855523; - wire [53 : 0] r1__read__h854873, - r1__read__h854904, - r1__read__h854938, - r1__read__h855525, + r1__read__h855523, sfd__h734302, sfd__h743953, sfd__h752713, @@ -4834,11 +4834,11 @@ module mkCore(CLK, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719, - r1__read__h854766, - r1__read__h854875, - r1__read__h854906, - r1__read__h854940, - r1__read__h855527; + r1__read__h854764, + r1__read__h854873, + r1__read__h854904, + r1__read__h854938, + r1__read__h855525; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000, @@ -4905,9 +4905,9 @@ module mkCore(CLK, _theResult___snd_fst_sfd__h793510, _theResult___snd_fst_sfd__h813203, _theResult___snd_fst_sfd__h831638, - mask__h239971, - mask__h241128, - mask__h254752, + mask__h239973, + mask__h241130, + mask__h254754, out___1_sfd__h714960, out___1_sfd__h753954, out___1_sfd__h793258, @@ -4920,47 +4920,47 @@ module mkCore(CLK, out_sfd__h813100, out_sfd__h822751, out_sfd__h831535; - wire [50 : 0] r1__read__h853120, r1__read__h854768; - wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, - coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5, + wire [50 : 0] r1__read__h853118, r1__read__h854766; + wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5, + coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3, - highBitsfilter__h1008407, - highBitsfilter__h1008810, - highBitsfilter__h1009227, - highBitsfilter__h1009630, - highBitsfilter__h1010299, - highOffsetBits__h1008408, - highOffsetBits__h1008811, - highOffsetBits__h1009228, - highOffsetBits__h1009631, - highOffsetBits__h1010300, - highOffsetBits__h1031458, - highOffsetBits__h1031861, - highOffsetBits__h1032278, - highOffsetBits__h1032681, - highOffsetBits__h1033348, - highOffsetBits__h242644, - mask__h239862, - mask__h241019, - mask__h254643, - r1__read__h854877, - signBits__h1008405, - signBits__h1031455, - signBits__h242641, - x__h1008435, - x__h1031485, - x__h242671; - wire [48 : 0] r1__read__h853122, r1__read__h854770, r1__read__h854879; - wire [47 : 0] r1__read__h854881; - wire [46 : 0] r1__read__h853124, r1__read__h854772; - wire [45 : 0] r1__read__h853126, r1__read__h854774; - wire [44 : 0] r1__read__h853128, r1__read__h854776; - wire [43 : 0] r1__read__h853130, r1__read__h854778; - wire [42 : 0] r1__read__h854780; - wire [41 : 0] r1__read__h854782; - wire [40 : 0] r1__read__h854784; + highBitsfilter__h1008411, + highBitsfilter__h1008814, + highBitsfilter__h1009231, + highBitsfilter__h1009634, + highBitsfilter__h1010303, + highOffsetBits__h1008412, + highOffsetBits__h1008815, + highOffsetBits__h1009232, + highOffsetBits__h1009635, + highOffsetBits__h1010304, + highOffsetBits__h1031462, + highOffsetBits__h1031865, + highOffsetBits__h1032282, + highOffsetBits__h1032685, + highOffsetBits__h1033352, + highOffsetBits__h242646, + mask__h239864, + mask__h241021, + mask__h254645, + r1__read__h854875, + signBits__h1008409, + signBits__h1031459, + signBits__h242643, + x__h1008439, + x__h1031489, + x__h242673; + wire [48 : 0] r1__read__h853120, r1__read__h854768, r1__read__h854877; + wire [47 : 0] r1__read__h854879; + wire [46 : 0] r1__read__h853122, r1__read__h854770; + wire [45 : 0] r1__read__h853124, r1__read__h854772; + wire [44 : 0] r1__read__h853126, r1__read__h854774; + wire [43 : 0] r1__read__h853128, r1__read__h854776; + wire [42 : 0] r1__read__h854778; + wire [41 : 0] r1__read__h854780; + wire [40 : 0] r1__read__h854782; wire [38 : 0] IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878; - wire [37 : 0] r1__read__h854883; + wire [37 : 0] r1__read__h854881; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954, IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210, @@ -4985,15 +4985,15 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15, data05831_BITS_31_TO_0__q26, - r1__read__h853132, - r1__read__h854786, + r1__read__h853130, + r1__read__h854784, x__h568251, x__h614005, x__h65639, x__h659752, x_data__h60140; - wire [29 : 0] r1__read__h853134, r1__read__h854788; - wire [27 : 0] r1__read__h854790; + wire [29 : 0] r1__read__h853132, r1__read__h854786; + wire [27 : 0] r1__read__h854788; wire [25 : 0] IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142, @@ -5102,7 +5102,7 @@ module mkCore(CLK, out_sfd__h685161, out_sfd__h694345, out_sfd__h702981; - wire [19 : 0] r1__read__h854725; + wire [19 : 0] r1__read__h854723; wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q16, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, @@ -5111,8 +5111,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, - INV_x83397_BITS_108_TO_90__q34, - INV_x99249_BITS_108_TO_90__q36; + INV_x83398_BITS_108_TO_90__q34, + INV_x99250_BITS_108_TO_90__q36; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19042, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19043, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16647, @@ -5129,43 +5129,43 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3559; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3536, - _theResult____h920230, - base__h239696, - base__h240853, - base__h254477, - base__h854219, - base__h855212, - base__h895973, - base__h896257, - base__h896602, - base__h997609, - enabled_ints___1__h920755, - enabled_ints__h920801, - newAddrBits__h1008590, - newAddrBits__h1008993, - newAddrBits__h1009410, - newAddrBits__h1009813, - newAddrBits__h1010482, - newAddrBits__h1031640, - newAddrBits__h1032043, - newAddrBits__h1032460, - newAddrBits__h1032863, - newAddrBits__h1033530, - offset__h239697, - offset__h240854, - offset__h254478, - offset__h854220, - offset__h855213, - offset__h895974, - offset__h896258, - offset__h896603, - offset__h997610, - pend_ints__h920228, - x__h240069, - x__h241226, - x__h254850, - x__h896540, - y__h920767; + _theResult____h920234, + base__h239698, + base__h240855, + base__h254479, + base__h854217, + base__h855210, + base__h895976, + base__h896260, + base__h896605, + base__h997613, + enabled_ints___1__h920759, + enabled_ints__h920805, + newAddrBits__h1008594, + newAddrBits__h1008997, + newAddrBits__h1009414, + newAddrBits__h1009817, + newAddrBits__h1010486, + newAddrBits__h1031644, + newAddrBits__h1032047, + newAddrBits__h1032464, + newAddrBits__h1032867, + newAddrBits__h1033534, + offset__h239699, + offset__h240856, + offset__h254480, + offset__h854218, + offset__h855211, + offset__h895977, + offset__h896261, + offset__h896606, + offset__h997614, + pend_ints__h920232, + x__h240071, + x__h241228, + x__h254852, + x__h896543, + y__h920771; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18828, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18829, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16433, @@ -5189,83 +5189,83 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3425, b_base__h127527, b_base__h140443, - b_base__h183704, - b_base__h202455, - b_base__h217021, - b_base__h867085, - b_base__h867633, - b_base__h906770, - b_base__h907318, - b_base__h995134, + b_base__h183705, + b_base__h202456, + b_base__h217022, + b_base__h867083, + b_base__h867631, + b_base__h906773, + b_base__h907321, + b_base__h995138, checkForException___d20654, checkForException___d21604, - cr_addrBits__h866671, - cr_addrBits__h867219, - cr_addrBits__h906356, - cr_addrBits__h906904, - data_addrBits__h1018752, - data_addrBits__h1019606, - pc_addrBits__h994738, - r1__read_BITS_13_TO_0___h920777, - repBoundBits__h242650, + cr_addrBits__h866669, + cr_addrBits__h867217, + cr_addrBits__h906359, + cr_addrBits__h906907, + data_addrBits__h1018756, + data_addrBits__h1019610, + pc_addrBits__h994742, + r1__read_BITS_13_TO_0___h920781, + repBoundBits__h242652, res_addrBits__h126822, res_addrBits__h139734, - res_addrBits__h178897, - res_addrBits__h197662, - res_addrBits__h216421, - res_addrBits__h235321, - res_addrBits__h567344, + res_addrBits__h178898, + res_addrBits__h197663, + res_addrBits__h216422, + res_addrBits__h235323, + res_addrBits__h567345, res_addrBits__h568197, res_addrBits__h613954, res_addrBits__h659701, res_addrBits__h705510, res_addrBits__h706370, - res_addrBits__h848643, - res_addrBits__h892145, - result_d_addrBits__h1008602, - result_d_addrBits__h1009005, - result_d_addrBits__h1009422, - result_d_addrBits__h1009825, - result_d_addrBits__h1010494, - result_d_addrBits__h1031652, - result_d_addrBits__h1032055, - result_d_addrBits__h1032472, - result_d_addrBits__h1032875, - result_d_addrBits__h1033542, - toBoundsM1__h1008418, - toBoundsM1__h1008821, - toBoundsM1__h1009238, - toBoundsM1__h1009641, - toBoundsM1__h1010310, - toBoundsM1__h242654, - toBounds__h1008417, - toBounds__h1008820, - toBounds__h1009237, - toBounds__h1009640, - toBounds__h1010309, - toBounds__h242653, - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922, - x__h1000919, + res_addrBits__h848642, + res_addrBits__h892147, + result_d_addrBits__h1008606, + result_d_addrBits__h1009009, + result_d_addrBits__h1009426, + result_d_addrBits__h1009829, + result_d_addrBits__h1010498, + result_d_addrBits__h1031656, + result_d_addrBits__h1032059, + result_d_addrBits__h1032476, + result_d_addrBits__h1032879, + result_d_addrBits__h1033546, + toBoundsM1__h1008422, + toBoundsM1__h1008825, + toBoundsM1__h1009242, + toBoundsM1__h1009645, + toBoundsM1__h1010314, + toBoundsM1__h242656, + toBounds__h1008421, + toBounds__h1008824, + toBounds__h1009241, + toBounds__h1009644, + toBounds__h1010313, + toBounds__h242655, + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926, + x__h1000923, x__h127500, x__h127520, x__h140416, x__h140436, - x__h183677, - x__h183697, - x__h202428, - x__h202448, - x__h216994, - x__h217014, - x__h867058, - x__h867078, - x__h867606, - x__h867626, - x__h906743, - x__h906763, - x__h907291, - x__h907311, - x__h995107, - x__h995127; + x__h183678, + x__h183698, + x__h202429, + x__h202449, + x__h216995, + x__h217015, + x__h867056, + x__h867076, + x__h867604, + x__h867624, + x__h906746, + x__h906766, + x__h907294, + x__h907314, + x__h995111, + x__h995131; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__257_BIT_27_ETC___d4757, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20987, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20988, @@ -5303,43 +5303,43 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677, b_top__h127526, b_top__h140442, - b_top__h183703, - b_top__h202454, - b_top__h217020, - b_top__h867084, - b_top__h867632, - b_top__h906769, - b_top__h907317, - b_top__h995133, + b_top__h183704, + b_top__h202455, + b_top__h217021, + b_top__h867082, + b_top__h867630, + b_top__h906772, + b_top__h907320, + b_top__h995137, capChecks___d4160, - renaming_spec_bits__h968739, - result__h915808, - result__h915859, - spec_bits__h973790, + renaming_spec_bits__h968743, + result__h915812, + result__h915863, + spec_bits__h973794, topBits__h127429, topBits__h140345, - topBits__h183606, - topBits__h202357, - topBits__h216923, - topBits__h866986, - topBits__h867534, - topBits__h906671, - topBits__h907219, - topBits__h995036, - w__h915803, + topBits__h183607, + topBits__h202358, + topBits__h216924, + topBits__h866984, + topBits__h867532, + topBits__h906674, + topBits__h907222, + topBits__h995040, + w__h915807, x__h594834, x__h640583, x__h686330, x__h736366, x__h775219, x__h814523, - x__h915807, - x__h915858, - y__h915837, - y__h973803, - y_avValue_snd_fst__h963383, - y_avValue_snd_fst__h963425, - y_avValue_snd_fst__h963467; + x__h915811, + x__h915862, + y__h915841, + y__h973807, + y_avValue_snd_fst__h963387, + y_avValue_snd_fst__h963429, + y_avValue_snd_fst__h963471; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917, @@ -5459,7 +5459,7 @@ module mkCore(CLK, out_exp__h813099, out_exp__h822750, out_exp__h831534, - x__h998896; + x__h998900; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3635; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789, @@ -5632,11 +5632,11 @@ module mkCore(CLK, out_f_exp__h611860, out_f_exp__h657609, out_f_exp__h703356, - x__h853091; + x__h853089; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320, - x__h244675, - x__h999622; + x__h244677, + x__h999626; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767, @@ -5665,19 +5665,19 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476, fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d20616, fetchStage_pipelines_1_first__0265_BIT_167_155_ETC___d21577, - x__h1000253, - x__h1000940, + x__h1000257, + x__h1000944, x__h127340, x__h140256, - x__h183517, - x__h202268, - x__h216834, - x__h866885, - x__h867433, - x__h906570, - x__h907118, - x__h994947, - x__h999596; + x__h183518, + x__h202269, + x__h216835, + x__h866883, + x__h867431, + x__h906573, + x__h907121, + x__h994951, + x__h999600; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20090, IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20091, IF_IF_coreFix_aluExe_1_exeToFinQ_first__7830_B_ETC___d17975, @@ -5720,11 +5720,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10706, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12103, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9309, - cause_code__h996893, + cause_code__h996897, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156, - fflags__h1016351, - r1__read__h855836, + fflags__h1016355, + r1__read__h855834, res_fflags__h568237, res_fflags__h613991, res_fflags__h659738, @@ -5732,39 +5732,39 @@ module mkCore(CLK, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786, x__h148990, x__h152124, - x__h249475, - x__h249487, - x__h249499, - x__h249511, - x__h249523, - x__h249535, - x__h249547, - x__h249559, - x__h249571, - x__h249583, - x__h249595, - x__h249607, - x__h249619, - x__h249631, - x__h249643, - y__h249476, - y__h249488, - y__h249500, - y__h249512, - y__h249524, - y__h249536, - y__h249548, - y__h249560, - y__h249572, - y__h249584, - y__h249596, - y__h249608, - y__h249620, - y__h249632, - y__h249644, - y_avValue_snd_fst__h1015829, - y_avValue_snd_fst__h1016411, - y_avValue_snd_fst__h1016440; + x__h249477, + x__h249489, + x__h249501, + x__h249513, + x__h249525, + x__h249537, + x__h249549, + x__h249561, + x__h249573, + x__h249585, + x__h249597, + x__h249609, + x__h249621, + x__h249633, + x__h249645, + y__h249478, + y__h249490, + y__h249502, + y__h249514, + y__h249526, + y__h249538, + y__h249550, + y__h249562, + y__h249574, + y__h249586, + y__h249598, + y__h249610, + y__h249622, + y__h249634, + y__h249646, + y_avValue_snd_fst__h1015833, + y_avValue_snd_fst__h1016415, + y_avValue_snd_fst__h1016444; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8383__ETC___d19433, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5620__ETC___d17317, IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20977, @@ -5809,7 +5809,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3390, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3433, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3632, - vm_mode_reg__read__h854731; + vm_mode_reg__read__h854729; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19088, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16693, @@ -5826,57 +5826,57 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7096, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409, - _theResult_____2__h515366, - dcsr_cause__h994362, - next_deqP___1__h515611, - repBound__h237315, - repBound__h239000, - repBound__h248215, - repBound__h248740, - repBound__h854075, - repBound__h854397, - repBound__h855068, - repBound__h855389, - repBound__h855898, - repBound__h857576, - repBound__h860538, - repBound__h860556, - repBound__h867139, - repBound__h867687, - repBound__h898284, - repBound__h900611, - repBound__h900629, - repBound__h906824, - repBound__h907372, - repBound__h997634, - tb__h867136, - tb__h867684, - tb__h906821, - tb__h907369, + _theResult_____2__h515367, + dcsr_cause__h994366, + next_deqP___1__h515612, + repBound__h237317, + repBound__h239002, + repBound__h248217, + repBound__h248742, + repBound__h854073, + repBound__h854395, + repBound__h855066, + repBound__h855387, + repBound__h855896, + repBound__h857574, + repBound__h860536, + repBound__h860554, + repBound__h867137, + repBound__h867685, + repBound__h898287, + repBound__h900614, + repBound__h900632, + repBound__h906827, + repBound__h907375, + repBound__h997638, + tb__h867134, + tb__h867682, + tb__h906824, + tb__h907372, tmp_expBotHalf__h127295, tmp_expBotHalf__h140211, - tmp_expBotHalf__h183472, - tmp_expBotHalf__h202223, - tmp_expBotHalf__h216789, - tmp_expBotHalf__h866839, - tmp_expBotHalf__h867387, - tmp_expBotHalf__h906524, - tmp_expBotHalf__h907072, - tmp_expBotHalf__h994902, + tmp_expBotHalf__h183473, + tmp_expBotHalf__h202224, + tmp_expBotHalf__h216790, + tmp_expBotHalf__h866837, + tmp_expBotHalf__h867385, + tmp_expBotHalf__h906527, + tmp_expBotHalf__h907075, + tmp_expBotHalf__h994906, tmp_expTopHalf__h127293, tmp_expTopHalf__h140209, - tmp_expTopHalf__h183470, - tmp_expTopHalf__h202221, - tmp_expTopHalf__h216787, - tmp_expTopHalf__h866837, - tmp_expTopHalf__h867385, - tmp_expTopHalf__h906522, - tmp_expTopHalf__h907070, - tmp_expTopHalf__h994900, - v__h514822, - v__h515017, - x__h521673, - x_decodeInfo_frm__h926246; + tmp_expTopHalf__h183471, + tmp_expTopHalf__h202222, + tmp_expTopHalf__h216788, + tmp_expTopHalf__h866835, + tmp_expTopHalf__h867383, + tmp_expTopHalf__h906525, + tmp_expTopHalf__h907073, + tmp_expTopHalf__h994904, + v__h514823, + v__h515018, + x__h521674, + x_decodeInfo_frm__h926250; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19029, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19030, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16634, @@ -5915,21 +5915,21 @@ module mkCore(CLK, IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43, carry_out__h127431, carry_out__h140347, - carry_out__h183608, - carry_out__h202359, - carry_out__h216925, - carry_out__h866988, - carry_out__h867536, - carry_out__h906673, - carry_out__h907221, - carry_out__h995038, - coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, + carry_out__h183609, + carry_out__h202360, + carry_out__h216926, + carry_out__h866986, + carry_out__h867534, + carry_out__h906676, + carry_out__h907224, + carry_out__h995042, + coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2, - coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4, - cr_reserved__h866674, - cr_reserved__h867222, - cr_reserved__h906359, - cr_reserved__h906907, + coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6, + cr_reserved__h866672, + cr_reserved__h867220, + cr_reserved__h906362, + cr_reserved__h906910, guard__h576462, guard__h585171, guard__h594101, @@ -5953,47 +5953,47 @@ module mkCore(CLK, guard__h822861, impliedTopBits__h127433, impliedTopBits__h140349, - impliedTopBits__h183610, - impliedTopBits__h202361, - impliedTopBits__h216927, - impliedTopBits__h866990, - impliedTopBits__h867538, - impliedTopBits__h906675, - impliedTopBits__h907223, - impliedTopBits__h995040, + impliedTopBits__h183611, + impliedTopBits__h202362, + impliedTopBits__h216928, + impliedTopBits__h866988, + impliedTopBits__h867536, + impliedTopBits__h906678, + impliedTopBits__h907226, + impliedTopBits__h995044, len_correction__h127432, len_correction__h140348, - len_correction__h183609, - len_correction__h202360, - len_correction__h216926, - len_correction__h866989, - len_correction__h867537, - len_correction__h906674, - len_correction__h907222, - len_correction__h995039, - prv__h1017444, - prv__h1017488, - r1__read_BITS_13_TO_12___h926452, + len_correction__h183610, + len_correction__h202361, + len_correction__h216927, + len_correction__h866987, + len_correction__h867535, + len_correction__h906677, + len_correction__h907225, + len_correction__h995043, + prv__h1017448, + prv__h1017492, + r1__read_BITS_13_TO_12___h926456, sbIdx__h152015, v__h836639, v__h836649, v__h837284, - wordIdx__h263231, - x__h1012317, - x__h1016599, + wordIdx__h263233, + x__h1012321, + x__h1016603, x__h127517, x__h140433, - x__h183694, - x__h202445, - x__h217011, - x__h867075, - x__h867623, - x__h906760, - x__h907308, - x__h995124, - y_avValue_snd_snd_snd_fst__h1015839, - y_avValue_snd_snd_snd_fst__h1016421, - y_avValue_snd_snd_snd_fst__h1016450; + x__h183695, + x__h202446, + x__h217012, + x__h867073, + x__h867621, + x__h906763, + x__h907311, + x__h995128, + y_avValue_snd_snd_snd_fst__h1015843, + y_avValue_snd_snd_snd_fst__h1016425, + y_avValue_snd_snd_snd_fst__h1016454; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10589, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10639, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11986, @@ -6736,12 +6736,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h526143, - _theResult_____2__h533236, - _theResult_____2__h543871, - _theResult_____2__h557704, - _theResult_____2__h561483, - cause_interrupt__h995316, + _theResult_____2__h526144, + _theResult_____2__h533237, + _theResult_____2__h543872, + _theResult_____2__h557705, + _theResult_____2__h561484, + cause_interrupt__h995320, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22508, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613, @@ -7125,10 +7125,10 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029, - cr_flags__h866673, - cr_flags__h867221, - cr_flags__h906358, - cr_flags__h906906, + cr_flags__h866671, + cr_flags__h867219, + cr_flags__h906361, + cr_flags__h906909, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, @@ -7186,21 +7186,21 @@ module mkCore(CLK, guard__h736233, guard__h775086, guard__h814390, - idx__h968878, - k__h945028, + idx__h968882, + k__h945032, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21071, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21091, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22008, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22010, - next_deqP___1__h526388, - next_deqP___1__h533666, - next_deqP___1__h544301, - next_deqP___1__h557949, - next_deqP___1__h561728, - r1__read_BIT_20___h926958, - r__h853138, - r__h855582, + next_deqP___1__h526389, + next_deqP___1__h533667, + next_deqP___1__h544302, + next_deqP___1__h557950, + next_deqP___1__h561729, + r1__read_BIT_20___h926962, + r__h853136, + r__h855580, regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039, regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180, @@ -7244,20 +7244,20 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12443, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2768, - v__h516842, - v__h517222, - v__h532561, - v__h532756, - v__h535010, - v__h535205, - v__h556030, - v__h556225, - v__h559809, - v__h560004, + v__h516843, + v__h517223, + v__h532562, + v__h532757, + v__h535011, + v__h535206, + v__h556031, + v__h556226, + v__h559810, + v__h560005, value_BIT_52___h677325, - x__h240138, - x__h241295, - x__h254919, + x__h240140, + x__h241297, + x__h254921, x__h836140; // action method coreReq_start @@ -11325,15 +11325,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h989734, + addr__h989738, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328, rob$deqPort_0_deq_data[501:470] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1016374 ; + commitStage_rg_serial_num + y__h1016378 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h945032 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -11351,7 +11351,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11459,7 +11459,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h501096 } ; + x__h501097 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7036 } ; @@ -11469,7 +11469,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h505614, + addr__h505615, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7144 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11501,7 +11501,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:578] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h509110, + resp_addr__h509111, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11509,8 +11509,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1017488, - prv__h1017488 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1017492, + prv__h1017492 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11579,39 +11579,39 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h914618, - new_pc__h912071, + { x__h914622, + new_pc__h912075, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h914618, - new_pc__h912071, + { x__h914622, + new_pc__h912075, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h879902, - new_pc__h872924, + { x__h879901, + new_pc__h872923, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h879902, - new_pc__h872924, + { x__h879901, + new_pc__h872923, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1016351 ; + csrf_fflags_reg | fflags__h1016355 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1) ? @@ -11662,21 +11662,21 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd27) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318, - result_d_address__h1009824, - result_d_addrBits__h1009825, + result_d_address__h1009828, + result_d_addrBits__h1009829, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238, - result_d_address__h1032874, - result_d_addrBits__h1032875, + result_d_address__h1032878, + result_d_addrBits__h1032879, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1014147 + 64'd1 ; + n__read__h1014151 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1014147 + { 62'd0, x__h1016599 } ; + n__read__h1014151 + { 62'd0, x__h1016603 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == @@ -11688,21 +11688,21 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd24) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274, - result_d_address__h1009421, - result_d_addrBits__h1009422, + result_d_address__h1009425, + result_d_addrBits__h1009426, csrf_mtcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_mtcc_reg$write_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218, - result_d_address__h1032471, - result_d_addrBits__h1032472, + result_d_address__h1032475, + result_d_addrBits__h1032476, csrf_mtcc_reg[71:0] } ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h997075 or trap_val__h996922) + always@(commitStage_commitTrap or trap_val__h997079 or trap_val__h996926) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997075; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996922; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997079; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996926; default: MUX_csrf_mtval_csr$write_1__VAL_3 = 64'd0; endcase end @@ -11724,7 +11724,7 @@ module mkCore(CLK, 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1012317 : + x__h1012321 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_3 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? @@ -11734,44 +11734,44 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__VAL_3 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h994362, + dcsr_cause__h994366, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432, - result_d_address__h1010493, - result_d_addrBits__h1010494, + result_d_address__h1010497, + result_d_addrBits__h1010498, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309, - result_d_address__h1033541, - result_d_addrBits__h1033542, + result_d_address__h1033545, + result_d_addrBits__h1033546, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { commitStage_commitTrap[237], - pc_address__h994737, - pc_addrBits__h994738, + pc_address__h994741, + pc_addrBits__h994742, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580, - x__h995107, - x__h995127 } ; + x__h995111, + x__h995131 } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd13) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181, - result_d_address__h1009004, - result_d_addrBits__h1009005, + result_d_address__h1009008, + result_d_addrBits__h1009009, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160, - result_d_address__h1032054, - result_d_addrBits__h1032055, + result_d_address__h1032058, + result_d_addrBits__h1032059, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] == 5'd17 && @@ -11785,17 +11785,17 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd10) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135, - result_d_address__h1008601, - result_d_addrBits__h1008602, + result_d_address__h1008605, + result_d_addrBits__h1008606, csrf_stcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_stcc_reg$write_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138, - result_d_address__h1031651, - result_d_addrBits__h1031652, + result_d_address__h1031655, + result_d_addrBits__h1031656, csrf_stcc_reg[71:0] } ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1020024 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1020028 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11811,14 +11811,14 @@ module mkCore(CLK, IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[14:3], ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[2], IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[1:0], - thin_address__h999417 } ; + thin_address__h999421 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1012257 or v__h1012296 or v__h1013005) + next_pc__h1012261 or v__h1012300 or v__h1013009) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012296; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1013005; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012257; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012300; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1013009; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012261; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11865,8 +11865,8 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h567343, - res_addrBits__h567344, + res_address__h567344, + res_addrBits__h567345, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, @@ -11914,27 +11914,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h178896, - res_addrBits__h178897, - x__h183397[127:112], - x__h183397[109], - x__h183397[111:110], - ~x__h183397[108:90], + res_address__h178897, + res_addrBits__h178898, + x__h183398[127:112], + x__h183398[109], + x__h183398[111:110], + ~x__h183398[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h197661, - res_addrBits__h197662, - x__h199249[127:112], - x__h199249[109], - x__h199249[111:110], - ~x__h199249[108:90], + res_address__h197662, + res_addrBits__h197663, + x__h199250[127:112], + x__h199250[109], + x__h199250[111:110], + ~x__h199250[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h216420, - res_addrBits__h216421, + res_address__h216421, + res_addrBits__h216422, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -11942,13 +11942,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1018751, - data_addrBits__h1018752, + data_address__h1018755, + data_addrBits__h1018756, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1019605, - data_addrBits__h1019606, + data_address__h1019609, + data_addrBits__h1019610, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[591:463], @@ -12531,7 +12531,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h515366 ; + _theResult_____2__h515367 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12550,7 +12550,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h514822 ; + v__h514823 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12592,7 +12592,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h526143 ; + _theResult_____2__h526144 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12611,7 +12611,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h516842 ; + v__h516843 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12708,7 +12708,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h533236 ; + _theResult_____2__h533237 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12724,7 +12724,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h532561 ; + v__h532562 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12744,7 +12744,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h535372, + { x_addr__h535373, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12771,7 +12771,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h543871 ; + _theResult_____2__h543872 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12790,7 +12790,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h535010 ; + v__h535011 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12866,7 +12866,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h561483 ; + _theResult_____2__h561484 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12881,7 +12881,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h559809 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h559810 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12922,7 +12922,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h557704 ; + _theResult_____2__h557705 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12937,7 +12937,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556030 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556031 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13298,14 +13298,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995318) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995322) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_code_reg$D_IN = cause_code__h995318; + csrf_mcause_code_reg$D_IN = cause_code__h995322; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_mcause_code_reg$EN = @@ -13324,7 +13324,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995316) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995320) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = @@ -13332,7 +13332,7 @@ module mkCore(CLK, MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995316; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995320; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_mcause_interrupt_reg$EN = @@ -13519,7 +13519,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3066 : - n__read__h1014147 ; + n__read__h1014151 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13877,14 +13877,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995318) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995322) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_code_reg$D_IN = cause_code__h995318; + csrf_scause_code_reg$D_IN = cause_code__h995322; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_scause_code_reg$EN = @@ -13903,7 +13903,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995316) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995320) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = @@ -13911,7 +13911,7 @@ module mkCore(CLK, MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995316; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995320; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_scause_interrupt_reg$EN = @@ -15079,7 +15079,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h945032 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -15097,7 +15097,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15745,7 +15745,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21343, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15899,7 +15899,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h501096 ; + x__h501097 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[582:581] == 2'd0) ? @@ -16331,7 +16331,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22059) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968739 ; + renaming_spec_bits__h968743 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? @@ -16351,7 +16351,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968739 ; + renaming_spec_bits__h968743 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16380,8 +16380,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h212839 : - t__h215125 ; + t__h212840 : + t__h215126 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16434,7 +16434,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } : - { pointer__h242635[3:0] == 4'd0 && + { pointer__h242637[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16604,7 +16604,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[239], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17017,9 +17017,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h872924 or + new_pc__h872923 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h912071 or + new_pc__h912075 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -17030,9 +17030,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h872924; + fetchStage$redirect_pc = new_pc__h872923; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h912071; + fetchStage$redirect_pc = new_pc__h912075; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -17222,7 +17222,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h968739 ; + renaming_spec_bits__h968743 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17499,7 +17499,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22188, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d22242, 7'd32, - renaming_spec_bits__h968739 } ; + renaming_spec_bits__h968743 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18062,11 +18062,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h855582 }), + .amoExec_current({ 128'd0, r__h855580 }), .amoExec_inpt({ 97'd0, x__h65639 }), .amoExec(amoExec___d773)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h263231), + .amoExec_wordIdx(wordIdx__h263233), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 } }), @@ -18083,12 +18083,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926246, - r1__read_BITS_13_TO_12___h926452 != + .checkForException_csrState({ x_decodeInfo_frm__h926250, + r1__read_BITS_13_TO_12___h926456 != 2'd0, - { prv__h1017444, + { prv__h1017448, csrf_tvm_reg, - { r1__read_BIT_20___h926958, + { r1__read_BIT_20___h926962, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18114,12 +18114,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926246, - r1__read_BITS_13_TO_12___h926452 != + .checkForException_csrState({ x_decodeInfo_frm__h926250, + r1__read_BITS_13_TO_12___h926456 != 2'd0, - { prv__h1017444, + { prv__h1017448, csrf_tvm_reg, - { r1__read_BIT_20___h926958, + { r1__read_BIT_20___h926962, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18130,14 +18130,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h963240), + .checkForException_pcc(pc__h963244), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21604)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[384:222]), .capChecks_b(coreFix_memExe_regToExeQ$first[221:59]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h248740, + repBound__h248742, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), @@ -18148,13 +18148,13 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[221:59]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h248740, + repBound__h248742, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h242834), - .prepareBoundsCheck_size(x__h249475 + - y__h249476), + .prepareBoundsCheck_vaddr(tmpAddr__h242836), + .prepareBoundsCheck_size(x__h249477 + + y__h249478), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[58:12]), .prepareBoundsCheck(prepareBoundsCheck___d4244)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], @@ -18174,24 +18174,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h866670, - cr_addrBits__h866671, + { cr_address__h866668, + cr_addrBits__h866669, { coreFix_aluExe_1_regToExeQ$first[305:290], - { cr_flags__h866673, - cr_reserved__h866674 }, + { cr_flags__h866671, + cr_reserved__h866672 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 } }, - repBound__h867139, + repBound__h867137, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h867218, - cr_addrBits__h867219, + { cr_address__h867216, + cr_addrBits__h867217, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h867221, - cr_reserved__h867222 }, + { cr_flags__h867219, + cr_reserved__h867220 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 } }, - repBound__h867687, + repBound__h867685, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 } }), @@ -18208,24 +18208,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h906355, - cr_addrBits__h906356, + { cr_address__h906358, + cr_addrBits__h906359, { coreFix_aluExe_0_regToExeQ$first[305:290], - { cr_flags__h906358, - cr_reserved__h906359 }, + { cr_flags__h906361, + cr_reserved__h906362 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 } }, - repBound__h906824, + repBound__h906827, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h906903, - cr_addrBits__h906904, + { cr_address__h906906, + cr_addrBits__h906907, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h906906, - cr_reserved__h906907 }, + { cr_flags__h906909, + cr_reserved__h906910 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 } }, - repBound__h907372, + repBound__h907375, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 } }), @@ -20287,11 +20287,11 @@ module mkCore(CLK, CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214) ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323 = - (_theResult____h920230 == 16'd0 && + (_theResult____h920234 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h920801 : - _theResult____h920230 ; + enabled_ints__h920805 : + _theResult____h920234 ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20676 = IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] || IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[1] || @@ -21094,7 +21094,7 @@ module mkCore(CLK, !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15164 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 = - _theResult_____2__h515366 == v__h514822 ; + _theResult_____2__h515367 == v__h514823 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7257 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 || @@ -21109,7 +21109,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 = - _theResult_____2__h526143 == v__h516842 ; + _theResult_____2__h526144 == v__h516843 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7349 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 || @@ -21138,9 +21138,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h521673 } ; + x__h521674 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 = - _theResult_____2__h533236 == v__h532561 ; + _theResult_____2__h533237 == v__h532562 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7508 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 || @@ -21155,7 +21155,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 = - _theResult_____2__h543871 == v__h535010 ; + _theResult_____2__h543872 == v__h535011 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7592 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 || @@ -21552,7 +21552,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 = - _theResult_____2__h561483 == v__h559809 ; + _theResult_____2__h561484 == v__h559810 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7878 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 || @@ -21567,7 +21567,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 = - _theResult_____2__h557704 == v__h556030 ; + _theResult_____2__h557705 == v__h556031 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7796 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 || @@ -21585,12 +21585,12 @@ module mkCore(CLK, (csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h1000919[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 } : - { x__h1000919[11:3], - x__h1000940[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922[13:3], - x__h1000940[2:0] } ; + { x__h1000923[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926 } : + { x__h1000923[11:3], + x__h1000944[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926[13:3], + x__h1000944[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? !csrf_rg_dcsr[2] && @@ -21832,46 +21832,46 @@ module mkCore(CLK, IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20984 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? - x__h1008531[13:0] >= toBounds__h1008417 : - x__h1008531[13:0] <= toBoundsM1__h1008418 ; + x__h1008535[13:0] >= toBounds__h1008421 : + x__h1008535[13:0] <= toBoundsM1__h1008422 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1008934[13:0] >= toBounds__h1008820 : - x__h1008934[13:0] <= toBoundsM1__h1008821 ; + x__h1008938[13:0] >= toBounds__h1008824 : + x__h1008938[13:0] <= toBoundsM1__h1008825 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? - x__h1009351[13:0] >= toBounds__h1009237 : - x__h1009351[13:0] <= toBoundsM1__h1009238 ; + x__h1009355[13:0] >= toBounds__h1009241 : + x__h1009355[13:0] <= toBoundsM1__h1009242 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1009754[13:0] >= toBounds__h1009640 : - x__h1009754[13:0] <= toBoundsM1__h1009641 ; + x__h1009758[13:0] >= toBounds__h1009644 : + x__h1009758[13:0] <= toBoundsM1__h1009645 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? - x__h1010423[13:0] >= toBounds__h1010309 : - x__h1010423[13:0] <= toBoundsM1__h1010310 ; + x__h1010427[13:0] >= toBounds__h1010313 : + x__h1010427[13:0] <= toBoundsM1__h1010314 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 = - { INV_x83397_BITS_108_TO_90__q34[0] ? x__h183517 : 6'd0, - x__h183677, - x__h183697 } ; + { INV_x83398_BITS_108_TO_90__q34[0] ? x__h183518 : 6'd0, + x__h183678, + x__h183698 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 = - { INV_x99249_BITS_108_TO_90__q36[0] ? x__h202268 : 6'd0, - x__h202428, - x__h202448 } ; + { INV_x99250_BITS_108_TO_90__q36[0] ? x__h202269 : 6'd0, + x__h202429, + x__h202449 } ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? - x__h994947 : + x__h994951 : 6'd0 ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 = - x__h995127[13:11] < repBound__h997634 ; + x__h995131[13:11] < repBound__h997638 ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664 = - pc_addrBits__h994738[13:11] < repBound__h997634 ; + pc_addrBits__h994742[13:11] < repBound__h997638 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 = - tb__h906821 < repBound__h906824 ; + tb__h906824 < repBound__h906827 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779 = - x__h906763[13:11] < repBound__h906824 ; + x__h906766[13:11] < repBound__h906827 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781 = - cr_addrBits__h906356[13:11] < repBound__h906824 ; + cr_addrBits__h906359[13:11] < repBound__h906827 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 == @@ -21889,11 +21889,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 = - tb__h907369 < repBound__h907372 ; + tb__h907372 < repBound__h907375 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843 = - x__h907311[13:11] < repBound__h907372 ; + x__h907314[13:11] < repBound__h907375 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845 = - cr_addrBits__h906904[13:11] < repBound__h907372 ; + cr_addrBits__h906907[13:11] < repBound__h907375 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 == @@ -21911,11 +21911,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 = - tb__h867136 < repBound__h867139 ; + tb__h867134 < repBound__h867137 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663 = - x__h867078[13:11] < repBound__h867139 ; + x__h867076[13:11] < repBound__h867137 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665 = - cr_addrBits__h866671[13:11] < repBound__h867139 ; + cr_addrBits__h866669[13:11] < repBound__h867137 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 == @@ -21933,11 +21933,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 = - tb__h867684 < repBound__h867687 ; + tb__h867682 < repBound__h867685 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727 = - x__h867626[13:11] < repBound__h867687 ; + x__h867624[13:11] < repBound__h867685 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729 = - cr_addrBits__h867219[13:11] < repBound__h867687 ; + cr_addrBits__h867217[13:11] < repBound__h867685 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 == @@ -21956,10 +21956,10 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216834 : + x__h216835 : 6'd0, - x__h216994, - x__h217014 } ; + x__h216995, + x__h217015 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? x__h127340 : @@ -23890,11 +23890,11 @@ module mkCore(CLK, _theResult___fst_exp__h611014 != 8'd255 && guard__h602937 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 = - offset__h242625[63] ? - x__h242774[13:0] >= toBounds__h242653 && - repBoundBits__h242650 != + offset__h242627[63] ? + x__h242776[13:0] >= toBounds__h242655 && + repBoundBits__h242652 != coreFix_memExe_regToExeQ$first[317:304] : - x__h242774[13:0] < toBoundsM1__h242654 ; + x__h242776[13:0] < toBoundsM1__h242656 ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8382_ETC___d18414 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && @@ -23982,24 +23982,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18608 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18820 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h892144 : + res_address__h892146 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18818 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18835 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h892145 : + res_addrBits__h892147 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18833 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h899111 : + thin_reserved__h899114 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h899112 : + thin_otype__h899115 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19382, @@ -24008,7 +24008,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h899287 : + thin_perms_soft__h899290 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, @@ -24039,18 +24039,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h899107 : + thin_address__h899110 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h899108 : + thin_addrBits__h899111 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19417 = - thin_bounds_topBits__h900513[13:11] < repBound__h900629 ; + thin_bounds_topBits__h900516[13:11] < repBound__h900632 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19419 = - thin_bounds_baseBits__h900514[13:11] < repBound__h900629 ; + thin_bounds_baseBits__h900517[13:11] < repBound__h900632 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19422 = - thin_addrBits__h899108[13:11] < repBound__h900629 ; + thin_addrBits__h899111[13:11] < repBound__h900632 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20092 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -24297,24 +24297,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d15845 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16425 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h848642 : + res_address__h848641 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16440 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h848643 : + res_addrBits__h848642 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h858476 : + thin_reserved__h858474 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h858477 : + thin_otype__h858475 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17235, @@ -24323,7 +24323,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h858712 : + thin_perms_soft__h858710 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16898, @@ -24354,18 +24354,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h858472 : + thin_address__h858470 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h858473 : + thin_addrBits__h858471 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17301 = - thin_bounds_topBits__h860420[13:11] < repBound__h860556 ; + thin_bounds_topBits__h860418[13:11] < repBound__h860554 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17303 = - thin_bounds_baseBits__h860421[13:11] < repBound__h860556 ; + thin_bounds_baseBits__h860419[13:11] < repBound__h860554 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17306 = - thin_addrBits__h858473[13:11] < repBound__h860556 ; + thin_addrBits__h858471[13:11] < repBound__h860554 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17977 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -25149,8 +25149,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h915808 : - w__h915803 ; + result__h915812 : + w__h915807 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5011 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25624,15 +25624,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__686_BIT_1_ETC___d3634 } ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h235321 : + res_addrBits__h235323 : ((coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3068 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3315 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h235320 : - x__h235743, + res_address__h235322 : + x__h235745, IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25771,13 +25771,13 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4249 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h242635[3:0] != 4'd0 : + pointer__h242637[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h242635[2:0] != 3'd0 : + pointer__h242637[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h242635[1:0] != 2'd0 : + pointer__h242637[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h242635[0])), + pointer__h242637[0])), capChecks___d4160[11:5], CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294, prepareBoundsCheck___d4244 } ; @@ -25809,10 +25809,10 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[13:0] ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] < - repBound__h855389 ; + repBound__h855387 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232[13:11] < - repBound__h855389 ; + repBound__h855387 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -25913,7 +25913,7 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 = - ((newAddrDiff__h1000193 == 64'd0) ? + ((newAddrDiff__h1000197 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 ? 2'd3 : @@ -25930,12 +25930,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845 = IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 && - (newAddrDiff__h1000193 == 64'd0 || + (newAddrDiff__h1000197 == 64'd0 || csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 || - newAddrDiff__h1000193 == + newAddrDiff__h1000197 == _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 = - ((newAddrDiff__h1000537 == 64'd0) ? + ((newAddrDiff__h1000541 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 ? 2'd3 : @@ -25952,12 +25952,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870 = IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 && - (newAddrDiff__h1000537 == 64'd0 || + (newAddrDiff__h1000541 == 64'd0 || csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 || - newAddrDiff__h1000537 == + newAddrDiff__h1000541 == _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873 = - (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? + (csrf_mtcc_reg[86] && cause_interrupt__h995320) ? (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 || IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845) && csrf_mtcc_reg[152] : @@ -25965,9 +25965,9 @@ module mkCore(CLK, IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870) && csrf_mtcc_reg[152] ; assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 = - (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? - address__h999513 : - base__h999478 ; + (csrf_mtcc_reg[86] && cause_interrupt__h995320) ? + address__h999517 : + base__h999482 ; assign IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? { IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804, @@ -25997,10 +25997,10 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[13:0] ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] < - repBound__h854397 ; + repBound__h854395 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080[13:11] < - repBound__h854397 ; + repBound__h854395 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26101,7 +26101,7 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 = - ((newAddrDiff__h999536 == 64'd0) ? + ((newAddrDiff__h999540 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 ? 2'd3 : @@ -26118,12 +26118,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776 = IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 && - (newAddrDiff__h999536 == 64'd0 || + (newAddrDiff__h999540 == 64'd0 || csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 || - newAddrDiff__h999536 == + newAddrDiff__h999540 == _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 = - ((newAddrDiff__h999880 == 64'd0) ? + ((newAddrDiff__h999884 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 ? 2'd3 : @@ -26140,12 +26140,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801 = IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 && - (newAddrDiff__h999880 == 64'd0 || + (newAddrDiff__h999884 == 64'd0 || csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 || - newAddrDiff__h999880 == + newAddrDiff__h999884 == _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804 = - (csrf_stcc_reg[86] && cause_interrupt__h995316) ? + (csrf_stcc_reg[86] && cause_interrupt__h995320) ? (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 || IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776) && csrf_stcc_reg[152] : @@ -26153,29 +26153,29 @@ module mkCore(CLK, IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801) && csrf_stcc_reg[152] ; assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 = - (csrf_stcc_reg[86] && cause_interrupt__h995316) ? - address__h999463 : - base__h999424 ; + (csrf_stcc_reg[86] && cause_interrupt__h995320) ? + address__h999467 : + base__h999428 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 = f_csr_reqs$D_OUT[63] ? - x__h1031581[13:0] >= toBounds__h1008417 : - x__h1031581[13:0] <= toBoundsM1__h1008418 ; + x__h1031585[13:0] >= toBounds__h1008421 : + x__h1031585[13:0] <= toBoundsM1__h1008422 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 = f_csr_reqs$D_OUT[63] ? - x__h1031984[13:0] >= toBounds__h1008820 : - x__h1031984[13:0] <= toBoundsM1__h1008821 ; + x__h1031988[13:0] >= toBounds__h1008824 : + x__h1031988[13:0] <= toBoundsM1__h1008825 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 = f_csr_reqs$D_OUT[63] ? - x__h1032401[13:0] >= toBounds__h1009237 : - x__h1032401[13:0] <= toBoundsM1__h1009238 ; + x__h1032405[13:0] >= toBounds__h1009241 : + x__h1032405[13:0] <= toBoundsM1__h1009242 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 = f_csr_reqs$D_OUT[63] ? - x__h1032804[13:0] >= toBounds__h1009640 : - x__h1032804[13:0] <= toBoundsM1__h1009641 ; + x__h1032808[13:0] >= toBounds__h1009644 : + x__h1032808[13:0] <= toBoundsM1__h1009645 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 = f_csr_reqs$D_OUT[63] ? - x__h1033471[13:0] >= toBounds__h1010309 : - x__h1033471[13:0] <= toBoundsM1__h1010310 ; + x__h1033475[13:0] >= toBounds__h1010313 : + x__h1033475[13:0] <= toBoundsM1__h1010314 ; assign IF_fetchStage_RDY_pipelines_0_first__0253_AND__ETC___d21186 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[268:266] != 3'd1 || @@ -26601,36 +26601,36 @@ module mkCore(CLK, 2'd3) } ; assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1015845 : + y_avValue_snd_snd_snd_snd_snd__h1015849 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015829 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015833 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1015839 : + y_avValue_snd_snd_snd_fst__h1015843 : 2'd0 ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135 = - (highOffsetBits__h1008408 == 50'd0 && + (highOffsetBits__h1008412 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 || NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181 = - (highOffsetBits__h1008811 == 50'd0 && + (highOffsetBits__h1008815 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 || NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274 = - (highOffsetBits__h1009228 == 50'd0 && + (highOffsetBits__h1009232 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 || NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318 = - (highOffsetBits__h1009631 == 50'd0 && + (highOffsetBits__h1009635 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 || NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432 = - (highOffsetBits__h1010300 == 50'd0 && + (highOffsetBits__h1010304 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 || NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; @@ -26766,7 +26766,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19071) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19093 = sbCons$lazyLookup_0_get[3] ? - repBound__h898284 : + repBound__h898287 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18430 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089) ; @@ -26797,7 +26797,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19196 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h900611, + repBound__h900614, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 } : @@ -26932,7 +26932,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16676) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16698 = sbCons$lazyLookup_1_get[3] ? - repBound__h857576 : + repBound__h857574 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5640_5_ETC___d15667 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16694) ; @@ -26963,7 +26963,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16801 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h860538, + repBound__h860536, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 } : @@ -27098,7 +27098,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3305) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3327 = sbCons$lazyLookup_3_get[3] ? - repBound__h237315 : + repBound__h237317 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2731 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3323) ; @@ -27254,7 +27254,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3572) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589 = sbCons$lazyLookup_3_get[2] ? - repBound__h239000 : + repBound__h239002 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2758 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3585) ; @@ -27329,17 +27329,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906570 : + x__h906573 : 6'd0, - x__h906743, - x__h906763 } ; + x__h906746, + x__h906766 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907118 : + x__h907121 : 6'd0, - x__h907291, - x__h907311 } ; + x__h907294, + x__h907314 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -27347,17 +27347,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866885 : + x__h866883 : 6'd0, - x__h867058, - x__h867078 } ; + x__h867056, + x__h867076 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867433 : + x__h867431 : 6'd0, - x__h867606, - x__h867626 } ; + x__h867604, + x__h867624 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -27368,8 +27368,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x83397_BITS_108_TO_90__q34 = ~x__h183397[108:90] ; - assign INV_x99249_BITS_108_TO_90__q36 = ~x__h199249[108:90] ; + assign INV_x83398_BITS_108_TO_90__q34 = ~x__h183398[108:90] ; + assign INV_x99250_BITS_108_TO_90__q36 = ~x__h199250[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10746 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -27458,10 +27458,10 @@ module mkCore(CLK, !checkForException___d21604[13] && NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21629 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 = - (fflags__h1016351 & csrf_fflags_reg) != fflags__h1016351 || - !r__h853138 && + (fflags__h1016355 & csrf_fflags_reg) != fflags__h1016355 || + !r__h853136 && (IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841 || - fflags__h1016351 != 5'd0) ; + fflags__h1016355 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 = !f1_sfd__h714897[21] && !f1_sfd__h714897[20] && !f1_sfd__h714897[19] && @@ -28743,7 +28743,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137, - x__h508764 } ; + x__h508765 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, @@ -28817,21 +28817,21 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881 = - { {64{x__h264730[63]}}, x__h264730 } ; + { {64{x__h264732[63]}}, x__h264732 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889 = - { {96{x__h264885[31]}}, x__h264885 } ; + { {96{x__h264887[31]}}, x__h264887 } ; assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678 = - x__h997622 | in__h997691[63:0] ; + x__h997626 | in__h997695[63:0] ; assign SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 = - x__h855225 | in__h855450[63:0] ; + x__h855223 | in__h855448[63:0] ; assign SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 = - x__h854232 | in__h854458[63:0] ; + x__h854230 | in__h854456[63:0] ; assign SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 = - x__h896270 | in__h855146[63:0] ; + x__h896273 | in__h855144[63:0] ; assign SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 = - x__h896615 | in__h855976[63:0] ; + x__h896618 | in__h855974[63:0] ; assign SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 = - x__h895986 | in__h854153[63:0] ; + x__h895989 | in__h854151[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10071 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83 } ; @@ -29179,17 +29179,17 @@ module mkCore(CLK, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834 = - x__h1000380[13:11] < repBound__h855068 ; + x__h1000384[13:11] < repBound__h855066 ; assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859 = - x__h1000684[13:11] < repBound__h855068 ; + x__h1000688[13:11] < repBound__h855066 ; assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765 = - x__h999723[13:11] < repBound__h854075 ; + x__h999727[13:11] < repBound__h854073 ; assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790 = - x__h1000027[13:11] < repBound__h854075 ; + x__h1000031[13:11] < repBound__h854073 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0256_BI_ETC___d21841 = (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21739 = (fetchStage$pipelines_1_first[268:266] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -29227,13 +29227,13 @@ module mkCore(CLK, 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677) ; assign _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 = - medeleg_csr__read__h850222[i__h995334] ; + medeleg_csr__read__h850220[i__h995338] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 = - mideleg_csr__read__h850320[i__h995534] ; + mideleg_csr__read__h850318[i__h995538] ; assign _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826 = - mask__h1000192 ^ y__h1000309 ; + mask__h1000196 ^ y__h1000313 ; assign _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757 = - mask__h999535 ^ y__h999652 ; + mask__h999539 ^ y__h999656 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10709 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -29840,7 +29840,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[238:237] != 2'd1 && fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d22174 ; assign _dfoo16 = - k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h945032 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29848,7 +29848,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22118 && NOT_fetchStage_pipelines_1_first__0265_BITS_26_ETC___d22130 ; assign _dfoo18 = - k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h945032 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29983,29 +29983,29 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h515366 = + assign _theResult_____2__h515367 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 ? - next_deqP___1__h515611 : + next_deqP___1__h515612 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h526143 = + assign _theResult_____2__h526144 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7334 ? - next_deqP___1__h526388 : + next_deqP___1__h526389 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h533236 = + assign _theResult_____2__h533237 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 ? - next_deqP___1__h533666 : + next_deqP___1__h533667 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h543871 = + assign _theResult_____2__h543872 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7577 ? - next_deqP___1__h544301 : + next_deqP___1__h544302 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h557704 = + assign _theResult_____2__h557705 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 ? - next_deqP___1__h557949 : + next_deqP___1__h557950 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h561483 = + assign _theResult_____2__h561484 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 ? - next_deqP___1__h561728 : + next_deqP___1__h561729 : coreFix_memExe_forwardQ_deqP ; assign _theResult____h576452 = (value__h577074 == 54'd0) ? sfd__h568847 : 57'd1 ; @@ -30049,9 +30049,9 @@ module mkCore(CLK, 12'd2105) ? result__h814395 : ((value__h797998 == 25'd0) ? sfd__h793556 : 57'd1) ; - assign _theResult____h920230 = + assign _theResult____h920234 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h920755 : + enabled_ints___1__h920759 : 16'd0 ; assign _theResult___exp__h585079 = sfd__h584655[24] ? @@ -32755,38 +32755,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? a___1__h835845 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h1008620 = - { {48{base__h895973[15]}}, base__h895973 } << + assign addBase__h1008624 = + { {48{base__h895976[15]}}, base__h895976 } << csrf_stcc_reg[33:28] ; - assign addBase__h1009023 = - { {48{base__h854219[15]}}, base__h854219 } << + assign addBase__h1009027 = + { {48{base__h854217[15]}}, base__h854217 } << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign addBase__h1009440 = - { {48{base__h896257[15]}}, base__h896257 } << + assign addBase__h1009444 = + { {48{base__h896260[15]}}, base__h896260 } << csrf_mtcc_reg[33:28] ; - assign addBase__h1009843 = - { {48{base__h855212[15]}}, base__h855212 } << + assign addBase__h1009847 = + { {48{base__h855210[15]}}, base__h855210 } << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign addBase__h1010513 = - { {48{base__h896602[15]}}, base__h896602 } << + assign addBase__h1010517 = + { {48{base__h896605[15]}}, base__h896605 } << csrf_rg_dpc[33:28] ; - assign addBase__h239861 = - { {48{base__h239696[15]}}, base__h239696 } << + assign addBase__h239863 = + { {48{base__h239698[15]}}, base__h239698 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addBase__h241018 = - { {48{base__h240853[15]}}, base__h240853 } << + assign addBase__h241020 = + { {48{base__h240855[15]}}, base__h240855 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addBase__h254642 = - { {48{base__h254477[15]}}, base__h254477 } << + assign addBase__h254644 = + { {48{base__h254479[15]}}, base__h254479 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h239970 = - { {50{x__h240069[15]}}, x__h240069 } << + assign addTop__h239972 = + { {50{x__h240071[15]}}, x__h240071 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addTop__h241127 = - { {50{x__h241226[15]}}, x__h241226 } << + assign addTop__h241129 = + { {50{x__h241228[15]}}, x__h241228 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addTop__h254751 = - { {50{x__h254850[15]}}, x__h254850 } << + assign addTop__h254753 = + { {50{x__h254852[15]}}, x__h254852 } << coreFix_memExe_dTlb$procResp[334:329] ; assign addr__h148438 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? @@ -32796,20 +32796,20 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h235314 = x__h235743[63:0] + csrf_ddc_reg[149:86] ; - assign addr__h989734 = + assign addr__h235316 = x__h235745[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h989738 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign address__h1000186 = { 2'd0, address__h999513 } ; - assign address__h1000530 = { 2'd0, base__h999478 } ; - assign address__h1013717 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h999463 = base__h999424 + { 57'd0, x__h999622 } ; - assign address__h999513 = base__h999478 + { 57'd0, x__h999622 } ; - assign address__h999529 = { 2'd0, address__h999463 } ; - assign address__h999873 = { 2'd0, base__h999424 } ; + assign address__h1000190 = { 2'd0, address__h999517 } ; + assign address__h1000534 = { 2'd0, base__h999482 } ; + assign address__h1013721 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h999467 = base__h999428 + { 57'd0, x__h999626 } ; + assign address__h999517 = base__h999482 + { 57'd0, x__h999626 } ; + assign address__h999533 = { 2'd0, address__h999467 } ; + assign address__h999877 = { 2'd0, base__h999428 } ; assign b___1__h835846 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23[31]}}, @@ -32828,31 +32828,31 @@ module mkCore(CLK, { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h183704 = - { x__h183397[77:67], ~x__h183397[66], x__h183397[65:64] } ; - assign b_base__h202455 = - { x__h199249[77:67], ~x__h199249[66], x__h199249[65:64] } ; - assign b_base__h217021 = + assign b_base__h183705 = + { x__h183398[77:67], ~x__h183398[66], x__h183398[65:64] } ; + assign b_base__h202456 = + { x__h199250[77:67], ~x__h199250[66], x__h199250[65:64] } ; + assign b_base__h217022 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h867085 = + assign b_base__h867083 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h867633 = + assign b_base__h867631 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h906770 = + assign b_base__h906773 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h907318 = + assign b_base__h907321 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_base__h995134 = + assign b_base__h995138 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; @@ -32864,44 +32864,44 @@ module mkCore(CLK, { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h183703 = - { x__h183397[89:81], ~x__h183397[80:79], x__h183397[78] } ; - assign b_top__h202454 = - { x__h199249[89:81], ~x__h199249[80:79], x__h199249[78] } ; - assign b_top__h217020 = + assign b_top__h183704 = + { x__h183398[89:81], ~x__h183398[80:79], x__h183398[78] } ; + assign b_top__h202455 = + { x__h199250[89:81], ~x__h199250[80:79], x__h199250[78] } ; + assign b_top__h217021 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h867084 = + assign b_top__h867082 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h867632 = + assign b_top__h867630 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h906769 = + assign b_top__h906772 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h907317 = + assign b_top__h907320 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign b_top__h995133 = + assign b_top__h995137 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign base__h239696 = + assign base__h239698 = { coreFix_memExe_regToExeQ$first[223:222], coreFix_memExe_regToExeQ$first[245:232] } ; - assign base__h240853 = + assign base__h240855 = { coreFix_memExe_regToExeQ$first[60:59], coreFix_memExe_regToExeQ$first[82:69] } ; - assign base__h254477 = + assign base__h254479 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h854219 = + assign base__h854217 = { (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 == IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089) ? 2'd0 : @@ -32910,7 +32910,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } ; - assign base__h855212 = + assign base__h855210 = { (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 == IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241) ? 2'd0 : @@ -32919,7 +32919,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } ; - assign base__h895973 = + assign base__h895976 = { (csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 == csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053) ? 2'd0 : @@ -32928,7 +32928,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_stcc_reg[13:0] } ; - assign base__h896257 = + assign base__h896260 = { (csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 == csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205) ? 2'd0 : @@ -32937,7 +32937,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_mtcc_reg[13:0] } ; - assign base__h896602 = + assign base__h896605 = { (csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 == csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350) ? 2'd0 : @@ -32946,7 +32946,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_rg_dpc[13:0] } ; - assign base__h997609 = + assign base__h997613 = { (IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 == IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd0 : @@ -32954,50 +32954,50 @@ module mkCore(CLK, !IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd1 : 2'd3), - x__h995127 } ; - assign base__h999424 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h999478 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign bot__h1008623 = - { csrf_stcc_reg[149:100] & highBitsfilter__h1008407, 14'd0 } + - addBase__h1008620 ; - assign bot__h1009026 = + x__h995131 } ; + assign base__h999428 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h999482 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign bot__h1008627 = + { csrf_stcc_reg[149:100] & highBitsfilter__h1008411, 14'd0 } + + addBase__h1008624 ; + assign bot__h1009030 = { IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104[63:14] & - highBitsfilter__h1008810, + highBitsfilter__h1008814, 14'd0 } + - addBase__h1009023 ; - assign bot__h1009443 = - { csrf_mtcc_reg[149:100] & highBitsfilter__h1009227, 14'd0 } + - addBase__h1009440 ; - assign bot__h1009846 = + addBase__h1009027 ; + assign bot__h1009447 = + { csrf_mtcc_reg[149:100] & highBitsfilter__h1009231, 14'd0 } + + addBase__h1009444 ; + assign bot__h1009850 = { IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256[63:14] & - highBitsfilter__h1009630, + highBitsfilter__h1009634, 14'd0 } + - addBase__h1009843 ; - assign bot__h1010516 = - { csrf_rg_dpc[149:100] & highBitsfilter__h1010299, 14'd0 } + - addBase__h1010513 ; + addBase__h1009847 ; + assign bot__h1010520 = + { csrf_rg_dpc[149:100] & highBitsfilter__h1010303, 14'd0 } + + addBase__h1010517 ; assign carry_out__h127431 = (topBits__h127429 < x__h127520[11:0]) ? 2'b01 : 2'b0 ; assign carry_out__h140347 = (topBits__h140345 < x__h140436[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h183608 = - (topBits__h183606 < x__h183697[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h202359 = - (topBits__h202357 < x__h202448[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h216925 = - (topBits__h216923 < x__h217014[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h866988 = - (topBits__h866986 < x__h867078[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h867536 = - (topBits__h867534 < x__h867626[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h906673 = - (topBits__h906671 < x__h906763[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h907221 = - (topBits__h907219 < x__h907311[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h995038 = - (topBits__h995036 < x__h995127[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h996893 = { 1'd0, i__h995534 } ; - assign cause_interrupt__h995316 = + assign carry_out__h183609 = + (topBits__h183607 < x__h183698[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h202360 = + (topBits__h202358 < x__h202449[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h216926 = + (topBits__h216924 < x__h217015[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h866986 = + (topBits__h866984 < x__h867076[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h867534 = + (topBits__h867532 < x__h867624[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h906676 = + (topBits__h906674 < x__h906766[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h907224 = + (topBits__h907222 < x__h907314[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h995042 = + (topBits__h995040 < x__h995131[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h996897 = { 1'd0, i__h995538 } ; + assign cause_interrupt__h995320 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501 = @@ -33062,7 +33062,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h900629 : + repBound__h900632 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436 } ; assign coreFix_aluExe_0_dispToRegQ_first__8383_BIT_13_ETC___d18468 = @@ -33113,7 +33113,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16826, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h860556 : + repBound__h860554 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320 } ; assign coreFix_aluExe_1_dispToRegQ_first__5620_BIT_13_ETC___d15705 = @@ -33299,7 +33299,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5023 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h422564 ; + y__h422565 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5632 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -35479,12 +35479,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:63] - - { 1'd0, x__h254919 } > + { 1'd0, x__h254921 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h254752, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h254754, 14'd0 } + - addTop__h254751 ; + addTop__h254753 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4557 = coreFix_memExe_dTlb$procResp[560:500] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4558 = @@ -35504,12 +35504,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__257_BITS_77_TO_1_ETC___d4550 = coreFix_memExe_dTlb$procResp[77:13] < coreFix_memExe_dTlb$procResp[212:148] ; - assign coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6 = + assign coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4 = coreFix_memExe_dTlb$procResp[292:291] ; - assign coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7 = + assign coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5 = coreFix_memExe_dTlb$procResp[450:401] + - ({ {48{coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6[1]}}, - coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6 } << + ({ {48{coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4[1]}}, + coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4 } << coreFix_memExe_dTlb$procResp[334:329]) ; assign coreFix_memExe_dispToRegQ_first__686_BIT_102_6_ETC___d3579 = { coreFix_memExe_dispToRegQ$first[102] && @@ -35530,15 +35530,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4250 = - { coreFix_memExe_lsq$getOrigBE << pointer__h242635[3:0], - (highOffsetBits__h242644 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h242637[3:0], + (highOffsetBits__h242646 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 || coreFix_memExe_regToExeQ$first[265:260] >= 6'd50) && coreFix_memExe_regToExeQ$first[384], - result_d_address__h242846, - x__h248117[13:0], + result_d_address__h242848, + x__h248119[13:0], coreFix_memExe_regToExeQ$first[303:232], - repBound__h248215, + repBound__h248217, coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110, coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, @@ -35546,7 +35546,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 = coreFix_memExe_regToExeQ$first[102:97] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:63] - - { 1'd0, x__h241295 } > + { 1'd0, x__h241297 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070 = { coreFix_memExe_regToExeQ$first[140:125], @@ -35559,26 +35559,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } << - x__h244675 ; + x__h244677 ; assign coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766 = - { coreFix_memExe_regToExeQ$first[220:169] & mask__h241128, + { coreFix_memExe_regToExeQ$first[220:169] & mask__h241130, 14'd0 } + - addTop__h241127 ; + addTop__h241129 ; assign coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111 = - coreFix_memExe_regToExeQ$first[245:243] < repBound__h248215 ; + coreFix_memExe_regToExeQ$first[245:243] < repBound__h248217 ; assign coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 = - coreFix_memExe_regToExeQ$first[259:257] < repBound__h248215 ; + coreFix_memExe_regToExeQ$first[259:257] < repBound__h248217 ; assign coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 = coreFix_memExe_regToExeQ$first[265:260] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:63] - - { 1'd0, x__h240138 } > + { 1'd0, x__h240140 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704 = - { coreFix_memExe_regToExeQ$first[383:332] & mask__h239971, + { coreFix_memExe_regToExeQ$first[383:332] & mask__h239973, 14'd0 } + - addTop__h239970 ; + addTop__h239972 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113 = - x__h248117[13:11] < repBound__h248215 ; + x__h248119[13:11] < repBound__h248217 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123 = { coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, (coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 == @@ -35595,10 +35595,10 @@ module mkCore(CLK, !coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113) ? 2'd1 : 2'd3) } ; - assign coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5 = + assign coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q7 = coreFix_memExe_regToExeQ$first[218:169] + - ({ {48{coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4[1]}}, - coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4 } << + ({ {48{coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6[1]}}, + coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6 } << coreFix_memExe_regToExeQ$first[102:97]) ; assign coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2 = coreFix_memExe_regToExeQ$first[223:222] ; @@ -35609,7 +35609,7 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[265:260]) ; assign coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 = coreFix_memExe_regToExeQ$first[434:403] ; - assign coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4 = + assign coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6 = coreFix_memExe_regToExeQ$first[60:59] ; assign coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && @@ -35619,44 +35619,44 @@ module mkCore(CLK, fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024 ; - assign cr_addrBits__h866671 = + assign cr_addrBits__h866669 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866847[13:0] : + x__h866845[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h867219 = + assign cr_addrBits__h867217 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867395[13:0] : + x__h867393[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h906356 = + assign cr_addrBits__h906359 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906532[13:0] : + x__h906535[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h906904 = + assign cr_addrBits__h906907 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907080[13:0] : + x__h907083[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h866670 = + assign cr_address__h866668 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h867218 = + assign cr_address__h867216 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h906355 = + assign cr_address__h906358 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h906903 = + assign cr_address__h906906 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h866673 = coreFix_aluExe_1_regToExeQ$first[287] ; - assign cr_flags__h867221 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h906358 = coreFix_aluExe_0_regToExeQ$first[287] ; - assign cr_flags__h906906 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h866674 = coreFix_aluExe_1_regToExeQ$first[289:288] ; - assign cr_reserved__h867222 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h906359 = coreFix_aluExe_0_regToExeQ$first[289:288] ; - assign cr_reserved__h906907 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h866671 = coreFix_aluExe_1_regToExeQ$first[287] ; + assign cr_flags__h867219 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h906361 = coreFix_aluExe_0_regToExeQ$first[287] ; + assign cr_flags__h906909 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h866672 = coreFix_aluExe_1_regToExeQ$first[289:288] ; + assign cr_reserved__h867220 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h906362 = coreFix_aluExe_0_regToExeQ$first[289:288] ; + assign cr_reserved__h906910 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144 = - csrf_ddc_reg[13:11] < repBound__h248740 ; + csrf_ddc_reg[13:11] < repBound__h248742 ; assign csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 = - csrf_ddc_reg[27:25] < repBound__h248740 ; + csrf_ddc_reg[27:25] < repBound__h248742 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146 = - csrf_ddc_reg[85:83] < repBound__h248740 ; + csrf_ddc_reg[85:83] < repBound__h248742 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 = { csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, (csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 == @@ -35713,33 +35713,33 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 = - csrf_mtcc_reg[13:11] < repBound__h855068 ; + csrf_mtcc_reg[13:11] < repBound__h855066 ; assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 = - csrf_mtcc_reg[149:86] & mask__h1000192 ; + csrf_mtcc_reg[149:86] & mask__h1000196 ; assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 = - newAddrDiff__h1000193 == mask__h1000192 ; + newAddrDiff__h1000197 == mask__h1000196 ; assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 = - newAddrDiff__h1000537 == mask__h1000192 ; + newAddrDiff__h1000541 == mask__h1000196 ; assign csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 = - csrf_mtcc_reg[85:83] < repBound__h855068 ; + csrf_mtcc_reg[85:83] < repBound__h855066 ; assign csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 = csrf_prv_reg_read__0286_ULE_1___d22614 && CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 ; assign csrf_prv_reg_read__0286_ULE_1___d22614 = csrf_prv_reg <= 2'd1 ; assign csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 = - csrf_rg_dpc[13:11] < repBound__h855898 ; + csrf_rg_dpc[13:11] < repBound__h855896 ; assign csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350 = - csrf_rg_dpc[85:83] < repBound__h855898 ; + csrf_rg_dpc[85:83] < repBound__h855896 ; assign csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 = - csrf_stcc_reg[13:11] < repBound__h854075 ; + csrf_stcc_reg[13:11] < repBound__h854073 ; assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 = - csrf_stcc_reg[149:86] & mask__h999535 ; + csrf_stcc_reg[149:86] & mask__h999539 ; assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 = - newAddrDiff__h999536 == mask__h999535 ; + newAddrDiff__h999540 == mask__h999539 ; assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 = - newAddrDiff__h999880 == mask__h999535 ; + newAddrDiff__h999884 == mask__h999539 ; assign csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 = - csrf_stcc_reg[85:83] < repBound__h854075 ; + csrf_stcc_reg[85:83] < repBound__h854073 ; assign data05831_BITS_31_TO_0__q26 = data__h705831[31:0] ; assign data___1__h705531 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145[31]}}, @@ -35772,11 +35772,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? data___1__h706391 : data__h705831 ; - assign data_addrBits__h1018752 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1019606 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1018751 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1019605 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h994362 = + assign data_addrBits__h1018756 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1019610 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1018755 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1019609 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h994366 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -35816,10 +35816,10 @@ module mkCore(CLK, assign din_inc___2_exp__h831691 = _theResult___fst_exp__h812441 + 11'd1 ; assign din_inc___2_exp__h831726 = _theResult___fst_exp__h822018 + 11'd1 ; assign din_inc___2_exp__h831752 = _theResult___fst_exp__h830851 + 11'd1 ; - assign enabled_ints___1__h920755 = pend_ints__h920228 & y__h920767 ; - assign enabled_ints__h920801 = - pend_ints__h920228 & - { r1__read_BITS_13_TO_0___h920777, csrf_mideleg_1_0_reg } ; + assign enabled_ints___1__h920759 = pend_ints__h920232 & y__h920771 ; + assign enabled_ints__h920805 = + pend_ints__h920232 & + { r1__read_BITS_13_TO_0___h920781, csrf_mideleg_1_0_reg } ; assign f1_exp14896_MINUS_127__q148 = f1_exp__h714896 - 8'd127 ; assign f1_exp__h714896 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -35852,27 +35852,27 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138 = - (highOffsetBits__h1031458 == 50'd0 && + (highOffsetBits__h1031462 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 || NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160 = - (highOffsetBits__h1031861 == 50'd0 && + (highOffsetBits__h1031865 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 || NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218 = - (highOffsetBits__h1032278 == 50'd0 && + (highOffsetBits__h1032282 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 || NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238 = - (highOffsetBits__h1032681 == 50'd0 && + (highOffsetBits__h1032685 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 || NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309 = - (highOffsetBits__h1033348 == 50'd0 && + (highOffsetBits__h1033352 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 || NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; @@ -35882,7 +35882,7 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h849218 = { 56'd0, x__h853091 } ; + assign fcsr_csr__read__h849216 = { 56'd0, x__h853089 } ; assign fetchStage_RDY_pipelines_0_first__0253_AND_fet_ETC___d21254 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[268:266] == 3'd1 && @@ -36156,12 +36156,12 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0265_BIT_180_145_ETC___d21553 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259 } ; - assign fflags__h1016351 = + assign fflags__h1016355 = NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? - y_avValue_snd_fst__h1016411 : + y_avValue_snd_fst__h1016415 : IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 ; - assign fflags_csr__read__h849193 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h849204 = { 61'd0, csrf_frm_reg } ; + assign fflags_csr__read__h849191 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h849202 = { 61'd0, csrf_frm_reg } ; assign guard__h576462 = { IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41[1], { sfdin__h584557[32:0], 23'd0 } != 56'd0 } ; @@ -36231,29 +36231,29 @@ module mkCore(CLK, assign guard__h822861 = { IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171[1], { _theResult___snd__h830797[3:0], 52'd0 } != 56'd0 } ; - assign highBitsfilter__h1008407 = + assign highBitsfilter__h1008411 = 50'h3FFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign highBitsfilter__h1008810 = + assign highBitsfilter__h1008814 = 50'h3FFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign highBitsfilter__h1009227 = + assign highBitsfilter__h1009231 = 50'h3FFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign highBitsfilter__h1009630 = + assign highBitsfilter__h1009634 = 50'h3FFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign highBitsfilter__h1010299 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign highOffsetBits__h1008408 = x__h1008435 & highBitsfilter__h1008407 ; - assign highOffsetBits__h1008811 = x__h1008435 & highBitsfilter__h1008810 ; - assign highOffsetBits__h1009228 = x__h1008435 & highBitsfilter__h1009227 ; - assign highOffsetBits__h1009631 = x__h1008435 & highBitsfilter__h1009630 ; - assign highOffsetBits__h1010300 = x__h1008435 & highBitsfilter__h1010299 ; - assign highOffsetBits__h1031458 = x__h1031485 & highBitsfilter__h1008407 ; - assign highOffsetBits__h1031861 = x__h1031485 & highBitsfilter__h1008810 ; - assign highOffsetBits__h1032278 = x__h1031485 & highBitsfilter__h1009227 ; - assign highOffsetBits__h1032681 = x__h1031485 & highBitsfilter__h1009630 ; - assign highOffsetBits__h1033348 = x__h1031485 & highBitsfilter__h1010299 ; - assign highOffsetBits__h242644 = x__h242671 & mask__h239862 ; - assign idx__h968878 = + assign highBitsfilter__h1010303 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign highOffsetBits__h1008412 = x__h1008439 & highBitsfilter__h1008411 ; + assign highOffsetBits__h1008815 = x__h1008439 & highBitsfilter__h1008814 ; + assign highOffsetBits__h1009232 = x__h1008439 & highBitsfilter__h1009231 ; + assign highOffsetBits__h1009635 = x__h1008439 & highBitsfilter__h1009634 ; + assign highOffsetBits__h1010304 = x__h1008439 & highBitsfilter__h1010303 ; + assign highOffsetBits__h1031462 = x__h1031489 & highBitsfilter__h1008411 ; + assign highOffsetBits__h1031865 = x__h1031489 & highBitsfilter__h1008814 ; + assign highOffsetBits__h1032282 = x__h1031489 & highBitsfilter__h1009231 ; + assign highOffsetBits__h1032685 = x__h1031489 & highBitsfilter__h1009634 ; + assign highOffsetBits__h1033352 = x__h1031489 & highBitsfilter__h1010303 ; + assign highOffsetBits__h242646 = x__h242673 & mask__h239864 ; + assign idx__h968882 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -36263,28 +36263,28 @@ module mkCore(CLK, !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; assign impliedTopBits__h127433 = x__h127517 + len_correction__h127432 ; assign impliedTopBits__h140349 = x__h140433 + len_correction__h140348 ; - assign impliedTopBits__h183610 = x__h183694 + len_correction__h183609 ; - assign impliedTopBits__h202361 = x__h202445 + len_correction__h202360 ; - assign impliedTopBits__h216927 = x__h217011 + len_correction__h216926 ; - assign impliedTopBits__h866990 = x__h867075 + len_correction__h866989 ; - assign impliedTopBits__h867538 = x__h867623 + len_correction__h867537 ; - assign impliedTopBits__h906675 = x__h906760 + len_correction__h906674 ; - assign impliedTopBits__h907223 = x__h907308 + len_correction__h907222 ; - assign impliedTopBits__h995040 = x__h995124 + len_correction__h995039 ; - assign in__h239801 = coreFix_memExe_regToExeQ$first[383:318] & y__h239818 ; - assign in__h240958 = coreFix_memExe_regToExeQ$first[220:155] & y__h240975 ; - assign in__h254582 = coreFix_memExe_dTlb$procResp[452:387] & y__h254599 ; - assign in__h854153 = csrf_stcc_reg[151:86] & y__h854170 ; - assign in__h854458 = + assign impliedTopBits__h183611 = x__h183695 + len_correction__h183610 ; + assign impliedTopBits__h202362 = x__h202446 + len_correction__h202361 ; + assign impliedTopBits__h216928 = x__h217012 + len_correction__h216927 ; + assign impliedTopBits__h866988 = x__h867073 + len_correction__h866987 ; + assign impliedTopBits__h867536 = x__h867621 + len_correction__h867535 ; + assign impliedTopBits__h906678 = x__h906763 + len_correction__h906677 ; + assign impliedTopBits__h907226 = x__h907311 + len_correction__h907225 ; + assign impliedTopBits__h995044 = x__h995128 + len_correction__h995043 ; + assign in__h239803 = coreFix_memExe_regToExeQ$first[383:318] & y__h239820 ; + assign in__h240960 = coreFix_memExe_regToExeQ$first[220:155] & y__h240977 ; + assign in__h254584 = coreFix_memExe_dTlb$procResp[452:387] & y__h254601 ; + assign in__h854151 = csrf_stcc_reg[151:86] & y__h854168 ; + assign in__h854456 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104 & - y__h854475 ; - assign in__h855146 = csrf_mtcc_reg[151:86] & y__h855163 ; - assign in__h855450 = + y__h854473 ; + assign in__h855144 = csrf_mtcc_reg[151:86] & y__h855161 ; + assign in__h855448 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256 & - y__h855467 ; - assign in__h855976 = csrf_rg_dpc[151:86] & y__h855993 ; - assign in__h997691 = pc_address__h994737 & y__h997708 ; - assign k__h945028 = + y__h855465 ; + assign in__h855974 = csrf_rg_dpc[151:86] & y__h855991 ; + assign in__h997695 = pc_address__h994741 & y__h997712 ; + assign k__h945032 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; @@ -36294,58 +36294,58 @@ module mkCore(CLK, 2'b0 ; assign len_correction__h140348 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h183609 = - INV_x83397_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; - assign len_correction__h202360 = - INV_x99249_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; - assign len_correction__h216926 = + assign len_correction__h183610 = + INV_x83398_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; + assign len_correction__h202361 = + INV_x99250_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; + assign len_correction__h216927 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h866989 = + assign len_correction__h866987 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h867537 = + assign len_correction__h867535 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h906674 = + assign len_correction__h906677 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h907222 = + assign len_correction__h907225 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign len_correction__h995039 = + assign len_correction__h995043 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? 2'b01 : 2'b0 ; - assign mask__h1000192 = 64'hFFFFFFFFFFFFFFFF << x__h1000253 ; - assign mask__h239862 = + assign mask__h1000196 = 64'hFFFFFFFFFFFFFFFF << x__h1000257 ; + assign mask__h239864 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h239971 = + assign mask__h239973 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h241019 = + assign mask__h241021 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h241128 = + assign mask__h241130 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h254643 = + assign mask__h254645 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h254752 = + assign mask__h254754 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h999535 = 64'hFFFFFFFFFFFFFFFF << x__h999596 ; - assign mcause_csr__read__h850885 = - { r1__read__h855500, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h850619 = - { r1__read__h855196, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h850222 = - { r1__read__h854873, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h850320 = - { r1__read__h854896, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h850447 = { r1__read__h854920, 1'b0 } ; - assign mip_csr__read__h851124 = { r1__read__h855507, 1'b0 } ; + assign mask__h999539 = 64'hFFFFFFFFFFFFFFFF << x__h999600 ; + assign mcause_csr__read__h850883 = + { r1__read__h855498, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h850617 = + { r1__read__h855194, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h850220 = + { r1__read__h854871, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h850318 = + { r1__read__h854894, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h850445 = { r1__read__h854918, 1'b0 } ; + assign mip_csr__read__h851122 = { r1__read__h855505, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -36387,56 +36387,56 @@ module mkCore(CLK, fetchStage$pipelines_0_first[273:269] != 5'd24 && fetchStage$pipelines_0_first[273:269] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h850061 = { r1__read__h854748, csrf_ie_vec_0 } ; - assign n__read__h1014147 = + assign mstatus_csr__read__h850059 = { r1__read__h854746, csrf_ie_vec_0 } ; + assign n__read__h1014151 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1014223 : + upd__h1014227 : csrf_minstret_ehr_data_rl ; assign n__read__h7908 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7977 : csrf_mcycle_ehr_data_rl ; - assign newAddrBits__h1008590 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008531[13:0] } ; - assign newAddrBits__h1008993 = + assign newAddrBits__h1008594 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008535[13:0] } ; + assign newAddrBits__h1008997 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1008934[13:0] } ; - assign newAddrBits__h1009410 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009351[13:0] } ; - assign newAddrBits__h1009813 = + { 2'd0, x__h1008938[13:0] } ; + assign newAddrBits__h1009414 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009355[13:0] } ; + assign newAddrBits__h1009817 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1009754[13:0] } ; - assign newAddrBits__h1010482 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010423[13:0] } ; - assign newAddrBits__h1031640 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031581[13:0] } ; - assign newAddrBits__h1032043 = + { 2'd0, x__h1009758[13:0] } ; + assign newAddrBits__h1010486 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010427[13:0] } ; + assign newAddrBits__h1031644 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031585[13:0] } ; + assign newAddrBits__h1032047 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1031984[13:0] } ; - assign newAddrBits__h1032460 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032401[13:0] } ; - assign newAddrBits__h1032863 = + { 2'd0, x__h1031988[13:0] } ; + assign newAddrBits__h1032464 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032405[13:0] } ; + assign newAddrBits__h1032867 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1032804[13:0] } ; - assign newAddrBits__h1033530 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033471[13:0] } ; - assign newAddrDiff__h1000193 = + { 2'd0, x__h1032808[13:0] } ; + assign newAddrBits__h1033534 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033475[13:0] } ; + assign newAddrDiff__h1000197 = csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - - (address__h999513 & mask__h1000192) ; - assign newAddrDiff__h1000537 = + (address__h999517 & mask__h1000196) ; + assign newAddrDiff__h1000541 = csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - - (base__h999478 & mask__h1000192) ; - assign newAddrDiff__h999536 = + (base__h999482 & mask__h1000196) ; + assign newAddrDiff__h999540 = csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - - (address__h999463 & mask__h999535) ; - assign newAddrDiff__h999880 = + (address__h999467 & mask__h999539) ; + assign newAddrDiff__h999884 = csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - - (base__h999424 & mask__h999535) ; - assign new_pc__h872924 = + (base__h999428 & mask__h999539) ; + assign new_pc__h872923 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -36448,7 +36448,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h912071 = + assign new_pc__h912075 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -36460,47 +36460,47 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h515611 = + assign next_deqP___1__h515612 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h526388 = + assign next_deqP___1__h526389 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h533666 = + assign next_deqP___1__h533667 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h544301 = + assign next_deqP___1__h544302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h557949 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h561728 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1012257 = + assign next_deqP___1__h557950 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h561729 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1012261 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1013717 } ; - assign offset__h239697 = + { rob$deqPort_0_deq_data[630:566], address__h1013721 } ; + assign offset__h239699 = { 2'd0, coreFix_memExe_regToExeQ$first[317:304] } - - base__h239696 ; - assign offset__h240854 = + base__h239698 ; + assign offset__h240856 = { 2'd0, coreFix_memExe_regToExeQ$first[154:141] } - - base__h240853 ; - assign offset__h242625 = + base__h240855 ; + assign offset__h242627 = { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15[31]}}, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 } ; - assign offset__h254478 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254477 ; - assign offset__h854220 = + assign offset__h254480 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254479 ; + assign offset__h854218 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080 } - - base__h854219 ; - assign offset__h855213 = + base__h854217 ; + assign offset__h855211 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232 } - - base__h855212 ; - assign offset__h895974 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895973 ; - assign offset__h896258 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896257 ; - assign offset__h896603 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896602 ; - assign offset__h997610 = { 2'd0, pc_addrBits__h994738 } - base__h997609 ; + base__h855210 ; + assign offset__h895977 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895976 ; + assign offset__h896261 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896260 ; + assign offset__h896606 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896605 ; + assign offset__h997614 = { 2'd0, pc_addrBits__h994742 } - base__h997613 ; assign out___1_sfd__h714960 = { f1_sfd__h714897, 29'd0 } ; assign out___1_sfd__h753954 = { f2_sfd__h753891, 29'd0 } ; assign out___1_sfd__h793258 = { f3_sfd__h793195, 29'd0 } ; @@ -36708,27 +36708,27 @@ module mkCore(CLK, _theResult___snd__h830797[5] ? _theResult___sfd__h831532 : _theResult___snd__h830797[56:5] ; - assign pc__h963240 = fetchStage$pipelines_1_first[591:463] ; - assign pc_addrBits__h994738 = + assign pc__h963244 = fetchStage$pipelines_1_first[591:463] ; + assign pc_addrBits__h994742 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? - x__h994909[13:0] : + x__h994913[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h994737 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h920228 = + assign pc_address__h994741 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h920232 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6183_ETC___d20297, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h242635 = + assign pointer__h242637 = coreFix_memExe_regToExeQ$first[383:318] + - { 2'd0, offset__h242625 } ; - assign prv__h1017444 = csrf_prv_reg ; - assign prv__h1017488 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + { 2'd0, offset__h242627 } ; + assign prv__h1017448 = csrf_prv_reg ; + assign prv__h1017492 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h706456 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h920777 = + assign r1__read_BITS_13_TO_0___h920781 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -36736,119 +36736,119 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h926452 = csrf_fs_reg ; - assign r1__read_BIT_20___h926958 = csrf_tw_reg ; - assign r1__read__h853106 = { r1__read__h853108, csrf_ie_vec_1 } ; - assign r1__read__h853108 = { r1__read__h853110, 2'b0 } ; - assign r1__read__h853110 = { r1__read__h853112, csrf_prev_ie_vec_0 } ; - assign r1__read__h853112 = { r1__read__h853114, csrf_prev_ie_vec_1 } ; - assign r1__read__h853114 = { r1__read__h853116, 2'b0 } ; - assign r1__read__h853116 = { r1__read__h853118, csrf_spp_reg } ; - assign r1__read__h853118 = { r1__read__h853120, 4'b0 } ; - assign r1__read__h853120 = { r1__read__h853122, csrf_fs_reg } ; - assign r1__read__h853122 = { r1__read__h853124, 2'd0 } ; - assign r1__read__h853124 = { r1__read__h853126, 1'b0 } ; - assign r1__read__h853126 = { r1__read__h853128, csrf_sum_reg } ; - assign r1__read__h853128 = { r1__read__h853130, csrf_mxr_reg } ; - assign r1__read__h853130 = { r1__read__h853132, 12'b0 } ; - assign r1__read__h853132 = { r1__read__h853134, 2'b10 } ; - assign r1__read__h853134 = { r__h853138, 29'b0 } ; - assign r1__read__h853510 = - { r1__read__h853512, csrf_software_int_en_vec_1 } ; - assign r1__read__h853512 = { r1__read__h853514, 2'b0 } ; - assign r1__read__h853514 = { r1__read__h853516, 1'b0 } ; - assign r1__read__h853516 = { r1__read__h853518, csrf_timer_int_en_vec_1 } ; - assign r1__read__h853518 = { r1__read__h853520, 2'b0 } ; - assign r1__read__h853520 = { r1__read__h853522, 1'b0 } ; - assign r1__read__h853522 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h854203 = { r1__read__h854205, csrf_scounteren_tm_reg } ; - assign r1__read__h854205 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h854508 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h854515 = - { r1__read__h854517, csrf_software_int_pend_vec_1 } ; - assign r1__read__h854517 = { r1__read__h854519, 2'b0 } ; - assign r1__read__h854519 = { r1__read__h854521, 1'b0 } ; - assign r1__read__h854521 = - { r1__read__h854523, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h854523 = { r1__read__h854525, 2'b0 } ; - assign r1__read__h854525 = { r1__read__h854527, 1'b0 } ; - assign r1__read__h854527 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h854725 = { vm_mode_reg__read__h854731, 16'd0 } ; - assign r1__read__h854748 = { r1__read__h854750, csrf_ie_vec_1 } ; - assign r1__read__h854750 = { r1__read__h854752, 1'b0 } ; - assign r1__read__h854752 = { r1__read__h854754, csrf_ie_vec_3 } ; - assign r1__read__h854754 = { r1__read__h854756, csrf_prev_ie_vec_0 } ; - assign r1__read__h854756 = { r1__read__h854758, csrf_prev_ie_vec_1 } ; - assign r1__read__h854758 = { r1__read__h854760, 1'b0 } ; - assign r1__read__h854760 = { r1__read__h854762, csrf_prev_ie_vec_3 } ; - assign r1__read__h854762 = { r1__read__h854764, csrf_spp_reg } ; - assign r1__read__h854764 = { r1__read__h854766, 2'b0 } ; - assign r1__read__h854766 = { r1__read__h854768, csrf_mpp_reg } ; - assign r1__read__h854768 = { r1__read__h854770, csrf_fs_reg } ; - assign r1__read__h854770 = { r1__read__h854772, 2'd0 } ; - assign r1__read__h854772 = { r1__read__h854774, csrf_mprv_reg } ; - assign r1__read__h854774 = { r1__read__h854776, csrf_sum_reg } ; - assign r1__read__h854776 = { r1__read__h854778, csrf_mxr_reg } ; - assign r1__read__h854778 = { r1__read__h854780, csrf_tvm_reg } ; - assign r1__read__h854780 = { r1__read__h854782, csrf_tw_reg } ; - assign r1__read__h854782 = { r1__read__h854784, csrf_tsr_reg } ; - assign r1__read__h854784 = { r1__read__h854786, 9'b0 } ; + assign r1__read_BITS_13_TO_12___h926456 = csrf_fs_reg ; + assign r1__read_BIT_20___h926962 = csrf_tw_reg ; + assign r1__read__h853104 = { r1__read__h853106, csrf_ie_vec_1 } ; + assign r1__read__h853106 = { r1__read__h853108, 2'b0 } ; + assign r1__read__h853108 = { r1__read__h853110, csrf_prev_ie_vec_0 } ; + assign r1__read__h853110 = { r1__read__h853112, csrf_prev_ie_vec_1 } ; + assign r1__read__h853112 = { r1__read__h853114, 2'b0 } ; + assign r1__read__h853114 = { r1__read__h853116, csrf_spp_reg } ; + assign r1__read__h853116 = { r1__read__h853118, 4'b0 } ; + assign r1__read__h853118 = { r1__read__h853120, csrf_fs_reg } ; + assign r1__read__h853120 = { r1__read__h853122, 2'd0 } ; + assign r1__read__h853122 = { r1__read__h853124, 1'b0 } ; + assign r1__read__h853124 = { r1__read__h853126, csrf_sum_reg } ; + assign r1__read__h853126 = { r1__read__h853128, csrf_mxr_reg } ; + assign r1__read__h853128 = { r1__read__h853130, 12'b0 } ; + assign r1__read__h853130 = { r1__read__h853132, 2'b10 } ; + assign r1__read__h853132 = { r__h853136, 29'b0 } ; + assign r1__read__h853508 = + { r1__read__h853510, csrf_software_int_en_vec_1 } ; + assign r1__read__h853510 = { r1__read__h853512, 2'b0 } ; + assign r1__read__h853512 = { r1__read__h853514, 1'b0 } ; + assign r1__read__h853514 = { r1__read__h853516, csrf_timer_int_en_vec_1 } ; + assign r1__read__h853516 = { r1__read__h853518, 2'b0 } ; + assign r1__read__h853518 = { r1__read__h853520, 1'b0 } ; + assign r1__read__h853520 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h854201 = { r1__read__h854203, csrf_scounteren_tm_reg } ; + assign r1__read__h854203 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h854506 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h854513 = + { r1__read__h854515, csrf_software_int_pend_vec_1 } ; + assign r1__read__h854515 = { r1__read__h854517, 2'b0 } ; + assign r1__read__h854517 = { r1__read__h854519, 1'b0 } ; + assign r1__read__h854519 = + { r1__read__h854521, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h854521 = { r1__read__h854523, 2'b0 } ; + assign r1__read__h854523 = { r1__read__h854525, 1'b0 } ; + assign r1__read__h854525 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h854723 = { vm_mode_reg__read__h854729, 16'd0 } ; + assign r1__read__h854746 = { r1__read__h854748, csrf_ie_vec_1 } ; + assign r1__read__h854748 = { r1__read__h854750, 1'b0 } ; + assign r1__read__h854750 = { r1__read__h854752, csrf_ie_vec_3 } ; + assign r1__read__h854752 = { r1__read__h854754, csrf_prev_ie_vec_0 } ; + assign r1__read__h854754 = { r1__read__h854756, csrf_prev_ie_vec_1 } ; + assign r1__read__h854756 = { r1__read__h854758, 1'b0 } ; + assign r1__read__h854758 = { r1__read__h854760, csrf_prev_ie_vec_3 } ; + assign r1__read__h854760 = { r1__read__h854762, csrf_spp_reg } ; + assign r1__read__h854762 = { r1__read__h854764, 2'b0 } ; + assign r1__read__h854764 = { r1__read__h854766, csrf_mpp_reg } ; + assign r1__read__h854766 = { r1__read__h854768, csrf_fs_reg } ; + assign r1__read__h854768 = { r1__read__h854770, 2'd0 } ; + assign r1__read__h854770 = { r1__read__h854772, csrf_mprv_reg } ; + assign r1__read__h854772 = { r1__read__h854774, csrf_sum_reg } ; + assign r1__read__h854774 = { r1__read__h854776, csrf_mxr_reg } ; + assign r1__read__h854776 = { r1__read__h854778, csrf_tvm_reg } ; + assign r1__read__h854778 = { r1__read__h854780, csrf_tw_reg } ; + assign r1__read__h854780 = { r1__read__h854782, csrf_tsr_reg } ; + assign r1__read__h854782 = { r1__read__h854784, 9'b0 } ; + assign r1__read__h854784 = { r1__read__h854786, 2'b10 } ; assign r1__read__h854786 = { r1__read__h854788, 2'b10 } ; - assign r1__read__h854788 = { r1__read__h854790, 2'b10 } ; - assign r1__read__h854790 = { r__h853138, 27'b0 } ; - assign r1__read__h854873 = { r1__read__h854875, 1'b0 } ; - assign r1__read__h854875 = { r1__read__h854877, csrf_medeleg_13_11_reg } ; - assign r1__read__h854877 = { r1__read__h854879, 1'b0 } ; - assign r1__read__h854879 = { r1__read__h854881, csrf_medeleg_15_reg } ; - assign r1__read__h854881 = { r1__read__h854883, 10'b0 } ; - assign r1__read__h854883 = { 35'b0, csrf_medeleg_28_26_reg } ; - assign r1__read__h854896 = { r1__read__h854898, 1'b0 } ; - assign r1__read__h854898 = { r1__read__h854900, csrf_mideleg_5_3_reg } ; - assign r1__read__h854900 = { r1__read__h854902, 1'b0 } ; - assign r1__read__h854902 = { r1__read__h854904, csrf_mideleg_9_7_reg } ; - assign r1__read__h854904 = { r1__read__h854906, 1'b0 } ; - assign r1__read__h854906 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h854920 = - { r1__read__h854922, csrf_software_int_en_vec_1 } ; - assign r1__read__h854922 = { r1__read__h854924, 1'b0 } ; - assign r1__read__h854924 = - { r1__read__h854926, csrf_software_int_en_vec_3 } ; - assign r1__read__h854926 = { r1__read__h854928, 1'b0 } ; - assign r1__read__h854928 = { r1__read__h854930, csrf_timer_int_en_vec_1 } ; - assign r1__read__h854930 = { r1__read__h854932, 1'b0 } ; - assign r1__read__h854932 = { r1__read__h854934, csrf_timer_int_en_vec_3 } ; - assign r1__read__h854934 = { r1__read__h854936, 1'b0 } ; - assign r1__read__h854936 = - { r1__read__h854938, csrf_external_int_en_vec_1 } ; - assign r1__read__h854938 = { r1__read__h854940, 1'b0 } ; - assign r1__read__h854940 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h855196 = { r1__read__h855198, csrf_mcounteren_tm_reg } ; - assign r1__read__h855198 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h855500 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h855507 = - { r1__read__h855509, csrf_software_int_pend_vec_1 } ; - assign r1__read__h855509 = { r1__read__h855511, 1'b0 } ; - assign r1__read__h855511 = - { r1__read__h855513, csrf_software_int_pend_vec_3 } ; - assign r1__read__h855513 = { r1__read__h855515, 1'b0 } ; - assign r1__read__h855515 = - { r1__read__h855517, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h855517 = { r1__read__h855519, 1'b0 } ; - assign r1__read__h855519 = - { r1__read__h855521, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h855521 = { r1__read__h855523, 1'b0 } ; - assign r1__read__h855523 = - { r1__read__h855525, csrf_external_int_pend_vec_1 } ; - assign r1__read__h855525 = { r1__read__h855527, 1'b0 } ; - assign r1__read__h855527 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h855836 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign r1__read__h854788 = { r__h853136, 27'b0 } ; + assign r1__read__h854871 = { r1__read__h854873, 1'b0 } ; + assign r1__read__h854873 = { r1__read__h854875, csrf_medeleg_13_11_reg } ; + assign r1__read__h854875 = { r1__read__h854877, 1'b0 } ; + assign r1__read__h854877 = { r1__read__h854879, csrf_medeleg_15_reg } ; + assign r1__read__h854879 = { r1__read__h854881, 10'b0 } ; + assign r1__read__h854881 = { 35'b0, csrf_medeleg_28_26_reg } ; + assign r1__read__h854894 = { r1__read__h854896, 1'b0 } ; + assign r1__read__h854896 = { r1__read__h854898, csrf_mideleg_5_3_reg } ; + assign r1__read__h854898 = { r1__read__h854900, 1'b0 } ; + assign r1__read__h854900 = { r1__read__h854902, csrf_mideleg_9_7_reg } ; + assign r1__read__h854902 = { r1__read__h854904, 1'b0 } ; + assign r1__read__h854904 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h854918 = + { r1__read__h854920, csrf_software_int_en_vec_1 } ; + assign r1__read__h854920 = { r1__read__h854922, 1'b0 } ; + assign r1__read__h854922 = + { r1__read__h854924, csrf_software_int_en_vec_3 } ; + assign r1__read__h854924 = { r1__read__h854926, 1'b0 } ; + assign r1__read__h854926 = { r1__read__h854928, csrf_timer_int_en_vec_1 } ; + assign r1__read__h854928 = { r1__read__h854930, 1'b0 } ; + assign r1__read__h854930 = { r1__read__h854932, csrf_timer_int_en_vec_3 } ; + assign r1__read__h854932 = { r1__read__h854934, 1'b0 } ; + assign r1__read__h854934 = + { r1__read__h854936, csrf_external_int_en_vec_1 } ; + assign r1__read__h854936 = { r1__read__h854938, 1'b0 } ; + assign r1__read__h854938 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h855194 = { r1__read__h855196, csrf_mcounteren_tm_reg } ; + assign r1__read__h855196 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h855498 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h855505 = + { r1__read__h855507, csrf_software_int_pend_vec_1 } ; + assign r1__read__h855507 = { r1__read__h855509, 1'b0 } ; + assign r1__read__h855509 = + { r1__read__h855511, csrf_software_int_pend_vec_3 } ; + assign r1__read__h855511 = { r1__read__h855513, 1'b0 } ; + assign r1__read__h855513 = + { r1__read__h855515, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h855515 = { r1__read__h855517, 1'b0 } ; + assign r1__read__h855517 = + { r1__read__h855519, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h855519 = { r1__read__h855521, 1'b0 } ; + assign r1__read__h855521 = + { r1__read__h855523, csrf_external_int_pend_vec_1 } ; + assign r1__read__h855523 = { r1__read__h855525, 1'b0 } ; + assign r1__read__h855525 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h855834 = { 4'd0, csrf_rg_tdata1_dmode } ; assign rVal1__h714517 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; assign rVal2__h714518 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; assign r___1__h706482 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h853138 = csrf_fs_reg == 2'b11 ; - assign r__h855582 = csrf_software_int_pend_vec_3 ; + assign r__h853136 = csrf_fs_reg == 2'b11 ; + assign r__h855580 = csrf_software_int_pend_vec_3 ; assign regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039 = regRenamingTable$RDY_rename_0_getRename && rob$RDY_enqPort_0_enq && @@ -37051,37 +37051,37 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20654[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h968739 = + assign renaming_spec_bits__h968743 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h963383 : + y_avValue_snd_fst__h963387 : specTagManager$currentSpecBits ; - assign repBoundBits__h242650 = + assign repBoundBits__h242652 = { coreFix_memExe_regToExeQ$first[231:229], 11'd0 } ; - assign repBound__h237315 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h239000 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h248215 = + assign repBound__h237317 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h239002 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h248217 = coreFix_memExe_regToExeQ$first[245:243] - 3'b001 ; - assign repBound__h248740 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h854075 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h854397 = + assign repBound__h248742 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h854073 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h854395 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] - 3'b001 ; - assign repBound__h855068 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign repBound__h855389 = + assign repBound__h855066 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign repBound__h855387 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] - 3'b001 ; - assign repBound__h855898 = csrf_rg_dpc[13:11] - 3'b001 ; - assign repBound__h857576 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h860538 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h860556 = thin_bounds_baseBits__h860421[13:11] - 3'b001 ; - assign repBound__h867139 = x__h867078[13:11] - 3'b001 ; - assign repBound__h867687 = x__h867626[13:11] - 3'b001 ; - assign repBound__h898284 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h900611 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h900629 = thin_bounds_baseBits__h900514[13:11] - 3'b001 ; - assign repBound__h906824 = x__h906763[13:11] - 3'b001 ; - assign repBound__h907372 = x__h907311[13:11] - 3'b001 ; - assign repBound__h997634 = x__h995127[13:11] - 3'b001 ; + assign repBound__h855896 = csrf_rg_dpc[13:11] - 3'b001 ; + assign repBound__h857574 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h860536 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h860554 = thin_bounds_baseBits__h860419[13:11] - 3'b001 ; + assign repBound__h867137 = x__h867076[13:11] - 3'b001 ; + assign repBound__h867685 = x__h867624[13:11] - 3'b001 ; + assign repBound__h898287 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h900614 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h900632 = thin_bounds_baseBits__h900517[13:11] - 3'b001 ; + assign repBound__h906827 = x__h906766[13:11] - 3'b001 ; + assign repBound__h907375 = x__h907314[13:11] - 3'b001 ; + assign repBound__h997638 = x__h995131[13:11] - 3'b001 ; assign res_addrBits__h126822 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? x__h127302[13:0] : @@ -37090,44 +37090,44 @@ module mkCore(CLK, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? x__h140218[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h178897 = - INV_x83397_BITS_108_TO_90__q34[0] ? - x__h183479[13:0] : - x__h183397[13:0] ; - assign res_addrBits__h197662 = - INV_x99249_BITS_108_TO_90__q36[0] ? - x__h202230[13:0] : - x__h199249[13:0] ; - assign res_addrBits__h216421 = + assign res_addrBits__h178898 = + INV_x83398_BITS_108_TO_90__q34[0] ? + x__h183480[13:0] : + x__h183398[13:0] ; + assign res_addrBits__h197663 = + INV_x99250_BITS_108_TO_90__q36[0] ? + x__h202231[13:0] : + x__h199250[13:0] ; + assign res_addrBits__h216422 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216796[13:0] : + x__h216797[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h235321 = { 2'b0, addr__h235314[63:52] } ; - assign res_addrBits__h567344 = + assign res_addrBits__h235323 = { 2'b0, addr__h235316[63:52] } ; + assign res_addrBits__h567345 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; assign res_addrBits__h568197 = { 2'b0, data__h567678[63:52] } ; assign res_addrBits__h613954 = { 2'b0, data__h613438[63:52] } ; assign res_addrBits__h659701 = { 2'b0, data__h659185[63:52] } ; assign res_addrBits__h705510 = { 2'b0, data__h704999[63:52] } ; assign res_addrBits__h706370 = { 2'b0, data__h705862[63:52] } ; - assign res_addrBits__h848643 = { 2'b0, addr__h843948[63:52] } ; - assign res_addrBits__h892145 = { 2'b0, addr__h887458[63:52] } ; + assign res_addrBits__h848642 = { 2'b0, addr__h843947[63:52] } ; + assign res_addrBits__h892147 = { 2'b0, addr__h887460[63:52] } ; assign res_address__h126821 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; assign res_address__h139733 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h178896 = { 2'd0, x__h183397[63:0] } ; - assign res_address__h197661 = { 2'd0, x__h199249[63:0] } ; - assign res_address__h216420 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h235320 = { 2'd0, addr__h235314 } ; - assign res_address__h567343 = + assign res_address__h178897 = { 2'd0, x__h183398[63:0] } ; + assign res_address__h197662 = { 2'd0, x__h199250[63:0] } ; + assign res_address__h216421 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h235322 = { 2'd0, addr__h235316 } ; + assign res_address__h567344 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; assign res_address__h568196 = { 2'd0, data__h567678 } ; assign res_address__h613953 = { 2'd0, data__h613438 } ; assign res_address__h659700 = { 2'd0, data__h659185 } ; assign res_address__h705509 = { 2'd0, data__h704999 } ; assign res_address__h706369 = { 2'd0, data__h705862 } ; - assign res_address__h848642 = { 2'd0, addr__h843948 } ; - assign res_address__h892144 = { 2'd0, addr__h887458 } ; + assign res_address__h848641 = { 2'd0, addr__h843947 } ; + assign res_address__h892146 = { 2'd0, addr__h887460 } ; assign res_data__h568236 = { 32'hFFFFFFFF, x__h568251 } ; assign res_data__h568241 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37369,18 +37369,18 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12177 } ; - assign resp_addr__h509110 = + assign resp_addr__h509111 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[169:158] } ; - assign result__h240597 = + assign result__h240599 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64], coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[63:0] } ; - assign result__h241754 = + assign result__h241756 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64], coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[63:0] } ; - assign result__h255378 = + assign result__h255380 = { 1'd0, ~coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64], coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[63:0] } ; @@ -37408,99 +37408,99 @@ module mkCore(CLK, { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[0] | guard__h814390 } ; - assign result__h915808 = w__h915803 & y__h915837 ; - assign result__h915859 = ~x__h915858 ; - assign result_d_addrBits__h1008602 = + assign result__h915812 = w__h915807 & y__h915841 ; + assign result__h915863 = ~x__h915862 ; + assign result_d_addrBits__h1008606 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1008590[12:0] } : - newAddrBits__h1008590[13:0] ; - assign result_d_addrBits__h1009005 = + { 1'b0, newAddrBits__h1008594[12:0] } : + newAddrBits__h1008594[13:0] ; + assign result_d_addrBits__h1009009 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1008993[12:0] } : - newAddrBits__h1008993[13:0] ; - assign result_d_addrBits__h1009422 = + { 1'b0, newAddrBits__h1008997[12:0] } : + newAddrBits__h1008997[13:0] ; + assign result_d_addrBits__h1009426 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1009410[12:0] } : - newAddrBits__h1009410[13:0] ; - assign result_d_addrBits__h1009825 = + { 1'b0, newAddrBits__h1009414[12:0] } : + newAddrBits__h1009414[13:0] ; + assign result_d_addrBits__h1009829 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1009813[12:0] } : - newAddrBits__h1009813[13:0] ; - assign result_d_addrBits__h1010494 = + { 1'b0, newAddrBits__h1009817[12:0] } : + newAddrBits__h1009817[13:0] ; + assign result_d_addrBits__h1010498 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1010482[12:0] } : - newAddrBits__h1010482[13:0] ; - assign result_d_addrBits__h1031652 = + { 1'b0, newAddrBits__h1010486[12:0] } : + newAddrBits__h1010486[13:0] ; + assign result_d_addrBits__h1031656 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1031640[12:0] } : - newAddrBits__h1031640[13:0] ; - assign result_d_addrBits__h1032055 = + { 1'b0, newAddrBits__h1031644[12:0] } : + newAddrBits__h1031644[13:0] ; + assign result_d_addrBits__h1032059 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1032043[12:0] } : - newAddrBits__h1032043[13:0] ; - assign result_d_addrBits__h1032472 = + { 1'b0, newAddrBits__h1032047[12:0] } : + newAddrBits__h1032047[13:0] ; + assign result_d_addrBits__h1032476 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1032460[12:0] } : - newAddrBits__h1032460[13:0] ; - assign result_d_addrBits__h1032875 = + { 1'b0, newAddrBits__h1032464[12:0] } : + newAddrBits__h1032464[13:0] ; + assign result_d_addrBits__h1032879 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1032863[12:0] } : - newAddrBits__h1032863[13:0] ; - assign result_d_addrBits__h1033542 = + { 1'b0, newAddrBits__h1032867[12:0] } : + newAddrBits__h1032867[13:0] ; + assign result_d_addrBits__h1033546 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1033530[12:0] } : - newAddrBits__h1033530[13:0] ; - assign result_d_address__h1008601 = - { 2'd0, bot__h1008623 } + + { 1'b0, newAddrBits__h1033534[12:0] } : + newAddrBits__h1033534[13:0] ; + assign result_d_address__h1008605 = + { 2'd0, bot__h1008627 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009004 = - { 2'd0, bot__h1009026 } + + assign result_d_address__h1009008 = + { 2'd0, bot__h1009030 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009421 = - { 2'd0, bot__h1009443 } + + assign result_d_address__h1009425 = + { 2'd0, bot__h1009447 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009824 = - { 2'd0, bot__h1009846 } + + assign result_d_address__h1009828 = + { 2'd0, bot__h1009850 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1010493 = - { 2'd0, bot__h1010516 } + + assign result_d_address__h1010497 = + { 2'd0, bot__h1010520 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1031651 = - { 2'd0, bot__h1008623 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032054 = - { 2'd0, bot__h1009026 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032471 = - { 2'd0, bot__h1009443 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032874 = - { 2'd0, bot__h1009846 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1033541 = - { 2'd0, bot__h1010516 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h242846 = { 2'd0, pointer__h242635[63:0] } ; - assign ret__h239974 = + assign result_d_address__h1031655 = + { 2'd0, bot__h1008627 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032058 = + { 2'd0, bot__h1009030 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032475 = + { 2'd0, bot__h1009447 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032878 = + { 2'd0, bot__h1009850 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1033545 = + { 2'd0, bot__h1010520 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h242848 = { 2'd0, pointer__h242637[63:0] } ; + assign ret__h239976 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:0] } ; - assign ret__h241131 = + assign ret__h241133 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:0] } ; - assign ret__h254755 = + assign ret__h254757 = { 1'd0, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19097 = - rf$read_0_rd1[27:25] < repBound__h898284 ; + rf$read_0_rd1[27:25] < repBound__h898287 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19110 = - rf$read_0_rd1[13:11] < repBound__h898284 ; + rf$read_0_rd1[13:11] < repBound__h898287 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19124 = - rf$read_0_rd1[85:83] < repBound__h898284 ; + rf$read_0_rd1[85:83] < repBound__h898287 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 = - rf$read_0_rd2[27:25] < repBound__h900611 ; + rf$read_0_rd2[27:25] < repBound__h900614 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169 = - rf$read_0_rd2[13:11] < repBound__h900611 ; + rf$read_0_rd2[13:11] < repBound__h900614 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171 = - rf$read_0_rd2[85:83] < repBound__h900611 ; + rf$read_0_rd2[85:83] < repBound__h900614 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 == @@ -37518,17 +37518,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16702 = - rf$read_1_rd1[27:25] < repBound__h857576 ; + rf$read_1_rd1[27:25] < repBound__h857574 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16715 = - rf$read_1_rd1[13:11] < repBound__h857576 ; + rf$read_1_rd1[13:11] < repBound__h857574 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16729 = - rf$read_1_rd1[85:83] < repBound__h857576 ; + rf$read_1_rd1[85:83] < repBound__h857574 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 = - rf$read_1_rd2[27:25] < repBound__h860538 ; + rf$read_1_rd2[27:25] < repBound__h860536 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774 = - rf$read_1_rd2[13:11] < repBound__h860538 ; + rf$read_1_rd2[13:11] < repBound__h860536 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776 = - rf$read_1_rd2[85:83] < repBound__h860538 ; + rf$read_1_rd2[85:83] < repBound__h860536 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 == @@ -37546,25 +37546,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3331 = - rf$read_3_rd1[27:25] < repBound__h237315 ; + rf$read_3_rd1[27:25] < repBound__h237317 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3344 = - rf$read_3_rd1[13:11] < repBound__h237315 ; + rf$read_3_rd1[13:11] < repBound__h237317 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3358 = - rf$read_3_rd1[85:83] < repBound__h237315 ; + rf$read_3_rd1[85:83] < repBound__h237317 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3592 = - rf$read_3_rd2[27:25] < repBound__h239000 ; + rf$read_3_rd2[27:25] < repBound__h239002 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3600 = - rf$read_3_rd2[13:11] < repBound__h239000 ; + rf$read_3_rd2[13:11] < repBound__h239002 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609 = - rf$read_3_rd2[85:83] < repBound__h239000 ; + rf$read_3_rd2[85:83] < repBound__h239002 ; assign rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h852225 = - { r1__read__h855836, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h852223 = + { r1__read__h855834, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1634_AND_epochManager_ch_ETC___d21639 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -37574,7 +37574,7 @@ module mkCore(CLK, IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q17 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h849915 = { r1__read__h854725, csrf_ppn_reg } ; + assign satp_csr__read__h849913 = { r1__read__h854723, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12398 && @@ -37598,10 +37598,10 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h849712 = - { r1__read__h854508, csrf_scause_code_reg } ; - assign scounteren_csr__read__h849572 = - { r1__read__h854203, csrf_scounteren_cy_reg } ; + assign scause_csr__read__h849710 = + { r1__read__h854506, csrf_scause_code_reg } ; + assign scounteren_csr__read__h849570 = + { r1__read__h854201, csrf_scounteren_cy_reg } ; assign sfd__h568847 = { value__h577074, 3'd0 } ; assign sfd__h584655 = { 1'b0, @@ -37749,46 +37749,46 @@ module mkCore(CLK, _theResult____h813782[56] ? _theResult___snd__h822029 : _theResult___snd__h822040 ; - assign sie_csr__read__h849484 = { r1__read__h853510, 1'b0 } ; - assign signBits__h1008405 = + assign sie_csr__read__h849482 = { r1__read__h853508, 1'b0 } ; + assign signBits__h1008409 = {50{robdeqPort_0_deq_data_BITS_95_TO_32__q17[63]}} ; - assign signBits__h1031455 = {50{f_csr_reqs$D_OUT[63]}} ; - assign signBits__h242641 = {50{offset__h242625[63]}} ; - assign sip_csr__read__h849852 = { r1__read__h854515, 1'b0 } ; - assign spec_bits__h973790 = specTagManager$currentSpecBits | y__h973803 ; - assign sstatus_csr__read__h849414 = { r1__read__h853106, csrf_ie_vec_0 } ; - assign tb__h867136 = { impliedTopBits__h866990, topBits__h866986[11] } ; - assign tb__h867684 = { impliedTopBits__h867538, topBits__h867534[11] } ; - assign tb__h906821 = { impliedTopBits__h906675, topBits__h906671[11] } ; - assign tb__h907369 = { impliedTopBits__h907223, topBits__h907219[11] } ; - assign thin_address__h999417 = + assign signBits__h1031459 = {50{f_csr_reqs$D_OUT[63]}} ; + assign signBits__h242643 = {50{offset__h242627[63]}} ; + assign sip_csr__read__h849850 = { r1__read__h854513, 1'b0 } ; + assign spec_bits__h973794 = specTagManager$currentSpecBits | y__h973807 ; + assign sstatus_csr__read__h849412 = { r1__read__h853104, csrf_ie_vec_0 } ; + assign tb__h867134 = { impliedTopBits__h866988, topBits__h866984[11] } ; + assign tb__h867682 = { impliedTopBits__h867536, topBits__h867532[11] } ; + assign tb__h906824 = { impliedTopBits__h906678, topBits__h906674[11] } ; + assign tb__h907372 = { impliedTopBits__h907226, topBits__h907222[11] } ; + assign thin_address__h999421 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 : IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 ; - assign tmpAddr__h242834 = pointer__h242635[63:0] ; + assign tmpAddr__h242836 = pointer__h242637[63:0] ; assign tmp_expBotHalf__h127295 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; assign tmp_expBotHalf__h140211 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h183472 = { ~x__h183397[66], x__h183397[65:64] } ; - assign tmp_expBotHalf__h202223 = { ~x__h199249[66], x__h199249[65:64] } ; - assign tmp_expBotHalf__h216789 = + assign tmp_expBotHalf__h183473 = { ~x__h183398[66], x__h183398[65:64] } ; + assign tmp_expBotHalf__h202224 = { ~x__h199250[66], x__h199250[65:64] } ; + assign tmp_expBotHalf__h216790 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h866839 = + assign tmp_expBotHalf__h866837 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h867387 = + assign tmp_expBotHalf__h867385 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h906524 = + assign tmp_expBotHalf__h906527 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h907072 = + assign tmp_expBotHalf__h907075 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h994902 = + assign tmp_expBotHalf__h994906 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; assign tmp_expTopHalf__h127293 = @@ -37796,51 +37796,51 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[78] } ; assign tmp_expTopHalf__h140209 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h183470 = { ~x__h183397[80:79], x__h183397[78] } ; - assign tmp_expTopHalf__h202221 = { ~x__h199249[80:79], x__h199249[78] } ; - assign tmp_expTopHalf__h216787 = + assign tmp_expTopHalf__h183471 = { ~x__h183398[80:79], x__h183398[78] } ; + assign tmp_expTopHalf__h202222 = { ~x__h199250[80:79], x__h199250[78] } ; + assign tmp_expTopHalf__h216788 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h866837 = + assign tmp_expTopHalf__h866835 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h867385 = + assign tmp_expTopHalf__h867383 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h906522 = + assign tmp_expTopHalf__h906525 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h907070 = + assign tmp_expTopHalf__h907073 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h994900 = + assign tmp_expTopHalf__h994904 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign toBoundsM1__h1008418 = { 3'b110, ~csrf_stcc_reg[10:0] } ; - assign toBoundsM1__h1008821 = + assign toBoundsM1__h1008422 = { 3'b110, ~csrf_stcc_reg[10:0] } ; + assign toBoundsM1__h1008825 = { 3'b110, ~IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBoundsM1__h1009238 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; - assign toBoundsM1__h1009641 = + assign toBoundsM1__h1009242 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; + assign toBoundsM1__h1009645 = { 3'b110, ~IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBoundsM1__h1010310 = { 3'b110, ~csrf_rg_dpc[10:0] } ; - assign toBoundsM1__h242654 = - repBoundBits__h242650 + + assign toBoundsM1__h1010314 = { 3'b110, ~csrf_rg_dpc[10:0] } ; + assign toBoundsM1__h242656 = + repBoundBits__h242652 + ~coreFix_memExe_regToExeQ$first[317:304] ; - assign toBounds__h1008417 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; - assign toBounds__h1008820 = + assign toBounds__h1008421 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; + assign toBounds__h1008824 = 14'd14336 - { 3'b0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBounds__h1009237 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; - assign toBounds__h1009640 = + assign toBounds__h1009241 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; + assign toBounds__h1009644 = 14'd14336 - { 3'b0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBounds__h1010309 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; - assign toBounds__h242653 = - repBoundBits__h242650 - coreFix_memExe_regToExeQ$first[317:304] ; + assign toBounds__h1010313 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; + assign toBounds__h242655 = + repBoundBits__h242652 - coreFix_memExe_regToExeQ$first[317:304] ; assign topBits__h127429 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : @@ -37849,40 +37849,40 @@ module mkCore(CLK, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : b_top__h140442 ; - assign topBits__h183606 = - INV_x83397_BITS_108_TO_90__q34[0] ? - { x__h183397[89:81], 3'd0 } : - b_top__h183703 ; - assign topBits__h202357 = - INV_x99249_BITS_108_TO_90__q36[0] ? - { x__h199249[89:81], 3'd0 } : - b_top__h202454 ; - assign topBits__h216923 = + assign topBits__h183607 = + INV_x83398_BITS_108_TO_90__q34[0] ? + { x__h183398[89:81], 3'd0 } : + b_top__h183704 ; + assign topBits__h202358 = + INV_x99250_BITS_108_TO_90__q36[0] ? + { x__h199250[89:81], 3'd0 } : + b_top__h202455 ; + assign topBits__h216924 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h217020 ; - assign topBits__h866986 = + b_top__h217021 ; + assign topBits__h866984 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h867084 ; - assign topBits__h867534 = + b_top__h867082 ; + assign topBits__h867532 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h867632 ; - assign topBits__h906671 = + b_top__h867630 ; + assign topBits__h906674 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h906769 ; - assign topBits__h907219 = + b_top__h906772 ; + assign topBits__h907222 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h907317 ; - assign topBits__h995036 = + b_top__h907320 ; + assign topBits__h995040 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h995133 ; - assign trap_val__h997075 = { 53'd0, x__h998896 } ; - assign upd__h1014223 = + b_top__h995137 ; + assign trap_val__h997079 = { 53'd0, x__h998900 } ; + assign upd__h1014227 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -37895,7 +37895,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1012296 = + assign v__h1012300 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], @@ -37908,7 +37908,7 @@ module mkCore(CLK, ~IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[2], IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1013005 = + assign v__h1013009 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], @@ -37921,41 +37921,41 @@ module mkCore(CLK, ~IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[2], IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h514822 = + assign v__h514823 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 ? - v__h515017 : + v__h515018 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h515017 = + assign v__h515018 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h516842 = + assign v__h516843 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 ? - v__h517222 : + v__h517223 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h517222 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h532561 = + assign v__h517223 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h532562 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 ? - v__h532756 : + v__h532757 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h532756 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h535010 = + assign v__h532757 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h535011 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 ? - v__h535205 : + v__h535206 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h535205 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h556030 = + assign v__h535206 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h556031 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 ? - v__h556225 : + v__h556226 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h556225 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h559809 = + assign v__h556226 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h559810 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 ? - v__h560004 : + v__h560005 : coreFix_memExe_forwardQ_enqP ; - assign v__h560004 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h560005 = coreFix_memExe_forwardQ_enqP + 1'd1 ; assign v__h836639 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? v__h836649 : @@ -37966,21 +37966,21 @@ module mkCore(CLK, assign value_BIT_52___h677325 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0 ; - assign value__h239691 = x__h239709 | in__h239801[63:0] ; - assign value__h239855 = - { coreFix_memExe_regToExeQ$first[381:332] & mask__h239862, + assign value__h239693 = x__h239711 | in__h239803[63:0] ; + assign value__h239857 = + { coreFix_memExe_regToExeQ$first[381:332] & mask__h239864, 14'd0 } + - addBase__h239861 ; - assign value__h240848 = x__h240866 | in__h240958[63:0] ; - assign value__h241012 = - { coreFix_memExe_regToExeQ$first[218:169] & mask__h241019, + addBase__h239863 ; + assign value__h240850 = x__h240868 | in__h240960[63:0] ; + assign value__h241014 = + { coreFix_memExe_regToExeQ$first[218:169] & mask__h241021, 14'd0 } + - addBase__h241018 ; - assign value__h254472 = x__h254490 | in__h254582[63:0] ; - assign value__h254636 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h254643, + addBase__h241020 ; + assign value__h254474 = x__h254492 | in__h254584[63:0] ; + assign value__h254638 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h254645, 14'd0 } + - addBase__h254642 ; + addBase__h254644 ; assign value__h577074 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37998,56 +37998,56 @@ module mkCore(CLK, assign value__h719841 = { 1'b0, f1_exp__h714896 != 8'd0, f1_sfd__h714897 } ; assign value__h758694 = { 1'b0, f2_exp__h753890 != 8'd0, f2_sfd__h753891 } ; assign value__h797998 = { 1'b0, f3_exp__h793194 != 8'd0, f3_sfd__h793195 } ; - assign vm_mode_reg__read__h854731 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h915803 = + assign vm_mode_reg__read__h854729 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h915807 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h915859 : + result__h915863 : 12'd4095 ; - assign wordIdx__h263231 = + assign wordIdx__h263233 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 = + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1000027 = address__h999873 >> csrf_stcc_reg[33:28] ; - assign x__h1000253 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h1000380 = address__h1000186 >> csrf_mtcc_reg[33:28] ; - assign x__h1000684 = address__h1000530 >> csrf_mtcc_reg[33:28] ; - assign x__h1000919 = + assign x__h1000031 = address__h999877 >> csrf_stcc_reg[33:28] ; + assign x__h1000257 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h1000384 = address__h1000190 >> csrf_mtcc_reg[33:28] ; + assign x__h1000688 = address__h1000534 >> csrf_mtcc_reg[33:28] ; + assign x__h1000923 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h1000940 = + assign x__h1000944 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; - assign x__h1008435 = + assign x__h1008439 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63:14] ^ - signBits__h1008405 ; - assign x__h1008531 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; - assign x__h1008934 = + signBits__h1008409 ; + assign x__h1008535 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; + assign x__h1008938 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1009351 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; - assign x__h1009754 = + assign x__h1009355 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; + assign x__h1009758 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1010423 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; - assign x__h1012317 = { 1'b0, csrf_spp_reg } ; - assign x__h1016599 = + assign x__h1010427 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; + assign x__h1012321 = { 1'b0, csrf_spp_reg } ; + assign x__h1016603 = NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? - y_avValue_snd_snd_snd_fst__h1016421 : + y_avValue_snd_snd_snd_fst__h1016425 : IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 ; - assign x__h1031485 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031455 ; - assign x__h1031581 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; - assign x__h1031984 = + assign x__h1031489 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031459 ; + assign x__h1031585 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; + assign x__h1031988 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1032401 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; - assign x__h1032804 = + assign x__h1032405 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; + assign x__h1032808 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1033471 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; + assign x__h1033475 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; assign x__h127302 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127340 ; assign x__h127340 = { tmp_expTopHalf__h127293, tmp_expBotHalf__h127295 } ; assign x__h127500 = { impliedTopBits__h127433, topBits__h127429 } ; @@ -38069,113 +38069,113 @@ module mkCore(CLK, coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; assign x__h152124 = { 3'd0, sbIdx__h152015 } ; - assign x__h183397 = + assign x__h183398 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 } ; - assign x__h183479 = x__h183397[63:0] >> x__h183517 ; - assign x__h183517 = { tmp_expTopHalf__h183470, tmp_expBotHalf__h183472 } ; - assign x__h183677 = { impliedTopBits__h183610, topBits__h183606 } ; - assign x__h183694 = x__h183697[13:12] + carry_out__h183608 ; - assign x__h183697 = - INV_x83397_BITS_108_TO_90__q34[0] ? - { x__h183397[77:67], 3'd0 } : - b_base__h183704 ; - assign x__h199249 = + assign x__h183480 = x__h183398[63:0] >> x__h183518 ; + assign x__h183518 = { tmp_expTopHalf__h183471, tmp_expBotHalf__h183473 } ; + assign x__h183678 = { impliedTopBits__h183611, topBits__h183607 } ; + assign x__h183695 = x__h183698[13:12] + carry_out__h183609 ; + assign x__h183698 = + INV_x83398_BITS_108_TO_90__q34[0] ? + { x__h183398[77:67], 3'd0 } : + b_base__h183705 ; + assign x__h199250 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 } ; - assign x__h202230 = x__h199249[63:0] >> x__h202268 ; - assign x__h202268 = { tmp_expTopHalf__h202221, tmp_expBotHalf__h202223 } ; - assign x__h202428 = { impliedTopBits__h202361, topBits__h202357 } ; - assign x__h202445 = x__h202448[13:12] + carry_out__h202359 ; - assign x__h202448 = - INV_x99249_BITS_108_TO_90__q36[0] ? - { x__h199249[77:67], 3'd0 } : - b_base__h202455 ; - assign x__h216796 = coreFix_memExe_lsq$respLd[63:0] >> x__h216834 ; - assign x__h216834 = { tmp_expTopHalf__h216787, tmp_expBotHalf__h216789 } ; - assign x__h216994 = { impliedTopBits__h216927, topBits__h216923 } ; - assign x__h217011 = x__h217014[13:12] + carry_out__h216925 ; - assign x__h217014 = + assign x__h202231 = x__h199250[63:0] >> x__h202269 ; + assign x__h202269 = { tmp_expTopHalf__h202222, tmp_expBotHalf__h202224 } ; + assign x__h202429 = { impliedTopBits__h202362, topBits__h202358 } ; + assign x__h202446 = x__h202449[13:12] + carry_out__h202360 ; + assign x__h202449 = + INV_x99250_BITS_108_TO_90__q36[0] ? + { x__h199250[77:67], 3'd0 } : + b_base__h202456 ; + assign x__h216797 = coreFix_memExe_lsq$respLd[63:0] >> x__h216835 ; + assign x__h216835 = { tmp_expTopHalf__h216788, tmp_expBotHalf__h216790 } ; + assign x__h216995 = { impliedTopBits__h216928, topBits__h216924 } ; + assign x__h217012 = x__h217015[13:12] + carry_out__h216926 ; + assign x__h217015 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h217021 ; - assign x__h235743 = + b_base__h217022 ; + assign x__h235745 = (coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048 : 66'd0 ; - assign x__h239709 = x__h239711 << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239711 = { {48{offset__h239697[15]}}, offset__h239697 } ; - assign x__h239819 = + assign x__h239711 = x__h239713 << coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h239713 = { {48{offset__h239699[15]}}, offset__h239699 } ; + assign x__h239821 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239967 = + assign x__h239969 = coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 ? - result__h240597 : - ret__h239974 ; - assign x__h240069 = + result__h240599 : + ret__h239976 ; + assign x__h240071 = { coreFix_memExe_regToExeQ$first[225:224], coreFix_memExe_regToExeQ$first[259:246] } ; - assign x__h240138 = + assign x__h240140 = (coreFix_memExe_regToExeQ$first[265:260] == 6'd50) ? coreFix_memExe_regToExeQ$first[245] : coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3[49] ; - assign x__h240866 = x__h240868 << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h240868 = { {48{offset__h240854[15]}}, offset__h240854 } ; - assign x__h240976 = + assign x__h240868 = x__h240870 << coreFix_memExe_regToExeQ$first[102:97] ; + assign x__h240870 = { {48{offset__h240856[15]}}, offset__h240856 } ; + assign x__h240978 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h241124 = + assign x__h241126 = coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 ? - result__h241754 : - ret__h241131 ; - assign x__h241226 = + result__h241756 : + ret__h241133 ; + assign x__h241228 = { coreFix_memExe_regToExeQ$first[62:61], coreFix_memExe_regToExeQ$first[96:83] } ; - assign x__h241295 = + assign x__h241297 = (coreFix_memExe_regToExeQ$first[102:97] == 6'd50) ? coreFix_memExe_regToExeQ$first[82] : - coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5[49] ; - assign x__h242671 = offset__h242625[63:14] ^ signBits__h242641 ; - assign x__h242774 = - offset__h242625 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h244675 = { pointer__h242635[3:0], 3'b0 } ; - assign x__h248117 = - pointer__h242635 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h249475 = x__h249487 + y__h249488 ; - assign x__h249487 = x__h249499 + y__h249500 ; - assign x__h249499 = x__h249511 + y__h249512 ; - assign x__h249511 = x__h249523 + y__h249524 ; - assign x__h249523 = x__h249535 + y__h249536 ; - assign x__h249535 = x__h249547 + y__h249548 ; - assign x__h249547 = x__h249559 + y__h249560 ; - assign x__h249559 = x__h249571 + y__h249572 ; - assign x__h249571 = x__h249583 + y__h249584 ; - assign x__h249583 = x__h249595 + y__h249596 ; - assign x__h249595 = x__h249607 + y__h249608 ; - assign x__h249607 = x__h249619 + y__h249620 ; - assign x__h249619 = x__h249631 + y__h249632 ; - assign x__h249631 = x__h249643 + y__h249644 ; - assign x__h249643 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h254490 = x__h254492 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254492 = { {48{offset__h254478[15]}}, offset__h254478 } ; - assign x__h254600 = + coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q7[49] ; + assign x__h242673 = offset__h242627[63:14] ^ signBits__h242643 ; + assign x__h242776 = + offset__h242627 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h244677 = { pointer__h242637[3:0], 3'b0 } ; + assign x__h248119 = + pointer__h242637 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h249477 = x__h249489 + y__h249490 ; + assign x__h249489 = x__h249501 + y__h249502 ; + assign x__h249501 = x__h249513 + y__h249514 ; + assign x__h249513 = x__h249525 + y__h249526 ; + assign x__h249525 = x__h249537 + y__h249538 ; + assign x__h249537 = x__h249549 + y__h249550 ; + assign x__h249549 = x__h249561 + y__h249562 ; + assign x__h249561 = x__h249573 + y__h249574 ; + assign x__h249573 = x__h249585 + y__h249586 ; + assign x__h249585 = x__h249597 + y__h249598 ; + assign x__h249597 = x__h249609 + y__h249610 ; + assign x__h249609 = x__h249621 + y__h249622 ; + assign x__h249621 = x__h249633 + y__h249634 ; + assign x__h249633 = x__h249645 + y__h249646 ; + assign x__h249645 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h254492 = x__h254494 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254494 = { {48{offset__h254480[15]}}, offset__h254480 } ; + assign x__h254602 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254748 = + assign x__h254750 = coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 ? - result__h255378 : - ret__h254755 ; - assign x__h254850 = + result__h255380 : + ret__h254757 ; + assign x__h254852 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h254919 = + assign x__h254921 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : - coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h521673 = + coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5[49] ; + assign x__h521674 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; @@ -38238,42 +38238,42 @@ module mkCore(CLK, 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ; assign x__h836140 = a__h835704[63] ^ b__h835705[63] ; - assign x__h853091 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h854171 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign x__h854232 = - x__h854234 << + assign x__h853089 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h854169 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; + assign x__h854230 = + x__h854232 << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h854234 = { {48{offset__h854220[15]}}, offset__h854220 } ; - assign x__h854476 = + assign x__h854232 = { {48{offset__h854218[15]}}, offset__h854218 } ; + assign x__h854474 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h855164 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign x__h855225 = - x__h855227 << + assign x__h855162 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; + assign x__h855223 = + x__h855225 << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855227 = { {48{offset__h855213[15]}}, offset__h855213 } ; - assign x__h855468 = + assign x__h855225 = { {48{offset__h855211[15]}}, offset__h855211 } ; + assign x__h855466 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855994 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign x__h866847 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866885 ; - assign x__h866885 = { tmp_expTopHalf__h866837, tmp_expBotHalf__h866839 } ; - assign x__h867058 = { impliedTopBits__h866990, topBits__h866986 } ; - assign x__h867075 = x__h867078[13:12] + carry_out__h866988 ; - assign x__h867078 = + assign x__h855992 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign x__h866845 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866883 ; + assign x__h866883 = { tmp_expTopHalf__h866835, tmp_expBotHalf__h866837 } ; + assign x__h867056 = { impliedTopBits__h866988, topBits__h866984 } ; + assign x__h867073 = x__h867076[13:12] + carry_out__h866986 ; + assign x__h867076 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h867085 ; - assign x__h867395 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867433 ; - assign x__h867433 = { tmp_expTopHalf__h867385, tmp_expBotHalf__h867387 } ; - assign x__h867606 = { impliedTopBits__h867538, topBits__h867534 } ; - assign x__h867623 = x__h867626[13:12] + carry_out__h867536 ; - assign x__h867626 = + b_base__h867083 ; + assign x__h867393 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867431 ; + assign x__h867431 = { tmp_expTopHalf__h867383, tmp_expBotHalf__h867385 } ; + assign x__h867604 = { impliedTopBits__h867536, topBits__h867532 } ; + assign x__h867621 = x__h867624[13:12] + carry_out__h867534 ; + assign x__h867624 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h867633 ; - assign x__h879902 = + b_base__h867631 ; + assign x__h879901 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -38285,34 +38285,34 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h895986 = x__h895988 << csrf_stcc_reg[33:28] ; - assign x__h895988 = { {48{offset__h895974[15]}}, offset__h895974 } ; - assign x__h896270 = x__h896272 << csrf_mtcc_reg[33:28] ; - assign x__h896272 = { {48{offset__h896258[15]}}, offset__h896258 } ; - assign x__h896540 = + assign x__h895989 = x__h895991 << csrf_stcc_reg[33:28] ; + assign x__h895991 = { {48{offset__h895977[15]}}, offset__h895977 } ; + assign x__h896273 = x__h896275 << csrf_mtcc_reg[33:28] ; + assign x__h896275 = { {48{offset__h896261[15]}}, offset__h896261 } ; + assign x__h896543 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q24, 5'd3 } ; - assign x__h896615 = x__h896617 << csrf_rg_dpc[33:28] ; - assign x__h896617 = { {48{offset__h896603[15]}}, offset__h896603 } ; - assign x__h906532 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906570 ; - assign x__h906570 = { tmp_expTopHalf__h906522, tmp_expBotHalf__h906524 } ; - assign x__h906743 = { impliedTopBits__h906675, topBits__h906671 } ; - assign x__h906760 = x__h906763[13:12] + carry_out__h906673 ; - assign x__h906763 = + assign x__h896618 = x__h896620 << csrf_rg_dpc[33:28] ; + assign x__h896620 = { {48{offset__h896606[15]}}, offset__h896606 } ; + assign x__h906535 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906573 ; + assign x__h906573 = { tmp_expTopHalf__h906525, tmp_expBotHalf__h906527 } ; + assign x__h906746 = { impliedTopBits__h906678, topBits__h906674 } ; + assign x__h906763 = x__h906766[13:12] + carry_out__h906676 ; + assign x__h906766 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h906770 ; - assign x__h907080 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907118 ; - assign x__h907118 = { tmp_expTopHalf__h907070, tmp_expBotHalf__h907072 } ; - assign x__h907291 = { impliedTopBits__h907223, topBits__h907219 } ; - assign x__h907308 = x__h907311[13:12] + carry_out__h907221 ; - assign x__h907311 = + b_base__h906773 ; + assign x__h907083 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907121 ; + assign x__h907121 = { tmp_expTopHalf__h907073, tmp_expBotHalf__h907075 } ; + assign x__h907294 = { impliedTopBits__h907226, topBits__h907222 } ; + assign x__h907311 = x__h907314[13:12] + carry_out__h907224 ; + assign x__h907314 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h907318 ; - assign x__h914618 = + b_base__h907321 ; + assign x__h914622 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -38324,29 +38324,29 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h915807 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h915858 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h994909 = commitStage_commitTrap[172:109] >> x__h994947 ; - assign x__h994947 = { tmp_expTopHalf__h994900, tmp_expBotHalf__h994902 } ; - assign x__h995107 = { impliedTopBits__h995040, topBits__h995036 } ; - assign x__h995124 = x__h995127[13:12] + carry_out__h995038 ; - assign x__h995127 = + assign x__h915811 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h915862 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h994913 = commitStage_commitTrap[172:109] >> x__h994951 ; + assign x__h994951 = { tmp_expTopHalf__h994904, tmp_expBotHalf__h994906 } ; + assign x__h995111 = { impliedTopBits__h995044, topBits__h995040 } ; + assign x__h995128 = x__h995131[13:12] + carry_out__h995042 ; + assign x__h995131 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h995134 ; - assign x__h997622 = - x__h997624 << + b_base__h995138 ; + assign x__h997626 = + x__h997628 << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h997624 = { {48{offset__h997610[15]}}, offset__h997610 } ; - assign x__h997709 = + assign x__h997628 = { {48{offset__h997614[15]}}, offset__h997614 } ; + assign x__h997713 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h998896 = + assign x__h998900 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q25 } ; - assign x__h999596 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h999622 = { cause_code__h995318, 2'b0 } ; - assign x__h999723 = address__h999529 >> csrf_stcc_reg[33:28] ; + assign x__h999600 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h999626 = { cause_code__h995322, 2'b0 } ; + assign x__h999727 = address__h999533 >> csrf_stcc_reg[33:28] ; assign x_addr__h19883 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[214:151] : @@ -38355,7 +38355,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h535372 = + assign x_addr__h535373 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -38363,7 +38363,7 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h926246 = csrf_frm_reg ; + assign x_decodeInfo_frm__h926250 = csrf_frm_reg ; assign x_quotient__h705745 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : @@ -38371,7 +38371,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? q___1__h706456 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h849323 = { 63'd0, csrf_stats_module_doStats } ; + assign x_reg_ifc__read__h849321 = { 63'd0, csrf_stats_module_doStats } ; assign x_remainder__h705746 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : @@ -38379,39 +38379,39 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? r___1__h706482 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h1000309 = { mask__h1000192[62:0], 1'd0 } ; - assign y__h1016374 = + assign y__h1000313 = { mask__h1000196[62:0], 1'd0 } ; + assign y__h1016378 = NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? - y_avValue_snd_snd_snd_snd_snd__h1016427 : + y_avValue_snd_snd_snd_snd_snd__h1016431 : IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 ; - assign y__h239818 = ~x__h239819 ; - assign y__h240975 = ~x__h240976 ; - assign y__h249476 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h249488 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h249500 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h249512 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h249524 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h249536 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h249548 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h249560 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h249572 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h249584 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h249596 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h249608 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h249620 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h249632 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h249644 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h254599 = ~x__h254600 ; - assign y__h422564 = + assign y__h239820 = ~x__h239821 ; + assign y__h240977 = ~x__h240978 ; + assign y__h249478 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h249490 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h249502 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h249514 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h249526 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h249538 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h249550 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h249562 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h249574 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h249586 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h249598 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h249610 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h249622 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h249634 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h249646 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h254601 = ~x__h254602 ; + assign y__h422565 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[169:164] } ; - assign y__h854170 = ~x__h854171 ; - assign y__h854475 = ~x__h854476 ; - assign y__h855163 = ~x__h855164 ; - assign y__h855467 = ~x__h855468 ; - assign y__h855993 = ~x__h855994 ; - assign y__h915837 = ~x__h915807 ; - assign y__h920767 = + assign y__h854168 = ~x__h854169 ; + assign y__h854473 = ~x__h854474 ; + assign y__h855161 = ~x__h855162 ; + assign y__h855465 = ~x__h855466 ; + assign y__h855991 = ~x__h855992 ; + assign y__h915841 = ~x__h915811 ; + assign y__h920771 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -38420,9 +38420,9 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h973803 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h997708 = ~x__h997709 ; - assign y__h999652 = { mask__h999535[62:0], 1'd0 } ; + assign y__h973807 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h997712 = ~x__h997713 ; + assign y__h999656 = { mask__h999539[62:0], 1'd0 } ; assign y_avValue__h710472 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12381 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : @@ -38435,7 +38435,7 @@ module mkCore(CLK, NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12432 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12510 ; - assign y_avValue_snd_fst__h1015829 = + assign y_avValue_snd_fst__h1015833 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38450,7 +38450,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1016411 = + assign y_avValue_snd_fst__h1016415 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38464,25 +38464,25 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 : - y_avValue_snd_fst__h1016440 ; - assign y_avValue_snd_fst__h1016440 = + y_avValue_snd_fst__h1016444 ; + assign y_avValue_snd_fst__h1016444 = IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h963383 = + assign y_avValue_snd_fst__h963387 = ((fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180) ? - y_avValue_snd_fst__h963425 : + y_avValue_snd_fst__h963429 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963425 = + assign y_avValue_snd_fst__h963429 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? - y_avValue_snd_fst__h963467 : + y_avValue_snd_fst__h963471 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963467 = + assign y_avValue_snd_fst__h963471 = (fetchStage$pipelines_0_first[268:266] == 3'd1) ? - spec_bits__h973790 : + spec_bits__h973794 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1015839 = + assign y_avValue_snd_snd_snd_fst__h1015843 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38497,7 +38497,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1016421 = + assign y_avValue_snd_snd_snd_fst__h1016425 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38511,11 +38511,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 : - y_avValue_snd_snd_snd_fst__h1016450 ; - assign y_avValue_snd_snd_snd_fst__h1016450 = + y_avValue_snd_snd_snd_fst__h1016454 ; + assign y_avValue_snd_snd_snd_fst__h1016454 = IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1015845 = + assign y_avValue_snd_snd_snd_snd_snd__h1015849 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38530,7 +38530,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016427 = + assign y_avValue_snd_snd_snd_snd_snd__h1016431 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38544,8 +38544,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 : - y_avValue_snd_snd_snd_snd_snd__h1016456 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016456 = + y_avValue_snd_snd_snd_snd_snd__h1016460 ; + assign y_avValue_snd_snd_snd_snd_snd__h1016460 = IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -38559,6 +38559,19 @@ module mkCore(CLK, { 2'd3, mmio_cRqQ_data_0[148:145] }; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + addr__h505615 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; + 1'd1: + addr__h505615 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or @@ -38571,59 +38584,46 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) - 1'd0: - addr__h505614 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; - 1'd1: - addr__h505614 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; - endcase - end always@(coreFix_memExe_memRespLdQ_deqP or coreFix_memExe_memRespLdQ_data_0 or coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h212839 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h212839 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h212840 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h212840 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h215125 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h215125 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h215126 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h215126 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -38682,16 +38682,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd1: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd2: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; 2'd3: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21; endcase end @@ -38699,8 +38699,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h995534 = commitStage_commitTrap[35:32]; - default: i__h995534 = 4'd15; + i__h995538 = commitStage_commitTrap[35:32]; + default: i__h995538 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -38773,9 +38773,9 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or @@ -39041,16 +39041,16 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h995334 = commitStage_commitTrap[36:32]; - default: i__h995334 = 5'd28; + i__h995338 = commitStage_commitTrap[36:32]; + default: i__h995338 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h996893 or i__h995334) + always@(commitStage_commitTrap or cause_code__h996897 or i__h995338) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h995318 = 5'd28; - 2'd1: cause_code__h995318 = i__h995334; - default: cause_code__h995318 = cause_code__h996893; + 2'd0: cause_code__h995322 = 5'd28; + 2'd1: cause_code__h995322 = i__h995338; + default: cause_code__h995322 = cause_code__h996897; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -39340,16 +39340,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[31:0]; 2'd1: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[63:32]; 2'd2: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[31:0]; 2'd3: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[63:32]; endcase end @@ -43864,10 +43864,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h945028 or + always@(k__h945032 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945028) + case (k__h945032) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__119_ETC___d21202 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -43887,10 +43887,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h945028 or + always@(k__h945032 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945028) + case (k__h945032) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1191_co_ETC___d21225 = coreFix_aluExe_0_rsAlu$canEnq; @@ -44107,7 +44107,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h968878 or + always@(idx__h968882 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 or coreFix_aluExe_0_rsAlu$canEnq or @@ -44117,7 +44117,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BITS_268_TO_ETC___d21657 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968878) + case (idx__h968882) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0254_AN_ETC___d21680 = fetchStage$pipelines_0_canDeq && @@ -44221,15 +44221,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1286_AND__ETC___d21642; endcase end - always@(k__h945028 or + always@(k__h945032 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h945028) + case (k__h945032) 1'd0: - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -44265,7 +44265,7 @@ module mkCore(CLK, regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854; endcase end - always@(idx__h968878 or + always@(idx__h968882 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -44275,7 +44275,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21911 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968878) + case (idx__h968882) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__025_ETC___d21916 = (!fetchStage$pipelines_0_canDeq || @@ -44697,87 +44697,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_1[127:64]; - endcase - end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_1[63:0]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_1[127:64]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_1[63:0]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = - 3'd0; - endcase - end - always@(commitStage_commitTrap or - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678) - begin - case (commitStage_commitTrap[36:32]) - 5'd0, 5'd3: - trap_val__h996922 = - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678; - 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h996922 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h996922 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h996922 = 64'd0; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -45004,6 +44923,87 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0]; endcase end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_1[63:0]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_1[63:0]; + endcase + end + always@(commitStage_commitTrap or + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, 5'd3: + trap_val__h996926 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678; + 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: + trap_val__h996926 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h996926 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h996926 = 64'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = + 3'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -45913,17 +45913,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h858473 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h858473 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h858473 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h858473 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h858471 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h858471 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h858471 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h858471 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h858473 = + thin_addrBits__h858471 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h858473 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h858473 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h858473 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h858473 = + 5'd28: thin_addrBits__h858471 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h858471 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h858471 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h858471 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45937,17 +45937,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h899108 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h899108 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h899108 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h899108 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h899111 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h899111 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h899111 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h899111 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h899108 = + thin_addrBits__h899111 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h899108 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h899108 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h899108 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h899108 = + 5'd28: thin_addrBits__h899111 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h899111 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h899111 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h899111 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45961,17 +45961,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h860421 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h860421 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h860421 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h860421 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h860419 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h860419 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h860419 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h860419 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h860421 = + thin_bounds_baseBits__h860419 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h860421 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h860421 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h860421 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h860421 = + 5'd28: thin_bounds_baseBits__h860419 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h860419 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h860419 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h860419 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -45985,17 +45985,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h900514 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h900514 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h900514 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h900514 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h900517 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h900517 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h900517 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h900517 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h900514 = + thin_bounds_baseBits__h900517 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h900514 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h900514 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h900514 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h900514 = + 5'd28: thin_bounds_baseBits__h900517 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h900517 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h900517 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h900517 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -46009,17 +46009,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h858472 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h858472 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h858472 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h858472 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h858470 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h858470 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h858470 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h858470 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h858472 = + thin_address__h858470 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h858472 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h858472 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h858472 = csrf_mScratchC_reg[151:86]; - default: thin_address__h858472 = + 5'd28: thin_address__h858470 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h858470 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h858470 = csrf_mScratchC_reg[151:86]; + default: thin_address__h858470 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end @@ -46033,289 +46033,289 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h899107 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h899107 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h899107 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h899107 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h899110 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h899110 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h899110 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h899110 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h899107 = + thin_address__h899110 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h899107 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h899107 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h899107 = csrf_mScratchC_reg[151:86]; - default: thin_address__h899107 = + 5'd28: thin_address__h899110 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h899110 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h899110 = csrf_mScratchC_reg[151:86]; + default: thin_address__h899110 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h849193 or - frm_csr__read__h849204 or - fcsr_csr__read__h849218 or - sstatus_csr__read__h849414 or - sie_csr__read__h849484 or + fflags_csr__read__h849191 or + frm_csr__read__h849202 or + fcsr_csr__read__h849216 or + sstatus_csr__read__h849412 or + sie_csr__read__h849482 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849572 or + scounteren_csr__read__h849570 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849712 or + scause_csr__read__h849710 or csrf_stval_csr or - sip_csr__read__h849852 or - satp_csr__read__h849915 or - mstatus_csr__read__h850061 or - medeleg_csr__read__h850222 or - mideleg_csr__read__h850320 or - mie_csr__read__h850447 or + sip_csr__read__h849850 or + satp_csr__read__h849913 or + mstatus_csr__read__h850059 or + medeleg_csr__read__h850220 or + mideleg_csr__read__h850318 or + mie_csr__read__h850445 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850619 or + mcounteren_csr__read__h850617 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850885 or + mcause_csr__read__h850883 or csrf_mtval_csr or - mip_csr__read__h851124 or + mip_csr__read__h851122 or csrf_rg_tselect or - rg_tdata1__read__h852225 or + rg_tdata1__read__h852223 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849323 or + x_reg_ifc__read__h849321 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896543 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1020024 = fflags_csr__read__h849193; - 12'd2: data_out__h1020024 = frm_csr__read__h849204; - 12'd3: data_out__h1020024 = fcsr_csr__read__h849218; - 12'd256: data_out__h1020024 = sstatus_csr__read__h849414; - 12'd260: data_out__h1020024 = sie_csr__read__h849484; + 12'd1: data_out__h1020028 = fflags_csr__read__h849191; + 12'd2: data_out__h1020028 = frm_csr__read__h849202; + 12'd3: data_out__h1020028 = fcsr_csr__read__h849216; + 12'd256: data_out__h1020028 = sstatus_csr__read__h849412; + 12'd260: data_out__h1020028 = sie_csr__read__h849482; 12'd261: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: data_out__h1020024 = scounteren_csr__read__h849572; - 12'd320: data_out__h1020024 = csrf_sscratch_csr; + 12'd262: data_out__h1020028 = scounteren_csr__read__h849570; + 12'd320: data_out__h1020028 = csrf_sscratch_csr; 12'd321: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: data_out__h1020024 = scause_csr__read__h849712; - 12'd323: data_out__h1020024 = csrf_stval_csr; - 12'd324: data_out__h1020024 = sip_csr__read__h849852; - 12'd384: data_out__h1020024 = satp_csr__read__h849915; - 12'd768: data_out__h1020024 = mstatus_csr__read__h850061; - 12'd769: data_out__h1020024 = 64'h800000000014112D; - 12'd770: data_out__h1020024 = medeleg_csr__read__h850222; - 12'd771: data_out__h1020024 = mideleg_csr__read__h850320; - 12'd772: data_out__h1020024 = mie_csr__read__h850447; + 12'd322: data_out__h1020028 = scause_csr__read__h849710; + 12'd323: data_out__h1020028 = csrf_stval_csr; + 12'd324: data_out__h1020028 = sip_csr__read__h849850; + 12'd384: data_out__h1020028 = satp_csr__read__h849913; + 12'd768: data_out__h1020028 = mstatus_csr__read__h850059; + 12'd769: data_out__h1020028 = 64'h800000000014112D; + 12'd770: data_out__h1020028 = medeleg_csr__read__h850220; + 12'd771: data_out__h1020028 = mideleg_csr__read__h850318; + 12'd772: data_out__h1020028 = mie_csr__read__h850445; 12'd773: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: data_out__h1020024 = mcounteren_csr__read__h850619; - 12'd832: data_out__h1020024 = csrf_mscratch_csr; + 12'd774: data_out__h1020028 = mcounteren_csr__read__h850617; + 12'd832: data_out__h1020028 = csrf_mscratch_csr; 12'd833: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: data_out__h1020024 = mcause_csr__read__h850885; - 12'd835: data_out__h1020024 = csrf_mtval_csr; - 12'd836: data_out__h1020024 = mip_csr__read__h851124; - 12'd1952: data_out__h1020024 = csrf_rg_tselect; - 12'd1953: data_out__h1020024 = rg_tdata1__read__h852225; - 12'd1954: data_out__h1020024 = csrf_rg_tdata2; - 12'd1955: data_out__h1020024 = csrf_rg_tdata3; - 12'd1968: data_out__h1020024 = csrf_rg_dcsr; + 12'd834: data_out__h1020028 = mcause_csr__read__h850883; + 12'd835: data_out__h1020028 = csrf_mtval_csr; + 12'd836: data_out__h1020028 = mip_csr__read__h851122; + 12'd1952: data_out__h1020028 = csrf_rg_tselect; + 12'd1953: data_out__h1020028 = rg_tdata1__read__h852223; + 12'd1954: data_out__h1020028 = csrf_rg_tdata2; + 12'd1955: data_out__h1020028 = csrf_rg_tdata3; + 12'd1968: data_out__h1020028 = csrf_rg_dcsr; 12'd1969: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: data_out__h1020024 = csrf_rg_dscratch0; - 12'd1971: data_out__h1020024 = csrf_rg_dscratch1; + 12'd1970: data_out__h1020028 = csrf_rg_dscratch0; + 12'd1971: data_out__h1020028 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1020024 = 64'd0; - 12'd2049: data_out__h1020024 = x_reg_ifc__read__h849323; - 12'd2816, 12'd3072: data_out__h1020024 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1020024 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1020024 = { 48'd0, x__h896540 }; - 12'd3073: data_out__h1020024 = csrf_time_reg; - default: data_out__h1020024 = 64'b0; + data_out__h1020028 = 64'd0; + 12'd2049: data_out__h1020028 = x_reg_ifc__read__h849321; + 12'd2816, 12'd3072: data_out__h1020028 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1020028 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1020028 = { 48'd0, x__h896543 }; + 12'd3073: data_out__h1020028 = csrf_time_reg; + default: data_out__h1020028 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h849193 or - frm_csr__read__h849204 or - fcsr_csr__read__h849218 or - sstatus_csr__read__h849414 or - sie_csr__read__h849484 or + fflags_csr__read__h849191 or + frm_csr__read__h849202 or + fcsr_csr__read__h849216 or + sstatus_csr__read__h849412 or + sie_csr__read__h849482 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849572 or + scounteren_csr__read__h849570 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849712 or + scause_csr__read__h849710 or csrf_stval_csr or - sip_csr__read__h849852 or - satp_csr__read__h849915 or - mstatus_csr__read__h850061 or - medeleg_csr__read__h850222 or - mideleg_csr__read__h850320 or - mie_csr__read__h850447 or + sip_csr__read__h849850 or + satp_csr__read__h849913 or + mstatus_csr__read__h850059 or + medeleg_csr__read__h850220 or + mideleg_csr__read__h850318 or + mie_csr__read__h850445 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850619 or + mcounteren_csr__read__h850617 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850885 or + mcause_csr__read__h850883 or csrf_mtval_csr or - mip_csr__read__h851124 or + mip_csr__read__h851122 or csrf_rg_tselect or - rg_tdata1__read__h852225 or + rg_tdata1__read__h852223 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849323 or + x_reg_ifc__read__h849321 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896543 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h843948 = fflags_csr__read__h849193; - 12'd2: addr__h843948 = frm_csr__read__h849204; - 12'd3: addr__h843948 = fcsr_csr__read__h849218; - 12'd256: addr__h843948 = sstatus_csr__read__h849414; - 12'd260: addr__h843948 = sie_csr__read__h849484; + 12'd1: addr__h843947 = fflags_csr__read__h849191; + 12'd2: addr__h843947 = frm_csr__read__h849202; + 12'd3: addr__h843947 = fcsr_csr__read__h849216; + 12'd256: addr__h843947 = sstatus_csr__read__h849412; + 12'd260: addr__h843947 = sie_csr__read__h849482; 12'd261: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h843948 = scounteren_csr__read__h849572; - 12'd320: addr__h843948 = csrf_sscratch_csr; + 12'd262: addr__h843947 = scounteren_csr__read__h849570; + 12'd320: addr__h843947 = csrf_sscratch_csr; 12'd321: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h843948 = scause_csr__read__h849712; - 12'd323: addr__h843948 = csrf_stval_csr; - 12'd324: addr__h843948 = sip_csr__read__h849852; - 12'd384: addr__h843948 = satp_csr__read__h849915; - 12'd768: addr__h843948 = mstatus_csr__read__h850061; - 12'd769: addr__h843948 = 64'h800000000014112D; - 12'd770: addr__h843948 = medeleg_csr__read__h850222; - 12'd771: addr__h843948 = mideleg_csr__read__h850320; - 12'd772: addr__h843948 = mie_csr__read__h850447; + 12'd322: addr__h843947 = scause_csr__read__h849710; + 12'd323: addr__h843947 = csrf_stval_csr; + 12'd324: addr__h843947 = sip_csr__read__h849850; + 12'd384: addr__h843947 = satp_csr__read__h849913; + 12'd768: addr__h843947 = mstatus_csr__read__h850059; + 12'd769: addr__h843947 = 64'h800000000014112D; + 12'd770: addr__h843947 = medeleg_csr__read__h850220; + 12'd771: addr__h843947 = mideleg_csr__read__h850318; + 12'd772: addr__h843947 = mie_csr__read__h850445; 12'd773: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h843948 = mcounteren_csr__read__h850619; - 12'd832: addr__h843948 = csrf_mscratch_csr; + 12'd774: addr__h843947 = mcounteren_csr__read__h850617; + 12'd832: addr__h843947 = csrf_mscratch_csr; 12'd833: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h843948 = mcause_csr__read__h850885; - 12'd835: addr__h843948 = csrf_mtval_csr; - 12'd836: addr__h843948 = mip_csr__read__h851124; - 12'd1952: addr__h843948 = csrf_rg_tselect; - 12'd1953: addr__h843948 = rg_tdata1__read__h852225; - 12'd1954: addr__h843948 = csrf_rg_tdata2; - 12'd1955: addr__h843948 = csrf_rg_tdata3; - 12'd1968: addr__h843948 = csrf_rg_dcsr; + 12'd834: addr__h843947 = mcause_csr__read__h850883; + 12'd835: addr__h843947 = csrf_mtval_csr; + 12'd836: addr__h843947 = mip_csr__read__h851122; + 12'd1952: addr__h843947 = csrf_rg_tselect; + 12'd1953: addr__h843947 = rg_tdata1__read__h852223; + 12'd1954: addr__h843947 = csrf_rg_tdata2; + 12'd1955: addr__h843947 = csrf_rg_tdata3; + 12'd1968: addr__h843947 = csrf_rg_dcsr; 12'd1969: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h843948 = csrf_rg_dscratch0; - 12'd1971: addr__h843948 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843948 = 64'd0; - 12'd2049: addr__h843948 = x_reg_ifc__read__h849323; - 12'd2816, 12'd3072: addr__h843948 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h843948 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h843948 = { 48'd0, x__h896540 }; - 12'd3073: addr__h843948 = csrf_time_reg; - default: addr__h843948 = 64'b0; + 12'd1970: addr__h843947 = csrf_rg_dscratch0; + 12'd1971: addr__h843947 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843947 = 64'd0; + 12'd2049: addr__h843947 = x_reg_ifc__read__h849321; + 12'd2816, 12'd3072: addr__h843947 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h843947 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h843947 = { 48'd0, x__h896543 }; + 12'd3073: addr__h843947 = csrf_time_reg; + default: addr__h843947 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h849193 or - frm_csr__read__h849204 or - fcsr_csr__read__h849218 or - sstatus_csr__read__h849414 or - sie_csr__read__h849484 or + fflags_csr__read__h849191 or + frm_csr__read__h849202 or + fcsr_csr__read__h849216 or + sstatus_csr__read__h849412 or + sie_csr__read__h849482 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849572 or + scounteren_csr__read__h849570 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849712 or + scause_csr__read__h849710 or csrf_stval_csr or - sip_csr__read__h849852 or - satp_csr__read__h849915 or - mstatus_csr__read__h850061 or - medeleg_csr__read__h850222 or - mideleg_csr__read__h850320 or - mie_csr__read__h850447 or + sip_csr__read__h849850 or + satp_csr__read__h849913 or + mstatus_csr__read__h850059 or + medeleg_csr__read__h850220 or + mideleg_csr__read__h850318 or + mie_csr__read__h850445 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850619 or + mcounteren_csr__read__h850617 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850885 or + mcause_csr__read__h850883 or csrf_mtval_csr or - mip_csr__read__h851124 or + mip_csr__read__h851122 or csrf_rg_tselect or - rg_tdata1__read__h852225 or + rg_tdata1__read__h852223 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849323 or + x_reg_ifc__read__h849321 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896543 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h887458 = fflags_csr__read__h849193; - 12'd2: addr__h887458 = frm_csr__read__h849204; - 12'd3: addr__h887458 = fcsr_csr__read__h849218; - 12'd256: addr__h887458 = sstatus_csr__read__h849414; - 12'd260: addr__h887458 = sie_csr__read__h849484; + 12'd1: addr__h887460 = fflags_csr__read__h849191; + 12'd2: addr__h887460 = frm_csr__read__h849202; + 12'd3: addr__h887460 = fcsr_csr__read__h849216; + 12'd256: addr__h887460 = sstatus_csr__read__h849412; + 12'd260: addr__h887460 = sie_csr__read__h849482; 12'd261: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h887458 = scounteren_csr__read__h849572; - 12'd320: addr__h887458 = csrf_sscratch_csr; + 12'd262: addr__h887460 = scounteren_csr__read__h849570; + 12'd320: addr__h887460 = csrf_sscratch_csr; 12'd321: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h887458 = scause_csr__read__h849712; - 12'd323: addr__h887458 = csrf_stval_csr; - 12'd324: addr__h887458 = sip_csr__read__h849852; - 12'd384: addr__h887458 = satp_csr__read__h849915; - 12'd768: addr__h887458 = mstatus_csr__read__h850061; - 12'd769: addr__h887458 = 64'h800000000014112D; - 12'd770: addr__h887458 = medeleg_csr__read__h850222; - 12'd771: addr__h887458 = mideleg_csr__read__h850320; - 12'd772: addr__h887458 = mie_csr__read__h850447; + 12'd322: addr__h887460 = scause_csr__read__h849710; + 12'd323: addr__h887460 = csrf_stval_csr; + 12'd324: addr__h887460 = sip_csr__read__h849850; + 12'd384: addr__h887460 = satp_csr__read__h849913; + 12'd768: addr__h887460 = mstatus_csr__read__h850059; + 12'd769: addr__h887460 = 64'h800000000014112D; + 12'd770: addr__h887460 = medeleg_csr__read__h850220; + 12'd771: addr__h887460 = mideleg_csr__read__h850318; + 12'd772: addr__h887460 = mie_csr__read__h850445; 12'd773: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h887458 = mcounteren_csr__read__h850619; - 12'd832: addr__h887458 = csrf_mscratch_csr; + 12'd774: addr__h887460 = mcounteren_csr__read__h850617; + 12'd832: addr__h887460 = csrf_mscratch_csr; 12'd833: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h887458 = mcause_csr__read__h850885; - 12'd835: addr__h887458 = csrf_mtval_csr; - 12'd836: addr__h887458 = mip_csr__read__h851124; - 12'd1952: addr__h887458 = csrf_rg_tselect; - 12'd1953: addr__h887458 = rg_tdata1__read__h852225; - 12'd1954: addr__h887458 = csrf_rg_tdata2; - 12'd1955: addr__h887458 = csrf_rg_tdata3; - 12'd1968: addr__h887458 = csrf_rg_dcsr; + 12'd834: addr__h887460 = mcause_csr__read__h850883; + 12'd835: addr__h887460 = csrf_mtval_csr; + 12'd836: addr__h887460 = mip_csr__read__h851122; + 12'd1952: addr__h887460 = csrf_rg_tselect; + 12'd1953: addr__h887460 = rg_tdata1__read__h852223; + 12'd1954: addr__h887460 = csrf_rg_tdata2; + 12'd1955: addr__h887460 = csrf_rg_tdata3; + 12'd1968: addr__h887460 = csrf_rg_dcsr; 12'd1969: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h887458 = csrf_rg_dscratch0; - 12'd1971: addr__h887458 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887458 = 64'd0; - 12'd2049: addr__h887458 = x_reg_ifc__read__h849323; - 12'd2816, 12'd3072: addr__h887458 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h887458 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h887458 = { 48'd0, x__h896540 }; - 12'd3073: addr__h887458 = csrf_time_reg; - default: addr__h887458 = 64'b0; + 12'd1970: addr__h887460 = csrf_rg_dscratch0; + 12'd1971: addr__h887460 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887460 = 64'd0; + 12'd2049: addr__h887460 = x_reg_ifc__read__h849321; + 12'd2816, 12'd3072: addr__h887460 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h887460 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h887460 = { 48'd0, x__h896543 }; + 12'd3073: addr__h887460 = csrf_time_reg; + default: addr__h887460 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -46898,17 +46898,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h858476 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h858476 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h858476 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h858476 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h858474 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h858474 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h858474 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h858474 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h858476 = + thin_reserved__h858474 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h858476 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h858476 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h858476 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h858476 = + 5'd28: thin_reserved__h858474 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h858474 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h858474 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h858474 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46922,17 +46922,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h899111 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h899111 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h899111 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h899111 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h899114 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h899114 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h899114 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h899114 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h899111 = + thin_reserved__h899114 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h899111 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h899111 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h899111 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h899111 = + 5'd28: thin_reserved__h899114 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h899114 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h899114 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h899114 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46946,17 +46946,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h858712 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h858712 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h858712 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h858712 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h858710 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h858710 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h858710 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h858710 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h858712 = + thin_perms_soft__h858710 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h858712 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h858712 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h858712 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h858712 = + 5'd28: thin_perms_soft__h858710 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h858710 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h858710 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h858710 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46970,17 +46970,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h899287 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h899287 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h899287 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h899287 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h899290 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h899290 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h899290 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h899290 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h899287 = + thin_perms_soft__h899290 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h899287 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h899287 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h899287 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h899287 = + 5'd28: thin_perms_soft__h899290 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h899290 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h899290 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h899290 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46994,17 +46994,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h860420 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h860420 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h860420 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h860420 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h860418 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h860418 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h860418 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h860418 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h860420 = + thin_bounds_topBits__h860418 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h860420 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h860420 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h860420 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h860420 = + 5'd28: thin_bounds_topBits__h860418 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h860418 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h860418 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h860418 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -47018,17 +47018,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h900513 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h900513 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h900513 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h900513 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h900516 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h900516 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h900516 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h900516 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h900513 = + thin_bounds_topBits__h900516 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h900513 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h900513 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h900513 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h900513 = + 5'd28: thin_bounds_topBits__h900516 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h900516 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h900516 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h900516 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -47612,17 +47612,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h858477 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h858477 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h858477 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h858477 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h858475 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h858475 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h858475 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h858475 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h858477 = + thin_otype__h858475 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h858477 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h858477 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h858477 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h858477 = + 5'd28: thin_otype__h858475 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h858475 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h858475 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h858475 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -47636,17 +47636,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h899112 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h899112 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h899112 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h899112 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h899115 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h899115 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h899115 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h899115 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h899112 = + thin_otype__h899115 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h899112 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h899112 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h899112 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h899112 = + 5'd28: thin_otype__h899115 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h899115 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h899115 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h899115 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -56736,17 +56736,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254472); + $write("'h%h", value__h254474); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254636); + $write("'h%h", value__h254638); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h254748[64:0]); + $write("'h%h", x__h254750[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58540,14 +58540,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h213411 = $time; + v__h213412 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h213411, "[doRespLdMem]", " "); + $write("%t : ", v__h213412, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212839); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212840); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58686,15 +58686,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h215680 = $time; + v__h215681 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h215680, "[doRespLdForward]", " "); + $write("%t : ", v__h215681, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h215125); + $write("'h%h", t__h215126); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58919,17 +58919,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239691); + $write("'h%h", value__h239693); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239855); + $write("'h%h", value__h239857); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h239967[64:0]); + $write("'h%h", x__h239969[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58969,17 +58969,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240848); + $write("'h%h", value__h240850); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h241012); + $write("'h%h", value__h241014); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h241124[64:0]); + $write("'h%h", x__h241126[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -67212,14 +67212,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) begin - v__h271938 = $time; + v__h271939 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) - $write("%t : [Ld resp] ", v__h271938); + $write("%t : [Ld resp] ", v__h271939); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -68859,13 +68859,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) begin - v__h347456 = $time; + v__h347457 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) - $write("%t : [Ld resp] ", v__h347456); + $write("%t : [Ld resp] ", v__h347457); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) @@ -70739,7 +70739,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h423782 = $time; + v__h423783 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -70747,7 +70747,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h423782); + $write("%t : [Ld resp] ", v__h423783); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && diff --git a/src_SSITH_P3/Verilog_RTL/mkCoreW.v b/src_SSITH_P3/Verilog_RTL/mkCoreW.v index 97af342..c33a462 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:12:58 BST 2020 +// On Mon Jul 6 19:26:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v index f19e789..e51786f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:40 BST 2020 +// On Mon Jul 6 19:21:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v index b2d1d32..5333400 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:35 BST 2020 +// On Mon Jul 6 19:14:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v index 8aa4e5c..97e03b0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:34 BST 2020 +// On Mon Jul 6 19:14:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v index 1288abf..b84cbf5 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:49 BST 2020 +// On Mon Jul 6 19:14:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v index 3d0951d..d6b5c8c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:41 BST 2020 +// On Mon Jul 6 19:21:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v index 32f3f60..1777d02 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:44 BST 2020 +// On Mon Jul 6 19:21:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v index ebb74d4..23c7868 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:13 BST 2020 +// On Mon Jul 6 19:22:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v index 9638caa..e5c6baf 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:50 BST 2020 +// On Mon Jul 6 19:14:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v index a74134e..e9a40c4 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:28 BST 2020 +// On Mon Jul 6 19:23:31 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v index 7eae238..b2ff1d9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:31 BST 2020 +// On Mon Jul 6 19:23:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v index e76bdf2..97e6b47 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:12 BST 2020 +// On Mon Jul 6 19:23:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v index 7883f66..39b6a8c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:17 BST 2020 +// On Mon Jul 6 19:23:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v index 977007a..26d852a 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:14 BST 2020 +// On Mon Jul 6 19:23:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v index b1eafde..e1dead6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:40 BST 2020 +// On Mon Jul 6 19:15:31 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v index 3053991..d807ba1 100644 --- a/src_SSITH_P3/Verilog_RTL/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:30 BST 2020 +// On Mon Jul 6 19:15:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v index 1327a8d..3e4955c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:42 BST 2020 +// On Mon Jul 6 19:23:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v index 066d9ca..ddee3d2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:20 BST 2020 +// On Mon Jul 6 19:23:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v index 44deef1..cd12bfc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:33 BST 2020 +// On Mon Jul 6 19:23:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v index 9e62170..23f9cc8 100644 --- a/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:33 BST 2020 +// On Mon Jul 6 19:23:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v index ab9d6c8..800f46f 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:25 BST 2020 +// On Mon Jul 6 19:23:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v index 46b1522..b7225f6 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:25 BST 2020 +// On Mon Jul 6 19:23:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v index d6cc216..97d4594 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v index 9759d34..5416d95 100644 --- a/src_SSITH_P3/Verilog_RTL/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v index bbf929a..8e24637 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:50 BST 2020 +// On Mon Jul 6 19:21:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v index 76020c1..9f10803 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:45 BST 2020 +// On Mon Jul 6 19:21:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkICoCache.v b/src_SSITH_P3/Verilog_RTL/mkICoCache.v index 7673da5..357a458 100644 --- a/src_SSITH_P3/Verilog_RTL/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:51 BST 2020 +// On Mon Jul 6 19:21:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v index 40ccefb..8746370 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:45 BST 2020 +// On Mon Jul 6 19:21:38 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v index e2ad67f..1c6ca35 100644 --- a/src_SSITH_P3/Verilog_RTL/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:49 BST 2020 +// On Mon Jul 6 19:21:41 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkITlb.v b/src_SSITH_P3/Verilog_RTL/mkITlb.v index 47dab80..114c598 100644 --- a/src_SSITH_P3/Verilog_RTL/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:28 BST 2020 +// On Mon Jul 6 19:15:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v index b442c38..5d63a28 100644 --- a/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:17 BST 2020 +// On Mon Jul 6 19:21:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLLCache.v b/src_SSITH_P3/Verilog_RTL/mkLLCache.v index 1d30beb..0c308ab 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:04 BST 2020 +// On Mon Jul 6 19:22:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v index 7bc651f..0b35c83 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:53 BST 2020 +// On Mon Jul 6 19:22:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v index 0077468..3ecd888 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:44 BST 2020 +// On Mon Jul 6 19:19:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v index 2b7c212..e635727 100644 --- a/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:45 BST 2020 +// On Mon Jul 6 19:22:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v index 9a95fb0..a26ccb1 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:19 BST 2020 +// On Mon Jul 6 19:15:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v index c41bb4a..d8ac626 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:05 BST 2020 +// On Mon Jul 6 19:21:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v index 03d1029..d5688d9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:21 BST 2020 +// On Mon Jul 6 19:22:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v index b4115d3..64169ac 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:05 BST 2020 +// On Mon Jul 6 19:21:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v index 7bbef51..dd9c600 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:19 BST 2020 +// On Mon Jul 6 19:23:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v index 1b3225e..616a61d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:31 BST 2020 +// On Mon Jul 6 19:23:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v index 040147d..c1d1f5c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:13 BST 2020 +// On Mon Jul 6 19:15:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v index 56a6e83..f82db2b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:13:07 BST 2020 +// On Mon Jul 6 19:26:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v index 4739fc7..e98f4dc 100644 --- a/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:43 BST 2020 +// On Mon Jul 6 19:14:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkProc.v b/src_SSITH_P3/Verilog_RTL/mkProc.v index 7ee018f..0ce2651 100644 --- a/src_SSITH_P3/Verilog_RTL/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:12:47 BST 2020 +// On Mon Jul 6 19:25:52 BST 2020 // // // Ports: @@ -1884,8 +1884,8 @@ module mkProc(CLK, MUX_llc$dma_memReq_enq_1__VAL_2, MUX_llc$dma_memReq_enq_1__VAL_3, MUX_llc$dma_memReq_enq_1__VAL_4; - wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2, - MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1; + wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, + MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; wire [515 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [214 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, @@ -1927,7 +1927,7 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7, + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6, MUX_llc$dma_memReq_enq_1__SEL_1, MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, @@ -1948,46 +1948,46 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h224139; - reg [31 : 0] v__h223691; + reg [31 : 0] v__h226276; + reg [31 : 0] v__h225828; reg [31 : 0] v__h9702; reg [31 : 0] v__h9897; reg [31 : 0] v__h11245; reg [31 : 0] v__h17177; - reg [31 : 0] v__h17348; - reg [31 : 0] v__h17740; - reg [31 : 0] v__h18150; + reg [31 : 0] v__h17357; + reg [31 : 0] v__h17749; + reg [31 : 0] v__h18159; reg [31 : 0] v__h2280; reg [31 : 0] v__h7388; - reg [31 : 0] v__h20462; - reg [31 : 0] v__h21008; - reg [31 : 0] v__h21530; - reg [31 : 0] v__h201342; - reg [31 : 0] v__h215051; - reg [31 : 0] v__h193319; - reg [31 : 0] v__h222677; - reg [31 : 0] v__h193908; - reg [31 : 0] v__h194094; + reg [31 : 0] v__h20472; + reg [31 : 0] v__h21018; + reg [31 : 0] v__h21540; + reg [31 : 0] v__h203428; + reg [31 : 0] v__h217146; + reg [31 : 0] v__h193329; + reg [31 : 0] v__h224814; + reg [31 : 0] v__h193918; + reg [31 : 0] v__h194104; reg [31 : 0] v__h2274; reg [31 : 0] v__h7382; reg [31 : 0] v__h9696; reg [31 : 0] v__h9891; reg [31 : 0] v__h11239; reg [31 : 0] v__h17171; - reg [31 : 0] v__h17342; - reg [31 : 0] v__h17734; - reg [31 : 0] v__h18144; - reg [31 : 0] v__h20456; - reg [31 : 0] v__h21002; - reg [31 : 0] v__h21524; - reg [31 : 0] v__h193313; - reg [31 : 0] v__h193902; - reg [31 : 0] v__h194088; - reg [31 : 0] v__h201336; - reg [31 : 0] v__h215045; - reg [31 : 0] v__h222671; - reg [31 : 0] v__h223685; - reg [31 : 0] v__h224133; + reg [31 : 0] v__h17351; + reg [31 : 0] v__h17743; + reg [31 : 0] v__h18153; + reg [31 : 0] v__h20466; + reg [31 : 0] v__h21012; + reg [31 : 0] v__h21534; + reg [31 : 0] v__h193323; + reg [31 : 0] v__h193912; + reg [31 : 0] v__h194098; + reg [31 : 0] v__h203422; + reg [31 : 0] v__h217140; + reg [31 : 0] v__h224808; + reg [31 : 0] v__h225822; + reg [31 : 0] v__h226270; // synopsys translate_on // remaining internal signals @@ -1995,121 +1995,121 @@ module mkProc(CLK, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971, - dword__h150359, - ld_data__h188181, - v_wdata__h215359, - wflit_wdata__h17678; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384; - reg [7 : 0] v_wstrb__h215360, wflit_wstrb__h17679; - reg [5 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844; - reg [2 : 0] x__h100956; - reg [1 : 0] CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973, + dword__h150369, + ld_data__h188191, + v_wdata__h217505, + wflit_wdata__h17687; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386; + reg [7 : 0] v_wstrb__h217506, wflit_wstrb__h17688; + reg [5 : 0] IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846; + reg [2 : 0] x__h100966; + reg [1 : 0] CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710, - v_wuser__h215362, - x__h100957, - x__h127593; - wire [583 : 0] IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1681; - wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830; - wire [517 : 0] IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680; - wire [515 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807; - wire [129 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164; - wire [128 : 0] amoExec___d1006, - amoExec___d1076, - amoExec___d1129, - amoExec___d1354, - amoExec___d920, + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712, + v_wuser__h217508, + x__h100967, + x__h127603; + wire [583 : 0] IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1683; + wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1832; + wire [517 : 0] IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1682; + wire [515 : 0] IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674, + IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1827; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2021, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1809; + wire [129 : 0] IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1166; + wire [128 : 0] amoExec___d1008, + amoExec___d1078, + amoExec___d1131, + amoExec___d1356, + amoExec___d922, mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1773, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1790, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1824; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1775, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1792, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1826; wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34, llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32; wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33; wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31; - wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546, - IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544; - wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159, - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918, - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054, - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982, - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106, - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604, - addr1__h90533, - data__h140632, - failed_testnum__h223734, - line_addr__h140065, - line_addr__h150176, - line_addr__h193455, - mmioPlatform_mtime__h59831, - newData__h45219, - newData__h53320, - v_awaddr__h214948, - value__h61538, - x__h48532, - x__h56610, - x__h64490, - x__h68445, - x__h71119, - x__h73614, - x__h79161; - wire [47 : 0] IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1145, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947; - wire [31 : 0] IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1140, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938, - IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389, - amo_req_data__h39114, - lower_data__h44520, + wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548, + IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546; + wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161, + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108, + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606, + addr1__h90543, + data__h140642, + failed_testnum__h225871, + line_addr__h140075, + line_addr__h150186, + line_addr__h193465, + mmioPlatform_mtime__h59841, + newData__h45229, + newData__h53330, + v_awaddr__h217034, + value__h61548, + x__h48542, + x__h56620, + x__h64500, + x__h68455, + x__h71129, + x__h73624, + x__h79171; + wire [47 : 0] IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1147, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949; + wire [31 : 0] IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1142, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940, + IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391, + amo_req_data__h39124, + lower_data__h44530, mmioPlatform_mtime_BITS_31_TO_0__q8, mmioPlatform_mtime_BITS_63_TO_32__q7, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, - upper_data__h44521, - v__h44376, - v__h44413, - x_data__h42055; - wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1533; - wire [7 : 0] IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905, + upper_data__h44531, + v__h44386, + v__h44423, + x_data__h42065; + wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535; + wire [7 : 0] IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907, mem_req_rd_addr_arlen__h5411, - mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910; + mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912; wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30; - wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1532, + wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534, x__h15143, x__h15155, x__h15167, @@ -2140,103 +2140,112 @@ module mkProc(CLK, y__h15288, y__h15300, y__h15312; - wire [3 : 0] b__h193255, b__h2174, mmioPlatform_reqAmofunc__h88303; - wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1748, - _theResult_____1_awsize_val__h17116; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609; - wire IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962, - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818, - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957, - IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678, - IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101, - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1171, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367, - IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883, - IF_mmio_axi4_adapter_f_rsps_to_core_first__291_ETC___d1367, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630, - IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479, - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416, - IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712, - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549, - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556, - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423, - NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539, - NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836, - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241, - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320, - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1310, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1358, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1370, - NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714, + wire [3 : 0] b__h193265, b__h2174, mmioPlatform_reqAmofunc__h88313; + wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1750, + _theResult_____1_awsize_val__h17116, + x__h194318, + x__h217392; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611; + wire IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964, + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820, + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959, + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680, + IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103, + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1173, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369, + IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885, + IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632, + IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481, + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418, + IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714, + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551, + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558, + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425, + NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541, + NOT_enqDst_1_0_rl_642_BIT_584_643_648_AND_SEL__ETC___d1838, + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243, + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2323, + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2326, + NOT_llc_axi4_adapter_rg_wr_req_beat_345_EQ_0_3_ETC___d2359, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1196, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1291, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1302, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1312, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1360, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1372, + NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995, + NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716, _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, _theResult____h13492, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788, - core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936, - mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307, - mmioPlatform_cycle_90_ULT_99___d491, - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372, - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029, - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974, - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253, - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790, + core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2301, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2304, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2309, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2312, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2317, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2320, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938, + mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309, + mmioPlatform_cycle_92_ULT_99___d493, + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374, + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031, + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217, + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221, whichHalf___1__h15055, - x__h100756, + x__h100766, x__h10399, - x__h116294, - x__h122858, - x__h17610; + x__h116304, + x__h122868, + x__h17619; // action method start assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; @@ -2974,7 +2983,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && - IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447 ; + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -2998,7 +3007,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642 ; + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3099,7 +3108,7 @@ module mkProc(CLK, // rule RL_mmio_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 && + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -3139,23 +3148,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_90_ULT_99___d491 ; + mmioPlatform_cycle_92_ULT_99___d493 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_90_ULT_99___d491 ; + !mmioPlatform_cycle_92_ULT_99___d493 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513 && + NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3172,7 +3181,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819 && + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3181,7 +3190,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883 && + IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3227,7 +3236,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h73614 == 64'd0 || + x__h73624 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3245,7 +3254,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1196 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3253,37 +3262,37 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1291 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1302 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307 && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1310 ; + mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309 && + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1312 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1358 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1360 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__291_ETC___d1367 && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1370 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369 && + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1372 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3397,7 +3406,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3465,7 +3474,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3477,7 +3486,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3496,7 +3505,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3507,7 +3516,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3520,7 +3529,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3530,7 +3539,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3610,10 +3619,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_clearing && llc$RDY_to_mem_toM_first && !llc_axi4_adapter_master_xactor_shim_wff_rv[74] && - (llc_axi4_adapter_rg_wr_req_beat != 3'd0 || - !llc_axi4_adapter_master_xactor_shim_awff_rv[98]) && - (llc_axi4_adapter_rg_wr_req_beat != 3'd7 || - llc$RDY_to_mem_toM_deq) && + NOT_llc_axi4_adapter_rg_wr_req_beat_345_EQ_0_3_ETC___d2359 && llc$to_mem_toM_first[644] ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -3626,7 +3632,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && - b__h193255 == 4'd0 ; + b__h193265 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -3688,7 +3694,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = !llc_axi4_adapter_master_xactor_clearing && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] && - b__h193255 != 4'd0 ; + b__h193265 != 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; @@ -3729,7 +3735,10 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && + (!llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] || + llc$RDY_to_mem_rsFromM_enq && + llc_axi4_adapter_f_pending_reads$EMPTY_N) ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3742,7 +3751,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 ; + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3750,27 +3759,27 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 || + (!mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 = + assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; assign MUX_llc$dma_memReq_enq_1__SEL_1 = @@ -3798,12 +3807,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && @@ -3831,28 +3840,28 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_shim_rff$D_OUT[1] ; - assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = + assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = { 1'd1, llc$to_child_toC_first[586:521], llc$to_child_toC_first[519:0] } ; - assign MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1 = + assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amo_req_data__h39114 : - x_data__h42055 } ; + amo_req_data__h39124 : + x_data__h42065 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -3868,42 +3877,42 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 67'h60000000000000000, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 3'd6, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 65'h0AAAAAAAAAAAAAAAA, - mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392 } ; + mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = - { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { 2'd3, mmioPlatform_amoResp } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = + { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { 3'd6, mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h44376, 32'd0 }, + { v__h44386, 32'd0 }, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1166 } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = { llc_mem_server_rg_cacheline_cache_addr, 64'hFFFFFFFFFFFFFFFF, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h140065, + { line_addr__h140075, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h150176, + { line_addr__h150186, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3923,14 +3932,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2021, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd0) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -3938,21 +3947,21 @@ module mkProc(CLK, { 65'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 } ; + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 } ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = { 1'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056, 64'd0 } ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) ? + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) ? 67'h1AAAAAAAAAAAAAAAA : - ((!core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) ? + ((!core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) ? 67'h2AAAAAAAAAAAAAAAA : - IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546) ; + IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, (mmioPlatform_instSel == 2'd3) ? @@ -3965,11 +3974,11 @@ module mkProc(CLK, mmioPlatform_instSel + 2'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) ? + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_3 = @@ -3980,32 +3989,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 or + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 or + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_5 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_5 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_5 = - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4013,30 +4022,30 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_6 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - (mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ? + (mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - amoExec___d1354 } ; + amoExec___d1356 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { addr1__h90533, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + { addr1__h90543, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = @@ -4047,47 +4056,47 @@ module mkProc(CLK, 129'd0 } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73614 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73624 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h73614 != 64'd0 ; + x__h73624 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h68445 == 64'd0 ; + x__h68455 == 64'd0 ; assign propDstIdx_1_lat_1$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 && - x__h100756 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 && + x__h100766 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, - SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1533 } ; + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535 } ; assign enqDst_0_lat_0$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 ; assign propDstIdx_1_1_lat_1$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 && - x__h122858 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 && + x__h122868 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830 } ; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1832 } ; assign enqDst_1_0_lat_0$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 ; assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { debug_module_mem_server_awid, debug_module_mem_server_awaddr, @@ -4126,10 +4135,10 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 } ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110 } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = @@ -4161,7 +4170,7 @@ module mkProc(CLK, master0_arready ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = @@ -4234,7 +4243,7 @@ module mkProc(CLK, assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 = { 1'd1, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[97:93], - dword__h150359, + dword__h150369, 4'd2 } ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? @@ -4252,7 +4261,7 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 6'd32, v_awaddr__h214948, 29'd15532032 } ; + { 6'd32, v_awaddr__h217034, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read = llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : @@ -4267,10 +4276,10 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - v_wdata__h215359, - v_wstrb__h215360, + v_wdata__h217505, + v_wstrb__h217506, llc_axi4_adapter_rg_wr_req_beat == 3'd7, - v_wuser__h215362 } ; + v_wuser__h217508 } ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : @@ -4299,7 +4308,7 @@ module mkProc(CLK, 8'd42 : llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 6'd32, line_addr__h193455, 29'd15532032 } ; + { 6'd32, line_addr__h193465, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ? llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : @@ -4333,11 +4342,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h193255 - 4'd1 ; + b__h193265 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h193255 ; + b__h193265 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4349,7 +4358,7 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447, + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : (enqDst_0_lat_0$whas ? @@ -4360,8 +4369,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642, - IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1681 } ; + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644, + IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1683 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4405,19 +4414,23 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ? + 516'd0 : + IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; // register llc_axi4_adapter_rg_rd_rsp_beat assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN = - llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ? + 3'd0 : + x__h194318 ; assign llc_axi4_adapter_rg_rd_rsp_beat$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; // register llc_axi4_adapter_rg_wr_req_beat assign llc_axi4_adapter_rg_wr_req_beat$D_IN = - llc_axi4_adapter_rg_wr_req_beat + 3'd1 ; + (llc_axi4_adapter_rg_wr_req_beat == 3'd7) ? 3'd0 : x__h217392 ; assign llc_axi4_adapter_rg_wr_req_beat$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4454,7 +4467,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, + IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4464,20 +4477,20 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h140065 : - line_addr__h150176 ; + line_addr__h140075 : + line_addr__h150186 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4560,7 +4573,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4573,11 +4586,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 && + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4587,11 +4600,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4642,16 +4655,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h53320 : + newData__h53330 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4660,7 +4673,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h45219 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h45229 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4670,9 +4683,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4781,7 +4794,7 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = !mmioPlatform_toHostQ_clearReq_rl && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4802,7 +4815,7 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = !mmioPlatform_toHostQ_clearReq_rl && - (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 || + (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl && mmioPlatform_toHostQ_full) ; @@ -4815,7 +4828,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4823,15 +4836,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -4860,7 +4873,7 @@ module mkProc(CLK, !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat && - x__h17610 ; + x__h17619 ; assign mmio_axi4_adapter_rg_wr_req_beat$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr ; @@ -4882,28 +4895,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571, + { IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[517] : propDstData_1_0_rl[517], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516:1] : propDstData_1_0_rl[516:1], - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592 } ; + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609, + { IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[517] : propDstData_1_1_rl[517], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516:1] : propDstData_1_1_rl[516:1], - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630 } ; + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -4915,26 +4928,26 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = - !NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539 && - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416 ; + !NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541 && + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = - !NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836 && - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549 ; + !NOT_enqDst_1_0_rl_642_BIT_584_643_648_AND_SEL__ETC___d1838 && + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 ; + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423 ; + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 @@ -4953,8 +4966,8 @@ module mkProc(CLK, assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq ? - MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1 : + WILL_FIRE_RL_sendPRs ? + MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; assign core_0$hart0_csr_mem_server_request_put = hart0_csr_mem_server_request_put ; @@ -4965,8 +4978,8 @@ module mkProc(CLK, assign core_0$hart0_run_halt_server_request_put = hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq_1 ? - MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1 : + WILL_FIRE_RL_sendPRs_1 ? + MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 or @@ -5002,9 +5015,9 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 or MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 or + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or WILL_FIRE_RL_mmioPlatform_waitMSIPDone or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or @@ -5029,10 +5042,10 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5; - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6; - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7: + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7; WILL_FIRE_RL_mmioPlatform_waitMSIPDone: @@ -5053,7 +5066,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h188181, llc$dma_respLd_first[3] } ; + { ld_data__h188191, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5061,11 +5074,11 @@ module mkProc(CLK, assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ; assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ; assign core_0$EN_dCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ; + WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ; assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; + WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ; assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_llc_mem_server_srcPropose ; assign core_0$EN_tlbToMem_respLd_enq = @@ -5076,31 +5089,31 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp || WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 || + (!mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMSIPDone || WILL_FIRE_RL_mmioPlatform_processToHost || WILL_FIRE_RL_mmioPlatform_processFromHost ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 || + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5182,13 +5195,13 @@ module mkProc(CLK, enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 } ; + { IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5215,7 +5228,7 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc$EN_to_mem_rsFromM_enq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ; assign llc$EN_cRqStuck_get = 1'b0 ; assign llc$EN_perf_setStatus = core_0$RDY_sendDoStats ; assign llc$EN_perf_req = 1'b0 ; @@ -5227,7 +5240,7 @@ module mkProc(CLK, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc_axi4_adapter_f_pending_reads$DEQ = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ; assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ; // submodule llc_mem_server_f_dword_in_line @@ -5342,7 +5355,7 @@ module mkProc(CLK, 18'd65536 } ; assign mmio_axi4_adapter_master_shim_awff$ENQ = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 ; assign mmio_axi4_adapter_master_shim_awff$DEQ = EN_master1_aw_drop ; assign mmio_axi4_adapter_master_shim_awff$CLR = 1'b0 ; @@ -5362,8 +5375,8 @@ module mkProc(CLK, // submodule mmio_axi4_adapter_master_shim_wff assign mmio_axi4_adapter_master_shim_wff$D_IN = - { wflit_wdata__h17678, - wflit_wstrb__h17679, + { wflit_wdata__h17687, + wflit_wstrb__h17688, whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, @@ -5381,41 +5394,41 @@ module mkProc(CLK, assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current({ 65'd0, - value__h61538 }), + value__h61548 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d920)); - module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d922)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current({ 65'd0, - mmioPlatform_mtime__h59831 }), + mmioPlatform_mtime__h59841 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1006)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1008)); + module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current(129'd0), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1076)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1078)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), - .amoExec_current({ 65'd0, x__h79161 }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), + .amoExec_current({ 65'd0, x__h79171 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1129)); - module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88303, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1131)); + module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88313, ((mmioPlatform_reqBE[0] ? 5'd1 : 5'd0) + @@ -5471,294 +5484,294 @@ module mkProc(CLK, .amoExec_wordIdx(mmioPlatform_curReq[3:2]), .amoExec_current(mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0]), .amoExec_inpt(mmioPlatform_reqData), - .amoExec(amoExec___d1354)); - assign IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962 = - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + .amoExec(amoExec___d1356)); + assign IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964 = + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_mtime[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_mtime[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_mtime[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_mtime[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1140 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1142 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_fromHostQ_data_0[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_fromHostQ_data_0[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_fromHostQ_data_0[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1145 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1140, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1147 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1142, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_fromHostQ_data_0[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_mtimecmp_0[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_mtimecmp_0[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_mtimecmp_0[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_mtimecmp_0[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546 = - (!core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) ? + assign IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548 = + (!core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) ? 67'h3AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544) ; - assign IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818 = + IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546) ; + assign IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 = - newData__h45219 <= mmioPlatform_mtime ; - assign IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544 = - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 ? + assign IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 = + newData__h45229 <= mmioPlatform_mtime ; + assign IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546 = + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 ? 67'h5AAAAAAAAAAAAAAAA : - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ? + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ; - assign IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447 = + assign IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449 = enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[584] : enqDst_1_0_rl[584] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[583:520] : enqDst_1_0_rl[583:520] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[519:518] : enqDst_1_0_rl[519:518] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[517] : enqDst_1_0_rl[517] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[516:1] : enqDst_1_0_rl[516:1] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680 = + assign IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1682 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664, CAN_FIRE_RL_doEnq_1 ? 516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - x__h116294 } ; - assign IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1681 = + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674, + x__h116304 } ; + assign IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1683 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, - IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 = + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659, + IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1682 } ; + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2021 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd6) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd5) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd4) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[319:256], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd3) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd2) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389 = + assign IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391 = mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 ; - assign IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 ; + assign IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161 = (mmioPlatform_fromHostQ_empty || mmioPlatform_fromHostAddr[0]) ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157 = + assign IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159 = mmioPlatform_fromHostQ_empty ? 64'd0 : (mmioPlatform_fromHostAddr[0] ? mmioPlatform_fromHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038 = - ((mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + assign IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040 = + ((mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905 = + assign IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 8'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqBE[15:8] : mmioPlatform_reqBE[7:0]) ; - assign IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 = + assign IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 64'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqData[127:64] : mmioPlatform_reqData[63:0]) ; - assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 = + assign IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q7 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q8 } ; - assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 = + assign IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, + { IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102, 1'd0, - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164 = + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108 } ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1166 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154, + { IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156, 1'd0, - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819 = + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161 } ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055 = + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982 = + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100 = + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? mmioPlatform_toHostQ_empty : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h73614 == 64'd0 : - x__h68445 == 64'd0) : + x__h73624 == 64'd0 : + x__h68455 == 64'd0) : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1171 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1173 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h73614 != 64'd0 : - x__h68445 != 64'd0) : + x__h73624 != 64'd0 : + x__h68455 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; - assign IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106 = + assign IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108 = (mmioPlatform_toHostQ_empty || mmioPlatform_toHostAddr[0]) ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104 = + assign IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106 = mmioPlatform_toHostQ_empty ? 64'd0 : (mmioPlatform_toHostAddr[0] ? mmioPlatform_toHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 = + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883 = + assign IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -5766,82 +5779,85 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__291_ETC___d1367 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 = + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_wff$FULL_N && - (!whichHalf___1__h15055 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && - mmio_axi4_adapter_rg_wr_req_beat || - mmio_axi4_adapter_master_shim_awff$FULL_N) : + NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208 : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566 = + assign IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[583:520] : propDstData_1_0_rl[583:520] ; - assign IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571 = + assign IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[519:518] : propDstData_1_0_rl[519:518] ; - assign IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592 = + assign IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604 = + assign IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[583:520] : propDstData_1_1_rl[583:520] ; - assign IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609 = + assign IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[519:518] : propDstData_1_1_rl[519:518] ; - assign IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630 = + assign IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479 = + assign IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 = !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416 = + assign IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 = + assign IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714 = !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549 = + assign IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 = + assign IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423 = + assign IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539 = + assign NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 && - (SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 ? + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 && + (SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 ? !srcRR_0 : - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416) ; - assign NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836 = + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418) ; + assign NOT_enqDst_1_0_rl_642_BIT_584_643_648_AND_SEL__ETC___d1838 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 && - (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 ? + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 && + (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 ? !srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 = + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320 = - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2323 = + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323 = - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2326 = + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194 = + assign NOT_llc_axi4_adapter_rg_wr_req_beat_345_EQ_0_3_ETC___d2359 = + (llc_axi4_adapter_rg_wr_req_beat != 3'd0 || + llc_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 && + !llc_axi4_adapter_master_xactor_shim_awff_rv[98]) && + (llc_axi4_adapter_rg_wr_req_beat != 3'd7 || + llc$RDY_to_mem_toM_deq) ; + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1196 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5852,7 +5868,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1291 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5863,7 +5879,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1302 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5875,7 +5891,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1310 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1312 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5887,7 +5903,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1358 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1360 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5897,7 +5913,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1370 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1372 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5907,90 +5923,96 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513 = + assign NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (!mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (!IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || !mmioPlatform_mtip_0) ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1532 = - { CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, - x__h100956, - x__h100957 } ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1533 = - { CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, - SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1532 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1748 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1773 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1790 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1773, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1790, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1824 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1748, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1824 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830 = - { CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, - !CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825, - x__h127593 } ; - assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 || - (IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479 ? - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423 : - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416) ; - assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 || - (IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 ? - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 : - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; + assign NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208 = + !whichHalf___1__h15055 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + mmio_axi4_adapter_rg_wr_req_beat || + mmio_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 && + mmio_axi4_adapter_master_shim_awff$FULL_N ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534 = + { CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + x__h100966, + x__h100967 } ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535 = + { CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1750 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1775 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1792 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1809 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1775, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1792, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1826 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1827 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1750, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1809, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1826 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1832 = + { CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, + !CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1827, + x__h127603 } ; + assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 || + (IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 ? + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 : + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418) ; + assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 || + (IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714 ? + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558 : + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551) ; assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && (whichHalf___1__h15055 || @@ -6004,8 +6026,8 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? whichHalf___1__h15055 : mmio_axi4_adapter_rg_wr_req_beat ; - assign addr1__h90533 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign amo_req_data__h39114 = + assign addr1__h90543 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign amo_req_data__h39124 = (mmioPlatform_reqBE[3:0] == 4'd0 && mmioPlatform_reqBE[7:4] == 4'd0 && mmioPlatform_reqBE[11:8] == 4'd0 && @@ -6021,7 +6043,7 @@ module mkProc(CLK, ((mmioPlatform_reqBE[3:0] == 4'd0) ? mmioPlatform_reqData[63:32] : mmioPlatform_reqData[31:0]))) ; - assign b__h193255 = + assign b__h193265 = llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6029,205 +6051,236 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554432 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556480 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_toHostAddr ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_fromHostAddr ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 ; + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ; + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ; - assign core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764 = + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ; + assign core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766 = core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530 ; - assign data__h140632 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532 ; + assign data__h140642 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[7:0] } ; - assign failed_testnum__h223734 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[7:0] } ; + assign failed_testnum__h225871 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h140065 = + assign line_addr__h140075 = { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h150176 = + assign line_addr__h150186 = { llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h193455 = { llc$to_mem_toM_first[68:11], 6'h0 } ; + assign line_addr__h193465 = { llc$to_mem_toM_first[68:11], 6'h0 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34 = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 = - llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && - (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || - llc$RDY_to_mem_rsFromM_enq && - llc_axi4_adapter_f_pending_reads$EMPTY_N) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2301 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[512] : + !llc_axi4_adapter_rg_cline[513]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2304 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[512] : + llc_axi4_adapter_rg_cline[513]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2309 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[513] : + !llc_axi4_adapter_rg_cline[514]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2312 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[513] : + llc_axi4_adapter_rg_cline[514]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2317 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[514] : + !llc_axi4_adapter_rg_cline[515]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2320 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[514] : + llc_axi4_adapter_rg_cline[515]) ; assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 = - line_addr__h150176 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 = - line_addr__h140065 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 = + line_addr__h150186 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 = + line_addr__h140075 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31 = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ; - assign lower_data__h44520 = - mmioPlatform_waitLowerMSIPCRs ? v__h44413 : 32'd0 ; + assign lower_data__h44530 = + mmioPlatform_waitLowerMSIPCRs ? v__h44423 : 32'd0 ; assign mem_req_rd_addr_arlen__h5411 = (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? 8'd1 : 8'd0 ; - assign mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307 = + assign mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309 = mmioPlatform_amoWaitWriteResp || core_0$RDY_mmioToPlatform_pRs_enq && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) ; - assign mmioPlatform_cycle_90_ULT_99___d491 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 = + assign mmioPlatform_cycle_92_ULT_99___d493 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h59831 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 = - mmioPlatform_mtimecmp_0 <= newData__h53320 ; - assign mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 = + assign mmioPlatform_mtime__h59841 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 = + mmioPlatform_mtimecmp_0 <= newData__h53330 ; + assign mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd0 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd1 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd2 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd3 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd4 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd5 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd6 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd7 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd8 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -6241,45 +6294,45 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_first[148:145] != 4'd6 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd7 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd8 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525 ; - assign mmioPlatform_reqAmofunc__h88303 = mmioPlatform_reqAmofunc ; - assign mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910 = + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527 ; + assign mmioPlatform_reqAmofunc__h88313 = mmioPlatform_reqAmofunc ; + assign mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912 = { mmioPlatform_reqFunc[3:0], - (IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0]) ? + (IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0]) ? 2'd1 : 2'd2, 2'd0 } ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (!mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (!IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || !mmioPlatform_mtip_0) ; - assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257 = (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_cfg_verbosity != 4'd0 ; - assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261 = (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && @@ -6289,14 +6342,14 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_arff$FULL_N : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392 = + assign mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394 = { mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmioPlatform_fetchingWay, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389 : + IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391 : mmioPlatform_fetchedInsts_0 } ; assign mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 = mmio_axi4_adapter_read_req_addr[3] + @@ -6308,43 +6361,43 @@ module mkProc(CLK, mmio_axi4_adapter_rspData[63:0] } : { mmio_axi4_adapter_rspData[127:64], mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; - assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 = + assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 = mmio_axi4_adapter_soc_map$m_is_IO_addr && (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) ; - assign newData__h45219 = + assign newData__h45229 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d920[63:0] : - x__h48532 ; - assign newData__h53320 = + amoExec___d922[63:0] : + x__h48542 ; + assign newData__h53330 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1006[63:0] : - x__h56610 ; - assign upper_data__h44521 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44376 ; - assign v__h44376 = mmioPlatform_waitUpperMSIPCRs ? v__h44413 : 32'd0 ; - assign v__h44413 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign v_awaddr__h214948 = { llc$to_mem_toM_first[643:586], 6'h0 } ; - assign value__h61538 = mmioPlatform_mtimecmp_0 ; + amoExec___d1008[63:0] : + x__h56620 ; + assign upper_data__h44531 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44386 ; + assign v__h44386 = mmioPlatform_waitUpperMSIPCRs ? v__h44423 : 32'd0 ; + assign v__h44423 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign v_awaddr__h217034 = { llc$to_mem_toM_first[643:586], 6'h0 } ; + assign value__h61548 = mmioPlatform_mtimecmp_0 ; assign whichHalf___1__h15055 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; - assign x__h100756 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 ? + assign x__h100766 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 ? srcRR_0 : - IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479 ; + IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 ; assign x__h10399 = mmio_axi4_adapter_rg_rd_rsp_beat + 1'd1 ; - assign x__h116294 = + assign x__h116304 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 ; - assign x__h122858 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 ? + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680 ; + assign x__h122868 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 ? srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 ; + IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714 ; assign x__h15143 = x__h15155 + y__h15156 ; assign x__h15155 = x__h15167 + y__h15168 ; assign x__h15167 = x__h15179 + y__h15180 ; @@ -6360,70 +6413,72 @@ module mkProc(CLK, assign x__h15287 = x__h15299 + y__h15300 ; assign x__h15299 = x__h15311 + y__h15312 ; assign x__h15311 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144] } ; - assign x__h17610 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; - assign x__h48532 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + assign x__h17619 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; + assign x__h194318 = llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; + assign x__h217392 = llc_axi4_adapter_rg_wr_req_beat + 3'd1 ; + assign x__h48542 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_mtimecmp_0[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign x__h56610 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + assign x__h56620 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_mtime[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_mtime[7:0] } ; - assign x__h64490 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign x__h64500 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : 8'd0 } ; - assign x__h68445 = + assign x__h68455 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1129[63:0] : - x__h71119 ; - assign x__h71119 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1145, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + amoExec___d1131[63:0] : + x__h71129 ; + assign x__h71129 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1147, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_fromHostQ_data_0[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign x__h73614 = + assign x__h73624 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1076[63:0] : - x__h64490 ; - assign x__h79161 = mmioPlatform_fromHostQ_data_0 ; - assign x_data__h42055 = { 31'd0, mmioPlatform_reqData[0] } ; + amoExec___d1078[63:0] : + x__h64500 ; + assign x__h79171 = mmioPlatform_fromHostQ_data_0 ; + assign x_data__h42065 = { 31'd0, mmioPlatform_reqData[0] } ; assign y__h15144 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[129] } ; assign y__h15156 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[130] } ; assign y__h15168 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[131] } ; @@ -6442,14 +6497,14 @@ module mkProc(CLK, always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h188181 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h188181 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h188181 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h188181 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h188181 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h188181 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h188181 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h188181 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h188191 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h188191 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h188191 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h188191 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h188191 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h188191 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h188191 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h188191 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) @@ -6504,40 +6559,40 @@ module mkProc(CLK, begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) 2'd0: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1; 2'd1: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2; 2'd2: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3; 2'd3: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: v_wstrb__h215360 = llc$to_mem_toM_first[523:516]; - 3'd1: v_wstrb__h215360 = llc$to_mem_toM_first[531:524]; - 3'd2: v_wstrb__h215360 = llc$to_mem_toM_first[539:532]; - 3'd3: v_wstrb__h215360 = llc$to_mem_toM_first[547:540]; - 3'd4: v_wstrb__h215360 = llc$to_mem_toM_first[555:548]; - 3'd5: v_wstrb__h215360 = llc$to_mem_toM_first[563:556]; - 3'd6: v_wstrb__h215360 = llc$to_mem_toM_first[571:564]; - 3'd7: v_wstrb__h215360 = llc$to_mem_toM_first[579:572]; + 3'd0: v_wstrb__h217506 = llc$to_mem_toM_first[523:516]; + 3'd1: v_wstrb__h217506 = llc$to_mem_toM_first[531:524]; + 3'd2: v_wstrb__h217506 = llc$to_mem_toM_first[539:532]; + 3'd3: v_wstrb__h217506 = llc$to_mem_toM_first[547:540]; + 3'd4: v_wstrb__h217506 = llc$to_mem_toM_first[555:548]; + 3'd5: v_wstrb__h217506 = llc$to_mem_toM_first[563:556]; + 3'd6: v_wstrb__h217506 = llc$to_mem_toM_first[571:564]; + 3'd7: v_wstrb__h217506 = llc$to_mem_toM_first[579:572]; endcase end always@(_theResult____h13492 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) begin case (_theResult____h13492) 1'd0: - wflit_wdata__h17678 = + wflit_wdata__h17687 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]; 1'd1: - wflit_wdata__h17678 = + wflit_wdata__h17687 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64]; endcase end @@ -6545,30 +6600,30 @@ module mkProc(CLK, begin case (_theResult____h13492) 1'd0: - wflit_wstrb__h17679 = + wflit_wstrb__h17688 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129]; 1'd1: - wflit_wstrb__h17679 = + wflit_wstrb__h17688 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) - 2'd0: v_wuser__h215362 = llc$to_mem_toM_first[512]; - 2'd1: v_wuser__h215362 = llc$to_mem_toM_first[513]; - 2'd2: v_wuser__h215362 = llc$to_mem_toM_first[514]; - 2'd3: v_wuser__h215362 = llc$to_mem_toM_first[515]; + 2'd0: v_wuser__h217508 = llc$to_mem_toM_first[512]; + 2'd1: v_wuser__h217508 = llc$to_mem_toM_first[513]; + 2'd2: v_wuser__h217508 = llc$to_mem_toM_first[514]; + 2'd3: v_wuser__h217508 = llc$to_mem_toM_first[515]; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844 = + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844 = + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6576,21 +6631,21 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 2'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 2'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; 2'd2: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64]; 2'd3: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962 or + IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6598,11 +6653,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = - IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962; + IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038 or + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6610,452 +6665,452 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038; + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040; endcase end always@(srcRR_0 or - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416 or - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423) + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 or + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425) begin case (srcRR_0) 1'd0: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 = - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 = + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418; 1'd1: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 = - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 = + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425; endcase end always@(srcRR_1_0 or - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549 or - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556) + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551 or + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558) begin case (srcRR_1_0) 1'd0: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 = - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 = + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551; 1'd1: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 = - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 = + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - x__h100956 = + x__h100966 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]; 1'd1: - x__h100956 = + x__h100966 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - x__h100957 = + x__h100967 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]; 1'd1: - x__h100957 = + x__h100967 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]; endcase end - always@(x__h122858 or - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592 or - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630) + always@(x__h122868 or + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594 or + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632) begin - case (x__h122858) + case (x__h122868) 1'd0: - x__h127593 = - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592; + x__h127603 = + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594; 1'd1: - x__h127593 = - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630; + x__h127603 = + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516] : propDstData_1_0_rl[516]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516] : propDstData_1_1_rl[516]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515] : propDstData_1_0_rl[515]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515] : propDstData_1_1_rl[515]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[514] : propDstData_1_0_rl[514]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[514] : propDstData_1_1_rl[514]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513]; endcase end - always@(x__h122858 or - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571 or - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609) + always@(x__h122868 or + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573 or + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573; 1'd1: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[517] : !propDstData_1_0_rl[517]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[517] : !propDstData_1_1_rl[517]; endcase end - always@(x__h122858 or - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566 or - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604) + always@(x__h122868 or + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568 or + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568; 1'd1: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606; endcase end always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or @@ -7063,28 +7118,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7092,14 +7147,14 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32]) - 3'd0: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7501,14 +7556,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h224139 = $stime; + v__h226276 = $stime; #0; end - v__h224133 = v__h224139 / 32'd10; + v__h226270 = v__h226276 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h224133, + v__h226270, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -7518,14 +7573,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h223691 = $stime; + v__h225828 = $stime; #0; end - v__h223685 = v__h223691 / 32'd10; + v__h225822 = v__h225828 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h223685, + v__h225822, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7535,7 +7590,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h223734); + $display("FAIL %0d", failed_testnum__h225871); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8147,7 +8202,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) begin v__h17177 = $stime; #0; @@ -8156,166 +8211,166 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $display("%d: %m.rl_handle_write_req: sent aw flit:", v__h17171); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", mem_req_rd_addr_arlen__h5411); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", _theResult_____1_awsize_val__h17116, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) begin - v__h17348 = $stime; + v__h17357 = $stime; #0; end - v__h17342 = v__h17348 / 32'd10; + v__h17351 = v__h17357 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) - $display("%0d: ERROR: CreditCounter: overflow", v__h17342); + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) + $display("%0d: ERROR: CreditCounter: overflow", v__h17351); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h17740 = $stime; + v__h17749 = $stime; #0; end - v__h17734 = v__h17740 / 32'd10; + v__h17743 = v__h17749 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: sent w flit:", v__h17734); + $display("%d: %m.rl_handle_write_req: sent w flit:", v__h17743); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8330,7 +8385,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", wflit_wdata__h17678); + $write("'h%h", wflit_wdata__h17687); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8340,7 +8395,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", wflit_wstrb__h17679); + $write("'h%h", wflit_wstrb__h17688); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8390,16 +8445,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h18150 = $stime; + v__h18159 = $stime; #0; end - v__h18144 = v__h18150 / 32'd10; + v__h18153 = v__h18159 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h18144); + v__h18153); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9652,14 +9707,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h20462 = $stime; + v__h20472 = $stime; #0; end - v__h20456 = v__h20462 / 32'd10; + v__h20466 = v__h20472 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h20456); + $display("%0d: %m.rl_discard_write_rsp", v__h20466); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9714,15 +9769,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) begin - v__h21008 = $stime; + v__h21018 = $stime; #0; end - v__h21002 = v__h21008 / 32'd10; + v__h21012 = v__h21018 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h21002); + v__h21012); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) @@ -9772,14 +9827,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h21530 = $stime; + v__h21540 = $stime; #0; end - v__h21524 = v__h21530 / 32'd10; + v__h21534 = v__h21540 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h21524); + v__h21534); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -10071,128 +10126,128 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write("[Platform - SelectReq] timer interrupt", ", mtime %x", mmioPlatform_mtime, ", mtimcmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(", old mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(", new interrupts "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("[Platform - SelectReq] core %d, req ", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write("tagged Inst ", "'h%h", core_0$mmioToPlatform_cRq_first[145]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write("tagged Ld ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write("tagged St ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -10201,542 +10256,542 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586) $write("Swap"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592) $write("Add"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598) $write("Xor"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604) $write("And"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610) $write("Or"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616) $write("Min"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622) $write("Max"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628) $write("Minu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634) $write("Maxu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656) $write("None"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("TaggedData { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[128]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && !core_0$mmioToPlatform_cRq_first[128]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" req type "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762) $write("tagged MSIP ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && - core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764) + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && + core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766) $write("tagged MTimeCmp ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769) + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771) $write("tagged MTime ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775) + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777) $write("tagged ToHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781) + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783) $write("tagged FromHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788) + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790) $write("tagged MMIO_Fabric_Adapter ", "'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) @@ -10799,8 +10854,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h44520, - upper_data__h44521); + lower_data__h44530, + upper_data__h44531); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -10812,62 +10867,62 @@ module mkProc(CLK, mmioPlatform_mtimecmp_0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write("[Platform - process mtimecmp] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(", mtime %x", mmioPlatform_mtime, ", old mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h45219, "\n"); + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) + $write(", new mtimecmp[%d] %x", 1'd0, newData__h45229, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -10912,61 +10967,61 @@ module mkProc(CLK, mmioPlatform_mtime); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write("[Platform - process mtime] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) - $write(", new mtime %x", newData__h53320, ", mtimecmp "); + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) + $write(", new mtime %x", newData__h53330, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeDone) @@ -11023,7 +11078,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11049,13 +11104,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11092,12 +11147,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1171) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1173) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11123,13 +11178,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11624,7 +11679,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", addr1__h90533); + $write("'h%h", addr1__h90543); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -11709,76 +11764,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display(" fetchingWay %0d instSel %0d inst 0x%0h", mmioPlatform_fetchingWay, mmioPlatform_instSel, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384); + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp: final resp to core:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && @@ -11846,16 +11901,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h201342 = $stime; + v__h203428 = $stime; #0; end - v__h201336 = v__h201342 / 32'd10; + v__h203422 = v__h203428 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h201336); + v__h203422); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -13312,15 +13367,15 @@ module mkProc(CLK, llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h215051 = $stime; + v__h217146 = $stime; #0; end - v__h215045 = v__h215051 / 32'd10; + v__h217140 = v__h217146 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h215045); + $display("%0d: ERROR: CreditCounter: overflow", v__h217140); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && @@ -13330,15 +13385,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h193319 = $stime; + v__h193329 = $stime; #0; end - v__h193313 = v__h193319 / 32'd10; + v__h193323 = v__h193329 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory", - v__h193313); + v__h193323); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) @@ -13395,103 +13450,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) - $write("'h%h", line_addr__h193455); + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) + $write("'h%h", line_addr__h193465); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) @@ -13506,15 +13561,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) begin - v__h222677 = $stime; + v__h224814 = $stime; #0; end - v__h222671 = v__h222677 / 32'd10; + v__h224808 = v__h224814 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h222671); + v__h224808); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) @@ -13572,62 +13627,62 @@ module mkProc(CLK, $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) begin - v__h193908 = $stime; + v__h193918 = $stime; #0; end - v__h193902 = v__h193908 / 32'd10; + v__h193912 = v__h193918 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h193902, + v__h193912, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13636,45 +13691,45 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) begin - v__h194094 = $stime; + v__h194104 = $stime; #0; end - v__h194088 = v__h194094 / 32'd10; + v__h194098 = v__h194104 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h194088); + v__h194098); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) @@ -13753,310 +13808,286 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v index f803dd8..acace0b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:04:33 BST 2020 +// On Mon Jul 6 19:18:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRas.v b/src_SSITH_P3/Verilog_RTL/mkRas.v index 5e97129..5e61bb2 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:38 BST 2020 +// On Mon Jul 6 19:19:31 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v index da783ff..e8da78b 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:02:06 BST 2020 +// On Mon Jul 6 19:15:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v index 328a358..ec81705 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:14 BST 2020 +// On Mon Jul 6 19:19:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v index 9cb0c11..0aff2af 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:54 BST 2020 +// On Mon Jul 6 19:23:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v index 8853cad..d6c2e48 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:28 BST 2020 +// On Mon Jul 6 19:19:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v index a30b4ef..58edb06 100644 --- a/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:23 BST 2020 +// On Mon Jul 6 19:19:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v index 2fb7dc7..b6ddf52 100644 --- a/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:04:43 BST 2020 +// On Mon Jul 6 19:18:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v index 0c61135..33b52d0 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:06:56 BST 2020 +// On Mon Jul 6 19:20:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v index fc94cdf..6d4f8f9 100644 --- a/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:06:49 BST 2020 +// On Mon Jul 6 19:20:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v index 8053261..4d7eb51 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:20 BST 2020 +// On Mon Jul 6 19:23:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v index 1017461..9a8bb14 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v +++ b/src_SSITH_P3/Verilog_RTL/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:39 BST 2020 +// On Mon Jul 6 19:14:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v index 21ba2ec..39c206d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:04:24 BST 2020 +// On Mon Jul 6 19:18:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v index 4c561b7..42dbc4d 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:06:21 BST 2020 +// On Mon Jul 6 19:20:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v index ec4d7e9..4c4704c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:12 BST 2020 +// On Mon Jul 6 19:15:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v index c0868c1..f59bf6e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:39 BST 2020 +// On Mon Jul 6 19:15:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v index a36266a..3d82e2c 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPred.v b/src_SSITH_P3/Verilog_RTL/mkTourPred.v index 47bb354..cdc0c9e 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v index 8d3e17b..8621a92 100644 --- a/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:27 BST 2020 +// On Mon Jul 6 19:23:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_alu.v b/src_SSITH_P3/Verilog_RTL/module_alu.v index 67ea0ed..9536d91 100644 --- a/src_SSITH_P3/Verilog_RTL/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:57 BST 2020 +// On Mon Jul 6 19:14:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_aluBr.v b/src_SSITH_P3/Verilog_RTL/module_aluBr.v index d525ba1..743e47b 100644 --- a/src_SSITH_P3/Verilog_RTL/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_amoExec.v b/src_SSITH_P3/Verilog_RTL/module_amoExec.v index 848b5ed..21a13cf 100644 --- a/src_SSITH_P3/Verilog_RTL/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:36 BST 2020 +// On Mon Jul 6 19:14:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_basicExec.v b/src_SSITH_P3/Verilog_RTL/module_basicExec.v index c13a99c..1afff3b 100644 --- a/src_SSITH_P3/Verilog_RTL/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:51 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v index 745a265..f1ccf07 100644 --- a/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capChecks.v b/src_SSITH_P3/Verilog_RTL/module_capChecks.v index 2cb88c4..53a9388 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capChecks.v +++ b/src_SSITH_P3/Verilog_RTL/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:57 BST 2020 +// On Mon Jul 6 19:14:47 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capInspect.v b/src_SSITH_P3/Verilog_RTL/module_capInspect.v index f990185..184990a 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capInspect.v +++ b/src_SSITH_P3/Verilog_RTL/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_capModify.v b/src_SSITH_P3/Verilog_RTL/module_capModify.v index 24ce649..c991fa2 100644 --- a/src_SSITH_P3/Verilog_RTL/module_capModify.v +++ b/src_SSITH_P3/Verilog_RTL/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:59 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_checkForException.v b/src_SSITH_P3/Verilog_RTL/module_checkForException.v index 4ea998e..5128c22 100644 --- a/src_SSITH_P3/Verilog_RTL/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:01 BST 2020 +// On Mon Jul 6 19:14:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_decode.v b/src_SSITH_P3/Verilog_RTL/module_decode.v index 6c790f8..b8dd08a 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:34 BST 2020 +// On Mon Jul 6 19:19:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v index 1cd22f1..439b8b1 100644 --- a/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:30 BST 2020 +// On Mon Jul 6 19:19:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v index 67ada5c..490ee7e 100644 --- a/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:26 BST 2020 +// On Mon Jul 6 19:23:20 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v b/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v index fb4e075..1c9e579 100644 --- a/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/Verilog_RTL/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:57 BST 2020 +// On Mon Jul 6 19:14:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v b/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v index 6a87c02..759e4d3 100644 --- a/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v +++ b/src_SSITH_P3/Verilog_RTL/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:58 BST 2020 +// On Mon Jul 6 19:14:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v b/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v index c9836ba..c234696 100644 --- a/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v +++ b/src_SSITH_P3/Verilog_RTL/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:59 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v index 3ac5465..c11530f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:44 BST 2020 +// On Mon Jul 6 19:11:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v index 4f229fa..f6ff710 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:45 BST 2020 +// On Mon Jul 6 19:12:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v index cb855f3..89355c5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:45 BST 2020 +// On Mon Jul 6 19:12:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkBht.v b/src_SSITH_P3/Verilog_RTL_sim/mkBht.v index d03c484..35d3ccb 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkBht.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:47 BST 2020 +// On Mon Jul 6 19:10:53 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index abf640d..1993f59 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:58:47 BST 2020 +// On Mon Jul 6 19:13:02 BST 2020 // // // Ports: @@ -3767,17 +3767,17 @@ module mkCore(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h215836; - reg [63 : 0] v__h218172; - reg [63 : 0] v__h275404; - reg [63 : 0] v__h351162; - reg [63 : 0] v__h427778; + reg [63 : 0] v__h215837; + reg [63 : 0] v__h218173; + reg [63 : 0] v__h275405; + reg [63 : 0] v__h351163; + reg [63 : 0] v__h427779; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5511; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4911; - reg [65 : 0] thin_address__h864886, thin_address__h906783; + reg [65 : 0] thin_address__h864884, thin_address__h906786; reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q369, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, @@ -3816,12 +3816,12 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2242, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2154, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_140_B_ETC___d2158, - addr__h509971, - addr__h850288, - addr__h895060, - data_out__h1031505, - trap_val__h1007654, - x__h267667; + addr__h509972, + addr__h850287, + addr__h895062, + data_out__h1031509, + trap_val__h1007658, + x__h267669; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q29, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q31, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q33, @@ -3856,7 +3856,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17440; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1876, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_31_TO_0_ETC___d2046, - x__h267822; + x__h267824; reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q351, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q345, @@ -3908,16 +3908,16 @@ module mkCore(CLK, _theResult___fst_sfd__h707480; reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, - thin_otype__h864891, - thin_otype__h906788; + thin_otype__h864889, + thin_otype__h906791; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_235_ETC___d1889, SEL_ARR_mmio_dataRespQ_data_0_393_BITS_15_TO_0_ETC___d2058; - reg [13 : 0] thin_addrBits__h864887, - thin_addrBits__h906784, - thin_bounds_baseBits__h866835, - thin_bounds_baseBits__h908190, - thin_bounds_topBits__h866834, - thin_bounds_topBits__h908189; + reg [13 : 0] thin_addrBits__h864885, + thin_addrBits__h906787, + thin_bounds_baseBits__h866833, + thin_bounds_baseBits__h908193, + thin_bounds_topBits__h866832, + thin_bounds_topBits__h908192; reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q342, CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q338, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q329; @@ -4036,10 +4036,10 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_95_TO_326_BITS_ETC__q333, IF_fetchStage_pipelines_0_first__0544_BITS_265_ETC___d22363, IF_fetchStage_pipelines_1_first__0553_BITS_265_ETC___d22544, - cause_code__h1006050, - i__h1006066, - t__h215264, - t__h217617; + cause_code__h1006054, + i__h1006070, + t__h215265, + t__h217618; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__861_ETC__q248, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9699_ETC__q250, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q246, @@ -4065,9 +4065,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0553_BITS_236_ETC___d21670, IF_fetchStage_pipelines_1_first__0553_BITS_265_ETC___d22545, IF_rob_deqPort_0_deq_data__2632_BIT_294_3837_T_ETC___d23859, - i__h1006266, - thin_perms_soft__h865126, - thin_perms_soft__h906963; + i__h1006270, + thin_perms_soft__h865124, + thin_perms_soft__h906966; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__861_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9699_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q245, @@ -4097,15 +4097,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__262_ETC___d14974, IF_fetchStage_pipelines_0_first__0544_BITS_232_ETC___d20730, IF_fetchStage_pipelines_1_first__0553_BITS_232_ETC___d21702, - x__h505453, - x__h513121; + x__h505454, + x__h513122; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q372, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q323, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, - thin_reserved__h864890, - thin_reserved__h906787; + thin_reserved__h864888, + thin_reserved__h906790; reg CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277, CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, @@ -4188,7 +4188,7 @@ module mkCore(CLK, CASE_guard98525_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q72, CASE_guard98857_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q145, CASE_guard98857_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q144, - CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, + CASE_k54122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19446, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19482, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19491, @@ -4321,20 +4321,20 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5583; wire [128 : 0] amoExec___d4942, amoExec___d775, - fallthrough_pc__h948605, - fallthrough_pc__h973092, - new_pc__h880397, - new_pc__h920770, - next_pc__h1023267, - pc__h973083, - v__h1023589, - v__h1024298, - x__h873778, - x__h887432, - x__h914818, - x__h923374, - y__h874032, - y__h915072; + fallthrough_pc__h948609, + fallthrough_pc__h973096, + new_pc__h880396, + new_pc__h920774, + next_pc__h1023271, + pc__h973087, + v__h1023593, + v__h1024302, + x__h873776, + x__h887431, + x__h914821, + x__h923378, + y__h874030, + y__h915075; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5188, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4901, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4909, @@ -4343,8 +4343,8 @@ module mkCore(CLK, b__h840999, b__h841011, coreFix_memExe_regToExeQ_first__664_BITS_140_T_ETC___d4089, - x__h185172, - x__h201336, + x__h185173, + x__h201337, x__h841823; wire [109 : 0] IF_fetchStage_pipelines_0_first__0544_BITS_238_ETC___d20910, IF_fetchStage_pipelines_1_first__0553_BITS_238_ETC___d21882; @@ -4371,91 +4371,91 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16614, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3075, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3437, - addTop__h242863, - addTop__h244020, - addTop__h257641, - address__h1010261, - address__h1010605, - address__h1010918, - address__h1011262, + addTop__h242865, + addTop__h244022, + addTop__h257643, + address__h1010265, + address__h1010609, + address__h1010922, + address__h1011266, coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426, coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723, - cr_address__h872615, - cr_address__h873163, - cr_address__h913655, - cr_address__h914203, - data_address__h1030232, - data_address__h1031086, - in__h1008423, - in__h242694, - in__h243851, - in__h257472, - in__h860567, - in__h860872, - in__h861560, - in__h861864, - in__h862390, - pc_address__h1005469, - pointer__h245525, + cr_address__h872613, + cr_address__h873161, + cr_address__h913658, + cr_address__h914206, + data_address__h1030236, + data_address__h1031090, + in__h1008427, + in__h242696, + in__h243853, + in__h257474, + in__h860565, + in__h860870, + in__h861558, + in__h861862, + in__h862388, + pc_address__h1005473, + pointer__h245527, res_address__h127848, res_address__h140988, - res_address__h180671, - res_address__h199748, - res_address__h218912, - res_address__h238211, - res_address__h571767, + res_address__h180672, + res_address__h199749, + res_address__h218913, + res_address__h238213, + res_address__h571768, res_address__h572620, res_address__h618377, res_address__h664124, res_address__h710010, res_address__h710956, - res_address__h855056, - res_address__h899820, - result__h243490, - result__h244647, - result__h258268, - result_d_address__h1019565, - result_d_address__h1019968, - result_d_address__h1020385, - result_d_address__h1020788, - result_d_address__h1021457, - result_d_address__h1043132, - result_d_address__h1043535, - result_d_address__h1043952, - result_d_address__h1044355, - result_d_address__h1045022, - result_d_address__h245736, - ret__h242867, - ret__h244024, - ret__h257645, - x__h1008441, - x__h1010455, - x__h1010759, - x__h1011112, - x__h1011416, - x__h238634, - x__h242712, - x__h242860, - x__h243869, - x__h244017, - x__h251007, - x__h257490, - x__h257638, - x__h860585, - x__h860890, - x__h861578, - x__h861882, - x__h862408, - y__h1008440, - y__h242711, - y__h243868, - y__h257489, - y__h860584, - y__h860889, - y__h861577, - y__h861881, - y__h862407; + res_address__h855055, + res_address__h899822, + result__h243492, + result__h244649, + result__h258270, + result_d_address__h1019569, + result_d_address__h1019972, + result_d_address__h1020389, + result_d_address__h1020792, + result_d_address__h1021461, + result_d_address__h1043136, + result_d_address__h1043539, + result_d_address__h1043956, + result_d_address__h1044359, + result_d_address__h1045026, + result_d_address__h245738, + ret__h242869, + ret__h244026, + ret__h257647, + x__h1008445, + x__h1010459, + x__h1010763, + x__h1011116, + x__h1011420, + x__h238636, + x__h242714, + x__h242862, + x__h243871, + x__h244019, + x__h251009, + x__h257492, + x__h257640, + x__h860583, + x__h860888, + x__h861576, + x__h861880, + x__h862406, + y__h1008444, + y__h242713, + y__h243870, + y__h257491, + y__h860582, + y__h860887, + y__h861575, + y__h861879, + y__h862405; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13430, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12597, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12598, @@ -4491,35 +4491,35 @@ module mkCore(CLK, a___1__h840836, a___1__h841227, a__h840674, - addBase__h1019584, - addBase__h1019987, - addBase__h1020404, - addBase__h1020807, - addBase__h1021477, - addBase__h242754, - addBase__h243911, - addBase__h257532, - addr__h1000330, + addBase__h1019588, + addBase__h1019991, + addBase__h1020408, + addBase__h1020811, + addBase__h1021481, + addBase__h242756, + addBase__h243913, + addBase__h257534, + addr__h1000334, addr__h149995, addr__h153571, - addr__h238205, - address__h1010195, - address__h1010245, - address__h1023320, - address__h874071, - address__h915075, - address__h965680, - address__h990656, + addr__h238207, + address__h1010199, + address__h1010249, + address__h1023324, + address__h874069, + address__h915078, + address__h965684, + address__h990660, b___1__h840837, b___1__h841288, b__h840675, - base__h1010156, - base__h1010210, - bot__h1019587, - bot__h1019990, - bot__h1020407, - bot__h1020810, - bot__h1021480, + base__h1010160, + base__h1010214, + bot__h1019591, + bot__h1019994, + bot__h1020411, + bot__h1020814, + bot__h1021484, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15402, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15403, csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192, @@ -4533,25 +4533,25 @@ module mkCore(CLK, data__h709525, data__h710440, data__h710471, - fcsr_csr__read__h855632, - fflags_csr__read__h855607, - frm_csr__read__h855618, - mask__h1010267, - mask__h1010924, - mcause_csr__read__h857299, - mcounteren_csr__read__h857033, - medeleg_csr__read__h856636, - mideleg_csr__read__h856734, - mie_csr__read__h856861, - mip_csr__read__h857538, - mstatus_csr__read__h856475, - n__read__h1025238, + fcsr_csr__read__h855630, + fflags_csr__read__h855605, + frm_csr__read__h855616, + mask__h1010271, + mask__h1010928, + mcause_csr__read__h857297, + mcounteren_csr__read__h857031, + medeleg_csr__read__h856634, + mideleg_csr__read__h856732, + mie_csr__read__h856859, + mip_csr__read__h857536, + mstatus_csr__read__h856473, + n__read__h1025242, n__read__h7908, - newAddrDiff__h1010268, - newAddrDiff__h1010612, - newAddrDiff__h1010925, - newAddrDiff__h1011269, - offset__h245515, + newAddrDiff__h1010272, + newAddrDiff__h1010616, + newAddrDiff__h1010929, + newAddrDiff__h1011273, + offset__h245517, q___1__h711053, rVal1__h719444, rVal2__h719445, @@ -4562,135 +4562,135 @@ module mkCore(CLK, res_data__h618419, res_data__h664161, res_data__h664166, - resp_addr__h513540, - rg_tdata1__read__h858639, + resp_addr__h513541, + rg_tdata1__read__h858637, robdeqPort_0_deq_data_BITS_95_TO_32__q16, - satp_csr__read__h856329, - scause_csr__read__h856126, - scounteren_csr__read__h855986, - sie_csr__read__h855898, - sip_csr__read__h856266, - sstatus_csr__read__h855828, - thin_address__h1010149, - tmpAddr__h245724, - trap_val__h1007807, - upd__h1025314, + satp_csr__read__h856327, + scause_csr__read__h856124, + scounteren_csr__read__h855984, + sie_csr__read__h855896, + sip_csr__read__h856264, + sstatus_csr__read__h855826, + thin_address__h1010153, + tmpAddr__h245726, + trap_val__h1007811, + upd__h1025318, upd__h3066, upd__h3676, upd__h7977, - value__h242584, - value__h242748, - value__h243741, - value__h243905, - value__h257362, - value__h257526, - x__h1005641, - x__h1008354, - x__h1008356, - x__h1019495, - x__h1019898, - x__h1020315, - x__h1020718, - x__h1021387, - x__h1043062, - x__h1043465, - x__h1043882, - x__h1044285, - x__h1044952, + value__h242586, + value__h242750, + value__h243743, + value__h243907, + value__h257364, + value__h257528, + x__h1005645, + x__h1008358, + x__h1008360, + x__h1019499, + x__h1019902, + x__h1020319, + x__h1020722, + x__h1021391, + x__h1043066, + x__h1043469, + x__h1043886, + x__h1044289, + x__h1044956, x__h128329, x__h141473, - x__h185254, - x__h204317, - x__h219288, - x__h242602, + x__h185255, + x__h204318, + x__h219289, x__h242604, - x__h243759, + x__h242606, x__h243761, - x__h245664, - x__h257380, + x__h243763, + x__h245666, x__h257382, + x__h257384, x__h719350, x__h719351, x__h719352, x__h841211, + x__h860644, x__h860646, - x__h860648, + x__h861637, x__h861639, - x__h861641, - x__h872792, - x__h873340, - x__h903662, - x__h903664, - x__h903946, - x__h903948, - x__h904291, - x__h904293, - x__h913832, - x__h914380, + x__h872790, + x__h873338, + x__h903665, + x__h903667, + x__h903949, + x__h903951, + x__h904294, + x__h904296, + x__h913835, + x__h914383, x_addr__h19883, x_addr__h44252, - x_addr__h539796, + x_addr__h539797, x_quotient__h710242, - x_reg_ifc__read__h855737, + x_reg_ifc__read__h855735, x_remainder__h710243, - y__h1010384, - y__h1011041, - y__h1027855, + y__h1010388, + y__h1011045, + y__h1027859, y_avValue__h715399, y_avValue__h716107, y_avValue__h716809, - y_avValue_snd_snd_snd_snd_snd__h1027265, - y_avValue_snd_snd_snd_snd_snd__h1027908, - y_avValue_snd_snd_snd_snd_snd__h1027937; + y_avValue_snd_snd_snd_snd_snd__h1027269, + y_avValue_snd_snd_snd_snd_snd__h1027912, + y_avValue_snd_snd_snd_snd_snd__h1027941; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14139, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14909, - r1__read__h859520, + r1__read__h859518, + r1__read__h859922, + r1__read__h860615, + r1__read__h860927, + r1__read__h861160, + r1__read__h861332, + r1__read__h861608, + r1__read__h861919; + wire [61 : 0] r1__read__h859520, r1__read__h859924, r1__read__h860617, r1__read__h860929, r1__read__h861162, + r1__read__h861308, r1__read__h861334, r1__read__h861610, r1__read__h861921; - wire [61 : 0] r1__read__h859522, - r1__read__h859926, - r1__read__h860619, - r1__read__h860931, - r1__read__h861164, + wire [60 : 0] r1__read__h861164, r1__read__h861310, r1__read__h861336, - r1__read__h861612, r1__read__h861923; - wire [60 : 0] r1__read__h861166, - r1__read__h861312, + wire [59 : 0] r1__read__h859522, + r1__read__h859926, + r1__read__h860931, + r1__read__h861166, r1__read__h861338, r1__read__h861925; - wire [59 : 0] r1__read__h859524, + wire [58 : 0] r1__read__h859524, r1__read__h859928, + r1__read__h860920, r1__read__h860933, r1__read__h861168, r1__read__h861340, + r1__read__h861912, r1__read__h861927; - wire [58 : 0] r1__read__h859526, - r1__read__h859930, - r1__read__h860922, - r1__read__h860935, - r1__read__h861170, - r1__read__h861342, - r1__read__h861914, - r1__read__h861929; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5519, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5561, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7302, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d7043, - r1__read__h859528, - r1__read__h859932, - r1__read__h860937, - r1__read__h861172, - r1__read__h861314, - r1__read__h861344, - r1__read__h861931, - y__h426314; + r1__read__h859526, + r1__read__h859930, + r1__read__h860935, + r1__read__h861170, + r1__read__h861312, + r1__read__h861342, + r1__read__h861929, + y__h426315; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q111, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q41, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q76, @@ -4835,10 +4835,10 @@ module mkCore(CLK, _theResult___snd__h835743, _theResult___snd__h835749, _theResult___snd__h835767, - r1__read__h861174, - r1__read__h861316, - r1__read__h861346, - r1__read__h861933, + r1__read__h861172, + r1__read__h861314, + r1__read__h861344, + r1__read__h861931, result__h599128, result__h644877, result__h690624, @@ -4867,24 +4867,24 @@ module mkCore(CLK, x__h780118, x__h819422; wire [55 : 0] coreFix_memExe_dispToRegQ_first__695_BIT_102_7_ETC___d3598, + r1__read__h859528, + r1__read__h859932, + r1__read__h860937, + r1__read__h861174, + r1__read__h861346, + r1__read__h861933; + wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636, + IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443, r1__read__h859530, r1__read__h859934, r1__read__h860939, r1__read__h861176, r1__read__h861348, r1__read__h861935; - wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636, - IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443, - r1__read__h859532, - r1__read__h859936, - r1__read__h860941, - r1__read__h861178, + wire [53 : 0] r1__read__h861285, + r1__read__h861316, r1__read__h861350, - r1__read__h861937; - wire [53 : 0] r1__read__h861287, - r1__read__h861318, - r1__read__h861352, - r1__read__h861939, + r1__read__h861937, sfd__h739234, sfd__h748885, sfd__h757645, @@ -4902,11 +4902,11 @@ module mkCore(CLK, INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20078, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17839, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17903, - r1__read__h861180, - r1__read__h861289, - r1__read__h861320, - r1__read__h861354, - r1__read__h861941; + r1__read__h861178, + r1__read__h861287, + r1__read__h861318, + r1__read__h861352, + r1__read__h861939; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13397, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13399, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14106, @@ -4973,9 +4973,9 @@ module mkCore(CLK, _theResult___snd_fst_sfd__h798442, _theResult___snd_fst_sfd__h818135, _theResult___snd_fst_sfd__h836570, - mask__h242864, - mask__h244021, - mask__h257642, + mask__h242866, + mask__h244023, + mask__h257644, out___1_sfd__h719892, out___1_sfd__h758886, out___1_sfd__h798190, @@ -4988,47 +4988,47 @@ module mkCore(CLK, out_sfd__h818032, out_sfd__h827683, out_sfd__h836467; - wire [50 : 0] r1__read__h859534, r1__read__h861182; + wire [50 : 0] r1__read__h859532, r1__read__h861180; wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5, coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3, - highBitsfilter__h1019371, - highBitsfilter__h1019774, - highBitsfilter__h1020191, - highBitsfilter__h1020594, - highBitsfilter__h1021263, - highOffsetBits__h1019372, - highOffsetBits__h1019775, - highOffsetBits__h1020192, - highOffsetBits__h1020595, - highOffsetBits__h1021264, - highOffsetBits__h1042939, - highOffsetBits__h1043342, - highOffsetBits__h1043759, - highOffsetBits__h1044162, - highOffsetBits__h1044829, - highOffsetBits__h245534, - mask__h242755, - mask__h243912, - mask__h257533, - r1__read__h861291, - signBits__h1019369, - signBits__h1042936, - signBits__h245531, - x__h1019399, - x__h1042966, - x__h245561; - wire [48 : 0] r1__read__h859536, r1__read__h861184, r1__read__h861293; - wire [47 : 0] r1__read__h861295; - wire [46 : 0] r1__read__h859538, r1__read__h861186; - wire [45 : 0] r1__read__h859540, r1__read__h861188; - wire [44 : 0] r1__read__h859542, r1__read__h861190; - wire [43 : 0] r1__read__h859544, r1__read__h861192; - wire [42 : 0] r1__read__h861194; - wire [41 : 0] r1__read__h861196; - wire [40 : 0] r1__read__h861198; + highBitsfilter__h1019375, + highBitsfilter__h1019778, + highBitsfilter__h1020195, + highBitsfilter__h1020598, + highBitsfilter__h1021267, + highOffsetBits__h1019376, + highOffsetBits__h1019779, + highOffsetBits__h1020196, + highOffsetBits__h1020599, + highOffsetBits__h1021268, + highOffsetBits__h1042943, + highOffsetBits__h1043346, + highOffsetBits__h1043763, + highOffsetBits__h1044166, + highOffsetBits__h1044833, + highOffsetBits__h245536, + mask__h242757, + mask__h243914, + mask__h257535, + r1__read__h861289, + signBits__h1019373, + signBits__h1042940, + signBits__h245533, + x__h1019403, + x__h1042970, + x__h245563; + wire [48 : 0] r1__read__h859534, r1__read__h861182, r1__read__h861291; + wire [47 : 0] r1__read__h861293; + wire [46 : 0] r1__read__h859536, r1__read__h861184; + wire [45 : 0] r1__read__h859538, r1__read__h861186; + wire [44 : 0] r1__read__h859540, r1__read__h861188; + wire [43 : 0] r1__read__h859542, r1__read__h861190; + wire [42 : 0] r1__read__h861192; + wire [41 : 0] r1__read__h861194; + wire [40 : 0] r1__read__h861196; wire [38 : 0] IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23254; - wire [37 : 0] r1__read__h861297; + wire [37 : 0] r1__read__h861295; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958, IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126, IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217, @@ -5053,15 +5053,15 @@ module mkCore(CLK, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17, data09494_BITS_31_TO_0__q22, data10440_BITS_31_TO_0__q27, - r1__read__h859546, - r1__read__h861200, + r1__read__h859544, + r1__read__h861198, x__h572675, x__h618429, x__h65639, x__h664176, x_data__h60140; - wire [29 : 0] r1__read__h859548, r1__read__h861202; - wire [27 : 0] r1__read__h861204; + wire [29 : 0] r1__read__h859546, r1__read__h861200; + wire [27 : 0] r1__read__h861202; wire [25 : 0] IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272, IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121, IF_basicExec_7927_BIT_325_7938_THEN_basicExec__ETC___d17946, @@ -5172,7 +5172,7 @@ module mkCore(CLK, out_sfd__h689585, out_sfd__h698769, out_sfd__h707405; - wire [19 : 0] r1__read__h861139; + wire [19 : 0] r1__read__h861137; wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q15, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, @@ -5181,8 +5181,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, - INV_x01336_BITS_108_TO_90__q37, - INV_x85172_BITS_108_TO_90__q35; + INV_x01337_BITS_108_TO_90__q37, + INV_x85173_BITS_108_TO_90__q35; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19292, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19293, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16838, @@ -5199,43 +5199,43 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3579; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611, IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3556, - _theResult____h928983, - base__h1008341, - base__h242589, - base__h243746, - base__h257367, - base__h860633, - base__h861626, - base__h903649, - base__h903933, - base__h904278, - enabled_ints___1__h929508, - enabled_ints__h929554, - newAddrBits__h1019554, - newAddrBits__h1019957, - newAddrBits__h1020374, - newAddrBits__h1020777, - newAddrBits__h1021446, - newAddrBits__h1043121, - newAddrBits__h1043524, - newAddrBits__h1043941, - newAddrBits__h1044344, - newAddrBits__h1045011, - offset__h1008342, - offset__h242590, - offset__h243747, - offset__h257368, - offset__h860634, - offset__h861627, - offset__h903650, - offset__h903934, - offset__h904279, - pend_ints__h928981, - x__h242962, - x__h244119, - x__h257740, - x__h904216, - y__h929520; + _theResult____h928987, + base__h1008345, + base__h242591, + base__h243748, + base__h257369, + base__h860631, + base__h861624, + base__h903652, + base__h903936, + base__h904281, + enabled_ints___1__h929512, + enabled_ints__h929558, + newAddrBits__h1019558, + newAddrBits__h1019961, + newAddrBits__h1020378, + newAddrBits__h1020781, + newAddrBits__h1021450, + newAddrBits__h1043125, + newAddrBits__h1043528, + newAddrBits__h1043945, + newAddrBits__h1044348, + newAddrBits__h1045015, + offset__h1008346, + offset__h242592, + offset__h243749, + offset__h257370, + offset__h860632, + offset__h861625, + offset__h903653, + offset__h903937, + offset__h904282, + pend_ints__h928985, + x__h242964, + x__h244121, + x__h257742, + x__h904219, + y__h929524; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19078, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19079, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16624, @@ -5257,85 +5257,85 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16629, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3095, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3445, - b_base__h1005866, + b_base__h1005870, b_base__h128554, b_base__h141698, - b_base__h185479, - b_base__h204542, - b_base__h219513, - b_base__h873030, - b_base__h873578, - b_base__h914070, - b_base__h914618, + b_base__h185480, + b_base__h204543, + b_base__h219514, + b_base__h873028, + b_base__h873576, + b_base__h914073, + b_base__h914621, checkForException___d20942, checkForException___d21903, - cr_addrBits__h872616, - cr_addrBits__h873164, - cr_addrBits__h913656, - cr_addrBits__h914204, - data_addrBits__h1030233, - data_addrBits__h1031087, - pc_addrBits__h1005470, - r1__read_BITS_13_TO_0___h929530, - repBoundBits__h245540, + cr_addrBits__h872614, + cr_addrBits__h873162, + cr_addrBits__h913659, + cr_addrBits__h914207, + data_addrBits__h1030237, + data_addrBits__h1031091, + pc_addrBits__h1005474, + r1__read_BITS_13_TO_0___h929534, + repBoundBits__h245542, res_addrBits__h127849, res_addrBits__h140989, - res_addrBits__h180672, - res_addrBits__h199749, - res_addrBits__h218913, - res_addrBits__h238212, - res_addrBits__h571768, + res_addrBits__h180673, + res_addrBits__h199750, + res_addrBits__h218914, + res_addrBits__h238214, + res_addrBits__h571769, res_addrBits__h572621, res_addrBits__h618378, res_addrBits__h664125, res_addrBits__h710011, res_addrBits__h710957, - res_addrBits__h855057, - res_addrBits__h899821, - result_d_addrBits__h1019566, - result_d_addrBits__h1019969, - result_d_addrBits__h1020386, - result_d_addrBits__h1020789, - result_d_addrBits__h1021458, - result_d_addrBits__h1043133, - result_d_addrBits__h1043536, - result_d_addrBits__h1043953, - result_d_addrBits__h1044356, - result_d_addrBits__h1045023, - toBoundsM1__h1019382, - toBoundsM1__h1019785, - toBoundsM1__h1020202, - toBoundsM1__h1020605, - toBoundsM1__h1021274, - toBoundsM1__h245544, - toBounds__h1019381, - toBounds__h1019784, - toBounds__h1020201, - toBounds__h1020604, - toBounds__h1021273, - toBounds__h245543, - x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654, - x__h1005839, - x__h1005859, - x__h1011651, + res_addrBits__h855056, + res_addrBits__h899823, + result_d_addrBits__h1019570, + result_d_addrBits__h1019973, + result_d_addrBits__h1020390, + result_d_addrBits__h1020793, + result_d_addrBits__h1021462, + result_d_addrBits__h1043137, + result_d_addrBits__h1043540, + result_d_addrBits__h1043957, + result_d_addrBits__h1044360, + result_d_addrBits__h1045027, + toBoundsM1__h1019386, + toBoundsM1__h1019789, + toBoundsM1__h1020206, + toBoundsM1__h1020609, + toBoundsM1__h1021278, + toBoundsM1__h245546, + toBounds__h1019385, + toBounds__h1019788, + toBounds__h1020205, + toBounds__h1020608, + toBounds__h1021277, + toBounds__h245545, + x1_avValue_new_pcc_capFat_bounds_baseBits__h1011658, + x__h1005843, + x__h1005863, + x__h1011655, x__h128527, x__h128547, x__h141671, x__h141691, - x__h185452, - x__h185472, - x__h204515, - x__h204535, - x__h219486, - x__h219506, - x__h873003, - x__h873023, - x__h873551, - x__h873571, - x__h914043, - x__h914063, - x__h914591, - x__h914611; + x__h185453, + x__h185473, + x__h204516, + x__h204536, + x__h219487, + x__h219507, + x__h873001, + x__h873021, + x__h873549, + x__h873569, + x__h914046, + x__h914066, + x__h914594, + x__h914614; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__276_BIT_27_ETC___d4776, IF_NOT_renameStage_rg_m_halt_req_0571_BIT_4_05_ETC___d21275, IF_NOT_renameStage_rg_m_halt_req_0571_BIT_4_05_ETC___d21276, @@ -5371,47 +5371,47 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d10165, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d11562, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8768, - b_top__h1005865, + b_top__h1005869, b_top__h128553, b_top__h141697, - b_top__h185478, - b_top__h204541, - b_top__h219512, - b_top__h873029, - b_top__h873577, - b_top__h914069, - b_top__h914617, + b_top__h185479, + b_top__h204542, + b_top__h219513, + b_top__h873027, + b_top__h873575, + b_top__h914072, + b_top__h914620, capChecks___d4179, - inc__h965679, - inc__h990655, - renaming_spec_bits__h978582, - result__h924561, - result__h924612, - spec_bits__h983633, - topBits__h1005768, + inc__h965683, + inc__h990659, + renaming_spec_bits__h978586, + result__h924565, + result__h924616, + spec_bits__h983637, + topBits__h1005772, topBits__h128456, topBits__h141600, - topBits__h185381, - topBits__h204444, - topBits__h219415, - topBits__h872931, - topBits__h873479, - topBits__h913971, - topBits__h914519, - w__h924556, + topBits__h185382, + topBits__h204445, + topBits__h219416, + topBits__h872929, + topBits__h873477, + topBits__h913974, + topBits__h914522, + w__h924560, x__h599258, x__h645007, x__h690754, x__h741298, x__h780151, x__h819455, - x__h924560, - x__h924611, - y__h924590, - y__h983646, - y_avValue_snd_fst__h973226, - y_avValue_snd_fst__h973268, - y_avValue_snd_fst__h973310; + x__h924564, + x__h924615, + y__h924594, + y__h983650, + y_avValue_snd_fst__h973230, + y_avValue_snd_fst__h973272, + y_avValue_snd_fst__h973314; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13313, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13315, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14023, @@ -5531,7 +5531,7 @@ module mkCore(CLK, out_exp__h818031, out_exp__h827682, out_exp__h836466, - x__h1009628; + x__h1009632; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3654; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10483, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11880, @@ -5704,11 +5704,11 @@ module mkCore(CLK, out_f_exp__h616284, out_f_exp__h662033, out_f_exp__h707780, - x__h859505; + x__h859503; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8612_BI_ETC___d19678, NOT_coreFix_aluExe_1_dispToRegQ_first__5790_BI_ETC___d17503, - x__h1010354, - x__h247565; + x__h1010358, + x__h247567; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11255, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8461, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9858, @@ -5737,19 +5737,19 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24866, fetchStage_pipelines_0_first__0544_BIT_167_088_ETC___d20904, fetchStage_pipelines_1_first__0553_BIT_167_185_ETC___d21876, - x__h1005679, - x__h1010328, - x__h1010985, - x__h1011672, + x__h1005683, + x__h1010332, + x__h1010989, + x__h1011676, x__h128367, x__h141511, - x__h185292, - x__h204355, - x__h219326, - x__h872830, - x__h873378, - x__h913870, - x__h914418; + x__h185293, + x__h204356, + x__h219327, + x__h872828, + x__h873376, + x__h913873, + x__h914421; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__0233_B_ETC___d20377, IF_IF_coreFix_aluExe_0_exeToFinQ_first__0233_B_ETC___d20378, IF_IF_coreFix_aluExe_1_exeToFinQ_first__8058_B_ETC___d18203, @@ -5792,11 +5792,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10797, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12194, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9400, - cause_code__h1007625, + cause_code__h1007629, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4142, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175, - fflags__h1027832, - r1__read__h862250, + fflags__h1027836, + r1__read__h862248, res_fflags__h572661, res_fflags__h618415, res_fflags__h664162, @@ -5804,39 +5804,39 @@ module mkCore(CLK, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16972, x__h150547, x__h153681, - x__h252365, - x__h252377, - x__h252389, - x__h252401, - x__h252413, - x__h252425, - x__h252437, - x__h252449, - x__h252461, - x__h252473, - x__h252485, - x__h252497, - x__h252509, - x__h252521, - x__h252533, - y__h252366, - y__h252378, - y__h252390, - y__h252402, - y__h252414, - y__h252426, - y__h252438, - y__h252450, - y__h252462, - y__h252474, - y__h252486, - y__h252498, - y__h252510, - y__h252522, - y__h252534, - y_avValue_snd_fst__h1027249, - y_avValue_snd_fst__h1027892, - y_avValue_snd_fst__h1027921; + x__h252367, + x__h252379, + x__h252391, + x__h252403, + x__h252415, + x__h252427, + x__h252439, + x__h252451, + x__h252463, + x__h252475, + x__h252487, + x__h252499, + x__h252511, + x__h252523, + x__h252535, + y__h252368, + y__h252380, + y__h252392, + y__h252404, + y__h252416, + y__h252428, + y__h252440, + y__h252452, + y__h252464, + y__h252476, + y__h252488, + y__h252500, + y__h252512, + y__h252524, + y__h252536, + y_avValue_snd_fst__h1027253, + y_avValue_snd_fst__h1027896, + y_avValue_snd_fst__h1027925; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8612__ETC___d19675, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5790__ETC___d17500, IF_IF_renameStage_rg_m_halt_req_0571_BIT_4_057_ETC___d21265, @@ -5881,7 +5881,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3416, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3453, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3651, - vm_mode_reg__read__h861145; + vm_mode_reg__read__h861143; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19336, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19337, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16882, @@ -5898,57 +5898,57 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3608, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7184, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24799, - _theResult_____2__h519790, - dcsr_cause__h1005094, - next_deqP___1__h520035, - repBound__h1008366, - repBound__h240206, - repBound__h241891, - repBound__h251105, - repBound__h251630, - repBound__h860489, - repBound__h860811, - repBound__h861482, - repBound__h861803, - repBound__h862312, - repBound__h863990, - repBound__h866952, - repBound__h866970, - repBound__h873084, - repBound__h873632, - repBound__h905960, - repBound__h908287, - repBound__h908305, - repBound__h914124, - repBound__h914672, - tb__h873081, - tb__h873629, - tb__h914121, - tb__h914669, - tmp_expBotHalf__h1005634, + _theResult_____2__h519791, + dcsr_cause__h1005098, + next_deqP___1__h520036, + repBound__h1008370, + repBound__h240208, + repBound__h241893, + repBound__h251107, + repBound__h251632, + repBound__h860487, + repBound__h860809, + repBound__h861480, + repBound__h861801, + repBound__h862310, + repBound__h863988, + repBound__h866950, + repBound__h866968, + repBound__h873082, + repBound__h873630, + repBound__h905963, + repBound__h908290, + repBound__h908308, + repBound__h914127, + repBound__h914675, + tb__h873079, + tb__h873627, + tb__h914124, + tb__h914672, + tmp_expBotHalf__h1005638, tmp_expBotHalf__h128322, tmp_expBotHalf__h141466, - tmp_expBotHalf__h185247, - tmp_expBotHalf__h204310, - tmp_expBotHalf__h219281, - tmp_expBotHalf__h872784, - tmp_expBotHalf__h873332, - tmp_expBotHalf__h913824, - tmp_expBotHalf__h914372, - tmp_expTopHalf__h1005632, + tmp_expBotHalf__h185248, + tmp_expBotHalf__h204311, + tmp_expBotHalf__h219282, + tmp_expBotHalf__h872782, + tmp_expBotHalf__h873330, + tmp_expBotHalf__h913827, + tmp_expBotHalf__h914375, + tmp_expTopHalf__h1005636, tmp_expTopHalf__h128320, tmp_expTopHalf__h141464, - tmp_expTopHalf__h185245, - tmp_expTopHalf__h204308, - tmp_expTopHalf__h219279, - tmp_expTopHalf__h872782, - tmp_expTopHalf__h873330, - tmp_expTopHalf__h913822, - tmp_expTopHalf__h914370, - v__h519246, - v__h519441, - x__h526097, - x_decodeInfo_frm__h934999; + tmp_expTopHalf__h185246, + tmp_expTopHalf__h204309, + tmp_expTopHalf__h219280, + tmp_expTopHalf__h872780, + tmp_expTopHalf__h873328, + tmp_expTopHalf__h913825, + tmp_expTopHalf__h914373, + v__h519247, + v__h519442, + x__h526098, + x_decodeInfo_frm__h935003; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19279, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19280, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16825, @@ -5985,21 +5985,21 @@ module mkCore(CLK, IF_theResult___snd89090_BIT_33_THEN_2_ELSE_0__q114, IF_theResult___snd96425_BIT_4_THEN_2_ELSE_0__q194, IF_theResult___snd97594_BIT_33_THEN_2_ELSE_0__q44, - carry_out__h1005770, + carry_out__h1005774, carry_out__h128458, carry_out__h141602, - carry_out__h185383, - carry_out__h204446, - carry_out__h219417, - carry_out__h872933, - carry_out__h873481, - carry_out__h913973, - carry_out__h914521, + carry_out__h185384, + carry_out__h204447, + carry_out__h219418, + carry_out__h872931, + carry_out__h873479, + carry_out__h913976, + carry_out__h914524, coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2, coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4, - cr_reserved__h873167, - cr_reserved__h914207, + cr_reserved__h873165, + cr_reserved__h914210, guard__h580886, guard__h589595, guard__h598525, @@ -6021,49 +6021,49 @@ module mkCore(CLK, guard__h809412, guard__h818724, guard__h827793, - impliedTopBits__h1005772, + impliedTopBits__h1005776, impliedTopBits__h128460, impliedTopBits__h141604, - impliedTopBits__h185385, - impliedTopBits__h204448, - impliedTopBits__h219419, - impliedTopBits__h872935, - impliedTopBits__h873483, - impliedTopBits__h913975, - impliedTopBits__h914523, - len_correction__h1005771, + impliedTopBits__h185386, + impliedTopBits__h204449, + impliedTopBits__h219420, + impliedTopBits__h872933, + impliedTopBits__h873481, + impliedTopBits__h913978, + impliedTopBits__h914526, + len_correction__h1005775, len_correction__h128459, len_correction__h141603, - len_correction__h185384, - len_correction__h204447, - len_correction__h219418, - len_correction__h872934, - len_correction__h873482, - len_correction__h913974, - len_correction__h914522, - prv__h1028925, - prv__h1028969, - r1__read_BITS_13_TO_12___h935205, + len_correction__h185385, + len_correction__h204448, + len_correction__h219419, + len_correction__h872932, + len_correction__h873480, + len_correction__h913977, + len_correction__h914525, + prv__h1028929, + prv__h1028973, + r1__read_BITS_13_TO_12___h935209, sbIdx__h153572, v__h841893, v__h841903, v__h842934, - wordIdx__h266168, - x__h1005856, - x__h1023610, - x__h1028080, + wordIdx__h266170, + x__h1005860, + x__h1023614, + x__h1028084, x__h128544, x__h141688, - x__h185469, - x__h204532, - x__h219503, - x__h873020, - x__h873568, - x__h914060, - x__h914608, - y_avValue_snd_snd_snd_fst__h1027259, - y_avValue_snd_snd_snd_fst__h1027902, - y_avValue_snd_snd_snd_fst__h1027931; + x__h185470, + x__h204533, + x__h219504, + x__h873018, + x__h873566, + x__h914063, + x__h914611, + y_avValue_snd_snd_snd_fst__h1027263, + y_avValue_snd_snd_snd_fst__h1027906, + y_avValue_snd_snd_snd_fst__h1027935; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10680, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10730, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d12077, @@ -6821,12 +6821,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h530567, - _theResult_____2__h537660, - _theResult_____2__h548295, - _theResult_____2__h562128, - _theResult_____2__h565907, - cause_interrupt__h1006048, + _theResult_____2__h530568, + _theResult_____2__h537661, + _theResult_____2__h548296, + _theResult_____2__h562129, + _theResult_____2__h565908, + cause_interrupt__h1006052, commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22877, commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22884, commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22989, @@ -7220,8 +7220,8 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__664_BITS_265_T_ETC___d3736, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4132, coreFix_memExe_stb_isEmpty__188_AND_coreFix_me_ETC___d23405, - cr_flags__h873166, - cr_flags__h914206, + cr_flags__h873164, + cr_flags__h914209, csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163, csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4165, @@ -7278,21 +7278,21 @@ module mkCore(CLK, guard__h741165, guard__h780018, guard__h819322, - idx__h978721, - k__h954118, + idx__h978725, + k__h954122, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20967, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21359, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21379, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22307, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22309, - next_deqP___1__h530812, - next_deqP___1__h538090, - next_deqP___1__h548725, - next_deqP___1__h562373, - next_deqP___1__h566152, - r1__read_BIT_20___h935711, - r__h859552, - r__h861996, + next_deqP___1__h530813, + next_deqP___1__h538091, + next_deqP___1__h548726, + next_deqP___1__h562374, + next_deqP___1__h566153, + r1__read_BIT_20___h935715, + r__h859550, + r__h861994, regRenamingTable_RDY_rename_0_getRename__1316__ETC___d21327, regRenamingTable_RDY_rename_0_getRename__1316__ETC___d22153, regRenamingTable_rename_0_canRename__1456_AND__ETC___d21480, @@ -7341,20 +7341,20 @@ module mkCore(CLK, rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3628, rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24285, rob_enqPort_1_canEnq__1933_AND_epochManager_ch_ETC___d21938, - v__h521266, - v__h521646, - v__h536985, - v__h537180, - v__h539434, - v__h539629, - v__h560454, - v__h560649, - v__h564233, - v__h564428, + v__h521267, + v__h521647, + v__h536986, + v__h537181, + v__h539435, + v__h539630, + v__h560455, + v__h560650, + v__h564234, + v__h564429, value_BIT_23___h810070, - x__h243031, - x__h244188, - x__h257809, + x__h243033, + x__h244190, + x__h257811, x__h841237; // action method coreReq_start @@ -11455,15 +11455,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h1000330, + addr__h1000334, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q329, rob$deqPort_0_deq_data[501:470] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1027855 ; + commitStage_rg_serial_num + y__h1027859 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h954118 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h954122 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d20670, @@ -11481,7 +11481,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978582, + renaming_spec_bits__h978586, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11589,7 +11589,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h505453 } ; + x__h505454 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7124 } ; @@ -11599,7 +11599,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h509971, + addr__h509972, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7232 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11631,7 +11631,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:578] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h513540, + resp_addr__h513541, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11639,8 +11639,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1028969, - prv__h1028969 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1028973, + prv__h1028973 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11709,39 +11709,39 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4874, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4911 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h923374, - new_pc__h920770, + { x__h923378, + new_pc__h920774, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h923374, - new_pc__h920770, + { x__h923378, + new_pc__h920774, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h887432, - new_pc__h880397, + { x__h887431, + new_pc__h880396, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h887432, - new_pc__h880397, + { x__h887431, + new_pc__h880396, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1027832 ; + csrf_fflags_reg | fflags__h1027836 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd1) ? @@ -11792,21 +11792,21 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd27) ? { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23695, - result_d_address__h1020788, - result_d_addrBits__h1020789, + result_d_address__h1020792, + result_d_addrBits__h1020793, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23714 } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24628, - result_d_address__h1044355, - result_d_addrBits__h1044356, + result_d_address__h1044359, + result_d_addrBits__h1044360, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23714 } ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1025238 + 64'd1 ; + n__read__h1025242 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1025238 + { 62'd0, x__h1028080 } ; + n__read__h1025242 + { 62'd0, x__h1028084 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == @@ -11818,21 +11818,21 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd24) ? { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23651, - result_d_address__h1020385, - result_d_addrBits__h1020386, + result_d_address__h1020389, + result_d_addrBits__h1020390, csrf_mtcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_mtcc_reg$write_1__VAL_2 = { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24608, - result_d_address__h1043952, - result_d_addrBits__h1043953, + result_d_address__h1043956, + result_d_addrBits__h1043957, csrf_mtcc_reg[71:0] } ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h1007807 or trap_val__h1007654) + always@(commitStage_commitTrap or trap_val__h1007811 or trap_val__h1007658) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007807; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007654; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007811; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h1007658; default: MUX_csrf_mtval_csr$write_1__VAL_3 = 64'd0; endcase end @@ -11854,7 +11854,7 @@ module mkCore(CLK, 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1023610 : + x__h1023614 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_3 = csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? @@ -11864,44 +11864,44 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__VAL_3 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h1005094, + dcsr_cause__h1005098, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23809, - result_d_address__h1021457, - result_d_addrBits__h1021458, + result_d_address__h1021461, + result_d_addrBits__h1021462, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24699, - result_d_address__h1045022, - result_d_addrBits__h1045023, + result_d_address__h1045026, + result_d_addrBits__h1045027, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { commitStage_commitTrap[237], - pc_address__h1005469, - pc_addrBits__h1005470, + pc_address__h1005473, + pc_addrBits__h1005474, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956, - x__h1005839, - x__h1005859 } ; + x__h1005843, + x__h1005863 } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd13) ? { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23558, - result_d_address__h1019968, - result_d_addrBits__h1019969, + result_d_address__h1019972, + result_d_addrBits__h1019973, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23577 } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24550, - result_d_address__h1043535, - result_d_addrBits__h1043536, + result_d_address__h1043539, + result_d_addrBits__h1043540, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23577 } ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] == 5'd17 && @@ -11915,17 +11915,17 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2632_BIT_288_3296_T_ETC___d23390 == 6'd10) ? { IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23512, - result_d_address__h1019565, - result_d_addrBits__h1019566, + result_d_address__h1019569, + result_d_addrBits__h1019570, csrf_stcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_stcc_reg$write_1__VAL_2 = { f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24528, - result_d_address__h1043132, - result_d_addrBits__h1043133, + result_d_address__h1043136, + result_d_addrBits__h1043137, csrf_stcc_reg[71:0] } ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1031505 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1031509 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11941,14 +11941,14 @@ module mkCore(CLK, IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[14:3], ~IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[2], IF_IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_I_ETC___d23272[1:0], - thin_address__h1010149 } ; + thin_address__h1010153 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1023267 or v__h1023589 or v__h1024298) + next_pc__h1023271 or v__h1023593 or v__h1024302) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1023589; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1024298; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1023267; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1023593; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1024302; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1023271; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11995,8 +11995,8 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h571767, - res_addrBits__h571768, + res_address__h571768, + res_addrBits__h571769, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, @@ -12044,27 +12044,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h180671, - res_addrBits__h180672, - x__h185172[127:112], - x__h185172[109], - x__h185172[111:110], - ~x__h185172[108:90], + res_address__h180672, + res_addrBits__h180673, + x__h185173[127:112], + x__h185173[109], + x__h185173[111:110], + ~x__h185173[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h199748, - res_addrBits__h199749, - x__h201336[127:112], - x__h201336[109], - x__h201336[111:110], - ~x__h201336[108:90], + res_address__h199749, + res_addrBits__h199750, + x__h201337[127:112], + x__h201337[109], + x__h201337[111:110], + ~x__h201337[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h218912, - res_addrBits__h218913, + res_address__h218913, + res_addrBits__h218914, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -12072,13 +12072,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1030232, - data_addrBits__h1030233, + data_address__h1030236, + data_addrBits__h1030237, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1031086, - data_addrBits__h1031087, + data_address__h1031090, + data_addrBits__h1031091, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[591:463], @@ -12720,7 +12720,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h519790 ; + _theResult_____2__h519791 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12739,7 +12739,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h519246 ; + v__h519247 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12781,7 +12781,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h530567 ; + _theResult_____2__h530568 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12800,7 +12800,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h521266 ; + v__h521267 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12897,7 +12897,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h537660 ; + _theResult_____2__h537661 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12913,7 +12913,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h536985 ; + v__h536986 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12933,7 +12933,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h539796, + { x_addr__h539797, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12960,7 +12960,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h548295 ; + _theResult_____2__h548296 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12979,7 +12979,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h539434 ; + v__h539435 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13055,7 +13055,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h565907 ; + _theResult_____2__h565908 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13070,7 +13070,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h564233 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h564234 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13111,7 +13111,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h562128 ; + _theResult_____2__h562129 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13126,7 +13126,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h560454 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h560455 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13487,14 +13487,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h1006050) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h1006054) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_code_reg$D_IN = cause_code__h1006050; + csrf_mcause_code_reg$D_IN = cause_code__h1006054; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_mcause_code_reg$EN = @@ -13513,7 +13513,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h1006048) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h1006052) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = @@ -13521,7 +13521,7 @@ module mkCore(CLK, MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h1006048; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h1006052; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_mcause_interrupt_reg$EN = @@ -13708,7 +13708,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3066 : - n__read__h1025238 ; + n__read__h1025242 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -14066,14 +14066,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h1006050) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h1006054) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_code_reg$D_IN = cause_code__h1006050; + csrf_scause_code_reg$D_IN = cause_code__h1006054; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_scause_code_reg$EN = @@ -14092,7 +14092,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h1006048) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h1006052) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = @@ -14100,7 +14100,7 @@ module mkCore(CLK, MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h1006048; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h1006052; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_scause_interrupt_reg$EN = @@ -15268,7 +15268,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h954118 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h954122 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d20670, @@ -15286,7 +15286,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978582, + renaming_spec_bits__h978586, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15933,7 +15933,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0553_BITS_268_ETC___d21642, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978582, + renaming_spec_bits__h978586, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16091,7 +16091,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h505453 ; + x__h505454 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[582:581] == 2'd0) ? @@ -16523,7 +16523,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1456_AND__ETC___d22394) ? specTagManager$currentSpecBits : - renaming_spec_bits__h978582 ; + renaming_spec_bits__h978586 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1456_AND__ETC___d22403) ? @@ -16543,7 +16543,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1456_AND__ETC___d22403) ? specTagManager$currentSpecBits : - renaming_spec_bits__h978582 ; + renaming_spec_bits__h978586 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16572,8 +16572,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h215264 : - t__h217617 ; + t__h215265 : + t__h217618 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16626,7 +16626,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[2], IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[1:0], coreFix_memExe_regToExeQ$first[218:155] } : - { pointer__h245525[3:0] == 4'd0 && + { pointer__h245527[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16796,7 +16796,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[239], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h978582, + renaming_spec_bits__h978586, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17209,9 +17209,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h880397 or + new_pc__h880396 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h920770 or + new_pc__h920774 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -17222,9 +17222,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h880397; + fetchStage$redirect_pc = new_pc__h880396; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h920770; + fetchStage$redirect_pc = new_pc__h920774; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -17414,7 +17414,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h978582 ; + renaming_spec_bits__h978586 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17691,7 +17691,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0553_BITS_265_ETC___d22542, IF_NOT_fetchStage_pipelines_1_first__0553_BITS_ETC___d22613, 7'd32, - renaming_spec_bits__h978582 } ; + renaming_spec_bits__h978586 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18254,11 +18254,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h861996 }), + .amoExec_current({ 128'd0, r__h861994 }), .amoExec_inpt({ 97'd0, x__h65639 }), .amoExec(amoExec___d775)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h266168), + .amoExec_wordIdx(wordIdx__h266170), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4874, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4881, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4887 } }), @@ -18275,12 +18275,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h934999, - r1__read_BITS_13_TO_12___h935205 != + .checkForException_csrState({ x_decodeInfo_frm__h935003, + r1__read_BITS_13_TO_12___h935209 != 2'd0, - { prv__h1028925, + { prv__h1028929, csrf_tvm_reg, - { r1__read_BIT_20___h935711, + { r1__read_BIT_20___h935715, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18306,12 +18306,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h934999, - r1__read_BITS_13_TO_12___h935205 != + .checkForException_csrState({ x_decodeInfo_frm__h935003, + r1__read_BITS_13_TO_12___h935209 != 2'd0, - { prv__h1028925, + { prv__h1028929, csrf_tvm_reg, - { r1__read_BIT_20___h935711, + { r1__read_BIT_20___h935715, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18322,14 +18322,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h973083), + .checkForException_pcc(pc__h973087), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21903)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[384:222]), .capChecks_b(coreFix_memExe_regToExeQ$first[221:59]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h251630, + repBound__h251632, { csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162, csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175 } }), @@ -18340,13 +18340,13 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[221:59]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h251630, + repBound__h251632, { csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162, csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163, csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h245724), - .prepareBoundsCheck_size(x__h252365 + - y__h252366), + .prepareBoundsCheck_vaddr(tmpAddr__h245726), + .prepareBoundsCheck_size(x__h252367 + + y__h252368), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[58:12]), .prepareBoundsCheck(prepareBoundsCheck___d4263)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], @@ -18366,24 +18366,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h872615, - cr_addrBits__h872616, + { cr_address__h872613, + cr_addrBits__h872614, { coreFix_aluExe_1_regToExeQ$first[305:290], { coreFix_aluExe_1_regToExeQ$first[287], coreFix_aluExe_1_regToExeQ$first[289:288] }, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17839 } }, - repBound__h873084, + repBound__h873082, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17846, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17847, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17859 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h873163, - cr_addrBits__h873164, + { cr_address__h873161, + cr_addrBits__h873162, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h873166, - cr_reserved__h873167 }, + { cr_flags__h873164, + cr_reserved__h873165 }, INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17903 } }, - repBound__h873632, + repBound__h873630, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17910, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17911, IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17923 } }), @@ -18400,24 +18400,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h913655, - cr_addrBits__h913656, + { cr_address__h913658, + cr_addrBits__h913659, { coreFix_aluExe_0_regToExeQ$first[305:290], { coreFix_aluExe_0_regToExeQ$first[287], coreFix_aluExe_0_regToExeQ$first[289:288] }, INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20014 } }, - repBound__h914124, + repBound__h914127, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20021, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20022, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20034 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h914203, - cr_addrBits__h914204, + { cr_address__h914206, + cr_addrBits__h914207, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h914206, - cr_reserved__h914207 }, + { cr_flags__h914209, + cr_reserved__h914210 }, INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20078 } }, - repBound__h914672, + repBound__h914675, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20085, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20086, IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20098 } }), @@ -20479,11 +20479,11 @@ module mkCore(CLK, CASE_guard88489_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214) ; assign IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611 = - (_theResult____h928983 == 16'd0 && + (_theResult____h928987 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h929554 : - _theResult____h928983 ; + enabled_ints__h929558 : + _theResult____h928987 ; assign IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20964 = IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[0] || IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[1] || @@ -21286,7 +21286,7 @@ module mkCore(CLK, !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13619 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15270 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7340 = - _theResult_____2__h519790 == v__h519246 ; + _theResult_____2__h519791 == v__h519247 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7348 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7340 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7318 || @@ -21301,7 +21301,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7331 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7431 = - _theResult_____2__h530567 == v__h521266 ; + _theResult_____2__h530568 == v__h521267 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7440 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7431 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7412 || @@ -21330,9 +21330,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h526097 } ; + x__h526098 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7591 = - _theResult_____2__h537660 == v__h536985 ; + _theResult_____2__h537661 == v__h536986 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7599 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7591 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7571 || @@ -21347,7 +21347,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7584 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7675 = - _theResult_____2__h548295 == v__h539434 ; + _theResult_____2__h548296 == v__h539435 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7683 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7675 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7655 || @@ -21744,7 +21744,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7961 = - _theResult_____2__h565907 == v__h564233 ; + _theResult_____2__h565908 == v__h564234 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7969 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7961 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7942 || @@ -21759,7 +21759,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7955 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7879 = - _theResult_____2__h562128 == v__h560454 ; + _theResult_____2__h562129 == v__h560455 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7887 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7879 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7860 || @@ -21777,12 +21777,12 @@ module mkCore(CLK, (csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h1011651[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654 } : - { x__h1011651[11:3], - x__h1011672[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654[13:3], - x__h1011672[2:0] } ; + { x__h1011655[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1011658 } : + { x__h1011655[11:3], + x__h1011676[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1011658[13:3], + x__h1011676[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0544_BITS__ETC___d21530 = IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d21521 ? !csrf_rg_dcsr[2] && @@ -22024,46 +22024,46 @@ module mkCore(CLK, IF_IF_renameStage_rg_m_halt_req_0571_BIT_4_057_ETC___d21272 ; assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23509 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1019495[13:0] >= toBounds__h1019381 : - x__h1019495[13:0] <= toBoundsM1__h1019382 ; + x__h1019499[13:0] >= toBounds__h1019385 : + x__h1019499[13:0] <= toBoundsM1__h1019386 ; assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23553 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1019898[13:0] >= toBounds__h1019784 : - x__h1019898[13:0] <= toBoundsM1__h1019785 ; + x__h1019902[13:0] >= toBounds__h1019788 : + x__h1019902[13:0] <= toBoundsM1__h1019789 ; assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23648 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1020315[13:0] >= toBounds__h1020201 : - x__h1020315[13:0] <= toBoundsM1__h1020202 ; + x__h1020319[13:0] >= toBounds__h1020205 : + x__h1020319[13:0] <= toBoundsM1__h1020206 ; assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23690 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1020718[13:0] >= toBounds__h1020604 : - x__h1020718[13:0] <= toBoundsM1__h1020605 ; + x__h1020722[13:0] >= toBounds__h1020608 : + x__h1020722[13:0] <= toBoundsM1__h1020609 ; assign IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23803 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63] ? - x__h1021387[13:0] >= toBounds__h1021273 : - x__h1021387[13:0] <= toBoundsM1__h1021274 ; + x__h1021391[13:0] >= toBounds__h1021277 : + x__h1021391[13:0] <= toBoundsM1__h1021278 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d1958 = - { INV_x85172_BITS_108_TO_90__q35[0] ? x__h185292 : 6'd0, - x__h185452, - x__h185472 } ; + { INV_x85173_BITS_108_TO_90__q35[0] ? x__h185293 : 6'd0, + x__h185453, + x__h185473 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__502_BITS_ETC___d2126 = - { INV_x01336_BITS_108_TO_90__q37[0] ? x__h204355 : 6'd0, - x__h204515, - x__h204535 } ; + { INV_x01337_BITS_108_TO_90__q37[0] ? x__h204356 : 6'd0, + x__h204516, + x__h204536 } ; assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h1005679 : + x__h1005683 : 6'd0 ; assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23038 = - x__h1005859[13:11] < repBound__h1008366 ; + x__h1005863[13:11] < repBound__h1008370 ; assign IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23040 = - pc_addrBits__h1005470[13:11] < repBound__h1008366 ; + pc_addrBits__h1005474[13:11] < repBound__h1008370 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20021 = - tb__h914121 < repBound__h914124 ; + tb__h914124 < repBound__h914127 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20022 = - x__h914063[13:11] < repBound__h914124 ; + x__h914066[13:11] < repBound__h914127 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20024 = - cr_addrBits__h913656[13:11] < repBound__h914124 ; + cr_addrBits__h913659[13:11] < repBound__h914127 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20034 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20024, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20021 == @@ -22081,11 +22081,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20085 = - tb__h914669 < repBound__h914672 ; + tb__h914672 < repBound__h914675 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20086 = - x__h914611[13:11] < repBound__h914672 ; + x__h914614[13:11] < repBound__h914675 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20088 = - cr_addrBits__h914204[13:11] < repBound__h914672 ; + cr_addrBits__h914207[13:11] < repBound__h914675 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20098 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20088, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9699__ETC___d20085 == @@ -22103,11 +22103,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17846 = - tb__h873081 < repBound__h873084 ; + tb__h873079 < repBound__h873082 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17847 = - x__h873023[13:11] < repBound__h873084 ; + x__h873021[13:11] < repBound__h873082 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17849 = - cr_addrBits__h872616[13:11] < repBound__h873084 ; + cr_addrBits__h872614[13:11] < repBound__h873082 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17859 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17849, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17846 == @@ -22125,11 +22125,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17910 = - tb__h873629 < repBound__h873632 ; + tb__h873627 < repBound__h873630 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17911 = - x__h873571[13:11] < repBound__h873632 ; + x__h873569[13:11] < repBound__h873630 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17913 = - cr_addrBits__h873164[13:11] < repBound__h873632 ; + cr_addrBits__h873162[13:11] < repBound__h873630 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17923 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17913, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7524__ETC___d17910 == @@ -22148,10 +22148,10 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_166_BITS_108__ETC___d2217 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h219326 : + x__h219327 : 6'd0, - x__h219486, - x__h219506 } ; + x__h219487, + x__h219507 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_235__ETC___d1275 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? x__h128367 : @@ -24073,11 +24073,11 @@ module mkCore(CLK, _theResult___fst_exp__h615438 != 8'd255 && guard__h607361 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__664_BI_ETC___d4114 = - offset__h245515[63] ? - x__h245664[13:0] >= toBounds__h245543 && - repBoundBits__h245540 != + offset__h245517[63] ? + x__h245666[13:0] >= toBounds__h245545 && + repBoundBits__h245542 != coreFix_memExe_regToExeQ$first[317:304] : - x__h245664[13:0] < toBoundsM1__h245544 ; + x__h245666[13:0] < toBoundsM1__h245546 ; assign IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121 = basicExec___d20102[325] ? { basicExec___d20102[316:308], @@ -24179,24 +24179,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d18866 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19070 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h899820 : + res_address__h899822 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19068 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19085 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h899821 : + res_addrBits__h899823 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19083 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h906787 : + thin_reserved__h906790 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h906788 : + thin_otype__h906791 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19624, @@ -24205,7 +24205,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19637 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h906963 : + thin_perms_soft__h906966 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19482, @@ -24236,18 +24236,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19636 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19638 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h906783 : + thin_address__h906786 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h906784 : + thin_addrBits__h906787 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19637 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19659 = - thin_bounds_topBits__h908189[13:11] < repBound__h908305 ; + thin_bounds_topBits__h908192[13:11] < repBound__h908308 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19661 = - thin_bounds_baseBits__h908190[13:11] < repBound__h908305 ; + thin_bounds_baseBits__h908193[13:11] < repBound__h908308 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19664 = - thin_addrBits__h906784[13:11] < repBound__h908305 ; + thin_addrBits__h906787[13:11] < repBound__h908308 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20379 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -24494,24 +24494,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d16044 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d16616 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h855056 : + res_address__h855055 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16614 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d16631 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h855057 : + res_addrBits__h855056 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16629 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h864890 : + thin_reserved__h864888 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h864891 : + thin_otype__h864889 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17418, @@ -24520,7 +24520,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17444 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h865126 : + thin_perms_soft__h865124 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17081, @@ -24551,18 +24551,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17443 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17445 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h864886 : + thin_address__h864884 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h864887 : + thin_addrBits__h864885 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17444 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17484 = - thin_bounds_topBits__h866834[13:11] < repBound__h866970 ; + thin_bounds_topBits__h866832[13:11] < repBound__h866968 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17486 = - thin_bounds_baseBits__h866835[13:11] < repBound__h866970 ; + thin_bounds_baseBits__h866833[13:11] < repBound__h866968 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17489 = - thin_addrBits__h864887[13:11] < repBound__h866970 ; + thin_addrBits__h864885[13:11] < repBound__h866968 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18205 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -25343,8 +25343,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20485 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h924561 : - w__h924556 ; + result__h924565 : + w__h924560 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5034 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25818,15 +25818,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__695_BIT_1_ETC___d3653 } ; assign IF_coreFix_memExe_dispToRegQ_first__695_BIT_12_ETC___d3097 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h238212 : + res_addrBits__h238214 : ((coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3095 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__695_BIT_12_ETC___d3341 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h238211 : - x__h238634, + res_address__h238213 : + x__h238636, IF_coreFix_memExe_dispToRegQ_first__695_BIT_12_ETC___d3097, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25965,13 +25965,13 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__502_BIT_113_517_ETC___d2084 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4268 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h245525[3:0] != 4'd0 : + pointer__h245527[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h245525[2:0] != 3'd0 : + pointer__h245527[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h245525[1:0] != 2'd0 : + pointer__h245527[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h245525[0])), + pointer__h245527[0])), capChecks___d4179[11:5], CASE_capChecks_179_BITS_4_TO_0_0_capChecks_179_ETC__q294, prepareBoundsCheck___d4263 } ; @@ -26003,10 +26003,10 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[13:0] ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16430 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[13:11] < - repBound__h861803 ; + repBound__h861801 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16432 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423[13:11] < - repBound__h861803 ; + repBound__h861801 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26107,7 +26107,7 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23218 = - ((newAddrDiff__h1010925 == 64'd0) ? + ((newAddrDiff__h1010929 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23199 ? 2'd3 : @@ -26124,12 +26124,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23221 = IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23218 && - (newAddrDiff__h1010925 == 64'd0 || + (newAddrDiff__h1010929 == 64'd0 || csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23199 || - newAddrDiff__h1010925 == + newAddrDiff__h1010929 == _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23202) ; assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23243 = - ((newAddrDiff__h1011269 == 64'd0) ? + ((newAddrDiff__h1011273 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23227 ? 2'd3 : @@ -26146,12 +26146,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23246 = IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23243 && - (newAddrDiff__h1011269 == 64'd0 || + (newAddrDiff__h1011273 == 64'd0 || csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23227 || - newAddrDiff__h1011269 == + newAddrDiff__h1011273 == _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23202) ; assign IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23249 = - (csrf_mtcc_reg[86] && cause_interrupt__h1006048) ? + (csrf_mtcc_reg[86] && cause_interrupt__h1006052) ? (NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188 || IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23221) && csrf_mtcc_reg[152] : @@ -26159,9 +26159,9 @@ module mkCore(CLK, IF_csrf_mtcc_reg_read__6389_BITS_149_TO_86_318_ETC___d23246) && csrf_mtcc_reg[152] ; assign IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23283 = - (csrf_mtcc_reg[86] && cause_interrupt__h1006048) ? - address__h1010245 : - base__h1010210 ; + (csrf_mtcc_reg[86] && cause_interrupt__h1006052) ? + address__h1010249 : + base__h1010214 ; assign IF_csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_c_ETC___d23254 = csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? { IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23180, @@ -26191,10 +26191,10 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[13:0] ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16278 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[13:11] < - repBound__h860811 ; + repBound__h860809 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16280 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271[13:11] < - repBound__h860811 ; + repBound__h860809 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26295,7 +26295,7 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23149 = - ((newAddrDiff__h1010268 == 64'd0) ? + ((newAddrDiff__h1010272 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23130 ? 2'd3 : @@ -26312,12 +26312,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23152 = IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23149 && - (newAddrDiff__h1010268 == 64'd0 || + (newAddrDiff__h1010272 == 64'd0 || csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23130 || - newAddrDiff__h1010268 == + newAddrDiff__h1010272 == _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23133) ; assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23174 = - ((newAddrDiff__h1010612 == 64'd0) ? + ((newAddrDiff__h1010616 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23158 ? 2'd3 : @@ -26334,12 +26334,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23177 = IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23174 && - (newAddrDiff__h1010612 == 64'd0 || + (newAddrDiff__h1010616 == 64'd0 || csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23158 || - newAddrDiff__h1010612 == + newAddrDiff__h1010616 == _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23133) ; assign IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23180 = - (csrf_stcc_reg[86] && cause_interrupt__h1006048) ? + (csrf_stcc_reg[86] && cause_interrupt__h1006052) ? (NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117 || IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23152) && csrf_stcc_reg[152] : @@ -26347,29 +26347,29 @@ module mkCore(CLK, IF_csrf_stcc_reg_read__6237_BITS_149_TO_86_311_ETC___d23177) && csrf_stcc_reg[152] ; assign IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23282 = - (csrf_stcc_reg[86] && cause_interrupt__h1006048) ? - address__h1010195 : - base__h1010156 ; + (csrf_stcc_reg[86] && cause_interrupt__h1006052) ? + address__h1010199 : + base__h1010160 ; assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24525 = f_csr_reqs$D_OUT[63] ? - x__h1043062[13:0] >= toBounds__h1019381 : - x__h1043062[13:0] <= toBoundsM1__h1019382 ; + x__h1043066[13:0] >= toBounds__h1019385 : + x__h1043066[13:0] <= toBoundsM1__h1019386 ; assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24547 = f_csr_reqs$D_OUT[63] ? - x__h1043465[13:0] >= toBounds__h1019784 : - x__h1043465[13:0] <= toBoundsM1__h1019785 ; + x__h1043469[13:0] >= toBounds__h1019788 : + x__h1043469[13:0] <= toBoundsM1__h1019789 ; assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24605 = f_csr_reqs$D_OUT[63] ? - x__h1043882[13:0] >= toBounds__h1020201 : - x__h1043882[13:0] <= toBoundsM1__h1020202 ; + x__h1043886[13:0] >= toBounds__h1020205 : + x__h1043886[13:0] <= toBoundsM1__h1020206 ; assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24625 = f_csr_reqs$D_OUT[63] ? - x__h1044285[13:0] >= toBounds__h1020604 : - x__h1044285[13:0] <= toBoundsM1__h1020605 ; + x__h1044289[13:0] >= toBounds__h1020608 : + x__h1044289[13:0] <= toBoundsM1__h1020609 ; assign IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24696 = f_csr_reqs$D_OUT[63] ? - x__h1044952[13:0] >= toBounds__h1021273 : - x__h1044952[13:0] <= toBoundsM1__h1021274 ; + x__h1044956[13:0] >= toBounds__h1021277 : + x__h1044956[13:0] <= toBoundsM1__h1021278 ; assign IF_fetchStage_RDY_pipelines_0_first__0541_AND__ETC___d21486 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[268:266] != 3'd1 || @@ -26795,36 +26795,36 @@ module mkCore(CLK, 2'd3) } ; assign IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1027265 : + y_avValue_snd_snd_snd_snd_snd__h1027269 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1027249 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1027253 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1027259 : + y_avValue_snd_snd_snd_fst__h1027263 : 2'd0 ; assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23512 = - (highOffsetBits__h1019372 == 50'd0 && + (highOffsetBits__h1019376 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23509 || NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117) && csrf_stcc_reg[152] ; assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23558 = - (highOffsetBits__h1019775 == 50'd0 && + (highOffsetBits__h1019779 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23553 || NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23556) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16993 ; assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23651 = - (highOffsetBits__h1020192 == 50'd0 && + (highOffsetBits__h1020196 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23648 || NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188) && csrf_mtcc_reg[152] ; assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23695 = - (highOffsetBits__h1020595 == 50'd0 && + (highOffsetBits__h1020599 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23690 || NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23693) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17001 ; assign IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_19_ETC___d23809 = - (highOffsetBits__h1021264 == 50'd0 && + (highOffsetBits__h1021268 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2632_BITS_196_TO_ETC___d23803 || NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23806) && csrf_rg_dpc[152] ; @@ -26960,7 +26960,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19319) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19341 = sbCons$lazyLookup_0_get[3] ? - repBound__h905960 : + repBound__h905963 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8635_8_ETC___d18662 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__863_ETC___d19337) ; @@ -26991,7 +26991,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19438 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h908287, + repBound__h908290, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19413, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19414, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19426 } : @@ -27126,7 +27126,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16865) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16887 = sbCons$lazyLookup_1_get[3] ? - repBound__h863990 : + repBound__h863988 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5813_5_ETC___d15840 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__581_ETC___d16883) ; @@ -27157,7 +27157,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16984 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h866952, + repBound__h866950, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16959, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16960, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16972 } : @@ -27292,7 +27292,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3331) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3353 = sbCons$lazyLookup_3_get[3] ? - repBound__h240206 : + repBound__h240208 : (NOT_coreFix_memExe_bypassWire_0_whas__716_722__ETC___d2743 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3349) ; @@ -27448,7 +27448,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3591) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3608 = sbCons$lazyLookup_3_get[2] ? - repBound__h241891 : + repBound__h241893 : (NOT_coreFix_memExe_bypassWire_0_whas__716_722__ETC___d2774 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__716_7_ETC___d3604) ; @@ -27523,17 +27523,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20014 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h913870 : + x__h913873 : 6'd0, - x__h914043, - x__h914063 } ; + x__h914046, + x__h914066 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9699_BIT_ETC___d20078 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h914418 : + x__h914421 : 6'd0, - x__h914591, - x__h914611 } ; + x__h914594, + x__h914614 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -27541,17 +27541,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17839 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h872830 : + x__h872828 : 6'd0, - x__h873003, - x__h873023 } ; + x__h873001, + x__h873021 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7524_BIT_ETC___d17903 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h873378 : + x__h873376 : 6'd0, - x__h873551, - x__h873571 } ; + x__h873549, + x__h873569 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -27562,8 +27562,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x01336_BITS_108_TO_90__q37 = ~x__h201336[108:90] ; - assign INV_x85172_BITS_108_TO_90__q35 = ~x__h185172[108:90] ; + assign INV_x01337_BITS_108_TO_90__q37 = ~x__h201337[108:90] ; + assign INV_x85173_BITS_108_TO_90__q35 = ~x__h185173[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10837 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9623 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? @@ -27652,10 +27652,10 @@ module mkCore(CLK, !checkForException___d21903[13] && NOT_csrf_fs_reg_read__6201_EQ_0_0928_0929_OR_N_ETC___d21928 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__3985_3986_OR__ETC___d24236 = - (fflags__h1027832 & csrf_fflags_reg) != fflags__h1027832 || - !r__h859552 && + (fflags__h1027836 & csrf_fflags_reg) != fflags__h1027836 || + !r__h859550 && (IF_rob_deqPort_1_canDeq__3989_THEN_IF_NOT_rob__ETC___d24231 || - fflags__h1027832 != 5'd0) ; + fflags__h1027836 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12813 = !f1_sfd__h719829[21] && !f1_sfd__h719829[20] && !f1_sfd__h719829[19] && @@ -28794,7 +28794,7 @@ module mkCore(CLK, SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1491_co_ETC___d21524 ; assign NOT_fetchStage_pipelines_0_first__0544_BITS_46_ETC___d22338 = fetchStage$pipelines_0_first[462:334] != - fallthrough_pc__h948605 ; + fallthrough_pc__h948609 ; assign NOT_fetchStage_pipelines_0_first__0544_BIT_69__ETC___d21014 = !fetchStage$pipelines_0_first[69] && !IF_IF_NOT_csrf_prv_reg_read__0574_EQ_3_0575_05_ETC___d20611[0] && @@ -28874,7 +28874,7 @@ module mkCore(CLK, SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__054_ETC___d22215 ; assign NOT_fetchStage_pipelines_1_first__0553_BITS_46_ETC___d22522 = fetchStage$pipelines_1_first[462:334] != - fallthrough_pc__h973092 ; + fallthrough_pc__h973096 ; assign NOT_fetchStage_pipelines_1_first__0553_BIT_69__ETC___d22460 = !fetchStage$pipelines_1_first[69] && !checkForException___d21903[13] && @@ -29042,7 +29042,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7225, - x__h513121 } ; + x__h513122 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24866 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q320, @@ -29120,21 +29120,21 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4901 = - { {64{x__h267667[63]}}, x__h267667 } ; + { {64{x__h267669[63]}}, x__h267669 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4909 = - { {96{x__h267822[31]}}, x__h267822 } ; + { {96{x__h267824[31]}}, x__h267824 } ; assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23054 = - x__h1008354 | in__h1008423[63:0] ; + x__h1008358 | in__h1008427[63:0] ; assign SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 = - x__h861639 | in__h861864[63:0] ; + x__h861637 | in__h861862[63:0] ; assign SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 = - x__h860646 | in__h860872[63:0] ; + x__h860644 | in__h860870[63:0] ; assign SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 = - x__h903946 | in__h861560[63:0] ; + x__h903949 | in__h861558[63:0] ; assign SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 = - x__h904291 | in__h862390[63:0] ; + x__h904294 | in__h862388[63:0] ; assign SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 = - x__h903662 | in__h860567[63:0] ; + x__h903665 | in__h860565[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10162 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q84[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q84 } ; @@ -29484,17 +29484,17 @@ module mkCore(CLK, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; assign _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23210 = - x__h1011112[13:11] < repBound__h861482 ; + x__h1011116[13:11] < repBound__h861480 ; assign _0_CONCAT_csrf_mtcc_reg_read__6389_BITS_149_TO__ETC___d23235 = - x__h1011416[13:11] < repBound__h861482 ; + x__h1011420[13:11] < repBound__h861480 ; assign _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23141 = - x__h1010455[13:11] < repBound__h860489 ; + x__h1010459[13:11] < repBound__h860487 ; assign _0_CONCAT_csrf_stcc_reg_read__6237_BITS_149_TO__ETC___d23166 = - x__h1010759[13:11] < repBound__h860489 ; + x__h1010763[13:11] < repBound__h860487 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0544_BI_ETC___d22140 = (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; + CASE_k54122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0553_BI_ETC___d22038 = (fetchStage$pipelines_1_first[268:266] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -29532,13 +29532,13 @@ module mkCore(CLK, 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8768) ; assign _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6352_6_ETC___d23018 = - medeleg_csr__read__h856636[i__h1006066] ; + medeleg_csr__read__h856634[i__h1006070] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6363_6364_ETC___d23021 = - mideleg_csr__read__h856734[i__h1006266] ; + mideleg_csr__read__h856732[i__h1006270] ; assign _18446744073709551615_SL_csrf_mtcc_reg_read__63_ETC___d23202 = - mask__h1010924 ^ y__h1011041 ; + mask__h1010928 ^ y__h1011045 ; assign _18446744073709551615_SL_csrf_stcc_reg_read__62_ETC___d23133 = - mask__h1010267 ^ y__h1010384 ; + mask__h1010271 ^ y__h1010388 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10800 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9623 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9624 ? @@ -30135,7 +30135,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22535 && fetchStage$pipelines_1_first[273:269] != 5'd19 ; assign _dfoo16 = - k__h954118 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h954122 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314 || (fetchStage_pipelines_0_canDeq__0542_AND_NOT_fe_ETC___d22435 || NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22448) == @@ -30143,7 +30143,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22453 && NOT_fetchStage_pipelines_1_first__0553_BITS_26_ETC___d22465 ; assign _dfoo18 = - k__h954118 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h954122 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22314 || (fetchStage_pipelines_0_canDeq__0542_AND_NOT_fe_ETC___d22435 || NOT_fetchStage_pipelines_0_canDeq__0542_0543_O_ETC___d22448) == @@ -30278,29 +30278,29 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h519790 = + assign _theResult_____2__h519791 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7331 ? - next_deqP___1__h520035 : + next_deqP___1__h520036 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h530567 = + assign _theResult_____2__h530568 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7425 ? - next_deqP___1__h530812 : + next_deqP___1__h530813 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h537660 = + assign _theResult_____2__h537661 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7584 ? - next_deqP___1__h538090 : + next_deqP___1__h538091 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h548295 = + assign _theResult_____2__h548296 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7668 ? - next_deqP___1__h548725 : + next_deqP___1__h548726 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h562128 = + assign _theResult_____2__h562129 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7873 ? - next_deqP___1__h562373 : + next_deqP___1__h562374 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h565907 = + assign _theResult_____2__h565908 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7955 ? - next_deqP___1__h566152 : + next_deqP___1__h566153 : coreFix_memExe_forwardQ_deqP ; assign _theResult____h580876 = (value__h581498 == 54'd0) ? sfd__h573271 : 57'd1 ; @@ -30344,9 +30344,9 @@ module mkCore(CLK, 12'd2105) ? result__h819327 : ((value__h802930 == 25'd0) ? sfd__h798488 : 57'd1) ; - assign _theResult____h928983 = + assign _theResult____h928987 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h929508 : + enabled_ints___1__h929512 : 16'd0 ; assign _theResult___exp__h589503 = sfd__h589079[24] ? @@ -33050,40 +33050,40 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? a___1__h840836 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h1019584 = - { {48{base__h903649[15]}}, base__h903649 } << + assign addBase__h1019588 = + { {48{base__h903652[15]}}, base__h903652 } << csrf_stcc_reg[33:28] ; - assign addBase__h1019987 = - { {48{base__h860633[15]}}, base__h860633 } << + assign addBase__h1019991 = + { {48{base__h860631[15]}}, base__h860631 } << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign addBase__h1020404 = - { {48{base__h903933[15]}}, base__h903933 } << + assign addBase__h1020408 = + { {48{base__h903936[15]}}, base__h903936 } << csrf_mtcc_reg[33:28] ; - assign addBase__h1020807 = - { {48{base__h861626[15]}}, base__h861626 } << + assign addBase__h1020811 = + { {48{base__h861624[15]}}, base__h861624 } << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign addBase__h1021477 = - { {48{base__h904278[15]}}, base__h904278 } << + assign addBase__h1021481 = + { {48{base__h904281[15]}}, base__h904281 } << csrf_rg_dpc[33:28] ; - assign addBase__h242754 = - { {48{base__h242589[15]}}, base__h242589 } << + assign addBase__h242756 = + { {48{base__h242591[15]}}, base__h242591 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addBase__h243911 = - { {48{base__h243746[15]}}, base__h243746 } << + assign addBase__h243913 = + { {48{base__h243748[15]}}, base__h243748 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addBase__h257532 = - { {48{base__h257367[15]}}, base__h257367 } << + assign addBase__h257534 = + { {48{base__h257369[15]}}, base__h257369 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h242863 = - { {50{x__h242962[15]}}, x__h242962 } << + assign addTop__h242865 = + { {50{x__h242964[15]}}, x__h242964 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addTop__h244020 = - { {50{x__h244119[15]}}, x__h244119 } << + assign addTop__h244022 = + { {50{x__h244121[15]}}, x__h244121 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addTop__h257641 = - { {50{x__h257740[15]}}, x__h257740 } << + assign addTop__h257643 = + { {50{x__h257742[15]}}, x__h257742 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addr__h1000330 = + assign addr__h1000334 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? @@ -33097,24 +33097,24 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h238205 = x__h238634[63:0] + csrf_ddc_reg[149:86] ; - assign address__h1010195 = base__h1010156 + { 57'd0, x__h1010354 } ; - assign address__h1010245 = base__h1010210 + { 57'd0, x__h1010354 } ; - assign address__h1010261 = { 2'd0, address__h1010195 } ; - assign address__h1010605 = { 2'd0, base__h1010156 } ; - assign address__h1010918 = { 2'd0, address__h1010245 } ; - assign address__h1011262 = { 2'd0, base__h1010210 } ; - assign address__h1023320 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h874071 = + assign addr__h238207 = x__h238636[63:0] + csrf_ddc_reg[149:86] ; + assign address__h1010199 = base__h1010160 + { 57'd0, x__h1010358 } ; + assign address__h1010249 = base__h1010214 + { 57'd0, x__h1010358 } ; + assign address__h1010265 = { 2'd0, address__h1010199 } ; + assign address__h1010609 = { 2'd0, base__h1010160 } ; + assign address__h1010922 = { 2'd0, address__h1010249 } ; + assign address__h1011266 = { 2'd0, base__h1010214 } ; + assign address__h1023324 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h874069 = coreFix_aluExe_1_regToExeQ$first[241:178] + 64'd4 ; - assign address__h915075 = + assign address__h915078 = coreFix_aluExe_0_regToExeQ$first[241:178] + 64'd4 ; - assign address__h965680 = + assign address__h965684 = fetchStage$pipelines_0_first[526:463] + - { {52{inc__h965679[11]}}, inc__h965679 } ; - assign address__h990656 = + { {52{inc__h965683[11]}}, inc__h965683 } ; + assign address__h990660 = fetchStage$pipelines_1_first[526:463] + - { {52{inc__h990655[11]}}, inc__h990655 } ; + { {52{inc__h990659[11]}}, inc__h990659 } ; assign b___1__h840837 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q24[31]}}, @@ -33129,7 +33129,7 @@ module mkCore(CLK, assign b__h840898 = { {64{b__h840675[63]}}, b__h840675 } ; assign b__h840999 = { 64'd0, a__h840674 } ; assign b__h841011 = { 64'd0, b__h840675 } ; - assign b_base__h1005866 = + assign b_base__h1005870 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; @@ -33141,31 +33141,31 @@ module mkCore(CLK, { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h185479 = - { x__h185172[77:67], ~x__h185172[66], x__h185172[65:64] } ; - assign b_base__h204542 = - { x__h201336[77:67], ~x__h201336[66], x__h201336[65:64] } ; - assign b_base__h219513 = + assign b_base__h185480 = + { x__h185173[77:67], ~x__h185173[66], x__h185173[65:64] } ; + assign b_base__h204543 = + { x__h201337[77:67], ~x__h201337[66], x__h201337[65:64] } ; + assign b_base__h219514 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h873030 = + assign b_base__h873028 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h873578 = + assign b_base__h873576 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h914070 = + assign b_base__h914073 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h914618 = + assign b_base__h914621 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_top__h1005865 = + assign b_top__h1005869 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; @@ -33177,31 +33177,31 @@ module mkCore(CLK, { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h185478 = - { x__h185172[89:81], ~x__h185172[80:79], x__h185172[78] } ; - assign b_top__h204541 = - { x__h201336[89:81], ~x__h201336[80:79], x__h201336[78] } ; - assign b_top__h219512 = + assign b_top__h185479 = + { x__h185173[89:81], ~x__h185173[80:79], x__h185173[78] } ; + assign b_top__h204542 = + { x__h201337[89:81], ~x__h201337[80:79], x__h201337[78] } ; + assign b_top__h219513 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h873029 = + assign b_top__h873027 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h873577 = + assign b_top__h873575 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h914069 = + assign b_top__h914072 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h914617 = + assign b_top__h914620 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign base__h1008341 = + assign base__h1008345 = { (IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23038 == IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23040) ? 2'd0 : @@ -33209,19 +33209,19 @@ module mkCore(CLK, !IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d23040) ? 2'd1 : 2'd3), - x__h1005859 } ; - assign base__h1010156 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h1010210 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign base__h242589 = + x__h1005863 } ; + assign base__h1010160 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h1010214 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign base__h242591 = { coreFix_memExe_regToExeQ$first[223:222], coreFix_memExe_regToExeQ$first[245:232] } ; - assign base__h243746 = + assign base__h243748 = { coreFix_memExe_regToExeQ$first[60:59], coreFix_memExe_regToExeQ$first[82:69] } ; - assign base__h257367 = + assign base__h257369 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h860633 = + assign base__h860631 = { (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16278 == IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16280) ? 2'd0 : @@ -33230,7 +33230,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275 } ; - assign base__h861626 = + assign base__h861624 = { (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16430 == IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16432) ? 2'd0 : @@ -33239,7 +33239,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427 } ; - assign base__h903649 = + assign base__h903652 = { (csrf_stcc_reg_read__6237_BITS_13_TO_11_6240_UL_ETC___d16242 == csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244) ? 2'd0 : @@ -33248,7 +33248,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_stcc_reg[13:0] } ; - assign base__h903933 = + assign base__h903936 = { (csrf_mtcc_reg_read__6389_BITS_13_TO_11_6392_UL_ETC___d16394 == csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396) ? 2'd0 : @@ -33257,7 +33257,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_mtcc_reg[13:0] } ; - assign base__h904278 = + assign base__h904281 = { (csrf_rg_dpc_read__6534_BITS_13_TO_11_6537_ULT__ETC___d16539 == csrf_rg_dpc_read__6534_BITS_85_TO_83_6540_ULT__ETC___d16541) ? 2'd0 : @@ -33266,47 +33266,47 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_rg_dpc[13:0] } ; - assign bot__h1019587 = - { csrf_stcc_reg[149:100] & highBitsfilter__h1019371, 14'd0 } + - addBase__h1019584 ; - assign bot__h1019990 = + assign bot__h1019591 = + { csrf_stcc_reg[149:100] & highBitsfilter__h1019375, 14'd0 } + + addBase__h1019588 ; + assign bot__h1019994 = { IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295[63:14] & - highBitsfilter__h1019774, + highBitsfilter__h1019778, 14'd0 } + - addBase__h1019987 ; - assign bot__h1020407 = - { csrf_mtcc_reg[149:100] & highBitsfilter__h1020191, 14'd0 } + - addBase__h1020404 ; - assign bot__h1020810 = + addBase__h1019991 ; + assign bot__h1020411 = + { csrf_mtcc_reg[149:100] & highBitsfilter__h1020195, 14'd0 } + + addBase__h1020408 ; + assign bot__h1020814 = { IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447[63:14] & - highBitsfilter__h1020594, + highBitsfilter__h1020598, 14'd0 } + - addBase__h1020807 ; - assign bot__h1021480 = - { csrf_rg_dpc[149:100] & highBitsfilter__h1021263, 14'd0 } + - addBase__h1021477 ; - assign carry_out__h1005770 = - (topBits__h1005768 < x__h1005859[11:0]) ? 2'b01 : 2'b0 ; + addBase__h1020811 ; + assign bot__h1021484 = + { csrf_rg_dpc[149:100] & highBitsfilter__h1021267, 14'd0 } + + addBase__h1021481 ; + assign carry_out__h1005774 = + (topBits__h1005772 < x__h1005863[11:0]) ? 2'b01 : 2'b0 ; assign carry_out__h128458 = (topBits__h128456 < x__h128547[11:0]) ? 2'b01 : 2'b0 ; assign carry_out__h141602 = (topBits__h141600 < x__h141691[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h185383 = - (topBits__h185381 < x__h185472[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h204446 = - (topBits__h204444 < x__h204535[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h219417 = - (topBits__h219415 < x__h219506[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h872933 = - (topBits__h872931 < x__h873023[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h873481 = - (topBits__h873479 < x__h873571[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h913973 = - (topBits__h913971 < x__h914063[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h914521 = - (topBits__h914519 < x__h914611[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h1007625 = { 1'd0, i__h1006266 } ; - assign cause_interrupt__h1006048 = + assign carry_out__h185384 = + (topBits__h185382 < x__h185473[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h204447 = + (topBits__h204445 < x__h204536[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h219418 = + (topBits__h219416 < x__h219507[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h872931 = + (topBits__h872929 < x__h873021[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h873479 = + (topBits__h873477 < x__h873569[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h913976 = + (topBits__h913974 < x__h914066[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h914524 = + (topBits__h914522 < x__h914614[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h1007629 = { 1'd0, i__h1006270 } ; + assign cause_interrupt__h1006052 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2639_BITS_44_TO_43_2837_ETC___d22877 = @@ -33390,7 +33390,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19446, IF_coreFix_aluExe_0_dispToRegQ_first__8612_BIT_ETC___d19638, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h908305 : + repBound__h908308 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8612_BI_ETC___d19678 } ; assign coreFix_aluExe_0_exeToFinQ_first__0233_BITS_14_ETC___d20267 = @@ -33452,7 +33452,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17009, IF_coreFix_aluExe_1_dispToRegQ_first__5790_BIT_ETC___d17445, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h866970 : + repBound__h866968 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5790_BI_ETC___d17503 } ; assign coreFix_aluExe_1_exeToFinQ_first__8058_BITS_14_ETC___d18093 = @@ -33607,7 +33607,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5046 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h426314 ; + y__h426315 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5655 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -35813,12 +35813,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__276_BITS_334_TO__ETC___d4439 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[64:63] - - { 1'd0, x__h257809 } > + { 1'd0, x__h257811 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h257642, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h257644, 14'd0 } + - addTop__h257641 ; + addTop__h257643 ; assign coreFix_memExe_dTlb_procResp__276_BITS_490_TO__ETC___d4784 = coreFix_memExe_dTlb$procResp[490:488] == 3'd0 && NOT_coreFix_memExe_dTlb_procResp__276_BITS_560_ETC___d4600 && @@ -35869,15 +35869,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__695_BIT_10_ETC___d3599 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4269 = - { coreFix_memExe_lsq$getOrigBE << pointer__h245525[3:0], - (highOffsetBits__h245534 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h245527[3:0], + (highOffsetBits__h245536 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__664_BI_ETC___d4114 || coreFix_memExe_regToExeQ$first[265:260] >= 6'd50) && coreFix_memExe_regToExeQ$first[384], - result_d_address__h245736, - x__h251007[13:0], + result_d_address__h245738, + x__h251009[13:0], coreFix_memExe_regToExeQ$first[303:232], - repBound__h251105, + repBound__h251107, coreFix_memExe_regToExeQ_first__664_BITS_259_T_ETC___d4129, coreFix_memExe_regToExeQ_first__664_BITS_245_T_ETC___d4130, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4142, @@ -35898,7 +35898,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__664_BITS_102_T_ETC___d3798 = coreFix_memExe_regToExeQ$first[102:97] < 6'd51 && coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[64:63] - - { 1'd0, x__h244188 } > + { 1'd0, x__h244190 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__664_BITS_140_T_ETC___d4089 = { coreFix_memExe_regToExeQ$first[140:125], @@ -35911,26 +35911,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[2], IF_coreFix_memExe_regToExeQ_first__664_BIT_103_ETC___d4036[1:0], coreFix_memExe_regToExeQ$first[218:155] } << - x__h247565 ; + x__h247567 ; assign coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785 = - { coreFix_memExe_regToExeQ$first[220:169] & mask__h244021, + { coreFix_memExe_regToExeQ$first[220:169] & mask__h244023, 14'd0 } + - addTop__h244020 ; + addTop__h244022 ; assign coreFix_memExe_regToExeQ_first__664_BITS_245_T_ETC___d4130 = - coreFix_memExe_regToExeQ$first[245:243] < repBound__h251105 ; + coreFix_memExe_regToExeQ$first[245:243] < repBound__h251107 ; assign coreFix_memExe_regToExeQ_first__664_BITS_259_T_ETC___d4129 = - coreFix_memExe_regToExeQ$first[259:257] < repBound__h251105 ; + coreFix_memExe_regToExeQ$first[259:257] < repBound__h251107 ; assign coreFix_memExe_regToExeQ_first__664_BITS_265_T_ETC___d3736 = coreFix_memExe_regToExeQ$first[265:260] < 6'd51 && coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[64:63] - - { 1'd0, x__h243031 } > + { 1'd0, x__h243033 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723 = - { coreFix_memExe_regToExeQ$first[383:332] & mask__h242864, + { coreFix_memExe_regToExeQ$first[383:332] & mask__h242866, 14'd0 } + - addTop__h242863 ; + addTop__h242865 ; assign coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4132 = - x__h251007[13:11] < repBound__h251105 ; + x__h251009[13:11] < repBound__h251107 ; assign coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4142 = { coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d4132, (coreFix_memExe_regToExeQ_first__664_BITS_259_T_ETC___d4129 == @@ -35971,40 +35971,40 @@ module mkCore(CLK, fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__2632_BITS_469_TO_4_ETC___d23400 ; - assign cr_addrBits__h872616 = + assign cr_addrBits__h872614 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h872792[13:0] : + x__h872790[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h873164 = + assign cr_addrBits__h873162 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h873340[13:0] : + x__h873338[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h913656 = + assign cr_addrBits__h913659 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h913832[13:0] : + x__h913835[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h914204 = + assign cr_addrBits__h914207 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h914380[13:0] : + x__h914383[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h872615 = + assign cr_address__h872613 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h873163 = + assign cr_address__h873161 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h913655 = + assign cr_address__h913658 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h914203 = + assign cr_address__h914206 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h873166 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h914206 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h873167 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h914207 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h873164 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h914209 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h873165 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h914210 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__078_BITS_13_TO_11_159_ULT_c_ETC___d4163 = - csrf_ddc_reg[13:11] < repBound__h251630 ; + csrf_ddc_reg[13:11] < repBound__h251632 ; assign csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162 = - csrf_ddc_reg[27:25] < repBound__h251630 ; + csrf_ddc_reg[27:25] < repBound__h251632 ; assign csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4165 = - csrf_ddc_reg[85:83] < repBound__h251630 ; + csrf_ddc_reg[85:83] < repBound__h251632 ; assign csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4175 = { csrf_ddc_reg_read__078_BITS_85_TO_83_164_ULT_c_ETC___d4165, (csrf_ddc_reg_read__078_BITS_27_TO_25_161_ULT_c_ETC___d4162 == @@ -36061,33 +36061,33 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6389_BITS_13_TO_11_6392_UL_ETC___d16394 = - csrf_mtcc_reg[13:11] < repBound__h861482 ; + csrf_mtcc_reg[13:11] < repBound__h861480 ; assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192 = - csrf_mtcc_reg[149:86] & mask__h1010924 ; + csrf_mtcc_reg[149:86] & mask__h1010928 ; assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23199 = - newAddrDiff__h1010925 == mask__h1010924 ; + newAddrDiff__h1010929 == mask__h1010928 ; assign csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23227 = - newAddrDiff__h1011269 == mask__h1010924 ; + newAddrDiff__h1011273 == mask__h1010928 ; assign csrf_mtcc_reg_read__6389_BITS_85_TO_83_6395_UL_ETC___d16396 = - csrf_mtcc_reg[85:83] < repBound__h861482 ; + csrf_mtcc_reg[85:83] < repBound__h861480 ; assign csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 = csrf_prv_reg_read__0574_ULE_1___d22990 && CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 ; assign csrf_prv_reg_read__0574_ULE_1___d22990 = csrf_prv_reg <= 2'd1 ; assign csrf_rg_dpc_read__6534_BITS_13_TO_11_6537_ULT__ETC___d16539 = - csrf_rg_dpc[13:11] < repBound__h862312 ; + csrf_rg_dpc[13:11] < repBound__h862310 ; assign csrf_rg_dpc_read__6534_BITS_85_TO_83_6540_ULT__ETC___d16541 = - csrf_rg_dpc[85:83] < repBound__h862312 ; + csrf_rg_dpc[85:83] < repBound__h862310 ; assign csrf_stcc_reg_read__6237_BITS_13_TO_11_6240_UL_ETC___d16242 = - csrf_stcc_reg[13:11] < repBound__h860489 ; + csrf_stcc_reg[13:11] < repBound__h860487 ; assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23121 = - csrf_stcc_reg[149:86] & mask__h1010267 ; + csrf_stcc_reg[149:86] & mask__h1010271 ; assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23130 = - newAddrDiff__h1010268 == mask__h1010267 ; + newAddrDiff__h1010272 == mask__h1010271 ; assign csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23158 = - newAddrDiff__h1010612 == mask__h1010267 ; + newAddrDiff__h1010616 == mask__h1010271 ; assign csrf_stcc_reg_read__6237_BITS_85_TO_83_6243_UL_ETC___d16244 = - csrf_stcc_reg[85:83] < repBound__h860489 ; + csrf_stcc_reg[85:83] < repBound__h860487 ; assign data09494_BITS_31_TO_0__q22 = data__h709494[31:0] ; assign data10440_BITS_31_TO_0__q27 = data__h710440[31:0] ; assign data___1__h710032 = @@ -36126,11 +36126,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? data___1__h710978 : data__h710440 ; - assign data_addrBits__h1030233 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1031087 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1030232 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1031086 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h1005094 = + assign data_addrBits__h1030237 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1031091 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1030236 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1031090 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h1005098 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -36170,10 +36170,10 @@ module mkCore(CLK, assign din_inc___2_exp__h836623 = _theResult___fst_exp__h817373 + 11'd1 ; assign din_inc___2_exp__h836658 = _theResult___fst_exp__h826950 + 11'd1 ; assign din_inc___2_exp__h836684 = _theResult___fst_exp__h835783 + 11'd1 ; - assign enabled_ints___1__h929508 = pend_ints__h928981 & y__h929520 ; - assign enabled_ints__h929554 = - pend_ints__h928981 & - { r1__read_BITS_13_TO_0___h929530, csrf_mideleg_1_0_reg } ; + assign enabled_ints___1__h929512 = pend_ints__h928985 & y__h929524 ; + assign enabled_ints__h929558 = + pend_ints__h928985 & + { r1__read_BITS_13_TO_0___h929534, csrf_mideleg_1_0_reg } ; assign f1_exp19828_MINUS_127__q148 = f1_exp__h719828 - 8'd127 ; assign f1_exp__h719828 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -36206,27 +36206,27 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24528 = - (highOffsetBits__h1042939 == 50'd0 && + (highOffsetBits__h1042943 == 50'd0 && IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24525 || NOT_csrf_stcc_reg_read__6237_BITS_33_TO_28_625_ETC___d23117) && csrf_stcc_reg[152] ; assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24550 = - (highOffsetBits__h1043342 == 50'd0 && + (highOffsetBits__h1043346 == 50'd0 && IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24547 || NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23556) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16993 ; assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24608 = - (highOffsetBits__h1043759 == 50'd0 && + (highOffsetBits__h1043763 == 50'd0 && IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24605 || NOT_csrf_mtcc_reg_read__6389_BITS_33_TO_28_640_ETC___d23188) && csrf_mtcc_reg[152] ; assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24628 = - (highOffsetBits__h1044162 == 50'd0 && + (highOffsetBits__h1044166 == 50'd0 && IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24625 || NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23693) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17001 ; assign f_csr_reqs_first__4361_BITS_63_TO_14_4514_XOR__ETC___d24699 = - (highOffsetBits__h1044829 == 50'd0 && + (highOffsetBits__h1044833 == 50'd0 && IF_f_csr_reqs_first__4361_BIT_63_4515_THEN_NOT_ETC___d24696 || NOT_csrf_rg_dpc_read__6534_BITS_33_TO_28_6551__ETC___d23806) && csrf_rg_dpc[152] ; @@ -36236,11 +36236,11 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fallthrough_pc__h948605 = - { fetchStage$pipelines_0_first[591:527], address__h965680 } ; - assign fallthrough_pc__h973092 = - { fetchStage$pipelines_1_first[591:527], address__h990656 } ; - assign fcsr_csr__read__h855632 = { 56'd0, x__h859505 } ; + assign fallthrough_pc__h948609 = + { fetchStage$pipelines_0_first[591:527], address__h965684 } ; + assign fallthrough_pc__h973096 = + { fetchStage$pipelines_1_first[591:527], address__h990660 } ; + assign fcsr_csr__read__h855630 = { 56'd0, x__h859503 } ; assign fetchStage_RDY_pipelines_0_first__0541_AND_fet_ETC___d21553 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[268:266] == 3'd1 && @@ -36503,12 +36503,12 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0553_BIT_180_175_ETC___d21852 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259 } ; - assign fflags__h1027832 = + assign fflags__h1027836 = NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210 ? - y_avValue_snd_fst__h1027892 : + y_avValue_snd_fst__h1027896 : IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 ; - assign fflags_csr__read__h855607 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h855618 = { 61'd0, csrf_frm_reg } ; + assign fflags_csr__read__h855605 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h855616 = { 61'd0, csrf_frm_reg } ; assign guard__h580886 = { IF_sfdin88981_BIT_33_THEN_2_ELSE_0__q42[1], { sfdin__h588981[32:0], 23'd0 } != 56'd0 } ; @@ -36578,29 +36578,29 @@ module mkCore(CLK, assign guard__h827793 = { IF_theResult___snd35729_BIT_4_THEN_2_ELSE_0__q171[1], { _theResult___snd__h835729[3:0], 52'd0 } != 56'd0 } ; - assign highBitsfilter__h1019371 = + assign highBitsfilter__h1019375 = 50'h3FFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign highBitsfilter__h1019774 = + assign highBitsfilter__h1019778 = 50'h3FFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign highBitsfilter__h1020191 = + assign highBitsfilter__h1020195 = 50'h3FFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign highBitsfilter__h1020594 = + assign highBitsfilter__h1020598 = 50'h3FFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign highBitsfilter__h1021263 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign highOffsetBits__h1019372 = x__h1019399 & highBitsfilter__h1019371 ; - assign highOffsetBits__h1019775 = x__h1019399 & highBitsfilter__h1019774 ; - assign highOffsetBits__h1020192 = x__h1019399 & highBitsfilter__h1020191 ; - assign highOffsetBits__h1020595 = x__h1019399 & highBitsfilter__h1020594 ; - assign highOffsetBits__h1021264 = x__h1019399 & highBitsfilter__h1021263 ; - assign highOffsetBits__h1042939 = x__h1042966 & highBitsfilter__h1019371 ; - assign highOffsetBits__h1043342 = x__h1042966 & highBitsfilter__h1019774 ; - assign highOffsetBits__h1043759 = x__h1042966 & highBitsfilter__h1020191 ; - assign highOffsetBits__h1044162 = x__h1042966 & highBitsfilter__h1020594 ; - assign highOffsetBits__h1044829 = x__h1042966 & highBitsfilter__h1021263 ; - assign highOffsetBits__h245534 = x__h245561 & mask__h242755 ; - assign idx__h978721 = + assign highBitsfilter__h1021267 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign highOffsetBits__h1019376 = x__h1019403 & highBitsfilter__h1019375 ; + assign highOffsetBits__h1019779 = x__h1019403 & highBitsfilter__h1019778 ; + assign highOffsetBits__h1020196 = x__h1019403 & highBitsfilter__h1020195 ; + assign highOffsetBits__h1020599 = x__h1019403 & highBitsfilter__h1020598 ; + assign highOffsetBits__h1021268 = x__h1019403 & highBitsfilter__h1021267 ; + assign highOffsetBits__h1042943 = x__h1042970 & highBitsfilter__h1019375 ; + assign highOffsetBits__h1043346 = x__h1042970 & highBitsfilter__h1019778 ; + assign highOffsetBits__h1043763 = x__h1042970 & highBitsfilter__h1020195 ; + assign highOffsetBits__h1044166 = x__h1042970 & highBitsfilter__h1020598 ; + assign highOffsetBits__h1044833 = x__h1042970 & highBitsfilter__h1021267 ; + assign highOffsetBits__h245536 = x__h245563 & mask__h242757 ; + assign idx__h978725 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d21951 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -36608,38 +36608,38 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0544_BITS_268_TO_ETC___d21974) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1496__ETC___d21498 ; - assign impliedTopBits__h1005772 = x__h1005856 + len_correction__h1005771 ; + assign impliedTopBits__h1005776 = x__h1005860 + len_correction__h1005775 ; assign impliedTopBits__h128460 = x__h128544 + len_correction__h128459 ; assign impliedTopBits__h141604 = x__h141688 + len_correction__h141603 ; - assign impliedTopBits__h185385 = x__h185469 + len_correction__h185384 ; - assign impliedTopBits__h204448 = x__h204532 + len_correction__h204447 ; - assign impliedTopBits__h219419 = x__h219503 + len_correction__h219418 ; - assign impliedTopBits__h872935 = x__h873020 + len_correction__h872934 ; - assign impliedTopBits__h873483 = x__h873568 + len_correction__h873482 ; - assign impliedTopBits__h913975 = x__h914060 + len_correction__h913974 ; - assign impliedTopBits__h914523 = x__h914608 + len_correction__h914522 ; - assign in__h1008423 = pc_address__h1005469 & y__h1008440 ; - assign in__h242694 = coreFix_memExe_regToExeQ$first[383:318] & y__h242711 ; - assign in__h243851 = coreFix_memExe_regToExeQ$first[220:155] & y__h243868 ; - assign in__h257472 = coreFix_memExe_dTlb$procResp[452:387] & y__h257489 ; - assign in__h860567 = csrf_stcc_reg[151:86] & y__h860584 ; - assign in__h860872 = + assign impliedTopBits__h185386 = x__h185470 + len_correction__h185385 ; + assign impliedTopBits__h204449 = x__h204533 + len_correction__h204448 ; + assign impliedTopBits__h219420 = x__h219504 + len_correction__h219419 ; + assign impliedTopBits__h872933 = x__h873018 + len_correction__h872932 ; + assign impliedTopBits__h873481 = x__h873566 + len_correction__h873480 ; + assign impliedTopBits__h913978 = x__h914063 + len_correction__h913977 ; + assign impliedTopBits__h914526 = x__h914611 + len_correction__h914525 ; + assign in__h1008427 = pc_address__h1005473 & y__h1008444 ; + assign in__h242696 = coreFix_memExe_regToExeQ$first[383:318] & y__h242713 ; + assign in__h243853 = coreFix_memExe_regToExeQ$first[220:155] & y__h243870 ; + assign in__h257474 = coreFix_memExe_dTlb$procResp[452:387] & y__h257491 ; + assign in__h860565 = csrf_stcc_reg[151:86] & y__h860582 ; + assign in__h860870 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295 & - y__h860889 ; - assign in__h861560 = csrf_mtcc_reg[151:86] & y__h861577 ; - assign in__h861864 = + y__h860887 ; + assign in__h861558 = csrf_mtcc_reg[151:86] & y__h861575 ; + assign in__h861862 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447 & - y__h861881 ; - assign in__h862390 = csrf_rg_dpc[151:86] & y__h862407 ; - assign inc__h965679 = + y__h861879 ; + assign in__h862388 = csrf_rg_dpc[151:86] & y__h862405 ; + assign inc__h965683 = (fetchStage$pipelines_0_first[98:97] == 2'b11) ? 12'd4 : 12'd2 ; - assign inc__h990655 = + assign inc__h990659 = (fetchStage$pipelines_1_first[98:97] == 2'b11) ? 12'd4 : 12'd2 ; - assign k__h954118 = + assign k__h954122 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1496__ETC___d21498 ; - assign len_correction__h1005771 = + assign len_correction__h1005775 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? 2'b01 : 2'b0 ; @@ -36649,54 +36649,54 @@ module mkCore(CLK, 2'b0 ; assign len_correction__h141603 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h185384 = - INV_x85172_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; - assign len_correction__h204447 = - INV_x01336_BITS_108_TO_90__q37[0] ? 2'b01 : 2'b0 ; - assign len_correction__h219418 = + assign len_correction__h185385 = + INV_x85173_BITS_108_TO_90__q35[0] ? 2'b01 : 2'b0 ; + assign len_correction__h204448 = + INV_x01337_BITS_108_TO_90__q37[0] ? 2'b01 : 2'b0 ; + assign len_correction__h219419 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h872934 = + assign len_correction__h872932 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h873482 = + assign len_correction__h873480 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h913974 = + assign len_correction__h913977 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h914522 = + assign len_correction__h914525 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign mask__h1010267 = 64'hFFFFFFFFFFFFFFFF << x__h1010328 ; - assign mask__h1010924 = 64'hFFFFFFFFFFFFFFFF << x__h1010985 ; - assign mask__h242755 = + assign mask__h1010271 = 64'hFFFFFFFFFFFFFFFF << x__h1010332 ; + assign mask__h1010928 = 64'hFFFFFFFFFFFFFFFF << x__h1010989 ; + assign mask__h242757 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h242864 = + assign mask__h242866 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h243912 = + assign mask__h243914 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h244021 = + assign mask__h244023 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h257533 = + assign mask__h257535 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h257642 = + assign mask__h257644 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mcause_csr__read__h857299 = - { r1__read__h861914, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h857033 = - { r1__read__h861610, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h856636 = - { r1__read__h861287, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h856734 = - { r1__read__h861310, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h856861 = { r1__read__h861334, 1'b0 } ; - assign mip_csr__read__h857538 = { r1__read__h861921, 1'b0 } ; + assign mcause_csr__read__h857297 = + { r1__read__h861912, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h857031 = + { r1__read__h861608, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h856634 = + { r1__read__h861285, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h856732 = + { r1__read__h861308, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h856859 = { r1__read__h861332, 1'b0 } ; + assign mip_csr__read__h857536 = { r1__read__h861919, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20967 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -36738,56 +36738,56 @@ module mkCore(CLK, fetchStage$pipelines_0_first[273:269] != 5'd24 && fetchStage$pipelines_0_first[273:269] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h856475 = { r1__read__h861162, csrf_ie_vec_0 } ; - assign n__read__h1025238 = + assign mstatus_csr__read__h856473 = { r1__read__h861160, csrf_ie_vec_0 } ; + assign n__read__h1025242 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1025314 : + upd__h1025318 : csrf_minstret_ehr_data_rl ; assign n__read__h7908 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7977 : csrf_mcycle_ehr_data_rl ; - assign newAddrBits__h1019554 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1019495[13:0] } ; - assign newAddrBits__h1019957 = + assign newAddrBits__h1019558 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1019499[13:0] } ; + assign newAddrBits__h1019961 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275 } + - { 2'd0, x__h1019898[13:0] } ; - assign newAddrBits__h1020374 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1020315[13:0] } ; - assign newAddrBits__h1020777 = + { 2'd0, x__h1019902[13:0] } ; + assign newAddrBits__h1020378 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1020319[13:0] } ; + assign newAddrBits__h1020781 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427 } + - { 2'd0, x__h1020718[13:0] } ; - assign newAddrBits__h1021446 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1021387[13:0] } ; - assign newAddrBits__h1043121 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1043062[13:0] } ; - assign newAddrBits__h1043524 = + { 2'd0, x__h1020722[13:0] } ; + assign newAddrBits__h1021450 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1021391[13:0] } ; + assign newAddrBits__h1043125 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1043066[13:0] } ; + assign newAddrBits__h1043528 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275 } + - { 2'd0, x__h1043465[13:0] } ; - assign newAddrBits__h1043941 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1043882[13:0] } ; - assign newAddrBits__h1044344 = + { 2'd0, x__h1043469[13:0] } ; + assign newAddrBits__h1043945 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1043886[13:0] } ; + assign newAddrBits__h1044348 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427 } + - { 2'd0, x__h1044285[13:0] } ; - assign newAddrBits__h1045011 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1044952[13:0] } ; - assign newAddrDiff__h1010268 = + { 2'd0, x__h1044289[13:0] } ; + assign newAddrBits__h1045015 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1044956[13:0] } ; + assign newAddrDiff__h1010272 = csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23121 - - (address__h1010195 & mask__h1010267) ; - assign newAddrDiff__h1010612 = + (address__h1010199 & mask__h1010271) ; + assign newAddrDiff__h1010616 = csrf_stcc_reg_read__6237_BITS_149_TO_86_3118_A_ETC___d23121 - - (base__h1010156 & mask__h1010267) ; - assign newAddrDiff__h1010925 = + (base__h1010160 & mask__h1010271) ; + assign newAddrDiff__h1010929 = csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192 - - (address__h1010245 & mask__h1010924) ; - assign newAddrDiff__h1011269 = + (address__h1010249 & mask__h1010928) ; + assign newAddrDiff__h1011273 = csrf_mtcc_reg_read__6389_BITS_149_TO_86_3189_A_ETC___d23192 - - (base__h1010210 & mask__h1010924) ; - assign new_pc__h880397 = + (base__h1010214 & mask__h1010928) ; + assign new_pc__h880396 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -36799,7 +36799,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18226[2], IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18226[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h920770 = + assign new_pc__h920774 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -36811,47 +36811,47 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20400[2], IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20400[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h520035 = + assign next_deqP___1__h520036 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h530812 = + assign next_deqP___1__h530813 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h538090 = + assign next_deqP___1__h538091 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h548725 = + assign next_deqP___1__h548726 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h562373 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h566152 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1023267 = + assign next_deqP___1__h562374 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h566153 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1023271 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1023320 } ; - assign offset__h1008342 = { 2'd0, pc_addrBits__h1005470 } - base__h1008341 ; - assign offset__h242590 = + { rob$deqPort_0_deq_data[630:566], address__h1023324 } ; + assign offset__h1008346 = { 2'd0, pc_addrBits__h1005474 } - base__h1008345 ; + assign offset__h242592 = { 2'd0, coreFix_memExe_regToExeQ$first[317:304] } - - base__h242589 ; - assign offset__h243747 = + base__h242591 ; + assign offset__h243749 = { 2'd0, coreFix_memExe_regToExeQ$first[154:141] } - - base__h243746 ; - assign offset__h245515 = + base__h243748 ; + assign offset__h245517 = { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17[31]}}, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q17 } ; - assign offset__h257368 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h257367 ; - assign offset__h860634 = + assign offset__h257370 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h257369 ; + assign offset__h860632 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271 } - - base__h860633 ; - assign offset__h861627 = + base__h860631 ; + assign offset__h861625 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423 } - - base__h861626 ; - assign offset__h903650 = { 2'd0, csrf_stcc_reg[85:72] } - base__h903649 ; - assign offset__h903934 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h903933 ; - assign offset__h904279 = { 2'd0, csrf_rg_dpc[85:72] } - base__h904278 ; + base__h861624 ; + assign offset__h903653 = { 2'd0, csrf_stcc_reg[85:72] } - base__h903652 ; + assign offset__h903937 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h903936 ; + assign offset__h904282 = { 2'd0, csrf_rg_dpc[85:72] } - base__h904281 ; assign out___1_sfd__h719892 = { f1_sfd__h719829, 29'd0 } ; assign out___1_sfd__h758886 = { f2_sfd__h758823, 29'd0 } ; assign out___1_sfd__h798190 = { f3_sfd__h798127, 29'd0 } ; @@ -37059,27 +37059,27 @@ module mkCore(CLK, _theResult___snd__h835729[5] ? _theResult___sfd__h836464 : _theResult___snd__h835729[56:5] ; - assign pc__h973083 = fetchStage$pipelines_1_first[591:463] ; - assign pc_addrBits__h1005470 = + assign pc__h973087 = fetchStage$pipelines_1_first[591:463] ; + assign pc_addrBits__h1005474 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? - x__h1005641[13:0] : + x__h1005645[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h1005469 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h928981 = + assign pc_address__h1005473 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h928985 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6374_ETC___d20585, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h245525 = + assign pointer__h245527 = coreFix_memExe_regToExeQ$first[383:318] + - { 2'd0, offset__h245515 } ; - assign prv__h1028925 = csrf_prv_reg ; - assign prv__h1028969 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + { 2'd0, offset__h245517 } ; + assign prv__h1028929 = csrf_prv_reg ; + assign prv__h1028973 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h711053 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_0___h929530 = + assign r1__read_BITS_13_TO_0___h929534 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -37087,119 +37087,119 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h935205 = csrf_fs_reg ; - assign r1__read_BIT_20___h935711 = csrf_tw_reg ; - assign r1__read__h859520 = { r1__read__h859522, csrf_ie_vec_1 } ; - assign r1__read__h859522 = { r1__read__h859524, 2'b0 } ; - assign r1__read__h859524 = { r1__read__h859526, csrf_prev_ie_vec_0 } ; - assign r1__read__h859526 = { r1__read__h859528, csrf_prev_ie_vec_1 } ; - assign r1__read__h859528 = { r1__read__h859530, 2'b0 } ; - assign r1__read__h859530 = { r1__read__h859532, csrf_spp_reg } ; - assign r1__read__h859532 = { r1__read__h859534, 4'b0 } ; - assign r1__read__h859534 = { r1__read__h859536, csrf_fs_reg } ; - assign r1__read__h859536 = { r1__read__h859538, 2'd0 } ; - assign r1__read__h859538 = { r1__read__h859540, 1'b0 } ; - assign r1__read__h859540 = { r1__read__h859542, csrf_sum_reg } ; - assign r1__read__h859542 = { r1__read__h859544, csrf_mxr_reg } ; - assign r1__read__h859544 = { r1__read__h859546, 12'b0 } ; - assign r1__read__h859546 = { r1__read__h859548, 2'b10 } ; - assign r1__read__h859548 = { r__h859552, 29'b0 } ; - assign r1__read__h859924 = - { r1__read__h859926, csrf_software_int_en_vec_1 } ; - assign r1__read__h859926 = { r1__read__h859928, 2'b0 } ; - assign r1__read__h859928 = { r1__read__h859930, 1'b0 } ; - assign r1__read__h859930 = { r1__read__h859932, csrf_timer_int_en_vec_1 } ; - assign r1__read__h859932 = { r1__read__h859934, 2'b0 } ; - assign r1__read__h859934 = { r1__read__h859936, 1'b0 } ; - assign r1__read__h859936 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h860617 = { r1__read__h860619, csrf_scounteren_tm_reg } ; - assign r1__read__h860619 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h860922 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h860929 = - { r1__read__h860931, csrf_software_int_pend_vec_1 } ; - assign r1__read__h860931 = { r1__read__h860933, 2'b0 } ; - assign r1__read__h860933 = { r1__read__h860935, 1'b0 } ; - assign r1__read__h860935 = - { r1__read__h860937, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h860937 = { r1__read__h860939, 2'b0 } ; - assign r1__read__h860939 = { r1__read__h860941, 1'b0 } ; - assign r1__read__h860941 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h861139 = { vm_mode_reg__read__h861145, 16'd0 } ; - assign r1__read__h861162 = { r1__read__h861164, csrf_ie_vec_1 } ; - assign r1__read__h861164 = { r1__read__h861166, 1'b0 } ; - assign r1__read__h861166 = { r1__read__h861168, csrf_ie_vec_3 } ; - assign r1__read__h861168 = { r1__read__h861170, csrf_prev_ie_vec_0 } ; - assign r1__read__h861170 = { r1__read__h861172, csrf_prev_ie_vec_1 } ; - assign r1__read__h861172 = { r1__read__h861174, 1'b0 } ; - assign r1__read__h861174 = { r1__read__h861176, csrf_prev_ie_vec_3 } ; - assign r1__read__h861176 = { r1__read__h861178, csrf_spp_reg } ; - assign r1__read__h861178 = { r1__read__h861180, 2'b0 } ; - assign r1__read__h861180 = { r1__read__h861182, csrf_mpp_reg } ; - assign r1__read__h861182 = { r1__read__h861184, csrf_fs_reg } ; - assign r1__read__h861184 = { r1__read__h861186, 2'd0 } ; - assign r1__read__h861186 = { r1__read__h861188, csrf_mprv_reg } ; - assign r1__read__h861188 = { r1__read__h861190, csrf_sum_reg } ; - assign r1__read__h861190 = { r1__read__h861192, csrf_mxr_reg } ; - assign r1__read__h861192 = { r1__read__h861194, csrf_tvm_reg } ; - assign r1__read__h861194 = { r1__read__h861196, csrf_tw_reg } ; - assign r1__read__h861196 = { r1__read__h861198, csrf_tsr_reg } ; - assign r1__read__h861198 = { r1__read__h861200, 9'b0 } ; + assign r1__read_BITS_13_TO_12___h935209 = csrf_fs_reg ; + assign r1__read_BIT_20___h935715 = csrf_tw_reg ; + assign r1__read__h859518 = { r1__read__h859520, csrf_ie_vec_1 } ; + assign r1__read__h859520 = { r1__read__h859522, 2'b0 } ; + assign r1__read__h859522 = { r1__read__h859524, csrf_prev_ie_vec_0 } ; + assign r1__read__h859524 = { r1__read__h859526, csrf_prev_ie_vec_1 } ; + assign r1__read__h859526 = { r1__read__h859528, 2'b0 } ; + assign r1__read__h859528 = { r1__read__h859530, csrf_spp_reg } ; + assign r1__read__h859530 = { r1__read__h859532, 4'b0 } ; + assign r1__read__h859532 = { r1__read__h859534, csrf_fs_reg } ; + assign r1__read__h859534 = { r1__read__h859536, 2'd0 } ; + assign r1__read__h859536 = { r1__read__h859538, 1'b0 } ; + assign r1__read__h859538 = { r1__read__h859540, csrf_sum_reg } ; + assign r1__read__h859540 = { r1__read__h859542, csrf_mxr_reg } ; + assign r1__read__h859542 = { r1__read__h859544, 12'b0 } ; + assign r1__read__h859544 = { r1__read__h859546, 2'b10 } ; + assign r1__read__h859546 = { r__h859550, 29'b0 } ; + assign r1__read__h859922 = + { r1__read__h859924, csrf_software_int_en_vec_1 } ; + assign r1__read__h859924 = { r1__read__h859926, 2'b0 } ; + assign r1__read__h859926 = { r1__read__h859928, 1'b0 } ; + assign r1__read__h859928 = { r1__read__h859930, csrf_timer_int_en_vec_1 } ; + assign r1__read__h859930 = { r1__read__h859932, 2'b0 } ; + assign r1__read__h859932 = { r1__read__h859934, 1'b0 } ; + assign r1__read__h859934 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h860615 = { r1__read__h860617, csrf_scounteren_tm_reg } ; + assign r1__read__h860617 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h860920 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h860927 = + { r1__read__h860929, csrf_software_int_pend_vec_1 } ; + assign r1__read__h860929 = { r1__read__h860931, 2'b0 } ; + assign r1__read__h860931 = { r1__read__h860933, 1'b0 } ; + assign r1__read__h860933 = + { r1__read__h860935, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h860935 = { r1__read__h860937, 2'b0 } ; + assign r1__read__h860937 = { r1__read__h860939, 1'b0 } ; + assign r1__read__h860939 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h861137 = { vm_mode_reg__read__h861143, 16'd0 } ; + assign r1__read__h861160 = { r1__read__h861162, csrf_ie_vec_1 } ; + assign r1__read__h861162 = { r1__read__h861164, 1'b0 } ; + assign r1__read__h861164 = { r1__read__h861166, csrf_ie_vec_3 } ; + assign r1__read__h861166 = { r1__read__h861168, csrf_prev_ie_vec_0 } ; + assign r1__read__h861168 = { r1__read__h861170, csrf_prev_ie_vec_1 } ; + assign r1__read__h861170 = { r1__read__h861172, 1'b0 } ; + assign r1__read__h861172 = { r1__read__h861174, csrf_prev_ie_vec_3 } ; + assign r1__read__h861174 = { r1__read__h861176, csrf_spp_reg } ; + assign r1__read__h861176 = { r1__read__h861178, 2'b0 } ; + assign r1__read__h861178 = { r1__read__h861180, csrf_mpp_reg } ; + assign r1__read__h861180 = { r1__read__h861182, csrf_fs_reg } ; + assign r1__read__h861182 = { r1__read__h861184, 2'd0 } ; + assign r1__read__h861184 = { r1__read__h861186, csrf_mprv_reg } ; + assign r1__read__h861186 = { r1__read__h861188, csrf_sum_reg } ; + assign r1__read__h861188 = { r1__read__h861190, csrf_mxr_reg } ; + assign r1__read__h861190 = { r1__read__h861192, csrf_tvm_reg } ; + assign r1__read__h861192 = { r1__read__h861194, csrf_tw_reg } ; + assign r1__read__h861194 = { r1__read__h861196, csrf_tsr_reg } ; + assign r1__read__h861196 = { r1__read__h861198, 9'b0 } ; + assign r1__read__h861198 = { r1__read__h861200, 2'b10 } ; assign r1__read__h861200 = { r1__read__h861202, 2'b10 } ; - assign r1__read__h861202 = { r1__read__h861204, 2'b10 } ; - assign r1__read__h861204 = { r__h859552, 27'b0 } ; - assign r1__read__h861287 = { r1__read__h861289, 1'b0 } ; - assign r1__read__h861289 = { r1__read__h861291, csrf_medeleg_13_11_reg } ; - assign r1__read__h861291 = { r1__read__h861293, 1'b0 } ; - assign r1__read__h861293 = { r1__read__h861295, csrf_medeleg_15_reg } ; - assign r1__read__h861295 = { r1__read__h861297, 10'b0 } ; - assign r1__read__h861297 = { 35'b0, csrf_medeleg_28_26_reg } ; - assign r1__read__h861310 = { r1__read__h861312, 1'b0 } ; - assign r1__read__h861312 = { r1__read__h861314, csrf_mideleg_5_3_reg } ; - assign r1__read__h861314 = { r1__read__h861316, 1'b0 } ; - assign r1__read__h861316 = { r1__read__h861318, csrf_mideleg_9_7_reg } ; - assign r1__read__h861318 = { r1__read__h861320, 1'b0 } ; - assign r1__read__h861320 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h861334 = - { r1__read__h861336, csrf_software_int_en_vec_1 } ; - assign r1__read__h861336 = { r1__read__h861338, 1'b0 } ; - assign r1__read__h861338 = - { r1__read__h861340, csrf_software_int_en_vec_3 } ; - assign r1__read__h861340 = { r1__read__h861342, 1'b0 } ; - assign r1__read__h861342 = { r1__read__h861344, csrf_timer_int_en_vec_1 } ; - assign r1__read__h861344 = { r1__read__h861346, 1'b0 } ; - assign r1__read__h861346 = { r1__read__h861348, csrf_timer_int_en_vec_3 } ; - assign r1__read__h861348 = { r1__read__h861350, 1'b0 } ; - assign r1__read__h861350 = - { r1__read__h861352, csrf_external_int_en_vec_1 } ; - assign r1__read__h861352 = { r1__read__h861354, 1'b0 } ; - assign r1__read__h861354 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h861610 = { r1__read__h861612, csrf_mcounteren_tm_reg } ; - assign r1__read__h861612 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h861914 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h861921 = - { r1__read__h861923, csrf_software_int_pend_vec_1 } ; - assign r1__read__h861923 = { r1__read__h861925, 1'b0 } ; - assign r1__read__h861925 = - { r1__read__h861927, csrf_software_int_pend_vec_3 } ; - assign r1__read__h861927 = { r1__read__h861929, 1'b0 } ; - assign r1__read__h861929 = - { r1__read__h861931, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h861931 = { r1__read__h861933, 1'b0 } ; - assign r1__read__h861933 = - { r1__read__h861935, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h861935 = { r1__read__h861937, 1'b0 } ; - assign r1__read__h861937 = - { r1__read__h861939, csrf_external_int_pend_vec_1 } ; - assign r1__read__h861939 = { r1__read__h861941, 1'b0 } ; - assign r1__read__h861941 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h862250 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign r1__read__h861202 = { r__h859550, 27'b0 } ; + assign r1__read__h861285 = { r1__read__h861287, 1'b0 } ; + assign r1__read__h861287 = { r1__read__h861289, csrf_medeleg_13_11_reg } ; + assign r1__read__h861289 = { r1__read__h861291, 1'b0 } ; + assign r1__read__h861291 = { r1__read__h861293, csrf_medeleg_15_reg } ; + assign r1__read__h861293 = { r1__read__h861295, 10'b0 } ; + assign r1__read__h861295 = { 35'b0, csrf_medeleg_28_26_reg } ; + assign r1__read__h861308 = { r1__read__h861310, 1'b0 } ; + assign r1__read__h861310 = { r1__read__h861312, csrf_mideleg_5_3_reg } ; + assign r1__read__h861312 = { r1__read__h861314, 1'b0 } ; + assign r1__read__h861314 = { r1__read__h861316, csrf_mideleg_9_7_reg } ; + assign r1__read__h861316 = { r1__read__h861318, 1'b0 } ; + assign r1__read__h861318 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h861332 = + { r1__read__h861334, csrf_software_int_en_vec_1 } ; + assign r1__read__h861334 = { r1__read__h861336, 1'b0 } ; + assign r1__read__h861336 = + { r1__read__h861338, csrf_software_int_en_vec_3 } ; + assign r1__read__h861338 = { r1__read__h861340, 1'b0 } ; + assign r1__read__h861340 = { r1__read__h861342, csrf_timer_int_en_vec_1 } ; + assign r1__read__h861342 = { r1__read__h861344, 1'b0 } ; + assign r1__read__h861344 = { r1__read__h861346, csrf_timer_int_en_vec_3 } ; + assign r1__read__h861346 = { r1__read__h861348, 1'b0 } ; + assign r1__read__h861348 = + { r1__read__h861350, csrf_external_int_en_vec_1 } ; + assign r1__read__h861350 = { r1__read__h861352, 1'b0 } ; + assign r1__read__h861352 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h861608 = { r1__read__h861610, csrf_mcounteren_tm_reg } ; + assign r1__read__h861610 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h861912 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h861919 = + { r1__read__h861921, csrf_software_int_pend_vec_1 } ; + assign r1__read__h861921 = { r1__read__h861923, 1'b0 } ; + assign r1__read__h861923 = + { r1__read__h861925, csrf_software_int_pend_vec_3 } ; + assign r1__read__h861925 = { r1__read__h861927, 1'b0 } ; + assign r1__read__h861927 = + { r1__read__h861929, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h861929 = { r1__read__h861931, 1'b0 } ; + assign r1__read__h861931 = + { r1__read__h861933, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h861933 = { r1__read__h861935, 1'b0 } ; + assign r1__read__h861935 = + { r1__read__h861937, csrf_external_int_pend_vec_1 } ; + assign r1__read__h861937 = { r1__read__h861939, 1'b0 } ; + assign r1__read__h861939 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h862248 = { 4'd0, csrf_rg_tdata1_dmode } ; assign rVal1__h719444 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; assign rVal2__h719445 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; assign r___1__h711080 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h859552 = csrf_fs_reg == 2'b11 ; - assign r__h861996 = csrf_software_int_pend_vec_3 ; + assign r__h859550 = csrf_fs_reg == 2'b11 ; + assign r__h861994 = csrf_software_int_pend_vec_3 ; assign regRenamingTable_RDY_rename_0_getRename__1316__ETC___d21327 = regRenamingTable$RDY_rename_0_getRename && rob$RDY_enqPort_0_enq && @@ -37482,37 +37482,37 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20942[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h978582 = + assign renaming_spec_bits__h978586 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h973226 : + y_avValue_snd_fst__h973230 : specTagManager$currentSpecBits ; - assign repBoundBits__h245540 = + assign repBoundBits__h245542 = { coreFix_memExe_regToExeQ$first[231:229], 11'd0 } ; - assign repBound__h1008366 = x__h1005859[13:11] - 3'b001 ; - assign repBound__h240206 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h241891 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h251105 = + assign repBound__h1008370 = x__h1005863[13:11] - 3'b001 ; + assign repBound__h240208 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h241893 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h251107 = coreFix_memExe_regToExeQ$first[245:243] - 3'b001 ; - assign repBound__h251630 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h860489 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h860811 = + assign repBound__h251632 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h860487 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h860809 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[13:11] - 3'b001 ; - assign repBound__h861482 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign repBound__h861803 = + assign repBound__h861480 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign repBound__h861801 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[13:11] - 3'b001 ; - assign repBound__h862312 = csrf_rg_dpc[13:11] - 3'b001 ; - assign repBound__h863990 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h866952 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h866970 = thin_bounds_baseBits__h866835[13:11] - 3'b001 ; - assign repBound__h873084 = x__h873023[13:11] - 3'b001 ; - assign repBound__h873632 = x__h873571[13:11] - 3'b001 ; - assign repBound__h905960 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h908287 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h908305 = thin_bounds_baseBits__h908190[13:11] - 3'b001 ; - assign repBound__h914124 = x__h914063[13:11] - 3'b001 ; - assign repBound__h914672 = x__h914611[13:11] - 3'b001 ; + assign repBound__h862310 = csrf_rg_dpc[13:11] - 3'b001 ; + assign repBound__h863988 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h866950 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h866968 = thin_bounds_baseBits__h866833[13:11] - 3'b001 ; + assign repBound__h873082 = x__h873021[13:11] - 3'b001 ; + assign repBound__h873630 = x__h873569[13:11] - 3'b001 ; + assign repBound__h905963 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h908290 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h908308 = thin_bounds_baseBits__h908193[13:11] - 3'b001 ; + assign repBound__h914127 = x__h914066[13:11] - 3'b001 ; + assign repBound__h914675 = x__h914614[13:11] - 3'b001 ; assign res_addrBits__h127849 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? x__h128329[13:0] : @@ -37521,44 +37521,44 @@ module mkCore(CLK, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? x__h141473[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h180672 = - INV_x85172_BITS_108_TO_90__q35[0] ? - x__h185254[13:0] : - x__h185172[13:0] ; - assign res_addrBits__h199749 = - INV_x01336_BITS_108_TO_90__q37[0] ? - x__h204317[13:0] : - x__h201336[13:0] ; - assign res_addrBits__h218913 = + assign res_addrBits__h180673 = + INV_x85173_BITS_108_TO_90__q35[0] ? + x__h185255[13:0] : + x__h185173[13:0] ; + assign res_addrBits__h199750 = + INV_x01337_BITS_108_TO_90__q37[0] ? + x__h204318[13:0] : + x__h201337[13:0] ; + assign res_addrBits__h218914 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h219288[13:0] : + x__h219289[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h238212 = { 2'b0, addr__h238205[63:52] } ; - assign res_addrBits__h571768 = + assign res_addrBits__h238214 = { 2'b0, addr__h238207[63:52] } ; + assign res_addrBits__h571769 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; assign res_addrBits__h572621 = { 2'b0, data__h572102[63:52] } ; assign res_addrBits__h618378 = { 2'b0, data__h617862[63:52] } ; assign res_addrBits__h664125 = { 2'b0, data__h663609[63:52] } ; assign res_addrBits__h710011 = { 2'b0, data__h709525[63:52] } ; assign res_addrBits__h710957 = { 2'b0, data__h710471[63:52] } ; - assign res_addrBits__h855057 = { 2'b0, addr__h850288[63:52] } ; - assign res_addrBits__h899821 = { 2'b0, addr__h895060[63:52] } ; + assign res_addrBits__h855056 = { 2'b0, addr__h850287[63:52] } ; + assign res_addrBits__h899823 = { 2'b0, addr__h895062[63:52] } ; assign res_address__h127848 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; assign res_address__h140988 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h180671 = { 2'd0, x__h185172[63:0] } ; - assign res_address__h199748 = { 2'd0, x__h201336[63:0] } ; - assign res_address__h218912 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h238211 = { 2'd0, addr__h238205 } ; - assign res_address__h571767 = + assign res_address__h180672 = { 2'd0, x__h185173[63:0] } ; + assign res_address__h199749 = { 2'd0, x__h201337[63:0] } ; + assign res_address__h218913 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h238213 = { 2'd0, addr__h238207 } ; + assign res_address__h571768 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; assign res_address__h572620 = { 2'd0, data__h572102 } ; assign res_address__h618377 = { 2'd0, data__h617862 } ; assign res_address__h664124 = { 2'd0, data__h663609 } ; assign res_address__h710010 = { 2'd0, data__h709525 } ; assign res_address__h710956 = { 2'd0, data__h710471 } ; - assign res_address__h855056 = { 2'd0, addr__h850288 } ; - assign res_address__h899820 = { 2'd0, addr__h895060 } ; + assign res_address__h855055 = { 2'd0, addr__h850287 } ; + assign res_address__h899822 = { 2'd0, addr__h895062 } ; assign res_data__h572660 = { 32'hFFFFFFFF, x__h572675 } ; assign res_data__h572665 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37805,18 +37805,18 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12268 } ; - assign resp_addr__h513540 = + assign resp_addr__h513541 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[169:158] } ; - assign result__h243490 = + assign result__h243492 = { 1'd0, ~coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[64], coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[63:0] } ; - assign result__h244647 = + assign result__h244649 = { 1'd0, ~coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[64], coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[63:0] } ; - assign result__h258268 = + assign result__h258270 = { 1'd0, ~coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[64], coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[63:0] } ; @@ -37844,99 +37844,99 @@ module mkCore(CLK, { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13625[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13625[0] | guard__h819322 } ; - assign result__h924561 = w__h924556 & y__h924590 ; - assign result__h924612 = ~x__h924611 ; - assign result_d_addrBits__h1019566 = + assign result__h924565 = w__h924560 & y__h924594 ; + assign result__h924616 = ~x__h924615 ; + assign result_d_addrBits__h1019570 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1019554[12:0] } : - newAddrBits__h1019554[13:0] ; - assign result_d_addrBits__h1019969 = + { 1'b0, newAddrBits__h1019558[12:0] } : + newAddrBits__h1019558[13:0] ; + assign result_d_addrBits__h1019973 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 == 6'd52) ? - { 1'b0, newAddrBits__h1019957[12:0] } : - newAddrBits__h1019957[13:0] ; - assign result_d_addrBits__h1020386 = + { 1'b0, newAddrBits__h1019961[12:0] } : + newAddrBits__h1019961[13:0] ; + assign result_d_addrBits__h1020390 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1020374[12:0] } : - newAddrBits__h1020374[13:0] ; - assign result_d_addrBits__h1020789 = + { 1'b0, newAddrBits__h1020378[12:0] } : + newAddrBits__h1020378[13:0] ; + assign result_d_addrBits__h1020793 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 == 6'd52) ? - { 1'b0, newAddrBits__h1020777[12:0] } : - newAddrBits__h1020777[13:0] ; - assign result_d_addrBits__h1021458 = + { 1'b0, newAddrBits__h1020781[12:0] } : + newAddrBits__h1020781[13:0] ; + assign result_d_addrBits__h1021462 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1021446[12:0] } : - newAddrBits__h1021446[13:0] ; - assign result_d_addrBits__h1043133 = + { 1'b0, newAddrBits__h1021450[12:0] } : + newAddrBits__h1021450[13:0] ; + assign result_d_addrBits__h1043137 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1043121[12:0] } : - newAddrBits__h1043121[13:0] ; - assign result_d_addrBits__h1043536 = + { 1'b0, newAddrBits__h1043125[12:0] } : + newAddrBits__h1043125[13:0] ; + assign result_d_addrBits__h1043540 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 == 6'd52) ? - { 1'b0, newAddrBits__h1043524[12:0] } : - newAddrBits__h1043524[13:0] ; - assign result_d_addrBits__h1043953 = + { 1'b0, newAddrBits__h1043528[12:0] } : + newAddrBits__h1043528[13:0] ; + assign result_d_addrBits__h1043957 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1043941[12:0] } : - newAddrBits__h1043941[13:0] ; - assign result_d_addrBits__h1044356 = + { 1'b0, newAddrBits__h1043945[12:0] } : + newAddrBits__h1043945[13:0] ; + assign result_d_addrBits__h1044360 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 == 6'd52) ? - { 1'b0, newAddrBits__h1044344[12:0] } : - newAddrBits__h1044344[13:0] ; - assign result_d_addrBits__h1045023 = + { 1'b0, newAddrBits__h1044348[12:0] } : + newAddrBits__h1044348[13:0] ; + assign result_d_addrBits__h1045027 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1045011[12:0] } : - newAddrBits__h1045011[13:0] ; - assign result_d_address__h1019565 = - { 2'd0, bot__h1019587 } + + { 1'b0, newAddrBits__h1045015[12:0] } : + newAddrBits__h1045015[13:0] ; + assign result_d_address__h1019569 = + { 2'd0, bot__h1019591 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1019968 = - { 2'd0, bot__h1019990 } + + assign result_d_address__h1019972 = + { 2'd0, bot__h1019994 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1020385 = - { 2'd0, bot__h1020407 } + + assign result_d_address__h1020389 = + { 2'd0, bot__h1020411 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1020788 = - { 2'd0, bot__h1020810 } + + assign result_d_address__h1020792 = + { 2'd0, bot__h1020814 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1021457 = - { 2'd0, bot__h1021480 } + + assign result_d_address__h1021461 = + { 2'd0, bot__h1021484 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1043132 = - { 2'd0, bot__h1019587 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1043535 = - { 2'd0, bot__h1019990 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1043952 = - { 2'd0, bot__h1020407 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1044355 = - { 2'd0, bot__h1020810 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1045022 = - { 2'd0, bot__h1021480 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h245736 = { 2'd0, pointer__h245525[63:0] } ; - assign ret__h242867 = + assign result_d_address__h1043136 = + { 2'd0, bot__h1019591 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1043539 = + { 2'd0, bot__h1019994 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1043956 = + { 2'd0, bot__h1020411 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1044359 = + { 2'd0, bot__h1020814 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1045026 = + { 2'd0, bot__h1021484 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h245738 = { 2'd0, pointer__h245527[63:0] } ; + assign ret__h242869 = { 1'd0, coreFix_memExe_regToExeQ_first__664_BITS_383_T_ETC___d3723[64:0] } ; - assign ret__h244024 = + assign ret__h244026 = { 1'd0, coreFix_memExe_regToExeQ_first__664_BITS_220_T_ETC___d3785[64:0] } ; - assign ret__h257645 = + assign ret__h257647 = { 1'd0, coreFix_memExe_dTlb_procResp__276_BITS_452_TO__ETC___d4426[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19345 = - rf$read_0_rd1[27:25] < repBound__h905960 ; + rf$read_0_rd1[27:25] < repBound__h905963 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19358 = - rf$read_0_rd1[13:11] < repBound__h905960 ; + rf$read_0_rd1[13:11] < repBound__h905963 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19372 = - rf$read_0_rd1[85:83] < repBound__h905960 ; + rf$read_0_rd1[85:83] < repBound__h905963 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19413 = - rf$read_0_rd2[27:25] < repBound__h908287 ; + rf$read_0_rd2[27:25] < repBound__h908290 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19414 = - rf$read_0_rd2[13:11] < repBound__h908287 ; + rf$read_0_rd2[13:11] < repBound__h908290 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19416 = - rf$read_0_rd2[85:83] < repBound__h908287 ; + rf$read_0_rd2[85:83] < repBound__h908290 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19426 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19416, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19413 == @@ -37954,17 +37954,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16891 = - rf$read_1_rd1[27:25] < repBound__h863990 ; + rf$read_1_rd1[27:25] < repBound__h863988 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16904 = - rf$read_1_rd1[13:11] < repBound__h863990 ; + rf$read_1_rd1[13:11] < repBound__h863988 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16918 = - rf$read_1_rd1[85:83] < repBound__h863990 ; + rf$read_1_rd1[85:83] < repBound__h863988 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16959 = - rf$read_1_rd2[27:25] < repBound__h866952 ; + rf$read_1_rd2[27:25] < repBound__h866950 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16960 = - rf$read_1_rd2[13:11] < repBound__h866952 ; + rf$read_1_rd2[13:11] < repBound__h866950 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16962 = - rf$read_1_rd2[85:83] < repBound__h866952 ; + rf$read_1_rd2[85:83] < repBound__h866950 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16972 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16962, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16959 == @@ -37982,25 +37982,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3357 = - rf$read_3_rd1[27:25] < repBound__h240206 ; + rf$read_3_rd1[27:25] < repBound__h240208 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3370 = - rf$read_3_rd1[13:11] < repBound__h240206 ; + rf$read_3_rd1[13:11] < repBound__h240208 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3384 = - rf$read_3_rd1[85:83] < repBound__h240206 ; + rf$read_3_rd1[85:83] < repBound__h240208 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3611 = - rf$read_3_rd2[27:25] < repBound__h241891 ; + rf$read_3_rd2[27:25] < repBound__h241893 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3619 = - rf$read_3_rd2[13:11] < repBound__h241891 ; + rf$read_3_rd2[13:11] < repBound__h241893 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3628 = - rf$read_3_rd2[85:83] < repBound__h241891 ; + rf$read_3_rd2[85:83] < repBound__h241893 ; assign rg_core_run_state_read__0970_EQ_2_0971_AND_NOT_ETC___d24285 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h858639 = - { r1__read__h862250, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h858637 = + { r1__read__h862248, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1933_AND_epochManager_ch_ETC___d21938 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -38010,15 +38010,15 @@ module mkCore(CLK, IF_IF_fetchStage_pipelines_0_first__0544_BITS__ETC___d21530) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q16 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h856329 = { r1__read__h861139, csrf_ppn_reg } ; + assign satp_csr__read__h856327 = { r1__read__h861137, csrf_ppn_reg } ; assign sbIdx__h153572 = CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h856126 = - { r1__read__h860922, csrf_scause_code_reg } ; - assign scounteren_csr__read__h855986 = - { r1__read__h860617, csrf_scounteren_cy_reg } ; + assign scause_csr__read__h856124 = + { r1__read__h860920, csrf_scause_code_reg } ; + assign scounteren_csr__read__h855984 = + { r1__read__h860615, csrf_scounteren_cy_reg } ; assign sfd__h573271 = { value__h581498, 3'd0 } ; assign sfd__h589079 = { 1'b0, @@ -38166,24 +38166,24 @@ module mkCore(CLK, _theResult____h818714[56] ? _theResult___snd__h826961 : _theResult___snd__h826972 ; - assign sie_csr__read__h855898 = { r1__read__h859924, 1'b0 } ; - assign signBits__h1019369 = + assign sie_csr__read__h855896 = { r1__read__h859922, 1'b0 } ; + assign signBits__h1019373 = {50{robdeqPort_0_deq_data_BITS_95_TO_32__q16[63]}} ; - assign signBits__h1042936 = {50{f_csr_reqs$D_OUT[63]}} ; - assign signBits__h245531 = {50{offset__h245515[63]}} ; - assign sip_csr__read__h856266 = { r1__read__h860929, 1'b0 } ; - assign spec_bits__h983633 = specTagManager$currentSpecBits | y__h983646 ; - assign sstatus_csr__read__h855828 = { r1__read__h859520, csrf_ie_vec_0 } ; - assign tb__h873081 = { impliedTopBits__h872935, topBits__h872931[11] } ; - assign tb__h873629 = { impliedTopBits__h873483, topBits__h873479[11] } ; - assign tb__h914121 = { impliedTopBits__h913975, topBits__h913971[11] } ; - assign tb__h914669 = { impliedTopBits__h914523, topBits__h914519[11] } ; - assign thin_address__h1010149 = + assign signBits__h1042940 = {50{f_csr_reqs$D_OUT[63]}} ; + assign signBits__h245533 = {50{offset__h245517[63]}} ; + assign sip_csr__read__h856264 = { r1__read__h860927, 1'b0 } ; + assign spec_bits__h983637 = specTagManager$currentSpecBits | y__h983650 ; + assign sstatus_csr__read__h855826 = { r1__read__h859518, csrf_ie_vec_0 } ; + assign tb__h873079 = { impliedTopBits__h872933, topBits__h872929[11] } ; + assign tb__h873627 = { impliedTopBits__h873481, topBits__h873477[11] } ; + assign tb__h914124 = { impliedTopBits__h913978, topBits__h913974[11] } ; + assign tb__h914672 = { impliedTopBits__h914526, topBits__h914522[11] } ; + assign thin_address__h1010153 = csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? IF_csrf_stcc_reg_read__6237_BIT_86_3114_AND_NO_ETC___d23282 : IF_csrf_mtcc_reg_read__6389_BIT_86_3185_AND_NO_ETC___d23283 ; - assign tmpAddr__h245724 = pointer__h245525[63:0] ; - assign tmp_expBotHalf__h1005634 = + assign tmpAddr__h245726 = pointer__h245527[63:0] ; + assign tmp_expBotHalf__h1005638 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; assign tmp_expBotHalf__h128322 = @@ -38191,24 +38191,24 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; assign tmp_expBotHalf__h141466 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h185247 = { ~x__h185172[66], x__h185172[65:64] } ; - assign tmp_expBotHalf__h204310 = { ~x__h201336[66], x__h201336[65:64] } ; - assign tmp_expBotHalf__h219281 = + assign tmp_expBotHalf__h185248 = { ~x__h185173[66], x__h185173[65:64] } ; + assign tmp_expBotHalf__h204311 = { ~x__h201337[66], x__h201337[65:64] } ; + assign tmp_expBotHalf__h219282 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h872784 = + assign tmp_expBotHalf__h872782 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h873332 = + assign tmp_expBotHalf__h873330 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h913824 = + assign tmp_expBotHalf__h913827 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h914372 = + assign tmp_expBotHalf__h914375 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expTopHalf__h1005632 = + assign tmp_expTopHalf__h1005636 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; assign tmp_expTopHalf__h128320 = @@ -38216,52 +38216,52 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[78] } ; assign tmp_expTopHalf__h141464 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h185245 = { ~x__h185172[80:79], x__h185172[78] } ; - assign tmp_expTopHalf__h204308 = { ~x__h201336[80:79], x__h201336[78] } ; - assign tmp_expTopHalf__h219279 = + assign tmp_expTopHalf__h185246 = { ~x__h185173[80:79], x__h185173[78] } ; + assign tmp_expTopHalf__h204309 = { ~x__h201337[80:79], x__h201337[78] } ; + assign tmp_expTopHalf__h219280 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h872782 = + assign tmp_expTopHalf__h872780 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h873330 = + assign tmp_expTopHalf__h873328 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h913822 = + assign tmp_expTopHalf__h913825 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h914370 = + assign tmp_expTopHalf__h914373 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign toBoundsM1__h1019382 = { 3'b110, ~csrf_stcc_reg[10:0] } ; - assign toBoundsM1__h1019785 = + assign toBoundsM1__h1019386 = { 3'b110, ~csrf_stcc_reg[10:0] } ; + assign toBoundsM1__h1019789 = { 3'b110, ~IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[10:0] } ; - assign toBoundsM1__h1020202 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; - assign toBoundsM1__h1020605 = + assign toBoundsM1__h1020206 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; + assign toBoundsM1__h1020609 = { 3'b110, ~IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[10:0] } ; - assign toBoundsM1__h1021274 = { 3'b110, ~csrf_rg_dpc[10:0] } ; - assign toBoundsM1__h245544 = - repBoundBits__h245540 + + assign toBoundsM1__h1021278 = { 3'b110, ~csrf_rg_dpc[10:0] } ; + assign toBoundsM1__h245546 = + repBoundBits__h245542 + ~coreFix_memExe_regToExeQ$first[317:304] ; - assign toBounds__h1019381 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; - assign toBounds__h1019784 = + assign toBounds__h1019385 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; + assign toBounds__h1019788 = 14'd14336 - { 3'b0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275[10:0] } ; - assign toBounds__h1020201 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; - assign toBounds__h1020604 = + assign toBounds__h1020205 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; + assign toBounds__h1020608 = 14'd14336 - { 3'b0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427[10:0] } ; - assign toBounds__h1021273 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; - assign toBounds__h245543 = - repBoundBits__h245540 - coreFix_memExe_regToExeQ$first[317:304] ; - assign topBits__h1005768 = + assign toBounds__h1021277 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; + assign toBounds__h245545 = + repBoundBits__h245542 - coreFix_memExe_regToExeQ$first[317:304] ; + assign topBits__h1005772 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h1005865 ; + b_top__h1005869 ; assign topBits__h128456 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : @@ -38270,36 +38270,36 @@ module mkCore(CLK, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : b_top__h141697 ; - assign topBits__h185381 = - INV_x85172_BITS_108_TO_90__q35[0] ? - { x__h185172[89:81], 3'd0 } : - b_top__h185478 ; - assign topBits__h204444 = - INV_x01336_BITS_108_TO_90__q37[0] ? - { x__h201336[89:81], 3'd0 } : - b_top__h204541 ; - assign topBits__h219415 = + assign topBits__h185382 = + INV_x85173_BITS_108_TO_90__q35[0] ? + { x__h185173[89:81], 3'd0 } : + b_top__h185479 ; + assign topBits__h204445 = + INV_x01337_BITS_108_TO_90__q37[0] ? + { x__h201337[89:81], 3'd0 } : + b_top__h204542 ; + assign topBits__h219416 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h219512 ; - assign topBits__h872931 = + b_top__h219513 ; + assign topBits__h872929 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h873029 ; - assign topBits__h873479 = + b_top__h873027 ; + assign topBits__h873477 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h873577 ; - assign topBits__h913971 = + b_top__h873575 ; + assign topBits__h913974 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h914069 ; - assign topBits__h914519 = + b_top__h914072 ; + assign topBits__h914522 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h914617 ; - assign trap_val__h1007807 = { 53'd0, x__h1009628 } ; - assign upd__h1025314 = + b_top__h914620 ; + assign trap_val__h1007811 = { 53'd0, x__h1009632 } ; + assign upd__h1025318 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -38312,7 +38312,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1023589 = + assign v__h1023593 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], @@ -38325,7 +38325,7 @@ module mkCore(CLK, ~IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918[2], IF_csrf_sepcc_reg_read_wget__3896_BIT_34_3908__ETC___d23918[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1024298 = + assign v__h1024302 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], @@ -38338,41 +38338,41 @@ module mkCore(CLK, ~IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952[2], IF_csrf_mepcc_reg_read_wget__3930_BIT_34_3942__ETC___d23952[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h519246 = + assign v__h519247 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7318 ? - v__h519441 : + v__h519442 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h519441 = + assign v__h519442 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h521266 = + assign v__h521267 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7412 ? - v__h521646 : + v__h521647 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h521646 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h536985 = + assign v__h521647 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h536986 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7571 ? - v__h537180 : + v__h537181 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h537180 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h539434 = + assign v__h537181 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h539435 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7655 ? - v__h539629 : + v__h539630 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h539629 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h560454 = + assign v__h539630 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h560455 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7860 ? - v__h560649 : + v__h560650 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h560649 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h564233 = + assign v__h560650 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h564234 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7942 ? - v__h564428 : + v__h564429 : coreFix_memExe_forwardQ_enqP ; - assign v__h564428 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h564429 = coreFix_memExe_forwardQ_enqP + 1'd1 ; assign v__h841893 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? v__h841903 : @@ -38381,21 +38381,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; assign v__h842934 = v__h841893 - 2'd1 ; assign value_BIT_23___h810070 = f3_exp__h798126 != 8'd0 ; - assign value__h242584 = x__h242602 | in__h242694[63:0] ; - assign value__h242748 = - { coreFix_memExe_regToExeQ$first[381:332] & mask__h242755, + assign value__h242586 = x__h242604 | in__h242696[63:0] ; + assign value__h242750 = + { coreFix_memExe_regToExeQ$first[381:332] & mask__h242757, 14'd0 } + - addBase__h242754 ; - assign value__h243741 = x__h243759 | in__h243851[63:0] ; - assign value__h243905 = - { coreFix_memExe_regToExeQ$first[218:169] & mask__h243912, + addBase__h242756 ; + assign value__h243743 = x__h243761 | in__h243853[63:0] ; + assign value__h243907 = + { coreFix_memExe_regToExeQ$first[218:169] & mask__h243914, 14'd0 } + - addBase__h243911 ; - assign value__h257362 = x__h257380 | in__h257472[63:0] ; - assign value__h257526 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h257533, + addBase__h243913 ; + assign value__h257364 = x__h257382 | in__h257474[63:0] ; + assign value__h257528 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h257535, 14'd0 } + - addBase__h257532 ; + addBase__h257534 ; assign value__h581498 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -38414,78 +38414,78 @@ module mkCore(CLK, assign value__h724773 = { 1'b0, f1_exp__h719828 != 8'd0, f1_sfd__h719829 } ; assign value__h763626 = { 1'b0, f2_exp__h758822 != 8'd0, f2_sfd__h758823 } ; assign value__h802930 = { 1'b0, value_BIT_23___h810070, f3_sfd__h798127 } ; - assign vm_mode_reg__read__h861145 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h924556 = + assign vm_mode_reg__read__h861143 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h924560 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h924612 : + result__h924616 : 12'd4095 ; - assign wordIdx__h266168 = + assign wordIdx__h266170 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1011654 = + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1011658 = csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1005641 = commitStage_commitTrap[172:109] >> x__h1005679 ; - assign x__h1005679 = - { tmp_expTopHalf__h1005632, tmp_expBotHalf__h1005634 } ; - assign x__h1005839 = { impliedTopBits__h1005772, topBits__h1005768 } ; - assign x__h1005856 = x__h1005859[13:12] + carry_out__h1005770 ; - assign x__h1005859 = + assign x__h1005645 = commitStage_commitTrap[172:109] >> x__h1005683 ; + assign x__h1005683 = + { tmp_expTopHalf__h1005636, tmp_expBotHalf__h1005638 } ; + assign x__h1005843 = { impliedTopBits__h1005776, topBits__h1005772 } ; + assign x__h1005860 = x__h1005863[13:12] + carry_out__h1005774 ; + assign x__h1005863 = INV_commitStage_commitTrap_BITS_217_TO_199__q15[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h1005866 ; - assign x__h1008354 = - x__h1008356 << + b_base__h1005870 ; + assign x__h1008358 = + x__h1008360 << IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956 ; - assign x__h1008356 = { {48{offset__h1008342[15]}}, offset__h1008342 } ; - assign x__h1008441 = + assign x__h1008360 = { {48{offset__h1008346[15]}}, offset__h1008346 } ; + assign x__h1008445 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2639_BITS_217_TO_ETC___d22956 ; - assign x__h1009628 = + assign x__h1009632 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q26 } ; - assign x__h1010328 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h1010354 = { cause_code__h1006050, 2'b0 } ; - assign x__h1010455 = address__h1010261 >> csrf_stcc_reg[33:28] ; - assign x__h1010759 = address__h1010605 >> csrf_stcc_reg[33:28] ; - assign x__h1010985 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h1011112 = address__h1010918 >> csrf_mtcc_reg[33:28] ; - assign x__h1011416 = address__h1011262 >> csrf_mtcc_reg[33:28] ; - assign x__h1011651 = + assign x__h1010332 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h1010358 = { cause_code__h1006054, 2'b0 } ; + assign x__h1010459 = address__h1010265 >> csrf_stcc_reg[33:28] ; + assign x__h1010763 = address__h1010609 >> csrf_stcc_reg[33:28] ; + assign x__h1010989 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h1011116 = address__h1010922 >> csrf_mtcc_reg[33:28] ; + assign x__h1011420 = address__h1011266 >> csrf_mtcc_reg[33:28] ; + assign x__h1011655 = csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h1011672 = + assign x__h1011676 = csrf_prv_reg_read__0574_ULE_1_2990_AND_IF_comm_ETC___d23024 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; - assign x__h1019399 = + assign x__h1019403 = robdeqPort_0_deq_data_BITS_95_TO_32__q16[63:14] ^ - signBits__h1019369 ; - assign x__h1019495 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; - assign x__h1019898 = + signBits__h1019373 ; + assign x__h1019499 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; + assign x__h1019902 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h1020315 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; - assign x__h1020718 = + assign x__h1020319 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; + assign x__h1020722 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h1021387 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; - assign x__h1023610 = { 1'b0, csrf_spp_reg } ; - assign x__h1028080 = + assign x__h1021391 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; + assign x__h1023614 = { 1'b0, csrf_spp_reg } ; + assign x__h1028084 = NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210 ? - y_avValue_snd_snd_snd_fst__h1027902 : + y_avValue_snd_snd_snd_fst__h1027906 : IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 ; - assign x__h1042966 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1042936 ; - assign x__h1043062 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; - assign x__h1043465 = + assign x__h1042970 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1042940 ; + assign x__h1043066 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; + assign x__h1043469 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h1043882 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; - assign x__h1044285 = + assign x__h1043886 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; + assign x__h1044289 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h1044952 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; + assign x__h1044956 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; assign x__h128329 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h128367 ; assign x__h128367 = { tmp_expTopHalf__h128320, tmp_expBotHalf__h128322 } ; assign x__h128527 = { impliedTopBits__h128460, topBits__h128456 } ; @@ -38507,113 +38507,113 @@ module mkCore(CLK, coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; assign x__h153681 = { 3'd0, sbIdx__h153572 } ; - assign x__h185172 = + assign x__h185173 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d1917 } ; - assign x__h185254 = x__h185172[63:0] >> x__h185292 ; - assign x__h185292 = { tmp_expTopHalf__h185245, tmp_expBotHalf__h185247 } ; - assign x__h185452 = { impliedTopBits__h185385, topBits__h185381 } ; - assign x__h185469 = x__h185472[13:12] + carry_out__h185383 ; - assign x__h185472 = - INV_x85172_BITS_108_TO_90__q35[0] ? - { x__h185172[77:67], 3'd0 } : - b_base__h185479 ; - assign x__h201336 = + assign x__h185255 = x__h185173[63:0] >> x__h185293 ; + assign x__h185293 = { tmp_expTopHalf__h185246, tmp_expBotHalf__h185248 } ; + assign x__h185453 = { impliedTopBits__h185386, topBits__h185382 } ; + assign x__h185470 = x__h185473[13:12] + carry_out__h185384 ; + assign x__h185473 = + INV_x85173_BITS_108_TO_90__q35[0] ? + { x__h185173[77:67], 3'd0 } : + b_base__h185480 ; + assign x__h201337 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__502_BIT_117_525_ETC___d2085 } ; - assign x__h204317 = x__h201336[63:0] >> x__h204355 ; - assign x__h204355 = { tmp_expTopHalf__h204308, tmp_expBotHalf__h204310 } ; - assign x__h204515 = { impliedTopBits__h204448, topBits__h204444 } ; - assign x__h204532 = x__h204535[13:12] + carry_out__h204446 ; - assign x__h204535 = - INV_x01336_BITS_108_TO_90__q37[0] ? - { x__h201336[77:67], 3'd0 } : - b_base__h204542 ; - assign x__h219288 = coreFix_memExe_lsq$respLd[63:0] >> x__h219326 ; - assign x__h219326 = { tmp_expTopHalf__h219279, tmp_expBotHalf__h219281 } ; - assign x__h219486 = { impliedTopBits__h219419, topBits__h219415 } ; - assign x__h219503 = x__h219506[13:12] + carry_out__h219417 ; - assign x__h219506 = + assign x__h204318 = x__h201337[63:0] >> x__h204356 ; + assign x__h204356 = { tmp_expTopHalf__h204309, tmp_expBotHalf__h204311 } ; + assign x__h204516 = { impliedTopBits__h204449, topBits__h204445 } ; + assign x__h204533 = x__h204536[13:12] + carry_out__h204447 ; + assign x__h204536 = + INV_x01337_BITS_108_TO_90__q37[0] ? + { x__h201337[77:67], 3'd0 } : + b_base__h204543 ; + assign x__h219289 = coreFix_memExe_lsq$respLd[63:0] >> x__h219327 ; + assign x__h219327 = { tmp_expTopHalf__h219280, tmp_expBotHalf__h219282 } ; + assign x__h219487 = { impliedTopBits__h219420, topBits__h219416 } ; + assign x__h219504 = x__h219507[13:12] + carry_out__h219418 ; + assign x__h219507 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h219513 ; - assign x__h238634 = + b_base__h219514 ; + assign x__h238636 = (coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3075 : 66'd0 ; - assign x__h242602 = x__h242604 << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h242604 = { {48{offset__h242590[15]}}, offset__h242590 } ; - assign x__h242712 = + assign x__h242604 = x__h242606 << coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h242606 = { {48{offset__h242592[15]}}, offset__h242592 } ; + assign x__h242714 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h242860 = + assign x__h242862 = coreFix_memExe_regToExeQ_first__664_BITS_265_T_ETC___d3736 ? - result__h243490 : - ret__h242867 ; - assign x__h242962 = + result__h243492 : + ret__h242869 ; + assign x__h242964 = { coreFix_memExe_regToExeQ$first[225:224], coreFix_memExe_regToExeQ$first[259:246] } ; - assign x__h243031 = + assign x__h243033 = (coreFix_memExe_regToExeQ$first[265:260] == 6'd50) ? coreFix_memExe_regToExeQ$first[245] : coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3[49] ; - assign x__h243759 = x__h243761 << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h243761 = { {48{offset__h243747[15]}}, offset__h243747 } ; - assign x__h243869 = + assign x__h243761 = x__h243763 << coreFix_memExe_regToExeQ$first[102:97] ; + assign x__h243763 = { {48{offset__h243749[15]}}, offset__h243749 } ; + assign x__h243871 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h244017 = + assign x__h244019 = coreFix_memExe_regToExeQ_first__664_BITS_102_T_ETC___d3798 ? - result__h244647 : - ret__h244024 ; - assign x__h244119 = + result__h244649 : + ret__h244026 ; + assign x__h244121 = { coreFix_memExe_regToExeQ$first[62:61], coreFix_memExe_regToExeQ$first[96:83] } ; - assign x__h244188 = + assign x__h244190 = (coreFix_memExe_regToExeQ$first[102:97] == 6'd50) ? coreFix_memExe_regToExeQ$first[82] : coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5[49] ; - assign x__h245561 = offset__h245515[63:14] ^ signBits__h245531 ; - assign x__h245664 = - offset__h245515 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h247565 = { pointer__h245525[3:0], 3'b0 } ; - assign x__h251007 = - pointer__h245525 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h252365 = x__h252377 + y__h252378 ; - assign x__h252377 = x__h252389 + y__h252390 ; - assign x__h252389 = x__h252401 + y__h252402 ; - assign x__h252401 = x__h252413 + y__h252414 ; - assign x__h252413 = x__h252425 + y__h252426 ; - assign x__h252425 = x__h252437 + y__h252438 ; - assign x__h252437 = x__h252449 + y__h252450 ; - assign x__h252449 = x__h252461 + y__h252462 ; - assign x__h252461 = x__h252473 + y__h252474 ; - assign x__h252473 = x__h252485 + y__h252486 ; - assign x__h252485 = x__h252497 + y__h252498 ; - assign x__h252497 = x__h252509 + y__h252510 ; - assign x__h252509 = x__h252521 + y__h252522 ; - assign x__h252521 = x__h252533 + y__h252534 ; - assign x__h252533 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h257380 = x__h257382 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h257382 = { {48{offset__h257368[15]}}, offset__h257368 } ; - assign x__h257490 = + assign x__h245563 = offset__h245517[63:14] ^ signBits__h245533 ; + assign x__h245666 = + offset__h245517 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h247567 = { pointer__h245527[3:0], 3'b0 } ; + assign x__h251009 = + pointer__h245527 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h252367 = x__h252379 + y__h252380 ; + assign x__h252379 = x__h252391 + y__h252392 ; + assign x__h252391 = x__h252403 + y__h252404 ; + assign x__h252403 = x__h252415 + y__h252416 ; + assign x__h252415 = x__h252427 + y__h252428 ; + assign x__h252427 = x__h252439 + y__h252440 ; + assign x__h252439 = x__h252451 + y__h252452 ; + assign x__h252451 = x__h252463 + y__h252464 ; + assign x__h252463 = x__h252475 + y__h252476 ; + assign x__h252475 = x__h252487 + y__h252488 ; + assign x__h252487 = x__h252499 + y__h252500 ; + assign x__h252499 = x__h252511 + y__h252512 ; + assign x__h252511 = x__h252523 + y__h252524 ; + assign x__h252523 = x__h252535 + y__h252536 ; + assign x__h252535 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h257382 = x__h257384 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h257384 = { {48{offset__h257370[15]}}, offset__h257370 } ; + assign x__h257492 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h257638 = + assign x__h257640 = coreFix_memExe_dTlb_procResp__276_BITS_334_TO__ETC___d4439 ? - result__h258268 : - ret__h257645 ; - assign x__h257740 = + result__h258270 : + ret__h257647 ; + assign x__h257742 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h257809 = + assign x__h257811 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h526097 = + assign x__h526098 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; @@ -38687,42 +38687,42 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15402, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d15403 } ; - assign x__h859505 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h860585 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign x__h860646 = - x__h860648 << + assign x__h859503 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h860583 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; + assign x__h860644 = + x__h860646 << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h860648 = { {48{offset__h860634[15]}}, offset__h860634 } ; - assign x__h860890 = + assign x__h860646 = { {48{offset__h860632[15]}}, offset__h860632 } ; + assign x__h860888 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16291 ; - assign x__h861578 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign x__h861639 = - x__h861641 << + assign x__h861576 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; + assign x__h861637 = + x__h861639 << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h861641 = { {48{offset__h861627[15]}}, offset__h861627 } ; - assign x__h861882 = + assign x__h861639 = { {48{offset__h861625[15]}}, offset__h861625 } ; + assign x__h861880 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16443 ; - assign x__h862408 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign x__h872792 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h872830 ; - assign x__h872830 = { tmp_expTopHalf__h872782, tmp_expBotHalf__h872784 } ; - assign x__h873003 = { impliedTopBits__h872935, topBits__h872931 } ; - assign x__h873020 = x__h873023[13:12] + carry_out__h872933 ; - assign x__h873023 = + assign x__h862406 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign x__h872790 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h872828 ; + assign x__h872828 = { tmp_expTopHalf__h872780, tmp_expBotHalf__h872782 } ; + assign x__h873001 = { impliedTopBits__h872933, topBits__h872929 } ; + assign x__h873018 = x__h873021[13:12] + carry_out__h872931 ; + assign x__h873021 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h873030 ; - assign x__h873340 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h873378 ; - assign x__h873378 = { tmp_expTopHalf__h873330, tmp_expBotHalf__h873332 } ; - assign x__h873551 = { impliedTopBits__h873483, topBits__h873479 } ; - assign x__h873568 = x__h873571[13:12] + carry_out__h873481 ; - assign x__h873571 = + b_base__h873028 ; + assign x__h873338 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h873376 ; + assign x__h873376 = { tmp_expTopHalf__h873328, tmp_expBotHalf__h873330 } ; + assign x__h873549 = { impliedTopBits__h873481, topBits__h873477 } ; + assign x__h873566 = x__h873569[13:12] + carry_out__h873479 ; + assign x__h873569 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h873578 ; - assign x__h873778 = + b_base__h873576 ; + assign x__h873776 = { basicExec___d17927[443], basicExec___d17927[362:347], basicExec___d17927[345:344], @@ -38734,7 +38734,7 @@ module mkCore(CLK, ~IF_basicExec_7927_BIT_325_7938_THEN_basicExec__ETC___d17946[2], IF_basicExec_7927_BIT_325_7938_THEN_basicExec__ETC___d17946[1:0], basicExec___d17927[440:377] } ; - assign x__h887432 = + assign x__h887431 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -38746,34 +38746,34 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18268[2], IF_coreFix_aluExe_1_exeToFinQ_first__8058_BIT__ETC___d18268[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h903662 = x__h903664 << csrf_stcc_reg[33:28] ; - assign x__h903664 = { {48{offset__h903650[15]}}, offset__h903650 } ; - assign x__h903946 = x__h903948 << csrf_mtcc_reg[33:28] ; - assign x__h903948 = { {48{offset__h903934[15]}}, offset__h903934 } ; - assign x__h904216 = + assign x__h903665 = x__h903667 << csrf_stcc_reg[33:28] ; + assign x__h903667 = { {48{offset__h903653[15]}}, offset__h903653 } ; + assign x__h903949 = x__h903951 << csrf_mtcc_reg[33:28] ; + assign x__h903951 = { {48{offset__h903937[15]}}, offset__h903937 } ; + assign x__h904219 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q25, 5'd3 } ; - assign x__h904291 = x__h904293 << csrf_rg_dpc[33:28] ; - assign x__h904293 = { {48{offset__h904279[15]}}, offset__h904279 } ; - assign x__h913832 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h913870 ; - assign x__h913870 = { tmp_expTopHalf__h913822, tmp_expBotHalf__h913824 } ; - assign x__h914043 = { impliedTopBits__h913975, topBits__h913971 } ; - assign x__h914060 = x__h914063[13:12] + carry_out__h913973 ; - assign x__h914063 = + assign x__h904294 = x__h904296 << csrf_rg_dpc[33:28] ; + assign x__h904296 = { {48{offset__h904282[15]}}, offset__h904282 } ; + assign x__h913835 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h913873 ; + assign x__h913873 = { tmp_expTopHalf__h913825, tmp_expBotHalf__h913827 } ; + assign x__h914046 = { impliedTopBits__h913978, topBits__h913974 } ; + assign x__h914063 = x__h914066[13:12] + carry_out__h913976 ; + assign x__h914066 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h914070 ; - assign x__h914380 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h914418 ; - assign x__h914418 = { tmp_expTopHalf__h914370, tmp_expBotHalf__h914372 } ; - assign x__h914591 = { impliedTopBits__h914523, topBits__h914519 } ; - assign x__h914608 = x__h914611[13:12] + carry_out__h914521 ; - assign x__h914611 = + b_base__h914073 ; + assign x__h914383 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h914421 ; + assign x__h914421 = { tmp_expTopHalf__h914373, tmp_expBotHalf__h914375 } ; + assign x__h914594 = { impliedTopBits__h914526, topBits__h914522 } ; + assign x__h914611 = x__h914614[13:12] + carry_out__h914524 ; + assign x__h914614 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h914618 ; - assign x__h914818 = + b_base__h914621 ; + assign x__h914821 = { basicExec___d20102[443], basicExec___d20102[362:347], basicExec___d20102[345:344], @@ -38785,7 +38785,7 @@ module mkCore(CLK, ~IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121[2], IF_basicExec_0102_BIT_325_0113_THEN_basicExec__ETC___d20121[1:0], basicExec___d20102[440:377] } ; - assign x__h923374 = + assign x__h923378 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -38797,8 +38797,8 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20442[2], IF_coreFix_aluExe_0_exeToFinQ_first__0233_BIT__ETC___d20442[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h924560 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h924611 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h924564 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h924615 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; assign x_addr__h19883 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[214:151] : @@ -38807,7 +38807,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h539796 = + assign x_addr__h539797 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -38815,7 +38815,7 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h934999 = csrf_frm_reg ; + assign x_decodeInfo_frm__h935003 = csrf_frm_reg ; assign x_quotient__h710242 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : @@ -38823,7 +38823,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? q___1__h711053 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h855737 = { 63'd0, csrf_stats_module_doStats } ; + assign x_reg_ifc__read__h855735 = { 63'd0, csrf_stats_module_doStats } ; assign x_remainder__h710243 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : @@ -38831,45 +38831,45 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? r___1__h711080 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h1008440 = ~x__h1008441 ; - assign y__h1010384 = { mask__h1010267[62:0], 1'd0 } ; - assign y__h1011041 = { mask__h1010924[62:0], 1'd0 } ; - assign y__h1027855 = + assign y__h1008444 = ~x__h1008445 ; + assign y__h1010388 = { mask__h1010271[62:0], 1'd0 } ; + assign y__h1011045 = { mask__h1010928[62:0], 1'd0 } ; + assign y__h1027859 = NOT_rob_deqPort_0_canDeq__3985_3986_OR_rob_deq_ETC___d24210 ? - y_avValue_snd_snd_snd_snd_snd__h1027908 : + y_avValue_snd_snd_snd_snd_snd__h1027912 : IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 ; - assign y__h242711 = ~x__h242712 ; - assign y__h243868 = ~x__h243869 ; - assign y__h252366 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h252378 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h252390 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h252402 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h252414 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h252426 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h252438 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h252450 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h252462 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h252474 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h252486 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h252498 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h252510 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h252522 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h252534 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h257489 = ~x__h257490 ; - assign y__h426314 = + assign y__h242713 = ~x__h242714 ; + assign y__h243870 = ~x__h243871 ; + assign y__h252368 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h252380 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h252392 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h252404 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h252416 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h252428 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h252440 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h252452 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h252464 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h252476 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h252488 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h252500 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h252512 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h252524 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h252536 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h257491 = ~x__h257492 ; + assign y__h426315 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[169:164] } ; - assign y__h860584 = ~x__h860585 ; - assign y__h860889 = ~x__h860890 ; - assign y__h861577 = ~x__h861578 ; - assign y__h861881 = ~x__h861882 ; - assign y__h862407 = ~x__h862408 ; - assign y__h874032 = - { coreFix_aluExe_1_regToExeQ$first[306:242], address__h874071 } ; - assign y__h915072 = - { coreFix_aluExe_0_regToExeQ$first[306:242], address__h915075 } ; - assign y__h924590 = ~x__h924560 ; - assign y__h929520 = + assign y__h860582 = ~x__h860583 ; + assign y__h860887 = ~x__h860888 ; + assign y__h861575 = ~x__h861576 ; + assign y__h861879 = ~x__h861880 ; + assign y__h862405 = ~x__h862406 ; + assign y__h874030 = + { coreFix_aluExe_1_regToExeQ$first[306:242], address__h874069 } ; + assign y__h915075 = + { coreFix_aluExe_0_regToExeQ$first[306:242], address__h915078 } ; + assign y__h924594 = ~x__h924564 ; + assign y__h929524 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -38878,7 +38878,7 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h983646 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h983650 = 12'd1 << specTagManager$nextSpecTag ; assign y_avValue__h715399 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12470 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : @@ -38891,7 +38891,7 @@ module mkCore(CLK, NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12525 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12616 ; - assign y_avValue_snd_fst__h1027249 = + assign y_avValue_snd_fst__h1027253 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38906,7 +38906,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1027892 = + assign y_avValue_snd_fst__h1027896 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38920,25 +38920,25 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 : - y_avValue_snd_fst__h1027921 ; - assign y_avValue_snd_fst__h1027921 = + y_avValue_snd_fst__h1027925 ; + assign y_avValue_snd_fst__h1027925 = IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24217 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h973226 = + assign y_avValue_snd_fst__h973230 = ((fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1456_AND__ETC___d21480) ? - y_avValue_snd_fst__h973268 : + y_avValue_snd_fst__h973272 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h973268 = + assign y_avValue_snd_fst__h973272 = IF_fetchStage_pipelines_0_first__0544_BITS_268_ETC___d21521 ? - y_avValue_snd_fst__h973310 : + y_avValue_snd_fst__h973314 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h973310 = + assign y_avValue_snd_fst__h973314 = (fetchStage$pipelines_0_first[268:266] == 3'd1) ? - spec_bits__h983633 : + spec_bits__h983637 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1027259 = + assign y_avValue_snd_snd_snd_fst__h1027263 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38953,7 +38953,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1027902 = + assign y_avValue_snd_snd_snd_fst__h1027906 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38967,11 +38967,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 : - y_avValue_snd_snd_snd_fst__h1027931 ; - assign y_avValue_snd_snd_snd_fst__h1027931 = + y_avValue_snd_snd_snd_fst__h1027935 ; + assign y_avValue_snd_snd_snd_fst__h1027935 = IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24239 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1027265 = + assign y_avValue_snd_snd_snd_snd_snd__h1027269 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38986,7 +38986,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1027908 = + assign y_avValue_snd_snd_snd_snd_snd__h1027912 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -39000,8 +39000,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 : - y_avValue_snd_snd_snd_snd_snd__h1027937 ; - assign y_avValue_snd_snd_snd_snd_snd__h1027937 = + y_avValue_snd_snd_snd_snd_snd__h1027941 ; + assign y_avValue_snd_snd_snd_snd_snd__h1027941 = IF_rob_deqPort_0_canDeq__3985_THEN_IF_NOT_rob__ETC___d24107 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -39027,28 +39027,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h505453 = + x__h505454 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -39058,10 +39058,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h509971 = + addr__h509972 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; 1'd1: - addr__h509971 = + addr__h509972 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; endcase end @@ -39070,16 +39070,16 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h215264 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h215264 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h215265 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h215265 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h217617 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h217617 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h217618 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h217618 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -39138,16 +39138,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h267667 = + x__h267669 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd1: - x__h267667 = + x__h267669 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd2: - x__h267667 = + x__h267669 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; 2'd3: - x__h267667 = + x__h267669 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21; endcase end @@ -39155,8 +39155,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h1006266 = commitStage_commitTrap[35:32]; - default: i__h1006266 = 4'd15; + i__h1006270 = commitStage_commitTrap[35:32]; + default: i__h1006270 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -39229,9 +39229,9 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h513121 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h513122 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h513121 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h513122 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or @@ -39497,16 +39497,16 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h1006066 = commitStage_commitTrap[36:32]; - default: i__h1006066 = 5'd28; + i__h1006070 = commitStage_commitTrap[36:32]; + default: i__h1006070 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h1007625 or i__h1006066) + always@(commitStage_commitTrap or cause_code__h1007629 or i__h1006070) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h1006050 = 5'd28; - 2'd1: cause_code__h1006050 = i__h1006066; - default: cause_code__h1006050 = cause_code__h1007625; + 2'd0: cause_code__h1006054 = 5'd28; + 2'd1: cause_code__h1006054 = i__h1006070; + default: cause_code__h1006054 = cause_code__h1007629; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -39814,16 +39814,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h267822 = + x__h267824 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4887[31:0]; 2'd1: - x__h267822 = + x__h267824 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4887[63:32]; 2'd2: - x__h267822 = + x__h267824 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4881[31:0]; 2'd3: - x__h267822 = + x__h267824 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4881[63:32]; endcase end @@ -44360,10 +44360,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h954118 or + always@(k__h954122 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h954118) + case (k__h954122) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__149_ETC___d21502 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -44383,10 +44383,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h954118 or + always@(k__h954122 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h954118) + case (k__h954122) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1491_co_ETC___d21524 = coreFix_aluExe_0_rsAlu$canEnq; @@ -44603,7 +44603,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h978721 or + always@(idx__h978725 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d21951 or coreFix_aluExe_0_rsAlu$canEnq or @@ -44613,7 +44613,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0544_BITS_268_TO_ETC___d21956 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h978721) + case (idx__h978725) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0542_AN_ETC___d21979 = fetchStage$pipelines_0_canDeq && @@ -44717,15 +44717,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1585_AND__ETC___d21941; endcase end - always@(k__h954118 or + always@(k__h954122 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h954118) + case (k__h954122) 1'd0: - CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k54122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k54118_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k54122_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -44761,7 +44761,7 @@ module mkCore(CLK, regRenamingTable_RDY_rename_0_getRename__1316__ETC___d22153; endcase end - always@(idx__h978721 or + always@(idx__h978725 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -44771,7 +44771,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0544_BITS_26_ETC___d22210 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h978721) + case (idx__h978725) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__054_ETC___d22215 = (!fetchStage$pipelines_0_canDeq || @@ -45193,18 +45193,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = - coreFix_memExe_forwardQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = - coreFix_memExe_forwardQ_data_1[127:64]; - endcase - end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -45249,6 +45237,18 @@ module mkCore(CLK, coreFix_memExe_memRespLdQ_data_1[63:0]; endcase end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_224_BIT_ETC___d2238 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin @@ -45266,12 +45266,12 @@ module mkCore(CLK, begin case (commitStage_commitTrap[36:32]) 5'd0, 5'd3: - trap_val__h1007654 = + trap_val__h1007658 = SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d23054; 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h1007654 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h1007654 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h1007654 = 64'd0; + trap_val__h1007658 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h1007658 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h1007658 = 64'd0; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or @@ -46401,17 +46401,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h864887 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h864887 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h864887 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h864887 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h864885 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h864885 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h864885 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h864885 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h864887 = + thin_addrBits__h864885 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271; - 5'd28: thin_addrBits__h864887 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h864887 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h864887 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h864887 = + 5'd28: thin_addrBits__h864885 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h864885 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h864885 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h864885 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423; endcase end @@ -46425,17 +46425,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h906784 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h906784 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h906784 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h906784 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h906787 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h906787 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h906787 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h906787 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h906784 = + thin_addrBits__h906787 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16271; - 5'd28: thin_addrBits__h906784 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h906784 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h906784 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h906784 = + 5'd28: thin_addrBits__h906787 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h906787 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h906787 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h906787 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16423; endcase end @@ -46449,17 +46449,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h866835 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h866835 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h866835 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h866835 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h866833 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h866833 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h866833 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h866833 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h866835 = + thin_bounds_baseBits__h866833 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275; - 5'd28: thin_bounds_baseBits__h866835 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h866835 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h866835 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h866835 = + 5'd28: thin_bounds_baseBits__h866833 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h866833 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h866833 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h866833 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427; endcase end @@ -46473,17 +46473,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h908190 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h908190 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h908190 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h908190 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h908193 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h908193 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h908193 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h908193 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h908190 = + thin_bounds_baseBits__h908193 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16275; - 5'd28: thin_bounds_baseBits__h908190 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h908190 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h908190 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h908190 = + 5'd28: thin_bounds_baseBits__h908193 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h908193 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h908193 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h908193 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16427; endcase end @@ -46497,17 +46497,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h864886 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h864886 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h864886 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h864886 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h864884 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h864884 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h864884 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h864884 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h864886 = + thin_address__h864884 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295; - 5'd28: thin_address__h864886 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h864886 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h864886 = csrf_mScratchC_reg[151:86]; - default: thin_address__h864886 = + 5'd28: thin_address__h864884 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h864884 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h864884 = csrf_mScratchC_reg[151:86]; + default: thin_address__h864884 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447; endcase end @@ -46521,289 +46521,289 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h906783 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h906783 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h906783 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h906783 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h906786 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h906786 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h906786 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h906786 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h906783 = + thin_address__h906786 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16295; - 5'd28: thin_address__h906783 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h906783 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h906783 = csrf_mScratchC_reg[151:86]; - default: thin_address__h906783 = + 5'd28: thin_address__h906786 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h906786 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h906786 = csrf_mScratchC_reg[151:86]; + default: thin_address__h906786 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16447; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h855607 or - frm_csr__read__h855618 or - fcsr_csr__read__h855632 or - sstatus_csr__read__h855828 or - sie_csr__read__h855898 or + fflags_csr__read__h855605 or + frm_csr__read__h855616 or + fcsr_csr__read__h855630 or + sstatus_csr__read__h855826 or + sie_csr__read__h855896 or SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 or - scounteren_csr__read__h855986 or + scounteren_csr__read__h855984 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 or - scause_csr__read__h856126 or + scause_csr__read__h856124 or csrf_stval_csr or - sip_csr__read__h856266 or - satp_csr__read__h856329 or - mstatus_csr__read__h856475 or - medeleg_csr__read__h856636 or - mideleg_csr__read__h856734 or - mie_csr__read__h856861 or + sip_csr__read__h856264 or + satp_csr__read__h856327 or + mstatus_csr__read__h856473 or + medeleg_csr__read__h856634 or + mideleg_csr__read__h856732 or + mie_csr__read__h856859 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 or - mcounteren_csr__read__h857033 or + mcounteren_csr__read__h857031 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 or - mcause_csr__read__h857299 or + mcause_csr__read__h857297 or csrf_mtval_csr or - mip_csr__read__h857538 or + mip_csr__read__h857536 or csrf_rg_tselect or - rg_tdata1__read__h858639 or + rg_tdata1__read__h858637 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855737 or + x_reg_ifc__read__h855735 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h904216 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h904219 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1031505 = fflags_csr__read__h855607; - 12'd2: data_out__h1031505 = frm_csr__read__h855618; - 12'd3: data_out__h1031505 = fcsr_csr__read__h855632; - 12'd256: data_out__h1031505 = sstatus_csr__read__h855828; - 12'd260: data_out__h1031505 = sie_csr__read__h855898; + 12'd1: data_out__h1031509 = fflags_csr__read__h855605; + 12'd2: data_out__h1031509 = frm_csr__read__h855616; + 12'd3: data_out__h1031509 = fcsr_csr__read__h855630; + 12'd256: data_out__h1031509 = sstatus_csr__read__h855826; + 12'd260: data_out__h1031509 = sie_csr__read__h855896; 12'd261: - data_out__h1031505 = + data_out__h1031509 = SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261; - 12'd262: data_out__h1031505 = scounteren_csr__read__h855986; - 12'd320: data_out__h1031505 = csrf_sscratch_csr; + 12'd262: data_out__h1031509 = scounteren_csr__read__h855984; + 12'd320: data_out__h1031509 = csrf_sscratch_csr; 12'd321: - data_out__h1031505 = + data_out__h1031509 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300; - 12'd322: data_out__h1031505 = scause_csr__read__h856126; - 12'd323: data_out__h1031505 = csrf_stval_csr; - 12'd324: data_out__h1031505 = sip_csr__read__h856266; - 12'd384: data_out__h1031505 = satp_csr__read__h856329; - 12'd768: data_out__h1031505 = mstatus_csr__read__h856475; - 12'd769: data_out__h1031505 = 64'h800000000014112D; - 12'd770: data_out__h1031505 = medeleg_csr__read__h856636; - 12'd771: data_out__h1031505 = mideleg_csr__read__h856734; - 12'd772: data_out__h1031505 = mie_csr__read__h856861; + 12'd322: data_out__h1031509 = scause_csr__read__h856124; + 12'd323: data_out__h1031509 = csrf_stval_csr; + 12'd324: data_out__h1031509 = sip_csr__read__h856264; + 12'd384: data_out__h1031509 = satp_csr__read__h856327; + 12'd768: data_out__h1031509 = mstatus_csr__read__h856473; + 12'd769: data_out__h1031509 = 64'h800000000014112D; + 12'd770: data_out__h1031509 = medeleg_csr__read__h856634; + 12'd771: data_out__h1031509 = mideleg_csr__read__h856732; + 12'd772: data_out__h1031509 = mie_csr__read__h856859; 12'd773: - data_out__h1031505 = + data_out__h1031509 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413; - 12'd774: data_out__h1031505 = mcounteren_csr__read__h857033; - 12'd832: data_out__h1031505 = csrf_mscratch_csr; + 12'd774: data_out__h1031509 = mcounteren_csr__read__h857031; + 12'd832: data_out__h1031509 = csrf_mscratch_csr; 12'd833: - data_out__h1031505 = + data_out__h1031509 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452; - 12'd834: data_out__h1031505 = mcause_csr__read__h857299; - 12'd835: data_out__h1031505 = csrf_mtval_csr; - 12'd836: data_out__h1031505 = mip_csr__read__h857538; - 12'd1952: data_out__h1031505 = csrf_rg_tselect; - 12'd1953: data_out__h1031505 = rg_tdata1__read__h858639; - 12'd1954: data_out__h1031505 = csrf_rg_tdata2; - 12'd1955: data_out__h1031505 = csrf_rg_tdata3; - 12'd1968: data_out__h1031505 = csrf_rg_dcsr; + 12'd834: data_out__h1031509 = mcause_csr__read__h857297; + 12'd835: data_out__h1031509 = csrf_mtval_csr; + 12'd836: data_out__h1031509 = mip_csr__read__h857536; + 12'd1952: data_out__h1031509 = csrf_rg_tselect; + 12'd1953: data_out__h1031509 = rg_tdata1__read__h858637; + 12'd1954: data_out__h1031509 = csrf_rg_tdata2; + 12'd1955: data_out__h1031509 = csrf_rg_tdata3; + 12'd1968: data_out__h1031509 = csrf_rg_dcsr; 12'd1969: - data_out__h1031505 = + data_out__h1031509 = SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558; - 12'd1970: data_out__h1031505 = csrf_rg_dscratch0; - 12'd1971: data_out__h1031505 = csrf_rg_dscratch1; + 12'd1970: data_out__h1031509 = csrf_rg_dscratch0; + 12'd1971: data_out__h1031509 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1031505 = 64'd0; - 12'd2049: data_out__h1031505 = x_reg_ifc__read__h855737; - 12'd2816, 12'd3072: data_out__h1031505 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1031505 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1031505 = { 48'd0, x__h904216 }; - 12'd3073: data_out__h1031505 = csrf_time_reg; - default: data_out__h1031505 = 64'b0; + data_out__h1031509 = 64'd0; + 12'd2049: data_out__h1031509 = x_reg_ifc__read__h855735; + 12'd2816, 12'd3072: data_out__h1031509 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1031509 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1031509 = { 48'd0, x__h904219 }; + 12'd3073: data_out__h1031509 = csrf_time_reg; + default: data_out__h1031509 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h855607 or - frm_csr__read__h855618 or - fcsr_csr__read__h855632 or - sstatus_csr__read__h855828 or - sie_csr__read__h855898 or + fflags_csr__read__h855605 or + frm_csr__read__h855616 or + fcsr_csr__read__h855630 or + sstatus_csr__read__h855826 or + sie_csr__read__h855896 or SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 or - scounteren_csr__read__h855986 or + scounteren_csr__read__h855984 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 or - scause_csr__read__h856126 or + scause_csr__read__h856124 or csrf_stval_csr or - sip_csr__read__h856266 or - satp_csr__read__h856329 or - mstatus_csr__read__h856475 or - medeleg_csr__read__h856636 or - mideleg_csr__read__h856734 or - mie_csr__read__h856861 or + sip_csr__read__h856264 or + satp_csr__read__h856327 or + mstatus_csr__read__h856473 or + medeleg_csr__read__h856634 or + mideleg_csr__read__h856732 or + mie_csr__read__h856859 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 or - mcounteren_csr__read__h857033 or + mcounteren_csr__read__h857031 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 or - mcause_csr__read__h857299 or + mcause_csr__read__h857297 or csrf_mtval_csr or - mip_csr__read__h857538 or + mip_csr__read__h857536 or csrf_rg_tselect or - rg_tdata1__read__h858639 or + rg_tdata1__read__h858637 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855737 or + x_reg_ifc__read__h855735 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h904216 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h904219 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h850288 = fflags_csr__read__h855607; - 12'd2: addr__h850288 = frm_csr__read__h855618; - 12'd3: addr__h850288 = fcsr_csr__read__h855632; - 12'd256: addr__h850288 = sstatus_csr__read__h855828; - 12'd260: addr__h850288 = sie_csr__read__h855898; + 12'd1: addr__h850287 = fflags_csr__read__h855605; + 12'd2: addr__h850287 = frm_csr__read__h855616; + 12'd3: addr__h850287 = fcsr_csr__read__h855630; + 12'd256: addr__h850287 = sstatus_csr__read__h855826; + 12'd260: addr__h850287 = sie_csr__read__h855896; 12'd261: - addr__h850288 = + addr__h850287 = SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261; - 12'd262: addr__h850288 = scounteren_csr__read__h855986; - 12'd320: addr__h850288 = csrf_sscratch_csr; + 12'd262: addr__h850287 = scounteren_csr__read__h855984; + 12'd320: addr__h850287 = csrf_sscratch_csr; 12'd321: - addr__h850288 = + addr__h850287 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300; - 12'd322: addr__h850288 = scause_csr__read__h856126; - 12'd323: addr__h850288 = csrf_stval_csr; - 12'd324: addr__h850288 = sip_csr__read__h856266; - 12'd384: addr__h850288 = satp_csr__read__h856329; - 12'd768: addr__h850288 = mstatus_csr__read__h856475; - 12'd769: addr__h850288 = 64'h800000000014112D; - 12'd770: addr__h850288 = medeleg_csr__read__h856636; - 12'd771: addr__h850288 = mideleg_csr__read__h856734; - 12'd772: addr__h850288 = mie_csr__read__h856861; + 12'd322: addr__h850287 = scause_csr__read__h856124; + 12'd323: addr__h850287 = csrf_stval_csr; + 12'd324: addr__h850287 = sip_csr__read__h856264; + 12'd384: addr__h850287 = satp_csr__read__h856327; + 12'd768: addr__h850287 = mstatus_csr__read__h856473; + 12'd769: addr__h850287 = 64'h800000000014112D; + 12'd770: addr__h850287 = medeleg_csr__read__h856634; + 12'd771: addr__h850287 = mideleg_csr__read__h856732; + 12'd772: addr__h850287 = mie_csr__read__h856859; 12'd773: - addr__h850288 = + addr__h850287 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413; - 12'd774: addr__h850288 = mcounteren_csr__read__h857033; - 12'd832: addr__h850288 = csrf_mscratch_csr; + 12'd774: addr__h850287 = mcounteren_csr__read__h857031; + 12'd832: addr__h850287 = csrf_mscratch_csr; 12'd833: - addr__h850288 = + addr__h850287 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452; - 12'd834: addr__h850288 = mcause_csr__read__h857299; - 12'd835: addr__h850288 = csrf_mtval_csr; - 12'd836: addr__h850288 = mip_csr__read__h857538; - 12'd1952: addr__h850288 = csrf_rg_tselect; - 12'd1953: addr__h850288 = rg_tdata1__read__h858639; - 12'd1954: addr__h850288 = csrf_rg_tdata2; - 12'd1955: addr__h850288 = csrf_rg_tdata3; - 12'd1968: addr__h850288 = csrf_rg_dcsr; + 12'd834: addr__h850287 = mcause_csr__read__h857297; + 12'd835: addr__h850287 = csrf_mtval_csr; + 12'd836: addr__h850287 = mip_csr__read__h857536; + 12'd1952: addr__h850287 = csrf_rg_tselect; + 12'd1953: addr__h850287 = rg_tdata1__read__h858637; + 12'd1954: addr__h850287 = csrf_rg_tdata2; + 12'd1955: addr__h850287 = csrf_rg_tdata3; + 12'd1968: addr__h850287 = csrf_rg_dcsr; 12'd1969: - addr__h850288 = + addr__h850287 = SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558; - 12'd1970: addr__h850288 = csrf_rg_dscratch0; - 12'd1971: addr__h850288 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h850288 = 64'd0; - 12'd2049: addr__h850288 = x_reg_ifc__read__h855737; - 12'd2816, 12'd3072: addr__h850288 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h850288 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h850288 = { 48'd0, x__h904216 }; - 12'd3073: addr__h850288 = csrf_time_reg; - default: addr__h850288 = 64'b0; + 12'd1970: addr__h850287 = csrf_rg_dscratch0; + 12'd1971: addr__h850287 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h850287 = 64'd0; + 12'd2049: addr__h850287 = x_reg_ifc__read__h855735; + 12'd2816, 12'd3072: addr__h850287 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h850287 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h850287 = { 48'd0, x__h904219 }; + 12'd3073: addr__h850287 = csrf_time_reg; + default: addr__h850287 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h855607 or - frm_csr__read__h855618 or - fcsr_csr__read__h855632 or - sstatus_csr__read__h855828 or - sie_csr__read__h855898 or + fflags_csr__read__h855605 or + frm_csr__read__h855616 or + fcsr_csr__read__h855630 or + sstatus_csr__read__h855826 or + sie_csr__read__h855896 or SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261 or - scounteren_csr__read__h855986 or + scounteren_csr__read__h855984 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300 or - scause_csr__read__h856126 or + scause_csr__read__h856124 or csrf_stval_csr or - sip_csr__read__h856266 or - satp_csr__read__h856329 or - mstatus_csr__read__h856475 or - medeleg_csr__read__h856636 or - mideleg_csr__read__h856734 or - mie_csr__read__h856861 or + sip_csr__read__h856264 or + satp_csr__read__h856327 or + mstatus_csr__read__h856473 or + medeleg_csr__read__h856634 or + mideleg_csr__read__h856732 or + mie_csr__read__h856859 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413 or - mcounteren_csr__read__h857033 or + mcounteren_csr__read__h857031 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452 or - mcause_csr__read__h857299 or + mcause_csr__read__h857297 or csrf_mtval_csr or - mip_csr__read__h857538 or + mip_csr__read__h857536 or csrf_rg_tselect or - rg_tdata1__read__h858639 or + rg_tdata1__read__h858637 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h855737 or + x_reg_ifc__read__h855735 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h904216 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h904219 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h895060 = fflags_csr__read__h855607; - 12'd2: addr__h895060 = frm_csr__read__h855618; - 12'd3: addr__h895060 = fcsr_csr__read__h855632; - 12'd256: addr__h895060 = sstatus_csr__read__h855828; - 12'd260: addr__h895060 = sie_csr__read__h855898; + 12'd1: addr__h895062 = fflags_csr__read__h855605; + 12'd2: addr__h895062 = frm_csr__read__h855616; + 12'd3: addr__h895062 = fcsr_csr__read__h855630; + 12'd256: addr__h895062 = sstatus_csr__read__h855826; + 12'd260: addr__h895062 = sie_csr__read__h855896; 12'd261: - addr__h895060 = + addr__h895062 = SEXT__0_CONCAT_csrf_stcc_reg_read__6237_BITS_8_ETC___d16261; - 12'd262: addr__h895060 = scounteren_csr__read__h855986; - 12'd320: addr__h895060 = csrf_sscratch_csr; + 12'd262: addr__h895062 = scounteren_csr__read__h855984; + 12'd320: addr__h895062 = csrf_sscratch_csr; 12'd321: - addr__h895060 = + addr__h895062 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16300; - 12'd322: addr__h895060 = scause_csr__read__h856126; - 12'd323: addr__h895060 = csrf_stval_csr; - 12'd324: addr__h895060 = sip_csr__read__h856266; - 12'd384: addr__h895060 = satp_csr__read__h856329; - 12'd768: addr__h895060 = mstatus_csr__read__h856475; - 12'd769: addr__h895060 = 64'h800000000014112D; - 12'd770: addr__h895060 = medeleg_csr__read__h856636; - 12'd771: addr__h895060 = mideleg_csr__read__h856734; - 12'd772: addr__h895060 = mie_csr__read__h856861; + 12'd322: addr__h895062 = scause_csr__read__h856124; + 12'd323: addr__h895062 = csrf_stval_csr; + 12'd324: addr__h895062 = sip_csr__read__h856264; + 12'd384: addr__h895062 = satp_csr__read__h856327; + 12'd768: addr__h895062 = mstatus_csr__read__h856473; + 12'd769: addr__h895062 = 64'h800000000014112D; + 12'd770: addr__h895062 = medeleg_csr__read__h856634; + 12'd771: addr__h895062 = mideleg_csr__read__h856732; + 12'd772: addr__h895062 = mie_csr__read__h856859; 12'd773: - addr__h895060 = + addr__h895062 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6389_BITS_8_ETC___d16413; - 12'd774: addr__h895060 = mcounteren_csr__read__h857033; - 12'd832: addr__h895060 = csrf_mscratch_csr; + 12'd774: addr__h895062 = mcounteren_csr__read__h857031; + 12'd832: addr__h895062 = csrf_mscratch_csr; 12'd833: - addr__h895060 = + addr__h895062 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16452; - 12'd834: addr__h895060 = mcause_csr__read__h857299; - 12'd835: addr__h895060 = csrf_mtval_csr; - 12'd836: addr__h895060 = mip_csr__read__h857538; - 12'd1952: addr__h895060 = csrf_rg_tselect; - 12'd1953: addr__h895060 = rg_tdata1__read__h858639; - 12'd1954: addr__h895060 = csrf_rg_tdata2; - 12'd1955: addr__h895060 = csrf_rg_tdata3; - 12'd1968: addr__h895060 = csrf_rg_dcsr; + 12'd834: addr__h895062 = mcause_csr__read__h857297; + 12'd835: addr__h895062 = csrf_mtval_csr; + 12'd836: addr__h895062 = mip_csr__read__h857536; + 12'd1952: addr__h895062 = csrf_rg_tselect; + 12'd1953: addr__h895062 = rg_tdata1__read__h858637; + 12'd1954: addr__h895062 = csrf_rg_tdata2; + 12'd1955: addr__h895062 = csrf_rg_tdata3; + 12'd1968: addr__h895062 = csrf_rg_dcsr; 12'd1969: - addr__h895060 = + addr__h895062 = SEXT__0_CONCAT_csrf_rg_dpc_read__6534_BITS_85__ETC___d16558; - 12'd1970: addr__h895060 = csrf_rg_dscratch0; - 12'd1971: addr__h895060 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h895060 = 64'd0; - 12'd2049: addr__h895060 = x_reg_ifc__read__h855737; - 12'd2816, 12'd3072: addr__h895060 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h895060 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h895060 = { 48'd0, x__h904216 }; - 12'd3073: addr__h895060 = csrf_time_reg; - default: addr__h895060 = 64'b0; + 12'd1970: addr__h895062 = csrf_rg_dscratch0; + 12'd1971: addr__h895062 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h895062 = 64'd0; + 12'd2049: addr__h895062 = x_reg_ifc__read__h855735; + 12'd2816, 12'd3072: addr__h895062 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h895062 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h895062 = { 48'd0, x__h904219 }; + 12'd3073: addr__h895062 = csrf_time_reg; + default: addr__h895062 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -47386,17 +47386,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h864890 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h864890 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h864890 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h864890 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h864888 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h864888 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h864888 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h864888 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h864890 = + thin_reserved__h864888 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17359; - 5'd28: thin_reserved__h864890 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h864890 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h864890 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h864890 = + 5'd28: thin_reserved__h864888 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h864888 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h864888 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h864888 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17365; endcase end @@ -47410,17 +47410,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h906787 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h906787 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h906787 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h906787 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h906790 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h906790 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h906790 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h906790 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h906787 = + thin_reserved__h906790 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17359; - 5'd28: thin_reserved__h906787 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h906787 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h906787 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h906787 = + 5'd28: thin_reserved__h906790 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h906790 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h906790 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h906790 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17365; endcase end @@ -47434,17 +47434,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h865126 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h865126 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h865126 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h865126 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h865124 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h865124 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h865124 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h865124 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h865126 = + thin_perms_soft__h865124 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17045; - 5'd28: thin_perms_soft__h865126 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h865126 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h865126 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h865126 = + 5'd28: thin_perms_soft__h865124 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h865124 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h865124 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h865124 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17051; endcase end @@ -47458,17 +47458,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h906963 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h906963 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h906963 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h906963 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h906966 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h906966 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h906966 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h906966 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h906963 = + thin_perms_soft__h906966 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17045; - 5'd28: thin_perms_soft__h906963 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h906963 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h906963 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h906963 = + 5'd28: thin_perms_soft__h906966 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h906966 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h906966 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h906966 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17051; endcase end @@ -47482,17 +47482,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h866834 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h866834 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h866834 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h866834 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h866832 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h866832 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h866832 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h866832 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h866834 = + thin_bounds_topBits__h866832 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17468; - 5'd28: thin_bounds_topBits__h866834 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h866834 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h866834 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h866834 = + 5'd28: thin_bounds_topBits__h866832 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h866832 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h866832 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h866832 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17474; endcase end @@ -47506,17 +47506,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h908189 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h908189 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h908189 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h908189 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h908192 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h908192 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h908192 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h908192 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h908189 = + thin_bounds_topBits__h908192 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17468; - 5'd28: thin_bounds_topBits__h908189 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h908189 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h908189 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h908189 = + 5'd28: thin_bounds_topBits__h908192 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h908192 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h908192 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h908192 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17474; endcase end @@ -48100,17 +48100,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h864891 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h864891 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h864891 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h864891 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h864889 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h864889 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h864889 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h864889 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h864891 = + thin_otype__h864889 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17381; - 5'd28: thin_otype__h864891 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h864891 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h864891 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h864891 = + 5'd28: thin_otype__h864889 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h864889 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h864889 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h864889 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17387; endcase end @@ -48124,17 +48124,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h906788 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h906788 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h906788 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h906788 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h906791 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h906791 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h906791 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h906791 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h906788 = + thin_otype__h906791 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17381; - 5'd28: thin_otype__h906788 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h906788 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h906788 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h906788 = + 5'd28: thin_otype__h906791 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h906791 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h906791 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h906791 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17387; endcase end @@ -54538,7 +54538,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - next_pc__h1023267[63:0] != address__h1023320) + next_pc__h1023271[63:0] != address__h1023324) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && @@ -54940,8 +54940,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[729] && - (x__h873778 != coreFix_aluExe_1_regToExeQ$first[177:49] || - coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874032)) + (x__h873776 != coreFix_aluExe_1_regToExeQ$first[177:49] || + coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874030)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && @@ -54951,8 +54951,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[716] && - (x__h873778 != coreFix_aluExe_1_regToExeQ$first[177:49] || - coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874032)) + (x__h873776 != coreFix_aluExe_1_regToExeQ$first[177:49] || + coreFix_aluExe_1_regToExeQ$first[177:49] != y__h874030)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -54967,8 +54967,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[729] && - (x__h914818 != coreFix_aluExe_0_regToExeQ$first[177:49] || - coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915072)) + (x__h914821 != coreFix_aluExe_0_regToExeQ$first[177:49] || + coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915075)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -54978,8 +54978,8 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[716] && - (x__h914818 != coreFix_aluExe_0_regToExeQ$first[177:49] || - coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915072)) + (x__h914821 != coreFix_aluExe_0_regToExeQ$first[177:49] || + coreFix_aluExe_0_regToExeQ$first[177:49] != y__h915075)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -57527,17 +57527,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h257362); + $write("'h%h", value__h257364); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h257526); + $write("'h%h", value__h257528); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h257638[64:0]); + $write("'h%h", x__h257640[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -64477,14 +64477,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h215836 = $time; + v__h215837 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h215836, "[doRespLdMem]", " "); + $write("%t : ", v__h215837, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h215264); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h215265); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -64628,15 +64628,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h218172 = $time; + v__h218173 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h218172, "[doRespLdForward]", " "); + $write("%t : ", v__h218173, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h217617); + $write("'h%h", t__h217618); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -64805,14 +64805,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5614) begin - v__h275404 = $time; + v__h275405 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5614) - $write("%t : [Ld resp] ", v__h275404); + $write("%t : [Ld resp] ", v__h275405); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -66502,13 +66502,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618) begin - v__h351162 = $time; + v__h351163 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618) - $write("%t : [Ld resp] ", v__h351162); + $write("%t : [Ld resp] ", v__h351163); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5618) @@ -68408,7 +68408,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h427778 = $time; + v__h427779 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -68416,7 +68416,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h427778); + $write("%t : [Ld resp] ", v__h427779); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -70925,17 +70925,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h242584); + $write("'h%h", value__h242586); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h242748); + $write("'h%h", value__h242750); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h242860[64:0]); + $write("'h%h", x__h242862[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -70975,17 +70975,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h243741); + $write("'h%h", value__h243743); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h243905); + $write("'h%h", value__h243907); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h244017[64:0]); + $write("'h%h", x__h244019[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v index 6dbb899..e248e12 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:59:39 BST 2020 +// On Mon Jul 6 19:13:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v index 5f7e3f6..dfeb90c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:17 BST 2020 +// On Mon Jul 6 19:09:22 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v index de04d2b..f1730d5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:02 BST 2020 +// On Mon Jul 6 19:02:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v index 4d44422..d2ab724 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:01 BST 2020 +// On Mon Jul 6 19:02:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v b/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v index 444d6a6..493bb82 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:16 BST 2020 +// On Mon Jul 6 19:02:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v index 3feaf09..2d4cfe4 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:19 BST 2020 +// On Mon Jul 6 19:09:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v index 8596d13..db0c6bc 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:21 BST 2020 +// On Mon Jul 6 19:09:25 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v index 95aff0b..a13af18 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:52 BST 2020 +// On Mon Jul 6 19:09:56 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v b/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v index 9678620..d817800 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:18 BST 2020 +// On Mon Jul 6 19:02:20 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v b/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v index 9cdb473..5e4b68f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:07 BST 2020 +// On Mon Jul 6 19:11:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v index ffae0f1..089977d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:56:11 BST 2020 +// On Mon Jul 6 19:11:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v index 2063461..4f2c8ac 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:51 BST 2020 +// On Mon Jul 6 19:10:55 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v index c6f37eb..a05449d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:57 BST 2020 +// On Mon Jul 6 19:11:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v index 335ada7..e097a60 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:54 BST 2020 +// On Mon Jul 6 19:10:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v b/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v index 19a59af..bf745e3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:48:09 BST 2020 +// On Mon Jul 6 19:03:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v b/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v index 2cd156a..4b7f2cf 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:59 BST 2020 +// On Mon Jul 6 19:03:00 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v b/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v index 650b318..4e290b8 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:21 BST 2020 +// On Mon Jul 6 19:11:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v index a0294d2..af63e05 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:59 BST 2020 +// On Mon Jul 6 19:11:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v index 9b18969..c6b3d8a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:56:13 BST 2020 +// On Mon Jul 6 19:11:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v index b2a741a..bb0e94c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:56:13 BST 2020 +// On Mon Jul 6 19:11:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v index f7e78f1..1984b9e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:05 BST 2020 +// On Mon Jul 6 19:11:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v index e367b0e..a4085e4 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:05 BST 2020 +// On Mon Jul 6 19:11:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v index ac11bd2..2b6d65e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:05 BST 2020 +// On Mon Jul 6 19:11:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v b/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v index 69631c0..81b5a69 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:05 BST 2020 +// On Mon Jul 6 19:11:20 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v index 81a752e..383dec3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:28 BST 2020 +// On Mon Jul 6 19:09:32 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v index 8d5a576..db781e6 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:22 BST 2020 +// On Mon Jul 6 19:09:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v index a679ab4..2fb62b3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:28 BST 2020 +// On Mon Jul 6 19:09:32 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v b/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v index 54718f5..036cd34 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:23 BST 2020 +// On Mon Jul 6 19:09:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v index 7ee3c7c..ab3dc7c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:25 BST 2020 +// On Mon Jul 6 19:09:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v b/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v index 17dc57e..4508292 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:57 BST 2020 +// On Mon Jul 6 19:02:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v b/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v index 53fefb0..3b6affd 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:53:54 BST 2020 +// On Mon Jul 6 19:08:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v index e7f1a8e..1baab23 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:44 BST 2020 +// On Mon Jul 6 19:10:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v b/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v index 7c8fd14..e5f07b7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:32 BST 2020 +// On Mon Jul 6 19:10:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v index e779417..c62a990 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:52:16 BST 2020 +// On Mon Jul 6 19:07:18 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v b/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v index 0596d0e..2c92541 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:24 BST 2020 +// On Mon Jul 6 19:10:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v b/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v index 05d31d3..1d3e92c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:47 BST 2020 +// On Mon Jul 6 19:02:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v index dd7ae37..9519fc2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:42 BST 2020 +// On Mon Jul 6 19:09:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v index 9db7b9a..221742a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:00 BST 2020 +// On Mon Jul 6 19:10:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v b/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v index 7c0b8d3..a8a12b5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:54:42 BST 2020 +// On Mon Jul 6 19:09:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v index 0fef041..13fcc4b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:59 BST 2020 +// On Mon Jul 6 19:11:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v index 23663b2..80e194b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:56:11 BST 2020 +// On Mon Jul 6 19:11:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v index 4953d38..c8ae65c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:41 BST 2020 +// On Mon Jul 6 19:02:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v index 620572c..88588cc 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:59:48 BST 2020 +// On Mon Jul 6 19:14:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v b/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v index aae427d..b1dc692 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:10 BST 2020 +// On Mon Jul 6 19:02:13 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v index 40ed958..1ad5fe5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkProc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:59:27 BST 2020 +// On Mon Jul 6 19:13:43 BST 2020 // // // Ports: @@ -1948,46 +1948,46 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h224877; - reg [31 : 0] v__h224429; + reg [31 : 0] v__h227014; + reg [31 : 0] v__h226566; reg [31 : 0] v__h9702; reg [31 : 0] v__h9897; reg [31 : 0] v__h11245; reg [31 : 0] v__h17177; - reg [31 : 0] v__h17348; - reg [31 : 0] v__h17740; - reg [31 : 0] v__h18150; + reg [31 : 0] v__h17357; + reg [31 : 0] v__h17749; + reg [31 : 0] v__h18159; reg [31 : 0] v__h2280; reg [31 : 0] v__h7388; - reg [31 : 0] v__h20462; - reg [31 : 0] v__h21008; - reg [31 : 0] v__h21530; - reg [31 : 0] v__h202080; - reg [31 : 0] v__h215789; - reg [31 : 0] v__h194057; - reg [31 : 0] v__h223415; - reg [31 : 0] v__h194646; - reg [31 : 0] v__h194832; + reg [31 : 0] v__h20472; + reg [31 : 0] v__h21018; + reg [31 : 0] v__h21540; + reg [31 : 0] v__h204166; + reg [31 : 0] v__h217884; + reg [31 : 0] v__h194067; + reg [31 : 0] v__h225552; + reg [31 : 0] v__h194656; + reg [31 : 0] v__h194842; reg [31 : 0] v__h2274; reg [31 : 0] v__h7382; reg [31 : 0] v__h9696; reg [31 : 0] v__h9891; reg [31 : 0] v__h11239; reg [31 : 0] v__h17171; - reg [31 : 0] v__h17342; - reg [31 : 0] v__h17734; - reg [31 : 0] v__h18144; - reg [31 : 0] v__h20456; - reg [31 : 0] v__h21002; - reg [31 : 0] v__h21524; - reg [31 : 0] v__h194051; - reg [31 : 0] v__h194640; - reg [31 : 0] v__h194826; - reg [31 : 0] v__h202074; - reg [31 : 0] v__h215783; - reg [31 : 0] v__h223409; - reg [31 : 0] v__h224423; - reg [31 : 0] v__h224871; + reg [31 : 0] v__h17351; + reg [31 : 0] v__h17743; + reg [31 : 0] v__h18153; + reg [31 : 0] v__h20466; + reg [31 : 0] v__h21012; + reg [31 : 0] v__h21534; + reg [31 : 0] v__h194061; + reg [31 : 0] v__h194650; + reg [31 : 0] v__h194836; + reg [31 : 0] v__h204160; + reg [31 : 0] v__h217878; + reg [31 : 0] v__h225546; + reg [31 : 0] v__h226560; + reg [31 : 0] v__h227008; // synopsys translate_on // remaining internal signals @@ -1995,121 +1995,121 @@ module mkProc(CLK, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4, - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986, - dword__h150959, - ld_data__h188873, - v_wdata__h216097, - wflit_wdata__h17678; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391; - reg [7 : 0] v_wstrb__h216098, wflit_wstrb__h17679; - reg [5 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844; - reg [2 : 0] x__h101188; - reg [1 : 0] CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, - CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, + CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988, + dword__h150969, + ld_data__h188883, + v_wdata__h218243, + wflit_wdata__h17687; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393; + reg [7 : 0] v_wstrb__h218244, wflit_wstrb__h17688; + reg [5 : 0] IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846; + reg [2 : 0] x__h101198; + reg [1 : 0] CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9, - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1484, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1721, - v_wuser__h216100, - x__h101189, - x__h128009; - wire [583 : 0] IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1692; - wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1841; - wire [517 : 0] IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1691; - wire [515 : 0] IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1683, - IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1836; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2034, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1818; - wire [129 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1167; - wire [128 : 0] amoExec___d1006, - amoExec___d1076, - amoExec___d1132, - amoExec___d1361, - amoExec___d920, + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1486, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1723, + v_wuser__h218246, + x__h101199, + x__h128019; + wire [583 : 0] IF_enqDst_1_0_lat_1_whas__647_THEN_enqDst_1_0__ETC___d1694; + wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1843; + wire [517 : 0] IF_enqDst_1_0_lat_1_whas__647_THEN_enqDst_1_0__ETC___d1693; + wire [515 : 0] IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1685, + IF_llc_axi4_adapter_rg_rd_rsp_beat_275_BIT_0_3_ETC___d2307, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1838; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2036, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1820; + wire [129 : 0] IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1169; + wire [128 : 0] amoExec___d1008, + amoExec___d1078, + amoExec___d1134, + amoExec___d1363, + amoExec___d922, mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1784, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1801, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1835; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1786, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1803, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1837; wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34, llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32; wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33; wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31; - wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546, - IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544; - wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__298_BI_ETC___d1399; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1663, - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1162, - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1160, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918, - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054, - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982, - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106, - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1577, - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1615, - addr1__h90765, - data__h141232, - failed_testnum__h224472, - line_addr__h140665, - line_addr__h150776, - line_addr__h194193, - mmioPlatform_mtime__h59831, - newData__h45219, - newData__h53320, - v_awaddr__h215686, - value__h61538, - x__h48532, - x__h56610, - x__h64538, - x__h68539, - x__h71213, - x__h73754, - x__h79393; - wire [47 : 0] IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1148, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947; - wire [31 : 0] IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1143, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938, - IF_mmioPlatform_fetchingWay_370_THEN_mmioPlatf_ETC___d1396, - amo_req_data__h39114, - lower_data__h44520, + wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548, + IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546; + wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__300_BI_ETC___d1401; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2125; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1665, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1164, + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1162, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108, + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1579, + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1617, + addr1__h90775, + data__h141242, + failed_testnum__h226609, + line_addr__h140675, + line_addr__h150786, + line_addr__h194203, + mmioPlatform_mtime__h59841, + newData__h45229, + newData__h53330, + v_awaddr__h217772, + value__h61548, + x__h48542, + x__h56620, + x__h64548, + x__h68549, + x__h71223, + x__h73764, + x__h79403; + wire [47 : 0] IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1150, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949; + wire [31 : 0] IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1145, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940, + IF_mmioPlatform_fetchingWay_372_THEN_mmioPlatf_ETC___d1398, + amo_req_data__h39124, + lower_data__h44530, mmioPlatform_mtime_BITS_31_TO_0__q8, mmioPlatform_mtime_BITS_63_TO_32__q7, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, - upper_data__h44521, - v__h44376, - v__h44413, - x_data__h42055; - wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__434_THEN__ETC___d1540; - wire [7 : 0] IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905, + upper_data__h44531, + v__h44386, + v__h44423, + x_data__h42065; + wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__436_THEN__ETC___d1542; + wire [7 : 0] IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907, mem_req_rd_addr_arlen__h5411, - mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910; + mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912; wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30; - wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__434_THEN__ETC___d1539, + wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__436_THEN__ETC___d1541, x__h15143, x__h15155, x__h15167, @@ -2140,105 +2140,114 @@ module mkProc(CLK, y__h15288, y__h15300, y__h15312; - wire [3 : 0] b__h193993, b__h2174, mmioPlatform_reqAmofunc__h88535; - wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1759, - _theResult_____1_awsize_val__h17116; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1668, - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1582, - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1620; - wire IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962, - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818, - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957, - IF_enqDst_0_lat_0_whas__449_THEN_enqDst_0_lat__ETC___d1454, - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1653, - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1673, - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1689, - IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116, - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1157, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1178, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367, - IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883, - IF_mmio_axi4_adapter_f_rsps_to_core_first__298_ETC___d1374, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206, - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1603, - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1641, - IF_propDstIdx_0_lat_0_whas__420_THEN_NOT_propD_ETC___d1486, - IF_propDstIdx_0_lat_0_whas__420_THEN_propDstId_ETC___d1423, - IF_propDstIdx_1_0_lat_0_whas__557_THEN_NOT_pro_ETC___d1723, - IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560, - IF_propDstIdx_1_1_lat_0_whas__564_THEN_propDst_ETC___d1567, - IF_propDstIdx_1_lat_0_whas__427_THEN_propDstId_ETC___d1430, - NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1546, - NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1551, - NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1847, - NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1852, - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259, - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2338, - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2341, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1201, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1296, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1307, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1317, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1365, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1377, - NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1488, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1725, + wire [3 : 0] b__h194003, b__h2174, mmioPlatform_reqAmofunc__h88545; + wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1761, + _theResult_____1_awsize_val__h17116, + x__h195056, + x__h218130; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1670, + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1584, + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1622; + wire IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964, + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820, + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959, + IF_enqDst_0_lat_0_whas__451_THEN_enqDst_0_lat__ETC___d1456, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1655, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1675, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1691, + IF_llc_mem_server_enqDst_0_lat_0_whas__130_THE_ETC___d2135, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__115_ETC___d2118, + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1159, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1180, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369, + IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885, + IF_mmio_axi4_adapter_f_rsps_to_core_first__300_ETC___d1376, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210, + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1605, + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1643, + IF_propDstIdx_0_lat_0_whas__422_THEN_NOT_propD_ETC___d1488, + IF_propDstIdx_0_lat_0_whas__422_THEN_propDstId_ETC___d1425, + IF_propDstIdx_1_0_lat_0_whas__559_THEN_NOT_pro_ETC___d1725, + IF_propDstIdx_1_0_lat_0_whas__559_THEN_propDst_ETC___d1562, + IF_propDstIdx_1_1_lat_0_whas__566_THEN_propDst_ETC___d1569, + IF_propDstIdx_1_lat_0_whas__429_THEN_propDstId_ETC___d1432, + NOT_enqDst_0_rl_454_BIT_73_455_460_AND_SEL_ARR_ETC___d1548, + NOT_enqDst_0_rl_454_BIT_73_455_460_AND_SEL_ARR_ETC___d1553, + NOT_enqDst_1_0_rl_653_BIT_584_654_659_AND_SEL__ETC___d1849, + NOT_enqDst_1_0_rl_653_BIT_584_654_659_AND_SEL__ETC___d1854, + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261, + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2341, + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2344, + NOT_llc_axi4_adapter_rg_wr_req_beat_363_EQ_0_3_ETC___d2377, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1203, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1298, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1309, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1319, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1367, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1379, + NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995, + NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1490, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1727, _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, _theResult____h13492, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788, - core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2270, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951, - mmioPlatform_amoWaitWriteResp_311_OR_core_0_RD_ETC___d1314, - mmioPlatform_cycle_90_ULT_99___d491, - mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379, - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029, - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974, - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253, - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790, + core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2319, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2322, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2327, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2330, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2335, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2338, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2054, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1953, + mmioPlatform_amoWaitWriteResp_313_OR_core_0_RD_ETC___d1316, + mmioPlatform_cycle_92_ULT_99___d493, + mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381, + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031, + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217, + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221, whichHalf___1__h15055, - x__h100988, + x__h100998, x__h10399, - x__h116710, - x__h123274, - x__h17610; + x__h116720, + x__h123284, + x__h17619; // action method start assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; @@ -2976,7 +2985,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && - IF_enqDst_0_lat_0_whas__449_THEN_enqDst_0_lat__ETC___d1454 ; + IF_enqDst_0_lat_0_whas__451_THEN_enqDst_0_lat__ETC___d1456 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -3000,7 +3009,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1653 ; + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1655 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3101,7 +3110,7 @@ module mkProc(CLK, // rule RL_mmio_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 && + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -3141,23 +3150,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_90_ULT_99___d491 ; + mmioPlatform_cycle_92_ULT_99___d493 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_90_ULT_99___d491 ; + !mmioPlatform_cycle_92_ULT_99___d493 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513 && + NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3174,7 +3183,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819 && + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3183,7 +3192,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883 && + IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3229,7 +3238,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h73754 == 64'd0 || + x__h73764 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3247,7 +3256,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1201 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1203 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3255,37 +3264,37 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1296 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1298 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1307 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1309 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - mmioPlatform_amoWaitWriteResp_311_OR_core_0_RD_ETC___d1314 && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1317 ; + mmioPlatform_amoWaitWriteResp_313_OR_core_0_RD_ETC___d1316 && + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1319 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1365 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1367 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__298_ETC___d1374 && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1377 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__300_ETC___d1376 && + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1379 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3399,7 +3408,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__130_THE_ETC___d2135 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3467,7 +3476,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2054 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3479,7 +3488,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1953 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3498,7 +3507,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1953 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3509,7 +3518,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2054 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3522,7 +3531,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1953 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3532,7 +3541,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2054 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3612,10 +3621,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_clearing && llc$RDY_to_mem_toM_first && !llc_axi4_adapter_master_xactor_shim_wff_rv[74] && - (llc_axi4_adapter_rg_wr_req_beat != 3'd0 || - !llc_axi4_adapter_master_xactor_shim_awff_rv[98]) && - (llc_axi4_adapter_rg_wr_req_beat != 3'd7 || - llc$RDY_to_mem_toM_deq) && + NOT_llc_axi4_adapter_rg_wr_req_beat_363_EQ_0_3_ETC___d2377 && llc$to_mem_toM_first[644] ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -3628,7 +3634,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && - b__h193993 == 4'd0 ; + b__h194003 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -3690,7 +3696,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = !llc_axi4_adapter_master_xactor_clearing && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] && - b__h193993 != 4'd0 ; + b__h194003 != 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; @@ -3731,7 +3737,10 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2270 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && + (!llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] || + llc$RDY_to_mem_rsFromM_enq && + llc_axi4_adapter_f_pending_reads$EMPTY_N) ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3744,7 +3753,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 ; + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3752,25 +3761,25 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 || + (!mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || @@ -3800,12 +3809,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && @@ -3834,27 +3843,27 @@ module mkProc(CLK, WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_shim_rff$D_OUT[1] ; assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = + { 1'd0, llc$to_child_toC_first[586:1] } ; + assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd1, llc$to_child_toC_first[586:521], llc$to_child_toC_first[519:0] } ; - assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = - { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amo_req_data__h39114 : - x_data__h42055 } ; + amo_req_data__h39124 : + x_data__h42065 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -3870,16 +3879,16 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 67'h60000000000000000, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 3'd6, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 65'h0AAAAAAAAAAAAAAAA, - mmio_axi4_adapter_f_rsps_to_core_first__298_BI_ETC___d1399 } ; + mmio_axi4_adapter_f_rsps_to_core_first__300_BI_ETC___d1401 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 2'd3, mmioPlatform_amoResp } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = @@ -3888,24 +3897,24 @@ module mkProc(CLK, { 3'd6, mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h44376, 32'd0 }, + { v__h44386, 32'd0 }, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1167 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1169 } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = { llc_mem_server_rg_cacheline_cache_addr, 64'hFFFFFFFFFFFFFFFF, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h140665, + { line_addr__h140675, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h150776, + { line_addr__h150786, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3925,14 +3934,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2034, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2036, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd0) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -3940,21 +3949,21 @@ module mkProc(CLK, { 65'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 } ; + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 } ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = { 1'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056, 64'd0 } ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) ? + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) ? 67'h1AAAAAAAAAAAAAAAA : - ((!core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) ? + ((!core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) ? 67'h2AAAAAAAAAAAAAAAA : - IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546) ; + IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, (mmioPlatform_instSel == 2'd3) ? @@ -3967,11 +3976,11 @@ module mkProc(CLK, mmioPlatform_instSel + 2'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) ? + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_3 = @@ -3982,32 +3991,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 or + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 or + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_5 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_5 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_5 = - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4015,30 +4024,30 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_6 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - (mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 ? + (mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - amoExec___d1361 } ; + amoExec___d1363 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { addr1__h90765, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + { addr1__h90775, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = @@ -4049,47 +4058,47 @@ module mkProc(CLK, 129'd0 } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73754 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73764 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h73754 != 64'd0 ; + x__h73764 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h68539 == 64'd0 ; + x__h68549 == 64'd0 ; assign propDstIdx_1_lat_1$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1488 && - x__h100988 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1490 && + x__h100998 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, - SEL_ARR_IF_propDstData_0_lat_0_whas__434_THEN__ETC___d1540 } ; + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + SEL_ARR_IF_propDstData_0_lat_0_whas__436_THEN__ETC___d1542 } ; assign enqDst_0_lat_0$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1488 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1490 ; assign propDstIdx_1_1_lat_1$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1725 && - x__h123274 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1727 && + x__h123284 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1841 } ; + CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1843 } ; assign enqDst_1_0_lat_0$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1725 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1727 ; assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { debug_module_mem_server_awid, debug_module_mem_server_awaddr, @@ -4128,10 +4137,10 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__115_ETC___d2118 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123 } ; + IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2125 } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = @@ -4163,7 +4172,7 @@ module mkProc(CLK, master0_arready ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = @@ -4236,7 +4245,7 @@ module mkProc(CLK, assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 = { 1'd1, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[97:93], - dword__h150959, + dword__h150969, 4'd2 } ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? @@ -4254,7 +4263,7 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 6'd32, v_awaddr__h215686, 29'd15532032 } ; + { 6'd32, v_awaddr__h217772, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read = llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : @@ -4269,10 +4278,10 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - v_wdata__h216097, - v_wstrb__h216098, + v_wdata__h218243, + v_wstrb__h218244, llc_axi4_adapter_rg_wr_req_beat == 3'd7, - v_wuser__h216100 } ; + v_wuser__h218246 } ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : @@ -4301,7 +4310,7 @@ module mkProc(CLK, 8'd42 : llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 6'd32, line_addr__h194193, 29'd15532032 } ; + { 6'd32, line_addr__h194203, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ? llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : @@ -4335,11 +4344,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h193993 - 4'd1 ; + b__h194003 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h193993 ; + b__h194003 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4351,7 +4360,7 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__449_THEN_enqDst_0_lat__ETC___d1454, + IF_enqDst_0_lat_0_whas__451_THEN_enqDst_0_lat__ETC___d1456, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : (enqDst_0_lat_0$whas ? @@ -4362,8 +4371,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1653, - IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1692 } ; + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1655, + IF_enqDst_1_0_lat_1_whas__647_THEN_enqDst_1_0__ETC___d1694 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4407,19 +4416,23 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ? + 516'd0 : + IF_llc_axi4_adapter_rg_rd_rsp_beat_275_BIT_0_3_ETC___d2307 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; // register llc_axi4_adapter_rg_rd_rsp_beat assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN = - llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ? + 3'd0 : + x__h195056 ; assign llc_axi4_adapter_rg_rd_rsp_beat$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; // register llc_axi4_adapter_rg_wr_req_beat assign llc_axi4_adapter_rg_wr_req_beat$D_IN = - llc_axi4_adapter_rg_wr_req_beat + 3'd1 ; + (llc_axi4_adapter_rg_wr_req_beat == 3'd7) ? 3'd0 : x__h218130 ; assign llc_axi4_adapter_rg_wr_req_beat$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4456,7 +4469,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133, + IF_llc_mem_server_enqDst_0_lat_0_whas__130_THE_ETC___d2135, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4466,20 +4479,20 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2125 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__115_ETC___d2118 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h140665 : - line_addr__h150776 ; + line_addr__h140675 : + line_addr__h150786 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4562,7 +4575,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 ; + mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4575,11 +4588,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 && + mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4589,11 +4602,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 ; + mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4644,16 +4657,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 ; + mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h53320 : + newData__h53330 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4662,7 +4675,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h45219 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h45229 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4672,9 +4685,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4783,7 +4796,7 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = !mmioPlatform_toHostQ_clearReq_rl && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4804,7 +4817,7 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = !mmioPlatform_toHostQ_clearReq_rl && - (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 || + (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl && mmioPlatform_toHostQ_full) ; @@ -4817,7 +4830,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4825,15 +4838,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -4862,7 +4875,7 @@ module mkProc(CLK, !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat && - x__h17610 ; + x__h17619 ; assign mmio_axi4_adapter_rg_wr_req_beat$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr ; @@ -4884,28 +4897,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1577, - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1582, + { IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1579, + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1584, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[517] : propDstData_1_0_rl[517], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516:1] : propDstData_1_0_rl[516:1], - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1603 } ; + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1605 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1615, - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1620, + { IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1617, + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1622, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[517] : propDstData_1_1_rl[517], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516:1] : propDstData_1_1_rl[516:1], - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1641 } ; + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1643 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -4917,26 +4930,26 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = - !NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1546 && - IF_propDstIdx_0_lat_0_whas__420_THEN_propDstId_ETC___d1423 ; + !NOT_enqDst_0_rl_454_BIT_73_455_460_AND_SEL_ARR_ETC___d1548 && + IF_propDstIdx_0_lat_0_whas__422_THEN_propDstId_ETC___d1425 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = - !NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1847 && - IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560 ; + !NOT_enqDst_1_0_rl_653_BIT_584_654_659_AND_SEL__ETC___d1849 && + IF_propDstIdx_1_0_lat_0_whas__559_THEN_propDst_ETC___d1562 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__564_THEN_propDst_ETC___d1567 ; + IF_propDstIdx_1_1_lat_0_whas__566_THEN_propDst_ETC___d1569 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__427_THEN_propDstId_ETC___d1430 ; + IF_propDstIdx_1_lat_0_whas__429_THEN_propDstId_ETC___d1432 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 @@ -4955,7 +4968,7 @@ module mkProc(CLK, assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRs ? + WILL_FIRE_RL_sendPRq ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; assign core_0$hart0_csr_mem_server_request_put = @@ -4967,7 +4980,7 @@ module mkProc(CLK, assign core_0$hart0_run_halt_server_request_put = hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRs_1 ? + WILL_FIRE_RL_sendPRq_1 ? MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or @@ -5055,7 +5068,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h188873, llc$dma_respLd_first[3] } ; + { ld_data__h188883, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5063,11 +5076,11 @@ module mkProc(CLK, assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ; assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ; assign core_0$EN_dCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; + WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ; assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ; assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ; + WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_llc_mem_server_srcPropose ; assign core_0$EN_tlbToMem_respLd_enq = @@ -5078,13 +5091,13 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp || WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 || + (!mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || @@ -5094,15 +5107,15 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_processFromHost ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 || + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5184,13 +5197,13 @@ module mkProc(CLK, enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1663, - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1668, - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1673, - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1683, - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1689 } ; + { IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1665, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1670, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1675, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1685, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1691 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_275_BIT_0_3_ETC___d2307, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5217,7 +5230,7 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc$EN_to_mem_rsFromM_enq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ; assign llc$EN_cRqStuck_get = 1'b0 ; assign llc$EN_perf_setStatus = core_0$RDY_sendDoStats ; assign llc$EN_perf_req = 1'b0 ; @@ -5229,7 +5242,7 @@ module mkProc(CLK, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc_axi4_adapter_f_pending_reads$DEQ = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ; assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ; // submodule llc_mem_server_f_dword_in_line @@ -5344,7 +5357,7 @@ module mkProc(CLK, 18'd65536 } ; assign mmio_axi4_adapter_master_shim_awff$ENQ = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 ; assign mmio_axi4_adapter_master_shim_awff$DEQ = EN_master1_aw_drop ; assign mmio_axi4_adapter_master_shim_awff$CLR = 1'b0 ; @@ -5364,8 +5377,8 @@ module mkProc(CLK, // submodule mmio_axi4_adapter_master_shim_wff assign mmio_axi4_adapter_master_shim_wff$D_IN = - { wflit_wdata__h17678, - wflit_wstrb__h17679, + { wflit_wdata__h17687, + wflit_wstrb__h17688, whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, @@ -5383,41 +5396,41 @@ module mkProc(CLK, assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current({ 65'd0, - value__h61538 }), + value__h61548 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d920)); - module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d922)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current({ 65'd0, - mmioPlatform_mtime__h59831 }), + mmioPlatform_mtime__h59841 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1006)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1008)); + module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current(129'd0), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1076)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1078)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), - .amoExec_current({ 65'd0, x__h79393 }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), + .amoExec_current({ 65'd0, x__h79403 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1132)); - module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88535, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1134)); + module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88545, ((mmioPlatform_reqBE[0] ? 5'd1 : 5'd0) + @@ -5473,294 +5486,294 @@ module mkProc(CLK, .amoExec_wordIdx(mmioPlatform_curReq[3:2]), .amoExec_current(mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0]), .amoExec_inpt(mmioPlatform_reqData), - .amoExec(amoExec___d1361)); - assign IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962 = - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + .amoExec(amoExec___d1363)); + assign IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964 = + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_mtime[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_mtime[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_mtime[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_mtime[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1143 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1145 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_fromHostQ_data_0[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_fromHostQ_data_0[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_fromHostQ_data_0[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1148 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1143, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1150 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1145, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_fromHostQ_data_0[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_mtimecmp_0[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_mtimecmp_0[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_mtimecmp_0[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_mtimecmp_0[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546 = - (!core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) ? + assign IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548 = + (!core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) ? 67'h3AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544) ; - assign IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818 = + IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546) ; + assign IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 = - newData__h45219 <= mmioPlatform_mtime ; - assign IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544 = - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 ? + assign IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 = + newData__h45229 <= mmioPlatform_mtime ; + assign IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546 = + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 ? 67'h5AAAAAAAAAAAAAAAA : - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ? + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ; - assign IF_enqDst_0_lat_0_whas__449_THEN_enqDst_0_lat__ETC___d1454 = + assign IF_enqDst_0_lat_0_whas__451_THEN_enqDst_0_lat__ETC___d1456 = enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1653 = + assign IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1655 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[584] : enqDst_1_0_rl[584] ; - assign IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1663 = + assign IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1665 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[583:520] : enqDst_1_0_rl[583:520] ; - assign IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1668 = + assign IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1670 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[519:518] : enqDst_1_0_rl[519:518] ; - assign IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1673 = + assign IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1675 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[517] : enqDst_1_0_rl[517] ; - assign IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1683 = + assign IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1685 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[516:1] : enqDst_1_0_rl[516:1] ; - assign IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1689 = + assign IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1691 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1691 = + assign IF_enqDst_1_0_lat_1_whas__647_THEN_enqDst_1_0__ETC___d1693 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1673, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1675, CAN_FIRE_RL_doEnq_1 ? 516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1683, - x__h116710 } ; - assign IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1692 = + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1685, + x__h116720 } ; + assign IF_enqDst_1_0_lat_1_whas__647_THEN_enqDst_1_0__ETC___d1694 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1663, + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1665, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1668, - IF_enqDst_1_0_lat_1_whas__645_THEN_enqDst_1_0__ETC___d1691 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_263_BIT_0_2_ETC___d2305 = + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1670, + IF_enqDst_1_0_lat_1_whas__647_THEN_enqDst_1_0__ETC___d1693 } ; + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_275_BIT_0_3_ETC___d2307 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2034 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2036 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd6) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd5) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd4) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[319:256], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd3) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd2) ? - data__h141232 : + data__h141242 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__128_THE_ETC___d2133 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__130_THE_ETC___d2135 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2123 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__12_ETC___d2125 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__115_ETC___d2118 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_fetchingWay_370_THEN_mmioPlatf_ETC___d1396 = + assign IF_mmioPlatform_fetchingWay_372_THEN_mmioPlatf_ETC___d1398 = mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391 ; - assign IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1162 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393 ; + assign IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1164 = (mmioPlatform_fromHostQ_empty || mmioPlatform_fromHostAddr[0]) ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1160 = + assign IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1162 = mmioPlatform_fromHostQ_empty ? 64'd0 : (mmioPlatform_fromHostAddr[0] ? mmioPlatform_fromHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038 = - ((mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + assign IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040 = + ((mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905 = + assign IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 8'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqBE[15:8] : mmioPlatform_reqBE[7:0]) ; - assign IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 = + assign IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 64'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqData[127:64] : mmioPlatform_reqData[63:0]) ; - assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 = + assign IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q7 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q8 } ; - assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 = + assign IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, + { IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102, 1'd0, - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1167 = + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108 } ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1169 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1157, + { IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1159, 1'd0, - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1160, - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1162 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819 = + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1162, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1164 } ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055 = + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982 = + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100 = + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? mmioPlatform_toHostQ_empty : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1157 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1159 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h73754 == 64'd0 : - x__h68539 == 64'd0) : + x__h73764 == 64'd0 : + x__h68549 == 64'd0) : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1178 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1180 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h73754 != 64'd0 : - x__h68539 != 64'd0) : + x__h73764 != 64'd0 : + x__h68549 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; - assign IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106 = + assign IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108 = (mmioPlatform_toHostQ_empty || mmioPlatform_toHostAddr[0]) ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104 = + assign IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106 = mmioPlatform_toHostQ_empty ? 64'd0 : (mmioPlatform_toHostAddr[0] ? mmioPlatform_toHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 = + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883 = + assign IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -5768,94 +5781,97 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__298_ETC___d1374 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__300_ETC___d1376 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 = + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_wff$FULL_N && - (!whichHalf___1__h15055 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && - mmio_axi4_adapter_rg_wr_req_beat || - mmio_axi4_adapter_master_shim_awff$FULL_N) : + NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208 : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1577 = + assign IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1579 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[583:520] : propDstData_1_0_rl[583:520] ; - assign IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1582 = + assign IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1584 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[519:518] : propDstData_1_0_rl[519:518] ; - assign IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1603 = + assign IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1605 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1615 = + assign IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1617 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[583:520] : propDstData_1_1_rl[583:520] ; - assign IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1620 = + assign IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1622 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[519:518] : propDstData_1_1_rl[519:518] ; - assign IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1641 = + assign IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1643 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstIdx_0_lat_0_whas__420_THEN_NOT_propD_ETC___d1486 = + assign IF_propDstIdx_0_lat_0_whas__422_THEN_NOT_propD_ETC___d1488 = !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign IF_propDstIdx_0_lat_0_whas__420_THEN_propDstId_ETC___d1423 = + assign IF_propDstIdx_0_lat_0_whas__422_THEN_propDstId_ETC___d1425 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__557_THEN_NOT_pro_ETC___d1723 = + assign IF_propDstIdx_1_0_lat_0_whas__559_THEN_NOT_pro_ETC___d1725 = !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560 = + assign IF_propDstIdx_1_0_lat_0_whas__559_THEN_propDst_ETC___d1562 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__564_THEN_propDst_ETC___d1567 = + assign IF_propDstIdx_1_1_lat_0_whas__566_THEN_propDst_ETC___d1569 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__427_THEN_propDstId_ETC___d1430 = + assign IF_propDstIdx_1_lat_0_whas__429_THEN_propDstId_ETC___d1432 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1546 = + assign NOT_enqDst_0_rl_454_BIT_73_455_460_AND_SEL_ARR_ETC___d1548 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1488 && - (SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1484 ? + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1490 && + (SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1486 ? !srcRR_0 : - IF_propDstIdx_0_lat_0_whas__420_THEN_propDstId_ETC___d1423) ; - assign NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1551 = + IF_propDstIdx_0_lat_0_whas__422_THEN_propDstId_ETC___d1425) ; + assign NOT_enqDst_0_rl_454_BIT_73_455_460_AND_SEL_ARR_ETC___d1553 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1488 && - x__h100988 && + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1490 && + x__h100998 && !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ; - assign NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1847 = + assign NOT_enqDst_1_0_rl_653_BIT_584_654_659_AND_SEL__ETC___d1849 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1725 && - (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1721 ? + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1727 && + (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1723 ? !srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560) ; - assign NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1852 = + IF_propDstIdx_1_0_lat_0_whas__559_THEN_propDst_ETC___d1562) ; + assign NOT_enqDst_1_0_rl_653_BIT_584_654_659_AND_SEL__ETC___d1854 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1725 && - x__h123274 && + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1727 && + x__h123284 && !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 = + assign NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2338 = - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2341 = + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2341 = - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2344 = + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1201 = + assign NOT_llc_axi4_adapter_rg_wr_req_beat_363_EQ_0_3_ETC___d2377 = + (llc_axi4_adapter_rg_wr_req_beat != 3'd0 || + llc_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 && + !llc_axi4_adapter_master_xactor_shim_awff_rv[98]) && + (llc_axi4_adapter_rg_wr_req_beat != 3'd7 || + llc$RDY_to_mem_toM_deq) ; + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1203 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5866,7 +5882,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1296 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1298 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5877,7 +5893,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1307 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1309 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5889,7 +5905,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1317 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1319 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5901,7 +5917,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1365 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1367 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5911,7 +5927,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1377 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1379 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5921,90 +5937,96 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513 = + assign NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (!mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (!IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || !mmioPlatform_mtip_0) ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__434_THEN__ETC___d1539 = - { CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, - x__h101188, - x__h101189 } ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__434_THEN__ETC___d1540 = - { CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, - SEL_ARR_IF_propDstData_0_lat_0_whas__434_THEN__ETC___d1539 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1759 = - { CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1784 = - { CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1801 = - { CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1818 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1784, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1801, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1835 = - { CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1836 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1759, - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1818, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1835 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1841 = - { CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, - !CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__572_THE_ETC___d1836, - x__h128009 } ; - assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1488 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1484 || - (IF_propDstIdx_0_lat_0_whas__420_THEN_NOT_propD_ETC___d1486 ? - IF_propDstIdx_1_lat_0_whas__427_THEN_propDstId_ETC___d1430 : - IF_propDstIdx_0_lat_0_whas__420_THEN_propDstId_ETC___d1423) ; - assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1725 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1721 || - (IF_propDstIdx_1_0_lat_0_whas__557_THEN_NOT_pro_ETC___d1723 ? - IF_propDstIdx_1_1_lat_0_whas__564_THEN_propDst_ETC___d1567 : - IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560) ; + assign NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208 = + !whichHalf___1__h15055 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + mmio_axi4_adapter_rg_wr_req_beat || + mmio_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 && + mmio_axi4_adapter_master_shim_awff$FULL_N ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__436_THEN__ETC___d1541 = + { CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + x__h101198, + x__h101199 } ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__436_THEN__ETC___d1542 = + { CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + SEL_ARR_IF_propDstData_0_lat_0_whas__436_THEN__ETC___d1541 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1761 = + { CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1786 = + { CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1803 = + { CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1820 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1786, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1803, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1837 = + { CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1838 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1761, + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1820, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1837 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1843 = + { CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, + !CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__574_THE_ETC___d1838, + x__h128019 } ; + assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1490 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1486 || + (IF_propDstIdx_0_lat_0_whas__422_THEN_NOT_propD_ETC___d1488 ? + IF_propDstIdx_1_lat_0_whas__429_THEN_propDstId_ETC___d1432 : + IF_propDstIdx_0_lat_0_whas__422_THEN_propDstId_ETC___d1425) ; + assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1727 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1723 || + (IF_propDstIdx_1_0_lat_0_whas__559_THEN_NOT_pro_ETC___d1725 ? + IF_propDstIdx_1_1_lat_0_whas__566_THEN_propDst_ETC___d1569 : + IF_propDstIdx_1_0_lat_0_whas__559_THEN_propDst_ETC___d1562) ; assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && (whichHalf___1__h15055 || @@ -6018,8 +6040,8 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? whichHalf___1__h15055 : mmio_axi4_adapter_rg_wr_req_beat ; - assign addr1__h90765 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign amo_req_data__h39114 = + assign addr1__h90775 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign amo_req_data__h39124 = (mmioPlatform_reqBE[3:0] == 4'd0 && mmioPlatform_reqBE[7:4] == 4'd0 && mmioPlatform_reqBE[11:8] == 4'd0 && @@ -6035,7 +6057,7 @@ module mkProc(CLK, ((mmioPlatform_reqBE[3:0] == 4'd0) ? mmioPlatform_reqData[63:32] : mmioPlatform_reqData[31:0]))) ; - assign b__h193993 = + assign b__h194003 = llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6043,205 +6065,236 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554432 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556480 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_toHostAddr ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_fromHostAddr ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 ; + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ; + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ; - assign core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764 = + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ; + assign core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766 = core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530 ; - assign data__h141232 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532 ; + assign data__h141242 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986[7:0] } ; - assign failed_testnum__h224472 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988[7:0] } ; + assign failed_testnum__h226609 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h140665 = + assign line_addr__h140675 = { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h150776 = + assign line_addr__h150786 = { llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h194193 = { llc$to_mem_toM_first[68:11], 6'h0 } ; + assign line_addr__h194203 = { llc$to_mem_toM_first[68:11], 6'h0 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34 = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2270 = - llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && - (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || - llc$RDY_to_mem_rsFromM_enq && - llc_axi4_adapter_f_pending_reads$EMPTY_N) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2319 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[512] : + !llc_axi4_adapter_rg_cline[513]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2322 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[512] : + llc_axi4_adapter_rg_cline[513]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2327 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[513] : + !llc_axi4_adapter_rg_cline[514]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2330 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[513] : + llc_axi4_adapter_rg_cline[514]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2335 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[514] : + !llc_axi4_adapter_rg_cline[515]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2338 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[514] : + llc_axi4_adapter_rg_cline[515]) ; assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2052 = - line_addr__h150776 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1951 = - line_addr__h140665 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2054 = + line_addr__h150786 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1953 = + line_addr__h140675 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31 = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ; - assign lower_data__h44520 = - mmioPlatform_waitLowerMSIPCRs ? v__h44413 : 32'd0 ; + assign lower_data__h44530 = + mmioPlatform_waitLowerMSIPCRs ? v__h44423 : 32'd0 ; assign mem_req_rd_addr_arlen__h5411 = (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? 8'd1 : 8'd0 ; - assign mmioPlatform_amoWaitWriteResp_311_OR_core_0_RD_ETC___d1314 = + assign mmioPlatform_amoWaitWriteResp_313_OR_core_0_RD_ETC___d1316 = mmioPlatform_amoWaitWriteResp || core_0$RDY_mmioToPlatform_pRs_enq && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) ; - assign mmioPlatform_cycle_90_ULT_99___d491 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379 = + assign mmioPlatform_cycle_92_ULT_99___d493 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h59831 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 = - mmioPlatform_mtimecmp_0 <= newData__h53320 ; - assign mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 = + assign mmioPlatform_mtime__h59841 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 = + mmioPlatform_mtimecmp_0 <= newData__h53330 ; + assign mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd0 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd1 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd2 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd3 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd4 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd5 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd6 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd7 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd8 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -6255,45 +6308,45 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_first[148:145] != 4'd6 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd7 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd8 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525 ; - assign mmioPlatform_reqAmofunc__h88535 = mmioPlatform_reqAmofunc ; - assign mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910 = + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527 ; + assign mmioPlatform_reqAmofunc__h88545 = mmioPlatform_reqAmofunc ; + assign mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912 = { mmioPlatform_reqFunc[3:0], - (IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0]) ? + (IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0]) ? 2'd1 : 2'd2, 2'd0 } ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (!mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (!IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || !mmioPlatform_mtip_0) ; - assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257 = (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_cfg_verbosity != 4'd0 ; - assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261 = (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && @@ -6303,14 +6356,14 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_arff$FULL_N : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign mmio_axi4_adapter_f_rsps_to_core_first__298_BI_ETC___d1399 = + assign mmio_axi4_adapter_f_rsps_to_core_first__300_BI_ETC___d1401 = { mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmioPlatform_fetchingWay, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - IF_mmioPlatform_fetchingWay_370_THEN_mmioPlatf_ETC___d1396 : + IF_mmioPlatform_fetchingWay_372_THEN_mmioPlatf_ETC___d1398 : mmioPlatform_fetchedInsts_0 } ; assign mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 = mmio_axi4_adapter_read_req_addr[3] + @@ -6322,43 +6375,43 @@ module mkProc(CLK, mmio_axi4_adapter_rspData[63:0] } : { mmio_axi4_adapter_rspData[127:64], mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; - assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 = + assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 = mmio_axi4_adapter_soc_map$m_is_IO_addr && (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) ; - assign newData__h45219 = + assign newData__h45229 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d920[63:0] : - x__h48532 ; - assign newData__h53320 = + amoExec___d922[63:0] : + x__h48542 ; + assign newData__h53330 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1006[63:0] : - x__h56610 ; - assign upper_data__h44521 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44376 ; - assign v__h44376 = mmioPlatform_waitUpperMSIPCRs ? v__h44413 : 32'd0 ; - assign v__h44413 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign v_awaddr__h215686 = { llc$to_mem_toM_first[643:586], 6'h0 } ; - assign value__h61538 = mmioPlatform_mtimecmp_0 ; + amoExec___d1008[63:0] : + x__h56620 ; + assign upper_data__h44531 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44386 ; + assign v__h44386 = mmioPlatform_waitUpperMSIPCRs ? v__h44423 : 32'd0 ; + assign v__h44423 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign v_awaddr__h217772 = { llc$to_mem_toM_first[643:586], 6'h0 } ; + assign value__h61548 = mmioPlatform_mtimecmp_0 ; assign whichHalf___1__h15055 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; - assign x__h100988 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1484 ? + assign x__h100998 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1486 ? srcRR_0 : - IF_propDstIdx_0_lat_0_whas__420_THEN_NOT_propD_ETC___d1486 ; + IF_propDstIdx_0_lat_0_whas__422_THEN_NOT_propD_ETC___d1488 ; assign x__h10399 = mmio_axi4_adapter_rg_rd_rsp_beat + 1'd1 ; - assign x__h116710 = + assign x__h116720 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__648_THEN_enqDst_1_0__ETC___d1689 ; - assign x__h123274 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1721 ? + IF_enqDst_1_0_lat_0_whas__650_THEN_enqDst_1_0__ETC___d1691 ; + assign x__h123284 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1723 ? srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__557_THEN_NOT_pro_ETC___d1723 ; + IF_propDstIdx_1_0_lat_0_whas__559_THEN_NOT_pro_ETC___d1725 ; assign x__h15143 = x__h15155 + y__h15156 ; assign x__h15155 = x__h15167 + y__h15168 ; assign x__h15167 = x__h15179 + y__h15180 ; @@ -6374,70 +6427,72 @@ module mkProc(CLK, assign x__h15287 = x__h15299 + y__h15300 ; assign x__h15299 = x__h15311 + y__h15312 ; assign x__h15311 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144] } ; - assign x__h17610 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; - assign x__h48532 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + assign x__h17619 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; + assign x__h195056 = llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; + assign x__h218130 = llc_axi4_adapter_rg_wr_req_beat + 3'd1 ; + assign x__h48542 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_mtimecmp_0[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign x__h56610 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + assign x__h56620 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_mtime[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_mtime[7:0] } ; - assign x__h64538 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign x__h64548 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : 8'd0 } ; - assign x__h68539 = + assign x__h68549 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1132[63:0] : - x__h71213 ; - assign x__h71213 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1148, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + amoExec___d1134[63:0] : + x__h71223 ; + assign x__h71223 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1150, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_fromHostQ_data_0[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign x__h73754 = + assign x__h73764 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1076[63:0] : - x__h64538 ; - assign x__h79393 = mmioPlatform_fromHostQ_data_0 ; - assign x_data__h42055 = { 31'd0, mmioPlatform_reqData[0] } ; + amoExec___d1078[63:0] : + x__h64548 ; + assign x__h79403 = mmioPlatform_fromHostQ_data_0 ; + assign x_data__h42065 = { 31'd0, mmioPlatform_reqData[0] } ; assign y__h15144 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[129] } ; assign y__h15156 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[130] } ; assign y__h15168 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[131] } ; @@ -6456,14 +6511,14 @@ module mkProc(CLK, always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h188873 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h188873 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h188873 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h188873 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h188873 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h188873 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h188873 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h188873 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h188883 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h188883 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h188883 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h188883 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h188883 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h188883 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h188883 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h188883 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) @@ -6518,40 +6573,40 @@ module mkProc(CLK, begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) 2'd0: - v_wdata__h216097 = + v_wdata__h218243 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1; 2'd1: - v_wdata__h216097 = + v_wdata__h218243 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2; 2'd2: - v_wdata__h216097 = + v_wdata__h218243 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3; 2'd3: - v_wdata__h216097 = + v_wdata__h218243 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: v_wstrb__h216098 = llc$to_mem_toM_first[523:516]; - 3'd1: v_wstrb__h216098 = llc$to_mem_toM_first[531:524]; - 3'd2: v_wstrb__h216098 = llc$to_mem_toM_first[539:532]; - 3'd3: v_wstrb__h216098 = llc$to_mem_toM_first[547:540]; - 3'd4: v_wstrb__h216098 = llc$to_mem_toM_first[555:548]; - 3'd5: v_wstrb__h216098 = llc$to_mem_toM_first[563:556]; - 3'd6: v_wstrb__h216098 = llc$to_mem_toM_first[571:564]; - 3'd7: v_wstrb__h216098 = llc$to_mem_toM_first[579:572]; + 3'd0: v_wstrb__h218244 = llc$to_mem_toM_first[523:516]; + 3'd1: v_wstrb__h218244 = llc$to_mem_toM_first[531:524]; + 3'd2: v_wstrb__h218244 = llc$to_mem_toM_first[539:532]; + 3'd3: v_wstrb__h218244 = llc$to_mem_toM_first[547:540]; + 3'd4: v_wstrb__h218244 = llc$to_mem_toM_first[555:548]; + 3'd5: v_wstrb__h218244 = llc$to_mem_toM_first[563:556]; + 3'd6: v_wstrb__h218244 = llc$to_mem_toM_first[571:564]; + 3'd7: v_wstrb__h218244 = llc$to_mem_toM_first[579:572]; endcase end always@(_theResult____h13492 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) begin case (_theResult____h13492) 1'd0: - wflit_wdata__h17678 = + wflit_wdata__h17687 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]; 1'd1: - wflit_wdata__h17678 = + wflit_wdata__h17687 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64]; endcase end @@ -6559,30 +6614,30 @@ module mkProc(CLK, begin case (_theResult____h13492) 1'd0: - wflit_wstrb__h17679 = + wflit_wstrb__h17688 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129]; 1'd1: - wflit_wstrb__h17679 = + wflit_wstrb__h17688 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) - 2'd0: v_wuser__h216100 = llc$to_mem_toM_first[512]; - 2'd1: v_wuser__h216100 = llc$to_mem_toM_first[513]; - 2'd2: v_wuser__h216100 = llc$to_mem_toM_first[514]; - 2'd3: v_wuser__h216100 = llc$to_mem_toM_first[515]; + 2'd0: v_wuser__h218246 = llc$to_mem_toM_first[512]; + 2'd1: v_wuser__h218246 = llc$to_mem_toM_first[513]; + 2'd2: v_wuser__h218246 = llc$to_mem_toM_first[514]; + 2'd3: v_wuser__h218246 = llc$to_mem_toM_first[515]; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844 = + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844 = + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6590,21 +6645,21 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 2'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 2'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; 2'd2: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64]; 2'd3: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962 or + IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6612,11 +6667,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = - IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962; + IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038 or + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6624,452 +6679,452 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038; + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040; endcase end always@(srcRR_0 or - IF_propDstIdx_0_lat_0_whas__420_THEN_propDstId_ETC___d1423 or - IF_propDstIdx_1_lat_0_whas__427_THEN_propDstId_ETC___d1430) + IF_propDstIdx_0_lat_0_whas__422_THEN_propDstId_ETC___d1425 or + IF_propDstIdx_1_lat_0_whas__429_THEN_propDstId_ETC___d1432) begin case (srcRR_0) 1'd0: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1484 = - IF_propDstIdx_0_lat_0_whas__420_THEN_propDstId_ETC___d1423; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1486 = + IF_propDstIdx_0_lat_0_whas__422_THEN_propDstId_ETC___d1425; 1'd1: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__420_THEN_p_ETC___d1484 = - IF_propDstIdx_1_lat_0_whas__427_THEN_propDstId_ETC___d1430; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__422_THEN_p_ETC___d1486 = + IF_propDstIdx_1_lat_0_whas__429_THEN_propDstId_ETC___d1432; endcase end always@(srcRR_1_0 or - IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560 or - IF_propDstIdx_1_1_lat_0_whas__564_THEN_propDst_ETC___d1567) + IF_propDstIdx_1_0_lat_0_whas__559_THEN_propDst_ETC___d1562 or + IF_propDstIdx_1_1_lat_0_whas__566_THEN_propDst_ETC___d1569) begin case (srcRR_1_0) 1'd0: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1721 = - IF_propDstIdx_1_0_lat_0_whas__557_THEN_propDst_ETC___d1560; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1723 = + IF_propDstIdx_1_0_lat_0_whas__559_THEN_propDst_ETC___d1562; 1'd1: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__557_THEN_ETC___d1721 = - IF_propDstIdx_1_1_lat_0_whas__564_THEN_propDst_ETC___d1567; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__559_THEN_ETC___d1723 = + IF_propDstIdx_1_1_lat_0_whas__566_THEN_propDst_ETC___d1569; endcase end - always@(x__h100988 or + always@(x__h100998 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100988) + case (x__h100998) 1'd0: - x__h101188 = + x__h101198 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]; 1'd1: - x__h101188 = + x__h101198 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]; endcase end - always@(x__h100988 or + always@(x__h100998 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100988) + case (x__h100998) 1'd0: - x__h101189 = + x__h101199 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]; 1'd1: - x__h101189 = + x__h101199 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]; endcase end - always@(x__h100988 or + always@(x__h100998 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100988) + case (x__h100998) 1'd0: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]; 1'd1: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]; endcase end - always@(x__h100988 or + always@(x__h100998 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100988) + case (x__h100998) 1'd0: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]; 1'd1: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]; endcase end - always@(x__h100988 or + always@(x__h100998 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100988) + case (x__h100998) 1'd0: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]; 1'd1: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]; endcase end - always@(x__h100988 or + always@(x__h100998 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100988) + case (x__h100998) 1'd0: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]; 1'd1: - CASE_x00988_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = + CASE_x00998_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]; endcase end - always@(x__h123274 or - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1603 or - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1641) + always@(x__h123284 or + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1605 or + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1643) begin - case (x__h123274) + case (x__h123284) 1'd0: - x__h128009 = - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1603; + x__h128019 = + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1605; 1'd1: - x__h128009 = - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1641; + x__h128019 = + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1643; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516] : propDstData_1_0_rl[516]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516] : propDstData_1_1_rl[516]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515] : propDstData_1_0_rl[515]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515] : propDstData_1_1_rl[515]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[514] : propDstData_1_0_rl[514]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[514] : propDstData_1_1_rl[514]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513]; endcase end - always@(x__h123274 or - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1582 or - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1620) + always@(x__h123284 or + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1584 or + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1622) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1582; + CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1584; 1'd1: - CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1620; + CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1622; endcase end - always@(x__h123274 or + always@(x__h123284 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[517] : !propDstData_1_0_rl[517]; 1'd1: - CASE_x23274_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x23284_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[517] : !propDstData_1_1_rl[517]; endcase end - always@(x__h123274 or - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1577 or - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1615) + always@(x__h123284 or + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1579 or + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1617) begin - case (x__h123274) + case (x__h123284) 1'd0: - CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = - IF_propDstData_1_0_lat_0_whas__572_THEN_propDs_ETC___d1577; + CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_0_lat_0_whas__574_THEN_propDs_ETC___d1579; 1'd1: - CASE_x23274_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = - IF_propDstData_1_1_lat_0_whas__610_THEN_propDs_ETC___d1615; + CASE_x23284_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_1_lat_0_whas__612_THEN_propDs_ETC___d1617; endcase end always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or @@ -7077,28 +7132,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1986 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1988 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7106,14 +7161,14 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32]) - 3'd0: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h150959 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h150969 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7515,30 +7570,30 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h224877 = $stime; + v__h227014 = $stime; #0; end - v__h224871 = v__h224877 / 32'd10; + v__h227008 = v__h227014 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h224871, + v__h227008, start_startpc, start_tohostAddr, start_fromhostAddr); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1546 && - IF_propDstIdx_0_lat_0_whas__420_THEN_NOT_propD_ETC___d1486) + if (NOT_enqDst_0_rl_454_BIT_73_455_460_AND_SEL_ARR_ETC___d1548 && + IF_propDstIdx_0_lat_0_whas__422_THEN_NOT_propD_ETC___d1488) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_0_rl_452_BIT_73_453_458_AND_SEL_ARR_ETC___d1551) + if (NOT_enqDst_0_rl_454_BIT_73_455_460_AND_SEL_ARR_ETC___d1553) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1847 && - IF_propDstIdx_1_0_lat_0_whas__557_THEN_NOT_pro_ETC___d1723) + if (NOT_enqDst_1_0_rl_653_BIT_584_654_659_AND_SEL__ETC___d1849 && + IF_propDstIdx_1_0_lat_0_whas__559_THEN_NOT_pro_ETC___d1725) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) - if (NOT_enqDst_1_0_rl_651_BIT_584_652_657_AND_SEL__ETC___d1852) + if (NOT_enqDst_1_0_rl_653_BIT_584_654_659_AND_SEL__ETC___d1854) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (core_0$RDY_coreIndInv_terminate) @@ -7546,14 +7601,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h224429 = $stime; + v__h226566 = $stime; #0; end - v__h224423 = v__h224429 / 32'd10; + v__h226560 = v__h226566 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h224423, + v__h226560, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7563,7 +7618,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h224472); + $display("FAIL %0d", failed_testnum__h226609); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8175,7 +8230,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) begin v__h17177 = $stime; #0; @@ -8184,166 +8239,166 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $display("%d: %m.rl_handle_write_req: sent aw flit:", v__h17171); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", mem_req_rd_addr_arlen__h5411); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", _theResult_____1_awsize_val__h17116, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) begin - v__h17348 = $stime; + v__h17357 = $stime; #0; end - v__h17342 = v__h17348 / 32'd10; + v__h17351 = v__h17357 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) - $display("%0d: ERROR: CreditCounter: overflow", v__h17342); + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) + $display("%0d: ERROR: CreditCounter: overflow", v__h17351); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h17740 = $stime; + v__h17749 = $stime; #0; end - v__h17734 = v__h17740 / 32'd10; + v__h17743 = v__h17749 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: sent w flit:", v__h17734); + $display("%d: %m.rl_handle_write_req: sent w flit:", v__h17743); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8358,7 +8413,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", wflit_wdata__h17678); + $write("'h%h", wflit_wdata__h17687); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8368,7 +8423,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", wflit_wstrb__h17679); + $write("'h%h", wflit_wstrb__h17688); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8418,16 +8473,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h18150 = $stime; + v__h18159 = $stime; #0; end - v__h18144 = v__h18150 / 32'd10; + v__h18153 = v__h18159 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h18144); + v__h18153); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9680,14 +9735,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h20462 = $stime; + v__h20472 = $stime; #0; end - v__h20456 = v__h20462 / 32'd10; + v__h20466 = v__h20472 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h20456); + $display("%0d: %m.rl_discard_write_rsp", v__h20466); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9742,15 +9797,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) begin - v__h21008 = $stime; + v__h21018 = $stime; #0; end - v__h21002 = v__h21008 / 32'd10; + v__h21012 = v__h21018 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h21002); + v__h21012); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) @@ -9800,14 +9855,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h21530 = $stime; + v__h21540 = $stime; #0; end - v__h21524 = v__h21530 / 32'd10; + v__h21534 = v__h21540 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h21524); + v__h21534); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -10099,128 +10154,128 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write("[Platform - SelectReq] timer interrupt", ", mtime %x", mmioPlatform_mtime, ", mtimcmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(", old mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(", new interrupts "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("[Platform - SelectReq] core %d, req ", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write("tagged Inst ", "'h%h", core_0$mmioToPlatform_cRq_first[145]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write("tagged Ld ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write("tagged St ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -10229,542 +10284,542 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586) $write("Swap"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592) $write("Add"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598) $write("Xor"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604) $write("And"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610) $write("Or"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616) $write("Min"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622) $write("Max"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628) $write("Minu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634) $write("Maxu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656) $write("None"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("TaggedData { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[128]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && !core_0$mmioToPlatform_cRq_first[128]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" req type "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762) $write("tagged MSIP ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && - core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764) + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && + core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766) $write("tagged MTimeCmp ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769) + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771) $write("tagged MTime ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775) + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777) $write("tagged ToHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781) + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783) $write("tagged FromHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788) + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790) $write("tagged MMIO_Fabric_Adapter ", "'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) @@ -10827,8 +10882,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h44520, - upper_data__h44521); + lower_data__h44530, + upper_data__h44531); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -10840,62 +10895,62 @@ module mkProc(CLK, mmioPlatform_mtimecmp_0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write("[Platform - process mtimecmp] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(", mtime %x", mmioPlatform_mtime, ", old mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h45219, "\n"); + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) + $write(", new mtimecmp[%d] %x", 1'd0, newData__h45229, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -10940,61 +10995,61 @@ module mkProc(CLK, mmioPlatform_mtime); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write("[Platform - process mtime] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) - $write(", new mtime %x", newData__h53320, ", mtimecmp "); + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) + $write(", new mtime %x", newData__h53330, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeDone) @@ -11062,7 +11117,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11088,13 +11143,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11124,13 +11179,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_fromHostQ_empty && - x__h73754 != 64'd0) + x__h73764 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h68539 != 64'd0) + x__h68549 != 64'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11149,12 +11204,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1178) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1180) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1157) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1159) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11180,13 +11235,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1162, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1164, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1160, + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1162, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11681,7 +11736,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", addr1__h90765); + $write("'h%h", addr1__h90775); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -11766,76 +11821,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379) + mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379) + mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381) $display(" fetchingWay %0d instSel %0d inst 0x%0h", mmioPlatform_fetchingWay, mmioPlatform_instSel, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1391); + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1393); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379) + !mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp: final resp to core:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379) + !mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379) + !mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_370_ULT_mmioPlatform__ETC___d1379) + !mmioPlatform_fetchingWay_372_ULT_mmioPlatform__ETC___d1381) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && @@ -11885,7 +11940,7 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (!llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__113_ETC___d2116 && + IF_llc_mem_server_propDstIdx_0_lat_0_whas__115_ETC___d2118 && !CAN_FIRE_RL_llc_mem_server_srcPropose && !llc_mem_server_propDstIdx_0_rl) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); @@ -11912,16 +11967,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h202080 = $stime; + v__h204166 = $stime; #0; end - v__h202074 = v__h202080 / 32'd10; + v__h204160 = v__h204166 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h202074); + v__h204160); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -13378,15 +13433,15 @@ module mkProc(CLK, llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h215789 = $stime; + v__h217884 = $stime; #0; end - v__h215783 = v__h215789 / 32'd10; + v__h217878 = v__h217884 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h215783); + $display("%0d: ERROR: CreditCounter: overflow", v__h217878); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && @@ -13396,15 +13451,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h194057 = $stime; + v__h194067 = $stime; #0; end - v__h194051 = v__h194057 / 32'd10; + v__h194061 = v__h194067 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory", - v__h194051); + v__h194061); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) @@ -13461,103 +13516,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) - $write("'h%h", line_addr__h194193); + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) + $write("'h%h", line_addr__h194203); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) @@ -13572,15 +13627,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) begin - v__h223415 = $stime; + v__h225552 = $stime; #0; end - v__h223409 = v__h223415 / 32'd10; + v__h225546 = v__h225552 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h223409); + v__h225546); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) @@ -13638,62 +13693,62 @@ module mkProc(CLK, $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) begin - v__h194646 = $stime; + v__h194656 = $stime; #0; end - v__h194640 = v__h194646 / 32'd10; + v__h194650 = v__h194656 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h194640, + v__h194650, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13702,45 +13757,45 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) begin - v__h194832 = $stime; + v__h194842 = $stime; #0; end - v__h194826 = v__h194832 / 32'd10; + v__h194836 = v__h194842 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h194826); + v__h194836); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) @@ -13819,310 +13874,286 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__244_U_ETC___d2259) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__246_U_ETC___d2261) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v index 46ff41f..600d0e6 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:51:03 BST 2020 +// On Mon Jul 6 19:06:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRas.v b/src_SSITH_P3/Verilog_RTL_sim/mkRas.v index 5c9db8d..ff720c5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRas.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:52:09 BST 2020 +// On Mon Jul 6 19:07:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v b/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v index e8d31c7..ec44bbd 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:48:37 BST 2020 +// On Mon Jul 6 19:03:38 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v index fddc94d..9c82829 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:51:46 BST 2020 +// On Mon Jul 6 19:06:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v index a963b28..140d386 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:34 BST 2020 +// On Mon Jul 6 19:11:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v index df2e6e0..30e552c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:51:59 BST 2020 +// On Mon Jul 6 19:07:02 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v index ee7c291..28469d9 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:51:55 BST 2020 +// On Mon Jul 6 19:06:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v b/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v index 60d309f..005e12e 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:51:14 BST 2020 +// On Mon Jul 6 19:06:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v index 7b2af76..35f31f2 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:53:33 BST 2020 +// On Mon Jul 6 19:08:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v index dc6894c..6983783 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:53:26 BST 2020 +// On Mon Jul 6 19:08:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v index 3d5f245..81dd708 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:55:59 BST 2020 +// On Mon Jul 6 19:11:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v b/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v index c6e3f99..38d0cb7 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:05 BST 2020 +// On Mon Jul 6 19:02:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v b/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v index 6aaf985..eea2891 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:50:54 BST 2020 +// On Mon Jul 6 19:05:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v b/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v index 403f97f..27428d8 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:52:55 BST 2020 +// On Mon Jul 6 19:07:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v b/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v index 2a6477a..f547181 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:40 BST 2020 +// On Mon Jul 6 19:02:41 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v b/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v index 29d7301..ecc0a59 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:48:09 BST 2020 +// On Mon Jul 6 19:03:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v index 41fd333..660491b 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:06 BST 2020 +// On Mon Jul 6 19:11:20 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v index ca4581e..d5374b8 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:06 BST 2020 +// On Mon Jul 6 19:11:20 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v b/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v index 275ff8d..8e7063d 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:57:07 BST 2020 +// On Mon Jul 6 19:11:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_alu.v b/src_SSITH_P3/Verilog_RTL_sim/module_alu.v index d82802e..984e885 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_alu.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:25 BST 2020 +// On Mon Jul 6 19:02:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v b/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v index f68a1ae..b118a65 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:27 BST 2020 +// On Mon Jul 6 19:02:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v b/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v index b3e783f..151c72c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:03 BST 2020 +// On Mon Jul 6 19:02:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v b/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v index 9673ae6..a974fc5 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:28 BST 2020 +// On Mon Jul 6 19:02:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v b/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v index f94b791..7899098 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:27 BST 2020 +// On Mon Jul 6 19:02:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v b/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v index d01edaa..2b61837 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:24 BST 2020 +// On Mon Jul 6 19:02:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v b/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v index c4d9ffd..cc40d35 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:27 BST 2020 +// On Mon Jul 6 19:02:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v b/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v index 18971bd..1d31192 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:27 BST 2020 +// On Mon Jul 6 19:02:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v b/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v index f926fa6..8328d90 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:29 BST 2020 +// On Mon Jul 6 19:02:31 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_decode.v b/src_SSITH_P3/Verilog_RTL_sim/module_decode.v index 056f702..1a5051a 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_decode.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:52:05 BST 2020 +// On Mon Jul 6 19:07:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v b/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v index 0d4bf6b..501c854 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:52:02 BST 2020 +// On Mon Jul 6 19:07:05 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v b/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v index b193f89..3fdb03f 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:56:06 BST 2020 +// On Mon Jul 6 19:11:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v b/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v index 06430bd..a3d9fec 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:25 BST 2020 +// On Mon Jul 6 19:02:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v b/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v index b5ec3f3..a6fda1c 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:25 BST 2020 +// On Mon Jul 6 19:02:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v b/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v index af32069..8c5ce01 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v +++ b/src_SSITH_P3/Verilog_RTL_sim/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 21:47:27 BST 2020 +// On Mon Jul 6 19:02:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v index 8168e5e..289231a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:11:05 BST 2020 +// On Mon Jul 6 19:24:10 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v index 8aa1b42..22e001b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluExeToFinFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:11:06 BST 2020 +// On Mon Jul 6 19:24:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v index 55ce50e..89c08ff 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkAluRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:11:05 BST 2020 +// On Mon Jul 6 19:24:11 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v index 201d36e..c86db34 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkBht.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkBht.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:07 BST 2020 +// On Mon Jul 6 19:23:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 9839e9a..9405d27 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:12:07 BST 2020 +// On Mon Jul 6 19:25:12 BST 2020 // // // Ports: @@ -3721,17 +3721,17 @@ module mkCore(CLK, // declarations used by system tasks // synopsys translate_off - reg [63 : 0] v__h213411; - reg [63 : 0] v__h215680; - reg [63 : 0] v__h271938; - reg [63 : 0] v__h347456; - reg [63 : 0] v__h423782; + reg [63 : 0] v__h213412; + reg [63 : 0] v__h215681; + reg [63 : 0] v__h271939; + reg [63 : 0] v__h347457; + reg [63 : 0] v__h423783; // synopsys translate_on // remaining internal signals reg [515 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5488; reg [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891; - reg [65 : 0] thin_address__h858472, thin_address__h899107; + reg [65 : 0] thin_address__h858470, thin_address__h899110; reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q367, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q368, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295, @@ -3770,12 +3770,12 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147, SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151, - addr__h505614, - addr__h843948, - addr__h887458, - data_out__h1020024, - trap_val__h996922, - x__h264730; + addr__h505615, + addr__h843947, + addr__h887460, + data_out__h1020028, + trap_val__h996926, + x__h264732; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q28, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q30, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q32, @@ -3810,7 +3810,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17257; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1872, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_31_TO_0_ETC___d2040, - x__h264885; + x__h264887; reg [29 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_22_ETC__q350, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_817_ETC__q290, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q344, @@ -3862,16 +3862,16 @@ module mkCore(CLK, _theResult___fst_sfd__h703056; reg [17 : 0] CASE_csrf_mepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q279, CASE_csrf_sepcc_reg_data_rl_BITS_52_TO_35_2621_ETC__q278, - thin_otype__h858477, - thin_otype__h899112; + thin_otype__h858475, + thin_otype__h899115; reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_233_ETC___d1885, SEL_ARR_mmio_dataRespQ_data_0_389_BITS_15_TO_0_ETC___d2052; - reg [13 : 0] thin_addrBits__h858473, - thin_addrBits__h899108, - thin_bounds_baseBits__h860421, - thin_bounds_baseBits__h900514, - thin_bounds_topBits__h860420, - thin_bounds_topBits__h900513; + reg [13 : 0] thin_addrBits__h858471, + thin_addrBits__h899111, + thin_bounds_baseBits__h860419, + thin_bounds_baseBits__h900517, + thin_bounds_topBits__h860418, + thin_bounds_topBits__h900516; reg [12 : 0] CASE_coreFix_memExe_lsqfirstLd_BITS_15_TO_14__ETC__q341, CASE_coreFix_memExe_lsqfirstSt_BITS_12_TO_11__ETC__q337, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328; @@ -3990,10 +3990,10 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_95_TO_327_BITS_ETC__q332, IF_fetchStage_pipelines_0_first__0256_BITS_265_ETC___d22045, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22190, - cause_code__h995318, - i__h995334, - t__h212839, - t__h215125; + cause_code__h995322, + i__h995338, + t__h212840, + t__h215126; reg [3 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q248, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q250, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q246, @@ -4019,9 +4019,9 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_236_ETC___d21371, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22191, IF_rob_deqPort_0_deq_data__2261_BIT_294_3456_T_ETC___d23478, - i__h995534, - thin_perms_soft__h858712, - thin_perms_soft__h899287; + i__h995538, + thin_perms_soft__h858710, + thin_perms_soft__h899290; reg [2 : 0] CASE_IF_coreFix_aluExe_0_dispToRegQ_first__838_ETC__q247, CASE_IF_coreFix_aluExe_0_regToExeQ_first__9457_ETC__q249, CASE_IF_coreFix_aluExe_0_rsAlu_dispatchData__8_ETC__q245, @@ -4051,15 +4051,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868, IF_fetchStage_pipelines_0_first__0256_BITS_232_ETC___d20442, IF_fetchStage_pipelines_1_first__0265_BITS_232_ETC___d21403, - x__h501096, - x__h508764; + x__h501097, + x__h508765; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q371, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q322, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q314, - thin_reserved__h858476, - thin_reserved__h899111; + thin_reserved__h858474, + thin_reserved__h899114; reg CASE_commitStage_commitTrap_BITS_44_TO_43_0_NO_ETC__q277, CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q158, @@ -4141,7 +4141,7 @@ module mkCore(CLK, CASE_guard94101_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q71, CASE_guard94433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q144, CASE_guard94433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q143, - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19249, @@ -4272,20 +4272,20 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d5560; wire [128 : 0] amoExec___d4922, amoExec___d773, - new_pc__h872924, - new_pc__h912071, - next_pc__h1012257, - pc__h963240, - v__h1012296, - v__h1013005, - x__h879902, - x__h914618; + new_pc__h872923, + new_pc__h912075, + next_pc__h1012261, + pc__h963244, + v__h1012300, + v__h1013009, + x__h879901, + x__h914622; wire [127 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5165, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881, SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889, coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070, - x__h183397, - x__h199249; + x__h183398, + x__h199250; wire [109 : 0] IF_fetchStage_pipelines_0_first__0256_BITS_238_ETC___d20622, IF_fetchStage_pipelines_1_first__0265_BITS_238_ETC___d21583; wire [85 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580; @@ -4311,91 +4311,91 @@ module mkCore(CLK, IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3417, - addTop__h239970, - addTop__h241127, - addTop__h254751, - address__h1000186, - address__h1000530, - address__h999529, - address__h999873, + addTop__h239972, + addTop__h241129, + addTop__h254753, + address__h1000190, + address__h1000534, + address__h999533, + address__h999877, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704, - cr_address__h866670, - cr_address__h867218, - cr_address__h906355, - cr_address__h906903, - data_address__h1018751, - data_address__h1019605, - in__h239801, - in__h240958, - in__h254582, - in__h854153, - in__h854458, - in__h855146, - in__h855450, - in__h855976, - in__h997691, - pc_address__h994737, - pointer__h242635, + cr_address__h866668, + cr_address__h867216, + cr_address__h906358, + cr_address__h906906, + data_address__h1018755, + data_address__h1019609, + in__h239803, + in__h240960, + in__h254584, + in__h854151, + in__h854456, + in__h855144, + in__h855448, + in__h855974, + in__h997695, + pc_address__h994741, + pointer__h242637, res_address__h126821, res_address__h139733, - res_address__h178896, - res_address__h197661, - res_address__h216420, - res_address__h235320, - res_address__h567343, + res_address__h178897, + res_address__h197662, + res_address__h216421, + res_address__h235322, + res_address__h567344, res_address__h568196, res_address__h613953, res_address__h659700, res_address__h705509, res_address__h706369, - res_address__h848642, - res_address__h892144, - result__h240597, - result__h241754, - result__h255378, - result_d_address__h1008601, - result_d_address__h1009004, - result_d_address__h1009421, - result_d_address__h1009824, - result_d_address__h1010493, - result_d_address__h1031651, - result_d_address__h1032054, - result_d_address__h1032471, - result_d_address__h1032874, - result_d_address__h1033541, - result_d_address__h242846, - ret__h239974, - ret__h241131, - ret__h254755, - x__h1000027, - x__h1000380, - x__h1000684, - x__h235743, - x__h239819, - x__h239967, - x__h240976, - x__h241124, - x__h248117, - x__h254600, - x__h254748, - x__h854171, - x__h854476, - x__h855164, - x__h855468, - x__h855994, - x__h997709, - x__h999723, - y__h239818, - y__h240975, - y__h254599, - y__h854170, - y__h854475, - y__h855163, - y__h855467, - y__h855993, - y__h997708; + res_address__h848641, + res_address__h892146, + result__h240599, + result__h241756, + result__h255380, + result_d_address__h1008605, + result_d_address__h1009008, + result_d_address__h1009425, + result_d_address__h1009828, + result_d_address__h1010497, + result_d_address__h1031655, + result_d_address__h1032058, + result_d_address__h1032475, + result_d_address__h1032878, + result_d_address__h1033545, + result_d_address__h242848, + ret__h239976, + ret__h241133, + ret__h254757, + x__h1000031, + x__h1000384, + x__h1000688, + x__h235745, + x__h239821, + x__h239969, + x__h240978, + x__h241126, + x__h248119, + x__h254602, + x__h254750, + x__h854169, + x__h854474, + x__h855162, + x__h855466, + x__h855992, + x__h997713, + x__h999727, + y__h239820, + y__h240977, + y__h254601, + y__h854168, + y__h854473, + y__h855161, + y__h855465, + y__h855991, + y__h997712; wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d13324, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12485, IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12486, @@ -4431,31 +4431,31 @@ module mkCore(CLK, a___1__h835845, a___1__h836131, a__h835704, - addBase__h1008620, - addBase__h1009023, - addBase__h1009440, - addBase__h1009843, - addBase__h1010513, - addBase__h239861, - addBase__h241018, - addBase__h254642, + addBase__h1008624, + addBase__h1009027, + addBase__h1009444, + addBase__h1009847, + addBase__h1010517, + addBase__h239863, + addBase__h241020, + addBase__h254644, addr__h148438, addr__h152014, - addr__h235314, - addr__h989734, - address__h1013717, - address__h999463, - address__h999513, + addr__h235316, + addr__h989738, + address__h1013721, + address__h999467, + address__h999517, b___1__h835846, b___1__h836176, b__h835705, - base__h999424, - base__h999478, - bot__h1008623, - bot__h1009026, - bot__h1009443, - bot__h1009846, - bot__h1010516, + base__h999428, + base__h999482, + bot__h1008627, + bot__h1009030, + bot__h1009447, + bot__h1009850, + bot__h1010520, csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816, csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745, data___1__h705531, @@ -4466,25 +4466,25 @@ module mkCore(CLK, data__h704999, data__h705831, data__h705862, - fcsr_csr__read__h849218, - fflags_csr__read__h849193, - frm_csr__read__h849204, - mask__h1000192, - mask__h999535, - mcause_csr__read__h850885, - mcounteren_csr__read__h850619, - medeleg_csr__read__h850222, - mideleg_csr__read__h850320, - mie_csr__read__h850447, - mip_csr__read__h851124, - mstatus_csr__read__h850061, - n__read__h1014147, + fcsr_csr__read__h849216, + fflags_csr__read__h849191, + frm_csr__read__h849202, + mask__h1000196, + mask__h999539, + mcause_csr__read__h850883, + mcounteren_csr__read__h850617, + medeleg_csr__read__h850220, + mideleg_csr__read__h850318, + mie_csr__read__h850445, + mip_csr__read__h851122, + mstatus_csr__read__h850059, + n__read__h1014151, n__read__h7908, - newAddrDiff__h1000193, - newAddrDiff__h1000537, - newAddrDiff__h999536, - newAddrDiff__h999880, - offset__h242625, + newAddrDiff__h1000197, + newAddrDiff__h1000541, + newAddrDiff__h999540, + newAddrDiff__h999884, + offset__h242627, q___1__h706456, rVal1__h714517, rVal2__h714518, @@ -4495,134 +4495,134 @@ module mkCore(CLK, res_data__h613995, res_data__h659737, res_data__h659742, - resp_addr__h509110, - rg_tdata1__read__h852225, + resp_addr__h509111, + rg_tdata1__read__h852223, robdeqPort_0_deq_data_BITS_95_TO_32__q17, - satp_csr__read__h849915, - scause_csr__read__h849712, - scounteren_csr__read__h849572, - sie_csr__read__h849484, - sip_csr__read__h849852, - sstatus_csr__read__h849414, - thin_address__h999417, - tmpAddr__h242834, - trap_val__h997075, - upd__h1014223, + satp_csr__read__h849913, + scause_csr__read__h849710, + scounteren_csr__read__h849570, + sie_csr__read__h849482, + sip_csr__read__h849850, + sstatus_csr__read__h849412, + thin_address__h999421, + tmpAddr__h242836, + trap_val__h997079, + upd__h1014227, upd__h3066, upd__h3676, upd__h7977, - value__h239691, - value__h239855, - value__h240848, - value__h241012, - value__h254472, - value__h254636, - x__h1008531, - x__h1008934, - x__h1009351, - x__h1009754, - x__h1010423, - x__h1031581, - x__h1031984, - x__h1032401, - x__h1032804, - x__h1033471, + value__h239693, + value__h239857, + value__h240850, + value__h241014, + value__h254474, + value__h254638, + x__h1008535, + x__h1008938, + x__h1009355, + x__h1009758, + x__h1010427, + x__h1031585, + x__h1031988, + x__h1032405, + x__h1032808, + x__h1033475, x__h127302, x__h140218, - x__h183479, - x__h202230, - x__h216796, - x__h239709, + x__h183480, + x__h202231, + x__h216797, x__h239711, - x__h240866, + x__h239713, x__h240868, - x__h242774, - x__h254490, + x__h240870, + x__h242776, x__h254492, + x__h254494, x__h714426, x__h714427, x__h714428, + x__h854230, x__h854232, - x__h854234, + x__h855223, x__h855225, - x__h855227, - x__h866847, - x__h867395, - x__h895986, - x__h895988, - x__h896270, - x__h896272, - x__h896615, - x__h896617, - x__h906532, - x__h907080, - x__h994909, - x__h997622, - x__h997624, + x__h866845, + x__h867393, + x__h895989, + x__h895991, + x__h896273, + x__h896275, + x__h896618, + x__h896620, + x__h906535, + x__h907083, + x__h994913, + x__h997626, + x__h997628, x_addr__h19883, x_addr__h44252, - x_addr__h535372, + x_addr__h535373, x_quotient__h705745, - x_reg_ifc__read__h849323, + x_reg_ifc__read__h849321, x_remainder__h705746, - y__h1000309, - y__h1016374, - y__h999652, + y__h1000313, + y__h1016378, + y__h999656, y_avValue__h710472, y_avValue__h711105, y_avValue__h711732, - y_avValue_snd_snd_snd_snd_snd__h1015845, - y_avValue_snd_snd_snd_snd_snd__h1016427, - y_avValue_snd_snd_snd_snd_snd__h1016456; + y_avValue_snd_snd_snd_snd_snd__h1015849, + y_avValue_snd_snd_snd_snd_snd__h1016431, + y_avValue_snd_snd_snd_snd_snd__h1016460; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14033, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d14803, - r1__read__h853106, + r1__read__h853104, + r1__read__h853508, + r1__read__h854201, + r1__read__h854513, + r1__read__h854746, + r1__read__h854918, + r1__read__h855194, + r1__read__h855505; + wire [61 : 0] r1__read__h853106, r1__read__h853510, r1__read__h854203, r1__read__h854515, r1__read__h854748, + r1__read__h854894, r1__read__h854920, r1__read__h855196, r1__read__h855507; - wire [61 : 0] r1__read__h853108, - r1__read__h853512, - r1__read__h854205, - r1__read__h854517, - r1__read__h854750, + wire [60 : 0] r1__read__h854750, r1__read__h854896, r1__read__h854922, - r1__read__h855198, r1__read__h855509; - wire [60 : 0] r1__read__h854752, - r1__read__h854898, + wire [59 : 0] r1__read__h853108, + r1__read__h853512, + r1__read__h854517, + r1__read__h854752, r1__read__h854924, r1__read__h855511; - wire [59 : 0] r1__read__h853110, + wire [58 : 0] r1__read__h853110, r1__read__h853514, + r1__read__h854506, r1__read__h854519, r1__read__h854754, r1__read__h854926, + r1__read__h855498, r1__read__h855513; - wire [58 : 0] r1__read__h853112, - r1__read__h853516, - r1__read__h854508, - r1__read__h854521, - r1__read__h854756, - r1__read__h854928, - r1__read__h855500, - r1__read__h855515; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5496, IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5538, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d7211, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d6974, - r1__read__h853114, - r1__read__h853518, - r1__read__h854523, - r1__read__h854758, - r1__read__h854900, - r1__read__h854930, - r1__read__h855517, - y__h422564; + r1__read__h853112, + r1__read__h853516, + r1__read__h854521, + r1__read__h854756, + r1__read__h854898, + r1__read__h854928, + r1__read__h855515, + y__h422565; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q110, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q40, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q75, @@ -4767,10 +4767,10 @@ module mkCore(CLK, _theResult___snd__h830811, _theResult___snd__h830817, _theResult___snd__h830835, - r1__read__h854760, - r1__read__h854902, - r1__read__h854932, - r1__read__h855519, + r1__read__h854758, + r1__read__h854900, + r1__read__h854930, + r1__read__h855517, result__h594704, result__h640453, result__h686200, @@ -4799,24 +4799,24 @@ module mkCore(CLK, x__h775186, x__h814490; wire [55 : 0] coreFix_memExe_dispToRegQ_first__686_BIT_102_6_ETC___d3579, + r1__read__h853114, + r1__read__h853518, + r1__read__h854523, + r1__read__h854760, + r1__read__h854932, + r1__read__h855519; + wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394, + IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260, r1__read__h853116, r1__read__h853520, r1__read__h854525, r1__read__h854762, r1__read__h854934, r1__read__h855521; - wire [54 : 0] IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394, - IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260, - r1__read__h853118, - r1__read__h853522, - r1__read__h854527, - r1__read__h854764, + wire [53 : 0] r1__read__h854871, + r1__read__h854902, r1__read__h854936, - r1__read__h855523; - wire [53 : 0] r1__read__h854873, - r1__read__h854904, - r1__read__h854938, - r1__read__h855525, + r1__read__h855523, sfd__h734302, sfd__h743953, sfd__h752713, @@ -4834,11 +4834,11 @@ module mkCore(CLK, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719, - r1__read__h854766, - r1__read__h854875, - r1__read__h854906, - r1__read__h854940, - r1__read__h855527; + r1__read__h854764, + r1__read__h854873, + r1__read__h854904, + r1__read__h854938, + r1__read__h855525; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13291, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13293, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d14000, @@ -4905,9 +4905,9 @@ module mkCore(CLK, _theResult___snd_fst_sfd__h793510, _theResult___snd_fst_sfd__h813203, _theResult___snd_fst_sfd__h831638, - mask__h239971, - mask__h241128, - mask__h254752, + mask__h239973, + mask__h241130, + mask__h254754, out___1_sfd__h714960, out___1_sfd__h753954, out___1_sfd__h793258, @@ -4920,47 +4920,47 @@ module mkCore(CLK, out_sfd__h813100, out_sfd__h822751, out_sfd__h831535; - wire [50 : 0] r1__read__h853120, r1__read__h854768; - wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7, - coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5, + wire [50 : 0] r1__read__h853118, r1__read__h854766; + wire [49 : 0] coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5, + coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q7, coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3, - highBitsfilter__h1008407, - highBitsfilter__h1008810, - highBitsfilter__h1009227, - highBitsfilter__h1009630, - highBitsfilter__h1010299, - highOffsetBits__h1008408, - highOffsetBits__h1008811, - highOffsetBits__h1009228, - highOffsetBits__h1009631, - highOffsetBits__h1010300, - highOffsetBits__h1031458, - highOffsetBits__h1031861, - highOffsetBits__h1032278, - highOffsetBits__h1032681, - highOffsetBits__h1033348, - highOffsetBits__h242644, - mask__h239862, - mask__h241019, - mask__h254643, - r1__read__h854877, - signBits__h1008405, - signBits__h1031455, - signBits__h242641, - x__h1008435, - x__h1031485, - x__h242671; - wire [48 : 0] r1__read__h853122, r1__read__h854770, r1__read__h854879; - wire [47 : 0] r1__read__h854881; - wire [46 : 0] r1__read__h853124, r1__read__h854772; - wire [45 : 0] r1__read__h853126, r1__read__h854774; - wire [44 : 0] r1__read__h853128, r1__read__h854776; - wire [43 : 0] r1__read__h853130, r1__read__h854778; - wire [42 : 0] r1__read__h854780; - wire [41 : 0] r1__read__h854782; - wire [40 : 0] r1__read__h854784; + highBitsfilter__h1008411, + highBitsfilter__h1008814, + highBitsfilter__h1009231, + highBitsfilter__h1009634, + highBitsfilter__h1010303, + highOffsetBits__h1008412, + highOffsetBits__h1008815, + highOffsetBits__h1009232, + highOffsetBits__h1009635, + highOffsetBits__h1010304, + highOffsetBits__h1031462, + highOffsetBits__h1031865, + highOffsetBits__h1032282, + highOffsetBits__h1032685, + highOffsetBits__h1033352, + highOffsetBits__h242646, + mask__h239864, + mask__h241021, + mask__h254645, + r1__read__h854875, + signBits__h1008409, + signBits__h1031459, + signBits__h242643, + x__h1008439, + x__h1031489, + x__h242673; + wire [48 : 0] r1__read__h853120, r1__read__h854768, r1__read__h854877; + wire [47 : 0] r1__read__h854879; + wire [46 : 0] r1__read__h853122, r1__read__h854770; + wire [45 : 0] r1__read__h853124, r1__read__h854772; + wire [44 : 0] r1__read__h853126, r1__read__h854774; + wire [43 : 0] r1__read__h853128, r1__read__h854776; + wire [42 : 0] r1__read__h854778; + wire [41 : 0] r1__read__h854780; + wire [40 : 0] r1__read__h854782; wire [38 : 0] IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878; - wire [37 : 0] r1__read__h854883; + wire [37 : 0] r1__read__h854881; wire [33 : 0] IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954, IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210, @@ -4985,15 +4985,15 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q22, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15, data05831_BITS_31_TO_0__q26, - r1__read__h853132, - r1__read__h854786, + r1__read__h853130, + r1__read__h854784, x__h568251, x__h614005, x__h65639, x__h659752, x_data__h60140; - wire [29 : 0] r1__read__h853134, r1__read__h854788; - wire [27 : 0] r1__read__h854790; + wire [29 : 0] r1__read__h853132, r1__read__h854786; + wire [27 : 0] r1__read__h854788; wire [25 : 0] IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111, IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142, @@ -5102,7 +5102,7 @@ module mkCore(CLK, out_sfd__h685161, out_sfd__h694345, out_sfd__h702981; - wire [19 : 0] r1__read__h854725; + wire [19 : 0] r1__read__h854723; wire [18 : 0] INV_commitStage_commitTrap_BITS_217_TO_199__q16, INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14, INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13, @@ -5111,8 +5111,8 @@ module mkCore(CLK, INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10, INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9, - INV_x83397_BITS_108_TO_90__q34, - INV_x99249_BITS_108_TO_90__q36; + INV_x83398_BITS_108_TO_90__q34, + INV_x99250_BITS_108_TO_90__q36; wire [17 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19042, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19043, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16647, @@ -5129,43 +5129,43 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3559; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3536, - _theResult____h920230, - base__h239696, - base__h240853, - base__h254477, - base__h854219, - base__h855212, - base__h895973, - base__h896257, - base__h896602, - base__h997609, - enabled_ints___1__h920755, - enabled_ints__h920801, - newAddrBits__h1008590, - newAddrBits__h1008993, - newAddrBits__h1009410, - newAddrBits__h1009813, - newAddrBits__h1010482, - newAddrBits__h1031640, - newAddrBits__h1032043, - newAddrBits__h1032460, - newAddrBits__h1032863, - newAddrBits__h1033530, - offset__h239697, - offset__h240854, - offset__h254478, - offset__h854220, - offset__h855213, - offset__h895974, - offset__h896258, - offset__h896603, - offset__h997610, - pend_ints__h920228, - x__h240069, - x__h241226, - x__h254850, - x__h896540, - y__h920767; + _theResult____h920234, + base__h239698, + base__h240855, + base__h254479, + base__h854217, + base__h855210, + base__h895976, + base__h896260, + base__h896605, + base__h997613, + enabled_ints___1__h920759, + enabled_ints__h920805, + newAddrBits__h1008594, + newAddrBits__h1008997, + newAddrBits__h1009414, + newAddrBits__h1009817, + newAddrBits__h1010486, + newAddrBits__h1031644, + newAddrBits__h1032047, + newAddrBits__h1032464, + newAddrBits__h1032867, + newAddrBits__h1033534, + offset__h239699, + offset__h240856, + offset__h254480, + offset__h854218, + offset__h855211, + offset__h895977, + offset__h896261, + offset__h896606, + offset__h997614, + pend_ints__h920232, + x__h240071, + x__h241228, + x__h254852, + x__h896543, + y__h920771; wire [13 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18828, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d18829, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16433, @@ -5189,83 +5189,83 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3425, b_base__h127527, b_base__h140443, - b_base__h183704, - b_base__h202455, - b_base__h217021, - b_base__h867085, - b_base__h867633, - b_base__h906770, - b_base__h907318, - b_base__h995134, + b_base__h183705, + b_base__h202456, + b_base__h217022, + b_base__h867083, + b_base__h867631, + b_base__h906773, + b_base__h907321, + b_base__h995138, checkForException___d20654, checkForException___d21604, - cr_addrBits__h866671, - cr_addrBits__h867219, - cr_addrBits__h906356, - cr_addrBits__h906904, - data_addrBits__h1018752, - data_addrBits__h1019606, - pc_addrBits__h994738, - r1__read_BITS_13_TO_0___h920777, - repBoundBits__h242650, + cr_addrBits__h866669, + cr_addrBits__h867217, + cr_addrBits__h906359, + cr_addrBits__h906907, + data_addrBits__h1018756, + data_addrBits__h1019610, + pc_addrBits__h994742, + r1__read_BITS_13_TO_0___h920781, + repBoundBits__h242652, res_addrBits__h126822, res_addrBits__h139734, - res_addrBits__h178897, - res_addrBits__h197662, - res_addrBits__h216421, - res_addrBits__h235321, - res_addrBits__h567344, + res_addrBits__h178898, + res_addrBits__h197663, + res_addrBits__h216422, + res_addrBits__h235323, + res_addrBits__h567345, res_addrBits__h568197, res_addrBits__h613954, res_addrBits__h659701, res_addrBits__h705510, res_addrBits__h706370, - res_addrBits__h848643, - res_addrBits__h892145, - result_d_addrBits__h1008602, - result_d_addrBits__h1009005, - result_d_addrBits__h1009422, - result_d_addrBits__h1009825, - result_d_addrBits__h1010494, - result_d_addrBits__h1031652, - result_d_addrBits__h1032055, - result_d_addrBits__h1032472, - result_d_addrBits__h1032875, - result_d_addrBits__h1033542, - toBoundsM1__h1008418, - toBoundsM1__h1008821, - toBoundsM1__h1009238, - toBoundsM1__h1009641, - toBoundsM1__h1010310, - toBoundsM1__h242654, - toBounds__h1008417, - toBounds__h1008820, - toBounds__h1009237, - toBounds__h1009640, - toBounds__h1010309, - toBounds__h242653, - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922, - x__h1000919, + res_addrBits__h848642, + res_addrBits__h892147, + result_d_addrBits__h1008606, + result_d_addrBits__h1009009, + result_d_addrBits__h1009426, + result_d_addrBits__h1009829, + result_d_addrBits__h1010498, + result_d_addrBits__h1031656, + result_d_addrBits__h1032059, + result_d_addrBits__h1032476, + result_d_addrBits__h1032879, + result_d_addrBits__h1033546, + toBoundsM1__h1008422, + toBoundsM1__h1008825, + toBoundsM1__h1009242, + toBoundsM1__h1009645, + toBoundsM1__h1010314, + toBoundsM1__h242656, + toBounds__h1008421, + toBounds__h1008824, + toBounds__h1009241, + toBounds__h1009644, + toBounds__h1010313, + toBounds__h242655, + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926, + x__h1000923, x__h127500, x__h127520, x__h140416, x__h140436, - x__h183677, - x__h183697, - x__h202428, - x__h202448, - x__h216994, - x__h217014, - x__h867058, - x__h867078, - x__h867606, - x__h867626, - x__h906743, - x__h906763, - x__h907291, - x__h907311, - x__h995107, - x__h995127; + x__h183678, + x__h183698, + x__h202429, + x__h202449, + x__h216995, + x__h217015, + x__h867056, + x__h867076, + x__h867604, + x__h867624, + x__h906746, + x__h906766, + x__h907294, + x__h907314, + x__h995111, + x__h995131; wire [12 : 0] IF_IF_coreFix_memExe_dTlb_procResp__257_BIT_27_ETC___d4757, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20987, IF_NOT_renameStage_rg_m_halt_req_0283_BIT_4_02_ETC___d20988, @@ -5303,43 +5303,43 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677, b_top__h127526, b_top__h140442, - b_top__h183703, - b_top__h202454, - b_top__h217020, - b_top__h867084, - b_top__h867632, - b_top__h906769, - b_top__h907317, - b_top__h995133, + b_top__h183704, + b_top__h202455, + b_top__h217021, + b_top__h867082, + b_top__h867630, + b_top__h906772, + b_top__h907320, + b_top__h995137, capChecks___d4160, - renaming_spec_bits__h968739, - result__h915808, - result__h915859, - spec_bits__h973790, + renaming_spec_bits__h968743, + result__h915812, + result__h915863, + spec_bits__h973794, topBits__h127429, topBits__h140345, - topBits__h183606, - topBits__h202357, - topBits__h216923, - topBits__h866986, - topBits__h867534, - topBits__h906671, - topBits__h907219, - topBits__h995036, - w__h915803, + topBits__h183607, + topBits__h202358, + topBits__h216924, + topBits__h866984, + topBits__h867532, + topBits__h906674, + topBits__h907222, + topBits__h995040, + w__h915807, x__h594834, x__h640583, x__h686330, x__h736366, x__h775219, x__h814523, - x__h915807, - x__h915858, - y__h915837, - y__h973803, - y_avValue_snd_fst__h963383, - y_avValue_snd_fst__h963425, - y_avValue_snd_fst__h963467; + x__h915811, + x__h915862, + y__h915841, + y__h973807, + y_avValue_snd_fst__h963387, + y_avValue_snd_fst__h963429, + y_avValue_snd_fst__h963471; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13207, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13209, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d13917, @@ -5459,7 +5459,7 @@ module mkCore(CLK, out_exp__h813099, out_exp__h822750, out_exp__h831534, - x__h998896; + x__h998900; wire [9 : 0] IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3635; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d10392, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d11789, @@ -5632,11 +5632,11 @@ module mkCore(CLK, out_f_exp__h611860, out_f_exp__h657609, out_f_exp__h703356, - x__h853091; + x__h853089; wire [6 : 0] NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320, - x__h244675, - x__h999622; + x__h244677, + x__h999626; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d11164, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d8370, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d9767, @@ -5665,19 +5665,19 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476, fetchStage_pipelines_0_first__0256_BIT_167_059_ETC___d20616, fetchStage_pipelines_1_first__0265_BIT_167_155_ETC___d21577, - x__h1000253, - x__h1000940, + x__h1000257, + x__h1000944, x__h127340, x__h140256, - x__h183517, - x__h202268, - x__h216834, - x__h866885, - x__h867433, - x__h906570, - x__h907118, - x__h994947, - x__h999596; + x__h183518, + x__h202269, + x__h216835, + x__h866883, + x__h867431, + x__h906573, + x__h907121, + x__h994951, + x__h999600; wire [4 : 0] IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20090, IF_IF_coreFix_aluExe_0_exeToFinQ_first__9946_B_ETC___d20091, IF_IF_coreFix_aluExe_1_exeToFinQ_first__7830_B_ETC___d17975, @@ -5720,11 +5720,11 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d10706, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d12103, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d9309, - cause_code__h996893, + cause_code__h996897, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156, - fflags__h1016351, - r1__read__h855836, + fflags__h1016355, + r1__read__h855834, res_fflags__h568237, res_fflags__h613991, res_fflags__h659738, @@ -5732,39 +5732,39 @@ module mkCore(CLK, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786, x__h148990, x__h152124, - x__h249475, - x__h249487, - x__h249499, - x__h249511, - x__h249523, - x__h249535, - x__h249547, - x__h249559, - x__h249571, - x__h249583, - x__h249595, - x__h249607, - x__h249619, - x__h249631, - x__h249643, - y__h249476, - y__h249488, - y__h249500, - y__h249512, - y__h249524, - y__h249536, - y__h249548, - y__h249560, - y__h249572, - y__h249584, - y__h249596, - y__h249608, - y__h249620, - y__h249632, - y__h249644, - y_avValue_snd_fst__h1015829, - y_avValue_snd_fst__h1016411, - y_avValue_snd_fst__h1016440; + x__h249477, + x__h249489, + x__h249501, + x__h249513, + x__h249525, + x__h249537, + x__h249549, + x__h249561, + x__h249573, + x__h249585, + x__h249597, + x__h249609, + x__h249621, + x__h249633, + x__h249645, + y__h249478, + y__h249490, + y__h249502, + y__h249514, + y__h249526, + y__h249538, + y__h249550, + y__h249562, + y__h249574, + y__h249586, + y__h249598, + y__h249610, + y__h249622, + y__h249634, + y__h249646, + y_avValue_snd_fst__h1015833, + y_avValue_snd_fst__h1016415, + y_avValue_snd_fst__h1016444; wire [3 : 0] IF_IF_coreFix_aluExe_0_dispToRegQ_first__8383__ETC___d19433, IF_IF_coreFix_aluExe_1_dispToRegQ_first__5620__ETC___d17317, IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20977, @@ -5809,7 +5809,7 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3390, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3433, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3632, - vm_mode_reg__read__h854731; + vm_mode_reg__read__h854729; wire [2 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19088, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16693, @@ -5826,57 +5826,57 @@ module mkCore(CLK, IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7096, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d24409, - _theResult_____2__h515366, - dcsr_cause__h994362, - next_deqP___1__h515611, - repBound__h237315, - repBound__h239000, - repBound__h248215, - repBound__h248740, - repBound__h854075, - repBound__h854397, - repBound__h855068, - repBound__h855389, - repBound__h855898, - repBound__h857576, - repBound__h860538, - repBound__h860556, - repBound__h867139, - repBound__h867687, - repBound__h898284, - repBound__h900611, - repBound__h900629, - repBound__h906824, - repBound__h907372, - repBound__h997634, - tb__h867136, - tb__h867684, - tb__h906821, - tb__h907369, + _theResult_____2__h515367, + dcsr_cause__h994366, + next_deqP___1__h515612, + repBound__h237317, + repBound__h239002, + repBound__h248217, + repBound__h248742, + repBound__h854073, + repBound__h854395, + repBound__h855066, + repBound__h855387, + repBound__h855896, + repBound__h857574, + repBound__h860536, + repBound__h860554, + repBound__h867137, + repBound__h867685, + repBound__h898287, + repBound__h900614, + repBound__h900632, + repBound__h906827, + repBound__h907375, + repBound__h997638, + tb__h867134, + tb__h867682, + tb__h906824, + tb__h907372, tmp_expBotHalf__h127295, tmp_expBotHalf__h140211, - tmp_expBotHalf__h183472, - tmp_expBotHalf__h202223, - tmp_expBotHalf__h216789, - tmp_expBotHalf__h866839, - tmp_expBotHalf__h867387, - tmp_expBotHalf__h906524, - tmp_expBotHalf__h907072, - tmp_expBotHalf__h994902, + tmp_expBotHalf__h183473, + tmp_expBotHalf__h202224, + tmp_expBotHalf__h216790, + tmp_expBotHalf__h866837, + tmp_expBotHalf__h867385, + tmp_expBotHalf__h906527, + tmp_expBotHalf__h907075, + tmp_expBotHalf__h994906, tmp_expTopHalf__h127293, tmp_expTopHalf__h140209, - tmp_expTopHalf__h183470, - tmp_expTopHalf__h202221, - tmp_expTopHalf__h216787, - tmp_expTopHalf__h866837, - tmp_expTopHalf__h867385, - tmp_expTopHalf__h906522, - tmp_expTopHalf__h907070, - tmp_expTopHalf__h994900, - v__h514822, - v__h515017, - x__h521673, - x_decodeInfo_frm__h926246; + tmp_expTopHalf__h183471, + tmp_expTopHalf__h202222, + tmp_expTopHalf__h216788, + tmp_expTopHalf__h866835, + tmp_expTopHalf__h867383, + tmp_expTopHalf__h906525, + tmp_expTopHalf__h907073, + tmp_expTopHalf__h994904, + v__h514823, + v__h515018, + x__h521674, + x_decodeInfo_frm__h926250; wire [1 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19029, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19030, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16634, @@ -5915,21 +5915,21 @@ module mkCore(CLK, IF_theResult___snd93170_BIT_33_THEN_2_ELSE_0__q43, carry_out__h127431, carry_out__h140347, - carry_out__h183608, - carry_out__h202359, - carry_out__h216925, - carry_out__h866988, - carry_out__h867536, - carry_out__h906673, - carry_out__h907221, - carry_out__h995038, - coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6, + carry_out__h183609, + carry_out__h202360, + carry_out__h216926, + carry_out__h866986, + carry_out__h867534, + carry_out__h906676, + carry_out__h907224, + carry_out__h995042, + coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4, coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2, - coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4, - cr_reserved__h866674, - cr_reserved__h867222, - cr_reserved__h906359, - cr_reserved__h906907, + coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6, + cr_reserved__h866672, + cr_reserved__h867220, + cr_reserved__h906362, + cr_reserved__h906910, guard__h576462, guard__h585171, guard__h594101, @@ -5953,47 +5953,47 @@ module mkCore(CLK, guard__h822861, impliedTopBits__h127433, impliedTopBits__h140349, - impliedTopBits__h183610, - impliedTopBits__h202361, - impliedTopBits__h216927, - impliedTopBits__h866990, - impliedTopBits__h867538, - impliedTopBits__h906675, - impliedTopBits__h907223, - impliedTopBits__h995040, + impliedTopBits__h183611, + impliedTopBits__h202362, + impliedTopBits__h216928, + impliedTopBits__h866988, + impliedTopBits__h867536, + impliedTopBits__h906678, + impliedTopBits__h907226, + impliedTopBits__h995044, len_correction__h127432, len_correction__h140348, - len_correction__h183609, - len_correction__h202360, - len_correction__h216926, - len_correction__h866989, - len_correction__h867537, - len_correction__h906674, - len_correction__h907222, - len_correction__h995039, - prv__h1017444, - prv__h1017488, - r1__read_BITS_13_TO_12___h926452, + len_correction__h183610, + len_correction__h202361, + len_correction__h216927, + len_correction__h866987, + len_correction__h867535, + len_correction__h906677, + len_correction__h907225, + len_correction__h995043, + prv__h1017448, + prv__h1017492, + r1__read_BITS_13_TO_12___h926456, sbIdx__h152015, v__h836639, v__h836649, v__h837284, - wordIdx__h263231, - x__h1012317, - x__h1016599, + wordIdx__h263233, + x__h1012321, + x__h1016603, x__h127517, x__h140433, - x__h183694, - x__h202445, - x__h217011, - x__h867075, - x__h867623, - x__h906760, - x__h907308, - x__h995124, - y_avValue_snd_snd_snd_fst__h1015839, - y_avValue_snd_snd_snd_fst__h1016421, - y_avValue_snd_snd_snd_fst__h1016450; + x__h183695, + x__h202446, + x__h217012, + x__h867073, + x__h867621, + x__h906763, + x__h907311, + x__h995128, + y_avValue_snd_snd_snd_fst__h1015843, + y_avValue_snd_snd_snd_fst__h1016425, + y_avValue_snd_snd_snd_fst__h1016454; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10589, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10639, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d11986, @@ -6736,12 +6736,12 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h526143, - _theResult_____2__h533236, - _theResult_____2__h543871, - _theResult_____2__h557704, - _theResult_____2__h561483, - cause_interrupt__h995316, + _theResult_____2__h526144, + _theResult_____2__h533237, + _theResult_____2__h543872, + _theResult_____2__h557705, + _theResult_____2__h561484, + cause_interrupt__h995320, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22508, commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22613, @@ -7125,10 +7125,10 @@ module mkCore(CLK, coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029, - cr_flags__h866673, - cr_flags__h867221, - cr_flags__h906358, - cr_flags__h906906, + cr_flags__h866671, + cr_flags__h867219, + cr_flags__h906361, + cr_flags__h906909, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, @@ -7186,21 +7186,21 @@ module mkCore(CLK, guard__h736233, guard__h775086, guard__h814390, - idx__h968878, - k__h945028, + idx__h968882, + k__h945032, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21071, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d21091, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22008, mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d22010, - next_deqP___1__h526388, - next_deqP___1__h533666, - next_deqP___1__h544301, - next_deqP___1__h557949, - next_deqP___1__h561728, - r1__read_BIT_20___h926958, - r__h853138, - r__h855582, + next_deqP___1__h526389, + next_deqP___1__h533667, + next_deqP___1__h544302, + next_deqP___1__h557950, + next_deqP___1__h561729, + r1__read_BIT_20___h926962, + r__h853136, + r__h855580, regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039, regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854, regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180, @@ -7244,20 +7244,20 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12443, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d2768, - v__h516842, - v__h517222, - v__h532561, - v__h532756, - v__h535010, - v__h535205, - v__h556030, - v__h556225, - v__h559809, - v__h560004, + v__h516843, + v__h517223, + v__h532562, + v__h532757, + v__h535011, + v__h535206, + v__h556031, + v__h556226, + v__h559810, + v__h560005, value_BIT_52___h677325, - x__h240138, - x__h241295, - x__h254919, + x__h240140, + x__h241297, + x__h254921, x__h836140; // action method coreReq_start @@ -11325,15 +11325,15 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[630:502], - addr__h989734, + addr__h989738, CASE_robdeqPort_0_deq_data_BITS_273_TO_272_0__ETC__q328, rob$deqPort_0_deq_data[501:470] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h1016374 ; + commitStage_rg_serial_num + y__h1016378 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = - (k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && + (k__h945032 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -11351,7 +11351,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11459,7 +11459,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[221:158], - x__h501096 } ; + x__h501097 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 521'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d7036 } ; @@ -11469,7 +11469,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h505614, + addr__h505615, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7144 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11501,7 +11501,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[580:578] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h509110, + resp_addr__h509111, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11509,8 +11509,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h1017488, - prv__h1017488 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h1017492, + prv__h1017492 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -11579,39 +11579,39 @@ module mkCore(CLK, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d4891 } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = - { x__h914618, - new_pc__h912071, + { x__h914622, + new_pc__h912075, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 = - { x__h914618, - new_pc__h912071, + { x__h914622, + new_pc__h912075, coreFix_aluExe_0_exeToFinQ$first[1066:1062], coreFix_aluExe_0_exeToFinQ$first[297], coreFix_aluExe_0_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_0_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 = - { x__h879902, - new_pc__h872924, + { x__h879901, + new_pc__h872923, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd0, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 = - { x__h879902, - new_pc__h872924, + { x__h879901, + new_pc__h872923, coreFix_aluExe_1_exeToFinQ$first[1066:1062], coreFix_aluExe_1_exeToFinQ$first[297], coreFix_aluExe_1_exeToFinQ$first[1040:1017], 1'd1, coreFix_aluExe_1_exeToFinQ$first[1016] } ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h1016351 ; + csrf_fflags_reg | fflags__h1016355 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd1) ? @@ -11662,21 +11662,21 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd27) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318, - result_d_address__h1009824, - result_d_addrBits__h1009825, + result_d_address__h1009828, + result_d_addrBits__h1009829, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_mepcc_reg_data_lat_1$wset_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238, - result_d_address__h1032874, - result_d_addrBits__h1032875, + result_d_address__h1032878, + result_d_addrBits__h1032879, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d23337 } ; assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h1014147 + 64'd1 ; + n__read__h1014151 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h1014147 + { 62'd0, x__h1016599 } ; + n__read__h1014151 + { 62'd0, x__h1016603 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == @@ -11688,21 +11688,21 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd24) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274, - result_d_address__h1009421, - result_d_addrBits__h1009422, + result_d_address__h1009425, + result_d_addrBits__h1009426, csrf_mtcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_mtcc_reg$write_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218, - result_d_address__h1032471, - result_d_addrBits__h1032472, + result_d_address__h1032475, + result_d_addrBits__h1032476, csrf_mtcc_reg[71:0] } ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - always@(commitStage_commitTrap or trap_val__h997075 or trap_val__h996922) + always@(commitStage_commitTrap or trap_val__h997079 or trap_val__h996926) begin case (commitStage_commitTrap[44:43]) - 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997075; - 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996922; + 2'd0: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h997079; + 2'd1: MUX_csrf_mtval_csr$write_1__VAL_3 = trap_val__h996926; default: MUX_csrf_mtval_csr$write_1__VAL_3 = 64'd0; endcase end @@ -11724,7 +11724,7 @@ module mkCore(CLK, 6'd42) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[469:465] == 5'd24) ? - x__h1012317 : + x__h1012321 : csrf_mpp_reg) ; assign MUX_csrf_prv_reg$write_1__VAL_3 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? @@ -11734,44 +11734,44 @@ module mkCore(CLK, assign MUX_csrf_rg_dcsr$write_1__VAL_3 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h994362, + dcsr_cause__h994366, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_rg_dpc$write_1__VAL_1 = { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432, - result_d_address__h1010493, - result_d_addrBits__h1010494, + result_d_address__h1010497, + result_d_addrBits__h1010498, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309, - result_d_address__h1033541, - result_d_addrBits__h1033542, + result_d_address__h1033545, + result_d_addrBits__h1033546, csrf_rg_dpc[71:0] } ; assign MUX_csrf_rg_dpc$write_1__VAL_3 = { commitStage_commitTrap[237], - pc_address__h994737, - pc_addrBits__h994738, + pc_address__h994741, + pc_addrBits__h994742, commitStage_commitTrap[236:221], commitStage_commitTrap[218], commitStage_commitTrap[220:219], ~commitStage_commitTrap[217:199], IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580, - x__h995107, - x__h995127 } ; + x__h995111, + x__h995131 } ; assign MUX_csrf_rg_tselect$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_1 = (rob$deqPort_0_deq_data[469:465] == 5'd17 && IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd13) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181, - result_d_address__h1009004, - result_d_addrBits__h1009005, + result_d_address__h1009008, + result_d_addrBits__h1009009, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_sepcc_reg_data_lat_1$wset_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160, - result_d_address__h1032054, - result_d_addrBits__h1032055, + result_d_address__h1032058, + result_d_addrBits__h1032059, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d23200 } ; assign MUX_csrf_spp_reg$write_1__VAL_1 = rob$deqPort_0_deq_data[469:465] == 5'd17 && @@ -11785,17 +11785,17 @@ module mkCore(CLK, IF_rob_deqPort_0_deq_data__2261_BIT_288_2920_T_ETC___d23014 == 6'd10) ? { IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135, - result_d_address__h1008601, - result_d_addrBits__h1008602, + result_d_address__h1008605, + result_d_addrBits__h1008606, csrf_stcc_reg[71:0] } : rob$deqPort_0_deq_data[194:42] ; assign MUX_csrf_stcc_reg$write_1__VAL_2 = { f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138, - result_d_address__h1031651, - result_d_addrBits__h1031652, + result_d_address__h1031655, + result_d_addrBits__h1031656, csrf_stcc_reg[71:0] } ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1020024 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h1020028 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1[149:86] } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -11811,14 +11811,14 @@ module mkCore(CLK, IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[14:3], ~IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[2], IF_IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_I_ETC___d22896[1:0], - thin_address__h999417 } ; + thin_address__h999421 } ; always@(rob$deqPort_0_deq_data or - next_pc__h1012257 or v__h1012296 or v__h1013005) + next_pc__h1012261 or v__h1012300 or v__h1013009) begin case (rob$deqPort_0_deq_data[469:465]) - 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012296; - 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1013005; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012257; + 5'd24: MUX_fetchStage$redirect_1__VAL_5 = v__h1012300; + 5'd25: MUX_fetchStage$redirect_1__VAL_5 = v__h1013009; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h1012261; endcase end assign MUX_fetchStage$redirect_1__VAL_6 = @@ -11865,8 +11865,8 @@ module mkCore(CLK, 112'hAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_1 = { 1'd0, - res_address__h567343, - res_addrBits__h567344, + res_address__h567344, + res_addrBits__h567345, 72'h00001FFFFF44000000 } ; assign MUX_rf$write_2_wr_2__VAL_2 = { 1'd0, @@ -11914,27 +11914,27 @@ module mkCore(CLK, assign MUX_rf$write_3_wr_2__VAL_3 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && coreFix_memExe_respLrScAmoQ_data_0[128], - res_address__h178896, - res_addrBits__h178897, - x__h183397[127:112], - x__h183397[109], - x__h183397[111:110], - ~x__h183397[108:90], + res_address__h178897, + res_addrBits__h178898, + x__h183398[127:112], + x__h183398[109], + x__h183398[111:110], + ~x__h183398[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 } ; assign MUX_rf$write_3_wr_2__VAL_4 = { coreFix_memExe_lsq$firstLd[125:110] == 16'd65535 && mmio_dataRespQ_data_0[128], - res_address__h197661, - res_addrBits__h197662, - x__h199249[127:112], - x__h199249[109], - x__h199249[111:110], - ~x__h199249[108:90], + res_address__h197662, + res_addrBits__h197663, + x__h199250[127:112], + x__h199250[109], + x__h199250[111:110], + ~x__h199250[108:90], IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 } ; assign MUX_rf$write_3_wr_2__VAL_5 = { coreFix_memExe_lsq$respLd[128], - res_address__h216420, - res_addrBits__h216421, + res_address__h216421, + res_addrBits__h216422, coreFix_memExe_lsq$respLd[127:112], coreFix_memExe_lsq$respLd[109], coreFix_memExe_lsq$respLd[111:110], @@ -11942,13 +11942,13 @@ module mkCore(CLK, IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 } ; assign MUX_rf$write_4_wr_2__VAL_1 = { 1'd1, - data_address__h1018751, - data_addrBits__h1018752, + data_address__h1018755, + data_addrBits__h1018756, 72'hFFFF1FFFFF44000000 } ; assign MUX_rf$write_4_wr_2__VAL_2 = { 1'd0, - data_address__h1019605, - data_addrBits__h1019606, + data_address__h1019609, + data_addrBits__h1019610, 72'h00001FFFFF44000000 } ; assign MUX_rob$enqPort_0_enq_1__VAL_1 = { fetchStage$pipelines_0_first[591:463], @@ -12531,7 +12531,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - _theResult_____2__h515366 ; + _theResult_____2__h515367 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12550,7 +12550,7 @@ module mkCore(CLK, assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ? 3'd0 : - v__h514822 ; + v__h514823 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12592,7 +12592,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - _theResult_____2__h526143 ; + _theResult_____2__h526144 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12611,7 +12611,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl && - v__h516842 ; + v__h516843 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12708,7 +12708,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - _theResult_____2__h533236 ; + _theResult_____2__h533237 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12724,7 +12724,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl && - v__h532561 ; + v__h532562 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12744,7 +12744,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h535372, + { x_addr__h535373, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[518:517] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[518:517], @@ -12771,7 +12771,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - _theResult_____2__h543871 ; + _theResult_____2__h543872 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12790,7 +12790,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl && - v__h535010 ; + v__h535011 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12866,7 +12866,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = !coreFix_memExe_forwardQ_clearReq_rl && - _theResult_____2__h561483 ; + _theResult_____2__h561484 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12881,7 +12881,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = - !coreFix_memExe_forwardQ_clearReq_rl && v__h559809 ; + !coreFix_memExe_forwardQ_clearReq_rl && v__h559810 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12922,7 +12922,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = !coreFix_memExe_memRespLdQ_clearReq_rl && - _theResult_____2__h557704 ; + _theResult_____2__h557705 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12937,7 +12937,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = - !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556030 ; + !coreFix_memExe_memRespLdQ_clearReq_rl && v__h556031 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13298,14 +13298,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995318) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_code__h995322) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_code_reg$D_IN = cause_code__h995318; + csrf_mcause_code_reg$D_IN = cause_code__h995322; default: csrf_mcause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_mcause_code_reg$EN = @@ -13324,7 +13324,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_mcause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995316) + MUX_csrf_ie_vec_3$write_1__SEL_3 or cause_interrupt__h995320) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_interrupt_reg$D_IN = @@ -13332,7 +13332,7 @@ module mkCore(CLK, MUX_csrf_mcause_code_reg$write_1__SEL_2: csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_3$write_1__SEL_3: - csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995316; + csrf_mcause_interrupt_reg$D_IN = cause_interrupt__h995320; default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_mcause_interrupt_reg$EN = @@ -13519,7 +13519,7 @@ module mkCore(CLK, assign csrf_minstret_ehr_data_rl$D_IN = csrf_minstret_ehr_data_lat_1$whas ? upd__h3066 : - n__read__h1014147 ; + n__read__h1014151 ; assign csrf_minstret_ehr_data_rl$EN = 1'd1 ; // register csrf_mpp_reg @@ -13877,14 +13877,14 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995318) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_code__h995322) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0]; MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[4:0]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_code_reg$D_IN = cause_code__h995318; + csrf_scause_code_reg$D_IN = cause_code__h995322; default: csrf_scause_code_reg$D_IN = 5'b01010 /* unspecified value */ ; endcase assign csrf_scause_code_reg$EN = @@ -13903,7 +13903,7 @@ module mkCore(CLK, MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_scause_code_reg$write_1__SEL_2 or f_csr_reqs$D_OUT or - MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995316) + MUX_csrf_ie_vec_1$write_1__SEL_3 or cause_interrupt__h995320) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_interrupt_reg$D_IN = @@ -13911,7 +13911,7 @@ module mkCore(CLK, MUX_csrf_scause_code_reg$write_1__SEL_2: csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63]; MUX_csrf_ie_vec_1$write_1__SEL_3: - csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995316; + csrf_scause_interrupt_reg$D_IN = cause_interrupt__h995320; default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ; endcase assign csrf_scause_interrupt_reg$EN = @@ -15079,7 +15079,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && + (k__h945032 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015) ? { fetchStage$pipelines_0_first[273:269], IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d20382, @@ -15097,7 +15097,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[329:306], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15745,7 +15745,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__0265_BITS_268_ETC___d21343, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -15899,7 +15899,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h501096 ; + x__h501097 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[582:581] == 2'd0) ? @@ -16331,7 +16331,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22059) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968739 ; + renaming_spec_bits__h968743 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? @@ -16351,7 +16351,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__1151_AND__ETC___d22068) ? specTagManager$currentSpecBits : - renaming_spec_bits__h968739 ; + renaming_spec_bits__h968743 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -16380,8 +16380,8 @@ module mkCore(CLK, MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ; assign coreFix_memExe_lsq$respLd_t = WILL_FIRE_RL_coreFix_memExe_doRespLdMem ? - t__h212839 : - t__h215125 ; + t__h212840 : + t__h215126 ; assign coreFix_memExe_lsq$setAtCommit_0_put = rob$deqPort_0_deq_data[24:19] ; assign coreFix_memExe_lsq$setAtCommit_1_put = @@ -16434,7 +16434,7 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } : - { pointer__h242635[3:0] == 4'd0 && + { pointer__h242637[3:0] == 4'd0 && coreFix_memExe_lsq$getOrigBE[0] && coreFix_memExe_lsq$getOrigBE[1] && coreFix_memExe_lsq$getOrigBE[2] && @@ -16604,7 +16604,7 @@ module mkCore(CLK, !fetchStage$pipelines_1_first[239], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h968739, + renaming_spec_bits__h968743, fetchStage$pipelines_1_first[268:266] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -17017,9 +17017,9 @@ module mkCore(CLK, always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or MUX_fetchStage$redirect_1__VAL_1 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or - new_pc__h872924 or + new_pc__h872923 or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or - new_pc__h912071 or + new_pc__h912075 or WILL_FIRE_RL_commitStage_doCommitKilledLd or rob$deqPort_0_deq_data or WILL_FIRE_RL_commitStage_doCommitSystemInst or @@ -17030,9 +17030,9 @@ module mkCore(CLK, MUX_commitStage_rg_serial_num$write_1__SEL_1: fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h872924; + fetchStage$redirect_pc = new_pc__h872923; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: - fetchStage$redirect_pc = new_pc__h912071; + fetchStage$redirect_pc = new_pc__h912075; WILL_FIRE_RL_commitStage_doCommitKilledLd: fetchStage$redirect_pc = rob$deqPort_0_deq_data[630:502]; WILL_FIRE_RL_commitStage_doCommitSystemInst: @@ -17222,7 +17222,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h968739 ; + renaming_spec_bits__h968743 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[96:70] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17499,7 +17499,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__0265_BITS_265_ETC___d22188, IF_NOT_fetchStage_pipelines_1_first__0265_BITS_ETC___d22242, 7'd32, - renaming_spec_bits__h968739 } ; + renaming_spec_bits__h968743 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -18062,11 +18062,11 @@ module mkCore(CLK, module_amoExec instance_amoExec_5(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 4'd8 }), .amoExec_wordIdx(2'd0), - .amoExec_current({ 128'd0, r__h855582 }), + .amoExec_current({ 128'd0, r__h855580 }), .amoExec_inpt({ 97'd0, x__h65639 }), .amoExec(amoExec___d773)); module_amoExec instance_amoExec_4(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[11:4]), - .amoExec_wordIdx(wordIdx__h263231), + .amoExec_wordIdx(wordIdx__h263233), .amoExec_current({ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4854, { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867 } }), @@ -18083,12 +18083,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[81:77], { fetchStage$pipelines_0_first[76], fetchStage$pipelines_0_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926246, - r1__read_BITS_13_TO_12___h926452 != + .checkForException_csrState({ x_decodeInfo_frm__h926250, + r1__read_BITS_13_TO_12___h926456 != 2'd0, - { prv__h1017444, + { prv__h1017448, csrf_tvm_reg, - { r1__read_BIT_20___h926958, + { r1__read_BIT_20___h926962, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18114,12 +18114,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[81:77], { fetchStage$pipelines_1_first[76], fetchStage$pipelines_1_first[75:70] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h926246, - r1__read_BITS_13_TO_12___h926452 != + .checkForException_csrState({ x_decodeInfo_frm__h926250, + r1__read_BITS_13_TO_12___h926456 != 2'd0, - { prv__h1017444, + { prv__h1017448, csrf_tvm_reg, - { r1__read_BIT_20___h926958, + { r1__read_BIT_20___h926962, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -18130,14 +18130,14 @@ module mkCore(CLK, { csrf_mcounteren_tm_reg, csrf_mcounteren_tm_reg && csrf_scounteren_tm_reg } } } } } }), - .checkForException_pcc(pc__h963240), + .checkForException_pcc(pc__h963244), .checkForException_fourByteInst(fetchStage$pipelines_1_first[98:97] == 2'b11), .checkForException(checkForException___d21604)); module_capChecks instance_capChecks_0(.capChecks_a(coreFix_memExe_regToExeQ$first[384:222]), .capChecks_b(coreFix_memExe_regToExeQ$first[221:59]), .capChecks_ddc({ csrf_ddc_reg, - repBound__h248740, + repBound__h248742, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), @@ -18148,13 +18148,13 @@ module mkCore(CLK, .prepareBoundsCheck_b(coreFix_memExe_regToExeQ$first[221:59]), .prepareBoundsCheck_pcc(163'h400000000000000000003FFFC7FFFFD10000003F0), .prepareBoundsCheck_ddc({ csrf_ddc_reg, - repBound__h248740, + repBound__h248742, { csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143, csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144, csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 } }), - .prepareBoundsCheck_vaddr(tmpAddr__h242834), - .prepareBoundsCheck_size(x__h249475 + - y__h249476), + .prepareBoundsCheck_vaddr(tmpAddr__h242836), + .prepareBoundsCheck_size(x__h249477 + + y__h249478), .prepareBoundsCheck_toCheck(coreFix_memExe_regToExeQ$first[58:12]), .prepareBoundsCheck(prepareBoundsCheck___d4244)); module_execFpuSimple instance_execFpuSimple_3(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], @@ -18174,24 +18174,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_1_regToExeQ$first[306], - { cr_address__h866670, - cr_addrBits__h866671, + { cr_address__h866668, + cr_addrBits__h866669, { coreFix_aluExe_1_regToExeQ$first[305:290], - { cr_flags__h866673, - cr_reserved__h866674 }, + { cr_flags__h866671, + cr_reserved__h866672 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 } }, - repBound__h867139, + repBound__h867137, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 } }), .basicExec_ppc({ coreFix_aluExe_1_regToExeQ$first[177], - { cr_address__h867218, - cr_addrBits__h867219, + { cr_address__h867216, + cr_addrBits__h867217, { coreFix_aluExe_1_regToExeQ$first[176:161], - { cr_flags__h867221, - cr_reserved__h867222 }, + { cr_flags__h867219, + cr_reserved__h867220 }, INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 } }, - repBound__h867687, + repBound__h867685, { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727, IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 } }), @@ -18208,24 +18208,24 @@ module mkCore(CLK, .basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[632:470]), .basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[469:307]), .basicExec_pcc({ coreFix_aluExe_0_regToExeQ$first[306], - { cr_address__h906355, - cr_addrBits__h906356, + { cr_address__h906358, + cr_addrBits__h906359, { coreFix_aluExe_0_regToExeQ$first[305:290], - { cr_flags__h906358, - cr_reserved__h906359 }, + { cr_flags__h906361, + cr_reserved__h906362 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 } }, - repBound__h906824, + repBound__h906827, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 } }), .basicExec_ppc({ coreFix_aluExe_0_regToExeQ$first[177], - { cr_address__h906903, - cr_addrBits__h906904, + { cr_address__h906906, + cr_addrBits__h906907, { coreFix_aluExe_0_regToExeQ$first[176:161], - { cr_flags__h906906, - cr_reserved__h906907 }, + { cr_flags__h906909, + cr_reserved__h906910 }, INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 } }, - repBound__h907372, + repBound__h907375, { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843, IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 } }), @@ -20287,11 +20287,11 @@ module mkCore(CLK, CASE_guard83557_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q213 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q214) ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323 = - (_theResult____h920230 == 16'd0 && + (_theResult____h920234 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h920801 : - _theResult____h920230 ; + enabled_ints__h920805 : + _theResult____h920234 ; assign IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20676 = IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[0] || IF_IF_NOT_csrf_prv_reg_read__0286_EQ_3_0287_02_ETC___d20323[1] || @@ -21094,7 +21094,7 @@ module mkCore(CLK, !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d13513 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d15164 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 = - _theResult_____2__h515366 == v__h514822 ; + _theResult_____2__h515367 == v__h514823 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7257 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_cRqR_ETC___d7249 && (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 || @@ -21109,7 +21109,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 = - _theResult_____2__h526143 == v__h516842 ; + _theResult_____2__h526144 == v__h516843 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7349 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_from_ETC___d7340 && (IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 || @@ -21138,9 +21138,9 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[518:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[518:3], - x__h521673 } ; + x__h521674 } ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 = - _theResult_____2__h533236 == v__h532561 ; + _theResult_____2__h533237 == v__h532562 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7508 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rqTo_ETC___d7500 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 || @@ -21155,7 +21155,7 @@ module mkCore(CLK, (IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 = - _theResult_____2__h543871 == v__h535010 ; + _theResult_____2__h543872 == v__h535011 ; assign IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7592 = IF_IF_coreFix_memExe_dMem_cache_m_banks_0_rsTo_ETC___d7584 && (IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 || @@ -21552,7 +21552,7 @@ module mkCore(CLK, 5'd15 : 5'd28))))))))))))) } ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 = - _theResult_____2__h561483 == v__h559809 ; + _theResult_____2__h561484 == v__h559810 ; assign IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7878 = IF_IF_coreFix_memExe_forwardQ_deqReq_lat_1_wha_ETC___d7870 && (IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 || @@ -21567,7 +21567,7 @@ module mkCore(CLK, (IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 || coreFix_memExe_forwardQ_empty) ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 = - _theResult_____2__h557704 == v__h556030 ; + _theResult_____2__h557705 == v__h556031 ; assign IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7796 = IF_IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_w_ETC___d7788 && (IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 || @@ -21585,12 +21585,12 @@ module mkCore(CLK, (csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? !csrf_stcc_reg[34] : !csrf_mtcc_reg[34]) ? - { x__h1000919[11:0], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 } : - { x__h1000919[11:3], - x__h1000940[5:3], - x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922[13:3], - x__h1000940[2:0] } ; + { x__h1000923[11:0], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926 } : + { x__h1000923[11:3], + x__h1000944[5:3], + x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926[13:3], + x__h1000944[2:0] } ; assign IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? !csrf_rg_dcsr[2] && @@ -21832,46 +21832,46 @@ module mkCore(CLK, IF_IF_renameStage_rg_m_halt_req_0283_BIT_4_028_ETC___d20984 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? - x__h1008531[13:0] >= toBounds__h1008417 : - x__h1008531[13:0] <= toBoundsM1__h1008418 ; + x__h1008535[13:0] >= toBounds__h1008421 : + x__h1008535[13:0] <= toBoundsM1__h1008422 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1008934[13:0] >= toBounds__h1008820 : - x__h1008934[13:0] <= toBoundsM1__h1008821 ; + x__h1008938[13:0] >= toBounds__h1008824 : + x__h1008938[13:0] <= toBoundsM1__h1008825 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? - x__h1009351[13:0] >= toBounds__h1009237 : - x__h1009351[13:0] <= toBoundsM1__h1009238 ; + x__h1009355[13:0] >= toBounds__h1009241 : + x__h1009355[13:0] <= toBoundsM1__h1009242 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 = MUX_csrf_rg_dcsr$write_1__VAL_1[63] ? - x__h1009754[13:0] >= toBounds__h1009640 : - x__h1009754[13:0] <= toBoundsM1__h1009641 ; + x__h1009758[13:0] >= toBounds__h1009644 : + x__h1009758[13:0] <= toBoundsM1__h1009645 ; assign IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63] ? - x__h1010423[13:0] >= toBounds__h1010309 : - x__h1010423[13:0] <= toBoundsM1__h1010310 ; + x__h1010427[13:0] >= toBounds__h1010313 : + x__h1010427[13:0] <= toBoundsM1__h1010314 ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d1954 = - { INV_x83397_BITS_108_TO_90__q34[0] ? x__h183517 : 6'd0, - x__h183677, - x__h183697 } ; + { INV_x83398_BITS_108_TO_90__q34[0] ? x__h183518 : 6'd0, + x__h183678, + x__h183698 } ; assign IF_INV_IF_coreFix_memExe_lsq_firstLd__498_BITS_ETC___d2120 = - { INV_x99249_BITS_108_TO_90__q36[0] ? x__h202268 : 6'd0, - x__h202428, - x__h202448 } ; + { INV_x99250_BITS_108_TO_90__q36[0] ? x__h202269 : 6'd0, + x__h202429, + x__h202449 } ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? - x__h994947 : + x__h994951 : 6'd0 ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 = - x__h995127[13:11] < repBound__h997634 ; + x__h995131[13:11] < repBound__h997638 ; assign IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664 = - pc_addrBits__h994738[13:11] < repBound__h997634 ; + pc_addrBits__h994742[13:11] < repBound__h997638 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 = - tb__h906821 < repBound__h906824 ; + tb__h906824 < repBound__h906827 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19779 = - x__h906763[13:11] < repBound__h906824 ; + x__h906766[13:11] < repBound__h906827 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781 = - cr_addrBits__h906356[13:11] < repBound__h906824 ; + cr_addrBits__h906359[13:11] < repBound__h906827 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19791 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19781, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19778 == @@ -21889,11 +21889,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 = - tb__h907369 < repBound__h907372 ; + tb__h907372 < repBound__h907375 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19843 = - x__h907311[13:11] < repBound__h907372 ; + x__h907314[13:11] < repBound__h907375 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845 = - cr_addrBits__h906904[13:11] < repBound__h907372 ; + cr_addrBits__h906907[13:11] < repBound__h907375 ; assign IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19855 = { IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19845, (IF_INV_coreFix_aluExe_0_regToExeQ_first__9457__ETC___d19842 == @@ -21911,11 +21911,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 = - tb__h867136 < repBound__h867139 ; + tb__h867134 < repBound__h867137 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17663 = - x__h867078[13:11] < repBound__h867139 ; + x__h867076[13:11] < repBound__h867137 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665 = - cr_addrBits__h866671[13:11] < repBound__h867139 ; + cr_addrBits__h866669[13:11] < repBound__h867137 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17675 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17665, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17662 == @@ -21933,11 +21933,11 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 = - tb__h867684 < repBound__h867687 ; + tb__h867682 < repBound__h867685 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17727 = - x__h867626[13:11] < repBound__h867687 ; + x__h867624[13:11] < repBound__h867685 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729 = - cr_addrBits__h867219[13:11] < repBound__h867687 ; + cr_addrBits__h867217[13:11] < repBound__h867685 ; assign IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17739 = { IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17729, (IF_INV_coreFix_aluExe_1_regToExeQ_first__7341__ETC___d17726 == @@ -21956,10 +21956,10 @@ module mkCore(CLK, 2'd3) } ; assign IF_INV_coreFix_memExe_lsq_respLd_159_BITS_108__ETC___d2210 = { INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216834 : + x__h216835 : 6'd0, - x__h216994, - x__h217014 } ; + x__h216995, + x__h217015 } ; assign IF_INV_coreFix_memExe_respLrScAmoQ_data_0_233__ETC___d1273 = { INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? x__h127340 : @@ -23890,11 +23890,11 @@ module mkCore(CLK, _theResult___fst_exp__h611014 != 8'd255 && guard__h602937 != 2'b0 ; assign IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 = - offset__h242625[63] ? - x__h242774[13:0] >= toBounds__h242653 && - repBoundBits__h242650 != + offset__h242627[63] ? + x__h242776[13:0] >= toBounds__h242655 && + repBoundBits__h242652 != coreFix_memExe_regToExeQ$first[317:304] : - x__h242774[13:0] < toBoundsM1__h242654 ; + x__h242776[13:0] < toBoundsM1__h242656 ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__8382_ETC___d18414 = (coreFix_aluExe_0_dispToRegQ$RDY_first && coreFix_aluExe_0_bypassWire_0$whas && @@ -23982,24 +23982,24 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18608 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18820 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_address__h892144 : + res_address__h892146 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18818 : 66'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d18835 = coreFix_aluExe_0_dispToRegQ$first[137] ? - res_addrBits__h892145 : + res_addrBits__h892147 : ((coreFix_aluExe_0_dispToRegQ$first[85] && coreFix_aluExe_0_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d18833 : 14'd0) ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_reserved__h899111 : + thin_reserved__h899114 : 2'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_otype__h899112 : + thin_otype__h899115 : 18'd262143, !coreFix_aluExe_0_dispToRegQ$first[124] || IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19382, @@ -24008,7 +24008,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_perms_soft__h899287 : + thin_perms_soft__h899290 : 4'd0, coreFix_aluExe_0_dispToRegQ$first[124] && IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19240, @@ -24039,18 +24039,18 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19394 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396 = { coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_address__h899107 : + thin_address__h899110 : 66'd0, coreFix_aluExe_0_dispToRegQ$first[124] ? - thin_addrBits__h899108 : + thin_addrBits__h899111 : 14'd0, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19395 } ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19417 = - thin_bounds_topBits__h900513[13:11] < repBound__h900629 ; + thin_bounds_topBits__h900516[13:11] < repBound__h900632 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19419 = - thin_bounds_baseBits__h900514[13:11] < repBound__h900629 ; + thin_bounds_baseBits__h900517[13:11] < repBound__h900632 ; assign IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19422 = - thin_addrBits__h899108[13:11] < repBound__h900629 ; + thin_addrBits__h899111[13:11] < repBound__h900632 ; assign IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20092 = { (coreFix_aluExe_0_exeToFinQ$first[282] && !coreFix_aluExe_0_exeToFinQ$first[294]) ? @@ -24297,24 +24297,24 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d15845 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16425 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_address__h848642 : + res_address__h848641 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16423 : 66'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16440 = coreFix_aluExe_1_dispToRegQ$first[137] ? - res_addrBits__h848643 : + res_addrBits__h848642 : ((coreFix_aluExe_1_dispToRegQ$first[85] && coreFix_aluExe_1_dispToRegQ$first[84:78] != 7'd0) ? IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16438 : 14'd0) ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_reserved__h858476 : + thin_reserved__h858474 : 2'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_otype__h858477 : + thin_otype__h858475 : 18'd262143, !coreFix_aluExe_1_dispToRegQ$first[124] || IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17235, @@ -24323,7 +24323,7 @@ module mkCore(CLK, 34'h344000000 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_perms_soft__h858712 : + thin_perms_soft__h858710 : 4'd0, coreFix_aluExe_1_dispToRegQ$first[124] && IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16898, @@ -24354,18 +24354,18 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17260 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262 = { coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_address__h858472 : + thin_address__h858470 : 66'd0, coreFix_aluExe_1_dispToRegQ$first[124] ? - thin_addrBits__h858473 : + thin_addrBits__h858471 : 14'd0, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17261 } ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17301 = - thin_bounds_topBits__h860420[13:11] < repBound__h860556 ; + thin_bounds_topBits__h860418[13:11] < repBound__h860554 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17303 = - thin_bounds_baseBits__h860421[13:11] < repBound__h860556 ; + thin_bounds_baseBits__h860419[13:11] < repBound__h860554 ; assign IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17306 = - thin_addrBits__h858473[13:11] < repBound__h860556 ; + thin_addrBits__h858471[13:11] < repBound__h860554 ; assign IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17977 = { (coreFix_aluExe_1_exeToFinQ$first[282] && !coreFix_aluExe_1_exeToFinQ$first[294]) ? @@ -25149,8 +25149,8 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d20197 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h915808 : - w__h915803 ; + result__h915812 : + w__h915807 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d5011 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -25624,15 +25624,15 @@ module mkCore(CLK, NOT_coreFix_memExe_dispToRegQ_first__686_BIT_1_ETC___d3634 } ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070 = coreFix_memExe_dispToRegQ$first[12] ? - res_addrBits__h235321 : + res_addrBits__h235323 : ((coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3068 : 14'd0) ; assign IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3315 = { coreFix_memExe_dispToRegQ$first[12] ? - res_address__h235320 : - x__h235743, + res_address__h235322 : + x__h235745, IF_coreFix_memExe_dispToRegQ_first__686_BIT_12_ETC___d3070, coreFix_memExe_dispToRegQ$first[12] ? 4'd0 : @@ -25771,13 +25771,13 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__498_BIT_113_513_ETC___d2078 ; assign IF_coreFix_memExe_lsq_getOrigBE_coreFix_memExe_ETC___d4249 = { coreFix_memExe_lsq$getOrigBE[15] ? - pointer__h242635[3:0] != 4'd0 : + pointer__h242637[3:0] != 4'd0 : (coreFix_memExe_lsq$getOrigBE[7] ? - pointer__h242635[2:0] != 3'd0 : + pointer__h242637[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - pointer__h242635[1:0] != 2'd0 : + pointer__h242637[1:0] != 2'd0 : coreFix_memExe_lsq$getOrigBE[1] && - pointer__h242635[0])), + pointer__h242637[0])), capChecks___d4160[11:5], CASE_capChecks_160_BITS_4_TO_0_0_capChecks_160_ETC__q294, prepareBoundsCheck___d4244 } ; @@ -25809,10 +25809,10 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[13:0] ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] < - repBound__h855389 ; + repBound__h855387 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232[13:11] < - repBound__h855389 ; + repBound__h855387 ; assign IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 = MUX_csrf_ie_vec_3$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -25913,7 +25913,7 @@ module mkCore(CLK, csrf_mepcc_reg_data_rl[30:28] } : csrf_mepcc_reg_data_rl[25:0] ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 = - ((newAddrDiff__h1000193 == 64'd0) ? + ((newAddrDiff__h1000197 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 ? 2'd3 : @@ -25930,12 +25930,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845 = IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22842 && - (newAddrDiff__h1000193 == 64'd0 || + (newAddrDiff__h1000197 == 64'd0 || csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 || - newAddrDiff__h1000193 == + newAddrDiff__h1000197 == _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 = - ((newAddrDiff__h1000537 == 64'd0) ? + ((newAddrDiff__h1000541 == 64'd0) ? 2'd0 : (csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 ? 2'd3 : @@ -25952,12 +25952,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870 = IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22867 && - (newAddrDiff__h1000537 == 64'd0 || + (newAddrDiff__h1000541 == 64'd0 || csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 || - newAddrDiff__h1000537 == + newAddrDiff__h1000541 == _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826) ; assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22873 = - (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? + (csrf_mtcc_reg[86] && cause_interrupt__h995320) ? (NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812 || IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22845) && csrf_mtcc_reg[152] : @@ -25965,9 +25965,9 @@ module mkCore(CLK, IF_csrf_mtcc_reg_read__6198_BITS_149_TO_86_281_ETC___d22870) && csrf_mtcc_reg[152] ; assign IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 = - (csrf_mtcc_reg[86] && cause_interrupt__h995316) ? - address__h999513 : - base__h999478 ; + (csrf_mtcc_reg[86] && cause_interrupt__h995320) ? + address__h999517 : + base__h999482 ; assign IF_csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_c_ETC___d22878 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? { IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804, @@ -25997,10 +25997,10 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[13:0] ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] < - repBound__h854397 ; + repBound__h854395 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080[13:11] < - repBound__h854397 ; + repBound__h854395 ; assign IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 = MUX_csrf_ie_vec_1$write_1__SEL_3 ? MUX_csrf_rg_dpc$write_1__VAL_3[33:28] : @@ -26101,7 +26101,7 @@ module mkCore(CLK, csrf_sepcc_reg_data_rl[30:28] } : csrf_sepcc_reg_data_rl[25:0] ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 = - ((newAddrDiff__h999536 == 64'd0) ? + ((newAddrDiff__h999540 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 ? 2'd3 : @@ -26118,12 +26118,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776 = IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22773 && - (newAddrDiff__h999536 == 64'd0 || + (newAddrDiff__h999540 == 64'd0 || csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 || - newAddrDiff__h999536 == + newAddrDiff__h999540 == _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 = - ((newAddrDiff__h999880 == 64'd0) ? + ((newAddrDiff__h999884 == 64'd0) ? 2'd0 : (csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 ? 2'd3 : @@ -26140,12 +26140,12 @@ module mkCore(CLK, 2'd0))) ; assign IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801 = IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22798 && - (newAddrDiff__h999880 == 64'd0 || + (newAddrDiff__h999884 == 64'd0 || csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 || - newAddrDiff__h999880 == + newAddrDiff__h999884 == _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757) ; assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22804 = - (csrf_stcc_reg[86] && cause_interrupt__h995316) ? + (csrf_stcc_reg[86] && cause_interrupt__h995320) ? (NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741 || IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22776) && csrf_stcc_reg[152] : @@ -26153,29 +26153,29 @@ module mkCore(CLK, IF_csrf_stcc_reg_read__6046_BITS_149_TO_86_274_ETC___d22801) && csrf_stcc_reg[152] ; assign IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 = - (csrf_stcc_reg[86] && cause_interrupt__h995316) ? - address__h999463 : - base__h999424 ; + (csrf_stcc_reg[86] && cause_interrupt__h995320) ? + address__h999467 : + base__h999428 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 = f_csr_reqs$D_OUT[63] ? - x__h1031581[13:0] >= toBounds__h1008417 : - x__h1031581[13:0] <= toBoundsM1__h1008418 ; + x__h1031585[13:0] >= toBounds__h1008421 : + x__h1031585[13:0] <= toBoundsM1__h1008422 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 = f_csr_reqs$D_OUT[63] ? - x__h1031984[13:0] >= toBounds__h1008820 : - x__h1031984[13:0] <= toBoundsM1__h1008821 ; + x__h1031988[13:0] >= toBounds__h1008824 : + x__h1031988[13:0] <= toBoundsM1__h1008825 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 = f_csr_reqs$D_OUT[63] ? - x__h1032401[13:0] >= toBounds__h1009237 : - x__h1032401[13:0] <= toBoundsM1__h1009238 ; + x__h1032405[13:0] >= toBounds__h1009241 : + x__h1032405[13:0] <= toBoundsM1__h1009242 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 = f_csr_reqs$D_OUT[63] ? - x__h1032804[13:0] >= toBounds__h1009640 : - x__h1032804[13:0] <= toBoundsM1__h1009641 ; + x__h1032808[13:0] >= toBounds__h1009644 : + x__h1032808[13:0] <= toBoundsM1__h1009645 ; assign IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 = f_csr_reqs$D_OUT[63] ? - x__h1033471[13:0] >= toBounds__h1010309 : - x__h1033471[13:0] <= toBoundsM1__h1010310 ; + x__h1033475[13:0] >= toBounds__h1010313 : + x__h1033475[13:0] <= toBoundsM1__h1010314 ; assign IF_fetchStage_RDY_pipelines_0_first__0253_AND__ETC___d21186 = (fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[268:266] != 3'd1 || @@ -26601,36 +26601,36 @@ module mkCore(CLK, 2'd3) } ; assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h1015845 : + y_avValue_snd_snd_snd_snd_snd__h1015849 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 = - rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015829 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_snd_fst__h1015833 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h1015839 : + y_avValue_snd_snd_snd_fst__h1015843 : 2'd0 ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23135 = - (highOffsetBits__h1008408 == 50'd0 && + (highOffsetBits__h1008412 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23132 || NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23181 = - (highOffsetBits__h1008811 == 50'd0 && + (highOffsetBits__h1008815 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23176 || NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23274 = - (highOffsetBits__h1009228 == 50'd0 && + (highOffsetBits__h1009232 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23271 || NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23318 = - (highOffsetBits__h1009631 == 50'd0 && + (highOffsetBits__h1009635 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23313 || NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; assign IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_19_ETC___d23432 = - (highOffsetBits__h1010300 == 50'd0 && + (highOffsetBits__h1010304 == 50'd0 && IF_IF_rob_deqPort_0_deq_data__2261_BITS_196_TO_ETC___d23426 || NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; @@ -26766,7 +26766,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19071) ; assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19093 = sbCons$lazyLookup_0_get[3] ? - repBound__h898284 : + repBound__h898287 : (NOT_coreFix_aluExe_0_bypassWire_0_whas__8403_8_ETC___d18430 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__840_ETC___d19089) ; @@ -26797,7 +26797,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_0_get_coreFix_aluExe_0_di_ETC___d19196 = sbCons$lazyLookup_0_get[2] ? { rf$read_0_rd2, - repBound__h900611, + repBound__h900614, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169, rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 } : @@ -26932,7 +26932,7 @@ module mkCore(CLK, IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16676) ; assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16698 = sbCons$lazyLookup_1_get[3] ? - repBound__h857576 : + repBound__h857574 : (NOT_coreFix_aluExe_1_bypassWire_0_whas__5640_5_ETC___d15667 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__564_ETC___d16694) ; @@ -26963,7 +26963,7 @@ module mkCore(CLK, assign IF_sbCons_lazyLookup_1_get_coreFix_aluExe_1_di_ETC___d16801 = sbCons$lazyLookup_1_get[2] ? { rf$read_1_rd2, - repBound__h860538, + repBound__h860536, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774, rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 } : @@ -27098,7 +27098,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3305) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3327 = sbCons$lazyLookup_3_get[3] ? - repBound__h237315 : + repBound__h237317 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2731 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3323) ; @@ -27254,7 +27254,7 @@ module mkCore(CLK, IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3572) ; assign IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3589 = sbCons$lazyLookup_3_get[2] ? - repBound__h239000 : + repBound__h239002 : (NOT_coreFix_memExe_bypassWire_0_whas__704_710__ETC___d2758 ? coreFix_aluExe_0_bypassWire_3$wget[9:7] : IF_NOT_coreFix_memExe_bypassWire_0_whas__704_7_ETC___d3585) ; @@ -27329,17 +27329,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19771 = { ~coreFix_aluExe_0_regToExeQ$first[286:268], INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906570 : + x__h906573 : 6'd0, - x__h906743, - x__h906763 } ; + x__h906746, + x__h906766 } ; assign INV_coreFix_aluExe_0_regToExeQ_first__9457_BIT_ETC___d19835 = { ~coreFix_aluExe_0_regToExeQ$first[157:139], INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907118 : + x__h907121 : 6'd0, - x__h907291, - x__h907311 } ; + x__h907294, + x__h907314 } ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14 = ~coreFix_aluExe_0_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13 = @@ -27347,17 +27347,17 @@ module mkCore(CLK, assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17655 = { ~coreFix_aluExe_1_regToExeQ$first[286:268], INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866885 : + x__h866883 : 6'd0, - x__h867058, - x__h867078 } ; + x__h867056, + x__h867076 } ; assign INV_coreFix_aluExe_1_regToExeQ_first__7341_BIT_ETC___d17719 = { ~coreFix_aluExe_1_regToExeQ$first[157:139], INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867433 : + x__h867431 : 6'd0, - x__h867606, - x__h867626 } ; + x__h867604, + x__h867624 } ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12 = ~coreFix_aluExe_1_regToExeQ$first[157:139] ; assign INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11 = @@ -27368,8 +27368,8 @@ module mkCore(CLK, ~coreFix_memExe_respLrScAmoQ_data_0[108:90] ; assign INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9 = ~mmio_dataRespQ_data_0[108:90] ; - assign INV_x83397_BITS_108_TO_90__q34 = ~x__h183397[108:90] ; - assign INV_x99249_BITS_108_TO_90__q36 = ~x__h199249[108:90] ; + assign INV_x83398_BITS_108_TO_90__q34 = ~x__h183398[108:90] ; + assign INV_x99250_BITS_108_TO_90__q36 = ~x__h199250[108:90] ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d10746 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -27458,10 +27458,10 @@ module mkCore(CLK, !checkForException___d21604[13] && NOT_csrf_fs_reg_read__6010_EQ_0_0640_0641_OR_N_ETC___d21629 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__3600_3601_OR__ETC___d23846 = - (fflags__h1016351 & csrf_fflags_reg) != fflags__h1016351 || - !r__h853138 && + (fflags__h1016355 & csrf_fflags_reg) != fflags__h1016355 || + !r__h853136 && (IF_rob_deqPort_1_canDeq__3604_THEN_IF_NOT_rob__ETC___d23841 || - fflags__h1016351 != 5'd0) ; + fflags__h1016355 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d12707 = !f1_sfd__h714897[21] && !f1_sfd__h714897[20] && !f1_sfd__h714897[19] && @@ -28743,7 +28743,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q316, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q317, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d7137, - x__h508764 } ; + x__h508765 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d24476 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q318, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q319, @@ -28817,21 +28817,21 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q189[10:0] - 11'd1023 ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4881 = - { {64{x__h264730[63]}}, x__h264730 } ; + { {64{x__h264732[63]}}, x__h264732 } ; assign SEXT_SEL_ARR_SEL_ARR_coreFix_memExe_dMem_cache_ETC___d4889 = - { {96{x__h264885[31]}}, x__h264885 } ; + { {96{x__h264887[31]}}, x__h264887 } ; assign SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678 = - x__h997622 | in__h997691[63:0] ; + x__h997626 | in__h997695[63:0] ; assign SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 = - x__h855225 | in__h855450[63:0] ; + x__h855223 | in__h855448[63:0] ; assign SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 = - x__h854232 | in__h854458[63:0] ; + x__h854230 | in__h854456[63:0] ; assign SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 = - x__h896270 | in__h855146[63:0] ; + x__h896273 | in__h855144[63:0] ; assign SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 = - x__h896615 | in__h855976[63:0] ; + x__h896618 | in__h855974[63:0] ; assign SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 = - x__h895986 | in__h854153[63:0] ; + x__h895989 | in__h854151[63:0] ; assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d10071 = { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83[10], coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q83 } ; @@ -29179,17 +29179,17 @@ module mkCore(CLK, csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1, 1'd0 } ; assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22834 = - x__h1000380[13:11] < repBound__h855068 ; + x__h1000384[13:11] < repBound__h855066 ; assign _0_CONCAT_csrf_mtcc_reg_read__6198_BITS_149_TO__ETC___d22859 = - x__h1000684[13:11] < repBound__h855068 ; + x__h1000688[13:11] < repBound__h855066 ; assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22765 = - x__h999723[13:11] < repBound__h854075 ; + x__h999727[13:11] < repBound__h854073 ; assign _0_CONCAT_csrf_stcc_reg_read__6046_BITS_149_TO__ETC___d22790 = - x__h1000027[13:11] < repBound__h854075 ; + x__h1000031[13:11] < repBound__h854073 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__0256_BI_ETC___d21841 = (fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__0265_BI_ETC___d21739 = (fetchStage$pipelines_1_first[268:266] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -29227,13 +29227,13 @@ module mkCore(CLK, 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d8677) ; assign _0b0_CONCAT_csrf_medeleg_28_26_reg_read__6161_6_ETC___d22642 = - medeleg_csr__read__h850222[i__h995334] ; + medeleg_csr__read__h850220[i__h995338] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__6172_6173_ETC___d22645 = - mideleg_csr__read__h850320[i__h995534] ; + mideleg_csr__read__h850318[i__h995538] ; assign _18446744073709551615_SL_csrf_mtcc_reg_read__61_ETC___d22826 = - mask__h1000192 ^ y__h1000309 ; + mask__h1000196 ^ y__h1000313 ; assign _18446744073709551615_SL_csrf_stcc_reg_read__60_ETC___d22757 = - mask__h999535 ^ y__h999652 ; + mask__h999539 ^ y__h999656 ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d10709 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9532 && (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9533 ? @@ -29840,7 +29840,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[238:237] != 2'd1 && fetchStage_pipelines_1_first__0265_BITS_268_TO_ETC___d22174 ; assign _dfoo16 = - k__h945028 == 1'd1 && fetchStage$pipelines_0_canDeq && + k__h945032 == 1'd1 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29848,7 +29848,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22118 && NOT_fetchStage_pipelines_1_first__0265_BITS_26_ETC___d22130 ; assign _dfoo18 = - k__h945028 == 1'd0 && fetchStage$pipelines_0_canDeq && + k__h945032 == 1'd0 && fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d22015 || (fetchStage_pipelines_0_canDeq__0254_AND_NOT_fe_ETC___d22100 || NOT_fetchStage_pipelines_0_canDeq__0254_0255_O_ETC___d22113) == @@ -29983,29 +29983,29 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h515366 = + assign _theResult_____2__h515367 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7240 ? - next_deqP___1__h515611 : + next_deqP___1__h515612 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h526143 = + assign _theResult_____2__h526144 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7334 ? - next_deqP___1__h526388 : + next_deqP___1__h526389 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h533236 = + assign _theResult_____2__h533237 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7493 ? - next_deqP___1__h533666 : + next_deqP___1__h533667 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h543871 = + assign _theResult_____2__h543872 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7577 ? - next_deqP___1__h544301 : + next_deqP___1__h544302 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h557704 = + assign _theResult_____2__h557705 = IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d7782 ? - next_deqP___1__h557949 : + next_deqP___1__h557950 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h561483 = + assign _theResult_____2__h561484 = IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d7864 ? - next_deqP___1__h561728 : + next_deqP___1__h561729 : coreFix_memExe_forwardQ_deqP ; assign _theResult____h576452 = (value__h577074 == 54'd0) ? sfd__h568847 : 57'd1 ; @@ -30049,9 +30049,9 @@ module mkCore(CLK, 12'd2105) ? result__h814395 : ((value__h797998 == 25'd0) ? sfd__h793556 : 57'd1) ; - assign _theResult____h920230 = + assign _theResult____h920234 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h920755 : + enabled_ints___1__h920759 : 16'd0 ; assign _theResult___exp__h585079 = sfd__h584655[24] ? @@ -32755,38 +32755,38 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? a___1__h835845 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign addBase__h1008620 = - { {48{base__h895973[15]}}, base__h895973 } << + assign addBase__h1008624 = + { {48{base__h895976[15]}}, base__h895976 } << csrf_stcc_reg[33:28] ; - assign addBase__h1009023 = - { {48{base__h854219[15]}}, base__h854219 } << + assign addBase__h1009027 = + { {48{base__h854217[15]}}, base__h854217 } << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign addBase__h1009440 = - { {48{base__h896257[15]}}, base__h896257 } << + assign addBase__h1009444 = + { {48{base__h896260[15]}}, base__h896260 } << csrf_mtcc_reg[33:28] ; - assign addBase__h1009843 = - { {48{base__h855212[15]}}, base__h855212 } << + assign addBase__h1009847 = + { {48{base__h855210[15]}}, base__h855210 } << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign addBase__h1010513 = - { {48{base__h896602[15]}}, base__h896602 } << + assign addBase__h1010517 = + { {48{base__h896605[15]}}, base__h896605 } << csrf_rg_dpc[33:28] ; - assign addBase__h239861 = - { {48{base__h239696[15]}}, base__h239696 } << + assign addBase__h239863 = + { {48{base__h239698[15]}}, base__h239698 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addBase__h241018 = - { {48{base__h240853[15]}}, base__h240853 } << + assign addBase__h241020 = + { {48{base__h240855[15]}}, base__h240855 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addBase__h254642 = - { {48{base__h254477[15]}}, base__h254477 } << + assign addBase__h254644 = + { {48{base__h254479[15]}}, base__h254479 } << coreFix_memExe_dTlb$procResp[334:329] ; - assign addTop__h239970 = - { {50{x__h240069[15]}}, x__h240069 } << + assign addTop__h239972 = + { {50{x__h240071[15]}}, x__h240071 } << coreFix_memExe_regToExeQ$first[265:260] ; - assign addTop__h241127 = - { {50{x__h241226[15]}}, x__h241226 } << + assign addTop__h241129 = + { {50{x__h241228[15]}}, x__h241228 } << coreFix_memExe_regToExeQ$first[102:97] ; - assign addTop__h254751 = - { {50{x__h254850[15]}}, x__h254850 } << + assign addTop__h254753 = + { {50{x__h254852[15]}}, x__h254852 } << coreFix_memExe_dTlb$procResp[334:329] ; assign addr__h148438 = coreFix_memExe_reqLdQ_data_0_lat_0$whas ? @@ -32796,20 +32796,20 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0] ; - assign addr__h235314 = x__h235743[63:0] + csrf_ddc_reg[149:86] ; - assign addr__h989734 = + assign addr__h235316 = x__h235745[63:0] + csrf_ddc_reg[149:86] ; + assign addr__h989738 = (rob$deqPort_0_deq_data[273:272] == 2'd1 && (rob$deqPort_0_deq_data[265:261] == 5'd1 || rob$deqPort_0_deq_data[265:261] == 5'd12)) ? rob$deqPort_0_deq_data[260:197] : rob$deqPort_0_deq_data[191:128] ; - assign address__h1000186 = { 2'd0, address__h999513 } ; - assign address__h1000530 = { 2'd0, base__h999478 } ; - assign address__h1013717 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; - assign address__h999463 = base__h999424 + { 57'd0, x__h999622 } ; - assign address__h999513 = base__h999478 + { 57'd0, x__h999622 } ; - assign address__h999529 = { 2'd0, address__h999463 } ; - assign address__h999873 = { 2'd0, base__h999424 } ; + assign address__h1000190 = { 2'd0, address__h999517 } ; + assign address__h1000534 = { 2'd0, base__h999482 } ; + assign address__h1013721 = rob$deqPort_0_deq_data[565:502] + 64'd4 ; + assign address__h999467 = base__h999428 + { 57'd0, x__h999626 } ; + assign address__h999517 = base__h999482 + { 57'd0, x__h999626 } ; + assign address__h999533 = { 2'd0, address__h999467 } ; + assign address__h999877 = { 2'd0, base__h999428 } ; assign b___1__h835846 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q23[31]}}, @@ -32828,31 +32828,31 @@ module mkCore(CLK, { mmio_dataRespQ_data_0[77:67], ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign b_base__h183704 = - { x__h183397[77:67], ~x__h183397[66], x__h183397[65:64] } ; - assign b_base__h202455 = - { x__h199249[77:67], ~x__h199249[66], x__h199249[65:64] } ; - assign b_base__h217021 = + assign b_base__h183705 = + { x__h183398[77:67], ~x__h183398[66], x__h183398[65:64] } ; + assign b_base__h202456 = + { x__h199250[77:67], ~x__h199250[66], x__h199250[65:64] } ; + assign b_base__h217022 = { coreFix_memExe_lsq$respLd[77:67], ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign b_base__h867085 = + assign b_base__h867083 = { coreFix_aluExe_1_regToExeQ$first[255:245], ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign b_base__h867633 = + assign b_base__h867631 = { coreFix_aluExe_1_regToExeQ$first[126:116], ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign b_base__h906770 = + assign b_base__h906773 = { coreFix_aluExe_0_regToExeQ$first[255:245], ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign b_base__h907318 = + assign b_base__h907321 = { coreFix_aluExe_0_regToExeQ$first[126:116], ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign b_base__h995134 = + assign b_base__h995138 = { commitStage_commitTrap[186:176], ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; @@ -32864,44 +32864,44 @@ module mkCore(CLK, { mmio_dataRespQ_data_0[89:81], ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign b_top__h183703 = - { x__h183397[89:81], ~x__h183397[80:79], x__h183397[78] } ; - assign b_top__h202454 = - { x__h199249[89:81], ~x__h199249[80:79], x__h199249[78] } ; - assign b_top__h217020 = + assign b_top__h183704 = + { x__h183398[89:81], ~x__h183398[80:79], x__h183398[78] } ; + assign b_top__h202455 = + { x__h199250[89:81], ~x__h199250[80:79], x__h199250[78] } ; + assign b_top__h217021 = { coreFix_memExe_lsq$respLd[89:81], ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign b_top__h867084 = + assign b_top__h867082 = { coreFix_aluExe_1_regToExeQ$first[267:259], ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign b_top__h867632 = + assign b_top__h867630 = { coreFix_aluExe_1_regToExeQ$first[138:130], ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign b_top__h906769 = + assign b_top__h906772 = { coreFix_aluExe_0_regToExeQ$first[267:259], ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign b_top__h907317 = + assign b_top__h907320 = { coreFix_aluExe_0_regToExeQ$first[138:130], ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign b_top__h995133 = + assign b_top__h995137 = { commitStage_commitTrap[198:190], ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign base__h239696 = + assign base__h239698 = { coreFix_memExe_regToExeQ$first[223:222], coreFix_memExe_regToExeQ$first[245:232] } ; - assign base__h240853 = + assign base__h240855 = { coreFix_memExe_regToExeQ$first[60:59], coreFix_memExe_regToExeQ$first[82:69] } ; - assign base__h254477 = + assign base__h254479 = { coreFix_memExe_dTlb$procResp[292:291], coreFix_memExe_dTlb$procResp[314:301] } ; - assign base__h854219 = + assign base__h854217 = { (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16087 == IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16089) ? 2'd0 : @@ -32910,7 +32910,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } ; - assign base__h855212 = + assign base__h855210 = { (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16239 == IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16241) ? 2'd0 : @@ -32919,7 +32919,7 @@ module mkCore(CLK, 2'd1 : 2'd3), IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } ; - assign base__h895973 = + assign base__h895976 = { (csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 == csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053) ? 2'd0 : @@ -32928,7 +32928,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_stcc_reg[13:0] } ; - assign base__h896257 = + assign base__h896260 = { (csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 == csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205) ? 2'd0 : @@ -32937,7 +32937,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_mtcc_reg[13:0] } ; - assign base__h896602 = + assign base__h896605 = { (csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 == csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350) ? 2'd0 : @@ -32946,7 +32946,7 @@ module mkCore(CLK, 2'd1 : 2'd3), csrf_rg_dpc[13:0] } ; - assign base__h997609 = + assign base__h997613 = { (IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22662 == IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd0 : @@ -32954,50 +32954,50 @@ module mkCore(CLK, !IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22664) ? 2'd1 : 2'd3), - x__h995127 } ; - assign base__h999424 = { csrf_stcc_reg[149:88], 2'b0 } ; - assign base__h999478 = { csrf_mtcc_reg[149:88], 2'b0 } ; - assign bot__h1008623 = - { csrf_stcc_reg[149:100] & highBitsfilter__h1008407, 14'd0 } + - addBase__h1008620 ; - assign bot__h1009026 = + x__h995131 } ; + assign base__h999428 = { csrf_stcc_reg[149:88], 2'b0 } ; + assign base__h999482 = { csrf_mtcc_reg[149:88], 2'b0 } ; + assign bot__h1008627 = + { csrf_stcc_reg[149:100] & highBitsfilter__h1008411, 14'd0 } + + addBase__h1008624 ; + assign bot__h1009030 = { IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104[63:14] & - highBitsfilter__h1008810, + highBitsfilter__h1008814, 14'd0 } + - addBase__h1009023 ; - assign bot__h1009443 = - { csrf_mtcc_reg[149:100] & highBitsfilter__h1009227, 14'd0 } + - addBase__h1009440 ; - assign bot__h1009846 = + addBase__h1009027 ; + assign bot__h1009447 = + { csrf_mtcc_reg[149:100] & highBitsfilter__h1009231, 14'd0 } + + addBase__h1009444 ; + assign bot__h1009850 = { IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256[63:14] & - highBitsfilter__h1009630, + highBitsfilter__h1009634, 14'd0 } + - addBase__h1009843 ; - assign bot__h1010516 = - { csrf_rg_dpc[149:100] & highBitsfilter__h1010299, 14'd0 } + - addBase__h1010513 ; + addBase__h1009847 ; + assign bot__h1010520 = + { csrf_rg_dpc[149:100] & highBitsfilter__h1010303, 14'd0 } + + addBase__h1010517 ; assign carry_out__h127431 = (topBits__h127429 < x__h127520[11:0]) ? 2'b01 : 2'b0 ; assign carry_out__h140347 = (topBits__h140345 < x__h140436[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h183608 = - (topBits__h183606 < x__h183697[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h202359 = - (topBits__h202357 < x__h202448[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h216925 = - (topBits__h216923 < x__h217014[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h866988 = - (topBits__h866986 < x__h867078[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h867536 = - (topBits__h867534 < x__h867626[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h906673 = - (topBits__h906671 < x__h906763[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h907221 = - (topBits__h907219 < x__h907311[11:0]) ? 2'b01 : 2'b0 ; - assign carry_out__h995038 = - (topBits__h995036 < x__h995127[11:0]) ? 2'b01 : 2'b0 ; - assign cause_code__h996893 = { 1'd0, i__h995534 } ; - assign cause_interrupt__h995316 = + assign carry_out__h183609 = + (topBits__h183607 < x__h183698[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h202360 = + (topBits__h202358 < x__h202449[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h216926 = + (topBits__h216924 < x__h217015[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h866986 = + (topBits__h866984 < x__h867076[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h867534 = + (topBits__h867532 < x__h867624[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h906676 = + (topBits__h906674 < x__h906766[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h907224 = + (topBits__h907222 < x__h907314[11:0]) ? 2'b01 : 2'b0 ; + assign carry_out__h995042 = + (topBits__h995040 < x__h995131[11:0]) ? 2'b01 : 2'b0 ; + assign cause_code__h996897 = { 1'd0, i__h995538 } ; + assign cause_interrupt__h995320 = commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[44:43] != 2'd0 ; assign commitStage_commitTrap_2268_BITS_44_TO_43_2461_ETC___d22501 = @@ -33062,7 +33062,7 @@ module mkCore(CLK, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19204, IF_coreFix_aluExe_0_dispToRegQ_first__8383_BIT_ETC___d19396, coreFix_aluExe_0_dispToRegQ$first[124] ? - repBound__h900629 : + repBound__h900632 : 3'd7, NOT_coreFix_aluExe_0_dispToRegQ_first__8383_BI_ETC___d19436 } ; assign coreFix_aluExe_0_dispToRegQ_first__8383_BIT_13_ETC___d18468 = @@ -33113,7 +33113,7 @@ module mkCore(CLK, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d16826, IF_coreFix_aluExe_1_dispToRegQ_first__5620_BIT_ETC___d17262, coreFix_aluExe_1_dispToRegQ$first[124] ? - repBound__h860556 : + repBound__h860554 : 3'd7, NOT_coreFix_aluExe_1_dispToRegQ_first__5620_BI_ETC___d17320 } ; assign coreFix_aluExe_1_dispToRegQ_first__5620_BIT_13_ETC___d15705 = @@ -33299,7 +33299,7 @@ module mkCore(CLK, !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5023 && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h422564 ; + y__h422565 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d5632 = coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd3 && @@ -35479,12 +35479,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 = coreFix_memExe_dTlb$procResp[334:329] < 6'd51 && coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:63] - - { 1'd0, x__h254919 } > + { 1'd0, x__h254921 } > 2'd1 ; assign coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407 = - { coreFix_memExe_dTlb$procResp[452:401] & mask__h254752, + { coreFix_memExe_dTlb$procResp[452:401] & mask__h254754, 14'd0 } + - addTop__h254751 ; + addTop__h254753 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4557 = coreFix_memExe_dTlb$procResp[560:500] < 61'd402653184 ; assign coreFix_memExe_dTlb_procResp__257_BITS_560_TO__ETC___d4558 = @@ -35504,12 +35504,12 @@ module mkCore(CLK, assign coreFix_memExe_dTlb_procResp__257_BITS_77_TO_1_ETC___d4550 = coreFix_memExe_dTlb$procResp[77:13] < coreFix_memExe_dTlb$procResp[212:148] ; - assign coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6 = + assign coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4 = coreFix_memExe_dTlb$procResp[292:291] ; - assign coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7 = + assign coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5 = coreFix_memExe_dTlb$procResp[450:401] + - ({ {48{coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6[1]}}, - coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q6 } << + ({ {48{coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4[1]}}, + coreFix_memExe_dTlbprocResp_BITS_292_TO_291__q4 } << coreFix_memExe_dTlb$procResp[334:329]) ; assign coreFix_memExe_dispToRegQ_first__686_BIT_102_6_ETC___d3579 = { coreFix_memExe_dispToRegQ$first[102] && @@ -35530,15 +35530,15 @@ module mkCore(CLK, 66'd0, IF_coreFix_memExe_dispToRegQ_first__686_BIT_10_ETC___d3580 } ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d4250 = - { coreFix_memExe_lsq$getOrigBE << pointer__h242635[3:0], - (highOffsetBits__h242644 == 50'd0 && + { coreFix_memExe_lsq$getOrigBE << pointer__h242637[3:0], + (highOffsetBits__h242646 == 50'd0 && IF_SEXT_coreFix_memExe_regToExeQ_first__645_BI_ETC___d4095 || coreFix_memExe_regToExeQ$first[265:260] >= 6'd50) && coreFix_memExe_regToExeQ$first[384], - result_d_address__h242846, - x__h248117[13:0], + result_d_address__h242848, + x__h248119[13:0], coreFix_memExe_regToExeQ$first[303:232], - repBound__h248215, + repBound__h248217, coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110, coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123, @@ -35546,7 +35546,7 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 = coreFix_memExe_regToExeQ$first[102:97] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:63] - - { 1'd0, x__h241295 } > + { 1'd0, x__h241297 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_140_T_ETC___d4070 = { coreFix_memExe_regToExeQ$first[140:125], @@ -35559,26 +35559,26 @@ module mkCore(CLK, ~IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[2], IF_coreFix_memExe_regToExeQ_first__645_BIT_103_ETC___d4017[1:0], coreFix_memExe_regToExeQ$first[218:155] } << - x__h244675 ; + x__h244677 ; assign coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766 = - { coreFix_memExe_regToExeQ$first[220:169] & mask__h241128, + { coreFix_memExe_regToExeQ$first[220:169] & mask__h241130, 14'd0 } + - addTop__h241127 ; + addTop__h241129 ; assign coreFix_memExe_regToExeQ_first__645_BITS_245_T_ETC___d4111 = - coreFix_memExe_regToExeQ$first[245:243] < repBound__h248215 ; + coreFix_memExe_regToExeQ$first[245:243] < repBound__h248217 ; assign coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 = - coreFix_memExe_regToExeQ$first[259:257] < repBound__h248215 ; + coreFix_memExe_regToExeQ$first[259:257] < repBound__h248217 ; assign coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 = coreFix_memExe_regToExeQ$first[265:260] < 6'd51 && coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:63] - - { 1'd0, x__h240138 } > + { 1'd0, x__h240140 } > 2'd1 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704 = - { coreFix_memExe_regToExeQ$first[383:332] & mask__h239971, + { coreFix_memExe_regToExeQ$first[383:332] & mask__h239973, 14'd0 } + - addTop__h239970 ; + addTop__h239972 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113 = - x__h248117[13:11] < repBound__h248215 ; + x__h248119[13:11] < repBound__h248217 ; assign coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4123 = { coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113, (coreFix_memExe_regToExeQ_first__645_BITS_259_T_ETC___d4110 == @@ -35595,10 +35595,10 @@ module mkCore(CLK, !coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d4113) ? 2'd1 : 2'd3) } ; - assign coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5 = + assign coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q7 = coreFix_memExe_regToExeQ$first[218:169] + - ({ {48{coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4[1]}}, - coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4 } << + ({ {48{coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6[1]}}, + coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6 } << coreFix_memExe_regToExeQ$first[102:97]) ; assign coreFix_memExe_regToExeQfirst_BITS_223_TO_222__q2 = coreFix_memExe_regToExeQ$first[223:222] ; @@ -35609,7 +35609,7 @@ module mkCore(CLK, coreFix_memExe_regToExeQ$first[265:260]) ; assign coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 = coreFix_memExe_regToExeQ$first[434:403] ; - assign coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q4 = + assign coreFix_memExe_regToExeQfirst_BITS_60_TO_59__q6 = coreFix_memExe_regToExeQ$first[60:59] ; assign coreFix_memExe_stb_isEmpty__186_AND_coreFix_me_ETC___d23029 = coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty && @@ -35619,44 +35619,44 @@ module mkCore(CLK, fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__2261_BITS_469_TO_4_ETC___d23024 ; - assign cr_addrBits__h866671 = + assign cr_addrBits__h866669 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? - x__h866847[13:0] : + x__h866845[13:0] : coreFix_aluExe_1_regToExeQ$first[191:178] ; - assign cr_addrBits__h867219 = + assign cr_addrBits__h867217 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? - x__h867395[13:0] : + x__h867393[13:0] : coreFix_aluExe_1_regToExeQ$first[62:49] ; - assign cr_addrBits__h906356 = + assign cr_addrBits__h906359 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? - x__h906532[13:0] : + x__h906535[13:0] : coreFix_aluExe_0_regToExeQ$first[191:178] ; - assign cr_addrBits__h906904 = + assign cr_addrBits__h906907 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? - x__h907080[13:0] : + x__h907083[13:0] : coreFix_aluExe_0_regToExeQ$first[62:49] ; - assign cr_address__h866670 = + assign cr_address__h866668 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[241:178] } ; - assign cr_address__h867218 = + assign cr_address__h867216 = { 2'd0, coreFix_aluExe_1_regToExeQ$first[112:49] } ; - assign cr_address__h906355 = + assign cr_address__h906358 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[241:178] } ; - assign cr_address__h906903 = + assign cr_address__h906906 = { 2'd0, coreFix_aluExe_0_regToExeQ$first[112:49] } ; - assign cr_flags__h866673 = coreFix_aluExe_1_regToExeQ$first[287] ; - assign cr_flags__h867221 = coreFix_aluExe_1_regToExeQ$first[158] ; - assign cr_flags__h906358 = coreFix_aluExe_0_regToExeQ$first[287] ; - assign cr_flags__h906906 = coreFix_aluExe_0_regToExeQ$first[158] ; - assign cr_reserved__h866674 = coreFix_aluExe_1_regToExeQ$first[289:288] ; - assign cr_reserved__h867222 = coreFix_aluExe_1_regToExeQ$first[160:159] ; - assign cr_reserved__h906359 = coreFix_aluExe_0_regToExeQ$first[289:288] ; - assign cr_reserved__h906907 = coreFix_aluExe_0_regToExeQ$first[160:159] ; + assign cr_flags__h866671 = coreFix_aluExe_1_regToExeQ$first[287] ; + assign cr_flags__h867219 = coreFix_aluExe_1_regToExeQ$first[158] ; + assign cr_flags__h906361 = coreFix_aluExe_0_regToExeQ$first[287] ; + assign cr_flags__h906909 = coreFix_aluExe_0_regToExeQ$first[158] ; + assign cr_reserved__h866672 = coreFix_aluExe_1_regToExeQ$first[289:288] ; + assign cr_reserved__h867220 = coreFix_aluExe_1_regToExeQ$first[160:159] ; + assign cr_reserved__h906362 = coreFix_aluExe_0_regToExeQ$first[289:288] ; + assign cr_reserved__h906910 = coreFix_aluExe_0_regToExeQ$first[160:159] ; assign csrf_ddc_reg_read__051_BITS_13_TO_11_140_ULT_c_ETC___d4144 = - csrf_ddc_reg[13:11] < repBound__h248740 ; + csrf_ddc_reg[13:11] < repBound__h248742 ; assign csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 = - csrf_ddc_reg[27:25] < repBound__h248740 ; + csrf_ddc_reg[27:25] < repBound__h248742 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146 = - csrf_ddc_reg[85:83] < repBound__h248740 ; + csrf_ddc_reg[85:83] < repBound__h248742 ; assign csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4156 = { csrf_ddc_reg_read__051_BITS_85_TO_83_145_ULT_c_ETC___d4146, (csrf_ddc_reg_read__051_BITS_27_TO_25_142_ULT_c_ETC___d4143 == @@ -35713,33 +35713,33 @@ module mkCore(CLK, csrf_tw_reg && csrf_prv_reg != 2'd3 ; assign csrf_mtcc_reg_read__6198_BITS_13_TO_11_6201_UL_ETC___d16203 = - csrf_mtcc_reg[13:11] < repBound__h855068 ; + csrf_mtcc_reg[13:11] < repBound__h855066 ; assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 = - csrf_mtcc_reg[149:86] & mask__h1000192 ; + csrf_mtcc_reg[149:86] & mask__h1000196 ; assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22823 = - newAddrDiff__h1000193 == mask__h1000192 ; + newAddrDiff__h1000197 == mask__h1000196 ; assign csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22851 = - newAddrDiff__h1000537 == mask__h1000192 ; + newAddrDiff__h1000541 == mask__h1000196 ; assign csrf_mtcc_reg_read__6198_BITS_85_TO_83_6204_UL_ETC___d16205 = - csrf_mtcc_reg[85:83] < repBound__h855068 ; + csrf_mtcc_reg[85:83] < repBound__h855066 ; assign csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 = csrf_prv_reg_read__0286_ULE_1___d22614 && CASE_commitStage_commitTrap_BITS_44_TO_43_0_cs_ETC__q276 ; assign csrf_prv_reg_read__0286_ULE_1___d22614 = csrf_prv_reg <= 2'd1 ; assign csrf_rg_dpc_read__6343_BITS_13_TO_11_6346_ULT__ETC___d16348 = - csrf_rg_dpc[13:11] < repBound__h855898 ; + csrf_rg_dpc[13:11] < repBound__h855896 ; assign csrf_rg_dpc_read__6343_BITS_85_TO_83_6349_ULT__ETC___d16350 = - csrf_rg_dpc[85:83] < repBound__h855898 ; + csrf_rg_dpc[85:83] < repBound__h855896 ; assign csrf_stcc_reg_read__6046_BITS_13_TO_11_6049_UL_ETC___d16051 = - csrf_stcc_reg[13:11] < repBound__h854075 ; + csrf_stcc_reg[13:11] < repBound__h854073 ; assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 = - csrf_stcc_reg[149:86] & mask__h999535 ; + csrf_stcc_reg[149:86] & mask__h999539 ; assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22754 = - newAddrDiff__h999536 == mask__h999535 ; + newAddrDiff__h999540 == mask__h999539 ; assign csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22782 = - newAddrDiff__h999880 == mask__h999535 ; + newAddrDiff__h999884 == mask__h999539 ; assign csrf_stcc_reg_read__6046_BITS_85_TO_83_6052_UL_ETC___d16053 = - csrf_stcc_reg[85:83] < repBound__h854075 ; + csrf_stcc_reg[85:83] < repBound__h854073 ; assign data05831_BITS_31_TO_0__q26 = data__h705831[31:0] ; assign data___1__h705531 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q145[31]}}, @@ -35772,11 +35772,11 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? data___1__h706391 : data__h705831 ; - assign data_addrBits__h1018752 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; - assign data_addrBits__h1019606 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; - assign data_address__h1018751 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; - assign data_address__h1019605 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; - assign dcsr_cause__h994362 = + assign data_addrBits__h1018756 = { 2'd0, f_gpr_reqs$D_OUT[63:52] } ; + assign data_addrBits__h1019610 = { 2'b0, f_fpr_reqs$D_OUT[63:52] } ; + assign data_address__h1018755 = { 2'd0, f_gpr_reqs$D_OUT[63:0] } ; + assign data_address__h1019609 = { 2'd0, f_fpr_reqs$D_OUT[63:0] } ; + assign dcsr_cause__h994366 = (commitStage_commitTrap[44:43] != 2'd0 && commitStage_commitTrap[44:43] != 2'd1 && commitStage_commitTrap[35:32] == 4'd14) ? @@ -35816,10 +35816,10 @@ module mkCore(CLK, assign din_inc___2_exp__h831691 = _theResult___fst_exp__h812441 + 11'd1 ; assign din_inc___2_exp__h831726 = _theResult___fst_exp__h822018 + 11'd1 ; assign din_inc___2_exp__h831752 = _theResult___fst_exp__h830851 + 11'd1 ; - assign enabled_ints___1__h920755 = pend_ints__h920228 & y__h920767 ; - assign enabled_ints__h920801 = - pend_ints__h920228 & - { r1__read_BITS_13_TO_0___h920777, csrf_mideleg_1_0_reg } ; + assign enabled_ints___1__h920759 = pend_ints__h920232 & y__h920771 ; + assign enabled_ints__h920805 = + pend_ints__h920232 & + { r1__read_BITS_13_TO_0___h920781, csrf_mideleg_1_0_reg } ; assign f1_exp14896_MINUS_127__q148 = f1_exp__h714896 - 8'd127 ; assign f1_exp__h714896 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == @@ -35852,27 +35852,27 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24138 = - (highOffsetBits__h1031458 == 50'd0 && + (highOffsetBits__h1031462 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24135 || NOT_csrf_stcc_reg_read__6046_BITS_33_TO_28_606_ETC___d22741) && csrf_stcc_reg[152] ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24160 = - (highOffsetBits__h1031861 == 50'd0 && + (highOffsetBits__h1031865 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24157 || NOT_IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN__ETC___d23179) && IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16810 ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24218 = - (highOffsetBits__h1032278 == 50'd0 && + (highOffsetBits__h1032282 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24215 || NOT_csrf_mtcc_reg_read__6198_BITS_33_TO_28_621_ETC___d22812) && csrf_mtcc_reg[152] ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24238 = - (highOffsetBits__h1032681 == 50'd0 && + (highOffsetBits__h1032685 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24235 || NOT_IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN__ETC___d23316) && IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16818 ; assign f_csr_reqs_first__3971_BITS_63_TO_14_4124_XOR__ETC___d24309 = - (highOffsetBits__h1033348 == 50'd0 && + (highOffsetBits__h1033352 == 50'd0 && IF_f_csr_reqs_first__3971_BIT_63_4125_THEN_NOT_ETC___d24306 || NOT_csrf_rg_dpc_read__6343_BITS_33_TO_28_6360__ETC___d23429) && csrf_rg_dpc[152] ; @@ -35882,7 +35882,7 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h849218 = { 56'd0, x__h853091 } ; + assign fcsr_csr__read__h849216 = { 56'd0, x__h853089 } ; assign fetchStage_RDY_pipelines_0_first__0253_AND_fet_ETC___d21254 = fetchStage$RDY_pipelines_0_first && fetchStage$pipelines_1_first[268:266] == 3'd1 && @@ -36156,12 +36156,12 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__0265_BIT_180_145_ETC___d21553 = { fetchStage$pipelines_1_first[180], CASE_fetchStagepipelines_1_first_BITS_179_TO__ETC__q259 } ; - assign fflags__h1016351 = + assign fflags__h1016355 = NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? - y_avValue_snd_fst__h1016411 : + y_avValue_snd_fst__h1016415 : IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 ; - assign fflags_csr__read__h849193 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h849204 = { 61'd0, csrf_frm_reg } ; + assign fflags_csr__read__h849191 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h849202 = { 61'd0, csrf_frm_reg } ; assign guard__h576462 = { IF_sfdin84557_BIT_33_THEN_2_ELSE_0__q41[1], { sfdin__h584557[32:0], 23'd0 } != 56'd0 } ; @@ -36231,29 +36231,29 @@ module mkCore(CLK, assign guard__h822861 = { IF_theResult___snd30797_BIT_4_THEN_2_ELSE_0__q171[1], { _theResult___snd__h830797[3:0], 52'd0 } != 56'd0 } ; - assign highBitsfilter__h1008407 = + assign highBitsfilter__h1008411 = 50'h3FFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign highBitsfilter__h1008810 = + assign highBitsfilter__h1008814 = 50'h3FFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign highBitsfilter__h1009227 = + assign highBitsfilter__h1009231 = 50'h3FFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign highBitsfilter__h1009630 = + assign highBitsfilter__h1009634 = 50'h3FFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign highBitsfilter__h1010299 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign highOffsetBits__h1008408 = x__h1008435 & highBitsfilter__h1008407 ; - assign highOffsetBits__h1008811 = x__h1008435 & highBitsfilter__h1008810 ; - assign highOffsetBits__h1009228 = x__h1008435 & highBitsfilter__h1009227 ; - assign highOffsetBits__h1009631 = x__h1008435 & highBitsfilter__h1009630 ; - assign highOffsetBits__h1010300 = x__h1008435 & highBitsfilter__h1010299 ; - assign highOffsetBits__h1031458 = x__h1031485 & highBitsfilter__h1008407 ; - assign highOffsetBits__h1031861 = x__h1031485 & highBitsfilter__h1008810 ; - assign highOffsetBits__h1032278 = x__h1031485 & highBitsfilter__h1009227 ; - assign highOffsetBits__h1032681 = x__h1031485 & highBitsfilter__h1009630 ; - assign highOffsetBits__h1033348 = x__h1031485 & highBitsfilter__h1010299 ; - assign highOffsetBits__h242644 = x__h242671 & mask__h239862 ; - assign idx__h968878 = + assign highBitsfilter__h1010303 = 50'h3FFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign highOffsetBits__h1008412 = x__h1008439 & highBitsfilter__h1008411 ; + assign highOffsetBits__h1008815 = x__h1008439 & highBitsfilter__h1008814 ; + assign highOffsetBits__h1009232 = x__h1008439 & highBitsfilter__h1009231 ; + assign highOffsetBits__h1009635 = x__h1008439 & highBitsfilter__h1009634 ; + assign highOffsetBits__h1010304 = x__h1008439 & highBitsfilter__h1010303 ; + assign highOffsetBits__h1031462 = x__h1031489 & highBitsfilter__h1008411 ; + assign highOffsetBits__h1031865 = x__h1031489 & highBitsfilter__h1008814 ; + assign highOffsetBits__h1032282 = x__h1031489 & highBitsfilter__h1009231 ; + assign highOffsetBits__h1032685 = x__h1031489 & highBitsfilter__h1009634 ; + assign highOffsetBits__h1033352 = x__h1031489 & highBitsfilter__h1010303 ; + assign highOffsetBits__h242646 = x__h242673 & mask__h239864 ; + assign idx__h968882 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -36263,28 +36263,28 @@ module mkCore(CLK, !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; assign impliedTopBits__h127433 = x__h127517 + len_correction__h127432 ; assign impliedTopBits__h140349 = x__h140433 + len_correction__h140348 ; - assign impliedTopBits__h183610 = x__h183694 + len_correction__h183609 ; - assign impliedTopBits__h202361 = x__h202445 + len_correction__h202360 ; - assign impliedTopBits__h216927 = x__h217011 + len_correction__h216926 ; - assign impliedTopBits__h866990 = x__h867075 + len_correction__h866989 ; - assign impliedTopBits__h867538 = x__h867623 + len_correction__h867537 ; - assign impliedTopBits__h906675 = x__h906760 + len_correction__h906674 ; - assign impliedTopBits__h907223 = x__h907308 + len_correction__h907222 ; - assign impliedTopBits__h995040 = x__h995124 + len_correction__h995039 ; - assign in__h239801 = coreFix_memExe_regToExeQ$first[383:318] & y__h239818 ; - assign in__h240958 = coreFix_memExe_regToExeQ$first[220:155] & y__h240975 ; - assign in__h254582 = coreFix_memExe_dTlb$procResp[452:387] & y__h254599 ; - assign in__h854153 = csrf_stcc_reg[151:86] & y__h854170 ; - assign in__h854458 = + assign impliedTopBits__h183611 = x__h183695 + len_correction__h183610 ; + assign impliedTopBits__h202362 = x__h202446 + len_correction__h202361 ; + assign impliedTopBits__h216928 = x__h217012 + len_correction__h216927 ; + assign impliedTopBits__h866988 = x__h867073 + len_correction__h866987 ; + assign impliedTopBits__h867536 = x__h867621 + len_correction__h867535 ; + assign impliedTopBits__h906678 = x__h906763 + len_correction__h906677 ; + assign impliedTopBits__h907226 = x__h907311 + len_correction__h907225 ; + assign impliedTopBits__h995044 = x__h995128 + len_correction__h995043 ; + assign in__h239803 = coreFix_memExe_regToExeQ$first[383:318] & y__h239820 ; + assign in__h240960 = coreFix_memExe_regToExeQ$first[220:155] & y__h240977 ; + assign in__h254584 = coreFix_memExe_dTlb$procResp[452:387] & y__h254601 ; + assign in__h854151 = csrf_stcc_reg[151:86] & y__h854168 ; + assign in__h854456 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104 & - y__h854475 ; - assign in__h855146 = csrf_mtcc_reg[151:86] & y__h855163 ; - assign in__h855450 = + y__h854473 ; + assign in__h855144 = csrf_mtcc_reg[151:86] & y__h855161 ; + assign in__h855448 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256 & - y__h855467 ; - assign in__h855976 = csrf_rg_dpc[151:86] & y__h855993 ; - assign in__h997691 = pc_address__h994737 & y__h997708 ; - assign k__h945028 = + y__h855465 ; + assign in__h855974 = csrf_rg_dpc[151:86] & y__h855991 ; + assign in__h997695 = pc_address__h994741 & y__h997712 ; + assign k__h945032 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__1196__ETC___d21198 ; @@ -36294,58 +36294,58 @@ module mkCore(CLK, 2'b0 ; assign len_correction__h140348 = INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? 2'b01 : 2'b0 ; - assign len_correction__h183609 = - INV_x83397_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; - assign len_correction__h202360 = - INV_x99249_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; - assign len_correction__h216926 = + assign len_correction__h183610 = + INV_x83398_BITS_108_TO_90__q34[0] ? 2'b01 : 2'b0 ; + assign len_correction__h202361 = + INV_x99250_BITS_108_TO_90__q36[0] ? 2'b01 : 2'b0 ; + assign len_correction__h216927 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? 2'b01 : 2'b0 ; - assign len_correction__h866989 = + assign len_correction__h866987 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? 2'b01 : 2'b0 ; - assign len_correction__h867537 = + assign len_correction__h867535 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? 2'b01 : 2'b0 ; - assign len_correction__h906674 = + assign len_correction__h906677 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? 2'b01 : 2'b0 ; - assign len_correction__h907222 = + assign len_correction__h907225 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? 2'b01 : 2'b0 ; - assign len_correction__h995039 = + assign len_correction__h995043 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? 2'b01 : 2'b0 ; - assign mask__h1000192 = 64'hFFFFFFFFFFFFFFFF << x__h1000253 ; - assign mask__h239862 = + assign mask__h1000196 = 64'hFFFFFFFFFFFFFFFF << x__h1000257 ; + assign mask__h239864 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h239971 = + assign mask__h239973 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign mask__h241019 = + assign mask__h241021 = 50'h3FFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h241128 = + assign mask__h241130 = 52'hFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign mask__h254643 = + assign mask__h254645 = 50'h3FFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h254752 = + assign mask__h254754 = 52'hFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign mask__h999535 = 64'hFFFFFFFFFFFFFFFF << x__h999596 ; - assign mcause_csr__read__h850885 = - { r1__read__h855500, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h850619 = - { r1__read__h855196, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h850222 = - { r1__read__h854873, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h850320 = - { r1__read__h854896, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h850447 = { r1__read__h854920, 1'b0 } ; - assign mip_csr__read__h851124 = { r1__read__h855507, 1'b0 } ; + assign mask__h999539 = 64'hFFFFFFFFFFFFFFFF << x__h999600 ; + assign mcause_csr__read__h850883 = + { r1__read__h855498, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h850617 = + { r1__read__h855194, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h850220 = + { r1__read__h854871, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h850318 = + { r1__read__h854894, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h850445 = { r1__read__h854918, 1'b0 } ; + assign mip_csr__read__h851122 = { r1__read__h855505, 1'b0 } ; assign mmio_pRqQ_empty_64_AND_epochManager_checkEpoch_ETC___d20679 = mmio_pRqQ_empty && epochManager$checkEpoch_0_check && (renameStage_rg_m_halt_req[4] || @@ -36387,56 +36387,56 @@ module mkCore(CLK, fetchStage$pipelines_0_first[273:269] != 5'd24 && fetchStage$pipelines_0_first[273:269] != 5'd25 && rg_core_run_state == 2'd2 ; - assign mstatus_csr__read__h850061 = { r1__read__h854748, csrf_ie_vec_0 } ; - assign n__read__h1014147 = + assign mstatus_csr__read__h850059 = { r1__read__h854746, csrf_ie_vec_0 } ; + assign n__read__h1014151 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h1014223 : + upd__h1014227 : csrf_minstret_ehr_data_rl ; assign n__read__h7908 = csrf_mcycle_ehr_data_lat_0$whas ? upd__h7977 : csrf_mcycle_ehr_data_rl ; - assign newAddrBits__h1008590 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008531[13:0] } ; - assign newAddrBits__h1008993 = + assign newAddrBits__h1008594 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1008535[13:0] } ; + assign newAddrBits__h1008997 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1008934[13:0] } ; - assign newAddrBits__h1009410 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009351[13:0] } ; - assign newAddrBits__h1009813 = + { 2'd0, x__h1008938[13:0] } ; + assign newAddrBits__h1009414 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1009355[13:0] } ; + assign newAddrBits__h1009817 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1009754[13:0] } ; - assign newAddrBits__h1010482 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010423[13:0] } ; - assign newAddrBits__h1031640 = - { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031581[13:0] } ; - assign newAddrBits__h1032043 = + { 2'd0, x__h1009758[13:0] } ; + assign newAddrBits__h1010486 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1010427[13:0] } ; + assign newAddrBits__h1031644 = + { 2'd0, csrf_stcc_reg[13:0] } + { 2'd0, x__h1031585[13:0] } ; + assign newAddrBits__h1032047 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084 } + - { 2'd0, x__h1031984[13:0] } ; - assign newAddrBits__h1032460 = - { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032401[13:0] } ; - assign newAddrBits__h1032863 = + { 2'd0, x__h1031988[13:0] } ; + assign newAddrBits__h1032464 = + { 2'd0, csrf_mtcc_reg[13:0] } + { 2'd0, x__h1032405[13:0] } ; + assign newAddrBits__h1032867 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236 } + - { 2'd0, x__h1032804[13:0] } ; - assign newAddrBits__h1033530 = - { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033471[13:0] } ; - assign newAddrDiff__h1000193 = + { 2'd0, x__h1032808[13:0] } ; + assign newAddrBits__h1033534 = + { 2'd0, csrf_rg_dpc[13:0] } + { 2'd0, x__h1033475[13:0] } ; + assign newAddrDiff__h1000197 = csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - - (address__h999513 & mask__h1000192) ; - assign newAddrDiff__h1000537 = + (address__h999517 & mask__h1000196) ; + assign newAddrDiff__h1000541 = csrf_mtcc_reg_read__6198_BITS_149_TO_86_2813_A_ETC___d22816 - - (base__h999478 & mask__h1000192) ; - assign newAddrDiff__h999536 = + (base__h999482 & mask__h1000196) ; + assign newAddrDiff__h999540 = csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - - (address__h999463 & mask__h999535) ; - assign newAddrDiff__h999880 = + (address__h999467 & mask__h999539) ; + assign newAddrDiff__h999884 = csrf_stcc_reg_read__6046_BITS_149_TO_86_2742_A_ETC___d22745 - - (base__h999424 & mask__h999535) ; - assign new_pc__h872924 = + (base__h999428 & mask__h999539) ; + assign new_pc__h872923 = { coreFix_aluExe_1_exeToFinQ$first[460], coreFix_aluExe_1_exeToFinQ$first[379:364], coreFix_aluExe_1_exeToFinQ$first[362:361], @@ -36448,7 +36448,7 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d17996[1:0], coreFix_aluExe_1_exeToFinQ$first[457:394] } ; - assign new_pc__h912071 = + assign new_pc__h912075 = { coreFix_aluExe_0_exeToFinQ$first[460], coreFix_aluExe_0_exeToFinQ$first[379:364], coreFix_aluExe_0_exeToFinQ$first[362:361], @@ -36460,47 +36460,47 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20111[1:0], coreFix_aluExe_0_exeToFinQ$first[457:394] } ; - assign next_deqP___1__h515611 = + assign next_deqP___1__h515612 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h526388 = + assign next_deqP___1__h526389 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h533666 = + assign next_deqP___1__h533667 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h544301 = + assign next_deqP___1__h544302 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h557949 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h561728 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h1012257 = + assign next_deqP___1__h557950 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h561729 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h1012261 = (rob$deqPort_0_deq_data[196:195] == 2'd0) ? rob$deqPort_0_deq_data[160:32] : - { rob$deqPort_0_deq_data[630:566], address__h1013717 } ; - assign offset__h239697 = + { rob$deqPort_0_deq_data[630:566], address__h1013721 } ; + assign offset__h239699 = { 2'd0, coreFix_memExe_regToExeQ$first[317:304] } - - base__h239696 ; - assign offset__h240854 = + base__h239698 ; + assign offset__h240856 = { 2'd0, coreFix_memExe_regToExeQ$first[154:141] } - - base__h240853 ; - assign offset__h242625 = + base__h240855 ; + assign offset__h242627 = { {32{coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15[31]}}, coreFix_memExe_regToExeQfirst_BITS_434_TO_403__q15 } ; - assign offset__h254478 = - { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254477 ; - assign offset__h854220 = + assign offset__h254480 = + { 2'd0, coreFix_memExe_dTlb$procResp[386:373] } - base__h254479 ; + assign offset__h854218 = { 2'd0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080 } - - base__h854219 ; - assign offset__h855213 = + base__h854217 ; + assign offset__h855211 = { 2'd0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232 } - - base__h855212 ; - assign offset__h895974 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895973 ; - assign offset__h896258 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896257 ; - assign offset__h896603 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896602 ; - assign offset__h997610 = { 2'd0, pc_addrBits__h994738 } - base__h997609 ; + base__h855210 ; + assign offset__h895977 = { 2'd0, csrf_stcc_reg[85:72] } - base__h895976 ; + assign offset__h896261 = { 2'd0, csrf_mtcc_reg[85:72] } - base__h896260 ; + assign offset__h896606 = { 2'd0, csrf_rg_dpc[85:72] } - base__h896605 ; + assign offset__h997614 = { 2'd0, pc_addrBits__h994742 } - base__h997613 ; assign out___1_sfd__h714960 = { f1_sfd__h714897, 29'd0 } ; assign out___1_sfd__h753954 = { f2_sfd__h753891, 29'd0 } ; assign out___1_sfd__h793258 = { f3_sfd__h793195, 29'd0 } ; @@ -36708,27 +36708,27 @@ module mkCore(CLK, _theResult___snd__h830797[5] ? _theResult___sfd__h831532 : _theResult___snd__h830797[56:5] ; - assign pc__h963240 = fetchStage$pipelines_1_first[591:463] ; - assign pc_addrBits__h994738 = + assign pc__h963244 = fetchStage$pipelines_1_first[591:463] ; + assign pc_addrBits__h994742 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? - x__h994909[13:0] : + x__h994913[13:0] : commitStage_commitTrap[122:109] ; - assign pc_address__h994737 = { 2'd0, commitStage_commitTrap[172:109] } ; - assign pend_ints__h920228 = + assign pc_address__h994741 = { 2'd0, commitStage_commitTrap[172:109] } ; + assign pend_ints__h920232 = { _0_CONCAT_csrf_external_int_en_vec_3_read__6183_ETC___d20297, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign pointer__h242635 = + assign pointer__h242637 = coreFix_memExe_regToExeQ$first[383:318] + - { 2'd0, offset__h242625 } ; - assign prv__h1017444 = csrf_prv_reg ; - assign prv__h1017488 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + { 2'd0, offset__h242627 } ; + assign prv__h1017448 = csrf_prv_reg ; + assign prv__h1017492 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; assign q___1__h706456 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h920777 = + assign r1__read_BITS_13_TO_0___h920781 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -36736,119 +36736,119 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h926452 = csrf_fs_reg ; - assign r1__read_BIT_20___h926958 = csrf_tw_reg ; - assign r1__read__h853106 = { r1__read__h853108, csrf_ie_vec_1 } ; - assign r1__read__h853108 = { r1__read__h853110, 2'b0 } ; - assign r1__read__h853110 = { r1__read__h853112, csrf_prev_ie_vec_0 } ; - assign r1__read__h853112 = { r1__read__h853114, csrf_prev_ie_vec_1 } ; - assign r1__read__h853114 = { r1__read__h853116, 2'b0 } ; - assign r1__read__h853116 = { r1__read__h853118, csrf_spp_reg } ; - assign r1__read__h853118 = { r1__read__h853120, 4'b0 } ; - assign r1__read__h853120 = { r1__read__h853122, csrf_fs_reg } ; - assign r1__read__h853122 = { r1__read__h853124, 2'd0 } ; - assign r1__read__h853124 = { r1__read__h853126, 1'b0 } ; - assign r1__read__h853126 = { r1__read__h853128, csrf_sum_reg } ; - assign r1__read__h853128 = { r1__read__h853130, csrf_mxr_reg } ; - assign r1__read__h853130 = { r1__read__h853132, 12'b0 } ; - assign r1__read__h853132 = { r1__read__h853134, 2'b10 } ; - assign r1__read__h853134 = { r__h853138, 29'b0 } ; - assign r1__read__h853510 = - { r1__read__h853512, csrf_software_int_en_vec_1 } ; - assign r1__read__h853512 = { r1__read__h853514, 2'b0 } ; - assign r1__read__h853514 = { r1__read__h853516, 1'b0 } ; - assign r1__read__h853516 = { r1__read__h853518, csrf_timer_int_en_vec_1 } ; - assign r1__read__h853518 = { r1__read__h853520, 2'b0 } ; - assign r1__read__h853520 = { r1__read__h853522, 1'b0 } ; - assign r1__read__h853522 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h854203 = { r1__read__h854205, csrf_scounteren_tm_reg } ; - assign r1__read__h854205 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h854508 = { csrf_scause_interrupt_reg, 58'b0 } ; - assign r1__read__h854515 = - { r1__read__h854517, csrf_software_int_pend_vec_1 } ; - assign r1__read__h854517 = { r1__read__h854519, 2'b0 } ; - assign r1__read__h854519 = { r1__read__h854521, 1'b0 } ; - assign r1__read__h854521 = - { r1__read__h854523, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h854523 = { r1__read__h854525, 2'b0 } ; - assign r1__read__h854525 = { r1__read__h854527, 1'b0 } ; - assign r1__read__h854527 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h854725 = { vm_mode_reg__read__h854731, 16'd0 } ; - assign r1__read__h854748 = { r1__read__h854750, csrf_ie_vec_1 } ; - assign r1__read__h854750 = { r1__read__h854752, 1'b0 } ; - assign r1__read__h854752 = { r1__read__h854754, csrf_ie_vec_3 } ; - assign r1__read__h854754 = { r1__read__h854756, csrf_prev_ie_vec_0 } ; - assign r1__read__h854756 = { r1__read__h854758, csrf_prev_ie_vec_1 } ; - assign r1__read__h854758 = { r1__read__h854760, 1'b0 } ; - assign r1__read__h854760 = { r1__read__h854762, csrf_prev_ie_vec_3 } ; - assign r1__read__h854762 = { r1__read__h854764, csrf_spp_reg } ; - assign r1__read__h854764 = { r1__read__h854766, 2'b0 } ; - assign r1__read__h854766 = { r1__read__h854768, csrf_mpp_reg } ; - assign r1__read__h854768 = { r1__read__h854770, csrf_fs_reg } ; - assign r1__read__h854770 = { r1__read__h854772, 2'd0 } ; - assign r1__read__h854772 = { r1__read__h854774, csrf_mprv_reg } ; - assign r1__read__h854774 = { r1__read__h854776, csrf_sum_reg } ; - assign r1__read__h854776 = { r1__read__h854778, csrf_mxr_reg } ; - assign r1__read__h854778 = { r1__read__h854780, csrf_tvm_reg } ; - assign r1__read__h854780 = { r1__read__h854782, csrf_tw_reg } ; - assign r1__read__h854782 = { r1__read__h854784, csrf_tsr_reg } ; - assign r1__read__h854784 = { r1__read__h854786, 9'b0 } ; + assign r1__read_BITS_13_TO_12___h926456 = csrf_fs_reg ; + assign r1__read_BIT_20___h926962 = csrf_tw_reg ; + assign r1__read__h853104 = { r1__read__h853106, csrf_ie_vec_1 } ; + assign r1__read__h853106 = { r1__read__h853108, 2'b0 } ; + assign r1__read__h853108 = { r1__read__h853110, csrf_prev_ie_vec_0 } ; + assign r1__read__h853110 = { r1__read__h853112, csrf_prev_ie_vec_1 } ; + assign r1__read__h853112 = { r1__read__h853114, 2'b0 } ; + assign r1__read__h853114 = { r1__read__h853116, csrf_spp_reg } ; + assign r1__read__h853116 = { r1__read__h853118, 4'b0 } ; + assign r1__read__h853118 = { r1__read__h853120, csrf_fs_reg } ; + assign r1__read__h853120 = { r1__read__h853122, 2'd0 } ; + assign r1__read__h853122 = { r1__read__h853124, 1'b0 } ; + assign r1__read__h853124 = { r1__read__h853126, csrf_sum_reg } ; + assign r1__read__h853126 = { r1__read__h853128, csrf_mxr_reg } ; + assign r1__read__h853128 = { r1__read__h853130, 12'b0 } ; + assign r1__read__h853130 = { r1__read__h853132, 2'b10 } ; + assign r1__read__h853132 = { r__h853136, 29'b0 } ; + assign r1__read__h853508 = + { r1__read__h853510, csrf_software_int_en_vec_1 } ; + assign r1__read__h853510 = { r1__read__h853512, 2'b0 } ; + assign r1__read__h853512 = { r1__read__h853514, 1'b0 } ; + assign r1__read__h853514 = { r1__read__h853516, csrf_timer_int_en_vec_1 } ; + assign r1__read__h853516 = { r1__read__h853518, 2'b0 } ; + assign r1__read__h853518 = { r1__read__h853520, 1'b0 } ; + assign r1__read__h853520 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h854201 = { r1__read__h854203, csrf_scounteren_tm_reg } ; + assign r1__read__h854203 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h854506 = { csrf_scause_interrupt_reg, 58'b0 } ; + assign r1__read__h854513 = + { r1__read__h854515, csrf_software_int_pend_vec_1 } ; + assign r1__read__h854515 = { r1__read__h854517, 2'b0 } ; + assign r1__read__h854517 = { r1__read__h854519, 1'b0 } ; + assign r1__read__h854519 = + { r1__read__h854521, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h854521 = { r1__read__h854523, 2'b0 } ; + assign r1__read__h854523 = { r1__read__h854525, 1'b0 } ; + assign r1__read__h854525 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h854723 = { vm_mode_reg__read__h854729, 16'd0 } ; + assign r1__read__h854746 = { r1__read__h854748, csrf_ie_vec_1 } ; + assign r1__read__h854748 = { r1__read__h854750, 1'b0 } ; + assign r1__read__h854750 = { r1__read__h854752, csrf_ie_vec_3 } ; + assign r1__read__h854752 = { r1__read__h854754, csrf_prev_ie_vec_0 } ; + assign r1__read__h854754 = { r1__read__h854756, csrf_prev_ie_vec_1 } ; + assign r1__read__h854756 = { r1__read__h854758, 1'b0 } ; + assign r1__read__h854758 = { r1__read__h854760, csrf_prev_ie_vec_3 } ; + assign r1__read__h854760 = { r1__read__h854762, csrf_spp_reg } ; + assign r1__read__h854762 = { r1__read__h854764, 2'b0 } ; + assign r1__read__h854764 = { r1__read__h854766, csrf_mpp_reg } ; + assign r1__read__h854766 = { r1__read__h854768, csrf_fs_reg } ; + assign r1__read__h854768 = { r1__read__h854770, 2'd0 } ; + assign r1__read__h854770 = { r1__read__h854772, csrf_mprv_reg } ; + assign r1__read__h854772 = { r1__read__h854774, csrf_sum_reg } ; + assign r1__read__h854774 = { r1__read__h854776, csrf_mxr_reg } ; + assign r1__read__h854776 = { r1__read__h854778, csrf_tvm_reg } ; + assign r1__read__h854778 = { r1__read__h854780, csrf_tw_reg } ; + assign r1__read__h854780 = { r1__read__h854782, csrf_tsr_reg } ; + assign r1__read__h854782 = { r1__read__h854784, 9'b0 } ; + assign r1__read__h854784 = { r1__read__h854786, 2'b10 } ; assign r1__read__h854786 = { r1__read__h854788, 2'b10 } ; - assign r1__read__h854788 = { r1__read__h854790, 2'b10 } ; - assign r1__read__h854790 = { r__h853138, 27'b0 } ; - assign r1__read__h854873 = { r1__read__h854875, 1'b0 } ; - assign r1__read__h854875 = { r1__read__h854877, csrf_medeleg_13_11_reg } ; - assign r1__read__h854877 = { r1__read__h854879, 1'b0 } ; - assign r1__read__h854879 = { r1__read__h854881, csrf_medeleg_15_reg } ; - assign r1__read__h854881 = { r1__read__h854883, 10'b0 } ; - assign r1__read__h854883 = { 35'b0, csrf_medeleg_28_26_reg } ; - assign r1__read__h854896 = { r1__read__h854898, 1'b0 } ; - assign r1__read__h854898 = { r1__read__h854900, csrf_mideleg_5_3_reg } ; - assign r1__read__h854900 = { r1__read__h854902, 1'b0 } ; - assign r1__read__h854902 = { r1__read__h854904, csrf_mideleg_9_7_reg } ; - assign r1__read__h854904 = { r1__read__h854906, 1'b0 } ; - assign r1__read__h854906 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h854920 = - { r1__read__h854922, csrf_software_int_en_vec_1 } ; - assign r1__read__h854922 = { r1__read__h854924, 1'b0 } ; - assign r1__read__h854924 = - { r1__read__h854926, csrf_software_int_en_vec_3 } ; - assign r1__read__h854926 = { r1__read__h854928, 1'b0 } ; - assign r1__read__h854928 = { r1__read__h854930, csrf_timer_int_en_vec_1 } ; - assign r1__read__h854930 = { r1__read__h854932, 1'b0 } ; - assign r1__read__h854932 = { r1__read__h854934, csrf_timer_int_en_vec_3 } ; - assign r1__read__h854934 = { r1__read__h854936, 1'b0 } ; - assign r1__read__h854936 = - { r1__read__h854938, csrf_external_int_en_vec_1 } ; - assign r1__read__h854938 = { r1__read__h854940, 1'b0 } ; - assign r1__read__h854940 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h855196 = { r1__read__h855198, csrf_mcounteren_tm_reg } ; - assign r1__read__h855198 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h855500 = { csrf_mcause_interrupt_reg, 58'd0 } ; - assign r1__read__h855507 = - { r1__read__h855509, csrf_software_int_pend_vec_1 } ; - assign r1__read__h855509 = { r1__read__h855511, 1'b0 } ; - assign r1__read__h855511 = - { r1__read__h855513, csrf_software_int_pend_vec_3 } ; - assign r1__read__h855513 = { r1__read__h855515, 1'b0 } ; - assign r1__read__h855515 = - { r1__read__h855517, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h855517 = { r1__read__h855519, 1'b0 } ; - assign r1__read__h855519 = - { r1__read__h855521, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h855521 = { r1__read__h855523, 1'b0 } ; - assign r1__read__h855523 = - { r1__read__h855525, csrf_external_int_pend_vec_1 } ; - assign r1__read__h855525 = { r1__read__h855527, 1'b0 } ; - assign r1__read__h855527 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h855836 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign r1__read__h854788 = { r__h853136, 27'b0 } ; + assign r1__read__h854871 = { r1__read__h854873, 1'b0 } ; + assign r1__read__h854873 = { r1__read__h854875, csrf_medeleg_13_11_reg } ; + assign r1__read__h854875 = { r1__read__h854877, 1'b0 } ; + assign r1__read__h854877 = { r1__read__h854879, csrf_medeleg_15_reg } ; + assign r1__read__h854879 = { r1__read__h854881, 10'b0 } ; + assign r1__read__h854881 = { 35'b0, csrf_medeleg_28_26_reg } ; + assign r1__read__h854894 = { r1__read__h854896, 1'b0 } ; + assign r1__read__h854896 = { r1__read__h854898, csrf_mideleg_5_3_reg } ; + assign r1__read__h854898 = { r1__read__h854900, 1'b0 } ; + assign r1__read__h854900 = { r1__read__h854902, csrf_mideleg_9_7_reg } ; + assign r1__read__h854902 = { r1__read__h854904, 1'b0 } ; + assign r1__read__h854904 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h854918 = + { r1__read__h854920, csrf_software_int_en_vec_1 } ; + assign r1__read__h854920 = { r1__read__h854922, 1'b0 } ; + assign r1__read__h854922 = + { r1__read__h854924, csrf_software_int_en_vec_3 } ; + assign r1__read__h854924 = { r1__read__h854926, 1'b0 } ; + assign r1__read__h854926 = { r1__read__h854928, csrf_timer_int_en_vec_1 } ; + assign r1__read__h854928 = { r1__read__h854930, 1'b0 } ; + assign r1__read__h854930 = { r1__read__h854932, csrf_timer_int_en_vec_3 } ; + assign r1__read__h854932 = { r1__read__h854934, 1'b0 } ; + assign r1__read__h854934 = + { r1__read__h854936, csrf_external_int_en_vec_1 } ; + assign r1__read__h854936 = { r1__read__h854938, 1'b0 } ; + assign r1__read__h854938 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h855194 = { r1__read__h855196, csrf_mcounteren_tm_reg } ; + assign r1__read__h855196 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h855498 = { csrf_mcause_interrupt_reg, 58'd0 } ; + assign r1__read__h855505 = + { r1__read__h855507, csrf_software_int_pend_vec_1 } ; + assign r1__read__h855507 = { r1__read__h855509, 1'b0 } ; + assign r1__read__h855509 = + { r1__read__h855511, csrf_software_int_pend_vec_3 } ; + assign r1__read__h855511 = { r1__read__h855513, 1'b0 } ; + assign r1__read__h855513 = + { r1__read__h855515, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h855515 = { r1__read__h855517, 1'b0 } ; + assign r1__read__h855517 = + { r1__read__h855519, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h855519 = { r1__read__h855521, 1'b0 } ; + assign r1__read__h855521 = + { r1__read__h855523, csrf_external_int_pend_vec_1 } ; + assign r1__read__h855523 = { r1__read__h855525, 1'b0 } ; + assign r1__read__h855525 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h855834 = { 4'd0, csrf_rg_tdata1_dmode } ; assign rVal1__h714517 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; assign rVal2__h714518 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; assign r___1__h706482 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; - assign r__h853138 = csrf_fs_reg == 2'b11 ; - assign r__h855582 = csrf_software_int_pend_vec_3 ; + assign r__h853136 = csrf_fs_reg == 2'b11 ; + assign r__h855580 = csrf_software_int_pend_vec_3 ; assign regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21039 = regRenamingTable$RDY_rename_0_getRename && rob$RDY_enqPort_0_enq && @@ -37051,37 +37051,37 @@ module mkCore(CLK, fetchStage$pipelines_0_first[69] || checkForException___d20654[13] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h968739 = + assign renaming_spec_bits__h968743 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h963383 : + y_avValue_snd_fst__h963387 : specTagManager$currentSpecBits ; - assign repBoundBits__h242650 = + assign repBoundBits__h242652 = { coreFix_memExe_regToExeQ$first[231:229], 11'd0 } ; - assign repBound__h237315 = rf$read_3_rd1[13:11] - 3'b001 ; - assign repBound__h239000 = rf$read_3_rd2[13:11] - 3'b001 ; - assign repBound__h248215 = + assign repBound__h237317 = rf$read_3_rd1[13:11] - 3'b001 ; + assign repBound__h239002 = rf$read_3_rd2[13:11] - 3'b001 ; + assign repBound__h248217 = coreFix_memExe_regToExeQ$first[245:243] - 3'b001 ; - assign repBound__h248740 = csrf_ddc_reg[13:11] - 3'b001 ; - assign repBound__h854075 = csrf_stcc_reg[13:11] - 3'b001 ; - assign repBound__h854397 = + assign repBound__h248742 = csrf_ddc_reg[13:11] - 3'b001 ; + assign repBound__h854073 = csrf_stcc_reg[13:11] - 3'b001 ; + assign repBound__h854395 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[13:11] - 3'b001 ; - assign repBound__h855068 = csrf_mtcc_reg[13:11] - 3'b001 ; - assign repBound__h855389 = + assign repBound__h855066 = csrf_mtcc_reg[13:11] - 3'b001 ; + assign repBound__h855387 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[13:11] - 3'b001 ; - assign repBound__h855898 = csrf_rg_dpc[13:11] - 3'b001 ; - assign repBound__h857576 = rf$read_1_rd1[13:11] - 3'b001 ; - assign repBound__h860538 = rf$read_1_rd2[13:11] - 3'b001 ; - assign repBound__h860556 = thin_bounds_baseBits__h860421[13:11] - 3'b001 ; - assign repBound__h867139 = x__h867078[13:11] - 3'b001 ; - assign repBound__h867687 = x__h867626[13:11] - 3'b001 ; - assign repBound__h898284 = rf$read_0_rd1[13:11] - 3'b001 ; - assign repBound__h900611 = rf$read_0_rd2[13:11] - 3'b001 ; - assign repBound__h900629 = thin_bounds_baseBits__h900514[13:11] - 3'b001 ; - assign repBound__h906824 = x__h906763[13:11] - 3'b001 ; - assign repBound__h907372 = x__h907311[13:11] - 3'b001 ; - assign repBound__h997634 = x__h995127[13:11] - 3'b001 ; + assign repBound__h855896 = csrf_rg_dpc[13:11] - 3'b001 ; + assign repBound__h857574 = rf$read_1_rd1[13:11] - 3'b001 ; + assign repBound__h860536 = rf$read_1_rd2[13:11] - 3'b001 ; + assign repBound__h860554 = thin_bounds_baseBits__h860419[13:11] - 3'b001 ; + assign repBound__h867137 = x__h867076[13:11] - 3'b001 ; + assign repBound__h867685 = x__h867624[13:11] - 3'b001 ; + assign repBound__h898287 = rf$read_0_rd1[13:11] - 3'b001 ; + assign repBound__h900614 = rf$read_0_rd2[13:11] - 3'b001 ; + assign repBound__h900632 = thin_bounds_baseBits__h900517[13:11] - 3'b001 ; + assign repBound__h906827 = x__h906766[13:11] - 3'b001 ; + assign repBound__h907375 = x__h907314[13:11] - 3'b001 ; + assign repBound__h997638 = x__h995131[13:11] - 3'b001 ; assign res_addrBits__h126822 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? x__h127302[13:0] : @@ -37090,44 +37090,44 @@ module mkCore(CLK, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? x__h140218[13:0] : mmio_dataRespQ_data_0[13:0] ; - assign res_addrBits__h178897 = - INV_x83397_BITS_108_TO_90__q34[0] ? - x__h183479[13:0] : - x__h183397[13:0] ; - assign res_addrBits__h197662 = - INV_x99249_BITS_108_TO_90__q36[0] ? - x__h202230[13:0] : - x__h199249[13:0] ; - assign res_addrBits__h216421 = + assign res_addrBits__h178898 = + INV_x83398_BITS_108_TO_90__q34[0] ? + x__h183480[13:0] : + x__h183398[13:0] ; + assign res_addrBits__h197663 = + INV_x99250_BITS_108_TO_90__q36[0] ? + x__h202231[13:0] : + x__h199250[13:0] ; + assign res_addrBits__h216422 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? - x__h216796[13:0] : + x__h216797[13:0] : coreFix_memExe_lsq$respLd[13:0] ; - assign res_addrBits__h235321 = { 2'b0, addr__h235314[63:52] } ; - assign res_addrBits__h567344 = + assign res_addrBits__h235323 = { 2'b0, addr__h235316[63:52] } ; + assign res_addrBits__h567345 = { 2'b0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:90] } ; assign res_addrBits__h568197 = { 2'b0, data__h567678[63:52] } ; assign res_addrBits__h613954 = { 2'b0, data__h613438[63:52] } ; assign res_addrBits__h659701 = { 2'b0, data__h659185[63:52] } ; assign res_addrBits__h705510 = { 2'b0, data__h704999[63:52] } ; assign res_addrBits__h706370 = { 2'b0, data__h705862[63:52] } ; - assign res_addrBits__h848643 = { 2'b0, addr__h843948[63:52] } ; - assign res_addrBits__h892145 = { 2'b0, addr__h887458[63:52] } ; + assign res_addrBits__h848642 = { 2'b0, addr__h843947[63:52] } ; + assign res_addrBits__h892147 = { 2'b0, addr__h887460[63:52] } ; assign res_address__h126821 = { 2'd0, coreFix_memExe_respLrScAmoQ_data_0[63:0] } ; assign res_address__h139733 = { 2'd0, mmio_dataRespQ_data_0[63:0] } ; - assign res_address__h178896 = { 2'd0, x__h183397[63:0] } ; - assign res_address__h197661 = { 2'd0, x__h199249[63:0] } ; - assign res_address__h216420 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; - assign res_address__h235320 = { 2'd0, addr__h235314 } ; - assign res_address__h567343 = + assign res_address__h178897 = { 2'd0, x__h183398[63:0] } ; + assign res_address__h197662 = { 2'd0, x__h199250[63:0] } ; + assign res_address__h216421 = { 2'd0, coreFix_memExe_lsq$respLd[63:0] } ; + assign res_address__h235322 = { 2'd0, addr__h235316 } ; + assign res_address__h567344 = { 2'd0, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38] } ; assign res_address__h568196 = { 2'd0, data__h567678 } ; assign res_address__h613953 = { 2'd0, data__h613438 } ; assign res_address__h659700 = { 2'd0, data__h659185 } ; assign res_address__h705509 = { 2'd0, data__h704999 } ; assign res_address__h706369 = { 2'd0, data__h705862 } ; - assign res_address__h848642 = { 2'd0, addr__h843948 } ; - assign res_address__h892144 = { 2'd0, addr__h887458 } ; + assign res_address__h848641 = { 2'd0, addr__h843947 } ; + assign res_address__h892146 = { 2'd0, addr__h887460 } ; assign res_data__h568236 = { 32'hFFFFFFFF, x__h568251 } ; assign res_data__h568241 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37369,18 +37369,18 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d12177 } ; - assign resp_addr__h509110 = + assign resp_addr__h509111 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[169:158] } ; - assign result__h240597 = + assign result__h240599 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64], coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[63:0] } ; - assign result__h241754 = + assign result__h241756 = { 1'd0, ~coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64], coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[63:0] } ; - assign result__h255378 = + assign result__h255380 = { 1'd0, ~coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64], coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[63:0] } ; @@ -37408,99 +37408,99 @@ module mkCore(CLK, { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d13519[0] | guard__h814390 } ; - assign result__h915808 = w__h915803 & y__h915837 ; - assign result__h915859 = ~x__h915858 ; - assign result_d_addrBits__h1008602 = + assign result__h915812 = w__h915807 & y__h915841 ; + assign result__h915863 = ~x__h915862 ; + assign result_d_addrBits__h1008606 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1008590[12:0] } : - newAddrBits__h1008590[13:0] ; - assign result_d_addrBits__h1009005 = + { 1'b0, newAddrBits__h1008594[12:0] } : + newAddrBits__h1008594[13:0] ; + assign result_d_addrBits__h1009009 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1008993[12:0] } : - newAddrBits__h1008993[13:0] ; - assign result_d_addrBits__h1009422 = + { 1'b0, newAddrBits__h1008997[12:0] } : + newAddrBits__h1008997[13:0] ; + assign result_d_addrBits__h1009426 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1009410[12:0] } : - newAddrBits__h1009410[13:0] ; - assign result_d_addrBits__h1009825 = + { 1'b0, newAddrBits__h1009414[12:0] } : + newAddrBits__h1009414[13:0] ; + assign result_d_addrBits__h1009829 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1009813[12:0] } : - newAddrBits__h1009813[13:0] ; - assign result_d_addrBits__h1010494 = + { 1'b0, newAddrBits__h1009817[12:0] } : + newAddrBits__h1009817[13:0] ; + assign result_d_addrBits__h1010498 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1010482[12:0] } : - newAddrBits__h1010482[13:0] ; - assign result_d_addrBits__h1031652 = + { 1'b0, newAddrBits__h1010486[12:0] } : + newAddrBits__h1010486[13:0] ; + assign result_d_addrBits__h1031656 = (csrf_stcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1031640[12:0] } : - newAddrBits__h1031640[13:0] ; - assign result_d_addrBits__h1032055 = + { 1'b0, newAddrBits__h1031644[12:0] } : + newAddrBits__h1031644[13:0] ; + assign result_d_addrBits__h1032059 = (IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 == 6'd52) ? - { 1'b0, newAddrBits__h1032043[12:0] } : - newAddrBits__h1032043[13:0] ; - assign result_d_addrBits__h1032472 = + { 1'b0, newAddrBits__h1032047[12:0] } : + newAddrBits__h1032047[13:0] ; + assign result_d_addrBits__h1032476 = (csrf_mtcc_reg[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1032460[12:0] } : - newAddrBits__h1032460[13:0] ; - assign result_d_addrBits__h1032875 = + { 1'b0, newAddrBits__h1032464[12:0] } : + newAddrBits__h1032464[13:0] ; + assign result_d_addrBits__h1032879 = (IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 == 6'd52) ? - { 1'b0, newAddrBits__h1032863[12:0] } : - newAddrBits__h1032863[13:0] ; - assign result_d_addrBits__h1033542 = + { 1'b0, newAddrBits__h1032867[12:0] } : + newAddrBits__h1032867[13:0] ; + assign result_d_addrBits__h1033546 = (csrf_rg_dpc[33:28] == 6'd52) ? - { 1'b0, newAddrBits__h1033530[12:0] } : - newAddrBits__h1033530[13:0] ; - assign result_d_address__h1008601 = - { 2'd0, bot__h1008623 } + + { 1'b0, newAddrBits__h1033534[12:0] } : + newAddrBits__h1033534[13:0] ; + assign result_d_address__h1008605 = + { 2'd0, bot__h1008627 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009004 = - { 2'd0, bot__h1009026 } + + assign result_d_address__h1009008 = + { 2'd0, bot__h1009030 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009421 = - { 2'd0, bot__h1009443 } + + assign result_d_address__h1009425 = + { 2'd0, bot__h1009447 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1009824 = - { 2'd0, bot__h1009846 } + + assign result_d_address__h1009828 = + { 2'd0, bot__h1009850 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1010493 = - { 2'd0, bot__h1010516 } + + assign result_d_address__h1010497 = + { 2'd0, bot__h1010520 } + { 2'd0, rob$deqPort_0_deq_data[95:32] } ; - assign result_d_address__h1031651 = - { 2'd0, bot__h1008623 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032054 = - { 2'd0, bot__h1009026 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032471 = - { 2'd0, bot__h1009443 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1032874 = - { 2'd0, bot__h1009846 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h1033541 = - { 2'd0, bot__h1010516 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; - assign result_d_address__h242846 = { 2'd0, pointer__h242635[63:0] } ; - assign ret__h239974 = + assign result_d_address__h1031655 = + { 2'd0, bot__h1008627 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032058 = + { 2'd0, bot__h1009030 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032475 = + { 2'd0, bot__h1009447 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1032878 = + { 2'd0, bot__h1009850 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h1033545 = + { 2'd0, bot__h1010520 } + { 2'd0, f_csr_reqs$D_OUT[63:0] } ; + assign result_d_address__h242848 = { 2'd0, pointer__h242637[63:0] } ; + assign ret__h239976 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_383_T_ETC___d3704[64:0] } ; - assign ret__h241131 = + assign ret__h241133 = { 1'd0, coreFix_memExe_regToExeQ_first__645_BITS_220_T_ETC___d3766[64:0] } ; - assign ret__h254755 = + assign ret__h254757 = { 1'd0, coreFix_memExe_dTlb_procResp__257_BITS_452_TO__ETC___d4407[64:0] } ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19097 = - rf$read_0_rd1[27:25] < repBound__h898284 ; + rf$read_0_rd1[27:25] < repBound__h898287 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19110 = - rf$read_0_rd1[13:11] < repBound__h898284 ; + rf$read_0_rd1[13:11] < repBound__h898287 ; assign rf_read_0_rd1_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19124 = - rf$read_0_rd1[85:83] < repBound__h898284 ; + rf$read_0_rd1[85:83] < repBound__h898287 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 = - rf$read_0_rd2[27:25] < repBound__h900611 ; + rf$read_0_rd2[27:25] < repBound__h900614 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19169 = - rf$read_0_rd2[13:11] < repBound__h900611 ; + rf$read_0_rd2[13:11] < repBound__h900614 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171 = - rf$read_0_rd2[85:83] < repBound__h900611 ; + rf$read_0_rd2[85:83] < repBound__h900614 ; assign rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19181 = { rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19171, (rf_read_0_rd2_coreFix_aluExe_0_dispToRegQ_firs_ETC___d19168 == @@ -37518,17 +37518,17 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16702 = - rf$read_1_rd1[27:25] < repBound__h857576 ; + rf$read_1_rd1[27:25] < repBound__h857574 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16715 = - rf$read_1_rd1[13:11] < repBound__h857576 ; + rf$read_1_rd1[13:11] < repBound__h857574 ; assign rf_read_1_rd1_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16729 = - rf$read_1_rd1[85:83] < repBound__h857576 ; + rf$read_1_rd1[85:83] < repBound__h857574 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 = - rf$read_1_rd2[27:25] < repBound__h860538 ; + rf$read_1_rd2[27:25] < repBound__h860536 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16774 = - rf$read_1_rd2[13:11] < repBound__h860538 ; + rf$read_1_rd2[13:11] < repBound__h860536 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776 = - rf$read_1_rd2[85:83] < repBound__h860538 ; + rf$read_1_rd2[85:83] < repBound__h860536 ; assign rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16786 = { rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16776, (rf_read_1_rd2_coreFix_aluExe_1_dispToRegQ_firs_ETC___d16773 == @@ -37546,25 +37546,25 @@ module mkCore(CLK, 2'd1 : 2'd3) } ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3331 = - rf$read_3_rd1[27:25] < repBound__h237315 ; + rf$read_3_rd1[27:25] < repBound__h237317 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3344 = - rf$read_3_rd1[13:11] < repBound__h237315 ; + rf$read_3_rd1[13:11] < repBound__h237317 ; assign rf_read_3_rd1_coreFix_memExe_dispToRegQ_first__ETC___d3358 = - rf$read_3_rd1[85:83] < repBound__h237315 ; + rf$read_3_rd1[85:83] < repBound__h237317 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3592 = - rf$read_3_rd2[27:25] < repBound__h239000 ; + rf$read_3_rd2[27:25] < repBound__h239002 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3600 = - rf$read_3_rd2[13:11] < repBound__h239000 ; + rf$read_3_rd2[13:11] < repBound__h239002 ; assign rf_read_3_rd2_coreFix_memExe_dispToRegQ_first__ETC___d3609 = - rf$read_3_rd2[85:83] < repBound__h239000 ; + rf$read_3_rd2[85:83] < repBound__h239002 ; assign rg_core_run_state_read__0682_EQ_2_0683_AND_NOT_ETC___d23895 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h852225 = - { r1__read__h855836, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h852223 = + { r1__read__h855834, csrf_rg_tdata1_data } ; assign rob_enqPort_1_canEnq__1634_AND_epochManager_ch_ETC___d21639 = rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check && (!fetchStage$pipelines_0_canDeq || @@ -37574,7 +37574,7 @@ module mkCore(CLK, IF_IF_fetchStage_pipelines_0_first__0256_BITS__ETC___d21231) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q17 = rob$deqPort_0_deq_data[95:32] ; - assign satp_csr__read__h849915 = { r1__read__h854725, csrf_ppn_reg } ; + assign satp_csr__read__h849913 = { r1__read__h854723, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d12442 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d12398 && @@ -37598,10 +37598,10 @@ module mkCore(CLK, CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64] ; - assign scause_csr__read__h849712 = - { r1__read__h854508, csrf_scause_code_reg } ; - assign scounteren_csr__read__h849572 = - { r1__read__h854203, csrf_scounteren_cy_reg } ; + assign scause_csr__read__h849710 = + { r1__read__h854506, csrf_scause_code_reg } ; + assign scounteren_csr__read__h849570 = + { r1__read__h854201, csrf_scounteren_cy_reg } ; assign sfd__h568847 = { value__h577074, 3'd0 } ; assign sfd__h584655 = { 1'b0, @@ -37749,46 +37749,46 @@ module mkCore(CLK, _theResult____h813782[56] ? _theResult___snd__h822029 : _theResult___snd__h822040 ; - assign sie_csr__read__h849484 = { r1__read__h853510, 1'b0 } ; - assign signBits__h1008405 = + assign sie_csr__read__h849482 = { r1__read__h853508, 1'b0 } ; + assign signBits__h1008409 = {50{robdeqPort_0_deq_data_BITS_95_TO_32__q17[63]}} ; - assign signBits__h1031455 = {50{f_csr_reqs$D_OUT[63]}} ; - assign signBits__h242641 = {50{offset__h242625[63]}} ; - assign sip_csr__read__h849852 = { r1__read__h854515, 1'b0 } ; - assign spec_bits__h973790 = specTagManager$currentSpecBits | y__h973803 ; - assign sstatus_csr__read__h849414 = { r1__read__h853106, csrf_ie_vec_0 } ; - assign tb__h867136 = { impliedTopBits__h866990, topBits__h866986[11] } ; - assign tb__h867684 = { impliedTopBits__h867538, topBits__h867534[11] } ; - assign tb__h906821 = { impliedTopBits__h906675, topBits__h906671[11] } ; - assign tb__h907369 = { impliedTopBits__h907223, topBits__h907219[11] } ; - assign thin_address__h999417 = + assign signBits__h1031459 = {50{f_csr_reqs$D_OUT[63]}} ; + assign signBits__h242643 = {50{offset__h242627[63]}} ; + assign sip_csr__read__h849850 = { r1__read__h854513, 1'b0 } ; + assign spec_bits__h973794 = specTagManager$currentSpecBits | y__h973807 ; + assign sstatus_csr__read__h849412 = { r1__read__h853104, csrf_ie_vec_0 } ; + assign tb__h867134 = { impliedTopBits__h866988, topBits__h866984[11] } ; + assign tb__h867682 = { impliedTopBits__h867536, topBits__h867532[11] } ; + assign tb__h906824 = { impliedTopBits__h906678, topBits__h906674[11] } ; + assign tb__h907372 = { impliedTopBits__h907226, topBits__h907222[11] } ; + assign thin_address__h999421 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? IF_csrf_stcc_reg_read__6046_BIT_86_2738_AND_NO_ETC___d22906 : IF_csrf_mtcc_reg_read__6198_BIT_86_2809_AND_NO_ETC___d22907 ; - assign tmpAddr__h242834 = pointer__h242635[63:0] ; + assign tmpAddr__h242836 = pointer__h242637[63:0] ; assign tmp_expBotHalf__h127295 = { ~coreFix_memExe_respLrScAmoQ_data_0[66], coreFix_memExe_respLrScAmoQ_data_0[65:64] } ; assign tmp_expBotHalf__h140211 = { ~mmio_dataRespQ_data_0[66], mmio_dataRespQ_data_0[65:64] } ; - assign tmp_expBotHalf__h183472 = { ~x__h183397[66], x__h183397[65:64] } ; - assign tmp_expBotHalf__h202223 = { ~x__h199249[66], x__h199249[65:64] } ; - assign tmp_expBotHalf__h216789 = + assign tmp_expBotHalf__h183473 = { ~x__h183398[66], x__h183398[65:64] } ; + assign tmp_expBotHalf__h202224 = { ~x__h199250[66], x__h199250[65:64] } ; + assign tmp_expBotHalf__h216790 = { ~coreFix_memExe_lsq$respLd[66], coreFix_memExe_lsq$respLd[65:64] } ; - assign tmp_expBotHalf__h866839 = + assign tmp_expBotHalf__h866837 = { ~coreFix_aluExe_1_regToExeQ$first[244], coreFix_aluExe_1_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h867387 = + assign tmp_expBotHalf__h867385 = { ~coreFix_aluExe_1_regToExeQ$first[115], coreFix_aluExe_1_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h906524 = + assign tmp_expBotHalf__h906527 = { ~coreFix_aluExe_0_regToExeQ$first[244], coreFix_aluExe_0_regToExeQ$first[243:242] } ; - assign tmp_expBotHalf__h907072 = + assign tmp_expBotHalf__h907075 = { ~coreFix_aluExe_0_regToExeQ$first[115], coreFix_aluExe_0_regToExeQ$first[114:113] } ; - assign tmp_expBotHalf__h994902 = + assign tmp_expBotHalf__h994906 = { ~commitStage_commitTrap[175], commitStage_commitTrap[174:173] } ; assign tmp_expTopHalf__h127293 = @@ -37796,51 +37796,51 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_data_0[78] } ; assign tmp_expTopHalf__h140209 = { ~mmio_dataRespQ_data_0[80:79], mmio_dataRespQ_data_0[78] } ; - assign tmp_expTopHalf__h183470 = { ~x__h183397[80:79], x__h183397[78] } ; - assign tmp_expTopHalf__h202221 = { ~x__h199249[80:79], x__h199249[78] } ; - assign tmp_expTopHalf__h216787 = + assign tmp_expTopHalf__h183471 = { ~x__h183398[80:79], x__h183398[78] } ; + assign tmp_expTopHalf__h202222 = { ~x__h199250[80:79], x__h199250[78] } ; + assign tmp_expTopHalf__h216788 = { ~coreFix_memExe_lsq$respLd[80:79], coreFix_memExe_lsq$respLd[78] } ; - assign tmp_expTopHalf__h866837 = + assign tmp_expTopHalf__h866835 = { ~coreFix_aluExe_1_regToExeQ$first[258:257], coreFix_aluExe_1_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h867385 = + assign tmp_expTopHalf__h867383 = { ~coreFix_aluExe_1_regToExeQ$first[129:128], coreFix_aluExe_1_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h906522 = + assign tmp_expTopHalf__h906525 = { ~coreFix_aluExe_0_regToExeQ$first[258:257], coreFix_aluExe_0_regToExeQ$first[256] } ; - assign tmp_expTopHalf__h907070 = + assign tmp_expTopHalf__h907073 = { ~coreFix_aluExe_0_regToExeQ$first[129:128], coreFix_aluExe_0_regToExeQ$first[127] } ; - assign tmp_expTopHalf__h994900 = + assign tmp_expTopHalf__h994904 = { ~commitStage_commitTrap[189:188], commitStage_commitTrap[187] } ; - assign toBoundsM1__h1008418 = { 3'b110, ~csrf_stcc_reg[10:0] } ; - assign toBoundsM1__h1008821 = + assign toBoundsM1__h1008422 = { 3'b110, ~csrf_stcc_reg[10:0] } ; + assign toBoundsM1__h1008825 = { 3'b110, ~IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBoundsM1__h1009238 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; - assign toBoundsM1__h1009641 = + assign toBoundsM1__h1009242 = { 3'b110, ~csrf_mtcc_reg[10:0] } ; + assign toBoundsM1__h1009645 = { 3'b110, ~IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBoundsM1__h1010310 = { 3'b110, ~csrf_rg_dpc[10:0] } ; - assign toBoundsM1__h242654 = - repBoundBits__h242650 + + assign toBoundsM1__h1010314 = { 3'b110, ~csrf_rg_dpc[10:0] } ; + assign toBoundsM1__h242656 = + repBoundBits__h242652 + ~coreFix_memExe_regToExeQ$first[317:304] ; - assign toBounds__h1008417 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; - assign toBounds__h1008820 = + assign toBounds__h1008421 = 14'd14336 - { 3'b0, csrf_stcc_reg[10:0] } ; + assign toBounds__h1008824 = 14'd14336 - { 3'b0, IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084[10:0] } ; - assign toBounds__h1009237 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; - assign toBounds__h1009640 = + assign toBounds__h1009241 = 14'd14336 - { 3'b0, csrf_mtcc_reg[10:0] } ; + assign toBounds__h1009644 = 14'd14336 - { 3'b0, IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236[10:0] } ; - assign toBounds__h1010309 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; - assign toBounds__h242653 = - repBoundBits__h242650 - coreFix_memExe_regToExeQ$first[317:304] ; + assign toBounds__h1010313 = 14'd14336 - { 3'b0, csrf_rg_dpc[10:0] } ; + assign toBounds__h242655 = + repBoundBits__h242652 - coreFix_memExe_regToExeQ$first[317:304] ; assign topBits__h127429 = INV_coreFix_memExe_respLrScAmoQ_data_0_BITS_10_ETC__q8[0] ? { coreFix_memExe_respLrScAmoQ_data_0[89:81], 3'd0 } : @@ -37849,40 +37849,40 @@ module mkCore(CLK, INV_mmio_dataRespQ_data_0_BITS_108_TO_90__q9[0] ? { mmio_dataRespQ_data_0[89:81], 3'd0 } : b_top__h140442 ; - assign topBits__h183606 = - INV_x83397_BITS_108_TO_90__q34[0] ? - { x__h183397[89:81], 3'd0 } : - b_top__h183703 ; - assign topBits__h202357 = - INV_x99249_BITS_108_TO_90__q36[0] ? - { x__h199249[89:81], 3'd0 } : - b_top__h202454 ; - assign topBits__h216923 = + assign topBits__h183607 = + INV_x83398_BITS_108_TO_90__q34[0] ? + { x__h183398[89:81], 3'd0 } : + b_top__h183704 ; + assign topBits__h202358 = + INV_x99250_BITS_108_TO_90__q36[0] ? + { x__h199250[89:81], 3'd0 } : + b_top__h202455 ; + assign topBits__h216924 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[89:81], 3'd0 } : - b_top__h217020 ; - assign topBits__h866986 = + b_top__h217021 ; + assign topBits__h866984 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[267:259], 3'd0 } : - b_top__h867084 ; - assign topBits__h867534 = + b_top__h867082 ; + assign topBits__h867532 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[138:130], 3'd0 } : - b_top__h867632 ; - assign topBits__h906671 = + b_top__h867630 ; + assign topBits__h906674 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[267:259], 3'd0 } : - b_top__h906769 ; - assign topBits__h907219 = + b_top__h906772 ; + assign topBits__h907222 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[138:130], 3'd0 } : - b_top__h907317 ; - assign topBits__h995036 = + b_top__h907320 ; + assign topBits__h995040 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[198:190], 3'd0 } : - b_top__h995133 ; - assign trap_val__h997075 = { 53'd0, x__h998896 } ; - assign upd__h1014223 = + b_top__h995137 ; + assign trap_val__h997079 = { 53'd0, x__h998900 } ; + assign upd__h1014227 = MUX_csrf_minstret_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; @@ -37895,7 +37895,7 @@ module mkCore(CLK, MUX_csrf_mcycle_ehr_data_lat_0$wset_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h1012296 = + assign v__h1012300 = { csrf_sepcc_reg_data_rl[152], csrf_sepcc_reg_data_rl[71:56], csrf_sepcc_reg_data_rl[54:53], @@ -37908,7 +37908,7 @@ module mkCore(CLK, ~IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[2], IF_csrf_sepcc_reg_read_wget__3508_BIT_34_3520__ETC___d23530[1:0], csrf_sepcc_reg_data_rl[149:86] } ; - assign v__h1013005 = + assign v__h1013009 = { csrf_mepcc_reg_data_rl[152], csrf_mepcc_reg_data_rl[71:56], csrf_mepcc_reg_data_rl[54:53], @@ -37921,41 +37921,41 @@ module mkCore(CLK, ~IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[2], IF_csrf_mepcc_reg_read_wget__3542_BIT_34_3554__ETC___d23564[1:0], csrf_mepcc_reg_data_rl[149:86] } ; - assign v__h514822 = + assign v__h514823 = IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d7227 ? - v__h515017 : + v__h515018 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h515017 = + assign v__h515018 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h516842 = + assign v__h516843 = IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d7321 ? - v__h517222 : + v__h517223 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h517222 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h532561 = + assign v__h517223 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h532562 = IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d7480 ? - v__h532756 : + v__h532757 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h532756 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h535010 = + assign v__h532757 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h535011 = IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d7564 ? - v__h535205 : + v__h535206 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h535205 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h556030 = + assign v__h535206 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h556031 = IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d7769 ? - v__h556225 : + v__h556226 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h556225 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h559809 = + assign v__h556226 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h559810 = IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d7851 ? - v__h560004 : + v__h560005 : coreFix_memExe_forwardQ_enqP ; - assign v__h560004 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h560005 = coreFix_memExe_forwardQ_enqP + 1'd1 ; assign v__h836639 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? v__h836649 : @@ -37966,21 +37966,21 @@ module mkCore(CLK, assign value_BIT_52___h677325 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0 ; - assign value__h239691 = x__h239709 | in__h239801[63:0] ; - assign value__h239855 = - { coreFix_memExe_regToExeQ$first[381:332] & mask__h239862, + assign value__h239693 = x__h239711 | in__h239803[63:0] ; + assign value__h239857 = + { coreFix_memExe_regToExeQ$first[381:332] & mask__h239864, 14'd0 } + - addBase__h239861 ; - assign value__h240848 = x__h240866 | in__h240958[63:0] ; - assign value__h241012 = - { coreFix_memExe_regToExeQ$first[218:169] & mask__h241019, + addBase__h239863 ; + assign value__h240850 = x__h240868 | in__h240960[63:0] ; + assign value__h241014 = + { coreFix_memExe_regToExeQ$first[218:169] & mask__h241021, 14'd0 } + - addBase__h241018 ; - assign value__h254472 = x__h254490 | in__h254582[63:0] ; - assign value__h254636 = - { coreFix_memExe_dTlb$procResp[450:401] & mask__h254643, + addBase__h241020 ; + assign value__h254474 = x__h254492 | in__h254584[63:0] ; + assign value__h254638 = + { coreFix_memExe_dTlb$procResp[450:401] & mask__h254645, 14'd0 } + - addBase__h254642 ; + addBase__h254644 ; assign value__h577074 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -37998,56 +37998,56 @@ module mkCore(CLK, assign value__h719841 = { 1'b0, f1_exp__h714896 != 8'd0, f1_sfd__h714897 } ; assign value__h758694 = { 1'b0, f2_exp__h753890 != 8'd0, f2_sfd__h753891 } ; assign value__h797998 = { 1'b0, f3_exp__h793194 != 8'd0, f3_sfd__h793195 } ; - assign vm_mode_reg__read__h854731 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h915803 = + assign vm_mode_reg__read__h854729 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h915807 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h915859 : + result__h915863 : 12'd4095 ; - assign wordIdx__h263231 = + assign wordIdx__h263233 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164] ; - assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000922 = + assign x1_avValue_new_pcc_capFat_bounds_baseBits__h1000926 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[13:0] : csrf_mtcc_reg[13:0] ; - assign x__h1000027 = address__h999873 >> csrf_stcc_reg[33:28] ; - assign x__h1000253 = csrf_mtcc_reg[33:28] + 6'd14 ; - assign x__h1000380 = address__h1000186 >> csrf_mtcc_reg[33:28] ; - assign x__h1000684 = address__h1000530 >> csrf_mtcc_reg[33:28] ; - assign x__h1000919 = + assign x__h1000031 = address__h999877 >> csrf_stcc_reg[33:28] ; + assign x__h1000257 = csrf_mtcc_reg[33:28] + 6'd14 ; + assign x__h1000384 = address__h1000190 >> csrf_mtcc_reg[33:28] ; + assign x__h1000688 = address__h1000534 >> csrf_mtcc_reg[33:28] ; + assign x__h1000923 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[27:14] : csrf_mtcc_reg[27:14] ; - assign x__h1000940 = + assign x__h1000944 = csrf_prv_reg_read__0286_ULE_1_2614_AND_IF_comm_ETC___d22648 ? csrf_stcc_reg[33:28] : csrf_mtcc_reg[33:28] ; - assign x__h1008435 = + assign x__h1008439 = robdeqPort_0_deq_data_BITS_95_TO_32__q17[63:14] ^ - signBits__h1008405 ; - assign x__h1008531 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; - assign x__h1008934 = + signBits__h1008409 ; + assign x__h1008535 = rob$deqPort_0_deq_data[95:32] >> csrf_stcc_reg[33:28] ; + assign x__h1008938 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1009351 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; - assign x__h1009754 = + assign x__h1009355 = rob$deqPort_0_deq_data[95:32] >> csrf_mtcc_reg[33:28] ; + assign x__h1009758 = rob$deqPort_0_deq_data[95:32] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1010423 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; - assign x__h1012317 = { 1'b0, csrf_spp_reg } ; - assign x__h1016599 = + assign x__h1010427 = rob$deqPort_0_deq_data[95:32] >> csrf_rg_dpc[33:28] ; + assign x__h1012321 = { 1'b0, csrf_spp_reg } ; + assign x__h1016603 = NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? - y_avValue_snd_snd_snd_fst__h1016421 : + y_avValue_snd_snd_snd_fst__h1016425 : IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 ; - assign x__h1031485 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031455 ; - assign x__h1031581 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; - assign x__h1031984 = + assign x__h1031489 = f_csr_reqs$D_OUT[63:14] ^ signBits__h1031459 ; + assign x__h1031585 = f_csr_reqs$D_OUT[63:0] >> csrf_stcc_reg[33:28] ; + assign x__h1031988 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h1032401 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; - assign x__h1032804 = + assign x__h1032405 = f_csr_reqs$D_OUT[63:0] >> csrf_mtcc_reg[33:28] ; + assign x__h1032808 = f_csr_reqs$D_OUT[63:0] >> IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h1033471 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; + assign x__h1033475 = f_csr_reqs$D_OUT[63:0] >> csrf_rg_dpc[33:28] ; assign x__h127302 = coreFix_memExe_respLrScAmoQ_data_0[63:0] >> x__h127340 ; assign x__h127340 = { tmp_expTopHalf__h127293, tmp_expBotHalf__h127295 } ; assign x__h127500 = { impliedTopBits__h127433, topBits__h127429 } ; @@ -38069,113 +38069,113 @@ module mkCore(CLK, coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64] ; assign x__h152124 = { 3'd0, sbIdx__h152015 } ; - assign x__h183397 = + assign x__h183398 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? coreFix_memExe_respLrScAmoQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d1913 } ; - assign x__h183479 = x__h183397[63:0] >> x__h183517 ; - assign x__h183517 = { tmp_expTopHalf__h183470, tmp_expBotHalf__h183472 } ; - assign x__h183677 = { impliedTopBits__h183610, topBits__h183606 } ; - assign x__h183694 = x__h183697[13:12] + carry_out__h183608 ; - assign x__h183697 = - INV_x83397_BITS_108_TO_90__q34[0] ? - { x__h183397[77:67], 3'd0 } : - b_base__h183704 ; - assign x__h199249 = + assign x__h183480 = x__h183398[63:0] >> x__h183518 ; + assign x__h183518 = { tmp_expTopHalf__h183471, tmp_expBotHalf__h183473 } ; + assign x__h183678 = { impliedTopBits__h183611, topBits__h183607 } ; + assign x__h183695 = x__h183698[13:12] + carry_out__h183609 ; + assign x__h183698 = + INV_x83398_BITS_108_TO_90__q34[0] ? + { x__h183398[77:67], 3'd0 } : + b_base__h183705 ; + assign x__h199250 = (coreFix_memExe_lsq$firstLd[125:110] == 16'd65535) ? mmio_dataRespQ_data_0[127:0] : { 64'd0, IF_coreFix_memExe_lsq_firstLd__498_BIT_117_521_ETC___d2079 } ; - assign x__h202230 = x__h199249[63:0] >> x__h202268 ; - assign x__h202268 = { tmp_expTopHalf__h202221, tmp_expBotHalf__h202223 } ; - assign x__h202428 = { impliedTopBits__h202361, topBits__h202357 } ; - assign x__h202445 = x__h202448[13:12] + carry_out__h202359 ; - assign x__h202448 = - INV_x99249_BITS_108_TO_90__q36[0] ? - { x__h199249[77:67], 3'd0 } : - b_base__h202455 ; - assign x__h216796 = coreFix_memExe_lsq$respLd[63:0] >> x__h216834 ; - assign x__h216834 = { tmp_expTopHalf__h216787, tmp_expBotHalf__h216789 } ; - assign x__h216994 = { impliedTopBits__h216927, topBits__h216923 } ; - assign x__h217011 = x__h217014[13:12] + carry_out__h216925 ; - assign x__h217014 = + assign x__h202231 = x__h199250[63:0] >> x__h202269 ; + assign x__h202269 = { tmp_expTopHalf__h202222, tmp_expBotHalf__h202224 } ; + assign x__h202429 = { impliedTopBits__h202362, topBits__h202358 } ; + assign x__h202446 = x__h202449[13:12] + carry_out__h202360 ; + assign x__h202449 = + INV_x99250_BITS_108_TO_90__q36[0] ? + { x__h199250[77:67], 3'd0 } : + b_base__h202456 ; + assign x__h216797 = coreFix_memExe_lsq$respLd[63:0] >> x__h216835 ; + assign x__h216835 = { tmp_expTopHalf__h216788, tmp_expBotHalf__h216790 } ; + assign x__h216995 = { impliedTopBits__h216928, topBits__h216924 } ; + assign x__h217012 = x__h217015[13:12] + carry_out__h216926 ; + assign x__h217015 = INV_coreFix_memExe_lsqrespLd_BITS_108_TO_90__q10[0] ? { coreFix_memExe_lsq$respLd[77:67], 3'd0 } : - b_base__h217021 ; - assign x__h235743 = + b_base__h217022 ; + assign x__h235745 = (coreFix_memExe_dispToRegQ$first[110] && coreFix_memExe_dispToRegQ$first[109:103] != 7'd0) ? IF_sbCons_lazyLookup_3_get_coreFix_memExe_disp_ETC___d3048 : 66'd0 ; - assign x__h239709 = x__h239711 << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239711 = { {48{offset__h239697[15]}}, offset__h239697 } ; - assign x__h239819 = + assign x__h239711 = x__h239713 << coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h239713 = { {48{offset__h239699[15]}}, offset__h239699 } ; + assign x__h239821 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h239967 = + assign x__h239969 = coreFix_memExe_regToExeQ_first__645_BITS_265_T_ETC___d3717 ? - result__h240597 : - ret__h239974 ; - assign x__h240069 = + result__h240599 : + ret__h239976 ; + assign x__h240071 = { coreFix_memExe_regToExeQ$first[225:224], coreFix_memExe_regToExeQ$first[259:246] } ; - assign x__h240138 = + assign x__h240140 = (coreFix_memExe_regToExeQ$first[265:260] == 6'd50) ? coreFix_memExe_regToExeQ$first[245] : coreFix_memExe_regToExeQfirst_BITS_381_TO_332_ETC__q3[49] ; - assign x__h240866 = x__h240868 << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h240868 = { {48{offset__h240854[15]}}, offset__h240854 } ; - assign x__h240976 = + assign x__h240868 = x__h240870 << coreFix_memExe_regToExeQ$first[102:97] ; + assign x__h240870 = { {48{offset__h240856[15]}}, offset__h240856 } ; + assign x__h240978 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_regToExeQ$first[102:97] ; - assign x__h241124 = + assign x__h241126 = coreFix_memExe_regToExeQ_first__645_BITS_102_T_ETC___d3779 ? - result__h241754 : - ret__h241131 ; - assign x__h241226 = + result__h241756 : + ret__h241133 ; + assign x__h241228 = { coreFix_memExe_regToExeQ$first[62:61], coreFix_memExe_regToExeQ$first[96:83] } ; - assign x__h241295 = + assign x__h241297 = (coreFix_memExe_regToExeQ$first[102:97] == 6'd50) ? coreFix_memExe_regToExeQ$first[82] : - coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q5[49] ; - assign x__h242671 = offset__h242625[63:14] ^ signBits__h242641 ; - assign x__h242774 = - offset__h242625 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h244675 = { pointer__h242635[3:0], 3'b0 } ; - assign x__h248117 = - pointer__h242635 >> coreFix_memExe_regToExeQ$first[265:260] ; - assign x__h249475 = x__h249487 + y__h249488 ; - assign x__h249487 = x__h249499 + y__h249500 ; - assign x__h249499 = x__h249511 + y__h249512 ; - assign x__h249511 = x__h249523 + y__h249524 ; - assign x__h249523 = x__h249535 + y__h249536 ; - assign x__h249535 = x__h249547 + y__h249548 ; - assign x__h249547 = x__h249559 + y__h249560 ; - assign x__h249559 = x__h249571 + y__h249572 ; - assign x__h249571 = x__h249583 + y__h249584 ; - assign x__h249583 = x__h249595 + y__h249596 ; - assign x__h249595 = x__h249607 + y__h249608 ; - assign x__h249607 = x__h249619 + y__h249620 ; - assign x__h249619 = x__h249631 + y__h249632 ; - assign x__h249631 = x__h249643 + y__h249644 ; - assign x__h249643 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; - assign x__h254490 = x__h254492 << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254492 = { {48{offset__h254478[15]}}, offset__h254478 } ; - assign x__h254600 = + coreFix_memExe_regToExeQfirst_BITS_218_TO_169_ETC__q7[49] ; + assign x__h242673 = offset__h242627[63:14] ^ signBits__h242643 ; + assign x__h242776 = + offset__h242627 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h244677 = { pointer__h242637[3:0], 3'b0 } ; + assign x__h248119 = + pointer__h242637 >> coreFix_memExe_regToExeQ$first[265:260] ; + assign x__h249477 = x__h249489 + y__h249490 ; + assign x__h249489 = x__h249501 + y__h249502 ; + assign x__h249501 = x__h249513 + y__h249514 ; + assign x__h249513 = x__h249525 + y__h249526 ; + assign x__h249525 = x__h249537 + y__h249538 ; + assign x__h249537 = x__h249549 + y__h249550 ; + assign x__h249549 = x__h249561 + y__h249562 ; + assign x__h249561 = x__h249573 + y__h249574 ; + assign x__h249573 = x__h249585 + y__h249586 ; + assign x__h249585 = x__h249597 + y__h249598 ; + assign x__h249597 = x__h249609 + y__h249610 ; + assign x__h249609 = x__h249621 + y__h249622 ; + assign x__h249621 = x__h249633 + y__h249634 ; + assign x__h249633 = x__h249645 + y__h249646 ; + assign x__h249645 = { 4'd0, coreFix_memExe_lsq$getOrigBE[15] } ; + assign x__h254492 = x__h254494 << coreFix_memExe_dTlb$procResp[334:329] ; + assign x__h254494 = { {48{offset__h254480[15]}}, offset__h254480 } ; + assign x__h254602 = 66'h3FFFFFFFFFFFFFFFF << coreFix_memExe_dTlb$procResp[334:329] ; - assign x__h254748 = + assign x__h254750 = coreFix_memExe_dTlb_procResp__257_BITS_334_TO__ETC___d4420 ? - result__h255378 : - ret__h254755 ; - assign x__h254850 = + result__h255380 : + ret__h254757 ; + assign x__h254852 = { coreFix_memExe_dTlb$procResp[294:293], coreFix_memExe_dTlb$procResp[328:315] } ; - assign x__h254919 = + assign x__h254921 = (coreFix_memExe_dTlb$procResp[334:329] == 6'd50) ? coreFix_memExe_dTlb$procResp[314] : - coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q7[49] ; - assign x__h521673 = + coreFix_memExe_dTlbprocResp_BITS_450_TO_401_P_ETC__q5[49] ; + assign x__h521674 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; @@ -38238,42 +38238,42 @@ module mkCore(CLK, 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d13515 ; assign x__h836140 = a__h835704[63] ^ b__h835705[63] ; - assign x__h853091 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h854171 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; - assign x__h854232 = - x__h854234 << + assign x__h853089 = { csrf_frm_reg, csrf_fflags_reg } ; + assign x__h854169 = 66'h3FFFFFFFFFFFFFFFF << csrf_stcc_reg[33:28] ; + assign x__h854230 = + x__h854232 << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h854234 = { {48{offset__h854220[15]}}, offset__h854220 } ; - assign x__h854476 = + assign x__h854232 = { {48{offset__h854218[15]}}, offset__h854218 } ; + assign x__h854474 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16100 ; - assign x__h855164 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; - assign x__h855225 = - x__h855227 << + assign x__h855162 = 66'h3FFFFFFFFFFFFFFFF << csrf_mtcc_reg[33:28] ; + assign x__h855223 = + x__h855225 << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855227 = { {48{offset__h855213[15]}}, offset__h855213 } ; - assign x__h855468 = + assign x__h855225 = { {48{offset__h855211[15]}}, offset__h855211 } ; + assign x__h855466 = 66'h3FFFFFFFFFFFFFFFF << IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16252 ; - assign x__h855994 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; - assign x__h866847 = - coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866885 ; - assign x__h866885 = { tmp_expTopHalf__h866837, tmp_expBotHalf__h866839 } ; - assign x__h867058 = { impliedTopBits__h866990, topBits__h866986 } ; - assign x__h867075 = x__h867078[13:12] + carry_out__h866988 ; - assign x__h867078 = + assign x__h855992 = 66'h3FFFFFFFFFFFFFFFF << csrf_rg_dpc[33:28] ; + assign x__h866845 = + coreFix_aluExe_1_regToExeQ$first[241:178] >> x__h866883 ; + assign x__h866883 = { tmp_expTopHalf__h866835, tmp_expBotHalf__h866837 } ; + assign x__h867056 = { impliedTopBits__h866988, topBits__h866984 } ; + assign x__h867073 = x__h867076[13:12] + carry_out__h866986 ; + assign x__h867076 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_286__ETC__q11[0] ? { coreFix_aluExe_1_regToExeQ$first[255:245], 3'd0 } : - b_base__h867085 ; - assign x__h867395 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867433 ; - assign x__h867433 = { tmp_expTopHalf__h867385, tmp_expBotHalf__h867387 } ; - assign x__h867606 = { impliedTopBits__h867538, topBits__h867534 } ; - assign x__h867623 = x__h867626[13:12] + carry_out__h867536 ; - assign x__h867626 = + b_base__h867083 ; + assign x__h867393 = coreFix_aluExe_1_regToExeQ$first[112:49] >> x__h867431 ; + assign x__h867431 = { tmp_expTopHalf__h867383, tmp_expBotHalf__h867385 } ; + assign x__h867604 = { impliedTopBits__h867536, topBits__h867532 } ; + assign x__h867621 = x__h867624[13:12] + carry_out__h867534 ; + assign x__h867624 = INV_coreFix_aluExe_1_regToExeQfirst_BITS_157__ETC__q12[0] ? { coreFix_aluExe_1_regToExeQ$first[126:116], 3'd0 } : - b_base__h867633 ; - assign x__h879902 = + b_base__h867631 ; + assign x__h879901 = { coreFix_aluExe_1_exeToFinQ$first[623], coreFix_aluExe_1_exeToFinQ$first[542:527], coreFix_aluExe_1_exeToFinQ$first[525:524], @@ -38285,34 +38285,34 @@ module mkCore(CLK, ~IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[2], IF_coreFix_aluExe_1_exeToFinQ_first__7830_BIT__ETC___d18027[1:0], coreFix_aluExe_1_exeToFinQ$first[620:557] } ; - assign x__h895986 = x__h895988 << csrf_stcc_reg[33:28] ; - assign x__h895988 = { {48{offset__h895974[15]}}, offset__h895974 } ; - assign x__h896270 = x__h896272 << csrf_mtcc_reg[33:28] ; - assign x__h896272 = { {48{offset__h896258[15]}}, offset__h896258 } ; - assign x__h896540 = + assign x__h895989 = x__h895991 << csrf_stcc_reg[33:28] ; + assign x__h895991 = { {48{offset__h895977[15]}}, offset__h895977 } ; + assign x__h896273 = x__h896275 << csrf_mtcc_reg[33:28] ; + assign x__h896275 = { {48{offset__h896261[15]}}, offset__h896261 } ; + assign x__h896543 = { csrf_mccsr_reg[10:5], CASE_csrf_mccsr_reg_BITS_4_TO_0_0_csrf_mccsr_r_ETC__q24, 5'd3 } ; - assign x__h896615 = x__h896617 << csrf_rg_dpc[33:28] ; - assign x__h896617 = { {48{offset__h896603[15]}}, offset__h896603 } ; - assign x__h906532 = - coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906570 ; - assign x__h906570 = { tmp_expTopHalf__h906522, tmp_expBotHalf__h906524 } ; - assign x__h906743 = { impliedTopBits__h906675, topBits__h906671 } ; - assign x__h906760 = x__h906763[13:12] + carry_out__h906673 ; - assign x__h906763 = + assign x__h896618 = x__h896620 << csrf_rg_dpc[33:28] ; + assign x__h896620 = { {48{offset__h896606[15]}}, offset__h896606 } ; + assign x__h906535 = + coreFix_aluExe_0_regToExeQ$first[241:178] >> x__h906573 ; + assign x__h906573 = { tmp_expTopHalf__h906525, tmp_expBotHalf__h906527 } ; + assign x__h906746 = { impliedTopBits__h906678, topBits__h906674 } ; + assign x__h906763 = x__h906766[13:12] + carry_out__h906676 ; + assign x__h906766 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_286__ETC__q13[0] ? { coreFix_aluExe_0_regToExeQ$first[255:245], 3'd0 } : - b_base__h906770 ; - assign x__h907080 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907118 ; - assign x__h907118 = { tmp_expTopHalf__h907070, tmp_expBotHalf__h907072 } ; - assign x__h907291 = { impliedTopBits__h907223, topBits__h907219 } ; - assign x__h907308 = x__h907311[13:12] + carry_out__h907221 ; - assign x__h907311 = + b_base__h906773 ; + assign x__h907083 = coreFix_aluExe_0_regToExeQ$first[112:49] >> x__h907121 ; + assign x__h907121 = { tmp_expTopHalf__h907073, tmp_expBotHalf__h907075 } ; + assign x__h907294 = { impliedTopBits__h907226, topBits__h907222 } ; + assign x__h907311 = x__h907314[13:12] + carry_out__h907224 ; + assign x__h907314 = INV_coreFix_aluExe_0_regToExeQfirst_BITS_157__ETC__q14[0] ? { coreFix_aluExe_0_regToExeQ$first[126:116], 3'd0 } : - b_base__h907318 ; - assign x__h914618 = + b_base__h907321 ; + assign x__h914622 = { coreFix_aluExe_0_exeToFinQ$first[623], coreFix_aluExe_0_exeToFinQ$first[542:527], coreFix_aluExe_0_exeToFinQ$first[525:524], @@ -38324,29 +38324,29 @@ module mkCore(CLK, ~IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[2], IF_coreFix_aluExe_0_exeToFinQ_first__9946_BIT__ETC___d20142[1:0], coreFix_aluExe_0_exeToFinQ$first[620:557] } ; - assign x__h915807 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h915858 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h994909 = commitStage_commitTrap[172:109] >> x__h994947 ; - assign x__h994947 = { tmp_expTopHalf__h994900, tmp_expBotHalf__h994902 } ; - assign x__h995107 = { impliedTopBits__h995040, topBits__h995036 } ; - assign x__h995124 = x__h995127[13:12] + carry_out__h995038 ; - assign x__h995127 = + assign x__h915811 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h915862 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h994913 = commitStage_commitTrap[172:109] >> x__h994951 ; + assign x__h994951 = { tmp_expTopHalf__h994904, tmp_expBotHalf__h994906 } ; + assign x__h995111 = { impliedTopBits__h995044, topBits__h995040 } ; + assign x__h995128 = x__h995131[13:12] + carry_out__h995042 ; + assign x__h995131 = INV_commitStage_commitTrap_BITS_217_TO_199__q16[0] ? { commitStage_commitTrap[186:176], 3'd0 } : - b_base__h995134 ; - assign x__h997622 = - x__h997624 << + b_base__h995138 ; + assign x__h997626 = + x__h997628 << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h997624 = { {48{offset__h997610[15]}}, offset__h997610 } ; - assign x__h997709 = + assign x__h997628 = { {48{offset__h997614[15]}}, offset__h997614 } ; + assign x__h997713 = 66'h3FFFFFFFFFFFFFFFF << IF_INV_commitStage_commitTrap_2268_BITS_217_TO_ETC___d22580 ; - assign x__h998896 = + assign x__h998900 = { commitStage_commitTrap[42:37], CASE_commitStage_commitTrap_BITS_36_TO_32_0_co_ETC__q25 } ; - assign x__h999596 = csrf_stcc_reg[33:28] + 6'd14 ; - assign x__h999622 = { cause_code__h995318, 2'b0 } ; - assign x__h999723 = address__h999529 >> csrf_stcc_reg[33:28] ; + assign x__h999600 = csrf_stcc_reg[33:28] + 6'd14 ; + assign x__h999626 = { cause_code__h995322, 2'b0 } ; + assign x__h999727 = address__h999533 >> csrf_stcc_reg[33:28] ; assign x_addr__h19883 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[214:151] : @@ -38355,7 +38355,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[214:151] : mmio_cRqQ_enqReq_rl[214:151] ; - assign x_addr__h535372 = + assign x_addr__h535373 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[582:519] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[582:519] ; @@ -38363,7 +38363,7 @@ module mkCore(CLK, EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_decodeInfo_frm__h926246 = csrf_frm_reg ; + assign x_decodeInfo_frm__h926250 = csrf_frm_reg ; assign x_quotient__h705745 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : @@ -38371,7 +38371,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? q___1__h706456 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h849323 = { 63'd0, csrf_stats_module_doStats } ; + assign x_reg_ifc__read__h849321 = { 63'd0, csrf_stats_module_doStats } ; assign x_remainder__h705746 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : @@ -38379,39 +38379,39 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? r___1__h706482 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h1000309 = { mask__h1000192[62:0], 1'd0 } ; - assign y__h1016374 = + assign y__h1000313 = { mask__h1000196[62:0], 1'd0 } ; + assign y__h1016378 = NOT_rob_deqPort_0_canDeq__3600_3601_OR_rob_deq_ETC___d23820 ? - y_avValue_snd_snd_snd_snd_snd__h1016427 : + y_avValue_snd_snd_snd_snd_snd__h1016431 : IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 ; - assign y__h239818 = ~x__h239819 ; - assign y__h240975 = ~x__h240976 ; - assign y__h249476 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; - assign y__h249488 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; - assign y__h249500 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; - assign y__h249512 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; - assign y__h249524 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; - assign y__h249536 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; - assign y__h249548 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; - assign y__h249560 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; - assign y__h249572 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; - assign y__h249584 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; - assign y__h249596 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; - assign y__h249608 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; - assign y__h249620 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; - assign y__h249632 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; - assign y__h249644 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; - assign y__h254599 = ~x__h254600 ; - assign y__h422564 = + assign y__h239820 = ~x__h239821 ; + assign y__h240977 = ~x__h240978 ; + assign y__h249478 = { 4'd0, coreFix_memExe_lsq$getOrigBE[0] } ; + assign y__h249490 = { 4'd0, coreFix_memExe_lsq$getOrigBE[1] } ; + assign y__h249502 = { 4'd0, coreFix_memExe_lsq$getOrigBE[2] } ; + assign y__h249514 = { 4'd0, coreFix_memExe_lsq$getOrigBE[3] } ; + assign y__h249526 = { 4'd0, coreFix_memExe_lsq$getOrigBE[4] } ; + assign y__h249538 = { 4'd0, coreFix_memExe_lsq$getOrigBE[5] } ; + assign y__h249550 = { 4'd0, coreFix_memExe_lsq$getOrigBE[6] } ; + assign y__h249562 = { 4'd0, coreFix_memExe_lsq$getOrigBE[7] } ; + assign y__h249574 = { 4'd0, coreFix_memExe_lsq$getOrigBE[8] } ; + assign y__h249586 = { 4'd0, coreFix_memExe_lsq$getOrigBE[9] } ; + assign y__h249598 = { 4'd0, coreFix_memExe_lsq$getOrigBE[10] } ; + assign y__h249610 = { 4'd0, coreFix_memExe_lsq$getOrigBE[11] } ; + assign y__h249622 = { 4'd0, coreFix_memExe_lsq$getOrigBE[12] } ; + assign y__h249634 = { 4'd0, coreFix_memExe_lsq$getOrigBE[13] } ; + assign y__h249646 = { 4'd0, coreFix_memExe_lsq$getOrigBE[14] } ; + assign y__h254601 = ~x__h254602 ; + assign y__h422565 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:522], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[169:164] } ; - assign y__h854170 = ~x__h854171 ; - assign y__h854475 = ~x__h854476 ; - assign y__h855163 = ~x__h855164 ; - assign y__h855467 = ~x__h855468 ; - assign y__h855993 = ~x__h855994 ; - assign y__h915837 = ~x__h915807 ; - assign y__h920767 = + assign y__h854168 = ~x__h854169 ; + assign y__h854473 = ~x__h854474 ; + assign y__h855161 = ~x__h855162 ; + assign y__h855465 = ~x__h855466 ; + assign y__h855991 = ~x__h855992 ; + assign y__h915841 = ~x__h915811 ; + assign y__h920771 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -38420,9 +38420,9 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h973803 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h997708 = ~x__h997709 ; - assign y__h999652 = { mask__h999535[62:0], 1'd0 } ; + assign y__h973807 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h997712 = ~x__h997713 ; + assign y__h999656 = { mask__h999539[62:0], 1'd0 } ; assign y_avValue__h710472 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12381 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : @@ -38435,7 +38435,7 @@ module mkCore(CLK, NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d12432 ? coreFix_fpuMulDivExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d12510 ; - assign y_avValue_snd_fst__h1015829 = + assign y_avValue_snd_fst__h1015833 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38450,7 +38450,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_snd_fst__h1016411 = + assign y_avValue_snd_fst__h1016415 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38464,25 +38464,25 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 : - y_avValue_snd_fst__h1016440 ; - assign y_avValue_snd_fst__h1016440 = + y_avValue_snd_fst__h1016444 ; + assign y_avValue_snd_fst__h1016444 = IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23827 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_snd_fst__h963383 = + assign y_avValue_snd_fst__h963387 = ((fetchStage$pipelines_0_first[268:266] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__1151_AND__ETC___d21180) ? - y_avValue_snd_fst__h963425 : + y_avValue_snd_fst__h963429 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963425 = + assign y_avValue_snd_fst__h963429 = IF_fetchStage_pipelines_0_first__0256_BITS_268_ETC___d21222 ? - y_avValue_snd_fst__h963467 : + y_avValue_snd_fst__h963471 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h963467 = + assign y_avValue_snd_fst__h963471 = (fetchStage$pipelines_0_first[268:266] == 3'd1) ? - spec_bits__h973790 : + spec_bits__h973794 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h1015839 = + assign y_avValue_snd_snd_snd_fst__h1015843 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38497,7 +38497,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h1016421 = + assign y_avValue_snd_snd_snd_fst__h1016425 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38511,11 +38511,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 : - y_avValue_snd_snd_snd_fst__h1016450 ; - assign y_avValue_snd_snd_snd_fst__h1016450 = + y_avValue_snd_snd_snd_fst__h1016454 ; + assign y_avValue_snd_snd_snd_fst__h1016454 = IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23849 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1015845 = + assign y_avValue_snd_snd_snd_snd_snd__h1015849 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[274] || rob$deqPort_0_deq_data[469:465] == 5'd0 || @@ -38530,7 +38530,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[469:465] == 5'd25) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016427 = + assign y_avValue_snd_snd_snd_snd_snd__h1016431 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[274] || rob$deqPort_1_deq_data[469:465] == 5'd0 || @@ -38544,8 +38544,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[469:465] == 5'd24 || rob$deqPort_1_deq_data[469:465] == 5'd25) ? IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 : - y_avValue_snd_snd_snd_snd_snd__h1016456 ; - assign y_avValue_snd_snd_snd_snd_snd__h1016456 = + y_avValue_snd_snd_snd_snd_snd__h1016460 ; + assign y_avValue_snd_snd_snd_snd_snd__h1016460 = IF_rob_deqPort_0_canDeq__3600_THEN_IF_NOT_rob__ETC___d23721 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -38559,6 +38559,19 @@ module mkCore(CLK, { 2'd3, mmio_cRqQ_data_0[148:145] }; endcase end + always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) + begin + case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) + 1'd0: + addr__h505615 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; + 1'd1: + addr__h505615 = + coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; + endcase + end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or @@ -38571,59 +38584,46 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h501096 = + x__h501097 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end - always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1) - begin - case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) - 1'd0: - addr__h505614 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[585:522]; - 1'd1: - addr__h505614 = - coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[585:522]; - endcase - end always@(coreFix_memExe_memRespLdQ_deqP or coreFix_memExe_memRespLdQ_data_0 or coreFix_memExe_memRespLdQ_data_1) begin case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: t__h212839 = coreFix_memExe_memRespLdQ_data_0[133:129]; - 1'd1: t__h212839 = coreFix_memExe_memRespLdQ_data_1[133:129]; + 1'd0: t__h212840 = coreFix_memExe_memRespLdQ_data_0[133:129]; + 1'd1: t__h212840 = coreFix_memExe_memRespLdQ_data_1[133:129]; endcase end always@(coreFix_memExe_forwardQ_deqP or coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) begin case (coreFix_memExe_forwardQ_deqP) - 1'd0: t__h215125 = coreFix_memExe_forwardQ_data_0[133:129]; - 1'd1: t__h215125 = coreFix_memExe_forwardQ_data_1[133:129]; + 1'd0: t__h215126 = coreFix_memExe_forwardQ_data_0[133:129]; + 1'd1: t__h215126 = coreFix_memExe_forwardQ_data_1[133:129]; endcase end always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or @@ -38682,16 +38682,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[167:166]) 2'd0: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q18; 2'd1: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q19; 2'd2: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q20; 2'd3: - x__h264730 = + x__h264732 = CASE_coreFix_memExe_dMem_cache_m_banks_0_proce_ETC__q21; endcase end @@ -38699,8 +38699,8 @@ module mkCore(CLK, begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h995534 = commitStage_commitTrap[35:32]; - default: i__h995534 = 4'd15; + i__h995538 = commitStage_commitTrap[35:32]; + default: i__h995538 = 4'd15; endcase end always@(csrf_mccsr_reg) @@ -38773,9 +38773,9 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h508764 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h508765 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or @@ -39041,16 +39041,16 @@ module mkCore(CLK, 5'd12, 5'd13, 5'd15: - i__h995334 = commitStage_commitTrap[36:32]; - default: i__h995334 = 5'd28; + i__h995338 = commitStage_commitTrap[36:32]; + default: i__h995338 = 5'd28; endcase end - always@(commitStage_commitTrap or cause_code__h996893 or i__h995334) + always@(commitStage_commitTrap or cause_code__h996897 or i__h995338) begin case (commitStage_commitTrap[44:43]) - 2'd0: cause_code__h995318 = 5'd28; - 2'd1: cause_code__h995318 = i__h995334; - default: cause_code__h995318 = cause_code__h996893; + 2'd0: cause_code__h995322 = 5'd28; + 2'd1: cause_code__h995322 = i__h995338; + default: cause_code__h995322 = cause_code__h996897; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -39340,16 +39340,16 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[165:164]) 2'd0: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[31:0]; 2'd1: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4867[63:32]; 2'd2: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[31:0]; 2'd3: - x__h264885 = + x__h264887 = SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_pi_ETC___d4861[63:32]; endcase end @@ -43864,10 +43864,10 @@ module mkCore(CLK, 4'd14; endcase end - always@(k__h945028 or + always@(k__h945032 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945028) + case (k__h945032) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__119_ETC___d21202 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -43887,10 +43887,10 @@ module mkCore(CLK, coreFix_memExe_lsq$enqStTag[6]; endcase end - always@(k__h945028 or + always@(k__h945032 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h945028) + case (k__h945032) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__1191_co_ETC___d21225 = coreFix_aluExe_0_rsAlu$canEnq; @@ -44107,7 +44107,7 @@ module mkCore(CLK, 11'd1194; endcase end - always@(idx__h968878 or + always@(idx__h968882 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21652 or coreFix_aluExe_0_rsAlu$canEnq or @@ -44117,7 +44117,7 @@ module mkCore(CLK, fetchStage_pipelines_0_first__0256_BITS_268_TO_ETC___d21657 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968878) + case (idx__h968882) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__0254_AN_ETC___d21680 = fetchStage$pipelines_0_canDeq && @@ -44221,15 +44221,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__1286_AND__ETC___d21642; endcase end - always@(k__h945028 or + always@(k__h945032 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h945028) + case (k__h945032) 1'd0: - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k45028_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = + CASE_k45032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q268 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -44265,7 +44265,7 @@ module mkCore(CLK, regRenamingTable_RDY_rename_0_getRename__1028__ETC___d21854; endcase end - always@(idx__h968878 or + always@(idx__h968882 or fetchStage$pipelines_0_canDeq or fetchStage$pipelines_0_first or specTagManager$canClaim or @@ -44275,7 +44275,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_first__0256_BITS_26_ETC___d21911 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h968878) + case (idx__h968882) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__025_ETC___d21916 = (!fetchStage$pipelines_0_canDeq || @@ -44697,87 +44697,6 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[513]; endcase end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = - coreFix_memExe_memRespLdQ_data_1[127:64]; - endcase - end - always@(coreFix_memExe_memRespLdQ_deqP or - coreFix_memExe_memRespLdQ_data_0 or - coreFix_memExe_memRespLdQ_data_1) - begin - case (coreFix_memExe_memRespLdQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = - coreFix_memExe_memRespLdQ_data_1[63:0]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_0[127:64]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = - coreFix_memExe_forwardQ_data_1[127:64]; - endcase - end - always@(coreFix_memExe_forwardQ_deqP or - coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) - begin - case (coreFix_memExe_forwardQ_deqP) - 1'd0: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_0[63:0]; - 1'd1: - SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = - coreFix_memExe_forwardQ_data_1[63:0]; - endcase - end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first) - begin - case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) - 3'd0: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = - coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; - 3'd1: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd4; - 3'd2: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd3; - 3'd3: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd2; - 3'd4: - IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd1; - default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = - 3'd0; - endcase - end - always@(commitStage_commitTrap or - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678) - begin - case (commitStage_commitTrap[36:32]) - 5'd0, 5'd3: - trap_val__h996922 = - SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678; - 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: - trap_val__h996922 = commitStage_commitTrap[108:45]; - 5'd2: trap_val__h996922 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h996922 = 64'd0; - endcase - end always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or coreFix_memExe_stb$deq or @@ -45004,6 +44923,87 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:0]; endcase end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2147 = + coreFix_memExe_memRespLdQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_memRespLdQ_deqP or + coreFix_memExe_memRespLdQ_data_0 or + coreFix_memExe_memRespLdQ_data_1) + begin + case (coreFix_memExe_memRespLdQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_memRespLdQ_data_0_133_B_ETC___d2151 = + coreFix_memExe_memRespLdQ_data_1[63:0]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_0[127:64]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2230 = + coreFix_memExe_forwardQ_data_1[127:64]; + endcase + end + always@(coreFix_memExe_forwardQ_deqP or + coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1) + begin + case (coreFix_memExe_forwardQ_deqP) + 1'd0: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_0[63:0]; + 1'd1: + SEL_ARR_coreFix_memExe_forwardQ_data_0_216_BIT_ETC___d2234 = + coreFix_memExe_forwardQ_data_1[63:0]; + endcase + end + always@(commitStage_commitTrap or + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678) + begin + case (commitStage_commitTrap[36:32]) + 5'd0, 5'd3: + trap_val__h996926 = + SEXT__0_CONCAT_IF_INV_commitStage_commitTrap_2_ETC___d22678; + 5'd1, 5'd4, 5'd5, 5'd6, 5'd7, 5'd12, 5'd13, 5'd15: + trap_val__h996926 = commitStage_commitTrap[108:45]; + 5'd2: trap_val__h996926 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h996926 = 64'd0; + endcase + end + always@(coreFix_fpuMulDivExe_0_regToExeQ$first) + begin + case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) + 3'd0: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = + coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]; + 3'd1: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd4; + 3'd2: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd3; + 3'd3: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd2; + 3'd4: + IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = 3'd1; + default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__252_ETC___d14868 = + 3'd0; + endcase + end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) @@ -45913,17 +45913,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h858473 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h858473 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h858473 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h858473 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h858471 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h858471 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h858471 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h858471 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h858473 = + thin_addrBits__h858471 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h858473 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h858473 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h858473 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h858473 = + 5'd28: thin_addrBits__h858471 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h858471 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h858471 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h858471 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45937,17 +45937,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_addrBits__h899108 = csrf_ddc_reg[85:72]; - 5'd12: thin_addrBits__h899108 = csrf_stcc_reg[85:72]; - 5'd13: thin_addrBits__h899108 = csrf_stdc_reg[85:72]; - 5'd14: thin_addrBits__h899108 = csrf_sScratchC_reg[85:72]; + 5'd1: thin_addrBits__h899111 = csrf_ddc_reg[85:72]; + 5'd12: thin_addrBits__h899111 = csrf_stcc_reg[85:72]; + 5'd13: thin_addrBits__h899111 = csrf_stdc_reg[85:72]; + 5'd14: thin_addrBits__h899111 = csrf_sScratchC_reg[85:72]; 5'd15: - thin_addrBits__h899108 = + thin_addrBits__h899111 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16080; - 5'd28: thin_addrBits__h899108 = csrf_mtcc_reg[85:72]; - 5'd29: thin_addrBits__h899108 = csrf_mtdc_reg[85:72]; - 5'd30: thin_addrBits__h899108 = csrf_mScratchC_reg[85:72]; - default: thin_addrBits__h899108 = + 5'd28: thin_addrBits__h899111 = csrf_mtcc_reg[85:72]; + 5'd29: thin_addrBits__h899111 = csrf_mtdc_reg[85:72]; + 5'd30: thin_addrBits__h899111 = csrf_mScratchC_reg[85:72]; + default: thin_addrBits__h899111 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16232; endcase end @@ -45961,17 +45961,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h860421 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h860421 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h860421 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h860421 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h860419 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h860419 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h860419 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h860419 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h860421 = + thin_bounds_baseBits__h860419 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h860421 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h860421 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h860421 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h860421 = + 5'd28: thin_bounds_baseBits__h860419 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h860419 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h860419 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h860419 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -45985,17 +45985,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_baseBits__h900514 = csrf_ddc_reg[13:0]; - 5'd12: thin_bounds_baseBits__h900514 = csrf_stcc_reg[13:0]; - 5'd13: thin_bounds_baseBits__h900514 = csrf_stdc_reg[13:0]; - 5'd14: thin_bounds_baseBits__h900514 = csrf_sScratchC_reg[13:0]; + 5'd1: thin_bounds_baseBits__h900517 = csrf_ddc_reg[13:0]; + 5'd12: thin_bounds_baseBits__h900517 = csrf_stcc_reg[13:0]; + 5'd13: thin_bounds_baseBits__h900517 = csrf_stdc_reg[13:0]; + 5'd14: thin_bounds_baseBits__h900517 = csrf_sScratchC_reg[13:0]; 5'd15: - thin_bounds_baseBits__h900514 = + thin_bounds_baseBits__h900517 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16084; - 5'd28: thin_bounds_baseBits__h900514 = csrf_mtcc_reg[13:0]; - 5'd29: thin_bounds_baseBits__h900514 = csrf_mtdc_reg[13:0]; - 5'd30: thin_bounds_baseBits__h900514 = csrf_mScratchC_reg[13:0]; - default: thin_bounds_baseBits__h900514 = + 5'd28: thin_bounds_baseBits__h900517 = csrf_mtcc_reg[13:0]; + 5'd29: thin_bounds_baseBits__h900517 = csrf_mtdc_reg[13:0]; + 5'd30: thin_bounds_baseBits__h900517 = csrf_mScratchC_reg[13:0]; + default: thin_bounds_baseBits__h900517 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16236; endcase end @@ -46009,17 +46009,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_address__h858472 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h858472 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h858472 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h858472 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h858470 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h858470 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h858470 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h858470 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h858472 = + thin_address__h858470 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h858472 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h858472 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h858472 = csrf_mScratchC_reg[151:86]; - default: thin_address__h858472 = + 5'd28: thin_address__h858470 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h858470 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h858470 = csrf_mScratchC_reg[151:86]; + default: thin_address__h858470 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end @@ -46033,289 +46033,289 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_address__h899107 = csrf_ddc_reg[151:86]; - 5'd12: thin_address__h899107 = csrf_stcc_reg[151:86]; - 5'd13: thin_address__h899107 = csrf_stdc_reg[151:86]; - 5'd14: thin_address__h899107 = csrf_sScratchC_reg[151:86]; + 5'd1: thin_address__h899110 = csrf_ddc_reg[151:86]; + 5'd12: thin_address__h899110 = csrf_stcc_reg[151:86]; + 5'd13: thin_address__h899110 = csrf_stdc_reg[151:86]; + 5'd14: thin_address__h899110 = csrf_sScratchC_reg[151:86]; 5'd15: - thin_address__h899107 = + thin_address__h899110 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16104; - 5'd28: thin_address__h899107 = csrf_mtcc_reg[151:86]; - 5'd29: thin_address__h899107 = csrf_mtdc_reg[151:86]; - 5'd30: thin_address__h899107 = csrf_mScratchC_reg[151:86]; - default: thin_address__h899107 = + 5'd28: thin_address__h899110 = csrf_mtcc_reg[151:86]; + 5'd29: thin_address__h899110 = csrf_mtdc_reg[151:86]; + 5'd30: thin_address__h899110 = csrf_mScratchC_reg[151:86]; + default: thin_address__h899110 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16256; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h849193 or - frm_csr__read__h849204 or - fcsr_csr__read__h849218 or - sstatus_csr__read__h849414 or - sie_csr__read__h849484 or + fflags_csr__read__h849191 or + frm_csr__read__h849202 or + fcsr_csr__read__h849216 or + sstatus_csr__read__h849412 or + sie_csr__read__h849482 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849572 or + scounteren_csr__read__h849570 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849712 or + scause_csr__read__h849710 or csrf_stval_csr or - sip_csr__read__h849852 or - satp_csr__read__h849915 or - mstatus_csr__read__h850061 or - medeleg_csr__read__h850222 or - mideleg_csr__read__h850320 or - mie_csr__read__h850447 or + sip_csr__read__h849850 or + satp_csr__read__h849913 or + mstatus_csr__read__h850059 or + medeleg_csr__read__h850220 or + mideleg_csr__read__h850318 or + mie_csr__read__h850445 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850619 or + mcounteren_csr__read__h850617 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850885 or + mcause_csr__read__h850883 or csrf_mtval_csr or - mip_csr__read__h851124 or + mip_csr__read__h851122 or csrf_rg_tselect or - rg_tdata1__read__h852225 or + rg_tdata1__read__h852223 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849323 or + x_reg_ifc__read__h849321 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896543 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h1020024 = fflags_csr__read__h849193; - 12'd2: data_out__h1020024 = frm_csr__read__h849204; - 12'd3: data_out__h1020024 = fcsr_csr__read__h849218; - 12'd256: data_out__h1020024 = sstatus_csr__read__h849414; - 12'd260: data_out__h1020024 = sie_csr__read__h849484; + 12'd1: data_out__h1020028 = fflags_csr__read__h849191; + 12'd2: data_out__h1020028 = frm_csr__read__h849202; + 12'd3: data_out__h1020028 = fcsr_csr__read__h849216; + 12'd256: data_out__h1020028 = sstatus_csr__read__h849412; + 12'd260: data_out__h1020028 = sie_csr__read__h849482; 12'd261: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: data_out__h1020024 = scounteren_csr__read__h849572; - 12'd320: data_out__h1020024 = csrf_sscratch_csr; + 12'd262: data_out__h1020028 = scounteren_csr__read__h849570; + 12'd320: data_out__h1020028 = csrf_sscratch_csr; 12'd321: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: data_out__h1020024 = scause_csr__read__h849712; - 12'd323: data_out__h1020024 = csrf_stval_csr; - 12'd324: data_out__h1020024 = sip_csr__read__h849852; - 12'd384: data_out__h1020024 = satp_csr__read__h849915; - 12'd768: data_out__h1020024 = mstatus_csr__read__h850061; - 12'd769: data_out__h1020024 = 64'h800000000014112D; - 12'd770: data_out__h1020024 = medeleg_csr__read__h850222; - 12'd771: data_out__h1020024 = mideleg_csr__read__h850320; - 12'd772: data_out__h1020024 = mie_csr__read__h850447; + 12'd322: data_out__h1020028 = scause_csr__read__h849710; + 12'd323: data_out__h1020028 = csrf_stval_csr; + 12'd324: data_out__h1020028 = sip_csr__read__h849850; + 12'd384: data_out__h1020028 = satp_csr__read__h849913; + 12'd768: data_out__h1020028 = mstatus_csr__read__h850059; + 12'd769: data_out__h1020028 = 64'h800000000014112D; + 12'd770: data_out__h1020028 = medeleg_csr__read__h850220; + 12'd771: data_out__h1020028 = mideleg_csr__read__h850318; + 12'd772: data_out__h1020028 = mie_csr__read__h850445; 12'd773: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: data_out__h1020024 = mcounteren_csr__read__h850619; - 12'd832: data_out__h1020024 = csrf_mscratch_csr; + 12'd774: data_out__h1020028 = mcounteren_csr__read__h850617; + 12'd832: data_out__h1020028 = csrf_mscratch_csr; 12'd833: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: data_out__h1020024 = mcause_csr__read__h850885; - 12'd835: data_out__h1020024 = csrf_mtval_csr; - 12'd836: data_out__h1020024 = mip_csr__read__h851124; - 12'd1952: data_out__h1020024 = csrf_rg_tselect; - 12'd1953: data_out__h1020024 = rg_tdata1__read__h852225; - 12'd1954: data_out__h1020024 = csrf_rg_tdata2; - 12'd1955: data_out__h1020024 = csrf_rg_tdata3; - 12'd1968: data_out__h1020024 = csrf_rg_dcsr; + 12'd834: data_out__h1020028 = mcause_csr__read__h850883; + 12'd835: data_out__h1020028 = csrf_mtval_csr; + 12'd836: data_out__h1020028 = mip_csr__read__h851122; + 12'd1952: data_out__h1020028 = csrf_rg_tselect; + 12'd1953: data_out__h1020028 = rg_tdata1__read__h852223; + 12'd1954: data_out__h1020028 = csrf_rg_tdata2; + 12'd1955: data_out__h1020028 = csrf_rg_tdata3; + 12'd1968: data_out__h1020028 = csrf_rg_dcsr; 12'd1969: - data_out__h1020024 = + data_out__h1020028 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: data_out__h1020024 = csrf_rg_dscratch0; - 12'd1971: data_out__h1020024 = csrf_rg_dscratch1; + 12'd1970: data_out__h1020028 = csrf_rg_dscratch0; + 12'd1971: data_out__h1020028 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h1020024 = 64'd0; - 12'd2049: data_out__h1020024 = x_reg_ifc__read__h849323; - 12'd2816, 12'd3072: data_out__h1020024 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: data_out__h1020024 = csrf_minstret_ehr_data_rl; - 12'd3008: data_out__h1020024 = { 48'd0, x__h896540 }; - 12'd3073: data_out__h1020024 = csrf_time_reg; - default: data_out__h1020024 = 64'b0; + data_out__h1020028 = 64'd0; + 12'd2049: data_out__h1020028 = x_reg_ifc__read__h849321; + 12'd2816, 12'd3072: data_out__h1020028 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: data_out__h1020028 = csrf_minstret_ehr_data_rl; + 12'd3008: data_out__h1020028 = { 48'd0, x__h896543 }; + 12'd3073: data_out__h1020028 = csrf_time_reg; + default: data_out__h1020028 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h849193 or - frm_csr__read__h849204 or - fcsr_csr__read__h849218 or - sstatus_csr__read__h849414 or - sie_csr__read__h849484 or + fflags_csr__read__h849191 or + frm_csr__read__h849202 or + fcsr_csr__read__h849216 or + sstatus_csr__read__h849412 or + sie_csr__read__h849482 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849572 or + scounteren_csr__read__h849570 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849712 or + scause_csr__read__h849710 or csrf_stval_csr or - sip_csr__read__h849852 or - satp_csr__read__h849915 or - mstatus_csr__read__h850061 or - medeleg_csr__read__h850222 or - mideleg_csr__read__h850320 or - mie_csr__read__h850447 or + sip_csr__read__h849850 or + satp_csr__read__h849913 or + mstatus_csr__read__h850059 or + medeleg_csr__read__h850220 or + mideleg_csr__read__h850318 or + mie_csr__read__h850445 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850619 or + mcounteren_csr__read__h850617 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850885 or + mcause_csr__read__h850883 or csrf_mtval_csr or - mip_csr__read__h851124 or + mip_csr__read__h851122 or csrf_rg_tselect or - rg_tdata1__read__h852225 or + rg_tdata1__read__h852223 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849323 or + x_reg_ifc__read__h849321 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896543 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[136:125]) - 12'd1: addr__h843948 = fflags_csr__read__h849193; - 12'd2: addr__h843948 = frm_csr__read__h849204; - 12'd3: addr__h843948 = fcsr_csr__read__h849218; - 12'd256: addr__h843948 = sstatus_csr__read__h849414; - 12'd260: addr__h843948 = sie_csr__read__h849484; + 12'd1: addr__h843947 = fflags_csr__read__h849191; + 12'd2: addr__h843947 = frm_csr__read__h849202; + 12'd3: addr__h843947 = fcsr_csr__read__h849216; + 12'd256: addr__h843947 = sstatus_csr__read__h849412; + 12'd260: addr__h843947 = sie_csr__read__h849482; 12'd261: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h843948 = scounteren_csr__read__h849572; - 12'd320: addr__h843948 = csrf_sscratch_csr; + 12'd262: addr__h843947 = scounteren_csr__read__h849570; + 12'd320: addr__h843947 = csrf_sscratch_csr; 12'd321: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h843948 = scause_csr__read__h849712; - 12'd323: addr__h843948 = csrf_stval_csr; - 12'd324: addr__h843948 = sip_csr__read__h849852; - 12'd384: addr__h843948 = satp_csr__read__h849915; - 12'd768: addr__h843948 = mstatus_csr__read__h850061; - 12'd769: addr__h843948 = 64'h800000000014112D; - 12'd770: addr__h843948 = medeleg_csr__read__h850222; - 12'd771: addr__h843948 = mideleg_csr__read__h850320; - 12'd772: addr__h843948 = mie_csr__read__h850447; + 12'd322: addr__h843947 = scause_csr__read__h849710; + 12'd323: addr__h843947 = csrf_stval_csr; + 12'd324: addr__h843947 = sip_csr__read__h849850; + 12'd384: addr__h843947 = satp_csr__read__h849913; + 12'd768: addr__h843947 = mstatus_csr__read__h850059; + 12'd769: addr__h843947 = 64'h800000000014112D; + 12'd770: addr__h843947 = medeleg_csr__read__h850220; + 12'd771: addr__h843947 = mideleg_csr__read__h850318; + 12'd772: addr__h843947 = mie_csr__read__h850445; 12'd773: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h843948 = mcounteren_csr__read__h850619; - 12'd832: addr__h843948 = csrf_mscratch_csr; + 12'd774: addr__h843947 = mcounteren_csr__read__h850617; + 12'd832: addr__h843947 = csrf_mscratch_csr; 12'd833: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h843948 = mcause_csr__read__h850885; - 12'd835: addr__h843948 = csrf_mtval_csr; - 12'd836: addr__h843948 = mip_csr__read__h851124; - 12'd1952: addr__h843948 = csrf_rg_tselect; - 12'd1953: addr__h843948 = rg_tdata1__read__h852225; - 12'd1954: addr__h843948 = csrf_rg_tdata2; - 12'd1955: addr__h843948 = csrf_rg_tdata3; - 12'd1968: addr__h843948 = csrf_rg_dcsr; + 12'd834: addr__h843947 = mcause_csr__read__h850883; + 12'd835: addr__h843947 = csrf_mtval_csr; + 12'd836: addr__h843947 = mip_csr__read__h851122; + 12'd1952: addr__h843947 = csrf_rg_tselect; + 12'd1953: addr__h843947 = rg_tdata1__read__h852223; + 12'd1954: addr__h843947 = csrf_rg_tdata2; + 12'd1955: addr__h843947 = csrf_rg_tdata3; + 12'd1968: addr__h843947 = csrf_rg_dcsr; 12'd1969: - addr__h843948 = + addr__h843947 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h843948 = csrf_rg_dscratch0; - 12'd1971: addr__h843948 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843948 = 64'd0; - 12'd2049: addr__h843948 = x_reg_ifc__read__h849323; - 12'd2816, 12'd3072: addr__h843948 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h843948 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h843948 = { 48'd0, x__h896540 }; - 12'd3073: addr__h843948 = csrf_time_reg; - default: addr__h843948 = 64'b0; + 12'd1970: addr__h843947 = csrf_rg_dscratch0; + 12'd1971: addr__h843947 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h843947 = 64'd0; + 12'd2049: addr__h843947 = x_reg_ifc__read__h849321; + 12'd2816, 12'd3072: addr__h843947 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h843947 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h843947 = { 48'd0, x__h896543 }; + 12'd3073: addr__h843947 = csrf_time_reg; + default: addr__h843947 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h849193 or - frm_csr__read__h849204 or - fcsr_csr__read__h849218 or - sstatus_csr__read__h849414 or - sie_csr__read__h849484 or + fflags_csr__read__h849191 or + frm_csr__read__h849202 or + fcsr_csr__read__h849216 or + sstatus_csr__read__h849412 or + sie_csr__read__h849482 or SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070 or - scounteren_csr__read__h849572 or + scounteren_csr__read__h849570 or csrf_sscratch_csr or SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109 or - scause_csr__read__h849712 or + scause_csr__read__h849710 or csrf_stval_csr or - sip_csr__read__h849852 or - satp_csr__read__h849915 or - mstatus_csr__read__h850061 or - medeleg_csr__read__h850222 or - mideleg_csr__read__h850320 or - mie_csr__read__h850447 or + sip_csr__read__h849850 or + satp_csr__read__h849913 or + mstatus_csr__read__h850059 or + medeleg_csr__read__h850220 or + mideleg_csr__read__h850318 or + mie_csr__read__h850445 or SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222 or - mcounteren_csr__read__h850619 or + mcounteren_csr__read__h850617 or csrf_mscratch_csr or SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261 or - mcause_csr__read__h850885 or + mcause_csr__read__h850883 or csrf_mtval_csr or - mip_csr__read__h851124 or + mip_csr__read__h851122 or csrf_rg_tselect or - rg_tdata1__read__h852225 or + rg_tdata1__read__h852223 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367 or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h849323 or + x_reg_ifc__read__h849321 or csrf_mcycle_ehr_data_rl or - csrf_minstret_ehr_data_rl or x__h896540 or csrf_time_reg) + csrf_minstret_ehr_data_rl or x__h896543 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[136:125]) - 12'd1: addr__h887458 = fflags_csr__read__h849193; - 12'd2: addr__h887458 = frm_csr__read__h849204; - 12'd3: addr__h887458 = fcsr_csr__read__h849218; - 12'd256: addr__h887458 = sstatus_csr__read__h849414; - 12'd260: addr__h887458 = sie_csr__read__h849484; + 12'd1: addr__h887460 = fflags_csr__read__h849191; + 12'd2: addr__h887460 = frm_csr__read__h849202; + 12'd3: addr__h887460 = fcsr_csr__read__h849216; + 12'd256: addr__h887460 = sstatus_csr__read__h849412; + 12'd260: addr__h887460 = sie_csr__read__h849482; 12'd261: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_csrf_stcc_reg_read__6046_BITS_8_ETC___d16070; - 12'd262: addr__h887458 = scounteren_csr__read__h849572; - 12'd320: addr__h887458 = csrf_sscratch_csr; + 12'd262: addr__h887460 = scounteren_csr__read__h849570; + 12'd320: addr__h887460 = csrf_sscratch_csr; 12'd321: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_IF_csrf_sepcc_reg_data_lat_0_wh_ETC___d16109; - 12'd322: addr__h887458 = scause_csr__read__h849712; - 12'd323: addr__h887458 = csrf_stval_csr; - 12'd324: addr__h887458 = sip_csr__read__h849852; - 12'd384: addr__h887458 = satp_csr__read__h849915; - 12'd768: addr__h887458 = mstatus_csr__read__h850061; - 12'd769: addr__h887458 = 64'h800000000014112D; - 12'd770: addr__h887458 = medeleg_csr__read__h850222; - 12'd771: addr__h887458 = mideleg_csr__read__h850320; - 12'd772: addr__h887458 = mie_csr__read__h850447; + 12'd322: addr__h887460 = scause_csr__read__h849710; + 12'd323: addr__h887460 = csrf_stval_csr; + 12'd324: addr__h887460 = sip_csr__read__h849850; + 12'd384: addr__h887460 = satp_csr__read__h849913; + 12'd768: addr__h887460 = mstatus_csr__read__h850059; + 12'd769: addr__h887460 = 64'h800000000014112D; + 12'd770: addr__h887460 = medeleg_csr__read__h850220; + 12'd771: addr__h887460 = mideleg_csr__read__h850318; + 12'd772: addr__h887460 = mie_csr__read__h850445; 12'd773: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_csrf_mtcc_reg_read__6198_BITS_8_ETC___d16222; - 12'd774: addr__h887458 = mcounteren_csr__read__h850619; - 12'd832: addr__h887458 = csrf_mscratch_csr; + 12'd774: addr__h887460 = mcounteren_csr__read__h850617; + 12'd832: addr__h887460 = csrf_mscratch_csr; 12'd833: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_IF_csrf_mepcc_reg_data_lat_0_wh_ETC___d16261; - 12'd834: addr__h887458 = mcause_csr__read__h850885; - 12'd835: addr__h887458 = csrf_mtval_csr; - 12'd836: addr__h887458 = mip_csr__read__h851124; - 12'd1952: addr__h887458 = csrf_rg_tselect; - 12'd1953: addr__h887458 = rg_tdata1__read__h852225; - 12'd1954: addr__h887458 = csrf_rg_tdata2; - 12'd1955: addr__h887458 = csrf_rg_tdata3; - 12'd1968: addr__h887458 = csrf_rg_dcsr; + 12'd834: addr__h887460 = mcause_csr__read__h850883; + 12'd835: addr__h887460 = csrf_mtval_csr; + 12'd836: addr__h887460 = mip_csr__read__h851122; + 12'd1952: addr__h887460 = csrf_rg_tselect; + 12'd1953: addr__h887460 = rg_tdata1__read__h852223; + 12'd1954: addr__h887460 = csrf_rg_tdata2; + 12'd1955: addr__h887460 = csrf_rg_tdata3; + 12'd1968: addr__h887460 = csrf_rg_dcsr; 12'd1969: - addr__h887458 = + addr__h887460 = SEXT__0_CONCAT_csrf_rg_dpc_read__6343_BITS_85__ETC___d16367; - 12'd1970: addr__h887458 = csrf_rg_dscratch0; - 12'd1971: addr__h887458 = csrf_rg_dscratch1; - 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887458 = 64'd0; - 12'd2049: addr__h887458 = x_reg_ifc__read__h849323; - 12'd2816, 12'd3072: addr__h887458 = csrf_mcycle_ehr_data_rl; - 12'd2818, 12'd3074: addr__h887458 = csrf_minstret_ehr_data_rl; - 12'd3008: addr__h887458 = { 48'd0, x__h896540 }; - 12'd3073: addr__h887458 = csrf_time_reg; - default: addr__h887458 = 64'b0; + 12'd1970: addr__h887460 = csrf_rg_dscratch0; + 12'd1971: addr__h887460 = csrf_rg_dscratch1; + 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: addr__h887460 = 64'd0; + 12'd2049: addr__h887460 = x_reg_ifc__read__h849321; + 12'd2816, 12'd3072: addr__h887460 = csrf_mcycle_ehr_data_rl; + 12'd2818, 12'd3074: addr__h887460 = csrf_minstret_ehr_data_rl; + 12'd3008: addr__h887460 = { 48'd0, x__h896543 }; + 12'd3073: addr__h887460 = csrf_time_reg; + default: addr__h887460 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or @@ -46898,17 +46898,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h858476 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h858476 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h858476 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h858476 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h858474 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h858474 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h858474 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h858474 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h858476 = + thin_reserved__h858474 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h858476 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h858476 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h858476 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h858476 = + 5'd28: thin_reserved__h858474 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h858474 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h858474 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h858474 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46922,17 +46922,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_reserved__h899111 = csrf_ddc_reg[54:53]; - 5'd12: thin_reserved__h899111 = csrf_stcc_reg[54:53]; - 5'd13: thin_reserved__h899111 = csrf_stdc_reg[54:53]; - 5'd14: thin_reserved__h899111 = csrf_sScratchC_reg[54:53]; + 5'd1: thin_reserved__h899114 = csrf_ddc_reg[54:53]; + 5'd12: thin_reserved__h899114 = csrf_stcc_reg[54:53]; + 5'd13: thin_reserved__h899114 = csrf_stdc_reg[54:53]; + 5'd14: thin_reserved__h899114 = csrf_sScratchC_reg[54:53]; 5'd15: - thin_reserved__h899111 = + thin_reserved__h899114 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17176; - 5'd28: thin_reserved__h899111 = csrf_mtcc_reg[54:53]; - 5'd29: thin_reserved__h899111 = csrf_mtdc_reg[54:53]; - 5'd30: thin_reserved__h899111 = csrf_mScratchC_reg[54:53]; - default: thin_reserved__h899111 = + 5'd28: thin_reserved__h899114 = csrf_mtcc_reg[54:53]; + 5'd29: thin_reserved__h899114 = csrf_mtdc_reg[54:53]; + 5'd30: thin_reserved__h899114 = csrf_mScratchC_reg[54:53]; + default: thin_reserved__h899114 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17182; endcase end @@ -46946,17 +46946,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h858712 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h858712 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h858712 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h858712 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h858710 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h858710 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h858710 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h858710 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h858712 = + thin_perms_soft__h858710 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h858712 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h858712 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h858712 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h858712 = + 5'd28: thin_perms_soft__h858710 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h858710 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h858710 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h858710 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46970,17 +46970,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_perms_soft__h899287 = csrf_ddc_reg[71:68]; - 5'd12: thin_perms_soft__h899287 = csrf_stcc_reg[71:68]; - 5'd13: thin_perms_soft__h899287 = csrf_stdc_reg[71:68]; - 5'd14: thin_perms_soft__h899287 = csrf_sScratchC_reg[71:68]; + 5'd1: thin_perms_soft__h899290 = csrf_ddc_reg[71:68]; + 5'd12: thin_perms_soft__h899290 = csrf_stcc_reg[71:68]; + 5'd13: thin_perms_soft__h899290 = csrf_stdc_reg[71:68]; + 5'd14: thin_perms_soft__h899290 = csrf_sScratchC_reg[71:68]; 5'd15: - thin_perms_soft__h899287 = + thin_perms_soft__h899290 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d16862; - 5'd28: thin_perms_soft__h899287 = csrf_mtcc_reg[71:68]; - 5'd29: thin_perms_soft__h899287 = csrf_mtdc_reg[71:68]; - 5'd30: thin_perms_soft__h899287 = csrf_mScratchC_reg[71:68]; - default: thin_perms_soft__h899287 = + 5'd28: thin_perms_soft__h899290 = csrf_mtcc_reg[71:68]; + 5'd29: thin_perms_soft__h899290 = csrf_mtdc_reg[71:68]; + 5'd30: thin_perms_soft__h899290 = csrf_mScratchC_reg[71:68]; + default: thin_perms_soft__h899290 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d16868; endcase end @@ -46994,17 +46994,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h860420 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h860420 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h860420 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h860420 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h860418 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h860418 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h860418 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h860418 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h860420 = + thin_bounds_topBits__h860418 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h860420 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h860420 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h860420 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h860420 = + 5'd28: thin_bounds_topBits__h860418 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h860418 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h860418 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h860418 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -47018,17 +47018,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_bounds_topBits__h900513 = csrf_ddc_reg[27:14]; - 5'd12: thin_bounds_topBits__h900513 = csrf_stcc_reg[27:14]; - 5'd13: thin_bounds_topBits__h900513 = csrf_stdc_reg[27:14]; - 5'd14: thin_bounds_topBits__h900513 = csrf_sScratchC_reg[27:14]; + 5'd1: thin_bounds_topBits__h900516 = csrf_ddc_reg[27:14]; + 5'd12: thin_bounds_topBits__h900516 = csrf_stcc_reg[27:14]; + 5'd13: thin_bounds_topBits__h900516 = csrf_stdc_reg[27:14]; + 5'd14: thin_bounds_topBits__h900516 = csrf_sScratchC_reg[27:14]; 5'd15: - thin_bounds_topBits__h900513 = + thin_bounds_topBits__h900516 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17285; - 5'd28: thin_bounds_topBits__h900513 = csrf_mtcc_reg[27:14]; - 5'd29: thin_bounds_topBits__h900513 = csrf_mtdc_reg[27:14]; - 5'd30: thin_bounds_topBits__h900513 = csrf_mScratchC_reg[27:14]; - default: thin_bounds_topBits__h900513 = + 5'd28: thin_bounds_topBits__h900516 = csrf_mtcc_reg[27:14]; + 5'd29: thin_bounds_topBits__h900516 = csrf_mtdc_reg[27:14]; + 5'd30: thin_bounds_topBits__h900516 = csrf_mScratchC_reg[27:14]; + default: thin_bounds_topBits__h900516 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17291; endcase end @@ -47612,17 +47612,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h858477 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h858477 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h858477 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h858477 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h858475 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h858475 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h858475 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h858475 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h858477 = + thin_otype__h858475 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h858477 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h858477 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h858477 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h858477 = + 5'd28: thin_otype__h858475 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h858475 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h858475 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h858475 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -47636,17 +47636,17 @@ module mkCore(CLK, csrf_mtcc_reg or csrf_mtdc_reg or csrf_mScratchC_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[123:119]) - 5'd1: thin_otype__h899112 = csrf_ddc_reg[52:35]; - 5'd12: thin_otype__h899112 = csrf_stcc_reg[52:35]; - 5'd13: thin_otype__h899112 = csrf_stdc_reg[52:35]; - 5'd14: thin_otype__h899112 = csrf_sScratchC_reg[52:35]; + 5'd1: thin_otype__h899115 = csrf_ddc_reg[52:35]; + 5'd12: thin_otype__h899115 = csrf_stcc_reg[52:35]; + 5'd13: thin_otype__h899115 = csrf_stdc_reg[52:35]; + 5'd14: thin_otype__h899115 = csrf_sScratchC_reg[52:35]; 5'd15: - thin_otype__h899112 = + thin_otype__h899115 = IF_csrf_sepcc_reg_data_lat_0_whas__9_THEN_csrf_ETC___d17198; - 5'd28: thin_otype__h899112 = csrf_mtcc_reg[52:35]; - 5'd29: thin_otype__h899112 = csrf_mtdc_reg[52:35]; - 5'd30: thin_otype__h899112 = csrf_mScratchC_reg[52:35]; - default: thin_otype__h899112 = + 5'd28: thin_otype__h899115 = csrf_mtcc_reg[52:35]; + 5'd29: thin_otype__h899115 = csrf_mtdc_reg[52:35]; + 5'd30: thin_otype__h899115 = csrf_mScratchC_reg[52:35]; + default: thin_otype__h899115 = IF_csrf_mepcc_reg_data_lat_0_whas__6_THEN_csrf_ETC___d17204; endcase end @@ -56736,17 +56736,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254472); + $write("'h%h", value__h254474); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", value__h254636); + $write("'h%h", value__h254638); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) - $write("'h%h", x__h254748[64:0]); + $write("'h%h", x__h254750[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doFinishMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58540,14 +58540,14 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) begin - v__h213411 = $time; + v__h213412 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) - $write("%t : ", v__h213411, "[doRespLdMem]", " "); + $write("%t : ", v__h213412, "[doRespLdMem]", " "); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212839); + if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("'h%h", t__h212840); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58686,15 +58686,15 @@ module mkCore(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) begin - v__h215680 = $time; + v__h215681 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("%t : ", v__h215680, "[doRespLdForward]", " "); + $write("%t : ", v__h215681, "[doRespLdForward]", " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) - $write("'h%h", t__h215125); + $write("'h%h", t__h215126); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward) $write("; "); if (RST_N != `BSV_RESET_VALUE) @@ -58919,17 +58919,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239691); + $write("'h%h", value__h239693); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h239855); + $write("'h%h", value__h239857); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h239967[64:0]); + $write("'h%h", x__h239969[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -58969,17 +58969,17 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" o: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h240848); + $write("'h%h", value__h240850); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" b: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", value__h241012); + $write("'h%h", value__h241014); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" t: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) - $write("'h%h", x__h241124[64:0]); + $write("'h%h", x__h241126[64:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_doExeMem) $write(" sp: "); if (RST_N != `BSV_RESET_VALUE) @@ -67212,14 +67212,14 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) begin - v__h271938 = $time; + v__h271939 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d5591) - $write("%t : [Ld resp] ", v__h271938); + $write("%t : [Ld resp] ", v__h271939); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && @@ -68859,13 +68859,13 @@ module mkCore(CLK, if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) begin - v__h347456 = $time; + v__h347457 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) - $write("%t : [Ld resp] ", v__h347456); + $write("%t : [Ld resp] ", v__h347457); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq && NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d5595) @@ -70739,7 +70739,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) begin - v__h423782 = $time; + v__h423783 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) @@ -70747,7 +70747,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[155:153] == 3'd0) - $write("%t : [Ld resp] ", v__h423782); + $write("%t : [Ld resp] ", v__h423783); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs && coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[519] && diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v index 97af342..c33a462 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCoreW.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:12:58 BST 2020 +// On Mon Jul 6 19:26:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v index f19e789..e51786f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDCRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:40 BST 2020 +// On Mon Jul 6 19:21:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v index b2d1d32..5333400 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Abstract_Commands.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:35 BST 2020 +// On Mon Jul 6 19:14:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v index 8aa4e5c..97e03b0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_Run_Control.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:34 BST 2020 +// On Mon Jul 6 19:14:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v index 1288abf..b84cbf5 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDM_System_Bus.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:49 BST 2020 +// On Mon Jul 6 19:14:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v index 3d0951d..d6b5c8c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:41 BST 2020 +// On Mon Jul 6 19:21:33 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v index 32f3f60..1777d02 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:44 BST 2020 +// On Mon Jul 6 19:21:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v index ebb74d4..23c7868 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDTlbSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:13 BST 2020 +// On Mon Jul 6 19:22:07 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v index 9638caa..e5c6baf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDebug_Module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:50 BST 2020 +// On Mon Jul 6 19:14:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v index a74134e..e9a40c4 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDirPredictor.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:28 BST 2020 +// On Mon Jul 6 19:23:31 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v index 7eae238..b2ff1d9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDivExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:31 BST 2020 +// On Mon Jul 6 19:23:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v index e76bdf2..97e6b47 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:12 BST 2020 +// On Mon Jul 6 19:23:06 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v index 7883f66..39b6a8c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleFMA.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:17 BST 2020 +// On Mon Jul 6 19:23:12 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v index 977007a..26d852a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDoubleSqrt.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:14 BST 2020 +// On Mon Jul 6 19:23:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v index b1eafde..e1dead6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkDummyStoreBuffer.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:40 BST 2020 +// On Mon Jul 6 19:15:31 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v index 3053991..d807ba1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkEpochManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:30 BST 2020 +// On Mon Jul 6 19:15:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v index 1327a8d..3e4955c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFetchStage.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:42 BST 2020 +// On Mon Jul 6 19:23:46 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v index 066d9ca..ddee3d2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFmaExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:20 BST 2020 +// On Mon Jul 6 19:23:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v index 44deef1..cd12bfc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:33 BST 2020 +// On Mon Jul 6 19:23:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v index 9e62170..23f9cc8 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkFpuMulDivRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:33 BST 2020 +// On Mon Jul 6 19:23:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v index ab9d6c8..800f46f 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:25 BST 2020 +// On Mon Jul 6 19:23:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v index 46b1522..b7225f6 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSelectPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:25 BST 2020 +// On Mon Jul 6 19:23:28 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v index d6cc216..97d4594 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGShareGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v index 9759d34..5416d95 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkGSharePred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v index bbf929a..8e24637 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIBankWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:50 BST 2020 +// On Mon Jul 6 19:21:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v index 76020c1..9f10803 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:45 BST 2020 +// On Mon Jul 6 19:21:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v index 7673da5..357a458 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkICoCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:51 BST 2020 +// On Mon Jul 6 19:21:43 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v index 40ccefb..8746370 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPRqMshrWrapper.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:45 BST 2020 +// On Mon Jul 6 19:21:38 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v index e2ad67f..1c6ca35 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkIPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:49 BST 2020 +// On Mon Jul 6 19:21:41 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v index 47dab80..114c598 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkITlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:28 BST 2020 +// On Mon Jul 6 19:15:19 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v index b442c38..5d63a28 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkL2Tlb.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:07:17 BST 2020 +// On Mon Jul 6 19:21:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v index 1d30beb..0c308ab 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:04 BST 2020 +// On Mon Jul 6 19:22:59 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v index 7bc651f..0b35c83 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLLPipeline.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:53 BST 2020 +// On Mon Jul 6 19:22:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v index 0077468..3ecd888 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLSQIssueLdQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:44 BST 2020 +// On Mon Jul 6 19:19:37 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v index 2b7c212..e635727 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkLastLvCRqMshr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:45 BST 2020 +// On Mon Jul 6 19:22:40 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v index 9a95fb0..a26ccb1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMMIOInst.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:19 BST 2020 +// On Mon Jul 6 19:15:09 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v index c41bb4a..d8ac626 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemDispToRegFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:05 BST 2020 +// On Mon Jul 6 19:21:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v index 03d1029..d5688d9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemLoader.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:21 BST 2020 +// On Mon Jul 6 19:22:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v index b4115d3..64169ac 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMemRegToExeFifo.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:08:05 BST 2020 +// On Mon Jul 6 19:21:57 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v index 7bbef51..dd9c600 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMinimumExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:19 BST 2020 +// On Mon Jul 6 19:23:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v index 1b3225e..616a61d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkMulExecQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:31 BST 2020 +// On Mon Jul 6 19:23:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v index 040147d..c1d1f5c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkNullTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:13 BST 2020 +// On Mon Jul 6 19:15:04 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v index 56a6e83..f82db2b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkP3_Core.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:13:07 BST 2020 +// On Mon Jul 6 19:26:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v index 4739fc7..e98f4dc 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkPLIC_16_2_7.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:43 BST 2020 +// On Mon Jul 6 19:14:34 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v index 7ee018f..0ce2651 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkProc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkProc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:12:47 BST 2020 +// On Mon Jul 6 19:25:52 BST 2020 // // // Ports: @@ -1884,8 +1884,8 @@ module mkProc(CLK, MUX_llc$dma_memReq_enq_1__VAL_2, MUX_llc$dma_memReq_enq_1__VAL_3, MUX_llc$dma_memReq_enq_1__VAL_4; - wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2, - MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1; + wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1, + MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2; wire [515 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1; wire [214 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1, MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2, @@ -1927,7 +1927,7 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5, - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7, + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6, MUX_llc$dma_memReq_enq_1__SEL_1, MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2, MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3, @@ -1948,46 +1948,46 @@ module mkProc(CLK, // declarations used by system tasks // synopsys translate_off - reg [31 : 0] v__h224139; - reg [31 : 0] v__h223691; + reg [31 : 0] v__h226276; + reg [31 : 0] v__h225828; reg [31 : 0] v__h9702; reg [31 : 0] v__h9897; reg [31 : 0] v__h11245; reg [31 : 0] v__h17177; - reg [31 : 0] v__h17348; - reg [31 : 0] v__h17740; - reg [31 : 0] v__h18150; + reg [31 : 0] v__h17357; + reg [31 : 0] v__h17749; + reg [31 : 0] v__h18159; reg [31 : 0] v__h2280; reg [31 : 0] v__h7388; - reg [31 : 0] v__h20462; - reg [31 : 0] v__h21008; - reg [31 : 0] v__h21530; - reg [31 : 0] v__h201342; - reg [31 : 0] v__h215051; - reg [31 : 0] v__h193319; - reg [31 : 0] v__h222677; - reg [31 : 0] v__h193908; - reg [31 : 0] v__h194094; + reg [31 : 0] v__h20472; + reg [31 : 0] v__h21018; + reg [31 : 0] v__h21540; + reg [31 : 0] v__h203428; + reg [31 : 0] v__h217146; + reg [31 : 0] v__h193329; + reg [31 : 0] v__h224814; + reg [31 : 0] v__h193918; + reg [31 : 0] v__h194104; reg [31 : 0] v__h2274; reg [31 : 0] v__h7382; reg [31 : 0] v__h9696; reg [31 : 0] v__h9891; reg [31 : 0] v__h11239; reg [31 : 0] v__h17171; - reg [31 : 0] v__h17342; - reg [31 : 0] v__h17734; - reg [31 : 0] v__h18144; - reg [31 : 0] v__h20456; - reg [31 : 0] v__h21002; - reg [31 : 0] v__h21524; - reg [31 : 0] v__h193313; - reg [31 : 0] v__h193902; - reg [31 : 0] v__h194088; - reg [31 : 0] v__h201336; - reg [31 : 0] v__h215045; - reg [31 : 0] v__h222671; - reg [31 : 0] v__h223685; - reg [31 : 0] v__h224133; + reg [31 : 0] v__h17351; + reg [31 : 0] v__h17743; + reg [31 : 0] v__h18153; + reg [31 : 0] v__h20466; + reg [31 : 0] v__h21012; + reg [31 : 0] v__h21534; + reg [31 : 0] v__h193323; + reg [31 : 0] v__h193912; + reg [31 : 0] v__h194098; + reg [31 : 0] v__h203422; + reg [31 : 0] v__h217140; + reg [31 : 0] v__h224808; + reg [31 : 0] v__h225822; + reg [31 : 0] v__h226270; // synopsys translate_on // remaining internal signals @@ -1995,121 +1995,121 @@ module mkProc(CLK, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3, CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971, - dword__h150359, - ld_data__h188181, - v_wdata__h215359, - wflit_wdata__h17678; - reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384; - reg [7 : 0] v_wstrb__h215360, wflit_wstrb__h17679; - reg [5 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844; - reg [2 : 0] x__h100956; - reg [1 : 0] CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25, + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973, + dword__h150369, + ld_data__h188191, + v_wdata__h217505, + wflit_wdata__h17687; + reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386; + reg [7 : 0] v_wstrb__h217506, wflit_wstrb__h17688; + reg [5 : 0] IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846; + reg [2 : 0] x__h100966; + reg [1 : 0] CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27; reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710, - v_wuser__h215362, - x__h100957, - x__h127593; - wire [583 : 0] IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1681; - wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830; - wire [517 : 0] IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680; - wire [515 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825; - wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807; - wire [129 : 0] IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164; - wire [128 : 0] amoExec___d1006, - amoExec___d1076, - amoExec___d1129, - amoExec___d1354, - amoExec___d920, + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712, + v_wuser__h217508, + x__h100967, + x__h127603; + wire [583 : 0] IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1683; + wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1832; + wire [517 : 0] IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1682; + wire [515 : 0] IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674, + IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1827; + wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2021, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1809; + wire [129 : 0] IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1166; + wire [128 : 0] amoExec___d1008, + amoExec___d1078, + amoExec___d1131, + amoExec___d1356, + amoExec___d922, mmio_axi4_adapter_rspData_77_BIT_128_78_CONCAT_ETC___d187; - wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1773, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1790, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1824; + wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1775, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1792, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1826; wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34, llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32; wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33; wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31; - wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546, - IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544; - wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392; - wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108; - wire [63 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159, - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918, - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054, - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982, - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106, - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604, - addr1__h90533, - data__h140632, - failed_testnum__h223734, - line_addr__h140065, - line_addr__h150176, - line_addr__h193455, - mmioPlatform_mtime__h59831, - newData__h45219, - newData__h53320, - v_awaddr__h214948, - value__h61538, - x__h48532, - x__h56610, - x__h64490, - x__h68445, - x__h71119, - x__h73614, - x__h79161; - wire [47 : 0] IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1145, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947; - wire [31 : 0] IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1140, - IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938, - IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389, - amo_req_data__h39114, - lower_data__h44520, + wire [66 : 0] IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548, + IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546; + wire [65 : 0] mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394; + wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110; + wire [63 : 0] IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161, + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108, + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606, + addr1__h90543, + data__h140642, + failed_testnum__h225871, + line_addr__h140075, + line_addr__h150186, + line_addr__h193465, + mmioPlatform_mtime__h59841, + newData__h45229, + newData__h53330, + v_awaddr__h217034, + value__h61548, + x__h48542, + x__h56620, + x__h64500, + x__h68455, + x__h71129, + x__h73624, + x__h79171; + wire [47 : 0] IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1147, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949; + wire [31 : 0] IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1142, + IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940, + IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391, + amo_req_data__h39124, + lower_data__h44530, mmioPlatform_mtime_BITS_31_TO_0__q8, mmioPlatform_mtime_BITS_63_TO_32__q7, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5, - upper_data__h44521, - v__h44376, - v__h44413, - x_data__h42055; - wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1533; - wire [7 : 0] IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905, + upper_data__h44531, + v__h44386, + v__h44423, + x_data__h42065; + wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535; + wire [7 : 0] IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907, mem_req_rd_addr_arlen__h5411, - mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910; + mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912; wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30; - wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1532, + wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534, x__h15143, x__h15155, x__h15167, @@ -2140,103 +2140,112 @@ module mkProc(CLK, y__h15288, y__h15300, y__h15312; - wire [3 : 0] b__h193255, b__h2174, mmioPlatform_reqAmofunc__h88303; - wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1748, - _theResult_____1_awsize_val__h17116; - wire [1 : 0] IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609; - wire IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962, - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818, - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957, - IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678, - IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, - IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101, - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1171, - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367, - IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883, - IF_mmio_axi4_adapter_f_rsps_to_core_first__291_ETC___d1367, - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630, - IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479, - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416, - IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712, - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549, - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556, - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423, - NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539, - NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836, - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241, - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320, - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1310, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1358, - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1370, - NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989, - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993, - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481, - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714, + wire [3 : 0] b__h193265, b__h2174, mmioPlatform_reqAmofunc__h88313; + wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1750, + _theResult_____1_awsize_val__h17116, + x__h194318, + x__h217392; + wire [1 : 0] IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611; + wire IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964, + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820, + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959, + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680, + IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120, + IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103, + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1173, + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369, + IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885, + IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369, + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632, + IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481, + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418, + IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714, + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551, + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558, + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425, + NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541, + NOT_enqDst_1_0_rl_642_BIT_584_643_648_AND_SEL__ETC___d1838, + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243, + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2323, + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2326, + NOT_llc_axi4_adapter_rg_wr_req_beat_345_EQ_0_3_ETC___d2359, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1196, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1291, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1302, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1312, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1360, + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1372, + NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991, + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995, + NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208, + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483, + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716, _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq, _theResult____h13492, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781, - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788, - core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764, - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252, - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037, - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936, - mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307, - mmioPlatform_cycle_90_ULT_99___d491, - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372, - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029, - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654, - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829, - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974, - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253, - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783, + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790, + core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2301, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2304, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2309, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2312, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2317, + llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2320, + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039, + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938, + mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309, + mmioPlatform_cycle_92_ULT_99___d493, + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374, + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031, + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656, + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831, + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257, + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261, mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d8, mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181, - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217, + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221, whichHalf___1__h15055, - x__h100756, + x__h100766, x__h10399, - x__h116294, - x__h122858, - x__h17610; + x__h116304, + x__h122868, + x__h17619; // action method start assign RDY_start = mmioPlatform_state == 2'd0 && core_0$RDY_coreReq_start ; @@ -2974,7 +2983,7 @@ module mkProc(CLK, // rule RL_doEnq assign CAN_FIRE_RL_doEnq = llc$RDY_to_child_rqFromC_enq && - IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447 ; + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449 ; assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ; // rule RL_srcPropose_2 @@ -2998,7 +3007,7 @@ module mkProc(CLK, // rule RL_doEnq_1 assign CAN_FIRE_RL_doEnq_1 = llc$RDY_to_child_rsFromC_enq && - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642 ; + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644 ; assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ; // rule RL_sendPRq @@ -3099,7 +3108,7 @@ module mkProc(CLK, // rule RL_mmio_axi4_adapter_rl_handle_write_req assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = mmio_axi4_adapter_f_reqs_from_core$EMPTY_N && - IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 && + IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ; assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && @@ -3139,23 +3148,23 @@ module mkProc(CLK, // rule RL_mmioPlatform_incCycle assign CAN_FIRE_RL_mmioPlatform_incCycle = mmioPlatform_state != 2'd0 && - mmioPlatform_cycle_90_ULT_99___d491 ; + mmioPlatform_cycle_92_ULT_99___d493 ; assign WILL_FIRE_RL_mmioPlatform_incCycle = CAN_FIRE_RL_mmioPlatform_incCycle ; // rule RL_mmioPlatform_incTime assign CAN_FIRE_RL_mmioPlatform_incTime = mmioPlatform_state == 2'd1 && - !mmioPlatform_cycle_90_ULT_99___d491 ; + !mmioPlatform_cycle_92_ULT_99___d493 ; assign WILL_FIRE_RL_mmioPlatform_incTime = CAN_FIRE_RL_mmioPlatform_incTime ; // rule RL_mmioPlatform_selectReq assign CAN_FIRE_RL_mmioPlatform_selectReq = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || core_0$RDY_mmioToPlatform_pRq_enq) && - NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513 && + NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515 && mmioPlatform_state == 2'd1 ; assign WILL_FIRE_RL_mmioPlatform_selectReq = CAN_FIRE_RL_mmioPlatform_selectReq && @@ -3172,7 +3181,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_processMSIP assign CAN_FIRE_RL_mmioPlatform_processMSIP = - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819 && + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd2 ; assign WILL_FIRE_RL_mmioPlatform_processMSIP = @@ -3181,7 +3190,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_waitMSIPDone assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone = core_0$RDY_mmioToPlatform_pRs_enq && - IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883 && + IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885 && mmioPlatform_curReq[66:64] == 3'd2 && mmioPlatform_state == 2'd3 ; assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone = @@ -3227,7 +3236,7 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_pRs_enq && (mmioPlatform_reqFunc[5:4] != 2'd2 || !mmioPlatform_toHostQ_empty || - x__h73614 == 64'd0 || + x__h73624 == 64'd0 || !mmioPlatform_toHostQ_full) && mmioPlatform_state == 2'd2 && mmioPlatform_curReq[66:64] == 3'd5 ; @@ -3245,7 +3254,7 @@ module mkProc(CLK, // rule RL_mmioPlatform_rl_mmio_to_fabric_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1196 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ; @@ -3253,37 +3262,37 @@ module mkProc(CLK, assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = core_0$RDY_mmioToPlatform_pRs_enq && mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1291 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1302 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307 && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1310 ; + mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309 && + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1312 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ; // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = mmio_axi4_adapter_f_reqs_from_core$FULL_N && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1358 ; + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1360 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req = CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ; // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = mmio_axi4_adapter_f_rsps_to_core$EMPTY_N && - IF_mmio_axi4_adapter_f_rsps_to_core_first__291_ETC___d1367 && - NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1370 ; + IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369 && + NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1372 ; assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp = CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ; @@ -3397,7 +3406,7 @@ module mkProc(CLK, // rule RL_llc_mem_server_doEnq assign CAN_FIRE_RL_llc_mem_server_doEnq = llc_mem_server_tlbQ$FULL_N && - IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 ; + IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120 ; assign WILL_FIRE_RL_llc_mem_server_doEnq = CAN_FIRE_RL_llc_mem_server_doEnq ; @@ -3465,7 +3474,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; + llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ; @@ -3477,7 +3486,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] && (llc_mem_server_rg_cacheline_cache_state == 3'd3 || llc_mem_server_rg_cacheline_cache_state == 3'd4) && - llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; + llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 ; assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3496,7 +3505,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss && !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ; @@ -3507,7 +3516,7 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_clearing && llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc_mem_server_rg_cacheline_cache_state == 3'd4 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3520,7 +3529,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 ; + !llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ; @@ -3530,7 +3539,7 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] && llc$RDY_dma_memReq_enq && llc_mem_server_rg_cacheline_cache_state == 3'd3 && - !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 ; + !llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 ; assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld = CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld && !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req && @@ -3610,10 +3619,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_clearing && llc$RDY_to_mem_toM_first && !llc_axi4_adapter_master_xactor_shim_wff_rv[74] && - (llc_axi4_adapter_rg_wr_req_beat != 3'd0 || - !llc_axi4_adapter_master_xactor_shim_awff_rv[98]) && - (llc_axi4_adapter_rg_wr_req_beat != 3'd7 || - llc$RDY_to_mem_toM_deq) && + NOT_llc_axi4_adapter_rg_wr_req_beat_345_EQ_0_3_ETC___d2359 && llc$to_mem_toM_first[644] ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -3626,7 +3632,7 @@ module mkProc(CLK, !llc_axi4_adapter_master_xactor_shim_arff_rv[98] && llc_axi4_adapter_f_pending_reads$FULL_N && !llc$to_mem_toM_first[644] && - b__h193255 == 4'd0 ; + b__h193265 == 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; @@ -3688,7 +3694,7 @@ module mkProc(CLK, assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = !llc_axi4_adapter_master_xactor_clearing && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] && - b__h193255 != 4'd0 ; + b__h193265 != 4'd0 ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ; @@ -3729,7 +3735,10 @@ module mkProc(CLK, // rule RL_llc_axi4_adapter_rl_handle_read_rsps assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = !llc_axi4_adapter_master_xactor_clearing && - llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && + (!llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] || + llc$RDY_to_mem_rsFromM_enq && + llc_axi4_adapter_f_pending_reads$EMPTY_N) ; assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; @@ -3742,7 +3751,7 @@ module mkProc(CLK, // inputs to muxes for submodule ports assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 ; + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && @@ -3750,27 +3759,27 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 = WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 = WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 ; + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 || + (!mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 = + assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 = WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ; assign MUX_llc$dma_memReq_enq_1__SEL_1 = @@ -3798,12 +3807,12 @@ module mkProc(CLK, assign MUX_mmioPlatform_curReq$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || core_0$mmioToPlatform_cRq_notEmpty) ; assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty ; assign MUX_mmioPlatform_state$write_1__SEL_2 = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && @@ -3831,28 +3840,28 @@ module mkProc(CLK, assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps && mmio_axi4_adapter_master_shim_rff$D_OUT[1] ; - assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = + assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 = { 1'd1, llc$to_child_toC_first[586:521], llc$to_child_toC_first[519:0] } ; - assign MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1 = + assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 = { 1'd0, llc$to_child_toC_first[586:1] } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 = { 1'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846, (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amo_req_data__h39114 : - x_data__h42055 } ; + amo_req_data__h39124 : + x_data__h42065 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 = { 7'd106, - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 = { 7'd106, - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0) ? 32'd1 : 32'd0 } ; @@ -3868,42 +3877,42 @@ module mkProc(CLK, (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 67'h60000000000000000, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : { 3'd6, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 = { 65'h0AAAAAAAAAAAAAAAA, - mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392 } ; + mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = - { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; - assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = { 2'd3, mmioPlatform_amoResp } ; + assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 = + { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 = { 3'd6, mmioPlatform_waitLowerMSIPCRs ? { 63'd0, core_0$mmioToPlatform_cRs_first } : - { v__h44376, 32'd0 }, + { v__h44386, 32'd0 }, 64'd0 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113 } ; assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 = { mmioPlatform_reqFunc[5:4] != 2'd0, - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164 } ; + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1166 } ; assign MUX_llc$dma_memReq_enq_1__VAL_1 = { llc_mem_server_rg_cacheline_cache_addr, 64'hFFFFFFFFFFFFFFFF, llc_mem_server_rg_cacheline_cache_data, 5'd10 } ; assign MUX_llc$dma_memReq_enq_1__VAL_2 = - { line_addr__h140065, + { line_addr__h140075, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_3 = - { line_addr__h150176, + { line_addr__h150186, 585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ; assign MUX_llc$dma_memReq_enq_1__VAL_4 = { llc_mem_server_tlbQ$D_OUT[64:1], @@ -3923,14 +3932,14 @@ module mkProc(CLK, llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] != 2'd0 && llc_mem_server_rg_cacheline_cache_data[512], - IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019, + IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2021, (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd1) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[127:64], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd0) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[63:0] } ; assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 = llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ; @@ -3938,21 +3947,21 @@ module mkProc(CLK, { 65'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 } ; + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 } ; assign MUX_mmioPlatform_amoResp$write_1__VAL_2 = { 1'd0, (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054, + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056, 64'd0 } ; assign MUX_mmioPlatform_curReq$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) ? + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) ? 67'h1AAAAAAAAAAAAAAAA : - ((!core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) ? + ((!core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) ? 67'h2AAAAAAAAAAAAAAAA : - IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546) ; + IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548) ; assign MUX_mmioPlatform_curReq$write_1__VAL_2 = { 3'd7, (mmioPlatform_instSel == 2'd3) ? @@ -3965,11 +3974,11 @@ module mkProc(CLK, mmioPlatform_instSel + 2'd1 ; assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ; assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 = - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 ; assign MUX_mmioPlatform_state$write_1__VAL_1 = (!mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) ? + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) ? 2'd3 : 2'd2 ; assign MUX_mmioPlatform_state$write_1__VAL_3 = @@ -3980,32 +3989,32 @@ module mkProc(CLK, (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) : 2'd3) ; always@(mmioPlatform_reqFunc or - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 or + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_4 = - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; endcase end always@(mmioPlatform_reqFunc or - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 or + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 or mmioPlatform_mtip_0) begin case (mmioPlatform_reqFunc[5:4]) 2'd0: MUX_mmioPlatform_state$write_1__VAL_5 = 2'd1; 2'd1: MUX_mmioPlatform_state$write_1__VAL_5 = mmioPlatform_reqFunc[5:4]; default: MUX_mmioPlatform_state$write_1__VAL_5 = - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0) ? 2'd3 : 2'd1; @@ -4013,30 +4022,30 @@ module mkProc(CLK, end assign MUX_mmioPlatform_state$write_1__VAL_6 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - (mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ? + (mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ? 2'd2 : 2'd1) : 2'd1 ; assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 = - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0 ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 = { mmioPlatform_curReq[63:0], 6'd42, mmioPlatform_reqBE, - amoExec___d1354 } ; + amoExec___d1356 } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 = { mmioPlatform_curReq[63:0], - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844, + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846, mmioPlatform_reqBE, mmioPlatform_reqData } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 = { mmioPlatform_curReq[63:0], 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 = - { addr1__h90533, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + { addr1__h90543, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 = { 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ; assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 = @@ -4047,47 +4056,47 @@ module mkProc(CLK, 129'd0 } ; // inlined wires - assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73614 } ; + assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h73624 } ; assign mmioPlatform_toHostQ_enqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] == 2'd2 && mmioPlatform_toHostQ_empty && - x__h73614 != 64'd0 ; + x__h73624 != 64'd0 ; assign mmioPlatform_fromHostQ_deqReq_lat_0$whas = WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] == 2'd2 && !mmioPlatform_fromHostQ_empty && - x__h68445 == 64'd0 ; + x__h68455 == 64'd0 ; assign propDstIdx_1_lat_1$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 && - x__h100756 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 && + x__h100766 ; assign propDstData_0_lat_0$wget = { core_0$dCacheToParent_rqToP_first, 1'd0 } ; assign propDstData_1_lat_0$wget = { core_0$iCacheToParent_rqToP_first, 1'd1 } ; assign enqDst_0_lat_0$wget = { 1'd1, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, - SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1533 } ; + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14, + SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535 } ; assign enqDst_0_lat_0$whas = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 ; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 ; assign propDstIdx_1_1_lat_1$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 && - x__h122858 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 && + x__h122868 ; assign propDstData_1_0_lat_0$wget = { core_0$dCacheToParent_rsToP_first, 1'd0 } ; assign propDstData_1_1_lat_0$wget = { core_0$iCacheToParent_rsToP_first, 1'd1 } ; assign enqDst_1_0_lat_0$wget = { 1'd1, - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830 } ; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1832 } ; assign enqDst_1_0_lat_0$whas = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 ; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 ; assign llc_mem_server_axi4_slave_xactor_slvSynth_awSynth_snk_putWire$wget = { debug_module_mem_server_awid, debug_module_mem_server_awaddr, @@ -4126,10 +4135,10 @@ module mkProc(CLK, !llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ; assign llc_mem_server_propDstIdx_0_lat_1$whas = !llc_mem_server_enqDst_0_rl[65] && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103 ; assign llc_mem_server_enqDst_0_lat_0$wget = { 1'd1, - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 } ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110 } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$wget = { master0_bid, master0_bresp } ; assign llc_axi4_adapter_master_xactor_master_bSynth_snk_putWire$whas = @@ -4161,7 +4170,7 @@ module mkProc(CLK, master0_arready ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = @@ -4234,7 +4243,7 @@ module mkProc(CLK, assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 = { 1'd1, llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[97:93], - dword__h150359, + dword__h150369, 4'd2 } ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read = CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ? @@ -4252,7 +4261,7 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 = - { 6'd32, v_awaddr__h214948, 29'd15532032 } ; + { 6'd32, v_awaddr__h217034, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read = llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ? llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 : @@ -4267,10 +4276,10 @@ module mkProc(CLK, llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 = { 1'd1, - v_wdata__h215359, - v_wstrb__h215360, + v_wdata__h217505, + v_wstrb__h217506, llc_axi4_adapter_rg_wr_req_beat == 3'd7, - v_wuser__h215362 } ; + v_wuser__h217508 } ; assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ? llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 : @@ -4299,7 +4308,7 @@ module mkProc(CLK, 8'd42 : llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 = - { 6'd32, line_addr__h193455, 29'd15532032 } ; + { 6'd32, line_addr__h193465, 29'd15532032 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ? llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 : @@ -4333,11 +4342,11 @@ module mkProc(CLK, assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 = llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 = - b__h193255 - 4'd1 ; + b__h193265 - 4'd1 ; assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read = CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 : - b__h193255 ; + b__h193265 ; // register cfg_verbosity assign cfg_verbosity$D_IN = @@ -4349,7 +4358,7 @@ module mkProc(CLK, // register enqDst_0_rl assign enqDst_0_rl$D_IN = { !CAN_FIRE_RL_doEnq && - IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447, + IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449, CAN_FIRE_RL_doEnq ? 73'h0AAAAAAAAAAAAAAAAAA : (enqDst_0_lat_0$whas ? @@ -4360,8 +4369,8 @@ module mkProc(CLK, // register enqDst_1_0_rl assign enqDst_1_0_rl$D_IN = { !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642, - IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1681 } ; + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644, + IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1683 } ; assign enqDst_1_0_rl$EN = 1'd1 ; // register llc_axi4_adapter_cfg_verbosity @@ -4405,19 +4414,23 @@ module mkProc(CLK, // register llc_axi4_adapter_rg_cline assign llc_axi4_adapter_rg_cline$D_IN = - IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ? + 516'd0 : + IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289 ; assign llc_axi4_adapter_rg_cline$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; // register llc_axi4_adapter_rg_rd_rsp_beat assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN = - llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ? + 3'd0 : + x__h194318 ; assign llc_axi4_adapter_rg_rd_rsp_beat$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ; // register llc_axi4_adapter_rg_wr_req_beat assign llc_axi4_adapter_rg_wr_req_beat$D_IN = - llc_axi4_adapter_rg_wr_req_beat + 3'd1 ; + (llc_axi4_adapter_rg_wr_req_beat == 3'd7) ? 3'd0 : x__h217392 ; assign llc_axi4_adapter_rg_wr_req_beat$EN = CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ; @@ -4454,7 +4467,7 @@ module mkProc(CLK, // register llc_mem_server_enqDst_0_rl assign llc_mem_server_enqDst_0_rl$D_IN = { !CAN_FIRE_RL_llc_mem_server_doEnq && - IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118, + IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120, CAN_FIRE_RL_llc_mem_server_doEnq ? 65'h0AAAAAAAAAAAAAAAA : (llc_mem_server_propDstIdx_0_lat_1$whas ? @@ -4464,20 +4477,20 @@ module mkProc(CLK, // register llc_mem_server_propDstData_0_rl assign llc_mem_server_propDstData_0_rl$D_IN = - IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 ; + IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110 ; assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ; // register llc_mem_server_propDstIdx_0_rl assign llc_mem_server_propDstIdx_0_rl$D_IN = !llc_mem_server_propDstIdx_0_lat_1$whas && - IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 ; + IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103 ; assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ; // register llc_mem_server_rg_cacheline_cache_addr assign llc_mem_server_rg_cacheline_cache_addr$D_IN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ? - line_addr__h140065 : - line_addr__h150176 ; + line_addr__h140075 : + line_addr__h150186 ; assign llc_mem_server_rg_cacheline_cache_addr$EN = WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st || WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ; @@ -4560,7 +4573,7 @@ module mkProc(CLK, MUX_mmioPlatform_curReq$write_1__SEL_1 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_cycle assign mmioPlatform_cycle$D_IN = @@ -4573,11 +4586,11 @@ module mkProc(CLK, // register mmioPlatform_fetchedInsts_0 assign mmioPlatform_fetchedInsts_0$D_IN = - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 ; + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 ; assign mmioPlatform_fetchedInsts_0$EN = WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 && + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 && !mmioPlatform_fetchingWay ; // register mmioPlatform_fetchingWay @@ -4587,11 +4600,11 @@ module mkProc(CLK, assign mmioPlatform_fetchingWay$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_fromHostAddr assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ; @@ -4642,16 +4655,16 @@ module mkProc(CLK, assign mmioPlatform_instSel$EN = WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 ; + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 ; // register mmioPlatform_mtime assign mmioPlatform_mtime$D_IN = MUX_mmioPlatform_amoResp$write_1__SEL_2 ? - newData__h53320 : + newData__h53330 : MUX_mmioPlatform_mtime$write_1__VAL_2 ; assign mmioPlatform_mtime$EN = WILL_FIRE_RL_mmioPlatform_processMTime && @@ -4660,7 +4673,7 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_incTime ; // register mmioPlatform_mtimecmp_0 - assign mmioPlatform_mtimecmp_0$D_IN = newData__h45219 ; + assign mmioPlatform_mtimecmp_0$D_IN = newData__h45229 ; assign mmioPlatform_mtimecmp_0$EN = MUX_mmioPlatform_amoResp$write_1__SEL_1 ; @@ -4670,9 +4683,9 @@ module mkProc(CLK, MUX_mmioPlatform_mtip_0$write_1__VAL_2 ; assign mmioPlatform_mtip_0$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 ; // register mmioPlatform_reqAmofunc assign mmioPlatform_reqAmofunc$D_IN = @@ -4781,7 +4794,7 @@ module mkProc(CLK, mmioPlatform_toHostQ_enqReq_rl[63:0] ; assign mmioPlatform_toHostQ_data_0$EN = !mmioPlatform_toHostQ_clearReq_rl && - IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 ; + IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 ; // register mmioPlatform_toHostQ_deqReq_rl assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ; @@ -4802,7 +4815,7 @@ module mkProc(CLK, // register mmioPlatform_toHostQ_full assign mmioPlatform_toHostQ_full$D_IN = !mmioPlatform_toHostQ_clearReq_rl && - (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 || + (IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 || !(!mmioPlatform_toHostQ_empty) && !mmioPlatform_toHostQ_deqReq_rl && mmioPlatform_toHostQ_full) ; @@ -4815,7 +4828,7 @@ module mkProc(CLK, mmioPlatform_reqBE[0] ; assign mmioPlatform_waitLowerMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 ; // register mmioPlatform_waitMTIPCRs assign mmioPlatform_waitMTIPCRs$D_IN = @@ -4823,15 +4836,15 @@ module mkProc(CLK, MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ; assign mmioPlatform_waitMTIPCRs$EN = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; // register mmioPlatform_waitUpperMSIPCRs assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ; assign mmioPlatform_waitUpperMSIPCRs$EN = WILL_FIRE_RL_mmioPlatform_processMSIP && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 ; // register mmio_axi4_adapter_cfg_verbosity assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ; @@ -4860,7 +4873,7 @@ module mkProc(CLK, !whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && !mmio_axi4_adapter_rg_wr_req_beat && - x__h17610 ; + x__h17619 ; assign mmio_axi4_adapter_rg_wr_req_beat$EN = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr ; @@ -4882,28 +4895,28 @@ module mkProc(CLK, // register propDstData_1_0_rl assign propDstData_1_0_rl$D_IN = - { IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566, - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571, + { IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568, + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573, CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[517] : propDstData_1_0_rl[517], CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516:1] : propDstData_1_0_rl[516:1], - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592 } ; + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594 } ; assign propDstData_1_0_rl$EN = 1'd1 ; // register propDstData_1_1_rl assign propDstData_1_1_rl$D_IN = - { IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604, - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609, + { IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606, + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611, CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[517] : propDstData_1_1_rl[517], CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516:1] : propDstData_1_1_rl[516:1], - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630 } ; + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632 } ; assign propDstData_1_1_rl$EN = 1'd1 ; // register propDstData_1_rl @@ -4915,26 +4928,26 @@ module mkProc(CLK, // register propDstIdx_0_rl assign propDstIdx_0_rl$D_IN = - !NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539 && - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416 ; + !NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541 && + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 ; assign propDstIdx_0_rl$EN = 1'd1 ; // register propDstIdx_1_0_rl assign propDstIdx_1_0_rl$D_IN = - !NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836 && - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549 ; + !NOT_enqDst_1_0_rl_642_BIT_584_643_648_AND_SEL__ETC___d1838 && + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551 ; assign propDstIdx_1_0_rl$EN = 1'd1 ; // register propDstIdx_1_1_rl assign propDstIdx_1_1_rl$D_IN = !propDstIdx_1_1_lat_1$whas && - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 ; + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558 ; assign propDstIdx_1_1_rl$EN = 1'd1 ; // register propDstIdx_1_rl assign propDstIdx_1_rl$D_IN = !propDstIdx_1_lat_1$whas && - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423 ; + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 ; assign propDstIdx_1_rl$EN = 1'd1 ; // register srcRR_0 @@ -4953,8 +4966,8 @@ module mkProc(CLK, assign core_0$coreReq_start_startpc = start_startpc ; assign core_0$coreReq_start_toHostAddr = start_tohostAddr ; assign core_0$dCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq ? - MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1 : + WILL_FIRE_RL_sendPRs ? + MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; assign core_0$hart0_csr_mem_server_request_put = hart0_csr_mem_server_request_put ; @@ -4965,8 +4978,8 @@ module mkProc(CLK, assign core_0$hart0_run_halt_server_request_put = hart0_run_halt_server_request_put ; assign core_0$iCacheToParent_fromP_enq_x = - WILL_FIRE_RL_sendPRq_1 ? - MUX_core_0$iCacheToParent_fromP_enq_1__VAL_1 : + WILL_FIRE_RL_sendPRs_1 ? + MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 : MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ; always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 or @@ -5002,9 +5015,9 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 or MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6 or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7 or + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or WILL_FIRE_RL_mmioPlatform_waitMSIPDone or MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or @@ -5029,10 +5042,10 @@ module mkProc(CLK, MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5; - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: + MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_6: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6; - MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_7: + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp: core_0$mmioToPlatform_pRs_enq_x = MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7; WILL_FIRE_RL_mmioPlatform_waitMSIPDone: @@ -5053,7 +5066,7 @@ module mkProc(CLK, assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ; assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ; assign core_0$tlbToMem_respLd_enq_x = - { ld_data__h188181, llc$dma_respLd_first[3] } ; + { ld_data__h188191, llc$dma_respLd_first[3] } ; assign core_0$EN_coreReq_start = EN_start ; assign core_0$EN_coreReq_perfReq = 1'b0 ; assign core_0$EN_coreIndInv_perfResp = 1'b0 ; @@ -5061,11 +5074,11 @@ module mkProc(CLK, assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ; assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ; assign core_0$EN_dCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ; + WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ; assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ; assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ; assign core_0$EN_iCacheToParent_fromP_enq = - WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ; + WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ; assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_llc_mem_server_srcPropose ; assign core_0$EN_tlbToMem_respLd_enq = @@ -5076,31 +5089,31 @@ module mkProc(CLK, WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp && !mmioPlatform_amoWaitWriteResp || WILL_FIRE_RL_mmioPlatform_processMSIP && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 || WILL_FIRE_RL_mmioPlatform_processMTime && - mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 || + mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 || WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && - (!mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 || + (!mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 || !mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) || - WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone || + WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp || WILL_FIRE_RL_mmioPlatform_waitMSIPDone || WILL_FIRE_RL_mmioPlatform_processToHost || WILL_FIRE_RL_mmioPlatform_processFromHost ; assign core_0$EN_mmioToPlatform_pRq_enq = WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || WILL_FIRE_RL_mmioPlatform_processMSIP && mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0] || WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 || + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 || WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 ; + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 ; assign core_0$EN_mmioToPlatform_cRs_deq = (WILL_FIRE_RL_mmioPlatform_waitMTimeDone || WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) && @@ -5182,13 +5195,13 @@ module mkProc(CLK, enqDst_0_lat_0$wget[72:0] : enqDst_0_rl[72:0] ; assign llc$to_child_rsFromC_enq_x = - { IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 } ; + { IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680 } ; assign llc$to_mem_rsFromM_enq_x = - { IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287, + { IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289, llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ; assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ; assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ; @@ -5215,7 +5228,7 @@ module mkProc(CLK, WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc$EN_to_mem_rsFromM_enq = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ; assign llc$EN_cRqStuck_get = 1'b0 ; assign llc$EN_perf_setStatus = core_0$RDY_sendDoStats ; assign llc$EN_perf_req = 1'b0 ; @@ -5227,7 +5240,7 @@ module mkProc(CLK, CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ; assign llc_axi4_adapter_f_pending_reads$DEQ = WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ; + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] ; assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ; // submodule llc_mem_server_f_dword_in_line @@ -5342,7 +5355,7 @@ module mkProc(CLK, 18'd65536 } ; assign mmio_axi4_adapter_master_shim_awff$ENQ = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && - mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 ; + mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 ; assign mmio_axi4_adapter_master_shim_awff$DEQ = EN_master1_aw_drop ; assign mmio_axi4_adapter_master_shim_awff$CLR = 1'b0 ; @@ -5362,8 +5375,8 @@ module mkProc(CLK, // submodule mmio_axi4_adapter_master_shim_wff assign mmio_axi4_adapter_master_shim_wff$D_IN = - { wflit_wdata__h17678, - wflit_wstrb__h17679, + { wflit_wdata__h17687, + wflit_wstrb__h17688, whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || mmio_axi4_adapter_rg_wr_req_beat, @@ -5381,41 +5394,41 @@ module mkProc(CLK, assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ; // remaining internal signals - module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current({ 65'd0, - value__h61538 }), + value__h61548 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d920)); - module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d922)); + module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current({ 65'd0, - mmioPlatform_mtime__h59831 }), + mmioPlatform_mtime__h59841 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1006)); - module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1008)); + module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), .amoExec_current(129'd0), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1076)); - module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1078)); + module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912), .amoExec_wordIdx({ 1'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - !IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] }), - .amoExec_current({ 65'd0, x__h79161 }), + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + !IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] }), + .amoExec_current({ 65'd0, x__h79171 }), .amoExec_inpt({ 65'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 }), - .amoExec(amoExec___d1129)); - module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88303, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 }), + .amoExec(amoExec___d1131)); + module_amoExec instance_amoExec_4(.amoExec_amo_inst({ mmioPlatform_reqAmofunc__h88313, ((mmioPlatform_reqBE[0] ? 5'd1 : 5'd0) + @@ -5471,294 +5484,294 @@ module mkProc(CLK, .amoExec_wordIdx(mmioPlatform_curReq[3:2]), .amoExec_current(mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0]), .amoExec_inpt(mmioPlatform_reqData), - .amoExec(amoExec___d1354)); - assign IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962 = - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + .amoExec(amoExec___d1356)); + assign IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964 = + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_mtime[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_mtime[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_mtime[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_mtime[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1017, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1019, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_mtime[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_mtime[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1140 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1142 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_fromHostQ_data_0[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_fromHostQ_data_0[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_fromHostQ_data_0[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_fromHostQ_data_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1145 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1140, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1147 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1142, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_fromHostQ_data_0[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_fromHostQ_data_0[23:16] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : mmioPlatform_mtimecmp_0[63:56], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : mmioPlatform_mtimecmp_0[55:48], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : mmioPlatform_mtimecmp_0[47:40], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : mmioPlatform_mtimecmp_0[39:32] } ; - assign IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d938, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + assign IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d940, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : mmioPlatform_mtimecmp_0[31:24], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : mmioPlatform_mtimecmp_0[23:16] } ; - assign IF_NOT_core_0_mmioToPlatform_cRq_first__21_BIT_ETC___d546 = - (!core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) ? + assign IF_NOT_core_0_mmioToPlatform_cRq_first__23_BIT_ETC___d548 = + (!core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) ? 67'h3AAAAAAAAAAAAAAAA : ((core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575) ? 67'h4AAAAAAAAAAAAAAAA : - IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544) ; - assign IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818 = + IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546) ; + assign IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820 = (mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? (mmioPlatform_reqBE[0] ? core_0$RDY_mmioToPlatform_pRq_enq : core_0$RDY_mmioToPlatform_pRs_enq) : !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ; - assign IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 = - newData__h45219 <= mmioPlatform_mtime ; - assign IF_core_0_mmioToPlatform_cRq_first__21_BITS_21_ETC___d544 = - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 ? + assign IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 = + newData__h45229 <= mmioPlatform_mtime ; + assign IF_core_0_mmioToPlatform_cRq_first__23_BITS_21_ETC___d546 = + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 ? 67'h5AAAAAAAAAAAAAAAA : - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ? + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ? 67'h6AAAAAAAAAAAAAAAA : { 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ; - assign IF_enqDst_0_lat_0_whas__442_THEN_enqDst_0_lat__ETC___d1447 = + assign IF_enqDst_0_lat_0_whas__444_THEN_enqDst_0_lat__ETC___d1449 = enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1642 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1644 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[584] : enqDst_1_0_rl[584] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[583:520] : enqDst_1_0_rl[583:520] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[519:518] : enqDst_1_0_rl[519:518] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[517] : enqDst_1_0_rl[517] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[516:1] : enqDst_1_0_rl[516:1] ; - assign IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 = + assign IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680 = enqDst_1_0_lat_0$whas ? enqDst_1_0_lat_0$wget[0] : enqDst_1_0_rl[0] ; - assign IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680 = + assign IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1682 = { CAN_FIRE_RL_doEnq_1 || - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1662, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1664, CAN_FIRE_RL_doEnq_1 ? 516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 : - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1672, - x__h116294 } ; - assign IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1681 = + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1674, + x__h116304 } ; + assign IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1683 = { CAN_FIRE_RL_doEnq_1 ? 64'hAAAAAAAAAAAAAAAA : - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1652, + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1654, CAN_FIRE_RL_doEnq_1 ? 2'b10 : - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1657, - IF_enqDst_1_0_lat_1_whas__634_THEN_enqDst_1_0__ETC___d1680 } ; - assign IF_llc_axi4_adapter_rg_rd_rsp_beat_245_BIT_0_2_ETC___d2287 = + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1659, + IF_enqDst_1_0_lat_1_whas__636_THEN_enqDst_1_0__ETC___d1682 } ; + assign IF_llc_axi4_adapter_rg_rd_rsp_beat_257_BIT_0_2_ETC___d2289 = { llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515:512] : { llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], llc_axi4_adapter_rg_cline[515:513] }, llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4], llc_axi4_adapter_rg_cline[511:64] } ; - assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2019 = + assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d2021 = { (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd7) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[511:448], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd6) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[447:384], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd5) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[383:320], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd4) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[319:256], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd3) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[255:192], (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] == 3'd2) ? - data__h140632 : + data__h140642 : llc_mem_server_rg_cacheline_cache_data[191:128] } ; - assign IF_llc_mem_server_enqDst_0_lat_0_whas__113_THE_ETC___d2118 = + assign IF_llc_mem_server_enqDst_0_lat_0_whas__115_THE_ETC___d2120 = llc_mem_server_propDstIdx_0_lat_1$whas ? llc_mem_server_enqDst_0_lat_0$wget[65] : llc_mem_server_enqDst_0_rl[65] ; - assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2108 = + assign IF_llc_mem_server_propDstData_0_lat_0_whas__10_ETC___d2110 = CAN_FIRE_RL_llc_mem_server_srcPropose ? core_0$tlbToMem_memReq_first : llc_mem_server_propDstData_0_rl ; - assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__098_ETC___d2101 = + assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__100_ETC___d2103 = CAN_FIRE_RL_llc_mem_server_srcPropose || llc_mem_server_propDstIdx_0_rl ; - assign IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389 = + assign IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391 = mmioPlatform_fetchingWay ? mmioPlatform_fetchedInsts_0 : - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 ; - assign IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 ; + assign IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161 = (mmioPlatform_fromHostQ_empty || mmioPlatform_fromHostAddr[0]) ? 64'd0 : mmioPlatform_fromHostQ_data_0 ; - assign IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157 = + assign IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159 = mmioPlatform_fromHostQ_empty ? 64'd0 : (mmioPlatform_fromHostAddr[0] ? mmioPlatform_fromHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038 = - ((mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + assign IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040 = + ((mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0) ? core_0$RDY_mmioToPlatform_pRq_enq : - mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRq_enq) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0 || core_0$RDY_mmioToPlatform_pRs_enq) ; - assign IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905 = + assign IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 8'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqBE[15:8] : mmioPlatform_reqBE[7:0]) ; - assign IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918 = + assign IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920 = (mmioPlatform_reqBE[7:0] == 8'd0 && mmioPlatform_reqBE[15:8] == 8'd0) ? 64'd0 : ((mmioPlatform_reqBE[7:0] == 8'd0) ? mmioPlatform_reqData[127:64] : mmioPlatform_reqData[63:0]) ; - assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 = + assign IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}}, mmioPlatform_mtime_BITS_63_TO_32__q7 } : { {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}}, mmioPlatform_mtime_BITS_31_TO_0__q8 } ; - assign IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 = + assign IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 = mmioPlatform_reqBE[4] ? { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}}, mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } : { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}}, mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1111 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1113 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100, + { IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102, 1'd0, - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d1164 = + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108 } ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d1166 = (mmioPlatform_reqFunc[5:4] == 2'd0) ? 130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA : - { IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154, + { IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156, 1'd0, - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159 } ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d819 = + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161 } ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d821 = (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ? core_0$RDY_mmioToPlatform_pRs_enq : - IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d818 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d1055 = + IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d820 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d1057 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtime : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d1054 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_1_ETC___d982 = + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d1056 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_1_ETC___d984 = (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? mmioPlatform_mtimecmp_0 : - IF_mmioPlatform_reqBE_05_BIT_4_06_THEN_SEXT_mm_ETC___d981 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100 = + IF_mmioPlatform_reqBE_07_BIT_4_08_THEN_SEXT_mm_ETC___d983 ; + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? mmioPlatform_toHostQ_empty : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h73614 == 64'd0 : - x__h68445 == 64'd0) : + x__h73624 == 64'd0 : + x__h68455 == 64'd0) : mmioPlatform_reqFunc[5:4] == 2'd1 ; - assign IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1171 = + assign IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1173 = (mmioPlatform_reqFunc[5:4] == 2'd2) ? (mmioPlatform_fromHostQ_empty ? - x__h73614 != 64'd0 : - x__h68445 != 64'd0) : + x__h73624 != 64'd0 : + x__h68455 != 64'd0) : mmioPlatform_reqFunc[5:4] != 2'd1 ; - assign IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106 = + assign IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108 = (mmioPlatform_toHostQ_empty || mmioPlatform_toHostAddr[0]) ? 64'd0 : mmioPlatform_toHostQ_data_0 ; - assign IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104 = + assign IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106 = mmioPlatform_toHostQ_empty ? 64'd0 : (mmioPlatform_toHostAddr[0] ? mmioPlatform_toHostQ_data_0 : 64'd0) ; - assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__58__ETC___d367 = + assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__60__ETC___d369 = mmioPlatform_toHostQ_enqReq_lat_0$whas ? mmioPlatform_toHostQ_enqReq_lat_0$wget[64] : mmioPlatform_toHostQ_enqReq_rl[64] ; - assign IF_mmioPlatform_waitLowerMSIPCRs_75_THEN_core__ETC___d883 = + assign IF_mmioPlatform_waitLowerMSIPCRs_77_THEN_core__ETC___d885 = mmioPlatform_waitLowerMSIPCRs ? core_0$RDY_mmioToPlatform_cRs_first && core_0$RDY_mmioToPlatform_cRs_deq : @@ -5766,82 +5779,85 @@ module mkProc(CLK, core_0$RDY_mmioToPlatform_cRs_first) && (!mmioPlatform_waitUpperMSIPCRs || core_0$RDY_mmioToPlatform_cRs_deq) ; - assign IF_mmio_axi4_adapter_f_rsps_to_core_first__291_ETC___d1367 = + assign IF_mmio_axi4_adapter_f_rsps_to_core_first__293_ETC___d1369 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? mmioPlatform_fetchingWay < (mmioPlatform_reqFunc[5:4] == 2'd0 && mmioPlatform_reqFunc[0]) || core_0$RDY_mmioToPlatform_pRs_enq : core_0$RDY_mmioToPlatform_pRs_enq ; - assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d206 = + assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d210 = mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_wff$FULL_N && - (!whichHalf___1__h15055 && - mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && - mmio_axi4_adapter_rg_wr_req_beat || - mmio_axi4_adapter_master_shim_awff$FULL_N) : + NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208 : mmio_axi4_adapter_f_rsps_to_core$FULL_N ; - assign IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566 = + assign IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[583:520] : propDstData_1_0_rl[583:520] ; - assign IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571 = + assign IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[519:518] : propDstData_1_0_rl[519:518] ; - assign IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592 = + assign IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[0] : propDstData_1_0_rl[0] ; - assign IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604 = + assign IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[583:520] : propDstData_1_1_rl[583:520] ; - assign IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609 = + assign IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[519:518] : propDstData_1_1_rl[519:518] ; - assign IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630 = + assign IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[0] : propDstData_1_1_rl[0] ; - assign IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479 = + assign IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 = !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ; - assign IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416 = + assign IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 = CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 = + assign IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714 = !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549 = + assign IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551 = CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ; - assign IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 = + assign IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558 = CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ; - assign IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423 = + assign IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 = CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ; - assign NOT_enqDst_0_rl_445_BIT_73_446_451_AND_SEL_ARR_ETC___d1539 = + assign NOT_enqDst_0_rl_447_BIT_73_448_453_AND_SEL_ARR_ETC___d1541 = !enqDst_0_rl[73] && - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 && - (SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 ? + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 && + (SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 ? !srcRR_0 : - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416) ; - assign NOT_enqDst_1_0_rl_640_BIT_584_641_646_AND_SEL__ETC___d1836 = + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418) ; + assign NOT_enqDst_1_0_rl_642_BIT_584_643_648_AND_SEL__ETC___d1838 = !enqDst_1_0_rl[584] && - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 && - (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 ? + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 && + (SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 ? !srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 = + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551) ; + assign NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 = llc_axi4_adapter_cfg_verbosity > 4'd1 ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2320 = - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2323 = + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? !llc_axi4_adapter_rg_cline[515] : !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2323 = - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + assign NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2326 = + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && (llc_axi4_adapter_rg_rd_rsp_beat[0] ? llc_axi4_adapter_rg_cline[515] : llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1194 = + assign NOT_llc_axi4_adapter_rg_wr_req_beat_345_EQ_0_3_ETC___d2359 = + (llc_axi4_adapter_rg_wr_req_beat != 3'd0 || + llc_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 && + !llc_axi4_adapter_master_xactor_shim_awff_rv[98]) && + (llc_axi4_adapter_rg_wr_req_beat != 3'd7 || + llc$RDY_to_mem_toM_deq) ; + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1196 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5852,7 +5868,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd2 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1289 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1291 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5863,7 +5879,7 @@ module mkProc(CLK, mmioPlatform_state == 2'd3 && (mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1300 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1302 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5875,7 +5891,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1310 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1312 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5887,7 +5903,7 @@ module mkProc(CLK, mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1358 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1360 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5897,7 +5913,7 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd2 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_curReq_97_BITS_66_TO_64_98_EQ_ETC___d1370 = + assign NOT_mmioPlatform_curReq_99_BITS_66_TO_64_00_EQ_ETC___d1372 = mmioPlatform_curReq[66:64] != 3'd0 && mmioPlatform_curReq[66:64] != 3'd1 && mmioPlatform_curReq[66:64] != 3'd2 && @@ -5907,90 +5923,96 @@ module mkProc(CLK, mmioPlatform_curReq[66:64] != 3'd6 && mmioPlatform_state == 2'd3 && mmioPlatform_reqFunc[5:4] == 2'd0 ; - assign NOT_mmioPlatform_mtip_0_98_05_AND_mmioPlatform_ETC___d513 = + assign NOT_mmioPlatform_mtip_0_00_07_AND_mmioPlatform_ETC___d515 = !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 || + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 || !core_0$mmioToPlatform_cRq_notEmpty || core_0$RDY_mmioToPlatform_cRq_first && core_0$RDY_mmioToPlatform_cRq_deq ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1061 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1063 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && !mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 && + !mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (!mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d871 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d873 = mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] && (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 || mmioPlatform_reqFunc[5:4] == 2'd2) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d989 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d991 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && !mmioPlatform_mtip_0 || - !IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 && + !IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 && mmioPlatform_mtip_0) ; - assign NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993 = + assign NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995 = mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && - (!IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (!IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || !mmioPlatform_mtip_0) ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1532 = - { CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, - x__h100956, - x__h100957 } ; - assign SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1533 = - { CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, - SEL_ARR_IF_propDstData_0_lat_0_whas__427_THEN__ETC___d1532 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1748 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1773 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1790 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1773, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1790, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1824 = - { CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825 = - { SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1748, - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1807, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1824 } ; - assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1830 = - { CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, - !CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, - SEL_ARR_IF_propDstData_1_0_lat_0_whas__561_THE_ETC___d1825, - x__h127593 } ; - assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1481 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 || - (IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479 ? - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423 : - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416) ; - assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1714 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 || - (IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 ? - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556 : - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549) ; + assign NOT_mmio_axi4_adapter_f_reqs_from_core_first_B_ETC___d208 = + !whichHalf___1__h15055 && + mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0 && + mmio_axi4_adapter_rg_wr_req_beat || + mmio_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 && + mmio_axi4_adapter_master_shim_awff$FULL_N ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534 = + { CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11, + x__h100966, + x__h100967 } ; + assign SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1535 = + { CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12, + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13, + SEL_ARR_IF_propDstData_0_lat_0_whas__429_THEN__ETC___d1534 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1750 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1775 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1792 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1809 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1775, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1792, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1826 = + { CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1827 = + { SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1750, + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1809, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1826 } ; + assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1832 = + { CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27, + !CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28, + SEL_ARR_IF_propDstData_1_0_lat_0_whas__563_THE_ETC___d1827, + x__h127603 } ; + assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1483 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 || + (IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 ? + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425 : + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418) ; + assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1716 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 || + (IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714 ? + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558 : + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551) ; assign _dand1mmio_axi4_adapter_f_reqs_from_core$EN_deq = WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && (whichHalf___1__h15055 || @@ -6004,8 +6026,8 @@ module mkProc(CLK, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0) ? whichHalf___1__h15055 : mmio_axi4_adapter_rg_wr_req_beat ; - assign addr1__h90533 = { mmioPlatform_curReq[63:3], 3'b0 } ; - assign amo_req_data__h39114 = + assign addr1__h90543 = { mmioPlatform_curReq[63:3], 3'b0 } ; + assign amo_req_data__h39124 = (mmioPlatform_reqBE[3:0] == 4'd0 && mmioPlatform_reqBE[7:4] == 4'd0 && mmioPlatform_reqBE[11:8] == 4'd0 && @@ -6021,7 +6043,7 @@ module mkProc(CLK, ((mmioPlatform_reqBE[3:0] == 4'd0) ? mmioPlatform_reqData[63:32] : mmioPlatform_reqData[31:0]))) ; - assign b__h193255 = + assign b__h193265 = llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : llc_axi4_adapter_ctr_wr_rsps_pending_crg ; @@ -6029,205 +6051,236 @@ module mkProc(CLK, mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ? mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 : mmio_axi4_adapter_ctr_wr_rsps_pending_crg ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554432 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556480 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532 = core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_toHostAddr ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 = + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 = core_0$mmioToPlatform_cRq_first[214:154] == mmioPlatform_fromHostAddr ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] == 61'd33560575 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 ; + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ; - assign core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788 = - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530) && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ; + assign core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532) && core_0$mmioToPlatform_cRq_first[214:154] != 61'd33560575 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d536 && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d539 ; - assign core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764 = + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d538 && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d541 ; + assign core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766 = core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d528 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d530 ; - assign data__h140632 = + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d530 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d532 ; + assign data__h140642 = { llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[63:56], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[63:56], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[55:48], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[55:48], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[47:40], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[47:40], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[39:32], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[39:32], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[31:24], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[31:24], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[23:16], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[23:16], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[15:8], + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[15:8], llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ? llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] : - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971[7:0] } ; - assign failed_testnum__h223734 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973[7:0] } ; + assign failed_testnum__h225871 = { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ; - assign line_addr__h140065 = + assign line_addr__h140075 = { llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h150176 = + assign line_addr__h150186 = { llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35], 6'b0 } ; - assign line_addr__h193455 = { llc$to_mem_toM_first[68:11], 6'h0 } ; + assign line_addr__h193465 = { llc$to_mem_toM_first[68:11], 6'h0 } ; assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q34 = llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ; assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q32 = llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ; - assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2252 = - llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] && - (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 || - llc$RDY_to_mem_rsFromM_enq && - llc_axi4_adapter_f_pending_reads$EMPTY_N) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2301 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[512] : + !llc_axi4_adapter_rg_cline[513]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2304 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[512] : + llc_axi4_adapter_rg_cline[513]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2309 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[513] : + !llc_axi4_adapter_rg_cline[514]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2312 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[513] : + llc_axi4_adapter_rg_cline[514]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2317 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + !llc_axi4_adapter_rg_cline[514] : + !llc_axi4_adapter_rg_cline[515]) ; + assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d2320 = + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && + (llc_axi4_adapter_rg_rd_rsp_beat[0] ? + llc_axi4_adapter_rg_cline[514] : + llc_axi4_adapter_rg_cline[515]) ; assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q33 = llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ; - assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2037 = - line_addr__h150176 == llc_mem_server_rg_cacheline_cache_addr ; - assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1936 = - line_addr__h140065 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d2039 = + line_addr__h150186 == llc_mem_server_rg_cacheline_cache_addr ; + assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1938 = + line_addr__h140075 == llc_mem_server_rg_cacheline_cache_addr ; assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q30 = llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ; assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q31 = llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ; - assign lower_data__h44520 = - mmioPlatform_waitLowerMSIPCRs ? v__h44413 : 32'd0 ; + assign lower_data__h44530 = + mmioPlatform_waitLowerMSIPCRs ? v__h44423 : 32'd0 ; assign mem_req_rd_addr_arlen__h5411 = (!whichHalf___1__h15055 && mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] != 8'd0) ? 8'd1 : 8'd0 ; - assign mmioPlatform_amoWaitWriteResp_304_OR_core_0_RD_ETC___d1307 = + assign mmioPlatform_amoWaitWriteResp_306_OR_core_0_RD_ETC___d1309 = mmioPlatform_amoWaitWriteResp || core_0$RDY_mmioToPlatform_pRs_enq && (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmio_axi4_adapter_f_reqs_from_core$FULL_N) ; - assign mmioPlatform_cycle_90_ULT_99___d491 = mmioPlatform_cycle < 7'd99 ; - assign mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372 = + assign mmioPlatform_cycle_92_ULT_99___d493 = mmioPlatform_cycle < 7'd99 ; + assign mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374 = mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ; assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ; assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ; - assign mmioPlatform_mtime__h59831 = mmioPlatform_mtime ; - assign mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 = - mmioPlatform_mtimecmp_0 <= newData__h53320 ; - assign mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500 = + assign mmioPlatform_mtime__h59841 = mmioPlatform_mtime ; + assign mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 = + mmioPlatform_mtimecmp_0 <= newData__h53330 ; + assign mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502 = mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ; assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 = mmioPlatform_mtimecmp_0[31:0] ; assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 = mmioPlatform_mtimecmp_0[63:32] ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd0 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd1 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd2 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd3 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd4 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd5 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd6 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd7 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd2 && core_0$mmioToPlatform_cRq_first[148:145] == 4'd8 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -6241,45 +6294,45 @@ module mkProc(CLK, core_0$mmioToPlatform_cRq_first[148:145] != 4'd6 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd7 && core_0$mmioToPlatform_cRq_first[148:145] != 4'd8 ; - assign mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760 = + assign mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762 = (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525 ; - assign mmioPlatform_reqAmofunc__h88303 = mmioPlatform_reqAmofunc ; - assign mmioPlatform_reqFunc_02_BITS_3_TO_0_42_CONCAT__ETC___d910 = + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527 ; + assign mmioPlatform_reqAmofunc__h88313 = mmioPlatform_reqAmofunc ; + assign mmioPlatform_reqFunc_04_BITS_3_TO_0_44_CONCAT__ETC___d912 = { mmioPlatform_reqFunc[3:0], - (IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] && - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0]) ? + (IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] && + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0]) ? 2'd1 : 2'd2, 2'd0 } ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d1049 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d1051 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (!mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || mmioPlatform_mtip_0) && - (mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioPlat_ETC___d1029 || + (mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioPlat_ETC___d1031 || !mmioPlatform_mtip_0) ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d829 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d831 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] || mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2 && !mmioPlatform_reqBE[0] ; - assign mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_04_ETC___d974 = + assign mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_06_ETC___d976 = mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqFunc[5:4] == 2'd1 || - (!IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (!IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || mmioPlatform_mtip_0) && - (IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03__ETC___d957 || + (IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05__ETC___d959 || !mmioPlatform_mtip_0) ; - assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257 = (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && mmio_axi4_adapter_cfg_verbosity != 4'd0 ; - assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259 = + assign mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261 = (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) && @@ -6289,14 +6342,14 @@ module mkProc(CLK, (mmio_axi4_adapter_soc_map$m_is_IO_addr ? mmio_axi4_adapter_master_shim_arff$FULL_N : mmio_axi4_adapter_f_rsps_to_core$FULL_N) ; - assign mmio_axi4_adapter_f_rsps_to_core_first__291_BI_ETC___d1392 = + assign mmio_axi4_adapter_f_rsps_to_core_first__293_BI_ETC___d1394 = { mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && mmioPlatform_fetchingWay, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384, + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] || mmioPlatform_fetchingWay, mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ? - IF_mmioPlatform_fetchingWay_363_THEN_mmioPlatf_ETC___d1389 : + IF_mmioPlatform_fetchingWay_365_THEN_mmioPlatf_ETC___d1391 : mmioPlatform_fetchedInsts_0 } ; assign mmio_axi4_adapter_read_req_addr_79_BIT_3_80_PL_ETC___d181 = mmio_axi4_adapter_read_req_addr[3] + @@ -6308,43 +6361,43 @@ module mkProc(CLK, mmio_axi4_adapter_rspData[63:0] } : { mmio_axi4_adapter_rspData[127:64], mmio_axi4_adapter_master_shim_rff$D_OUT[67:4] } } ; - assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d217 = + assign mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ax_ETC___d221 = mmio_axi4_adapter_soc_map$m_is_IO_addr && (whichHalf___1__h15055 || mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137] == 8'd0 || !mmio_axi4_adapter_rg_wr_req_beat) ; - assign newData__h45219 = + assign newData__h45229 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d920[63:0] : - x__h48532 ; - assign newData__h53320 = + amoExec___d922[63:0] : + x__h48542 ; + assign newData__h53330 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1006[63:0] : - x__h56610 ; - assign upper_data__h44521 = - mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44376 ; - assign v__h44376 = mmioPlatform_waitUpperMSIPCRs ? v__h44413 : 32'd0 ; - assign v__h44413 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; - assign v_awaddr__h214948 = { llc$to_mem_toM_first[643:586], 6'h0 } ; - assign value__h61538 = mmioPlatform_mtimecmp_0 ; + amoExec___d1008[63:0] : + x__h56620 ; + assign upper_data__h44531 = + mmioPlatform_waitLowerMSIPCRs ? 32'd0 : v__h44386 ; + assign v__h44386 = mmioPlatform_waitUpperMSIPCRs ? v__h44423 : 32'd0 ; + assign v__h44423 = { 31'd0, core_0$mmioToPlatform_cRs_first } ; + assign v_awaddr__h217034 = { llc$to_mem_toM_first[643:586], 6'h0 } ; + assign value__h61548 = mmioPlatform_mtimecmp_0 ; assign whichHalf___1__h15055 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129] == 8'd0 ; - assign x__h100756 = - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 ? + assign x__h100766 = + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 ? srcRR_0 : - IF_propDstIdx_0_lat_0_whas__413_THEN_NOT_propD_ETC___d1479 ; + IF_propDstIdx_0_lat_0_whas__415_THEN_NOT_propD_ETC___d1481 ; assign x__h10399 = mmio_axi4_adapter_rg_rd_rsp_beat + 1'd1 ; - assign x__h116294 = + assign x__h116304 = !CAN_FIRE_RL_doEnq_1 && - IF_enqDst_1_0_lat_0_whas__637_THEN_enqDst_1_0__ETC___d1678 ; - assign x__h122858 = - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 ? + IF_enqDst_1_0_lat_0_whas__639_THEN_enqDst_1_0__ETC___d1680 ; + assign x__h122868 = + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 ? srcRR_1_0 : - IF_propDstIdx_1_0_lat_0_whas__546_THEN_NOT_pro_ETC___d1712 ; + IF_propDstIdx_1_0_lat_0_whas__548_THEN_NOT_pro_ETC___d1714 ; assign x__h15143 = x__h15155 + y__h15156 ; assign x__h15155 = x__h15167 + y__h15168 ; assign x__h15167 = x__h15179 + y__h15180 ; @@ -6360,70 +6413,72 @@ module mkProc(CLK, assign x__h15287 = x__h15299 + y__h15300 ; assign x__h15299 = x__h15311 + y__h15312 ; assign x__h15311 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[144] } ; - assign x__h17610 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; - assign x__h48532 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d947, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + assign x__h17619 = mmio_axi4_adapter_rg_wr_req_beat + 1'd1 ; + assign x__h194318 = llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ; + assign x__h217392 = llc_axi4_adapter_rg_wr_req_beat + 3'd1 ; + assign x__h48542 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d949, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_mtimecmp_0[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_mtimecmp_0[7:0] } ; - assign x__h56610 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1022, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + assign x__h56620 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1024, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_mtime[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_mtime[7:0] } ; - assign x__h64490 = - { IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[7] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[63:56] : + assign x__h64500 = + { IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[7] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[63:56] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[6] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[55:48] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[6] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[55:48] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[5] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[47:40] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[5] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[47:40] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[4] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[39:32] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[4] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[39:32] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[3] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[31:24] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[3] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[31:24] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[2] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[23:16] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[2] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[23:16] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : 8'd0, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : 8'd0 } ; - assign x__h68445 = + assign x__h68455 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1129[63:0] : - x__h71119 ; - assign x__h71119 = - { IF_IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ__ETC___d1145, - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[1] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[15:8] : + amoExec___d1131[63:0] : + x__h71129 ; + assign x__h71129 = + { IF_IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ__ETC___d1147, + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[1] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[15:8] : mmioPlatform_fromHostQ_data_0[15:8], - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d905[0] ? - IF_mmioPlatform_reqBE_05_BITS_7_TO_0_99_EQ_0_0_ETC___d918[7:0] : + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d907[0] ? + IF_mmioPlatform_reqBE_07_BITS_7_TO_0_01_EQ_0_0_ETC___d920[7:0] : mmioPlatform_fromHostQ_data_0[7:0] } ; - assign x__h73614 = + assign x__h73624 = (mmioPlatform_reqFunc[5:4] != 2'd0 && mmioPlatform_reqFunc[5:4] != 2'd1 && mmioPlatform_reqFunc[5:4] != 2'd2) ? - amoExec___d1076[63:0] : - x__h64490 ; - assign x__h79161 = mmioPlatform_fromHostQ_data_0 ; - assign x_data__h42055 = { 31'd0, mmioPlatform_reqData[0] } ; + amoExec___d1078[63:0] : + x__h64500 ; + assign x__h79171 = mmioPlatform_fromHostQ_data_0 ; + assign x_data__h42065 = { 31'd0, mmioPlatform_reqData[0] } ; assign y__h15144 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[129] } ; assign y__h15156 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[130] } ; assign y__h15168 = { 4'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[131] } ; @@ -6442,14 +6497,14 @@ module mkProc(CLK, always@(llc$dma_respLd_first) begin case (llc$dma_respLd_first[2:0]) - 3'd0: ld_data__h188181 = llc$dma_respLd_first[68:5]; - 3'd1: ld_data__h188181 = llc$dma_respLd_first[132:69]; - 3'd2: ld_data__h188181 = llc$dma_respLd_first[196:133]; - 3'd3: ld_data__h188181 = llc$dma_respLd_first[260:197]; - 3'd4: ld_data__h188181 = llc$dma_respLd_first[324:261]; - 3'd5: ld_data__h188181 = llc$dma_respLd_first[388:325]; - 3'd6: ld_data__h188181 = llc$dma_respLd_first[452:389]; - 3'd7: ld_data__h188181 = llc$dma_respLd_first[516:453]; + 3'd0: ld_data__h188191 = llc$dma_respLd_first[68:5]; + 3'd1: ld_data__h188191 = llc$dma_respLd_first[132:69]; + 3'd2: ld_data__h188191 = llc$dma_respLd_first[196:133]; + 3'd3: ld_data__h188191 = llc$dma_respLd_first[260:197]; + 3'd4: ld_data__h188191 = llc$dma_respLd_first[324:261]; + 3'd5: ld_data__h188191 = llc$dma_respLd_first[388:325]; + 3'd6: ld_data__h188191 = llc$dma_respLd_first[452:389]; + 3'd7: ld_data__h188191 = llc$dma_respLd_first[516:453]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) @@ -6504,40 +6559,40 @@ module mkProc(CLK, begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) 2'd0: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1; 2'd1: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2; 2'd2: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3; 2'd3: - v_wdata__h215359 = + v_wdata__h217505 = CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat) - 3'd0: v_wstrb__h215360 = llc$to_mem_toM_first[523:516]; - 3'd1: v_wstrb__h215360 = llc$to_mem_toM_first[531:524]; - 3'd2: v_wstrb__h215360 = llc$to_mem_toM_first[539:532]; - 3'd3: v_wstrb__h215360 = llc$to_mem_toM_first[547:540]; - 3'd4: v_wstrb__h215360 = llc$to_mem_toM_first[555:548]; - 3'd5: v_wstrb__h215360 = llc$to_mem_toM_first[563:556]; - 3'd6: v_wstrb__h215360 = llc$to_mem_toM_first[571:564]; - 3'd7: v_wstrb__h215360 = llc$to_mem_toM_first[579:572]; + 3'd0: v_wstrb__h217506 = llc$to_mem_toM_first[523:516]; + 3'd1: v_wstrb__h217506 = llc$to_mem_toM_first[531:524]; + 3'd2: v_wstrb__h217506 = llc$to_mem_toM_first[539:532]; + 3'd3: v_wstrb__h217506 = llc$to_mem_toM_first[547:540]; + 3'd4: v_wstrb__h217506 = llc$to_mem_toM_first[555:548]; + 3'd5: v_wstrb__h217506 = llc$to_mem_toM_first[563:556]; + 3'd6: v_wstrb__h217506 = llc$to_mem_toM_first[571:564]; + 3'd7: v_wstrb__h217506 = llc$to_mem_toM_first[579:572]; endcase end always@(_theResult____h13492 or mmio_axi4_adapter_f_reqs_from_core$D_OUT) begin case (_theResult____h13492) 1'd0: - wflit_wdata__h17678 = + wflit_wdata__h17687 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]; 1'd1: - wflit_wdata__h17678 = + wflit_wdata__h17687 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64]; endcase end @@ -6545,30 +6600,30 @@ module mkProc(CLK, begin case (_theResult____h13492) 1'd0: - wflit_wstrb__h17679 = + wflit_wstrb__h17688 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129]; 1'd1: - wflit_wstrb__h17679 = + wflit_wstrb__h17688 = mmio_axi4_adapter_f_reqs_from_core$D_OUT[144:137]; endcase end always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first) begin case (llc_axi4_adapter_rg_wr_req_beat[2:1]) - 2'd0: v_wuser__h215362 = llc$to_mem_toM_first[512]; - 2'd1: v_wuser__h215362 = llc$to_mem_toM_first[513]; - 2'd2: v_wuser__h215362 = llc$to_mem_toM_first[514]; - 2'd3: v_wuser__h215362 = llc$to_mem_toM_first[515]; + 2'd0: v_wuser__h217508 = llc$to_mem_toM_first[512]; + 2'd1: v_wuser__h217508 = llc$to_mem_toM_first[513]; + 2'd2: v_wuser__h217508 = llc$to_mem_toM_first[514]; + 2'd3: v_wuser__h217508 = llc$to_mem_toM_first[515]; endcase end always@(mmioPlatform_reqFunc) begin case (mmioPlatform_reqFunc[5:4]) 2'd0, 2'd1, 2'd2: - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844 = + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846 = mmioPlatform_reqFunc; 2'd3: - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_0_ETC___d844 = + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_0_ETC___d846 = { 2'd3, mmioPlatform_reqFunc[3:0] }; endcase end @@ -6576,21 +6631,21 @@ module mkProc(CLK, begin case (mmioPlatform_instSel) 2'd0: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0]; 2'd1: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32]; 2'd2: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64]; 2'd3: - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384 = + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386 = mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96]; endcase end always@(mmioPlatform_reqFunc or - IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962 or + IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6598,11 +6653,11 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q9 = - IF_IF_NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4__ETC___d962; + IF_IF_NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4__ETC___d964; endcase end always@(mmioPlatform_reqFunc or - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038 or + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040 or core_0$RDY_mmioToPlatform_pRs_enq) begin case (mmioPlatform_reqFunc[5:4]) @@ -6610,452 +6665,452 @@ module mkProc(CLK, CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = core_0$RDY_mmioToPlatform_pRs_enq; default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 = - IF_mmioPlatform_mtimecmp_0_99_ULE_IF_NOT_mmioP_ETC___d1038; + IF_mmioPlatform_mtimecmp_0_01_ULE_IF_NOT_mmioP_ETC___d1040; endcase end always@(srcRR_0 or - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416 or - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423) + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418 or + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425) begin case (srcRR_0) 1'd0: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 = - IF_propDstIdx_0_lat_0_whas__413_THEN_propDstId_ETC___d1416; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 = + IF_propDstIdx_0_lat_0_whas__415_THEN_propDstId_ETC___d1418; 1'd1: - SEL_ARR_IF_propDstIdx_0_lat_0_whas__413_THEN_p_ETC___d1477 = - IF_propDstIdx_1_lat_0_whas__420_THEN_propDstId_ETC___d1423; + SEL_ARR_IF_propDstIdx_0_lat_0_whas__415_THEN_p_ETC___d1479 = + IF_propDstIdx_1_lat_0_whas__422_THEN_propDstId_ETC___d1425; endcase end always@(srcRR_1_0 or - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549 or - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556) + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551 or + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558) begin case (srcRR_1_0) 1'd0: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 = - IF_propDstIdx_1_0_lat_0_whas__546_THEN_propDst_ETC___d1549; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 = + IF_propDstIdx_1_0_lat_0_whas__548_THEN_propDst_ETC___d1551; 1'd1: - SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__546_THEN_ETC___d1710 = - IF_propDstIdx_1_1_lat_0_whas__553_THEN_propDst_ETC___d1556; + SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__548_THEN_ETC___d1712 = + IF_propDstIdx_1_1_lat_0_whas__555_THEN_propDst_ETC___d1558; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - x__h100956 = + x__h100966 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[3:1] : propDstData_0_rl[3:1]; 1'd1: - x__h100956 = + x__h100966 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[3:1] : propDstData_1_rl[3:1]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - x__h100957 = + x__h100967 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[0] : propDstData_0_rl[0]; 1'd1: - x__h100957 = + x__h100967 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[0] : propDstData_1_rl[0]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[4] : propDstData_0_rl[4]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q11 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[4] : propDstData_1_rl[4]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[8:7] : propDstData_0_rl[8:7]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q12 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[8:7] : propDstData_1_rl[8:7]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[6:5] : propDstData_0_rl[6:5]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q13 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[6:5] : propDstData_1_rl[6:5]; endcase end - always@(x__h100756 or + always@(x__h100766 or CAN_FIRE_RL_srcPropose or propDstData_0_lat_0$wget or propDstData_0_rl or CAN_FIRE_RL_srcPropose_1 or propDstData_1_lat_0$wget or propDstData_1_rl) begin - case (x__h100756) + case (x__h100766) 1'd0: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose ? propDstData_0_lat_0$wget[72:9] : propDstData_0_rl[72:9]; 1'd1: - CASE_x00756_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = + CASE_x00766_0_IF_CAN_FIRE_RL_srcPropose_THEN_p_ETC__q14 = CAN_FIRE_RL_srcPropose_1 ? propDstData_1_lat_0$wget[72:9] : propDstData_1_rl[72:9]; endcase end - always@(x__h122858 or - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592 or - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630) + always@(x__h122868 or + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594 or + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632) begin - case (x__h122858) + case (x__h122868) 1'd0: - x__h127593 = - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1592; + x__h127603 = + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1594; 1'd1: - x__h127593 = - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1630; + x__h127603 = + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1632; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[512:449] : propDstData_1_0_rl[512:449]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q15 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[512:449] : propDstData_1_1_rl[512:449]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[448:385] : propDstData_1_0_rl[448:385]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q16 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[448:385] : propDstData_1_1_rl[448:385]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[516] : propDstData_1_0_rl[516]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q17 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[516] : propDstData_1_1_rl[516]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[515] : propDstData_1_0_rl[515]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q18 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[515] : propDstData_1_1_rl[515]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[514] : propDstData_1_0_rl[514]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q19 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[514] : propDstData_1_1_rl[514]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[384:321] : propDstData_1_0_rl[384:321]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q20 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[384:321] : propDstData_1_1_rl[384:321]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[320:257] : propDstData_1_0_rl[320:257]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q21 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[320:257] : propDstData_1_1_rl[320:257]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[256:193] : propDstData_1_0_rl[256:193]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q22 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[256:193] : propDstData_1_1_rl[256:193]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[192:129] : propDstData_1_0_rl[192:129]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q23 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[192:129] : propDstData_1_1_rl[192:129]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[128:65] : propDstData_1_0_rl[128:65]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q24 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[128:65] : propDstData_1_1_rl[128:65]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[64:1] : propDstData_1_0_rl[64:1]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q25 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[64:1] : propDstData_1_1_rl[64:1]; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_2 ? propDstData_1_0_lat_0$wget[513] : propDstData_1_0_rl[513]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q26 = CAN_FIRE_RL_srcPropose_3 ? propDstData_1_1_lat_0$wget[513] : propDstData_1_1_rl[513]; endcase end - always@(x__h122858 or - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571 or - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609) + always@(x__h122868 or + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573 or + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1571; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1573; 1'd1: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1609; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q27 = + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1611; endcase end - always@(x__h122858 or + always@(x__h122868 or CAN_FIRE_RL_srcPropose_2 or propDstData_1_0_lat_0$wget or propDstData_1_0_rl or CAN_FIRE_RL_srcPropose_3 or propDstData_1_1_lat_0$wget or propDstData_1_1_rl) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_2 ? !propDstData_1_0_lat_0$wget[517] : !propDstData_1_0_rl[517]; 1'd1: - CASE_x22858_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = + CASE_x22868_0_IF_CAN_FIRE_RL_srcPropose_2_THEN_ETC__q28 = CAN_FIRE_RL_srcPropose_3 ? !propDstData_1_1_lat_0$wget[517] : !propDstData_1_1_rl[517]; endcase end - always@(x__h122858 or - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566 or - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604) + always@(x__h122868 or + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568 or + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606) begin - case (x__h122858) + case (x__h122868) 1'd0: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = - IF_propDstData_1_0_lat_0_whas__561_THEN_propDs_ETC___d1566; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_0_lat_0_whas__563_THEN_propDs_ETC___d1568; 1'd1: - CASE_x22858_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = - IF_propDstData_1_1_lat_0_whas__599_THEN_propDs_ETC___d1604; + CASE_x22868_0_IF_propDstData_1_0_lat_0_whas__5_ETC__q29 = + IF_propDstData_1_1_lat_0_whas__601_THEN_propDs_ETC___d1606; endcase end always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or @@ -7063,28 +7118,28 @@ module mkProc(CLK, begin case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32]) 3'd0: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[63:0]; 3'd1: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[127:64]; 3'd2: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[191:128]; 3'd3: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[255:192]; 3'd4: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[319:256]; 3'd5: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[383:320]; 3'd6: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[447:384]; 3'd7: - SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1971 = + SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1973 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7092,14 +7147,14 @@ module mkProc(CLK, llc_mem_server_rg_cacheline_cache_data) begin case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32]) - 3'd0: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[63:0]; - 3'd1: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[127:64]; - 3'd2: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[191:128]; - 3'd3: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[255:192]; - 3'd4: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[319:256]; - 3'd5: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[383:320]; - 3'd6: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[447:384]; - 3'd7: dword__h150359 = llc_mem_server_rg_cacheline_cache_data[511:448]; + 3'd0: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[63:0]; + 3'd1: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[127:64]; + 3'd2: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[191:128]; + 3'd3: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[255:192]; + 3'd4: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[319:256]; + 3'd5: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[383:320]; + 3'd6: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[447:384]; + 3'd7: dword__h150369 = llc_mem_server_rg_cacheline_cache_data[511:448]; endcase end @@ -7501,14 +7556,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (EN_start) begin - v__h224139 = $stime; + v__h226276 = $stime; #0; end - v__h224133 = v__h224139 / 32'd10; + v__h226270 = v__h226276 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (EN_start) $display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h", - v__h224133, + v__h226270, start_startpc, start_tohostAddr, start_fromhostAddr); @@ -7518,14 +7573,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) begin - v__h223691 = $stime; + v__h225828 = $stime; #0; end - v__h223685 = v__h223691 / 32'd10; + v__h225822 = v__h225828 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost) $display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)", - v__h223685, + v__h225822, mmioPlatform_toHostQ_data_0, mmioPlatform_toHostQ_data_0); if (RST_N != `BSV_RESET_VALUE) @@ -7535,7 +7590,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 && mmioPlatform_toHostQ_data_0[63:1] != 63'd0) - $display("FAIL %0d", failed_testnum__h223734); + $display("FAIL %0d", failed_testnum__h225871); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0) $finish(32'd0); @@ -8147,7 +8202,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) begin v__h17177 = $stime; #0; @@ -8156,166 +8211,166 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $display("%d: %m.rl_handle_write_req: sent aw flit:", v__h17171); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("AXI4_AWFlit { ", "awid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awaddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", mem_req_rd_addr_arlen__h5411); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", _theResult_____1_awsize_val__h17116, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write(", ", "awuser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d253) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d257) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) begin - v__h17348 = $stime; + v__h17357 = $stime; #0; end - v__h17342 = v__h17348 / 32'd10; + v__h17351 = v__h17357 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) - $display("%0d: ERROR: CreditCounter: overflow", v__h17342); + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) + $display("%0d: ERROR: CreditCounter: overflow", v__h17351); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && - mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d259) + mmio_axi4_adapter_f_reqs_from_core_first_BITS__ETC___d261) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h17740 = $stime; + v__h17749 = $stime; #0; end - v__h17734 = v__h17740 / 32'd10; + v__h17743 = v__h17749 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%d: %m.rl_handle_write_req: sent w flit:", v__h17734); + $display("%d: %m.rl_handle_write_req: sent w flit:", v__h17743); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8330,7 +8385,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", wflit_wdata__h17678); + $write("'h%h", wflit_wdata__h17687); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8340,7 +8395,7 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $write("'h%h", wflit_wstrb__h17679); + $write("'h%h", wflit_wstrb__h17688); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -8390,16 +8445,16 @@ module mkProc(CLK, !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h18150 = $stime; + v__h18159 = $stime; #0; end - v__h18144 = v__h18150 / 32'd10; + v__h18153 = v__h18159 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && mmio_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response", - v__h18144); + v__h18153); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req && !mmio_axi4_adapter_soc_map$m_is_IO_addr && @@ -9652,14 +9707,14 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h20462 = $stime; + v__h20472 = $stime; #0; end - v__h20456 = v__h20462 / 32'd10; + v__h20466 = v__h20472 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) - $display("%0d: %m.rl_discard_write_rsp", v__h20456); + $display("%0d: %m.rl_discard_write_rsp", v__h20466); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_cfg_verbosity != 4'd0) @@ -9714,15 +9769,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) begin - v__h21008 = $stime; + v__h21018 = $stime; #0; end - v__h21002 = v__h21008 / 32'd10; + v__h21012 = v__h21018 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) $display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", - v__h21002); + v__h21012); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp && mmio_axi4_adapter_master_shim_bff$D_OUT[1:0] != 2'd0) @@ -9772,14 +9827,14 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) begin - v__h21530 = $stime; + v__h21540 = $stime; #0; end - v__h21524 = v__h21530 / 32'd10; + v__h21534 = v__h21540 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", - v__h21524); + v__h21534); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" "); if (RST_N != `BSV_RESET_VALUE) @@ -10071,128 +10126,128 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write("[Platform - SelectReq] timer interrupt", ", mtime %x", mmioPlatform_mtime, ", mtimcmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(", old mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(", new interrupts "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 && - mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) + mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("[Platform - SelectReq] core %d, req ", $signed(32'd0)); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "func: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write("tagged Inst ", "'h%h", core_0$mmioToPlatform_cRq_first[145]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write("tagged Ld ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write("tagged St ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 && core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 && @@ -10201,542 +10256,542 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd0) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd1) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[150:149] == 2'd2) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d584) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d586) $write("Swap"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d590) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d592) $write("Add"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d596) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d598) $write("Xor"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d602) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d604) $write("And"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d608) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d610) $write("Or"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d614) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d616) $write("Min"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d620) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d622) $write("Max"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d626) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d628) $write("Minu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d632) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d634) $write("Maxu"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d654) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d656) $write("None"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "byteEn: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("TaggedData { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && core_0$mmioToPlatform_cRq_first[128]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && !core_0$mmioToPlatform_cRq_first[128]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write(" req type "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && - mmioPlatform_mtip_0_98_OR_NOT_mmioPlatform_mti_ETC___d760) + mmioPlatform_mtip_0_00_OR_NOT_mmioPlatform_mti_ETC___d762) $write("tagged MSIP ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && - core_0_mmioToPlatform_cRq_notEmpty__07_AND_cor_ETC___d764) + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && + core_0_mmioToPlatform_cRq_notEmpty__09_AND_cor_ETC___d766) $write("tagged MTimeCmp ", "'h%h", 1'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d769) + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d771) $write("tagged MTime ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d775) + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d777) $write("tagged ToHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d781) + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d783) $write("tagged FromHost ", ""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty && - (core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d523 || - !core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d525) && - core_0_mmioToPlatform_cRq_first__21_BITS_214_T_ETC___d788) + (core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d525 || + !core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d527) && + core_0_mmioToPlatform_cRq_first__23_BITS_214_T_ETC___d790) $write("tagged MMIO_Fabric_Adapter ", "'h%h", core_0$mmioToPlatform_cRq_first[214:151]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_selectReq && (mmioPlatform_mtip_0 || - !mmioPlatform_mtimecmp_0_99_ULE_mmioPlatform_mt_ETC___d500) && + !mmioPlatform_mtimecmp_0_01_ULE_mmioPlatform_mt_ETC___d502) && core_0$mmioToPlatform_cRq_notEmpty) $write("\n"); if (RST_N != `BSV_RESET_VALUE) @@ -10799,8 +10854,8 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMSIPDone) $display("[Platform - msip done] lower %x, upper %x", - lower_data__h44520, - upper_data__h44521); + lower_data__h44530, + upper_data__h44531); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && mmioPlatform_reqFunc[5:4] == 2'd0) @@ -10812,62 +10867,62 @@ module mkProc(CLK, mmioPlatform_mtimecmp_0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write("[Platform - process mtimecmp] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(", mtime %x", mmioPlatform_mtime, ", old mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTimeCmp && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d993) - $write(", new mtimecmp[%d] %x", 1'd0, newData__h45219, "\n"); + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d995) + $write(", new mtimecmp[%d] %x", 1'd0, newData__h45229, "\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone) $write("[Platform - mtimecmp done]", @@ -10912,61 +10967,61 @@ module mkProc(CLK, mmioPlatform_mtime); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write("[Platform - process mtime] ", "no change to mtip "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) - $write(", new mtime %x", newData__h53320, ", mtimecmp "); + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) + $write(", new mtime %x", newData__h53330, ", mtimecmp "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processMTime && - NOT_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ__ETC___d1065) + NOT_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ__ETC___d1067) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_waitMTimeDone) @@ -11023,7 +11078,7 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1100) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1102) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11049,13 +11104,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_14_OR_mmioPlatfo_ETC___d1106, + IF_mmioPlatform_toHostQ_empty_16_OR_mmioPlatfo_ETC___d1108, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_toHostQ_empty_14_THEN_0_ELSE_I_ETC___d1104, + IF_mmioPlatform_toHostQ_empty_16_THEN_0_ELSE_I_ETC___d1106, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processToHost && @@ -11092,12 +11147,12 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1171) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1173) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0 && - IF_mmioPlatform_reqFunc_02_BITS_5_TO_4_03_EQ_2_ETC___d1154) + IF_mmioPlatform_reqFunc_04_BITS_5_TO_4_05_EQ_2_ETC___d1156) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11123,13 +11178,13 @@ module mkProc(CLK, if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_80_OR_mmioPlat_ETC___d1159, + IF_mmioPlatform_fromHostQ_empty_82_OR_mmioPlat_ETC___d1161, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && mmioPlatform_reqFunc[5:4] != 2'd0) $write("'h%h", - IF_mmioPlatform_fromHostQ_empty_80_THEN_0_ELSE_ETC___d1157, + IF_mmioPlatform_fromHostQ_empty_82_THEN_0_ELSE_ETC___d1159, " "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_processFromHost && @@ -11624,7 +11679,7 @@ module mkProc(CLK, $write("MMIOCRq { ", "addr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) - $write("'h%h", addr1__h90533); + $write("'h%h", addr1__h90543); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req) $write(", ", "func: "); @@ -11709,76 +11764,76 @@ module mkProc(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display(" fetchingWay %0d instSel %0d inst 0x%0h", mmioPlatform_fetchingWay, mmioPlatform_instSel, - SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1384); + SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1386); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $display("MMIOPlatform.rl_mmio_from_fabric_ifetch_rsp: final resp to core:"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] && - !mmioPlatform_fetchingWay_363_ULT_mmioPlatform__ETC___d1372) + !mmioPlatform_fetchingWay_365_ULT_mmioPlatform__ETC___d1374) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp && @@ -11846,16 +11901,16 @@ module mkProc(CLK, llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) begin - v__h201342 = $stime; + v__h203428 = $stime; #0; end - v__h201336 = v__h201342 / 32'd10; + v__h203422 = v__h203428 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && llc_axi4_adapter_rg_wr_req_beat == 3'd0) $display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:", - v__h201336); + v__h203422); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_cfg_verbosity != 4'd0 && @@ -13312,15 +13367,15 @@ module mkProc(CLK, llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) begin - v__h215051 = $stime; + v__h217146 = $stime; #0; end - v__h215045 = v__h215051 / 32'd10; + v__h217140 = v__h217146 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15) - $display("%0d: ERROR: CreditCounter: overflow", v__h215045); + $display("%0d: ERROR: CreditCounter: overflow", v__h217140); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req && llc_axi4_adapter_rg_wr_req_beat == 3'd0 && @@ -13330,15 +13385,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) begin - v__h193319 = $stime; + v__h193329 = $stime; #0; end - v__h193313 = v__h193319 / 32'd10; + v__h193323 = v__h193329 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory", - v__h193313); + v__h193323); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && llc_axi4_adapter_cfg_verbosity != 4'd0) @@ -13395,103 +13450,103 @@ module mkProc(CLK, $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("AXI4_ARFlit { ", "arid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 5'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "araddr: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) - $write("'h%h", line_addr__h193455); + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) + $write("'h%h", line_addr__h193465); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arlen: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 8'd7); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arsize: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("AXI4_Size { ", "val: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 3'b011, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arburst: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("INCR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arlock: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("NORMAL"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arcache: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 4'b0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arprot: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 3'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arqos: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "arregion: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 4'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "aruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", 1'd0, " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_master_awSynth_src_warnDoDrop) @@ -13506,15 +13561,15 @@ module mkProc(CLK, if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) begin - v__h222677 = $stime; + v__h224814 = $stime; #0; end - v__h222671 = v__h222677 / 32'd10; + v__h224808 = v__h224814 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", - v__h222671); + v__h224808); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp && llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0) @@ -13572,62 +13627,62 @@ module mkProc(CLK, $display("WARNING: %m - putting into a Sink that can't be put into"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) begin - v__h193908 = $stime; + v__h193918 = $stime; #0; end - v__h193902 = v__h193908 / 32'd10; + v__h193912 = v__h193918 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", - v__h193902, + v__h193912, llc_axi4_adapter_rg_rd_rsp_beat); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("AXI4_RFlit { ", "rid: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "rdata: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "rresp: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0) $write("OKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1) $write("EXOKAY"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2) $write("SLVERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != @@ -13636,45 +13691,45 @@ module mkProc(CLK, $write("DECERR"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "rlast: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && !llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "ruser: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) begin - v__h194094 = $stime; + v__h194104 = $stime; #0; end - v__h194088 = v__h194094 / 32'd10; + v__h194098 = v__h194104 / 32'd10; if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) $display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", - v__h194088); + v__h194098); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0) @@ -13753,310 +13808,286 @@ module mkProc(CLK, $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" Response to LLC: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("MemRsMsg { ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("CLine { ", "tag: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "data: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" >"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "child: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(""); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "id: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("LdMemRqId { ", "refill: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("True"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241 && + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243 && !llc_axi4_adapter_f_pending_reads$D_OUT[4]) $write("False"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(", ", "mshrIdx: "); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write(" }"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps && - llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 && - NOT_llc_axi4_adapter_cfg_verbosity_read__226_U_ETC___d2241) + llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1] && + NOT_llc_axi4_adapter_cfg_verbosity_read__228_U_ETC___d2243) $write("\n"); end // synopsys translate_on diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v index f803dd8..acace0b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRFileSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:04:33 BST 2020 +// On Mon Jul 6 19:18:26 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v index 5e97129..5e61bb2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRas.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRas.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:38 BST 2020 +// On Mon Jul 6 19:19:31 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v index da783ff..e8da78b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRegRenamingTable.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:02:06 BST 2020 +// On Mon Jul 6 19:15:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v index 328a358..ec81705 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReorderBufferSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:14 BST 2020 +// On Mon Jul 6 19:19:08 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v index 9cb0c11..0aff2af 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationAlu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:54 BST 2020 +// On Mon Jul 6 19:23:58 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v index 8853cad..d6c2e48 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationFpuMulDiv.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:28 BST 2020 +// On Mon Jul 6 19:19:21 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v index a30b4ef..58edb06 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkReservationStationMem.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:23 BST 2020 +// On Mon Jul 6 19:19:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v index 2fb7dc7..b6ddf52 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkRobRowSynth.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:04:43 BST 2020 +// On Mon Jul 6 19:18:36 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v index 0c61135..33b52d0 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardAggr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:06:56 BST 2020 +// On Mon Jul 6 19:20:49 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v index fc94cdf..6d4f8f9 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkScoreboardCons.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:06:49 BST 2020 +// On Mon Jul 6 19:20:42 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v index 8053261..4d7eb51 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSimpleRespQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:20 BST 2020 +// On Mon Jul 6 19:23:15 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v index 1017461..9a8bb14 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSoC_Map.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:39 BST 2020 +// On Mon Jul 6 19:14:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v index 21ba2ec..39c206d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSpecTagManager.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:04:24 BST 2020 +// On Mon Jul 6 19:18:16 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v index 4c561b7..42dbc4d 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitLSQ.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:06:21 BST 2020 +// On Mon Jul 6 19:20:14 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v index ec4d7e9..4c4704c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkSplitTransCache.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:12 BST 2020 +// On Mon Jul 6 19:15:03 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v index c0868c1..f59bf6e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkStoreBufferEhr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:39 BST 2020 +// On Mon Jul 6 19:15:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v index a36266a..3d82e2c 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourGHistReg.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v index 47bb354..cdc0c9e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:26 BST 2020 +// On Mon Jul 6 19:23:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v index 8d3e17b..8621a92 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkTourPredSecure.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:10:27 BST 2020 +// On Mon Jul 6 19:23:30 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v index 67ea0ed..9536d91 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_alu.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_alu.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:57 BST 2020 +// On Mon Jul 6 19:14:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v index d525ba1..743e47b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_aluBr.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v index 848b5ed..21a13cf 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_amoExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:36 BST 2020 +// On Mon Jul 6 19:14:29 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v index c13a99c..1afff3b 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_basicExec.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:51 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v index 745a265..f1ccf07 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_brAddrCalc.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v b/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v index 2cb88c4..53a9388 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capChecks.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:57 BST 2020 +// On Mon Jul 6 19:14:47 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v b/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v index f990185..184990a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capInspect.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:00 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v b/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v index 24ce649..c991fa2 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_capModify.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:59 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v index 4ea998e..5128c22 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_checkForException.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:01:01 BST 2020 +// On Mon Jul 6 19:14:52 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v index 6c790f8..b8dd08a 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decode.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decode.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:34 BST 2020 +// On Mon Jul 6 19:19:27 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v index 1cd22f1..439b8b1 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_decodeBrPred.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:05:30 BST 2020 +// On Mon Jul 6 19:19:23 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v index 67ada5c..490ee7e 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_execFpuSimple.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:09:26 BST 2020 +// On Mon Jul 6 19:23:20 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v b/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v index fb4e075..1c9e579 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_prepareBoundsCheck.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:57 BST 2020 +// On Mon Jul 6 19:14:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v b/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v index 6a87c02..759e4d3 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_setBoundsALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:58 BST 2020 +// On Mon Jul 6 19:14:48 BST 2020 // // // Ports: diff --git a/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v b/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v index c9836ba..c234696 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v +++ b/src_SSITH_P3/xilinx_ip/hdl/module_specialRWALU.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24) // -// On Sun Jul 5 22:00:59 BST 2020 +// On Mon Jul 6 19:14:50 BST 2020 // // // Ports: