From 4714070aef2bab8996f158554b77d291e9c841c9 Mon Sep 17 00:00:00 2001 From: jon Date: Wed, 1 Apr 2020 18:43:48 +0100 Subject: [PATCH] Trace the next PC correctly for mret. --- src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index 706c0e3..15463f8 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -236,9 +236,9 @@ deriving (Eq, FShow, Bits); `endif module mkCommitStage#(CommitInput inIfc)(CommitStage); - Bool verbose = False; + Bool verbose = True; - Integer verbosity = 1; // Bluespec: for lightweight verbosity trace + Integer verbosity = 2; // Bluespec: for lightweight verbosity trace // Used to inform tandem-verifier about program order. // 0 is used to indicate we've just come out of reset @@ -904,6 +904,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); `ifdef RVFI Rvfi_Traces rvfis = replicate(tagged Invalid); + x.ppc_vaddr_csrData = tagged PPC setAddrUnsafe(x.pc, next_pc); rvfis[0] = genRVFI(x, traceCnt, getTSB(), next_pc); rvfiQ.enq(rvfis); traceCnt <= traceCnt + 1;