diff --git a/builds/RV64ADFIMSU_Toooba_verilator/Makefile b/builds/RV64ADFIMSU_Toooba_verilator/Makefile
index 9f7c798..a7bef4c 100644
--- a/builds/RV64ADFIMSU_Toooba_verilator/Makefile
+++ b/builds/RV64ADFIMSU_Toooba_verilator/Makefile
@@ -39,6 +39,9 @@ TEST ?= rv64ui-p-add
 #================================================================
 # Parameter settings for MIT RISCY
 
+BSC_COMPILATION_FLAGS += D BSIM \
+
+
 include $(REPO)/builds/Resources/Include_RISCY_Config.mk
 
 #================================================================
diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk
index 7fc485e..203f5e8 100644
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -70,11 +70,10 @@ XILINX_INT_MUL_LATENCY = 2
 
 
 BSC_COMPILATION_FLAGS += \
-	-D BSIM \
 	-D CORE_$(CORE_SIZE) \
 	-D NUM_CORES=$(CORE_NUM) \
 	-D CACHE_$(CACHE_SIZE) \
-	-D  USE_XILINX_FPU \
+	-D USE_XILINX_FPU \
         -D XILINX_FP_FMA_LATENCY=$(XILINX_FP_FMA_LATENCY) \
         -D XILINX_INT_MUL_LATENCY=$(XILINX_INT_MUL_LATENCY) \
 	-D USE_BSV_BRAM_SYNC_FIFO \
diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile
index faadac6..9f1b56c 100644
--- a/src_SSITH_P3/Makefile
+++ b/src_SSITH_P3/Makefile
@@ -37,6 +37,7 @@ BSC_COMPILATION_FLAGS += \
 
 #================================================================
 # Parameter settings for MIT RISCY
+# We omit 'BSC_COMPILATION_FLAGS += D BSIM' so it'll use Xilinx IP for floating point arith
 
 include $(REPO)/builds/Resources/Include_RISCY_Config.mk