diff --git a/src_SSITH_P3/src_BSV/SoC_Map.bsv b/src_SSITH_P3/src_BSV/SoC_Map.bsv
index 0b2da5b..183ad20 100644
--- a/src_SSITH_P3/src_BSV/SoC_Map.bsv
+++ b/src_SSITH_P3/src_BSV/SoC_Map.bsv
@@ -71,7 +71,7 @@ SoC_Map_Struct {
    boot_rom_addr_size:     'h_0000_1000,
 
    main_mem_addr_base:     'h_C000_0000,
-   main_mem_addr_size:     'h_4000_0000,
+   main_mem_addr_size:     'h_C000_0000,
 
    pc_reset_value:         'h_7000_0000    // = boot_rom_addr_base
    };
@@ -194,7 +194,7 @@ module mkSoC_Map (SoC_Map_IFC);
 
    let ddr4_0_cached_addr_range = Range {
       base: 'h_C000_0000,
-      size: 'h_4000_0000    // 1G
+      size: 'h_C000_0000    // 3G
    };
 
    // ----------------------------------------------------------------
diff --git a/src_SSITH_P3/src_BSV/TagTableStructure.bsv b/src_SSITH_P3/src_BSV/TagTableStructure.bsv
index 0593a8f..98c695a 100644
--- a/src_SSITH_P3/src_BSV/TagTableStructure.bsv
+++ b/src_SSITH_P3/src_BSV/TagTableStructure.bsv
@@ -28,7 +28,7 @@
 
 import Vector::*;
 Vector#(2, Integer) tableStructure = cons(0, cons(64, nil));
-Integer table_end_addr = 'hfffff000;
-Integer table_start_addr = 'hff7df080;
+Integer table_end_addr = 'h17ffff000;
+Integer table_start_addr = 'h17e79f100;
 Integer covered_start_addr = 'hc0000000;
-Integer covered_mem_size  = 'h3fffc000;
+Integer covered_mem_size  = 'hbfff8000;