From 483cef8852f55c959aebf896d8ecb02ca02850a3 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 12 Jul 2021 14:55:07 +0200 Subject: [PATCH] Removed unnecessary display statements --- src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv | 6 ------ src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 2 -- src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv | 3 --- 3 files changed, 11 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 9d13826..b3b19df 100755 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -317,7 +317,6 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); Bit#(32) imm = fromMaybe(32'h00000000, x.dInst.imm); let val = pc_addr + signExtend(imm); if((val != ppc_addr) && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin - $display("Wild direct jump: pc = ", fshow(pc), " ppc = ", fshow(ppc), " imm = ", fshow(imm)); events.evt_WILD_JUMP = 1; events_reg[1] <= events; end @@ -328,9 +327,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); else if(x.dInst.iType == CJALR || x.dInst.iType == Jr) begin let res_targets = inIfc.checkTarget(ppc); let res_ret_targets = inIfc.checkReturnTarget(ppc); - $display("pc = ", fshow(pc), "res_targets = ", fshow(res_targets), " res_ret_targets = ", fshow(res_ret_targets)); if(!res_targets && !res_ret_targets && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin - $display("Wild indirect jump: pc = ", fshow(pc), " ppc = ", fshow(ppc)); events.evt_WILD_JUMP = 1; events_reg[1] <= events; end @@ -457,10 +454,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); let pc = getAddr(x.controlFlow.pc); let ppc = getAddr(x.controlFlow.nextPc); let validPc = x.isCompressed ? (pc + 2) : (pc + 4); - $display("spec_excps: pc = ", fshow(pc), ", ppc = ", fshow(ppc), ", validPc = ", fshow(validPc)); - $display("capException = ", fshow(x.capException)); if(x.capException matches tagged Valid .exc &&& (ppc != validPc)) begin - $display("Wild exception"); EventsTransExe events = unpack(0); events.evt_WILD_EXCEPTION = 1; events_reg[0] <= events; diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index 50df284..1d2d6a2 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -1173,11 +1173,9 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); // update return target if(x.iType == J || x.iType == CJAL || x.iType == CJALR || x.iType == Jr) begin tar = tagged Valid x.ppc_vaddr_csrData.PPC; - $display("BRANCH target added: pc = ", fshow(x.pc), " tar = ", fshow(tar)); if(linkedR(x.dst)) begin let imm = is_16b_inst(x.orig_inst) ? 2 : 4; retTar = tagged Valid addPc(x.pc, imm); - $display("RETURN target added: pc = ", fshow(x.pc), " retTar = ", fshow(retTar)); end end `endif diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index f856789..cf91a32 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -695,10 +695,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); let ppc = inIfc.rob_getPredPC(x.tag); let inst = inIfc.rob_getOrig_Inst(x.tag); let validPc = is_16b_inst(inst) ? addPc(pc,2) : addPc(pc,4); - $display("spec_excps: pc = ", fshow(pc), ", ppc = ", fshow(ppc), ", validPc = ", fshow(validPc)); - $display("sbc_excps: cause = ", fshow(cause)); if(cause matches tagged Valid .c &&& (ppc != validPc)) begin - $display("Wild Exception"); EventsTransExe events_trans = unpack(0); events_trans.evt_WILD_EXCEPTION = 1; events_trans_reg <= events_trans;