diff --git a/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv b/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv
index bae699f..242e03e 100644
--- a/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/SpecFifo.bsv
@@ -155,6 +155,8 @@ module mkSpecFifo#(
         specBits[enqP][sched.sbEnqPort] <= x.spec_bits;
     endmethod
 
+    method Bool notFull = (empty_for_enq || enqP != deqP_for_enq);
+
     method Action deq if (valid[deqP][sched.validDeqPort]
                           && !wrongSpec_deq_conflict); // make conflict with incorrect spec
         valid[deqP][sched.validDeqPort] <= False;