diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv
index 70c1f3d..dbb61d0 100644
--- a/src_Core/CPU/CsrFile.bsv
+++ b/src_Core/CPU/CsrFile.bsv
@@ -1027,7 +1027,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
             end
             tagged CapException .ce: begin
                 cause_code = pack(CHERIFault);
-                // populate CHERI cause register.
+                trap_val = zeroExtend({pack(ce.cheri_exc_reg), pack(ce.cheri_exc_code)});
             end
             tagged Interrupt .i: begin
                 cause_code = zeroExtend(pack(i));