diff --git a/builds/Resources/Include_RISCY_Config.mk b/builds/Resources/Include_RISCY_Config.mk
index 78005ab..888b825 100644
--- a/builds/Resources/Include_RISCY_Config.mk
+++ b/builds/Resources/Include_RISCY_Config.mk
@@ -45,10 +45,10 @@ SIM_LLC_ARBITER_LAT ?=
 # default check cache deadlock and rename error
 CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
-INSTR_PREFETCHER_LOCATION ?= NONE
-INSTR_PREFETCHER_TYPE ?= MULTI_WINDOW
+INSTR_PREFETCHER_LOCATION ?= L1
+INSTR_PREFETCHER_TYPE ?= MULTI_WINDOW_TARGET
 DATA_PREFETCHER_LOCATION ?= NONE
-DATA_PREFETCHER_TYPE ?= STRIDE
+DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT_2
 
 # clk frequency depends on core size
 ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))
diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
index 8c4cf4d..b8a0ab8 100644
--- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
@@ -816,14 +816,14 @@ provisos(
     Vector#(numWindows, Reg#(windowIdxT)) shiftReg <- genWithM(compose(mkReg, fromInteger));
     Reg#(LineAddr) lastChildRequest <- mkReg(0);
 
-    TargetTableBRAM#(64, 8) targetTable <- mkTargetTableBRAM;
+    TargetTableBRAM#(8192, 2048) targetTable <- mkTargetTableBRAM;
     FIFOF#(LineAddr) targetTableReadResp <- mkBypassFIFOF;
     Reg#(Vector#(numLastRequests, Bit#(32))) lastTargetRequests <- mkReg(replicate(0));
 
     rule sendReadReq;
         if (!elem(hash(lastChildRequest), lastTargetRequests)) begin 
             targetTable.readReq(lastChildRequest);
-            $display("%t Prefetcher sending target read request for %h", $time, lastChildRequest);
+            $display("%t Prefetcher sending target read request for %h", $time, Addr'{lastChildRequest, 'h0});
             lastTargetRequests <= shiftInAt0(lastTargetRequests, hash(lastChildRequest));
         end
     endrule