diff --git a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v index 3ab812a..ccff47b 100644 --- a/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v +++ b/builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v @@ -4125,33 +4125,33 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968, - addr__h294612, - curData__h195303, - rVal1__h615931, - rVal1__h640775, - trap_val__h708781, - x__h200346; + addr__h294613, + curData__h195304, + rVal1__h615932, + rVal1__h640776, + trap_val__h708782, + x__h200347; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8, - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q209, - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q210, - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211, - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212, - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197, - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198, - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199, - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200, - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201, - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202, - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213, - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214, - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215, - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216, - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217, - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218, - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q207, - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q208, + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q209, + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q210, + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q211, + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q212, + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q197, + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q198, + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q199, + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q200, + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q201, + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q202, + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q213, + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q214, + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q215, + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q216, + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q217, + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q218, + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q207, + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q208, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755, @@ -4163,45 +4163,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75, - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76, - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79, - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80, - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81, - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82, - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112, - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113, - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42, - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43, - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110, - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111, - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40, - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41, - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114, - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115, - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44, - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45, - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116, - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117, - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46, - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47, - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77, - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78, - _theResult___fst_sfd__h350718, - _theResult___fst_sfd__h359441, - _theResult___fst_sfd__h368023, - _theResult___fst_sfd__h377207, - _theResult___fst_sfd__h385843, - _theResult___fst_sfd__h396417, - _theResult___fst_sfd__h405138, - _theResult___fst_sfd__h413720, - _theResult___fst_sfd__h422904, - _theResult___fst_sfd__h431540, - _theResult___fst_sfd__h442112, - _theResult___fst_sfd__h450833, - _theResult___fst_sfd__h459415, - _theResult___fst_sfd__h468599, - _theResult___fst_sfd__h477235; + reg [22 : 0] CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q75, + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q76, + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q79, + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q80, + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q81, + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q82, + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q112, + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q113, + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q42, + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q43, + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q110, + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q111, + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q40, + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q41, + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q114, + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q115, + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q44, + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q45, + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q116, + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q117, + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q46, + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q47, + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q77, + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q78, + _theResult___fst_sfd__h350719, + _theResult___fst_sfd__h359442, + _theResult___fst_sfd__h368024, + _theResult___fst_sfd__h377208, + _theResult___fst_sfd__h385844, + _theResult___fst_sfd__h396418, + _theResult___fst_sfd__h405139, + _theResult___fst_sfd__h413721, + _theResult___fst_sfd__h422905, + _theResult___fst_sfd__h431541, + _theResult___fst_sfd__h442113, + _theResult___fst_sfd__h450834, + _theResult___fst_sfd__h459416, + _theResult___fst_sfd__h468600, + _theResult___fst_sfd__h477236; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268, @@ -4225,24 +4225,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9, - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203, - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204, - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205, - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206, - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175, - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176, - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177, - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178, - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179, - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180, - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152, - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153, - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183, - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184, - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181, - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182, - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135, - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136, + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q203, + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q204, + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q205, + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q206, + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q175, + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q176, + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q177, + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q178, + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q179, + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q180, + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q152, + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q153, + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q183, + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q184, + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q181, + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q182, + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q135, + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q136, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684, @@ -4252,47 +4252,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914; - reg [7 : 0] CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60, - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61, - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68, - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69, - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73, - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74, - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97, - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98, - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27, - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28, - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95, - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96, - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25, - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26, - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103, - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104, - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33, - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34, - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108, - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109, - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38, - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39, - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62, - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63, + reg [7 : 0] CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q60, + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q61, + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q68, + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q69, + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q73, + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q74, + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q97, + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q98, + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q27, + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q28, + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q95, + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q96, + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q25, + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q26, + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q103, + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q104, + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q33, + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q34, + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q108, + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q109, + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q38, + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q39, + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q62, + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q63, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430, - _theResult___fst_exp__h350717, - _theResult___fst_exp__h359440, - _theResult___fst_exp__h368022, - _theResult___fst_exp__h377206, - _theResult___fst_exp__h385842, - _theResult___fst_exp__h396416, - _theResult___fst_exp__h405137, - _theResult___fst_exp__h413719, - _theResult___fst_exp__h422903, - _theResult___fst_exp__h431539, - _theResult___fst_exp__h442111, - _theResult___fst_exp__h450832, - _theResult___fst_exp__h459414, - _theResult___fst_exp__h468598, - _theResult___fst_exp__h477234; + _theResult___fst_exp__h350718, + _theResult___fst_exp__h359441, + _theResult___fst_exp__h368023, + _theResult___fst_exp__h377207, + _theResult___fst_exp__h385843, + _theResult___fst_exp__h396417, + _theResult___fst_exp__h405138, + _theResult___fst_exp__h413720, + _theResult___fst_exp__h422904, + _theResult___fst_exp__h431540, + _theResult___fst_exp__h442112, + _theResult___fst_exp__h450833, + _theResult___fst_exp__h459415, + _theResult___fst_exp__h468599, + _theResult___fst_exp__h477235; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263, @@ -4310,8 +4310,8 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14219, IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266, IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14380, - i__h707773, - i__h707933; + i__h707774, + i__h707934; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267, @@ -4325,8 +4325,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q228, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828, - x__h290391, - x__h296161; + x__h290392, + x__h296162; reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, @@ -4358,46 +4358,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235, - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, - CASE_k74092_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, + CASE_guard05152_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86, + CASE_guard05152_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85, + CASE_guard08266_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139, + CASE_guard14082_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88, + CASE_guard14082_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87, + CASE_guard17335_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141, + CASE_guard22918_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90, + CASE_guard22918_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89, + CASE_guard37807_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195, + CASE_guard37807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185, + CASE_guard42140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120, + CASE_guard42140_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118, + CASE_guard47119_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191, + CASE_guard47119_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187, + CASE_guard50746_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49, + CASE_guard50746_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48, + CASE_guard50847_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121, + CASE_guard50847_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119, + CASE_guard56188_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193, + CASE_guard56188_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189, + CASE_guard59455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51, + CASE_guard59455_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50, + CASE_guard59777_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123, + CASE_guard59777_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122, + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53, + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52, + CASE_guard68613_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125, + CASE_guard68613_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124, + CASE_guard77111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164, + CASE_guard77111_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154, + CASE_guard77221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55, + CASE_guard77221_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54, + CASE_guard86423_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160, + CASE_guard86423_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156, + CASE_guard95492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162, + CASE_guard95492_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158, + CASE_guard96445_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84, + CASE_guard96445_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83, + CASE_guard98954_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137, + CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, @@ -4482,7 +4482,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023; - wire [127 : 0] b__h608520, b__h608596, b__h608697, b__h608709, x__h609549; + wire [127 : 0] b__h608521, b__h608597, b__h608698, b__h608710, x__h609550; wire [68 : 0] execFpuSimple___d11167; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627; wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598; @@ -4517,162 +4517,162 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095, - _theResult___fst__h608920, - _theResult___snd__h608921, - a___1__h608534, - a___1__h608925, - a__h608372, + _theResult___fst__h608921, + _theResult___snd__h608922, + a___1__h608535, + a___1__h608926, + a__h608373, amoExec___d882, - b___1__h608535, - b___1__h608986, - b__h608373, - base__h710681, - base__h710701, + b___1__h608536, + b___1__h608987, + b__h608374, + base__h710682, + base__h710702, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257, - data___1__h479773, - data___1__h480705, - data__h479261, - data__h480193, - fallthrough_pc__h670384, - fallthrough_pc__h686130, - fcsr_csr__read__h616233, - fflags_csr__read__h616208, - frm_csr__read__h616219, - mcause_csr__read__h617875, - mcounteren_csr__read__h617620, - medeleg_csr__read__h617227, - mideleg_csr__read__h617322, - mie_csr__read__h617446, - mip_csr__read__h618108, - mstatus_csr__read__h617079, - mtvec_csr__read__h617528, - n___1__h201749, - n__h196841, - n__read__h618212, - n__read__h618403, - n__read__h6330, - n__read__h719388, - next_pc__h718598, - q___1__h480780, - rVal1__h487142, - rVal2__h487143, - r___1__h480807, - res_data__h342519, - res_data__h342524, - res_data__h388221, - res_data__h388226, - res_data__h433916, - res_data__h433921, - resp_addr__h296627, - rg_tdata1__read__h619063, + data___1__h479774, + data___1__h480706, + data__h479262, + data__h480194, + fallthrough_pc__h670385, + fallthrough_pc__h686131, + fcsr_csr__read__h616234, + fflags_csr__read__h616209, + frm_csr__read__h616220, + mcause_csr__read__h617876, + mcounteren_csr__read__h617621, + medeleg_csr__read__h617228, + mideleg_csr__read__h617323, + mie_csr__read__h617447, + mip_csr__read__h618109, + mstatus_csr__read__h617080, + mtvec_csr__read__h617529, + n___1__h201750, + n__h196842, + n__read__h618213, + n__read__h618404, + n__read__h6331, + n__read__h719389, + next_pc__h718599, + q___1__h480781, + rVal1__h487143, + rVal2__h487144, + r___1__h480808, + res_data__h342520, + res_data__h342525, + res_data__h388222, + res_data__h388227, + res_data__h433917, + res_data__h433922, + resp_addr__h296628, + rg_tdata1__read__h619064, rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954, robdeqPort_0_deq_data_BITS_95_TO_32__q262, - satp_csr__read__h616936, - scause_csr__read__h616733, - scounteren_csr__read__h616595, - shiftData__h184742, - sie_csr__read__h616499, - sip_csr__read__h616873, - sstatus_csr__read__h616429, - stvec_csr__read__h616542, + satp_csr__read__h616937, + scause_csr__read__h616734, + scounteren_csr__read__h616596, + shiftData__h184743, + sie_csr__read__h616500, + sip_csr__read__h616874, + sstatus_csr__read__h616430, + stvec_csr__read__h616543, upd__h3681, upd__h4998, - v__h614703, - v__h639701, - vaddr__h184737, - x__h155097, - x__h158644, - x__h161458, - x__h163306, - x__h17932, - x__h184649, + v__h614704, + v__h639702, + vaddr__h184738, + x__h155098, + x__h158645, + x__h161459, + x__h163307, + x__h17933, x__h184650, - x__h20470, - x__h291836, - x__h293690, - x__h45839, - x__h48375, - x__h487048, + x__h184651, + x__h20471, + x__h291837, + x__h293691, + x__h45840, + x__h48376, x__h487049, x__h487050, - x__h608909, - x__h623642, + x__h487051, + x__h608910, x__h623643, - x__h646271, + x__h623644, x__h646272, - x__h704087, - x_addr__h318724, - x_quotient__h479957, - x_reg_ifc__read__h616338, - x_remainder__h479958, - y__h626444, - y__h648780, - y__h722608, - y_avValue__h183777, - y_avValue__h184496, - y_avValue__h484111, - y_avValue__h484832, - y_avValue__h485547, - y_avValue__h615874, - y_avValue__h621652, - y_avValue__h640720, - y_avValue__h644291, - y_avValue_new_pc__h710462, - y_avValue_new_pc__h710648, - y_avValue_snd_snd_snd_snd_snd__h722002, - y_avValue_snd_snd_snd_snd_snd__h722661, - y_avValue_snd_snd_snd_snd_snd__h722690; + x__h646273, + x__h704088, + x_addr__h318725, + x_quotient__h479958, + x_reg_ifc__read__h616339, + x_remainder__h479959, + y__h626445, + y__h648781, + y__h722609, + y_avValue__h183778, + y_avValue__h184497, + y_avValue__h484112, + y_avValue__h484833, + y_avValue__h485548, + y_avValue__h615875, + y_avValue__h621653, + y_avValue__h640721, + y_avValue__h644292, + y_avValue_new_pc__h710463, + y_avValue_new_pc__h710649, + y_avValue_snd_snd_snd_snd_snd__h722003, + y_avValue_snd_snd_snd_snd_snd__h722662, + y_avValue_snd_snd_snd_snd_snd__h722691; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993, - r1__read__h619388, - r1__read__h619792, - r1__read__h620302, - r1__read__h620307, - r1__read__h620326, - r1__read__h620559, - r1__read__h620725, - r1__read__h620818, - r1__read__h620823, - r1__read__h620842; - wire [61 : 0] r1__read__h619390, - r1__read__h619794, - r1__read__h620309, - r1__read__h620328, - r1__read__h620561, - r1__read__h620701, - r1__read__h620727, - r1__read__h620825, - r1__read__h620844; - wire [60 : 0] r1__read__h620563, - r1__read__h620703, - r1__read__h620729, - r1__read__h620846; - wire [59 : 0] r1__read__h619392, - r1__read__h619796, - r1__read__h620320, - r1__read__h620330, - r1__read__h620565, - r1__read__h620731, - r1__read__h620836, - r1__read__h620848; - wire [58 : 0] r1__read__h619394, - r1__read__h619798, - r1__read__h620332, - r1__read__h620567, - r1__read__h620733, - r1__read__h620850; + r1__read__h619389, + r1__read__h619793, + r1__read__h620303, + r1__read__h620308, + r1__read__h620327, + r1__read__h620560, + r1__read__h620726, + r1__read__h620819, + r1__read__h620824, + r1__read__h620843; + wire [61 : 0] r1__read__h619391, + r1__read__h619795, + r1__read__h620310, + r1__read__h620329, + r1__read__h620562, + r1__read__h620702, + r1__read__h620728, + r1__read__h620826, + r1__read__h620845; + wire [60 : 0] r1__read__h620564, + r1__read__h620704, + r1__read__h620730, + r1__read__h620847; + wire [59 : 0] r1__read__h619393, + r1__read__h619797, + r1__read__h620321, + r1__read__h620331, + r1__read__h620566, + r1__read__h620732, + r1__read__h620837, + r1__read__h620849; + wire [58 : 0] r1__read__h619395, + r1__read__h619799, + r1__read__h620333, + r1__read__h620568, + r1__read__h620734, + r1__read__h620851; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, - r1__read__h619396, - r1__read__h619800, - r1__read__h620334, - r1__read__h620569, - r1__read__h620705, - r1__read__h620735, - r1__read__h620852, - y__h258434; + r1__read__h619397, + r1__read__h619801, + r1__read__h620335, + r1__read__h620570, + r1__read__h620706, + r1__read__h620736, + r1__read__h620853, + y__h258435; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91, @@ -4700,187 +4700,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438, - _theResult____h350735, - _theResult____h368374, - _theResult____h396434, - _theResult____h414071, - _theResult____h442129, - _theResult____h459766, - _theResult____h508255, - _theResult____h547108, - _theResult____h586412, - _theResult___snd__h358857, - _theResult___snd__h358868, - _theResult___snd__h358870, - _theResult___snd__h358880, - _theResult___snd__h358886, - _theResult___snd__h358909, - _theResult___snd__h367453, - _theResult___snd__h367455, - _theResult___snd__h367462, - _theResult___snd__h367468, - _theResult___snd__h367491, - _theResult___snd__h376623, - _theResult___snd__h376634, - _theResult___snd__h376636, - _theResult___snd__h376646, - _theResult___snd__h376652, - _theResult___snd__h376675, - _theResult___snd__h385243, - _theResult___snd__h385257, - _theResult___snd__h385263, - _theResult___snd__h385281, - _theResult___snd__h404554, - _theResult___snd__h404565, - _theResult___snd__h404567, - _theResult___snd__h404577, - _theResult___snd__h404583, - _theResult___snd__h404606, - _theResult___snd__h413150, - _theResult___snd__h413152, - _theResult___snd__h413159, - _theResult___snd__h413165, - _theResult___snd__h413188, - _theResult___snd__h422320, - _theResult___snd__h422331, - _theResult___snd__h422333, - _theResult___snd__h422343, - _theResult___snd__h422349, - _theResult___snd__h422372, - _theResult___snd__h430940, - _theResult___snd__h430954, - _theResult___snd__h430960, - _theResult___snd__h430978, - _theResult___snd__h450249, - _theResult___snd__h450260, - _theResult___snd__h450262, - _theResult___snd__h450272, - _theResult___snd__h450278, - _theResult___snd__h450301, - _theResult___snd__h458845, - _theResult___snd__h458847, - _theResult___snd__h458854, - _theResult___snd__h458860, - _theResult___snd__h458883, - _theResult___snd__h468015, - _theResult___snd__h468026, - _theResult___snd__h468028, - _theResult___snd__h468038, - _theResult___snd__h468044, - _theResult___snd__h468067, - _theResult___snd__h476635, - _theResult___snd__h476649, - _theResult___snd__h476655, - _theResult___snd__h476673, - _theResult___snd__h506865, - _theResult___snd__h506867, - _theResult___snd__h506874, - _theResult___snd__h506880, - _theResult___snd__h506903, - _theResult___snd__h516502, - _theResult___snd__h516513, - _theResult___snd__h516515, - _theResult___snd__h516525, - _theResult___snd__h516531, - _theResult___snd__h516554, - _theResult___snd__h525270, - _theResult___snd__h525284, - _theResult___snd__h525290, - _theResult___snd__h525308, - _theResult___snd__h545718, - _theResult___snd__h545720, - _theResult___snd__h545727, - _theResult___snd__h545733, - _theResult___snd__h545756, - _theResult___snd__h555355, - _theResult___snd__h555366, - _theResult___snd__h555368, - _theResult___snd__h555378, - _theResult___snd__h555384, - _theResult___snd__h555407, - _theResult___snd__h564123, - _theResult___snd__h564137, - _theResult___snd__h564143, - _theResult___snd__h564161, - _theResult___snd__h585022, - _theResult___snd__h585024, - _theResult___snd__h585031, - _theResult___snd__h585037, - _theResult___snd__h585060, - _theResult___snd__h594659, - _theResult___snd__h594670, - _theResult___snd__h594672, - _theResult___snd__h594682, - _theResult___snd__h594688, - _theResult___snd__h594711, - _theResult___snd__h603427, - _theResult___snd__h603441, - _theResult___snd__h603447, - _theResult___snd__h603465, - r1__read__h620571, - r1__read__h620707, - r1__read__h620737, - r1__read__h620854, - result__h368987, - result__h414684, - result__h460379, - result__h508868, - result__h547721, - result__h587025, - sfd__h343130, - sfd__h388832, - sfd__h434527, - sfd__h487888, - sfd__h526882, - sfd__h566186, - sfdin__h358840, - sfdin__h376606, - sfdin__h404537, - sfdin__h422303, - sfdin__h450232, - sfdin__h467998, - sfdin__h516485, - sfdin__h555338, - sfdin__h594642, - x__h369084, - x__h414781, - x__h460476, - x__h508963, - x__h547816, - x__h587120; - wire [55 : 0] r1__read__h619398, - r1__read__h619802, - r1__read__h620336, - r1__read__h620573, - r1__read__h620739, - r1__read__h620856; - wire [54 : 0] r1__read__h619400, - r1__read__h619804, - r1__read__h620338, - r1__read__h620575, - r1__read__h620741, - r1__read__h620858; - wire [53 : 0] r1__read__h620684, - r1__read__h620709, - r1__read__h620743, - r1__read__h620860, - sfd__h506932, - sfd__h516583, - sfd__h525343, - sfd__h545785, - sfd__h555436, - sfd__h564196, - sfd__h585089, - sfd__h594740, - sfd__h603500, - value__h351357, - value__h397054, - value__h442749; - wire [52 : 0] r1__read__h620577, - r1__read__h620686, - r1__read__h620711, - r1__read__h620745, - r1__read__h620862; + _theResult____h350736, + _theResult____h368375, + _theResult____h396435, + _theResult____h414072, + _theResult____h442130, + _theResult____h459767, + _theResult____h508256, + _theResult____h547109, + _theResult____h586413, + _theResult___snd__h358858, + _theResult___snd__h358869, + _theResult___snd__h358871, + _theResult___snd__h358881, + _theResult___snd__h358887, + _theResult___snd__h358910, + _theResult___snd__h367454, + _theResult___snd__h367456, + _theResult___snd__h367463, + _theResult___snd__h367469, + _theResult___snd__h367492, + _theResult___snd__h376624, + _theResult___snd__h376635, + _theResult___snd__h376637, + _theResult___snd__h376647, + _theResult___snd__h376653, + _theResult___snd__h376676, + _theResult___snd__h385244, + _theResult___snd__h385258, + _theResult___snd__h385264, + _theResult___snd__h385282, + _theResult___snd__h404555, + _theResult___snd__h404566, + _theResult___snd__h404568, + _theResult___snd__h404578, + _theResult___snd__h404584, + _theResult___snd__h404607, + _theResult___snd__h413151, + _theResult___snd__h413153, + _theResult___snd__h413160, + _theResult___snd__h413166, + _theResult___snd__h413189, + _theResult___snd__h422321, + _theResult___snd__h422332, + _theResult___snd__h422334, + _theResult___snd__h422344, + _theResult___snd__h422350, + _theResult___snd__h422373, + _theResult___snd__h430941, + _theResult___snd__h430955, + _theResult___snd__h430961, + _theResult___snd__h430979, + _theResult___snd__h450250, + _theResult___snd__h450261, + _theResult___snd__h450263, + _theResult___snd__h450273, + _theResult___snd__h450279, + _theResult___snd__h450302, + _theResult___snd__h458846, + _theResult___snd__h458848, + _theResult___snd__h458855, + _theResult___snd__h458861, + _theResult___snd__h458884, + _theResult___snd__h468016, + _theResult___snd__h468027, + _theResult___snd__h468029, + _theResult___snd__h468039, + _theResult___snd__h468045, + _theResult___snd__h468068, + _theResult___snd__h476636, + _theResult___snd__h476650, + _theResult___snd__h476656, + _theResult___snd__h476674, + _theResult___snd__h506866, + _theResult___snd__h506868, + _theResult___snd__h506875, + _theResult___snd__h506881, + _theResult___snd__h506904, + _theResult___snd__h516503, + _theResult___snd__h516514, + _theResult___snd__h516516, + _theResult___snd__h516526, + _theResult___snd__h516532, + _theResult___snd__h516555, + _theResult___snd__h525271, + _theResult___snd__h525285, + _theResult___snd__h525291, + _theResult___snd__h525309, + _theResult___snd__h545719, + _theResult___snd__h545721, + _theResult___snd__h545728, + _theResult___snd__h545734, + _theResult___snd__h545757, + _theResult___snd__h555356, + _theResult___snd__h555367, + _theResult___snd__h555369, + _theResult___snd__h555379, + _theResult___snd__h555385, + _theResult___snd__h555408, + _theResult___snd__h564124, + _theResult___snd__h564138, + _theResult___snd__h564144, + _theResult___snd__h564162, + _theResult___snd__h585023, + _theResult___snd__h585025, + _theResult___snd__h585032, + _theResult___snd__h585038, + _theResult___snd__h585061, + _theResult___snd__h594660, + _theResult___snd__h594671, + _theResult___snd__h594673, + _theResult___snd__h594683, + _theResult___snd__h594689, + _theResult___snd__h594712, + _theResult___snd__h603428, + _theResult___snd__h603442, + _theResult___snd__h603448, + _theResult___snd__h603466, + r1__read__h620572, + r1__read__h620708, + r1__read__h620738, + r1__read__h620855, + result__h368988, + result__h414685, + result__h460380, + result__h508869, + result__h547722, + result__h587026, + sfd__h343131, + sfd__h388833, + sfd__h434528, + sfd__h487889, + sfd__h526883, + sfd__h566187, + sfdin__h358841, + sfdin__h376607, + sfdin__h404538, + sfdin__h422304, + sfdin__h450233, + sfdin__h467999, + sfdin__h516486, + sfdin__h555339, + sfdin__h594643, + x__h369085, + x__h414782, + x__h460477, + x__h508964, + x__h547817, + x__h587121; + wire [55 : 0] r1__read__h619399, + r1__read__h619803, + r1__read__h620337, + r1__read__h620574, + r1__read__h620740, + r1__read__h620857; + wire [54 : 0] r1__read__h619401, + r1__read__h619805, + r1__read__h620339, + r1__read__h620576, + r1__read__h620742, + r1__read__h620859; + wire [53 : 0] r1__read__h620685, + r1__read__h620710, + r1__read__h620744, + r1__read__h620861, + sfd__h506933, + sfd__h516584, + sfd__h525344, + sfd__h545786, + sfd__h555437, + sfd__h564197, + sfd__h585090, + sfd__h594741, + sfd__h603501, + value__h351358, + value__h397055, + value__h442750; + wire [52 : 0] r1__read__h620578, + r1__read__h620687, + r1__read__h620712, + r1__read__h620746, + r1__read__h620863; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251, @@ -4902,109 +4902,109 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992, - _theResult___fst_sfd__h491842, - _theResult___fst_sfd__h507670, - _theResult___fst_sfd__h507673, - _theResult___fst_sfd__h517321, - _theResult___fst_sfd__h517324, - _theResult___fst_sfd__h526105, - _theResult___fst_sfd__h526108, - _theResult___fst_sfd__h526117, - _theResult___fst_sfd__h526123, - _theResult___fst_sfd__h530695, - _theResult___fst_sfd__h546523, - _theResult___fst_sfd__h546526, - _theResult___fst_sfd__h556174, - _theResult___fst_sfd__h556177, - _theResult___fst_sfd__h564958, - _theResult___fst_sfd__h564961, - _theResult___fst_sfd__h564970, - _theResult___fst_sfd__h564976, - _theResult___fst_sfd__h569999, - _theResult___fst_sfd__h585827, - _theResult___fst_sfd__h585830, - _theResult___fst_sfd__h595478, - _theResult___fst_sfd__h595481, - _theResult___fst_sfd__h604262, - _theResult___fst_sfd__h604265, - _theResult___fst_sfd__h604274, - _theResult___fst_sfd__h604280, - _theResult___sfd__h507570, - _theResult___sfd__h517221, - _theResult___sfd__h526005, - _theResult___sfd__h546423, - _theResult___sfd__h556074, - _theResult___sfd__h564858, - _theResult___sfd__h585727, - _theResult___sfd__h595378, - _theResult___sfd__h604162, - _theResult___snd_fst_sfd__h487842, - _theResult___snd_fst_sfd__h507676, - _theResult___snd_fst_sfd__h526111, - _theResult___snd_fst_sfd__h526836, - _theResult___snd_fst_sfd__h546529, - _theResult___snd_fst_sfd__h564964, - _theResult___snd_fst_sfd__h566140, - _theResult___snd_fst_sfd__h585833, - _theResult___snd_fst_sfd__h604268, - out___1_sfd__h487590, - out___1_sfd__h526584, - out___1_sfd__h565888, - out_sfd__h507573, - out_sfd__h517224, - out_sfd__h526008, - out_sfd__h546426, - out_sfd__h556077, - out_sfd__h564861, - out_sfd__h585730, - out_sfd__h595381, - out_sfd__h604165; - wire [50 : 0] r1__read__h619402, r1__read__h620579; - wire [49 : 0] r1__read__h620688; - wire [48 : 0] r1__read__h619404, r1__read__h620581, r1__read__h620690; - wire [46 : 0] r1__read__h619406, r1__read__h620583; - wire [45 : 0] r1__read__h619408, r1__read__h620585; - wire [44 : 0] r1__read__h619410, r1__read__h620587; - wire [43 : 0] r1__read__h619412, r1__read__h620589; - wire [42 : 0] r1__read__h620591; - wire [41 : 0] r1__read__h620593; - wire [40 : 0] r1__read__h620595; + _theResult___fst_sfd__h491843, + _theResult___fst_sfd__h507671, + _theResult___fst_sfd__h507674, + _theResult___fst_sfd__h517322, + _theResult___fst_sfd__h517325, + _theResult___fst_sfd__h526106, + _theResult___fst_sfd__h526109, + _theResult___fst_sfd__h526118, + _theResult___fst_sfd__h526124, + _theResult___fst_sfd__h530696, + _theResult___fst_sfd__h546524, + _theResult___fst_sfd__h546527, + _theResult___fst_sfd__h556175, + _theResult___fst_sfd__h556178, + _theResult___fst_sfd__h564959, + _theResult___fst_sfd__h564962, + _theResult___fst_sfd__h564971, + _theResult___fst_sfd__h564977, + _theResult___fst_sfd__h570000, + _theResult___fst_sfd__h585828, + _theResult___fst_sfd__h585831, + _theResult___fst_sfd__h595479, + _theResult___fst_sfd__h595482, + _theResult___fst_sfd__h604263, + _theResult___fst_sfd__h604266, + _theResult___fst_sfd__h604275, + _theResult___fst_sfd__h604281, + _theResult___sfd__h507571, + _theResult___sfd__h517222, + _theResult___sfd__h526006, + _theResult___sfd__h546424, + _theResult___sfd__h556075, + _theResult___sfd__h564859, + _theResult___sfd__h585728, + _theResult___sfd__h595379, + _theResult___sfd__h604163, + _theResult___snd_fst_sfd__h487843, + _theResult___snd_fst_sfd__h507677, + _theResult___snd_fst_sfd__h526112, + _theResult___snd_fst_sfd__h526837, + _theResult___snd_fst_sfd__h546530, + _theResult___snd_fst_sfd__h564965, + _theResult___snd_fst_sfd__h566141, + _theResult___snd_fst_sfd__h585834, + _theResult___snd_fst_sfd__h604269, + out___1_sfd__h487591, + out___1_sfd__h526585, + out___1_sfd__h565889, + out_sfd__h507574, + out_sfd__h517225, + out_sfd__h526009, + out_sfd__h546427, + out_sfd__h556078, + out_sfd__h564862, + out_sfd__h585731, + out_sfd__h595382, + out_sfd__h604166; + wire [50 : 0] r1__read__h619403, r1__read__h620580; + wire [49 : 0] r1__read__h620689; + wire [48 : 0] r1__read__h619405, r1__read__h620582, r1__read__h620691; + wire [46 : 0] r1__read__h619407, r1__read__h620584; + wire [45 : 0] r1__read__h619409, r1__read__h620586; + wire [44 : 0] r1__read__h619411, r1__read__h620588; + wire [43 : 0] r1__read__h619413, r1__read__h620590; + wire [42 : 0] r1__read__h620592; + wire [41 : 0] r1__read__h620594; + wire [40 : 0] r1__read__h620596; wire [37 : 0] IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14222, IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14383; wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5, - data79261_BITS_31_TO_0__q2, - data80193_BITS_31_TO_0__q6, - imm__h661837, - r1__read__h619414, - r1__read__h620597, - x__h196066, - x__h342534, - x__h388236, - x__h433931, - x__h75784, - x_data__h65633, - x_data_imm__h681437, - x_data_imm__h697341; - wire [29 : 0] r1__read__h619416, r1__read__h620599; - wire [27 : 0] r1__read__h620601; + data79262_BITS_31_TO_0__q2, + data80194_BITS_31_TO_0__q6, + imm__h661838, + r1__read__h619415, + r1__read__h620598, + x__h196067, + x__h342535, + x__h388237, + x__h433932, + x__h75785, + x_data__h65634, + x_data_imm__h681438, + x_data_imm__h697342; + wire [29 : 0] r1__read__h619417, r1__read__h620600; + wire [27 : 0] r1__read__h620602; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14268, - sfd__h358938, - sfd__h367520, - sfd__h376704, - sfd__h385316, - sfd__h404635, - sfd__h413217, - sfd__h422401, - sfd__h431013, - sfd__h450330, - sfd__h458912, - sfd__h468096, - sfd__h476708, - value__h492471, - value__h531324, - value__h570628; + sfd__h358939, + sfd__h367521, + sfd__h376705, + sfd__h385317, + sfd__h404636, + sfd__h413218, + sfd__h422402, + sfd__h431014, + sfd__h450331, + sfd__h458913, + sfd__h468097, + sfd__h476709, + value__h492472, + value__h531325, + value__h570629; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445, @@ -5029,67 +5029,67 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904, - _theResult___fst_sfd__h359444, - _theResult___fst_sfd__h368026, - _theResult___fst_sfd__h377210, - _theResult___fst_sfd__h385846, - _theResult___fst_sfd__h385855, - _theResult___fst_sfd__h385861, - _theResult___fst_sfd__h405141, - _theResult___fst_sfd__h413723, - _theResult___fst_sfd__h422907, - _theResult___fst_sfd__h431543, - _theResult___fst_sfd__h431552, - _theResult___fst_sfd__h431558, - _theResult___fst_sfd__h450836, - _theResult___fst_sfd__h459418, - _theResult___fst_sfd__h468602, - _theResult___fst_sfd__h477238, - _theResult___fst_sfd__h477247, - _theResult___fst_sfd__h477253, - _theResult___sfd__h359363, - _theResult___sfd__h367945, - _theResult___sfd__h377129, - _theResult___sfd__h385765, - _theResult___sfd__h385867, - _theResult___sfd__h405060, - _theResult___sfd__h413642, - _theResult___sfd__h422826, - _theResult___sfd__h431462, - _theResult___sfd__h431564, - _theResult___sfd__h450755, - _theResult___sfd__h459337, - _theResult___sfd__h468521, - _theResult___sfd__h477157, - _theResult___sfd__h477259, - _theResult___snd_fst_sfd__h343080, - _theResult___snd_fst_sfd__h368029, - _theResult___snd_fst_sfd__h385849, - _theResult___snd_fst_sfd__h388782, - _theResult___snd_fst_sfd__h413726, - _theResult___snd_fst_sfd__h431546, - _theResult___snd_fst_sfd__h434477, - _theResult___snd_fst_sfd__h459421, - _theResult___snd_fst_sfd__h477241, - f1_sfd__h487527, - f2_sfd__h526521, - f3_sfd__h565825, - out_f_sfd__h386144, - out_f_sfd__h431841, - out_f_sfd__h477536, - out_sfd__h359366, - out_sfd__h367948, - out_sfd__h377132, - out_sfd__h385768, - out_sfd__h405063, - out_sfd__h413645, - out_sfd__h422829, - out_sfd__h431465, - out_sfd__h450758, - out_sfd__h459340, - out_sfd__h468524, - out_sfd__h477160; - wire [19 : 0] r1__read__h620536; + _theResult___fst_sfd__h359445, + _theResult___fst_sfd__h368027, + _theResult___fst_sfd__h377211, + _theResult___fst_sfd__h385847, + _theResult___fst_sfd__h385856, + _theResult___fst_sfd__h385862, + _theResult___fst_sfd__h405142, + _theResult___fst_sfd__h413724, + _theResult___fst_sfd__h422908, + _theResult___fst_sfd__h431544, + _theResult___fst_sfd__h431553, + _theResult___fst_sfd__h431559, + _theResult___fst_sfd__h450837, + _theResult___fst_sfd__h459419, + _theResult___fst_sfd__h468603, + _theResult___fst_sfd__h477239, + _theResult___fst_sfd__h477248, + _theResult___fst_sfd__h477254, + _theResult___sfd__h359364, + _theResult___sfd__h367946, + _theResult___sfd__h377130, + _theResult___sfd__h385766, + _theResult___sfd__h385868, + _theResult___sfd__h405061, + _theResult___sfd__h413643, + _theResult___sfd__h422827, + _theResult___sfd__h431463, + _theResult___sfd__h431565, + _theResult___sfd__h450756, + _theResult___sfd__h459338, + _theResult___sfd__h468522, + _theResult___sfd__h477158, + _theResult___sfd__h477260, + _theResult___snd_fst_sfd__h343081, + _theResult___snd_fst_sfd__h368030, + _theResult___snd_fst_sfd__h385850, + _theResult___snd_fst_sfd__h388783, + _theResult___snd_fst_sfd__h413727, + _theResult___snd_fst_sfd__h431547, + _theResult___snd_fst_sfd__h434478, + _theResult___snd_fst_sfd__h459422, + _theResult___snd_fst_sfd__h477242, + f1_sfd__h487528, + f2_sfd__h526522, + f3_sfd__h565826, + out_f_sfd__h386145, + out_f_sfd__h431842, + out_f_sfd__h477537, + out_sfd__h359367, + out_sfd__h367949, + out_sfd__h377133, + out_sfd__h385769, + out_sfd__h405064, + out_sfd__h413646, + out_sfd__h422830, + out_sfd__h431466, + out_sfd__h450759, + out_sfd__h459341, + out_sfd__h468525, + out_sfd__h477161; + wire [19 : 0] r1__read__h620537; wire [12 : 0] fetchStage_pipelines_1_first__2937_BIT_173_368_ETC___d13770; wire [11 : 0] IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992, IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542, @@ -5120,30 +5120,30 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434, - _theResult____h658026, - csr_addr__h661835, - enabled_ints___1__h658439, - enabled_ints__h658485, - pend_ints__h658024, - renaming_spec_bits__h689556, - result__h653733, - result__h653784, - spec_bits__h692683, - w__h653728, - x__h369117, - x__h414814, - x__h460509, - x__h508996, - x__h547849, - x__h587153, - x__h653732, - x__h653783, - y__h653762, - y__h658451, - y__h692696, - y_avValue_fst__h685980, - y_avValue_snd_fst__h686254, - y_avValue_snd_fst__h686289; + _theResult____h658027, + csr_addr__h661836, + enabled_ints___1__h658440, + enabled_ints__h658486, + pend_ints__h658025, + renaming_spec_bits__h689557, + result__h653734, + result__h653785, + spec_bits__h692684, + w__h653729, + x__h369118, + x__h414815, + x__h460510, + x__h508997, + x__h547850, + x__h587154, + x__h653733, + x__h653784, + y__h653763, + y__h658452, + y__h692697, + y_avValue_fst__h685981, + y_avValue_snd_fst__h686255, + y_avValue_snd_fst__h686290; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167, @@ -5165,103 +5165,103 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172, - _theResult___exp__h507569, - _theResult___exp__h517220, - _theResult___exp__h526004, - _theResult___exp__h546422, - _theResult___exp__h556073, - _theResult___exp__h564857, - _theResult___exp__h585726, - _theResult___exp__h595377, - _theResult___exp__h604161, - _theResult___fst_exp__h491841, - _theResult___fst_exp__h506905, - _theResult___fst_exp__h506911, - _theResult___fst_exp__h506914, - _theResult___fst_exp__h507669, - _theResult___fst_exp__h507672, - _theResult___fst_exp__h516491, - _theResult___fst_exp__h516556, - _theResult___fst_exp__h516562, - _theResult___fst_exp__h516565, - _theResult___fst_exp__h517320, - _theResult___fst_exp__h517323, - _theResult___fst_exp__h525276, - _theResult___fst_exp__h525315, - _theResult___fst_exp__h525321, - _theResult___fst_exp__h525324, - _theResult___fst_exp__h526104, - _theResult___fst_exp__h526107, - _theResult___fst_exp__h526116, - _theResult___fst_exp__h526119, - _theResult___fst_exp__h530694, - _theResult___fst_exp__h545758, - _theResult___fst_exp__h545764, - _theResult___fst_exp__h545767, - _theResult___fst_exp__h546522, - _theResult___fst_exp__h546525, - _theResult___fst_exp__h555344, - _theResult___fst_exp__h555409, - _theResult___fst_exp__h555415, - _theResult___fst_exp__h555418, - _theResult___fst_exp__h556173, - _theResult___fst_exp__h556176, - _theResult___fst_exp__h564129, - _theResult___fst_exp__h564168, - _theResult___fst_exp__h564174, - _theResult___fst_exp__h564177, - _theResult___fst_exp__h564957, - _theResult___fst_exp__h564960, - _theResult___fst_exp__h564969, - _theResult___fst_exp__h564972, - _theResult___fst_exp__h569998, - _theResult___fst_exp__h585062, - _theResult___fst_exp__h585068, - _theResult___fst_exp__h585071, - _theResult___fst_exp__h585826, - _theResult___fst_exp__h585829, - _theResult___fst_exp__h594648, - _theResult___fst_exp__h594713, - _theResult___fst_exp__h594719, - _theResult___fst_exp__h594722, - _theResult___fst_exp__h595477, - _theResult___fst_exp__h595480, - _theResult___fst_exp__h603433, - _theResult___fst_exp__h603472, - _theResult___fst_exp__h603478, - _theResult___fst_exp__h603481, - _theResult___fst_exp__h604261, - _theResult___fst_exp__h604264, - _theResult___fst_exp__h604273, - _theResult___fst_exp__h604276, - _theResult___snd_fst_exp__h507675, - _theResult___snd_fst_exp__h526110, - _theResult___snd_fst_exp__h546528, - _theResult___snd_fst_exp__h564963, - _theResult___snd_fst_exp__h585832, - _theResult___snd_fst_exp__h604267, + _theResult___exp__h507570, + _theResult___exp__h517221, + _theResult___exp__h526005, + _theResult___exp__h546423, + _theResult___exp__h556074, + _theResult___exp__h564858, + _theResult___exp__h585727, + _theResult___exp__h595378, + _theResult___exp__h604162, + _theResult___fst_exp__h491842, + _theResult___fst_exp__h506906, + _theResult___fst_exp__h506912, + _theResult___fst_exp__h506915, + _theResult___fst_exp__h507670, + _theResult___fst_exp__h507673, + _theResult___fst_exp__h516492, + _theResult___fst_exp__h516557, + _theResult___fst_exp__h516563, + _theResult___fst_exp__h516566, + _theResult___fst_exp__h517321, + _theResult___fst_exp__h517324, + _theResult___fst_exp__h525277, + _theResult___fst_exp__h525316, + _theResult___fst_exp__h525322, + _theResult___fst_exp__h525325, + _theResult___fst_exp__h526105, + _theResult___fst_exp__h526108, + _theResult___fst_exp__h526117, + _theResult___fst_exp__h526120, + _theResult___fst_exp__h530695, + _theResult___fst_exp__h545759, + _theResult___fst_exp__h545765, + _theResult___fst_exp__h545768, + _theResult___fst_exp__h546523, + _theResult___fst_exp__h546526, + _theResult___fst_exp__h555345, + _theResult___fst_exp__h555410, + _theResult___fst_exp__h555416, + _theResult___fst_exp__h555419, + _theResult___fst_exp__h556174, + _theResult___fst_exp__h556177, + _theResult___fst_exp__h564130, + _theResult___fst_exp__h564169, + _theResult___fst_exp__h564175, + _theResult___fst_exp__h564178, + _theResult___fst_exp__h564958, + _theResult___fst_exp__h564961, + _theResult___fst_exp__h564970, + _theResult___fst_exp__h564973, + _theResult___fst_exp__h569999, + _theResult___fst_exp__h585063, + _theResult___fst_exp__h585069, + _theResult___fst_exp__h585072, + _theResult___fst_exp__h585827, + _theResult___fst_exp__h585830, + _theResult___fst_exp__h594649, + _theResult___fst_exp__h594714, + _theResult___fst_exp__h594720, + _theResult___fst_exp__h594723, + _theResult___fst_exp__h595478, + _theResult___fst_exp__h595481, + _theResult___fst_exp__h603434, + _theResult___fst_exp__h603473, + _theResult___fst_exp__h603479, + _theResult___fst_exp__h603482, + _theResult___fst_exp__h604262, + _theResult___fst_exp__h604265, + _theResult___fst_exp__h604274, + _theResult___fst_exp__h604277, + _theResult___snd_fst_exp__h507676, + _theResult___snd_fst_exp__h526111, + _theResult___snd_fst_exp__h546529, + _theResult___snd_fst_exp__h564964, + _theResult___snd_fst_exp__h585833, + _theResult___snd_fst_exp__h604268, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99, - din_inc___2_exp__h526164, - din_inc___2_exp__h526199, - din_inc___2_exp__h526225, - din_inc___2_exp__h565017, - din_inc___2_exp__h565052, - din_inc___2_exp__h565078, - din_inc___2_exp__h604321, - din_inc___2_exp__h604356, - din_inc___2_exp__h604382, - out_exp__h507572, - out_exp__h517223, - out_exp__h526007, - out_exp__h546425, - out_exp__h556076, - out_exp__h564860, - out_exp__h585729, - out_exp__h595380, - out_exp__h604164; - wire [9 : 0] r1__read_BITS_9_TO_0___h658461; + din_inc___2_exp__h526165, + din_inc___2_exp__h526200, + din_inc___2_exp__h526226, + din_inc___2_exp__h565018, + din_inc___2_exp__h565053, + din_inc___2_exp__h565079, + din_inc___2_exp__h604322, + din_inc___2_exp__h604357, + din_inc___2_exp__h604383, + out_exp__h507573, + out_exp__h517224, + out_exp__h526008, + out_exp__h546426, + out_exp__h556077, + out_exp__h564861, + out_exp__h585730, + out_exp__h595381, + out_exp__h604165; + wire [9 : 0] r1__read_BITS_9_TO_0___h658462; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752; @@ -5292,125 +5292,125 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105, - _theResult___exp__h359362, - _theResult___exp__h367944, - _theResult___exp__h377128, - _theResult___exp__h385764, - _theResult___exp__h385866, - _theResult___exp__h405059, - _theResult___exp__h413641, - _theResult___exp__h422825, - _theResult___exp__h431461, - _theResult___exp__h431563, - _theResult___exp__h450754, - _theResult___exp__h459336, - _theResult___exp__h468520, - _theResult___exp__h477156, - _theResult___exp__h477258, - _theResult___fst_exp__h358846, - _theResult___fst_exp__h358911, - _theResult___fst_exp__h358917, - _theResult___fst_exp__h358920, - _theResult___fst_exp__h359443, - _theResult___fst_exp__h367493, - _theResult___fst_exp__h367499, - _theResult___fst_exp__h367502, - _theResult___fst_exp__h368025, - _theResult___fst_exp__h376612, - _theResult___fst_exp__h376677, - _theResult___fst_exp__h376683, - _theResult___fst_exp__h376686, - _theResult___fst_exp__h377209, - _theResult___fst_exp__h385249, - _theResult___fst_exp__h385288, - _theResult___fst_exp__h385294, - _theResult___fst_exp__h385297, - _theResult___fst_exp__h385845, - _theResult___fst_exp__h385854, - _theResult___fst_exp__h385857, - _theResult___fst_exp__h404543, - _theResult___fst_exp__h404608, - _theResult___fst_exp__h404614, - _theResult___fst_exp__h404617, - _theResult___fst_exp__h405140, - _theResult___fst_exp__h413190, - _theResult___fst_exp__h413196, - _theResult___fst_exp__h413199, - _theResult___fst_exp__h413722, - _theResult___fst_exp__h422309, - _theResult___fst_exp__h422374, - _theResult___fst_exp__h422380, - _theResult___fst_exp__h422383, - _theResult___fst_exp__h422906, - _theResult___fst_exp__h430946, - _theResult___fst_exp__h430985, - _theResult___fst_exp__h430991, - _theResult___fst_exp__h430994, - _theResult___fst_exp__h431542, - _theResult___fst_exp__h431551, - _theResult___fst_exp__h431554, - _theResult___fst_exp__h450238, - _theResult___fst_exp__h450303, - _theResult___fst_exp__h450309, - _theResult___fst_exp__h450312, - _theResult___fst_exp__h450835, - _theResult___fst_exp__h458885, - _theResult___fst_exp__h458891, - _theResult___fst_exp__h458894, - _theResult___fst_exp__h459417, - _theResult___fst_exp__h468004, - _theResult___fst_exp__h468069, - _theResult___fst_exp__h468075, - _theResult___fst_exp__h468078, - _theResult___fst_exp__h468601, - _theResult___fst_exp__h476641, - _theResult___fst_exp__h476680, - _theResult___fst_exp__h476686, - _theResult___fst_exp__h476689, - _theResult___fst_exp__h477237, - _theResult___fst_exp__h477246, - _theResult___fst_exp__h477249, - _theResult___snd_fst_exp__h368028, - _theResult___snd_fst_exp__h385848, - _theResult___snd_fst_exp__h413725, - _theResult___snd_fst_exp__h431545, - _theResult___snd_fst_exp__h459420, - _theResult___snd_fst_exp__h477240, + _theResult___exp__h359363, + _theResult___exp__h367945, + _theResult___exp__h377129, + _theResult___exp__h385765, + _theResult___exp__h385867, + _theResult___exp__h405060, + _theResult___exp__h413642, + _theResult___exp__h422826, + _theResult___exp__h431462, + _theResult___exp__h431564, + _theResult___exp__h450755, + _theResult___exp__h459337, + _theResult___exp__h468521, + _theResult___exp__h477157, + _theResult___exp__h477259, + _theResult___fst_exp__h358847, + _theResult___fst_exp__h358912, + _theResult___fst_exp__h358918, + _theResult___fst_exp__h358921, + _theResult___fst_exp__h359444, + _theResult___fst_exp__h367494, + _theResult___fst_exp__h367500, + _theResult___fst_exp__h367503, + _theResult___fst_exp__h368026, + _theResult___fst_exp__h376613, + _theResult___fst_exp__h376678, + _theResult___fst_exp__h376684, + _theResult___fst_exp__h376687, + _theResult___fst_exp__h377210, + _theResult___fst_exp__h385250, + _theResult___fst_exp__h385289, + _theResult___fst_exp__h385295, + _theResult___fst_exp__h385298, + _theResult___fst_exp__h385846, + _theResult___fst_exp__h385855, + _theResult___fst_exp__h385858, + _theResult___fst_exp__h404544, + _theResult___fst_exp__h404609, + _theResult___fst_exp__h404615, + _theResult___fst_exp__h404618, + _theResult___fst_exp__h405141, + _theResult___fst_exp__h413191, + _theResult___fst_exp__h413197, + _theResult___fst_exp__h413200, + _theResult___fst_exp__h413723, + _theResult___fst_exp__h422310, + _theResult___fst_exp__h422375, + _theResult___fst_exp__h422381, + _theResult___fst_exp__h422384, + _theResult___fst_exp__h422907, + _theResult___fst_exp__h430947, + _theResult___fst_exp__h430986, + _theResult___fst_exp__h430992, + _theResult___fst_exp__h430995, + _theResult___fst_exp__h431543, + _theResult___fst_exp__h431552, + _theResult___fst_exp__h431555, + _theResult___fst_exp__h450239, + _theResult___fst_exp__h450304, + _theResult___fst_exp__h450310, + _theResult___fst_exp__h450313, + _theResult___fst_exp__h450836, + _theResult___fst_exp__h458886, + _theResult___fst_exp__h458892, + _theResult___fst_exp__h458895, + _theResult___fst_exp__h459418, + _theResult___fst_exp__h468005, + _theResult___fst_exp__h468070, + _theResult___fst_exp__h468076, + _theResult___fst_exp__h468079, + _theResult___fst_exp__h468602, + _theResult___fst_exp__h476642, + _theResult___fst_exp__h476681, + _theResult___fst_exp__h476687, + _theResult___fst_exp__h476690, + _theResult___fst_exp__h477238, + _theResult___fst_exp__h477247, + _theResult___fst_exp__h477250, + _theResult___snd_fst_exp__h368029, + _theResult___snd_fst_exp__h385849, + _theResult___snd_fst_exp__h413726, + _theResult___snd_fst_exp__h431546, + _theResult___snd_fst_exp__h459421, + _theResult___snd_fst_exp__h477241, csrf_external_int_en_vec_3_read__1844_AND_csrf_ETC___d12967, - din_inc___2_exp__h385879, - din_inc___2_exp__h385903, - din_inc___2_exp__h385933, - din_inc___2_exp__h385957, - din_inc___2_exp__h431576, - din_inc___2_exp__h431600, - din_inc___2_exp__h431630, - din_inc___2_exp__h431654, - din_inc___2_exp__h477271, - din_inc___2_exp__h477295, - din_inc___2_exp__h477325, - din_inc___2_exp__h477349, - f1_exp87526_MINUS_127__q128, - f1_exp__h487526, - f2_exp26520_MINUS_127__q168, - f2_exp__h526520, - f3_exp65824_MINUS_127__q145, - f3_exp__h565824, - out_exp__h359365, - out_exp__h367947, - out_exp__h377131, - out_exp__h385767, - out_exp__h405062, - out_exp__h413644, - out_exp__h422828, - out_exp__h431464, - out_exp__h450757, - out_exp__h459339, - out_exp__h468523, - out_exp__h477159, - out_f_exp__h386143, - out_f_exp__h431840, - out_f_exp__h477535, - x__h619373; + din_inc___2_exp__h385880, + din_inc___2_exp__h385904, + din_inc___2_exp__h385934, + din_inc___2_exp__h385958, + din_inc___2_exp__h431577, + din_inc___2_exp__h431601, + din_inc___2_exp__h431631, + din_inc___2_exp__h431655, + din_inc___2_exp__h477272, + din_inc___2_exp__h477296, + din_inc___2_exp__h477326, + din_inc___2_exp__h477350, + f1_exp87527_MINUS_127__q128, + f1_exp__h487527, + f2_exp26521_MINUS_127__q168, + f2_exp__h526521, + f3_exp65825_MINUS_127__q145, + f3_exp__h565825, + out_exp__h359366, + out_exp__h367948, + out_exp__h377132, + out_exp__h385768, + out_exp__h405063, + out_exp__h413645, + out_exp__h422829, + out_exp__h431465, + out_exp__h450758, + out_exp__h459340, + out_exp__h468524, + out_exp__h477160, + out_f_exp__h386144, + out_f_exp__h431841, + out_f_exp__h477536, + x__h619374; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127, @@ -5431,8 +5431,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15324, - x__h184871, - x__h710696; + x__h184872, + x__h710697; wire [4 : 0] IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14436, IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265, @@ -5452,19 +5452,19 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061, checkForException___d13160, checkForException___d13792, - fflags__h722585, - r1__read__h620939, - res_fflags__h342520, - res_fflags__h388222, - res_fflags__h433917, - rs1__h661836, - x__h155091, - x__h158638, - x__h161454, - x__h291824, - y_avValue_fst__h721562, - y_avValue_fst__h722504, - y_avValue_fst__h722532; + fflags__h722586, + r1__read__h620940, + res_fflags__h342521, + res_fflags__h388223, + res_fflags__h433918, + rs1__h661837, + x__h155092, + x__h158639, + x__h161455, + x__h291825, + y_avValue_fst__h721563, + y_avValue_fst__h722505, + y_avValue_fst__h722533; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877, IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879, @@ -5491,74 +5491,74 @@ module mkCore(CLK, IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13385, - cause_code__h707758, - vm_mode_reg__read__h620542; + cause_code__h707759, + vm_mode_reg__read__h620543; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, - _theResult_____2__h301171, - next_deqP___1__h301450, - v__h300591, - v__h300822, - x__h306801, - x_decodeInfo_frm__h661520; + _theResult_____2__h301172, + next_deqP___1__h301451, + v__h300592, + v__h300823, + x__h306802, + x_decodeInfo_frm__h661521; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205, - IF_sfdin04537_BIT_33_THEN_2_ELSE_0__q57, - IF_sfdin16485_BIT_4_THEN_2_ELSE_0__q131, - IF_sfdin22303_BIT_33_THEN_2_ELSE_0__q67, - IF_sfdin50232_BIT_33_THEN_2_ELSE_0__q92, - IF_sfdin55338_BIT_4_THEN_2_ELSE_0__q171, - IF_sfdin58840_BIT_33_THEN_2_ELSE_0__q22, - IF_sfdin67998_BIT_33_THEN_2_ELSE_0__q102, - IF_sfdin76606_BIT_33_THEN_2_ELSE_0__q32, - IF_sfdin94642_BIT_4_THEN_2_ELSE_0__q148, - IF_theResult___snd03427_BIT_4_THEN_2_ELSE_0__q151, - IF_theResult___snd06865_BIT_4_THEN_2_ELSE_0__q127, - IF_theResult___snd13150_BIT_33_THEN_2_ELSE_0__q59, - IF_theResult___snd25270_BIT_4_THEN_2_ELSE_0__q134, - IF_theResult___snd30940_BIT_33_THEN_2_ELSE_0__q72, - IF_theResult___snd45718_BIT_4_THEN_2_ELSE_0__q167, - IF_theResult___snd58845_BIT_33_THEN_2_ELSE_0__q94, - IF_theResult___snd64123_BIT_4_THEN_2_ELSE_0__q174, - IF_theResult___snd67453_BIT_33_THEN_2_ELSE_0__q24, - IF_theResult___snd76635_BIT_33_THEN_2_ELSE_0__q107, - IF_theResult___snd85022_BIT_4_THEN_2_ELSE_0__q144, - IF_theResult___snd85243_BIT_33_THEN_2_ELSE_0__q37, - guard__h350745, - guard__h359454, - guard__h368384, - guard__h377220, - guard__h396444, - guard__h405151, - guard__h414081, - guard__h422917, - guard__h442139, - guard__h450846, - guard__h459776, - guard__h468612, - guard__h498953, - guard__h508265, - guard__h517334, - guard__h537806, - guard__h547118, - guard__h556187, - guard__h577110, - guard__h586422, - guard__h595491, - prv__h724099, - prv__h724143, - r1__read_BITS_13_TO_12___h661705, - sbIdx__h158517, - v__h609619, - v__h609629, - v__h610687, - x__h718767, - x__h722832, - y_avValue_snd_snd_snd_fst__h721996, - y_avValue_snd_snd_snd_fst__h722655, - y_avValue_snd_snd_snd_fst__h722684; + IF_sfdin04538_BIT_33_THEN_2_ELSE_0__q57, + IF_sfdin16486_BIT_4_THEN_2_ELSE_0__q131, + IF_sfdin22304_BIT_33_THEN_2_ELSE_0__q67, + IF_sfdin50233_BIT_33_THEN_2_ELSE_0__q92, + IF_sfdin55339_BIT_4_THEN_2_ELSE_0__q171, + IF_sfdin58841_BIT_33_THEN_2_ELSE_0__q22, + IF_sfdin67999_BIT_33_THEN_2_ELSE_0__q102, + IF_sfdin76607_BIT_33_THEN_2_ELSE_0__q32, + IF_sfdin94643_BIT_4_THEN_2_ELSE_0__q148, + IF_theResult___snd03428_BIT_4_THEN_2_ELSE_0__q151, + IF_theResult___snd06866_BIT_4_THEN_2_ELSE_0__q127, + IF_theResult___snd13151_BIT_33_THEN_2_ELSE_0__q59, + IF_theResult___snd25271_BIT_4_THEN_2_ELSE_0__q134, + IF_theResult___snd30941_BIT_33_THEN_2_ELSE_0__q72, + IF_theResult___snd45719_BIT_4_THEN_2_ELSE_0__q167, + IF_theResult___snd58846_BIT_33_THEN_2_ELSE_0__q94, + IF_theResult___snd64124_BIT_4_THEN_2_ELSE_0__q174, + IF_theResult___snd67454_BIT_33_THEN_2_ELSE_0__q24, + IF_theResult___snd76636_BIT_33_THEN_2_ELSE_0__q107, + IF_theResult___snd85023_BIT_4_THEN_2_ELSE_0__q144, + IF_theResult___snd85244_BIT_33_THEN_2_ELSE_0__q37, + guard__h350746, + guard__h359455, + guard__h368385, + guard__h377221, + guard__h396445, + guard__h405152, + guard__h414082, + guard__h422918, + guard__h442140, + guard__h450847, + guard__h459777, + guard__h468613, + guard__h498954, + guard__h508266, + guard__h517335, + guard__h537807, + guard__h547119, + guard__h556188, + guard__h577111, + guard__h586423, + guard__h595492, + prv__h724100, + prv__h724144, + r1__read_BITS_13_TO_12___h661706, + sbIdx__h158518, + v__h609620, + v__h609630, + v__h610688, + x__h718768, + x__h722833, + y_avValue_snd_snd_snd_fst__h721997, + y_avValue_snd_snd_snd_fst__h722656, + y_avValue_snd_snd_snd_fst__h722685; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557, @@ -6011,11 +6011,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h309167, - _theResult_____2__h315161, - _theResult_____2__h323015, - _theResult_____2__h333359, - _theResult_____2__h336584, + _theResult_____2__h309168, + _theResult_____2__h315162, + _theResult_____2__h323016, + _theResult_____2__h333360, + _theResult_____2__h336585, coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369, coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410, coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382, @@ -6166,14 +6166,14 @@ module mkCore(CLK, fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14054, fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13889, fetchStage_pipelines_1_first__2937_BIT_68_3660_ETC___d14058, - guard__h368982, - guard__h414679, - guard__h460374, - guard__h508863, - guard__h547716, - guard__h587020, - idx__h689687, - k__h674092, + guard__h368983, + guard__h414680, + guard__h460375, + guard__h508864, + guard__h547717, + guard__h587021, + idx__h689688, + k__h674093, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6184,14 +6184,14 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14165, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h75669, - next_deqP___1__h309446, - next_deqP___1__h315727, - next_deqP___1__h323581, - next_deqP___1__h333638, - next_deqP___1__h336863, - r1__read_BIT_20___h662369, - r__h619420, + msip__h75670, + next_deqP___1__h309447, + next_deqP___1__h315728, + next_deqP___1__h323582, + next_deqP___1__h333639, + next_deqP___1__h336864, + r1__read_BIT_20___h662370, + r__h619421, regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407, regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14022, regRenamingTable_RDY_rename_1_getRename__4078__ETC___d14096, @@ -6215,17 +6215,17 @@ module mkCore(CLK, rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13826, rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13960, rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13977, - v__h303936, - v__h304454, - v__h314450, - v__h314681, - v__h318326, - v__h318557, - v__h332927, - v__h333158, - v__h336152, - v__h336383, - x__h608935; + v__h303937, + v__h304455, + v__h314451, + v__h314682, + v__h318327, + v__h318558, + v__h332928, + v__h333159, + v__h336153, + v__h336384, + x__h608936; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -11034,7 +11034,7 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[353:290], - x__h704087, + x__h704088, rob$deqPort_0_deq_data[166], rob$deqPort_0_deq_data[166] ? CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 : @@ -11043,7 +11043,7 @@ module mkCore(CLK, assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_2 = - commitStage_rg_serial_num + y__h722608 ; + commitStage_rg_serial_num + y__h722609 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, @@ -11057,7 +11057,7 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h674092 == 1'd0 && + (k__h674093 == 1'd0 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, @@ -11078,7 +11078,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689556, + renaming_spec_bits__h689557, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -11169,7 +11169,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787, @@ -11183,10 +11183,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h290391 } ; + x__h290392 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h291836, + x__h291837, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -11194,7 +11194,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h294612, + addr__h294613, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -11207,12 +11207,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h155091, x__h155097, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h155092, x__h155098, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h158638, x__h158644, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h158639, x__h158645, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h161454, - x__h161458, + { x__h161455, + x__h161459, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, @@ -11223,7 +11223,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255, - x__h163306, + x__h163307, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, @@ -11236,7 +11236,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h296627, + resp_addr__h296628, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -11316,7 +11316,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h200346 } ; + x__h200347 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -11351,8 +11351,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h195303 : - { {32{x__h196066[31]}}, x__h196066 } } ; + curData__h195304 : + { {32{x__h196067[31]}}, x__h196067 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -11385,7 +11385,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_2 = - csrf_fflags_reg | fflags__h722585 ; + csrf_fflags_reg | fflags__h722586 ; always@(IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 or robdeqPort_0_deq_data_BITS_95_TO_32__q262) begin @@ -11411,9 +11411,9 @@ module mkCore(CLK, csrf_prev_ie_vec_3 ; assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h719388 + 64'd1 ; + n__read__h719389 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h719388 + { 62'd0, x__h722832 } ; + n__read__h719389 + { 62'd0, x__h722833 } ; assign MUX_csrf_mpp_reg$write_1__VAL_2 = (rob$deqPort_0_deq_data[257:253] == 5'd13 && IF_rob_deqPort_0_deq_data__4451_BIT_181_4681_T_ETC___d14763 == @@ -11421,7 +11421,7 @@ module mkCore(CLK, MUX_csrf_mepc_csr$write_1__VAL_2[12:11] : 2'd0 ; assign MUX_csrf_mtval_csr$write_1__VAL_1 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h708781 ; + commitStage_commitTrap[36] ? 64'd0 : trap_val__h708782 ; assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 = rob$deqPort_0_deq_data[257:253] != 5'd13 || @@ -11437,7 +11437,7 @@ module mkCore(CLK, MUX_csrf_mtval_csr$write_1__VAL_2[7] ; assign MUX_csrf_prv_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[257:253] == 5'd19) ? - x__h718767 : + x__h718768 : csrf_mpp_reg ; assign MUX_csrf_prv_reg$write_1__VAL_2 = csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 ? @@ -11457,15 +11457,15 @@ module mkCore(CLK, MUX_csrf_sepc_csr$write_1__VAL_2[8] ; assign MUX_fetchStage$redirect_1__VAL_4 = csrf_prv_reg_read__2956_ULE_1_4592_AND_IF_comm_ETC___d14631 ? - y_avValue_new_pc__h710462 : - y_avValue_new_pc__h710648 ; + y_avValue_new_pc__h710463 : + y_avValue_new_pc__h710649 ; always@(rob$deqPort_0_deq_data or - next_pc__h718598 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h718599 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[257:253]) 5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h718598; + default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h718599; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -11500,24 +11500,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h342524 : - res_data__h342519 ; + res_data__h342525 : + res_data__h342520 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h388226 : - res_data__h388221 ; + res_data__h388227 : + res_data__h388222 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h433921 : - res_data__h433916 ; + res_data__h433922 : + res_data__h433917 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h479773 : - data__h479261 ; + data___1__h479774 : + data__h479262 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h480705 : - data__h480193 ; + data___1__h480706 : + data__h480194 ; assign MUX_rf$write_3_wr_2__VAL_4 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -11598,15 +11598,15 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h342520 ; + res_fflags__h342521 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h388222 ; + res_fflags__h388223 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h433917 ; + res_fflags__h433918 ; // inlined wires assign csrf_minstret_ehr_data_lat_0$whas = @@ -11944,8 +11944,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h610687 : - v__h609619 ; + v__h610688 : + v__h609620 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -12091,7 +12091,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h301171 ; + _theResult_____2__h301172 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -12113,7 +12113,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h300591 ; + v__h300592 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -12159,7 +12159,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - _theResult_____2__h309167 ; + _theResult_____2__h309168 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -12177,7 +12177,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 && - v__h303936 ; + v__h303937 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -12277,7 +12277,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - _theResult_____2__h315161 ; + _theResult_____2__h315162 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -12295,7 +12295,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 && - v__h314450 ; + v__h314451 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -12316,7 +12316,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h318724, + { x_addr__h318725, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -12346,7 +12346,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - _theResult_____2__h323015 ; + _theResult_____2__h323016 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -12364,7 +12364,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 && - v__h318326 ; + v__h318327 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -12441,7 +12441,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - _theResult_____2__h336584 ; + _theResult_____2__h336585 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -12459,7 +12459,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 && - v__h336152 ; + v__h336153 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -12502,7 +12502,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - _theResult_____2__h333359 ; + _theResult_____2__h333360 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -12520,7 +12520,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 && - v__h332927 ; + v__h332928 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -12793,7 +12793,7 @@ module mkCore(CLK, // register csrf_mcause_code_reg assign csrf_mcause_code_reg$D_IN = MUX_csrf_ie_vec_3$write_1__SEL_1 ? - cause_code__h707758 : + cause_code__h707759 : csrf_mcycle_ehr_data_lat_0$wget[3:0] ; assign csrf_mcause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -13078,7 +13078,7 @@ module mkCore(CLK, // register csrf_scause_code_reg assign csrf_scause_code_reg$D_IN = MUX_csrf_ie_vec_1$write_1__SEL_1 ? - cause_code__h707758 : + cause_code__h707759 : csrf_rg_tdata3$D_IN[3:0] ; assign csrf_scause_code_reg$EN = WILL_FIRE_RL_commitStage_doCommitTrap_handle && @@ -13340,7 +13340,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h45839, + { x__h45840, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -13352,7 +13352,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48375 } ; + x__h48376 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -13445,7 +13445,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h17932, + { x__h17933, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -13457,7 +13457,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20470 } ; + x__h20471 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -13541,7 +13541,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h65633 } ; + x_data__h65634 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -13722,8 +13722,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h646271, x__h646272, + x__h646273, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -14013,8 +14013,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h623642, x__h623643, + x__h623644, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -14056,7 +14056,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h674092 == 1'd1 && + (k__h674093 == 1'd1 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043, @@ -14077,7 +14077,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689556, + renaming_spec_bits__h689557, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14175,7 +14175,7 @@ module mkCore(CLK, end assign coreFix_aluExe_1_rsAlu$EN_enq = WILL_FIRE_RL_renameStage_doRenaming && - (k__h674092 == 1'd1 && + (k__h674093 == 1'd1 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171 || fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14290 == 1'd1 && @@ -14560,12 +14560,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h608909, - b__h608373 == 64'd0, - a__h608372, + { x__h608910, + b__h608374 == 64'd0, + a__h608373, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h608935, - a__h608372[63], + x__h608936, + a__h608373[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -14580,8 +14580,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h608921 : - b__h608373 ; + _theResult___snd__h608922 : + b__h608374 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -14594,7 +14594,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h609549, + { x__h609550, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -14675,9 +14675,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h487048, x__h487049, x__h487050, + x__h487051, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ; @@ -14729,7 +14729,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689556, + renaming_spec_bits__h689557, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -14887,8 +14887,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h291824, - x__h291836, + { x__h291825, + x__h291837, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890, @@ -14899,13 +14899,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921, - x__h293690, + x__h293691, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h290391 ; + x__h290392 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -15542,13 +15542,13 @@ module mkCore(CLK, assign coreFix_memExe_dTlb$procReq_req = { coreFix_memExe_regToExeQ$first[192:190], coreFix_memExe_regToExeQ$first[157:140], - coreFix_memExe_lsq$getOrigBE << vaddr__h184737[2:0], - vaddr__h184737, + coreFix_memExe_lsq$getOrigBE << vaddr__h184738[2:0], + vaddr__h184738, coreFix_memExe_lsq$getOrigBE[7] ? - vaddr__h184737[2:0] != 3'd0 : + vaddr__h184738[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - vaddr__h184737[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184737[0]), + vaddr__h184738[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184738[0]), coreFix_memExe_regToExeQ$first[11:0] } ; assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ; @@ -15578,8 +15578,8 @@ module mkCore(CLK, { l2Tlb$toChildren_rsToC_first[80:0], l2Tlb$toChildren_rsToC_first[82:81] } ; assign coreFix_memExe_dTlb$updateVMInfo_vm = - { prv__h724143, - prv__h724143 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h724144, + prv__h724144 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -15704,7 +15704,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3513_AND__ETC___d14240) ? specTagManager$currentSpecBits : - renaming_spec_bits__h689556 ; + renaming_spec_bits__h689557 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3513_AND__ETC___d14248) ? @@ -15724,7 +15724,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3513_AND__ETC___d14248) ? specTagManager$currentSpecBits : - renaming_spec_bits__h689556 ; + renaming_spec_bits__h689557 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -15804,7 +15804,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h184742 ; + shiftData__h184743 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -15904,8 +15904,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h184649, x__h184650, + x__h184651, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ; @@ -16169,7 +16169,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14383, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h689556, + renaming_spec_bits__h689557, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16882,7 +16882,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h689556 ; + renaming_spec_bits__h689557 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -17149,7 +17149,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14377, IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14436, 7'd32, - renaming_spec_bits__h689556 } ; + renaming_spec_bits__h689557 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -17698,15 +17698,15 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h195303), + .amoExec_current_data(curData__h195304), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h196841)); + .amoExec(n__h196842)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h75669 }), - .amoExec_in_data({ 32'd0, x__h75784 }), + msip__h75670 }), + .amoExec_in_data({ 32'd0, x__h75785 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d882)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], @@ -17738,7 +17738,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 }, fetchStage$pipelines_0_first[160], - x_data_imm__h681437 } }), + x_data_imm__h681438 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -17747,12 +17747,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h661520, - r1__read_BITS_13_TO_12___h661705 != + .checkForException_csrState({ x_decodeInfo_frm__h661521, + r1__read_BITS_13_TO_12___h661706 != 2'd0, - { prv__h724099, + { prv__h724100, csrf_tvm_reg, - { r1__read_BIT_20___h662369, + { r1__read_BIT_20___h662370, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17768,7 +17768,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13686, { fetchStage_pipelines_1_first__2937_BIT_173_368_ETC___d13770, fetchStage$pipelines_1_first[160], - x_data_imm__h697341 } }), + x_data_imm__h697342 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -17777,12 +17777,12 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h661520, - r1__read_BITS_13_TO_12___h661705 != + .checkForException_csrState({ x_decodeInfo_frm__h661521, + r1__read_BITS_13_TO_12___h661706 != 2'd0, - { prv__h724099, + { prv__h724100, csrf_tvm_reg, - { r1__read_BIT_20___h662369, + { r1__read_BIT_20___h662370, csrf_tsr_reg, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && @@ -17797,1196 +17797,1196 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h487142), - .execFpuSimple_rVal2(rVal2__h487143), + .execFpuSimple_rVal1(rVal1__h487143), + .execFpuSimple_rVal2(rVal2__h487144), .execFpuSimple(execFpuSimple___d11167)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ? - _theResult___snd__h358909 : - _theResult____h350735 ; + _theResult___snd__h358910 : + _theResult____h350736 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 ? - _theResult___snd__h404606 : - _theResult____h396434 ; + _theResult___snd__h404607 : + _theResult____h396435 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 ? - _theResult___snd__h450301 : - _theResult____h442129 ; + _theResult___snd__h450302 : + _theResult____h442130 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 ? - _theResult___snd__h516554 : - _theResult____h508255 ; + _theResult___snd__h516555 : + _theResult____h508256 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723 ? - _theResult___snd__h594711 : - _theResult____h586412 ; + _theResult___snd__h594712 : + _theResult____h586413 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 ? - _theResult___snd__h555407 : - _theResult____h547108 ; + _theResult___snd__h555408 : + _theResult____h547109 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 ? - _theResult___snd__h468067 : - _theResult____h459766 ; + _theResult___snd__h468068 : + _theResult____h459767 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896 ? - _theResult___snd__h376675 : - _theResult____h368374 ; + _theResult___snd__h376676 : + _theResult____h368375 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 ? - _theResult___snd__h422372 : - _theResult____h414071 ; + _theResult___snd__h422373 : + _theResult____h414072 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 ? - _theResult___snd__h506903 : + _theResult___snd__h506904 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058 ? - _theResult___snd__h506903 : - _theResult___snd__h525308 ; + _theResult___snd__h506904 : + _theResult___snd__h525309 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426 ? - _theResult___snd__h585060 : + _theResult___snd__h585061 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773 ? - _theResult___snd__h585060 : - _theResult___snd__h603465 ; + _theResult___snd__h585061 : + _theResult___snd__h603466 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 ? - _theResult___snd__h545756 : + _theResult___snd__h545757 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543 ? - _theResult___snd__h545756 : - _theResult___snd__h564161 ; + _theResult___snd__h545757 : + _theResult___snd__h564162 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ? - _theResult___snd__h458883 : - _theResult___snd__h476673 ; + _theResult___snd__h458884 : + _theResult___snd__h476674 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ? - _theResult___snd__h367491 : + _theResult___snd__h367492 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969 ? - _theResult___snd__h367491 : - _theResult___snd__h385281 ; + _theResult___snd__h367492 : + _theResult___snd__h385282 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 ? - _theResult___snd__h413188 : + _theResult___snd__h413189 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361 ? - _theResult___snd__h413188 : - _theResult___snd__h430978 ; + _theResult___snd__h413189 : + _theResult___snd__h430979 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 ? - _theResult___snd__h458883 : + _theResult___snd__h458884 : 57'd0 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h358846 == 8'd255) ? + ((_theResult___fst_exp__h358847 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150) : - ((_theResult___fst_exp__h367502 == 8'd255) ? + ((_theResult___fst_exp__h367503 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - ((_theResult___fst_exp__h358846 == 8'd255) ? + ((_theResult___fst_exp__h358847 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206) : - ((_theResult___fst_exp__h367502 == 8'd255) ? + ((_theResult___fst_exp__h367503 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h404543 == 8'd255) ? + ((_theResult___fst_exp__h404544 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542) : - ((_theResult___fst_exp__h413199 == 8'd255) ? + ((_theResult___fst_exp__h413200 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - ((_theResult___fst_exp__h404543 == 8'd255) ? + ((_theResult___fst_exp__h404544 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598) : - ((_theResult___fst_exp__h413199 == 8'd255) ? + ((_theResult___fst_exp__h413200 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h450238 == 8'd255) ? + ((_theResult___fst_exp__h450239 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934) : - ((_theResult___fst_exp__h458894 == 8'd255) ? + ((_theResult___fst_exp__h458895 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - ((_theResult___fst_exp__h450238 == 8'd255) ? + ((_theResult___fst_exp__h450239 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990) : - ((_theResult___fst_exp__h458894 == 8'd255) ? + ((_theResult___fst_exp__h458895 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 = - (_theResult____h350735[56] ? + (_theResult____h350736[56] ? 6'd0 : - (_theResult____h350735[55] ? + (_theResult____h350736[55] ? 6'd1 : - (_theResult____h350735[54] ? + (_theResult____h350736[54] ? 6'd2 : - (_theResult____h350735[53] ? + (_theResult____h350736[53] ? 6'd3 : - (_theResult____h350735[52] ? + (_theResult____h350736[52] ? 6'd4 : - (_theResult____h350735[51] ? + (_theResult____h350736[51] ? 6'd5 : - (_theResult____h350735[50] ? + (_theResult____h350736[50] ? 6'd6 : - (_theResult____h350735[49] ? + (_theResult____h350736[49] ? 6'd7 : - (_theResult____h350735[48] ? + (_theResult____h350736[48] ? 6'd8 : - (_theResult____h350735[47] ? + (_theResult____h350736[47] ? 6'd9 : - (_theResult____h350735[46] ? + (_theResult____h350736[46] ? 6'd10 : - (_theResult____h350735[45] ? + (_theResult____h350736[45] ? 6'd11 : - (_theResult____h350735[44] ? + (_theResult____h350736[44] ? 6'd12 : - (_theResult____h350735[43] ? + (_theResult____h350736[43] ? 6'd13 : - (_theResult____h350735[42] ? + (_theResult____h350736[42] ? 6'd14 : - (_theResult____h350735[41] ? + (_theResult____h350736[41] ? 6'd15 : - (_theResult____h350735[40] ? + (_theResult____h350736[40] ? 6'd16 : - (_theResult____h350735[39] ? + (_theResult____h350736[39] ? 6'd17 : - (_theResult____h350735[38] ? + (_theResult____h350736[38] ? 6'd18 : - (_theResult____h350735[37] ? + (_theResult____h350736[37] ? 6'd19 : - (_theResult____h350735[36] ? + (_theResult____h350736[36] ? 6'd20 : - (_theResult____h350735[35] ? + (_theResult____h350736[35] ? 6'd21 : - (_theResult____h350735[34] ? + (_theResult____h350736[34] ? 6'd22 : - (_theResult____h350735[33] ? + (_theResult____h350736[33] ? 6'd23 : - (_theResult____h350735[32] ? + (_theResult____h350736[32] ? 6'd24 : - (_theResult____h350735[31] ? + (_theResult____h350736[31] ? 6'd25 : - (_theResult____h350735[30] ? + (_theResult____h350736[30] ? 6'd26 : - (_theResult____h350735[29] ? + (_theResult____h350736[29] ? 6'd27 : - (_theResult____h350735[28] ? + (_theResult____h350736[28] ? 6'd28 : - (_theResult____h350735[27] ? + (_theResult____h350736[27] ? 6'd29 : - (_theResult____h350735[26] ? + (_theResult____h350736[26] ? 6'd30 : - (_theResult____h350735[25] ? + (_theResult____h350736[25] ? 6'd31 : - (_theResult____h350735[24] ? + (_theResult____h350736[24] ? 6'd32 : - (_theResult____h350735[23] ? + (_theResult____h350736[23] ? 6'd33 : - (_theResult____h350735[22] ? + (_theResult____h350736[22] ? 6'd34 : - (_theResult____h350735[21] ? + (_theResult____h350736[21] ? 6'd35 : - (_theResult____h350735[20] ? + (_theResult____h350736[20] ? 6'd36 : - (_theResult____h350735[19] ? + (_theResult____h350736[19] ? 6'd37 : - (_theResult____h350735[18] ? + (_theResult____h350736[18] ? 6'd38 : - (_theResult____h350735[17] ? + (_theResult____h350736[17] ? 6'd39 : - (_theResult____h350735[16] ? + (_theResult____h350736[16] ? 6'd40 : - (_theResult____h350735[15] ? + (_theResult____h350736[15] ? 6'd41 : - (_theResult____h350735[14] ? + (_theResult____h350736[14] ? 6'd42 : - (_theResult____h350735[13] ? + (_theResult____h350736[13] ? 6'd43 : - (_theResult____h350735[12] ? + (_theResult____h350736[12] ? 6'd44 : - (_theResult____h350735[11] ? + (_theResult____h350736[11] ? 6'd45 : - (_theResult____h350735[10] ? + (_theResult____h350736[10] ? 6'd46 : - (_theResult____h350735[9] ? + (_theResult____h350736[9] ? 6'd47 : - (_theResult____h350735[8] ? + (_theResult____h350736[8] ? 6'd48 : - (_theResult____h350735[7] ? + (_theResult____h350736[7] ? 6'd49 : - (_theResult____h350735[6] ? + (_theResult____h350736[6] ? 6'd50 : - (_theResult____h350735[5] ? + (_theResult____h350736[5] ? 6'd51 : - (_theResult____h350735[4] ? + (_theResult____h350736[4] ? 6'd52 : - (_theResult____h350735[3] ? + (_theResult____h350736[3] ? 6'd53 : - (_theResult____h350735[2] ? + (_theResult____h350736[2] ? 6'd54 : - (_theResult____h350735[1] ? + (_theResult____h350736[1] ? 6'd55 : - (_theResult____h350735[0] ? + (_theResult____h350736[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 = - (_theResult____h396434[56] ? + (_theResult____h396435[56] ? 6'd0 : - (_theResult____h396434[55] ? + (_theResult____h396435[55] ? 6'd1 : - (_theResult____h396434[54] ? + (_theResult____h396435[54] ? 6'd2 : - (_theResult____h396434[53] ? + (_theResult____h396435[53] ? 6'd3 : - (_theResult____h396434[52] ? + (_theResult____h396435[52] ? 6'd4 : - (_theResult____h396434[51] ? + (_theResult____h396435[51] ? 6'd5 : - (_theResult____h396434[50] ? + (_theResult____h396435[50] ? 6'd6 : - (_theResult____h396434[49] ? + (_theResult____h396435[49] ? 6'd7 : - (_theResult____h396434[48] ? + (_theResult____h396435[48] ? 6'd8 : - (_theResult____h396434[47] ? + (_theResult____h396435[47] ? 6'd9 : - (_theResult____h396434[46] ? + (_theResult____h396435[46] ? 6'd10 : - (_theResult____h396434[45] ? + (_theResult____h396435[45] ? 6'd11 : - (_theResult____h396434[44] ? + (_theResult____h396435[44] ? 6'd12 : - (_theResult____h396434[43] ? + (_theResult____h396435[43] ? 6'd13 : - (_theResult____h396434[42] ? + (_theResult____h396435[42] ? 6'd14 : - (_theResult____h396434[41] ? + (_theResult____h396435[41] ? 6'd15 : - (_theResult____h396434[40] ? + (_theResult____h396435[40] ? 6'd16 : - (_theResult____h396434[39] ? + (_theResult____h396435[39] ? 6'd17 : - (_theResult____h396434[38] ? + (_theResult____h396435[38] ? 6'd18 : - (_theResult____h396434[37] ? + (_theResult____h396435[37] ? 6'd19 : - (_theResult____h396434[36] ? + (_theResult____h396435[36] ? 6'd20 : - (_theResult____h396434[35] ? + (_theResult____h396435[35] ? 6'd21 : - (_theResult____h396434[34] ? + (_theResult____h396435[34] ? 6'd22 : - (_theResult____h396434[33] ? + (_theResult____h396435[33] ? 6'd23 : - (_theResult____h396434[32] ? + (_theResult____h396435[32] ? 6'd24 : - (_theResult____h396434[31] ? + (_theResult____h396435[31] ? 6'd25 : - (_theResult____h396434[30] ? + (_theResult____h396435[30] ? 6'd26 : - (_theResult____h396434[29] ? + (_theResult____h396435[29] ? 6'd27 : - (_theResult____h396434[28] ? + (_theResult____h396435[28] ? 6'd28 : - (_theResult____h396434[27] ? + (_theResult____h396435[27] ? 6'd29 : - (_theResult____h396434[26] ? + (_theResult____h396435[26] ? 6'd30 : - (_theResult____h396434[25] ? + (_theResult____h396435[25] ? 6'd31 : - (_theResult____h396434[24] ? + (_theResult____h396435[24] ? 6'd32 : - (_theResult____h396434[23] ? + (_theResult____h396435[23] ? 6'd33 : - (_theResult____h396434[22] ? + (_theResult____h396435[22] ? 6'd34 : - (_theResult____h396434[21] ? + (_theResult____h396435[21] ? 6'd35 : - (_theResult____h396434[20] ? + (_theResult____h396435[20] ? 6'd36 : - (_theResult____h396434[19] ? + (_theResult____h396435[19] ? 6'd37 : - (_theResult____h396434[18] ? + (_theResult____h396435[18] ? 6'd38 : - (_theResult____h396434[17] ? + (_theResult____h396435[17] ? 6'd39 : - (_theResult____h396434[16] ? + (_theResult____h396435[16] ? 6'd40 : - (_theResult____h396434[15] ? + (_theResult____h396435[15] ? 6'd41 : - (_theResult____h396434[14] ? + (_theResult____h396435[14] ? 6'd42 : - (_theResult____h396434[13] ? + (_theResult____h396435[13] ? 6'd43 : - (_theResult____h396434[12] ? + (_theResult____h396435[12] ? 6'd44 : - (_theResult____h396434[11] ? + (_theResult____h396435[11] ? 6'd45 : - (_theResult____h396434[10] ? + (_theResult____h396435[10] ? 6'd46 : - (_theResult____h396434[9] ? + (_theResult____h396435[9] ? 6'd47 : - (_theResult____h396434[8] ? + (_theResult____h396435[8] ? 6'd48 : - (_theResult____h396434[7] ? + (_theResult____h396435[7] ? 6'd49 : - (_theResult____h396434[6] ? + (_theResult____h396435[6] ? 6'd50 : - (_theResult____h396434[5] ? + (_theResult____h396435[5] ? 6'd51 : - (_theResult____h396434[4] ? + (_theResult____h396435[4] ? 6'd52 : - (_theResult____h396434[3] ? + (_theResult____h396435[3] ? 6'd53 : - (_theResult____h396434[2] ? + (_theResult____h396435[2] ? 6'd54 : - (_theResult____h396434[1] ? + (_theResult____h396435[1] ? 6'd55 : - (_theResult____h396434[0] ? + (_theResult____h396435[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 = - (_theResult____h442129[56] ? + (_theResult____h442130[56] ? 6'd0 : - (_theResult____h442129[55] ? + (_theResult____h442130[55] ? 6'd1 : - (_theResult____h442129[54] ? + (_theResult____h442130[54] ? 6'd2 : - (_theResult____h442129[53] ? + (_theResult____h442130[53] ? 6'd3 : - (_theResult____h442129[52] ? + (_theResult____h442130[52] ? 6'd4 : - (_theResult____h442129[51] ? + (_theResult____h442130[51] ? 6'd5 : - (_theResult____h442129[50] ? + (_theResult____h442130[50] ? 6'd6 : - (_theResult____h442129[49] ? + (_theResult____h442130[49] ? 6'd7 : - (_theResult____h442129[48] ? + (_theResult____h442130[48] ? 6'd8 : - (_theResult____h442129[47] ? + (_theResult____h442130[47] ? 6'd9 : - (_theResult____h442129[46] ? + (_theResult____h442130[46] ? 6'd10 : - (_theResult____h442129[45] ? + (_theResult____h442130[45] ? 6'd11 : - (_theResult____h442129[44] ? + (_theResult____h442130[44] ? 6'd12 : - (_theResult____h442129[43] ? + (_theResult____h442130[43] ? 6'd13 : - (_theResult____h442129[42] ? + (_theResult____h442130[42] ? 6'd14 : - (_theResult____h442129[41] ? + (_theResult____h442130[41] ? 6'd15 : - (_theResult____h442129[40] ? + (_theResult____h442130[40] ? 6'd16 : - (_theResult____h442129[39] ? + (_theResult____h442130[39] ? 6'd17 : - (_theResult____h442129[38] ? + (_theResult____h442130[38] ? 6'd18 : - (_theResult____h442129[37] ? + (_theResult____h442130[37] ? 6'd19 : - (_theResult____h442129[36] ? + (_theResult____h442130[36] ? 6'd20 : - (_theResult____h442129[35] ? + (_theResult____h442130[35] ? 6'd21 : - (_theResult____h442129[34] ? + (_theResult____h442130[34] ? 6'd22 : - (_theResult____h442129[33] ? + (_theResult____h442130[33] ? 6'd23 : - (_theResult____h442129[32] ? + (_theResult____h442130[32] ? 6'd24 : - (_theResult____h442129[31] ? + (_theResult____h442130[31] ? 6'd25 : - (_theResult____h442129[30] ? + (_theResult____h442130[30] ? 6'd26 : - (_theResult____h442129[29] ? + (_theResult____h442130[29] ? 6'd27 : - (_theResult____h442129[28] ? + (_theResult____h442130[28] ? 6'd28 : - (_theResult____h442129[27] ? + (_theResult____h442130[27] ? 6'd29 : - (_theResult____h442129[26] ? + (_theResult____h442130[26] ? 6'd30 : - (_theResult____h442129[25] ? + (_theResult____h442130[25] ? 6'd31 : - (_theResult____h442129[24] ? + (_theResult____h442130[24] ? 6'd32 : - (_theResult____h442129[23] ? + (_theResult____h442130[23] ? 6'd33 : - (_theResult____h442129[22] ? + (_theResult____h442130[22] ? 6'd34 : - (_theResult____h442129[21] ? + (_theResult____h442130[21] ? 6'd35 : - (_theResult____h442129[20] ? + (_theResult____h442130[20] ? 6'd36 : - (_theResult____h442129[19] ? + (_theResult____h442130[19] ? 6'd37 : - (_theResult____h442129[18] ? + (_theResult____h442130[18] ? 6'd38 : - (_theResult____h442129[17] ? + (_theResult____h442130[17] ? 6'd39 : - (_theResult____h442129[16] ? + (_theResult____h442130[16] ? 6'd40 : - (_theResult____h442129[15] ? + (_theResult____h442130[15] ? 6'd41 : - (_theResult____h442129[14] ? + (_theResult____h442130[14] ? 6'd42 : - (_theResult____h442129[13] ? + (_theResult____h442130[13] ? 6'd43 : - (_theResult____h442129[12] ? + (_theResult____h442130[12] ? 6'd44 : - (_theResult____h442129[11] ? + (_theResult____h442130[11] ? 6'd45 : - (_theResult____h442129[10] ? + (_theResult____h442130[10] ? 6'd46 : - (_theResult____h442129[9] ? + (_theResult____h442130[9] ? 6'd47 : - (_theResult____h442129[8] ? + (_theResult____h442130[8] ? 6'd48 : - (_theResult____h442129[7] ? + (_theResult____h442130[7] ? 6'd49 : - (_theResult____h442129[6] ? + (_theResult____h442130[6] ? 6'd50 : - (_theResult____h442129[5] ? + (_theResult____h442130[5] ? 6'd51 : - (_theResult____h442129[4] ? + (_theResult____h442130[4] ? 6'd52 : - (_theResult____h442129[3] ? + (_theResult____h442130[3] ? 6'd53 : - (_theResult____h442129[2] ? + (_theResult____h442130[2] ? 6'd54 : - (_theResult____h442129[1] ? + (_theResult____h442130[1] ? 6'd55 : - (_theResult____h442129[0] ? + (_theResult____h442130[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 = - (_theResult____h547108[56] ? + (_theResult____h547109[56] ? 6'd0 : - (_theResult____h547108[55] ? + (_theResult____h547109[55] ? 6'd1 : - (_theResult____h547108[54] ? + (_theResult____h547109[54] ? 6'd2 : - (_theResult____h547108[53] ? + (_theResult____h547109[53] ? 6'd3 : - (_theResult____h547108[52] ? + (_theResult____h547109[52] ? 6'd4 : - (_theResult____h547108[51] ? + (_theResult____h547109[51] ? 6'd5 : - (_theResult____h547108[50] ? + (_theResult____h547109[50] ? 6'd6 : - (_theResult____h547108[49] ? + (_theResult____h547109[49] ? 6'd7 : - (_theResult____h547108[48] ? + (_theResult____h547109[48] ? 6'd8 : - (_theResult____h547108[47] ? + (_theResult____h547109[47] ? 6'd9 : - (_theResult____h547108[46] ? + (_theResult____h547109[46] ? 6'd10 : - (_theResult____h547108[45] ? + (_theResult____h547109[45] ? 6'd11 : - (_theResult____h547108[44] ? + (_theResult____h547109[44] ? 6'd12 : - (_theResult____h547108[43] ? + (_theResult____h547109[43] ? 6'd13 : - (_theResult____h547108[42] ? + (_theResult____h547109[42] ? 6'd14 : - (_theResult____h547108[41] ? + (_theResult____h547109[41] ? 6'd15 : - (_theResult____h547108[40] ? + (_theResult____h547109[40] ? 6'd16 : - (_theResult____h547108[39] ? + (_theResult____h547109[39] ? 6'd17 : - (_theResult____h547108[38] ? + (_theResult____h547109[38] ? 6'd18 : - (_theResult____h547108[37] ? + (_theResult____h547109[37] ? 6'd19 : - (_theResult____h547108[36] ? + (_theResult____h547109[36] ? 6'd20 : - (_theResult____h547108[35] ? + (_theResult____h547109[35] ? 6'd21 : - (_theResult____h547108[34] ? + (_theResult____h547109[34] ? 6'd22 : - (_theResult____h547108[33] ? + (_theResult____h547109[33] ? 6'd23 : - (_theResult____h547108[32] ? + (_theResult____h547109[32] ? 6'd24 : - (_theResult____h547108[31] ? + (_theResult____h547109[31] ? 6'd25 : - (_theResult____h547108[30] ? + (_theResult____h547109[30] ? 6'd26 : - (_theResult____h547108[29] ? + (_theResult____h547109[29] ? 6'd27 : - (_theResult____h547108[28] ? + (_theResult____h547109[28] ? 6'd28 : - (_theResult____h547108[27] ? + (_theResult____h547109[27] ? 6'd29 : - (_theResult____h547108[26] ? + (_theResult____h547109[26] ? 6'd30 : - (_theResult____h547108[25] ? + (_theResult____h547109[25] ? 6'd31 : - (_theResult____h547108[24] ? + (_theResult____h547109[24] ? 6'd32 : - (_theResult____h547108[23] ? + (_theResult____h547109[23] ? 6'd33 : - (_theResult____h547108[22] ? + (_theResult____h547109[22] ? 6'd34 : - (_theResult____h547108[21] ? + (_theResult____h547109[21] ? 6'd35 : - (_theResult____h547108[20] ? + (_theResult____h547109[20] ? 6'd36 : - (_theResult____h547108[19] ? + (_theResult____h547109[19] ? 6'd37 : - (_theResult____h547108[18] ? + (_theResult____h547109[18] ? 6'd38 : - (_theResult____h547108[17] ? + (_theResult____h547109[17] ? 6'd39 : - (_theResult____h547108[16] ? + (_theResult____h547109[16] ? 6'd40 : - (_theResult____h547108[15] ? + (_theResult____h547109[15] ? 6'd41 : - (_theResult____h547108[14] ? + (_theResult____h547109[14] ? 6'd42 : - (_theResult____h547108[13] ? + (_theResult____h547109[13] ? 6'd43 : - (_theResult____h547108[12] ? + (_theResult____h547109[12] ? 6'd44 : - (_theResult____h547108[11] ? + (_theResult____h547109[11] ? 6'd45 : - (_theResult____h547108[10] ? + (_theResult____h547109[10] ? 6'd46 : - (_theResult____h547108[9] ? + (_theResult____h547109[9] ? 6'd47 : - (_theResult____h547108[8] ? + (_theResult____h547109[8] ? 6'd48 : - (_theResult____h547108[7] ? + (_theResult____h547109[7] ? 6'd49 : - (_theResult____h547108[6] ? + (_theResult____h547109[6] ? 6'd50 : - (_theResult____h547108[5] ? + (_theResult____h547109[5] ? 6'd51 : - (_theResult____h547108[4] ? + (_theResult____h547109[4] ? 6'd52 : - (_theResult____h547108[3] ? + (_theResult____h547109[3] ? 6'd53 : - (_theResult____h547108[2] ? + (_theResult____h547109[2] ? 6'd54 : - (_theResult____h547108[1] ? + (_theResult____h547109[1] ? 6'd55 : - (_theResult____h547108[0] ? + (_theResult____h547109[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 = - (_theResult____h508255[56] ? + (_theResult____h508256[56] ? 6'd0 : - (_theResult____h508255[55] ? + (_theResult____h508256[55] ? 6'd1 : - (_theResult____h508255[54] ? + (_theResult____h508256[54] ? 6'd2 : - (_theResult____h508255[53] ? + (_theResult____h508256[53] ? 6'd3 : - (_theResult____h508255[52] ? + (_theResult____h508256[52] ? 6'd4 : - (_theResult____h508255[51] ? + (_theResult____h508256[51] ? 6'd5 : - (_theResult____h508255[50] ? + (_theResult____h508256[50] ? 6'd6 : - (_theResult____h508255[49] ? + (_theResult____h508256[49] ? 6'd7 : - (_theResult____h508255[48] ? + (_theResult____h508256[48] ? 6'd8 : - (_theResult____h508255[47] ? + (_theResult____h508256[47] ? 6'd9 : - (_theResult____h508255[46] ? + (_theResult____h508256[46] ? 6'd10 : - (_theResult____h508255[45] ? + (_theResult____h508256[45] ? 6'd11 : - (_theResult____h508255[44] ? + (_theResult____h508256[44] ? 6'd12 : - (_theResult____h508255[43] ? + (_theResult____h508256[43] ? 6'd13 : - (_theResult____h508255[42] ? + (_theResult____h508256[42] ? 6'd14 : - (_theResult____h508255[41] ? + (_theResult____h508256[41] ? 6'd15 : - (_theResult____h508255[40] ? + (_theResult____h508256[40] ? 6'd16 : - (_theResult____h508255[39] ? + (_theResult____h508256[39] ? 6'd17 : - (_theResult____h508255[38] ? + (_theResult____h508256[38] ? 6'd18 : - (_theResult____h508255[37] ? + (_theResult____h508256[37] ? 6'd19 : - (_theResult____h508255[36] ? + (_theResult____h508256[36] ? 6'd20 : - (_theResult____h508255[35] ? + (_theResult____h508256[35] ? 6'd21 : - (_theResult____h508255[34] ? + (_theResult____h508256[34] ? 6'd22 : - (_theResult____h508255[33] ? + (_theResult____h508256[33] ? 6'd23 : - (_theResult____h508255[32] ? + (_theResult____h508256[32] ? 6'd24 : - (_theResult____h508255[31] ? + (_theResult____h508256[31] ? 6'd25 : - (_theResult____h508255[30] ? + (_theResult____h508256[30] ? 6'd26 : - (_theResult____h508255[29] ? + (_theResult____h508256[29] ? 6'd27 : - (_theResult____h508255[28] ? + (_theResult____h508256[28] ? 6'd28 : - (_theResult____h508255[27] ? + (_theResult____h508256[27] ? 6'd29 : - (_theResult____h508255[26] ? + (_theResult____h508256[26] ? 6'd30 : - (_theResult____h508255[25] ? + (_theResult____h508256[25] ? 6'd31 : - (_theResult____h508255[24] ? + (_theResult____h508256[24] ? 6'd32 : - (_theResult____h508255[23] ? + (_theResult____h508256[23] ? 6'd33 : - (_theResult____h508255[22] ? + (_theResult____h508256[22] ? 6'd34 : - (_theResult____h508255[21] ? + (_theResult____h508256[21] ? 6'd35 : - (_theResult____h508255[20] ? + (_theResult____h508256[20] ? 6'd36 : - (_theResult____h508255[19] ? + (_theResult____h508256[19] ? 6'd37 : - (_theResult____h508255[18] ? + (_theResult____h508256[18] ? 6'd38 : - (_theResult____h508255[17] ? + (_theResult____h508256[17] ? 6'd39 : - (_theResult____h508255[16] ? + (_theResult____h508256[16] ? 6'd40 : - (_theResult____h508255[15] ? + (_theResult____h508256[15] ? 6'd41 : - (_theResult____h508255[14] ? + (_theResult____h508256[14] ? 6'd42 : - (_theResult____h508255[13] ? + (_theResult____h508256[13] ? 6'd43 : - (_theResult____h508255[12] ? + (_theResult____h508256[12] ? 6'd44 : - (_theResult____h508255[11] ? + (_theResult____h508256[11] ? 6'd45 : - (_theResult____h508255[10] ? + (_theResult____h508256[10] ? 6'd46 : - (_theResult____h508255[9] ? + (_theResult____h508256[9] ? 6'd47 : - (_theResult____h508255[8] ? + (_theResult____h508256[8] ? 6'd48 : - (_theResult____h508255[7] ? + (_theResult____h508256[7] ? 6'd49 : - (_theResult____h508255[6] ? + (_theResult____h508256[6] ? 6'd50 : - (_theResult____h508255[5] ? + (_theResult____h508256[5] ? 6'd51 : - (_theResult____h508255[4] ? + (_theResult____h508256[4] ? 6'd52 : - (_theResult____h508255[3] ? + (_theResult____h508256[3] ? 6'd53 : - (_theResult____h508255[2] ? + (_theResult____h508256[2] ? 6'd54 : - (_theResult____h508255[1] ? + (_theResult____h508256[1] ? 6'd55 : - (_theResult____h508255[0] ? + (_theResult____h508256[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 = - (_theResult____h586412[56] ? + (_theResult____h586413[56] ? 6'd0 : - (_theResult____h586412[55] ? + (_theResult____h586413[55] ? 6'd1 : - (_theResult____h586412[54] ? + (_theResult____h586413[54] ? 6'd2 : - (_theResult____h586412[53] ? + (_theResult____h586413[53] ? 6'd3 : - (_theResult____h586412[52] ? + (_theResult____h586413[52] ? 6'd4 : - (_theResult____h586412[51] ? + (_theResult____h586413[51] ? 6'd5 : - (_theResult____h586412[50] ? + (_theResult____h586413[50] ? 6'd6 : - (_theResult____h586412[49] ? + (_theResult____h586413[49] ? 6'd7 : - (_theResult____h586412[48] ? + (_theResult____h586413[48] ? 6'd8 : - (_theResult____h586412[47] ? + (_theResult____h586413[47] ? 6'd9 : - (_theResult____h586412[46] ? + (_theResult____h586413[46] ? 6'd10 : - (_theResult____h586412[45] ? + (_theResult____h586413[45] ? 6'd11 : - (_theResult____h586412[44] ? + (_theResult____h586413[44] ? 6'd12 : - (_theResult____h586412[43] ? + (_theResult____h586413[43] ? 6'd13 : - (_theResult____h586412[42] ? + (_theResult____h586413[42] ? 6'd14 : - (_theResult____h586412[41] ? + (_theResult____h586413[41] ? 6'd15 : - (_theResult____h586412[40] ? + (_theResult____h586413[40] ? 6'd16 : - (_theResult____h586412[39] ? + (_theResult____h586413[39] ? 6'd17 : - (_theResult____h586412[38] ? + (_theResult____h586413[38] ? 6'd18 : - (_theResult____h586412[37] ? + (_theResult____h586413[37] ? 6'd19 : - (_theResult____h586412[36] ? + (_theResult____h586413[36] ? 6'd20 : - (_theResult____h586412[35] ? + (_theResult____h586413[35] ? 6'd21 : - (_theResult____h586412[34] ? + (_theResult____h586413[34] ? 6'd22 : - (_theResult____h586412[33] ? + (_theResult____h586413[33] ? 6'd23 : - (_theResult____h586412[32] ? + (_theResult____h586413[32] ? 6'd24 : - (_theResult____h586412[31] ? + (_theResult____h586413[31] ? 6'd25 : - (_theResult____h586412[30] ? + (_theResult____h586413[30] ? 6'd26 : - (_theResult____h586412[29] ? + (_theResult____h586413[29] ? 6'd27 : - (_theResult____h586412[28] ? + (_theResult____h586413[28] ? 6'd28 : - (_theResult____h586412[27] ? + (_theResult____h586413[27] ? 6'd29 : - (_theResult____h586412[26] ? + (_theResult____h586413[26] ? 6'd30 : - (_theResult____h586412[25] ? + (_theResult____h586413[25] ? 6'd31 : - (_theResult____h586412[24] ? + (_theResult____h586413[24] ? 6'd32 : - (_theResult____h586412[23] ? + (_theResult____h586413[23] ? 6'd33 : - (_theResult____h586412[22] ? + (_theResult____h586413[22] ? 6'd34 : - (_theResult____h586412[21] ? + (_theResult____h586413[21] ? 6'd35 : - (_theResult____h586412[20] ? + (_theResult____h586413[20] ? 6'd36 : - (_theResult____h586412[19] ? + (_theResult____h586413[19] ? 6'd37 : - (_theResult____h586412[18] ? + (_theResult____h586413[18] ? 6'd38 : - (_theResult____h586412[17] ? + (_theResult____h586413[17] ? 6'd39 : - (_theResult____h586412[16] ? + (_theResult____h586413[16] ? 6'd40 : - (_theResult____h586412[15] ? + (_theResult____h586413[15] ? 6'd41 : - (_theResult____h586412[14] ? + (_theResult____h586413[14] ? 6'd42 : - (_theResult____h586412[13] ? + (_theResult____h586413[13] ? 6'd43 : - (_theResult____h586412[12] ? + (_theResult____h586413[12] ? 6'd44 : - (_theResult____h586412[11] ? + (_theResult____h586413[11] ? 6'd45 : - (_theResult____h586412[10] ? + (_theResult____h586413[10] ? 6'd46 : - (_theResult____h586412[9] ? + (_theResult____h586413[9] ? 6'd47 : - (_theResult____h586412[8] ? + (_theResult____h586413[8] ? 6'd48 : - (_theResult____h586412[7] ? + (_theResult____h586413[7] ? 6'd49 : - (_theResult____h586412[6] ? + (_theResult____h586413[6] ? 6'd50 : - (_theResult____h586412[5] ? + (_theResult____h586413[5] ? 6'd51 : - (_theResult____h586412[4] ? + (_theResult____h586413[4] ? 6'd52 : - (_theResult____h586412[3] ? + (_theResult____h586413[3] ? 6'd53 : - (_theResult____h586412[2] ? + (_theResult____h586413[2] ? 6'd54 : - (_theResult____h586412[1] ? + (_theResult____h586413[1] ? 6'd55 : - (_theResult____h586412[0] ? + (_theResult____h586413[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 = - (_theResult____h368374[56] ? + (_theResult____h368375[56] ? 6'd0 : - (_theResult____h368374[55] ? + (_theResult____h368375[55] ? 6'd1 : - (_theResult____h368374[54] ? + (_theResult____h368375[54] ? 6'd2 : - (_theResult____h368374[53] ? + (_theResult____h368375[53] ? 6'd3 : - (_theResult____h368374[52] ? + (_theResult____h368375[52] ? 6'd4 : - (_theResult____h368374[51] ? + (_theResult____h368375[51] ? 6'd5 : - (_theResult____h368374[50] ? + (_theResult____h368375[50] ? 6'd6 : - (_theResult____h368374[49] ? + (_theResult____h368375[49] ? 6'd7 : - (_theResult____h368374[48] ? + (_theResult____h368375[48] ? 6'd8 : - (_theResult____h368374[47] ? + (_theResult____h368375[47] ? 6'd9 : - (_theResult____h368374[46] ? + (_theResult____h368375[46] ? 6'd10 : - (_theResult____h368374[45] ? + (_theResult____h368375[45] ? 6'd11 : - (_theResult____h368374[44] ? + (_theResult____h368375[44] ? 6'd12 : - (_theResult____h368374[43] ? + (_theResult____h368375[43] ? 6'd13 : - (_theResult____h368374[42] ? + (_theResult____h368375[42] ? 6'd14 : - (_theResult____h368374[41] ? + (_theResult____h368375[41] ? 6'd15 : - (_theResult____h368374[40] ? + (_theResult____h368375[40] ? 6'd16 : - (_theResult____h368374[39] ? + (_theResult____h368375[39] ? 6'd17 : - (_theResult____h368374[38] ? + (_theResult____h368375[38] ? 6'd18 : - (_theResult____h368374[37] ? + (_theResult____h368375[37] ? 6'd19 : - (_theResult____h368374[36] ? + (_theResult____h368375[36] ? 6'd20 : - (_theResult____h368374[35] ? + (_theResult____h368375[35] ? 6'd21 : - (_theResult____h368374[34] ? + (_theResult____h368375[34] ? 6'd22 : - (_theResult____h368374[33] ? + (_theResult____h368375[33] ? 6'd23 : - (_theResult____h368374[32] ? + (_theResult____h368375[32] ? 6'd24 : - (_theResult____h368374[31] ? + (_theResult____h368375[31] ? 6'd25 : - (_theResult____h368374[30] ? + (_theResult____h368375[30] ? 6'd26 : - (_theResult____h368374[29] ? + (_theResult____h368375[29] ? 6'd27 : - (_theResult____h368374[28] ? + (_theResult____h368375[28] ? 6'd28 : - (_theResult____h368374[27] ? + (_theResult____h368375[27] ? 6'd29 : - (_theResult____h368374[26] ? + (_theResult____h368375[26] ? 6'd30 : - (_theResult____h368374[25] ? + (_theResult____h368375[25] ? 6'd31 : - (_theResult____h368374[24] ? + (_theResult____h368375[24] ? 6'd32 : - (_theResult____h368374[23] ? + (_theResult____h368375[23] ? 6'd33 : - (_theResult____h368374[22] ? + (_theResult____h368375[22] ? 6'd34 : - (_theResult____h368374[21] ? + (_theResult____h368375[21] ? 6'd35 : - (_theResult____h368374[20] ? + (_theResult____h368375[20] ? 6'd36 : - (_theResult____h368374[19] ? + (_theResult____h368375[19] ? 6'd37 : - (_theResult____h368374[18] ? + (_theResult____h368375[18] ? 6'd38 : - (_theResult____h368374[17] ? + (_theResult____h368375[17] ? 6'd39 : - (_theResult____h368374[16] ? + (_theResult____h368375[16] ? 6'd40 : - (_theResult____h368374[15] ? + (_theResult____h368375[15] ? 6'd41 : - (_theResult____h368374[14] ? + (_theResult____h368375[14] ? 6'd42 : - (_theResult____h368374[13] ? + (_theResult____h368375[13] ? 6'd43 : - (_theResult____h368374[12] ? + (_theResult____h368375[12] ? 6'd44 : - (_theResult____h368374[11] ? + (_theResult____h368375[11] ? 6'd45 : - (_theResult____h368374[10] ? + (_theResult____h368375[10] ? 6'd46 : - (_theResult____h368374[9] ? + (_theResult____h368375[9] ? 6'd47 : - (_theResult____h368374[8] ? + (_theResult____h368375[8] ? 6'd48 : - (_theResult____h368374[7] ? + (_theResult____h368375[7] ? 6'd49 : - (_theResult____h368374[6] ? + (_theResult____h368375[6] ? 6'd50 : - (_theResult____h368374[5] ? + (_theResult____h368375[5] ? 6'd51 : - (_theResult____h368374[4] ? + (_theResult____h368375[4] ? 6'd52 : - (_theResult____h368374[3] ? + (_theResult____h368375[3] ? 6'd53 : - (_theResult____h368374[2] ? + (_theResult____h368375[2] ? 6'd54 : - (_theResult____h368374[1] ? + (_theResult____h368375[1] ? 6'd55 : - (_theResult____h368374[0] ? + (_theResult____h368375[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 = - (_theResult____h414071[56] ? + (_theResult____h414072[56] ? 6'd0 : - (_theResult____h414071[55] ? + (_theResult____h414072[55] ? 6'd1 : - (_theResult____h414071[54] ? + (_theResult____h414072[54] ? 6'd2 : - (_theResult____h414071[53] ? + (_theResult____h414072[53] ? 6'd3 : - (_theResult____h414071[52] ? + (_theResult____h414072[52] ? 6'd4 : - (_theResult____h414071[51] ? + (_theResult____h414072[51] ? 6'd5 : - (_theResult____h414071[50] ? + (_theResult____h414072[50] ? 6'd6 : - (_theResult____h414071[49] ? + (_theResult____h414072[49] ? 6'd7 : - (_theResult____h414071[48] ? + (_theResult____h414072[48] ? 6'd8 : - (_theResult____h414071[47] ? + (_theResult____h414072[47] ? 6'd9 : - (_theResult____h414071[46] ? + (_theResult____h414072[46] ? 6'd10 : - (_theResult____h414071[45] ? + (_theResult____h414072[45] ? 6'd11 : - (_theResult____h414071[44] ? + (_theResult____h414072[44] ? 6'd12 : - (_theResult____h414071[43] ? + (_theResult____h414072[43] ? 6'd13 : - (_theResult____h414071[42] ? + (_theResult____h414072[42] ? 6'd14 : - (_theResult____h414071[41] ? + (_theResult____h414072[41] ? 6'd15 : - (_theResult____h414071[40] ? + (_theResult____h414072[40] ? 6'd16 : - (_theResult____h414071[39] ? + (_theResult____h414072[39] ? 6'd17 : - (_theResult____h414071[38] ? + (_theResult____h414072[38] ? 6'd18 : - (_theResult____h414071[37] ? + (_theResult____h414072[37] ? 6'd19 : - (_theResult____h414071[36] ? + (_theResult____h414072[36] ? 6'd20 : - (_theResult____h414071[35] ? + (_theResult____h414072[35] ? 6'd21 : - (_theResult____h414071[34] ? + (_theResult____h414072[34] ? 6'd22 : - (_theResult____h414071[33] ? + (_theResult____h414072[33] ? 6'd23 : - (_theResult____h414071[32] ? + (_theResult____h414072[32] ? 6'd24 : - (_theResult____h414071[31] ? + (_theResult____h414072[31] ? 6'd25 : - (_theResult____h414071[30] ? + (_theResult____h414072[30] ? 6'd26 : - (_theResult____h414071[29] ? + (_theResult____h414072[29] ? 6'd27 : - (_theResult____h414071[28] ? + (_theResult____h414072[28] ? 6'd28 : - (_theResult____h414071[27] ? + (_theResult____h414072[27] ? 6'd29 : - (_theResult____h414071[26] ? + (_theResult____h414072[26] ? 6'd30 : - (_theResult____h414071[25] ? + (_theResult____h414072[25] ? 6'd31 : - (_theResult____h414071[24] ? + (_theResult____h414072[24] ? 6'd32 : - (_theResult____h414071[23] ? + (_theResult____h414072[23] ? 6'd33 : - (_theResult____h414071[22] ? + (_theResult____h414072[22] ? 6'd34 : - (_theResult____h414071[21] ? + (_theResult____h414072[21] ? 6'd35 : - (_theResult____h414071[20] ? + (_theResult____h414072[20] ? 6'd36 : - (_theResult____h414071[19] ? + (_theResult____h414072[19] ? 6'd37 : - (_theResult____h414071[18] ? + (_theResult____h414072[18] ? 6'd38 : - (_theResult____h414071[17] ? + (_theResult____h414072[17] ? 6'd39 : - (_theResult____h414071[16] ? + (_theResult____h414072[16] ? 6'd40 : - (_theResult____h414071[15] ? + (_theResult____h414072[15] ? 6'd41 : - (_theResult____h414071[14] ? + (_theResult____h414072[14] ? 6'd42 : - (_theResult____h414071[13] ? + (_theResult____h414072[13] ? 6'd43 : - (_theResult____h414071[12] ? + (_theResult____h414072[12] ? 6'd44 : - (_theResult____h414071[11] ? + (_theResult____h414072[11] ? 6'd45 : - (_theResult____h414071[10] ? + (_theResult____h414072[10] ? 6'd46 : - (_theResult____h414071[9] ? + (_theResult____h414072[9] ? 6'd47 : - (_theResult____h414071[8] ? + (_theResult____h414072[8] ? 6'd48 : - (_theResult____h414071[7] ? + (_theResult____h414072[7] ? 6'd49 : - (_theResult____h414071[6] ? + (_theResult____h414072[6] ? 6'd50 : - (_theResult____h414071[5] ? + (_theResult____h414072[5] ? 6'd51 : - (_theResult____h414071[4] ? + (_theResult____h414072[4] ? 6'd52 : - (_theResult____h414071[3] ? + (_theResult____h414072[3] ? 6'd53 : - (_theResult____h414071[2] ? + (_theResult____h414072[2] ? 6'd54 : - (_theResult____h414071[1] ? + (_theResult____h414072[1] ? 6'd55 : - (_theResult____h414071[0] ? + (_theResult____h414072[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 = - (_theResult____h459766[56] ? + (_theResult____h459767[56] ? 6'd0 : - (_theResult____h459766[55] ? + (_theResult____h459767[55] ? 6'd1 : - (_theResult____h459766[54] ? + (_theResult____h459767[54] ? 6'd2 : - (_theResult____h459766[53] ? + (_theResult____h459767[53] ? 6'd3 : - (_theResult____h459766[52] ? + (_theResult____h459767[52] ? 6'd4 : - (_theResult____h459766[51] ? + (_theResult____h459767[51] ? 6'd5 : - (_theResult____h459766[50] ? + (_theResult____h459767[50] ? 6'd6 : - (_theResult____h459766[49] ? + (_theResult____h459767[49] ? 6'd7 : - (_theResult____h459766[48] ? + (_theResult____h459767[48] ? 6'd8 : - (_theResult____h459766[47] ? + (_theResult____h459767[47] ? 6'd9 : - (_theResult____h459766[46] ? + (_theResult____h459767[46] ? 6'd10 : - (_theResult____h459766[45] ? + (_theResult____h459767[45] ? 6'd11 : - (_theResult____h459766[44] ? + (_theResult____h459767[44] ? 6'd12 : - (_theResult____h459766[43] ? + (_theResult____h459767[43] ? 6'd13 : - (_theResult____h459766[42] ? + (_theResult____h459767[42] ? 6'd14 : - (_theResult____h459766[41] ? + (_theResult____h459767[41] ? 6'd15 : - (_theResult____h459766[40] ? + (_theResult____h459767[40] ? 6'd16 : - (_theResult____h459766[39] ? + (_theResult____h459767[39] ? 6'd17 : - (_theResult____h459766[38] ? + (_theResult____h459767[38] ? 6'd18 : - (_theResult____h459766[37] ? + (_theResult____h459767[37] ? 6'd19 : - (_theResult____h459766[36] ? + (_theResult____h459767[36] ? 6'd20 : - (_theResult____h459766[35] ? + (_theResult____h459767[35] ? 6'd21 : - (_theResult____h459766[34] ? + (_theResult____h459767[34] ? 6'd22 : - (_theResult____h459766[33] ? + (_theResult____h459767[33] ? 6'd23 : - (_theResult____h459766[32] ? + (_theResult____h459767[32] ? 6'd24 : - (_theResult____h459766[31] ? + (_theResult____h459767[31] ? 6'd25 : - (_theResult____h459766[30] ? + (_theResult____h459767[30] ? 6'd26 : - (_theResult____h459766[29] ? + (_theResult____h459767[29] ? 6'd27 : - (_theResult____h459766[28] ? + (_theResult____h459767[28] ? 6'd28 : - (_theResult____h459766[27] ? + (_theResult____h459767[27] ? 6'd29 : - (_theResult____h459766[26] ? + (_theResult____h459767[26] ? 6'd30 : - (_theResult____h459766[25] ? + (_theResult____h459767[25] ? 6'd31 : - (_theResult____h459766[24] ? + (_theResult____h459767[24] ? 6'd32 : - (_theResult____h459766[23] ? + (_theResult____h459767[23] ? 6'd33 : - (_theResult____h459766[22] ? + (_theResult____h459767[22] ? 6'd34 : - (_theResult____h459766[21] ? + (_theResult____h459767[21] ? 6'd35 : - (_theResult____h459766[20] ? + (_theResult____h459767[20] ? 6'd36 : - (_theResult____h459766[19] ? + (_theResult____h459767[19] ? 6'd37 : - (_theResult____h459766[18] ? + (_theResult____h459767[18] ? 6'd38 : - (_theResult____h459766[17] ? + (_theResult____h459767[17] ? 6'd39 : - (_theResult____h459766[16] ? + (_theResult____h459767[16] ? 6'd40 : - (_theResult____h459766[15] ? + (_theResult____h459767[15] ? 6'd41 : - (_theResult____h459766[14] ? + (_theResult____h459767[14] ? 6'd42 : - (_theResult____h459766[13] ? + (_theResult____h459767[13] ? 6'd43 : - (_theResult____h459766[12] ? + (_theResult____h459767[12] ? 6'd44 : - (_theResult____h459766[11] ? + (_theResult____h459767[11] ? 6'd45 : - (_theResult____h459766[10] ? + (_theResult____h459767[10] ? 6'd46 : - (_theResult____h459766[9] ? + (_theResult____h459767[9] ? 6'd47 : - (_theResult____h459766[8] ? + (_theResult____h459767[8] ? 6'd48 : - (_theResult____h459766[7] ? + (_theResult____h459767[7] ? 6'd49 : - (_theResult____h459766[6] ? + (_theResult____h459767[6] ? 6'd50 : - (_theResult____h459766[5] ? + (_theResult____h459767[5] ? 6'd51 : - (_theResult____h459766[4] ? + (_theResult____h459767[4] ? 6'd52 : - (_theResult____h459766[3] ? + (_theResult____h459767[3] ? 6'd53 : - (_theResult____h459766[2] ? + (_theResult____h459767[2] ? 6'd54 : - (_theResult____h459766[1] ? + (_theResult____h459767[1] ? 6'd55 : - (_theResult____h459766[0] ? + (_theResult____h459767[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10033 = - (_theResult___fst_exp__h594648 == 11'd2047) ? + (_theResult___fst_exp__h594649 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -18994,10 +18994,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : + CASE_guard86423_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10535 = - (_theResult___fst_exp__h555344 == 11'd2047) ? + (_theResult___fst_exp__h555345 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19005,10 +19005,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : + CASE_guard47119_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10802 = - (_theResult___fst_exp__h555344 == 11'd2047) ? + (_theResult___fst_exp__h555345 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19016,10 +19016,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : + CASE_guard47119_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9050 = - (_theResult___fst_exp__h516491 == 11'd2047) ? + (_theResult___fst_exp__h516492 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19027,10 +19027,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : + CASE_guard08266_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9765 = - (_theResult___fst_exp__h594648 == 11'd2047) ? + (_theResult___fst_exp__h594649 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19038,538 +19038,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : + CASE_guard86423_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 = - (guard__h350745 == 2'b0 || + (guard__h350746 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h358846 : - _theResult___exp__h359362 ; + _theResult___fst_exp__h358847 : + _theResult___exp__h359363 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 = - (guard__h350745 == 2'b0) ? - _theResult___fst_exp__h358846 : + (guard__h350746 == 2'b0) ? + _theResult___fst_exp__h358847 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h359362 : - _theResult___fst_exp__h358846) ; + _theResult___exp__h359363 : + _theResult___fst_exp__h358847) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 = - (guard__h350745 == 2'b0 || + (guard__h350746 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h358840[56:34] : - _theResult___sfd__h359363 ; + sfdin__h358841[56:34] : + _theResult___sfd__h359364 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 = - (guard__h350745 == 2'b0) ? - sfdin__h358840[56:34] : + (guard__h350746 == 2'b0) ? + sfdin__h358841[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h359363 : - sfdin__h358840[56:34]) ; + _theResult___sfd__h359364 : + sfdin__h358841[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 = - (guard__h396444 == 2'b0 || + (guard__h396445 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h404543 : - _theResult___exp__h405059 ; + _theResult___fst_exp__h404544 : + _theResult___exp__h405060 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 = - (guard__h396444 == 2'b0) ? - _theResult___fst_exp__h404543 : + (guard__h396445 == 2'b0) ? + _theResult___fst_exp__h404544 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h405059 : - _theResult___fst_exp__h404543) ; + _theResult___exp__h405060 : + _theResult___fst_exp__h404544) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 = - (guard__h396444 == 2'b0 || + (guard__h396445 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h404537[56:34] : - _theResult___sfd__h405060 ; + sfdin__h404538[56:34] : + _theResult___sfd__h405061 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 = - (guard__h396444 == 2'b0) ? - sfdin__h404537[56:34] : + (guard__h396445 == 2'b0) ? + sfdin__h404538[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h405060 : - sfdin__h404537[56:34]) ; + _theResult___sfd__h405061 : + sfdin__h404538[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 = - (guard__h442139 == 2'b0 || + (guard__h442140 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h450238 : - _theResult___exp__h450754 ; + _theResult___fst_exp__h450239 : + _theResult___exp__h450755 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 = - (guard__h442139 == 2'b0) ? - _theResult___fst_exp__h450238 : + (guard__h442140 == 2'b0) ? + _theResult___fst_exp__h450239 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h450754 : - _theResult___fst_exp__h450238) ; + _theResult___exp__h450755 : + _theResult___fst_exp__h450239) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 = - (guard__h442139 == 2'b0 || + (guard__h442140 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h450232[56:34] : - _theResult___sfd__h450755 ; + sfdin__h450233[56:34] : + _theResult___sfd__h450756 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 = - (guard__h442139 == 2'b0) ? - sfdin__h450232[56:34] : + (guard__h442140 == 2'b0) ? + sfdin__h450233[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h450755 : - sfdin__h450232[56:34]) ; + _theResult___sfd__h450756 : + sfdin__h450233[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 = - (guard__h547118 == 2'b0 || + (guard__h547119 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h555344 : - _theResult___exp__h556073 ; + _theResult___fst_exp__h555345 : + _theResult___exp__h556074 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 = - (guard__h547118 == 2'b0) ? - _theResult___fst_exp__h555344 : + (guard__h547119 == 2'b0) ? + _theResult___fst_exp__h555345 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h556073 : - _theResult___fst_exp__h555344) ; + _theResult___exp__h556074 : + _theResult___fst_exp__h555345) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 = - (guard__h547118 == 2'b0 || + (guard__h547119 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h555338[56:5] : - _theResult___sfd__h556074 ; + sfdin__h555339[56:5] : + _theResult___sfd__h556075 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 = - (guard__h547118 == 2'b0) ? - sfdin__h555338[56:5] : + (guard__h547119 == 2'b0) ? + sfdin__h555339[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h556074 : - sfdin__h555338[56:5]) ; + _theResult___sfd__h556075 : + sfdin__h555339[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 = - (guard__h508265 == 2'b0 || + (guard__h508266 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h516491 : - _theResult___exp__h517220 ; + _theResult___fst_exp__h516492 : + _theResult___exp__h517221 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 = - (guard__h508265 == 2'b0) ? - _theResult___fst_exp__h516491 : + (guard__h508266 == 2'b0) ? + _theResult___fst_exp__h516492 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h517220 : - _theResult___fst_exp__h516491) ; + _theResult___exp__h517221 : + _theResult___fst_exp__h516492) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 = - (guard__h508265 == 2'b0 || + (guard__h508266 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h516485[56:5] : - _theResult___sfd__h517221 ; + sfdin__h516486[56:5] : + _theResult___sfd__h517222 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 = - (guard__h508265 == 2'b0) ? - sfdin__h516485[56:5] : + (guard__h508266 == 2'b0) ? + sfdin__h516486[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h517221 : - sfdin__h516485[56:5]) ; + _theResult___sfd__h517222 : + sfdin__h516486[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 = - (guard__h586422 == 2'b0 || + (guard__h586423 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h594648 : - _theResult___exp__h595377 ; + _theResult___fst_exp__h594649 : + _theResult___exp__h595378 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 = - (guard__h586422 == 2'b0) ? - _theResult___fst_exp__h594648 : + (guard__h586423 == 2'b0) ? + _theResult___fst_exp__h594649 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h595377 : - _theResult___fst_exp__h594648) ; + _theResult___exp__h595378 : + _theResult___fst_exp__h594649) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 = - (guard__h586422 == 2'b0 || + (guard__h586423 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h594642[56:5] : - _theResult___sfd__h595378 ; + sfdin__h594643[56:5] : + _theResult___sfd__h595379 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 = - (guard__h586422 == 2'b0) ? - sfdin__h594642[56:5] : + (guard__h586423 == 2'b0) ? + sfdin__h594643[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h595378 : - sfdin__h594642[56:5]) ; + _theResult___sfd__h595379 : + sfdin__h594643[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 = - (guard__h368384 == 2'b0 || + (guard__h368385 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h376612 : - _theResult___exp__h377128 ; + _theResult___fst_exp__h376613 : + _theResult___exp__h377129 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 = - (guard__h368384 == 2'b0) ? - _theResult___fst_exp__h376612 : + (guard__h368385 == 2'b0) ? + _theResult___fst_exp__h376613 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h377128 : - _theResult___fst_exp__h376612) ; + _theResult___exp__h377129 : + _theResult___fst_exp__h376613) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 = - (guard__h368384 == 2'b0 || + (guard__h368385 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h376606[56:34] : - _theResult___sfd__h377129 ; + sfdin__h376607[56:34] : + _theResult___sfd__h377130 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 = - (guard__h368384 == 2'b0) ? - sfdin__h376606[56:34] : + (guard__h368385 == 2'b0) ? + sfdin__h376607[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h377129 : - sfdin__h376606[56:34]) ; + _theResult___sfd__h377130 : + sfdin__h376607[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 = - (guard__h414081 == 2'b0 || + (guard__h414082 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h422309 : - _theResult___exp__h422825 ; + _theResult___fst_exp__h422310 : + _theResult___exp__h422826 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 = - (guard__h414081 == 2'b0) ? - _theResult___fst_exp__h422309 : + (guard__h414082 == 2'b0) ? + _theResult___fst_exp__h422310 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h422825 : - _theResult___fst_exp__h422309) ; + _theResult___exp__h422826 : + _theResult___fst_exp__h422310) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 = - (guard__h414081 == 2'b0 || + (guard__h414082 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h422303[56:34] : - _theResult___sfd__h422826 ; + sfdin__h422304[56:34] : + _theResult___sfd__h422827 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 = - (guard__h414081 == 2'b0) ? - sfdin__h422303[56:34] : + (guard__h414082 == 2'b0) ? + sfdin__h422304[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h422826 : - sfdin__h422303[56:34]) ; + _theResult___sfd__h422827 : + sfdin__h422304[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 = - (guard__h459776 == 2'b0 || + (guard__h459777 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h468004 : - _theResult___exp__h468520 ; + _theResult___fst_exp__h468005 : + _theResult___exp__h468521 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 = - (guard__h459776 == 2'b0) ? - _theResult___fst_exp__h468004 : + (guard__h459777 == 2'b0) ? + _theResult___fst_exp__h468005 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h468520 : - _theResult___fst_exp__h468004) ; + _theResult___exp__h468521 : + _theResult___fst_exp__h468005) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 = - (guard__h459776 == 2'b0 || + (guard__h459777 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h467998[56:34] : - _theResult___sfd__h468521 ; + sfdin__h467999[56:34] : + _theResult___sfd__h468522 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 = - (guard__h459776 == 2'b0) ? - sfdin__h467998[56:34] : + (guard__h459777 == 2'b0) ? + sfdin__h467999[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h468521 : - sfdin__h467998[56:34]) ; + _theResult___sfd__h468522 : + sfdin__h467999[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 = - (guard__h537806 == 2'b0 || + (guard__h537807 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h545767 : - _theResult___exp__h546422 ; + _theResult___fst_exp__h545768 : + _theResult___exp__h546423 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 = - (guard__h537806 == 2'b0) ? - _theResult___fst_exp__h545767 : + (guard__h537807 == 2'b0) ? + _theResult___fst_exp__h545768 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h546422 : - _theResult___fst_exp__h545767) ; + _theResult___exp__h546423 : + _theResult___fst_exp__h545768) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 = - (guard__h556187 == 2'b0 || + (guard__h556188 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h564177 : - _theResult___exp__h564857 ; + _theResult___fst_exp__h564178 : + _theResult___exp__h564858 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 = - (guard__h556187 == 2'b0) ? - _theResult___fst_exp__h564177 : + (guard__h556188 == 2'b0) ? + _theResult___fst_exp__h564178 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h564857 : - _theResult___fst_exp__h564177) ; + _theResult___exp__h564858 : + _theResult___fst_exp__h564178) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 = - (guard__h537806 == 2'b0 || + (guard__h537807 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h545718[56:5] : - _theResult___sfd__h546423 ; + _theResult___snd__h545719[56:5] : + _theResult___sfd__h546424 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 = - (guard__h537806 == 2'b0) ? - _theResult___snd__h545718[56:5] : + (guard__h537807 == 2'b0) ? + _theResult___snd__h545719[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h546423 : - _theResult___snd__h545718[56:5]) ; + _theResult___sfd__h546424 : + _theResult___snd__h545719[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 = - (guard__h556187 == 2'b0 || + (guard__h556188 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h564123[56:5] : - _theResult___sfd__h564858 ; + _theResult___snd__h564124[56:5] : + _theResult___sfd__h564859 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 = - (guard__h556187 == 2'b0) ? - _theResult___snd__h564123[56:5] : + (guard__h556188 == 2'b0) ? + _theResult___snd__h564124[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h564858 : - _theResult___snd__h564123[56:5]) ; + _theResult___sfd__h564859 : + _theResult___snd__h564124[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 = - (guard__h498953 == 2'b0 || + (guard__h498954 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h506914 : - _theResult___exp__h507569 ; + _theResult___fst_exp__h506915 : + _theResult___exp__h507570 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 = - (guard__h498953 == 2'b0) ? - _theResult___fst_exp__h506914 : + (guard__h498954 == 2'b0) ? + _theResult___fst_exp__h506915 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h507569 : - _theResult___fst_exp__h506914) ; + _theResult___exp__h507570 : + _theResult___fst_exp__h506915) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 = - (guard__h517334 == 2'b0 || + (guard__h517335 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h525324 : - _theResult___exp__h526004 ; + _theResult___fst_exp__h525325 : + _theResult___exp__h526005 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 = - (guard__h517334 == 2'b0) ? - _theResult___fst_exp__h525324 : + (guard__h517335 == 2'b0) ? + _theResult___fst_exp__h525325 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h526004 : - _theResult___fst_exp__h525324) ; + _theResult___exp__h526005 : + _theResult___fst_exp__h525325) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 = - (guard__h498953 == 2'b0 || + (guard__h498954 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h506865[56:5] : - _theResult___sfd__h507570 ; + _theResult___snd__h506866[56:5] : + _theResult___sfd__h507571 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 = - (guard__h498953 == 2'b0) ? - _theResult___snd__h506865[56:5] : + (guard__h498954 == 2'b0) ? + _theResult___snd__h506866[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h507570 : - _theResult___snd__h506865[56:5]) ; + _theResult___sfd__h507571 : + _theResult___snd__h506866[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 = - (guard__h517334 == 2'b0 || + (guard__h517335 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h525270[56:5] : - _theResult___sfd__h526005 ; + _theResult___snd__h525271[56:5] : + _theResult___sfd__h526006 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 = - (guard__h517334 == 2'b0) ? - _theResult___snd__h525270[56:5] : + (guard__h517335 == 2'b0) ? + _theResult___snd__h525271[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h526005 : - _theResult___snd__h525270[56:5]) ; + _theResult___sfd__h526006 : + _theResult___snd__h525271[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 = - (guard__h577110 == 2'b0 || + (guard__h577111 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h585071 : - _theResult___exp__h585726 ; + _theResult___fst_exp__h585072 : + _theResult___exp__h585727 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 = - (guard__h577110 == 2'b0) ? - _theResult___fst_exp__h585071 : + (guard__h577111 == 2'b0) ? + _theResult___fst_exp__h585072 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h585726 : - _theResult___fst_exp__h585071) ; + _theResult___exp__h585727 : + _theResult___fst_exp__h585072) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 = - (guard__h595491 == 2'b0 || + (guard__h595492 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h603481 : - _theResult___exp__h604161 ; + _theResult___fst_exp__h603482 : + _theResult___exp__h604162 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 = - (guard__h595491 == 2'b0) ? - _theResult___fst_exp__h603481 : + (guard__h595492 == 2'b0) ? + _theResult___fst_exp__h603482 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h604161 : - _theResult___fst_exp__h603481) ; + _theResult___exp__h604162 : + _theResult___fst_exp__h603482) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 = - (guard__h577110 == 2'b0 || + (guard__h577111 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h585022[56:5] : - _theResult___sfd__h585727 ; + _theResult___snd__h585023[56:5] : + _theResult___sfd__h585728 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 = - (guard__h577110 == 2'b0) ? - _theResult___snd__h585022[56:5] : + (guard__h577111 == 2'b0) ? + _theResult___snd__h585023[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h585727 : - _theResult___snd__h585022[56:5]) ; + _theResult___sfd__h585728 : + _theResult___snd__h585023[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 = - (guard__h595491 == 2'b0 || + (guard__h595492 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h603427[56:5] : - _theResult___sfd__h604162 ; + _theResult___snd__h603428[56:5] : + _theResult___sfd__h604163 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 = - (guard__h595491 == 2'b0) ? - _theResult___snd__h603427[56:5] : + (guard__h595492 == 2'b0) ? + _theResult___snd__h603428[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h604162 : - _theResult___snd__h603427[56:5]) ; + _theResult___sfd__h604163 : + _theResult___snd__h603428[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 = - (guard__h359454 == 2'b0 || + (guard__h359455 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h367502 : - _theResult___exp__h367944 ; + _theResult___fst_exp__h367503 : + _theResult___exp__h367945 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 = - (guard__h359454 == 2'b0) ? - _theResult___fst_exp__h367502 : + (guard__h359455 == 2'b0) ? + _theResult___fst_exp__h367503 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h367944 : - _theResult___fst_exp__h367502) ; + _theResult___exp__h367945 : + _theResult___fst_exp__h367503) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h377220 == 2'b0 || + (guard__h377221 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h385297 : - _theResult___exp__h385764 ; + _theResult___fst_exp__h385298 : + _theResult___exp__h385765 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h377220 == 2'b0) ? - _theResult___fst_exp__h385297 : + (guard__h377221 == 2'b0) ? + _theResult___fst_exp__h385298 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h385764 : - _theResult___fst_exp__h385297) ; + _theResult___exp__h385765 : + _theResult___fst_exp__h385298) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 = - (guard__h359454 == 2'b0 || + (guard__h359455 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h367453[56:34] : - _theResult___sfd__h367945 ; + _theResult___snd__h367454[56:34] : + _theResult___sfd__h367946 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 = - (guard__h359454 == 2'b0) ? - _theResult___snd__h367453[56:34] : + (guard__h359455 == 2'b0) ? + _theResult___snd__h367454[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h367945 : - _theResult___snd__h367453[56:34]) ; + _theResult___sfd__h367946 : + _theResult___snd__h367454[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 = - (guard__h377220 == 2'b0 || + (guard__h377221 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h385243[56:34] : - _theResult___sfd__h385765 ; + _theResult___snd__h385244[56:34] : + _theResult___sfd__h385766 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 = - (guard__h377220 == 2'b0) ? - _theResult___snd__h385243[56:34] : + (guard__h377221 == 2'b0) ? + _theResult___snd__h385244[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h385765 : - _theResult___snd__h385243[56:34]) ; + _theResult___sfd__h385766 : + _theResult___snd__h385244[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 = - (guard__h405151 == 2'b0 || + (guard__h405152 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h413199 : - _theResult___exp__h413641 ; + _theResult___fst_exp__h413200 : + _theResult___exp__h413642 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 = - (guard__h405151 == 2'b0) ? - _theResult___fst_exp__h413199 : + (guard__h405152 == 2'b0) ? + _theResult___fst_exp__h413200 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h413641 : - _theResult___fst_exp__h413199) ; + _theResult___exp__h413642 : + _theResult___fst_exp__h413200) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h422917 == 2'b0 || + (guard__h422918 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h430994 : - _theResult___exp__h431461 ; + _theResult___fst_exp__h430995 : + _theResult___exp__h431462 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h422917 == 2'b0) ? - _theResult___fst_exp__h430994 : + (guard__h422918 == 2'b0) ? + _theResult___fst_exp__h430995 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h431461 : - _theResult___fst_exp__h430994) ; + _theResult___exp__h431462 : + _theResult___fst_exp__h430995) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 = - (guard__h405151 == 2'b0 || + (guard__h405152 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h413150[56:34] : - _theResult___sfd__h413642 ; + _theResult___snd__h413151[56:34] : + _theResult___sfd__h413643 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 = - (guard__h405151 == 2'b0) ? - _theResult___snd__h413150[56:34] : + (guard__h405152 == 2'b0) ? + _theResult___snd__h413151[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h413642 : - _theResult___snd__h413150[56:34]) ; + _theResult___sfd__h413643 : + _theResult___snd__h413151[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 = - (guard__h422917 == 2'b0 || + (guard__h422918 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h430940[56:34] : - _theResult___sfd__h431462 ; + _theResult___snd__h430941[56:34] : + _theResult___sfd__h431463 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 = - (guard__h422917 == 2'b0) ? - _theResult___snd__h430940[56:34] : + (guard__h422918 == 2'b0) ? + _theResult___snd__h430941[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h431462 : - _theResult___snd__h430940[56:34]) ; + _theResult___sfd__h431463 : + _theResult___snd__h430941[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 = - (guard__h450846 == 2'b0 || + (guard__h450847 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h458894 : - _theResult___exp__h459336 ; + _theResult___fst_exp__h458895 : + _theResult___exp__h459337 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 = - (guard__h450846 == 2'b0) ? - _theResult___fst_exp__h458894 : + (guard__h450847 == 2'b0) ? + _theResult___fst_exp__h458895 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h459336 : - _theResult___fst_exp__h458894) ; + _theResult___exp__h459337 : + _theResult___fst_exp__h458895) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h468612 == 2'b0 || + (guard__h468613 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h476689 : - _theResult___exp__h477156 ; + _theResult___fst_exp__h476690 : + _theResult___exp__h477157 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h468612 == 2'b0) ? - _theResult___fst_exp__h476689 : + (guard__h468613 == 2'b0) ? + _theResult___fst_exp__h476690 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h477156 : - _theResult___fst_exp__h476689) ; + _theResult___exp__h477157 : + _theResult___fst_exp__h476690) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 = - (guard__h450846 == 2'b0 || + (guard__h450847 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h458845[56:34] : - _theResult___sfd__h459337 ; + _theResult___snd__h458846[56:34] : + _theResult___sfd__h459338 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 = - (guard__h450846 == 2'b0) ? - _theResult___snd__h458845[56:34] : + (guard__h450847 == 2'b0) ? + _theResult___snd__h458846[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h459337 : - _theResult___snd__h458845[56:34]) ; + _theResult___sfd__h459338 : + _theResult___snd__h458846[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 = - (guard__h468612 == 2'b0 || + (guard__h468613 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h476635[56:34] : - _theResult___sfd__h477157 ; + _theResult___snd__h476636[56:34] : + _theResult___sfd__h477158 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 = - (guard__h468612 == 2'b0) ? - _theResult___snd__h476635[56:34] : + (guard__h468613 == 2'b0) ? + _theResult___snd__h476636[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h477157 : - _theResult___snd__h476635[56:34]) ; + _theResult___sfd__h477158 : + _theResult___snd__h476636[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10018 = - (_theResult___fst_exp__h585071 == 11'd2047) ? + (_theResult___fst_exp__h585072 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19577,10 +19577,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : + CASE_guard77111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045 = - (_theResult___fst_exp__h603481 == 11'd2047) ? + (_theResult___fst_exp__h603482 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19588,10 +19588,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : + CASE_guard95492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581 = - (_theResult___fst_exp__h564177 == 11'd2047) ? + (_theResult___fst_exp__h564178 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19599,10 +19599,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : + CASE_guard56188_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10787 = - (_theResult___fst_exp__h545767 == 11'd2047) ? + (_theResult___fst_exp__h545768 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19610,10 +19610,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : + CASE_guard37807_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814 = - (_theResult___fst_exp__h564177 == 11'd2047) ? + (_theResult___fst_exp__h564178 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -19621,10 +19621,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : + CASE_guard56188_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 = - (_theResult___fst_exp__h525324 == 11'd2047) ? + (_theResult___fst_exp__h525325 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -19632,10 +19632,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : + CASE_guard17335_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811 = - (_theResult___fst_exp__h603481 == 11'd2047) ? + (_theResult___fst_exp__h603482 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -19643,14 +19643,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : + CASE_guard95492_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ; assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992 = - (_theResult____h658026 == 12'd0 && + (_theResult____h658027 == 12'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h658485 : - _theResult____h658026 ; + enabled_ints__h658486 : + _theResult____h658027 ; assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13204 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] || IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] || @@ -19700,7 +19700,7 @@ module mkCore(CLK, checkForException___d13792[4] || csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13881 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565825 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -19710,85 +19710,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049 = - (f3_exp__h565824 == 8'd255 && f3_sfd__h565825 != 23'd0 || - (f3_exp__h565824 == 8'd255 || f3_exp__h565824 == 8'd0) && - f3_sfd__h565825 == 23'd0) ? + (f3_exp__h565825 == 8'd255 && f3_sfd__h565826 != 23'd0 || + (f3_exp__h565825 == 8'd255 || f3_exp__h565825 == 8'd0) && + f3_sfd__h565826 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 = - ((f2_exp__h526520 == 8'd0) ? - (f2_sfd__h526521[22] ? + ((f2_exp__h526521 == 8'd0) ? + (f2_sfd__h526522[22] ? 6'd2 : - (f2_sfd__h526521[21] ? + (f2_sfd__h526522[21] ? 6'd3 : - (f2_sfd__h526521[20] ? + (f2_sfd__h526522[20] ? 6'd4 : - (f2_sfd__h526521[19] ? + (f2_sfd__h526522[19] ? 6'd5 : - (f2_sfd__h526521[18] ? + (f2_sfd__h526522[18] ? 6'd6 : - (f2_sfd__h526521[17] ? + (f2_sfd__h526522[17] ? 6'd7 : - (f2_sfd__h526521[16] ? + (f2_sfd__h526522[16] ? 6'd8 : - (f2_sfd__h526521[15] ? + (f2_sfd__h526522[15] ? 6'd9 : - (f2_sfd__h526521[14] ? + (f2_sfd__h526522[14] ? 6'd10 : - (f2_sfd__h526521[13] ? + (f2_sfd__h526522[13] ? 6'd11 : - (f2_sfd__h526521[12] ? + (f2_sfd__h526522[12] ? 6'd12 : - (f2_sfd__h526521[11] ? + (f2_sfd__h526522[11] ? 6'd13 : - (f2_sfd__h526521[10] ? + (f2_sfd__h526522[10] ? 6'd14 : - (f2_sfd__h526521[9] ? + (f2_sfd__h526522[9] ? 6'd15 : - (f2_sfd__h526521[8] ? + (f2_sfd__h526522[8] ? 6'd16 : - (f2_sfd__h526521[7] ? + (f2_sfd__h526522[7] ? 6'd17 : - (f2_sfd__h526521[6] ? + (f2_sfd__h526522[6] ? 6'd18 : - (f2_sfd__h526521[5] ? + (f2_sfd__h526522[5] ? 6'd19 : - (f2_sfd__h526521[4] ? + (f2_sfd__h526522[4] ? 6'd20 : - (f2_sfd__h526521[3] ? + (f2_sfd__h526522[3] ? 6'd21 : - (f2_sfd__h526521[2] ? + (f2_sfd__h526522[2] ? 6'd22 : - (f2_sfd__h526521[1] ? + (f2_sfd__h526522[1] ? 6'd23 : - (f2_sfd__h526521[0] ? + (f2_sfd__h526522[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585 = - (f2_exp__h526520 == 8'd255 && f2_sfd__h526521 != 23'd0 || - (f2_exp__h526520 == 8'd255 || f2_exp__h526520 == 8'd0) && - f2_sfd__h526521 == 23'd0) ? + (f2_exp__h526521 == 8'd255 && f2_sfd__h526522 != 23'd0 || + (f2_exp__h526521 == 8'd255 || f2_exp__h526521 == 8'd0) && + f2_sfd__h526522 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h526520 == 8'd0) ? + ((f2_exp__h526521 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f2_exp__h526520 == 8'd255 && f2_sfd__h526521 != 23'd0) ? - _theResult___snd_fst_sfd__h526836 : - _theResult___fst_sfd__h564976 ; + (f2_exp__h526521 == 8'd255 && f2_sfd__h526522 != 23'd0) ? + _theResult___snd_fst_sfd__h526837 : + _theResult___fst_sfd__h564977 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 = - { (f2_exp__h526520 == 8'd255) ? + { (f2_exp__h526521 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h564972, + _theResult___fst_exp__h564973, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526521 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -19798,15 +19798,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 = - (f2_exp__h526520 == 8'd255 && f2_sfd__h526521 != 23'd0 || - (f2_exp__h526520 == 8'd255 || f2_exp__h526520 == 8'd0) && - f2_sfd__h526521 == 23'd0) ? + (f2_exp__h526521 == 8'd255 && f2_sfd__h526522 != 23'd0 || + (f2_exp__h526521 == 8'd255 || f2_exp__h526521 == 8'd0) && + f2_sfd__h526522 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487527 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[4] : @@ -19814,7 +19814,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526521 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[4] : @@ -19822,7 +19822,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565825 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[4] : @@ -19830,7 +19830,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487527 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[3] : @@ -19838,7 +19838,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526521 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[3] : @@ -19846,7 +19846,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565825 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[3] : @@ -19854,208 +19854,208 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487527 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526521 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565825 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487527 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526521 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565825 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 = - (f1_exp__h487526 == 8'd0) ? + (f1_exp__h487527 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113 = - (f2_exp__h526520 == 8'd0) ? + (f2_exp__h526521 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126 = - (f3_exp__h565824 == 8'd0) ? + (f3_exp__h565825 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 = - ((f1_exp__h487526 == 8'd0) ? - (f1_sfd__h487527[22] ? + ((f1_exp__h487527 == 8'd0) ? + (f1_sfd__h487528[22] ? 6'd2 : - (f1_sfd__h487527[21] ? + (f1_sfd__h487528[21] ? 6'd3 : - (f1_sfd__h487527[20] ? + (f1_sfd__h487528[20] ? 6'd4 : - (f1_sfd__h487527[19] ? + (f1_sfd__h487528[19] ? 6'd5 : - (f1_sfd__h487527[18] ? + (f1_sfd__h487528[18] ? 6'd6 : - (f1_sfd__h487527[17] ? + (f1_sfd__h487528[17] ? 6'd7 : - (f1_sfd__h487527[16] ? + (f1_sfd__h487528[16] ? 6'd8 : - (f1_sfd__h487527[15] ? + (f1_sfd__h487528[15] ? 6'd9 : - (f1_sfd__h487527[14] ? + (f1_sfd__h487528[14] ? 6'd10 : - (f1_sfd__h487527[13] ? + (f1_sfd__h487528[13] ? 6'd11 : - (f1_sfd__h487527[12] ? + (f1_sfd__h487528[12] ? 6'd12 : - (f1_sfd__h487527[11] ? + (f1_sfd__h487528[11] ? 6'd13 : - (f1_sfd__h487527[10] ? + (f1_sfd__h487528[10] ? 6'd14 : - (f1_sfd__h487527[9] ? + (f1_sfd__h487528[9] ? 6'd15 : - (f1_sfd__h487527[8] ? + (f1_sfd__h487528[8] ? 6'd16 : - (f1_sfd__h487527[7] ? + (f1_sfd__h487528[7] ? 6'd17 : - (f1_sfd__h487527[6] ? + (f1_sfd__h487528[6] ? 6'd18 : - (f1_sfd__h487527[5] ? + (f1_sfd__h487528[5] ? 6'd19 : - (f1_sfd__h487527[4] ? + (f1_sfd__h487528[4] ? 6'd20 : - (f1_sfd__h487527[3] ? + (f1_sfd__h487528[3] ? 6'd21 : - (f1_sfd__h487527[2] ? + (f1_sfd__h487528[2] ? 6'd22 : - (f1_sfd__h487527[1] ? + (f1_sfd__h487528[1] ? 6'd23 : - (f1_sfd__h487527[0] ? + (f1_sfd__h487528[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100 = - (f1_exp__h487526 == 8'd255 && f1_sfd__h487527 != 23'd0 || - (f1_exp__h487526 == 8'd255 || f1_exp__h487526 == 8'd0) && - f1_sfd__h487527 == 23'd0) ? + (f1_exp__h487527 == 8'd255 && f1_sfd__h487528 != 23'd0 || + (f1_exp__h487527 == 8'd255 || f1_exp__h487527 == 8'd0) && + f1_sfd__h487528 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h487526 == 8'd0) ? + ((f1_exp__h487527 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 = - (f1_exp__h487526 == 8'd255 && f1_sfd__h487527 != 23'd0) ? - _theResult___snd_fst_sfd__h487842 : - _theResult___fst_sfd__h526123 ; + (f1_exp__h487527 == 8'd255 && f1_sfd__h487528 != 23'd0) ? + _theResult___snd_fst_sfd__h487843 : + _theResult___fst_sfd__h526124 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100, - (f1_exp__h487526 == 8'd255) ? + (f1_exp__h487527 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h526119, + _theResult___fst_exp__h526120, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 = - ((f3_exp__h565824 == 8'd0) ? - (f3_sfd__h565825[22] ? + ((f3_exp__h565825 == 8'd0) ? + (f3_sfd__h565826[22] ? 6'd2 : - (f3_sfd__h565825[21] ? + (f3_sfd__h565826[21] ? 6'd3 : - (f3_sfd__h565825[20] ? + (f3_sfd__h565826[20] ? 6'd4 : - (f3_sfd__h565825[19] ? + (f3_sfd__h565826[19] ? 6'd5 : - (f3_sfd__h565825[18] ? + (f3_sfd__h565826[18] ? 6'd6 : - (f3_sfd__h565825[17] ? + (f3_sfd__h565826[17] ? 6'd7 : - (f3_sfd__h565825[16] ? + (f3_sfd__h565826[16] ? 6'd8 : - (f3_sfd__h565825[15] ? + (f3_sfd__h565826[15] ? 6'd9 : - (f3_sfd__h565825[14] ? + (f3_sfd__h565826[14] ? 6'd10 : - (f3_sfd__h565825[13] ? + (f3_sfd__h565826[13] ? 6'd11 : - (f3_sfd__h565825[12] ? + (f3_sfd__h565826[12] ? 6'd12 : - (f3_sfd__h565825[11] ? + (f3_sfd__h565826[11] ? 6'd13 : - (f3_sfd__h565825[10] ? + (f3_sfd__h565826[10] ? 6'd14 : - (f3_sfd__h565825[9] ? + (f3_sfd__h565826[9] ? 6'd15 : - (f3_sfd__h565825[8] ? + (f3_sfd__h565826[8] ? 6'd16 : - (f3_sfd__h565825[7] ? + (f3_sfd__h565826[7] ? 6'd17 : - (f3_sfd__h565825[6] ? + (f3_sfd__h565826[6] ? 6'd18 : - (f3_sfd__h565825[5] ? + (f3_sfd__h565826[5] ? 6'd19 : - (f3_sfd__h565825[4] ? + (f3_sfd__h565826[4] ? 6'd20 : - (f3_sfd__h565825[3] ? + (f3_sfd__h565826[3] ? 6'd21 : - (f3_sfd__h565825[2] ? + (f3_sfd__h565826[2] ? 6'd22 : - (f3_sfd__h565825[1] ? + (f3_sfd__h565826[1] ? 6'd23 : - (f3_sfd__h565825[0] ? + (f3_sfd__h565826[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815 = - (f3_exp__h565824 == 8'd255 && f3_sfd__h565825 != 23'd0 || - (f3_exp__h565824 == 8'd255 || f3_exp__h565824 == 8'd0) && - f3_sfd__h565825 == 23'd0) ? + (f3_exp__h565825 == 8'd255 && f3_sfd__h565826 != 23'd0 || + (f3_exp__h565825 == 8'd255 || f3_exp__h565825 == 8'd0) && + f3_sfd__h565826 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h565824 == 8'd0) ? + ((f3_exp__h565825 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 = - (f3_exp__h565824 == 8'd255 && f3_sfd__h565825 != 23'd0) ? - _theResult___snd_fst_sfd__h566140 : - _theResult___fst_sfd__h604280 ; + (f3_exp__h565825 == 8'd255 && f3_sfd__h565826 != 23'd0) ? + _theResult___snd_fst_sfd__h566141 : + _theResult___fst_sfd__h604281 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 = - { (f3_exp__h565824 == 8'd255) ? + { (f3_exp__h565825 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h604276, + _theResult___fst_exp__h604277, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 } ; assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875 = IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864 ? @@ -20261,7 +20261,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 || - _theResult___fst_exp__h545767 == 11'd2047) ? + _theResult___fst_exp__h545768 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20269,12 +20269,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : + CASE_guard37807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 || - _theResult___fst_exp__h506914 == 11'd2047) ? + _theResult___fst_exp__h506915 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20282,12 +20282,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : + CASE_guard98954_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 || - _theResult___fst_exp__h585071 == 11'd2047) ? + _theResult___fst_exp__h585072 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20295,7 +20295,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : + CASE_guard77111_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368 = IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ? @@ -20779,48 +20779,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[2] : - _theResult___fst_exp__h526107 == 11'd2047 && - _theResult___fst_sfd__h526108 == 52'd0 ; + _theResult___fst_exp__h526108 == 11'd2047 && + _theResult___fst_sfd__h526109 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[2] : - _theResult___fst_exp__h564960 == 11'd2047 && - _theResult___fst_sfd__h564961 == 52'd0 ; + _theResult___fst_exp__h564961 == 11'd2047 && + _theResult___fst_sfd__h564962 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[2] : - _theResult___fst_exp__h604264 == 11'd2047 && - _theResult___fst_sfd__h604265 == 52'd0 ; + _theResult___fst_exp__h604265 == 11'd2047 && + _theResult___fst_sfd__h604266 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[1] : - _theResult___fst_exp__h525324 == 11'd0 && - guard__h517334 != 2'b0 ; + _theResult___fst_exp__h525325 == 11'd0 && + guard__h517335 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[1] : - _theResult___fst_exp__h564177 == 11'd0 && - guard__h556187 != 2'b0 ; + _theResult___fst_exp__h564178 == 11'd0 && + guard__h556188 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[1] : - _theResult___fst_exp__h603481 == 11'd0 && - guard__h595491 != 2'b0 ; + _theResult___fst_exp__h603482 == 11'd0 && + guard__h595492 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[0] : - _theResult___fst_exp__h525324 != 11'd2047 && - guard__h517334 != 2'b0 ; + _theResult___fst_exp__h525325 != 11'd2047 && + guard__h517335 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[0] : - _theResult___fst_exp__h564177 != 11'd2047 && - guard__h556187 != 2'b0 ; + _theResult___fst_exp__h564178 != 11'd2047 && + guard__h556188 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[0] : - _theResult___fst_exp__h603481 != 11'd2047 && - guard__h595491 != 2'b0 ; + _theResult___fst_exp__h603482 != 11'd2047 && + guard__h595492 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? @@ -20860,35 +20860,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h376612 == 8'd255) ? + ((_theResult___fst_exp__h376613 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180) : - ((_theResult___fst_exp__h385297 == 8'd255) ? + ((_theResult___fst_exp__h385298 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - ((_theResult___fst_exp__h376612 == 8'd255) ? + ((_theResult___fst_exp__h376613 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223) : - ((_theResult___fst_exp__h385297 == 8'd255) ? + ((_theResult___fst_exp__h385298 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[2] : - _theResult___fst_exp__h385845 == 8'd255 && - _theResult___fst_sfd__h385846 == 23'd0 ; + _theResult___fst_exp__h385846 == 8'd255 && + _theResult___fst_sfd__h385847 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[1] : - _theResult___fst_exp__h385297 == 8'd0 && - guard__h377220 != 2'b0 ; + _theResult___fst_exp__h385298 == 8'd0 && + guard__h377221 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[0] : - _theResult___fst_exp__h385297 != 8'd255 && - guard__h377220 != 2'b0 ; + _theResult___fst_exp__h385298 != 8'd255 && + guard__h377221 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? @@ -20898,35 +20898,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h422309 == 8'd255) ? + ((_theResult___fst_exp__h422310 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572) : - ((_theResult___fst_exp__h430994 == 8'd255) ? + ((_theResult___fst_exp__h430995 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - ((_theResult___fst_exp__h422309 == 8'd255) ? + ((_theResult___fst_exp__h422310 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615) : - ((_theResult___fst_exp__h430994 == 8'd255) ? + ((_theResult___fst_exp__h430995 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[2] : - _theResult___fst_exp__h431542 == 8'd255 && - _theResult___fst_sfd__h431543 == 23'd0 ; + _theResult___fst_exp__h431543 == 8'd255 && + _theResult___fst_sfd__h431544 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[1] : - _theResult___fst_exp__h430994 == 8'd0 && - guard__h422917 != 2'b0 ; + _theResult___fst_exp__h430995 == 8'd0 && + guard__h422918 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[0] : - _theResult___fst_exp__h430994 != 8'd255 && - guard__h422917 != 2'b0 ; + _theResult___fst_exp__h430995 != 8'd255 && + guard__h422918 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? @@ -20936,35 +20936,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h468004 == 8'd255) ? + ((_theResult___fst_exp__h468005 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964) : - ((_theResult___fst_exp__h476689 == 8'd255) ? + ((_theResult___fst_exp__h476690 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - ((_theResult___fst_exp__h468004 == 8'd255) ? + ((_theResult___fst_exp__h468005 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007) : - ((_theResult___fst_exp__h476689 == 8'd255) ? + ((_theResult___fst_exp__h476690 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[2] : - _theResult___fst_exp__h477237 == 8'd255 && - _theResult___fst_sfd__h477238 == 23'd0 ; + _theResult___fst_exp__h477238 == 8'd255 && + _theResult___fst_sfd__h477239 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[1] : - _theResult___fst_exp__h476689 == 8'd0 && - guard__h468612 != 2'b0 ; + _theResult___fst_exp__h476690 == 8'd0 && + guard__h468613 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[0] : - _theResult___fst_exp__h476689 != 8'd255 && - guard__h468612 != 2'b0 ; + _theResult___fst_exp__h476690 != 8'd255 && + guard__h468613 != 2'b0 ; assign IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 = checkForException___d13160[4] ? CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 : @@ -21622,8 +21622,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h653733 : - w__h653728 ; + result__h653734 : + w__h653729 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2112 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -21645,39 +21645,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h201749 : + n___1__h201750 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -21730,7 +21730,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h200346 : + x__h200347 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 ? 64'd0 : 64'd1) ; @@ -21742,7 +21742,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 = - _theResult_____2__h301171 == v__h300591 ; + _theResult_____2__h301172 == v__h300592 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21751,7 +21751,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 = - _theResult_____2__h309167 == v__h303936 ; + _theResult_____2__h309168 == v__h303937 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -21780,7 +21780,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h306801 } ; + x__h306802 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -21878,35 +21878,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h196841 : + n__h196842 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -21934,7 +21934,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 = - _theResult_____2__h315161 == v__h314450 ; + _theResult_____2__h315162 == v__h314451 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -21943,7 +21943,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 = - _theResult_____2__h323015 == v__h318326 ; + _theResult_____2__h323016 == v__h318327 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -22095,7 +22095,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 = - _theResult_____2__h336584 == v__h336152 ; + _theResult_____2__h336585 == v__h336153 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -22144,7 +22144,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) : IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 = - _theResult_____2__h333359 == v__h332927 ; + _theResult_____2__h333360 == v__h332928 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -22284,60 +22284,60 @@ module mkCore(CLK, mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd__h722002 : + y_avValue_snd_snd_snd_snd_snd__h722003 : 64'd0 ; assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 = - rob$deqPort_0_canDeq ? y_avValue_fst__h721562 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_fst__h721563 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h721996 : + y_avValue_snd_snd_snd_fst__h721997 : 2'd0 ; assign IF_rob_deqPort_1_canDeq__4990_THEN_IF_NOT_rob__ETC___d15197 = rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__4993_BIT_25_499_ETC___d15196 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin04537_BIT_33_THEN_2_ELSE_0__q57 = - sfdin__h404537[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin16485_BIT_4_THEN_2_ELSE_0__q131 = - sfdin__h516485[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin22303_BIT_33_THEN_2_ELSE_0__q67 = - sfdin__h422303[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin50232_BIT_33_THEN_2_ELSE_0__q92 = - sfdin__h450232[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin55338_BIT_4_THEN_2_ELSE_0__q171 = - sfdin__h555338[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin58840_BIT_33_THEN_2_ELSE_0__q22 = - sfdin__h358840[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin67998_BIT_33_THEN_2_ELSE_0__q102 = - sfdin__h467998[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin76606_BIT_33_THEN_2_ELSE_0__q32 = - sfdin__h376606[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin94642_BIT_4_THEN_2_ELSE_0__q148 = - sfdin__h594642[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd03427_BIT_4_THEN_2_ELSE_0__q151 = - _theResult___snd__h603427[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06865_BIT_4_THEN_2_ELSE_0__q127 = - _theResult___snd__h506865[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd13150_BIT_33_THEN_2_ELSE_0__q59 = - _theResult___snd__h413150[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd25270_BIT_4_THEN_2_ELSE_0__q134 = - _theResult___snd__h525270[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30940_BIT_33_THEN_2_ELSE_0__q72 = - _theResult___snd__h430940[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd45718_BIT_4_THEN_2_ELSE_0__q167 = - _theResult___snd__h545718[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58845_BIT_33_THEN_2_ELSE_0__q94 = - _theResult___snd__h458845[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd64123_BIT_4_THEN_2_ELSE_0__q174 = - _theResult___snd__h564123[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd67453_BIT_33_THEN_2_ELSE_0__q24 = - _theResult___snd__h367453[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76635_BIT_33_THEN_2_ELSE_0__q107 = - _theResult___snd__h476635[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd85022_BIT_4_THEN_2_ELSE_0__q144 = - _theResult___snd__h585022[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd85243_BIT_33_THEN_2_ELSE_0__q37 = - _theResult___snd__h385243[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin04538_BIT_33_THEN_2_ELSE_0__q57 = + sfdin__h404538[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin16486_BIT_4_THEN_2_ELSE_0__q131 = + sfdin__h516486[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin22304_BIT_33_THEN_2_ELSE_0__q67 = + sfdin__h422304[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin50233_BIT_33_THEN_2_ELSE_0__q92 = + sfdin__h450233[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin55339_BIT_4_THEN_2_ELSE_0__q171 = + sfdin__h555339[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin58841_BIT_33_THEN_2_ELSE_0__q22 = + sfdin__h358841[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin67999_BIT_33_THEN_2_ELSE_0__q102 = + sfdin__h467999[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin76607_BIT_33_THEN_2_ELSE_0__q32 = + sfdin__h376607[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin94643_BIT_4_THEN_2_ELSE_0__q148 = + sfdin__h594643[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd03428_BIT_4_THEN_2_ELSE_0__q151 = + _theResult___snd__h603428[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06866_BIT_4_THEN_2_ELSE_0__q127 = + _theResult___snd__h506866[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd13151_BIT_33_THEN_2_ELSE_0__q59 = + _theResult___snd__h413151[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd25271_BIT_4_THEN_2_ELSE_0__q134 = + _theResult___snd__h525271[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30941_BIT_33_THEN_2_ELSE_0__q72 = + _theResult___snd__h430941[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd45719_BIT_4_THEN_2_ELSE_0__q167 = + _theResult___snd__h545719[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58846_BIT_33_THEN_2_ELSE_0__q94 = + _theResult___snd__h458846[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd64124_BIT_4_THEN_2_ELSE_0__q174 = + _theResult___snd__h564124[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd67454_BIT_33_THEN_2_ELSE_0__q24 = + _theResult___snd__h367454[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76636_BIT_33_THEN_2_ELSE_0__q107 = + _theResult___snd__h476636[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd85023_BIT_4_THEN_2_ELSE_0__q144 = + _theResult___snd__h585023[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd85244_BIT_33_THEN_2_ELSE_0__q37 = + _theResult___snd__h385244[33] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? @@ -22417,133 +22417,133 @@ module mkCore(CLK, !checkForException___d13792[4] && NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13817 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__4986_4987_OR__ETC___d15202 = - (fflags__h722585 & csrf_fflags_reg) != fflags__h722585 || - !r__h619420 && + (fflags__h722586 & csrf_fflags_reg) != fflags__h722586 || + !r__h619421 && (IF_rob_deqPort_1_canDeq__4990_THEN_IF_NOT_rob__ETC___d15197 || - fflags__h722585 != 5'd0) ; + fflags__h722586 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 = - !f2_sfd__h526521[21] && !f2_sfd__h526521[20] && - !f2_sfd__h526521[19] && - !f2_sfd__h526521[18] && - !f2_sfd__h526521[17] && - !f2_sfd__h526521[16] && - !f2_sfd__h526521[15] && - !f2_sfd__h526521[14] && - !f2_sfd__h526521[13] && - !f2_sfd__h526521[12] && - !f2_sfd__h526521[11] && - !f2_sfd__h526521[10] && - !f2_sfd__h526521[9] && - !f2_sfd__h526521[8] && - !f2_sfd__h526521[7] && - !f2_sfd__h526521[6] && - !f2_sfd__h526521[5] && - !f2_sfd__h526521[4] && - !f2_sfd__h526521[3] && - !f2_sfd__h526521[2] && - !f2_sfd__h526521[1] && - !f2_sfd__h526521[0] ; + !f2_sfd__h526522[21] && !f2_sfd__h526522[20] && + !f2_sfd__h526522[19] && + !f2_sfd__h526522[18] && + !f2_sfd__h526522[17] && + !f2_sfd__h526522[16] && + !f2_sfd__h526522[15] && + !f2_sfd__h526522[14] && + !f2_sfd__h526522[13] && + !f2_sfd__h526522[12] && + !f2_sfd__h526522[11] && + !f2_sfd__h526522[10] && + !f2_sfd__h526522[9] && + !f2_sfd__h526522[8] && + !f2_sfd__h526522[7] && + !f2_sfd__h526522[6] && + !f2_sfd__h526522[5] && + !f2_sfd__h526522[4] && + !f2_sfd__h526522[3] && + !f2_sfd__h526522[2] && + !f2_sfd__h526522[1] && + !f2_sfd__h526522[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 == 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 != 23'd0) && + (f1_exp__h487527 != 8'd0 || f1_sfd__h487528 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526521 != 8'd255 || f2_sfd__h526522 == 23'd0) && + (f2_exp__h526521 != 8'd255 || f2_sfd__h526522 != 23'd0) && + (f2_exp__h526521 != 8'd0 || f2_sfd__h526522 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 == 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 != 23'd0) && + (f1_exp__h487527 != 8'd0 || f1_sfd__h487528 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526521 != 8'd255 || f2_sfd__h526522 == 23'd0) && + (f2_exp__h526521 != 8'd255 || f2_sfd__h526522 != 23'd0) && + (f2_exp__h526521 != 8'd0 || f2_sfd__h526522 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 == 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 != 23'd0) && + (f1_exp__h487527 != 8'd0 || f1_sfd__h487528 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526521 != 8'd255 || f2_sfd__h526522 == 23'd0) && + (f2_exp__h526521 != 8'd255 || f2_sfd__h526522 != 23'd0) && + (f2_exp__h526521 != 8'd0 || f2_sfd__h526522 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 == 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 != 23'd0) && + (f1_exp__h487527 != 8'd0 || f1_sfd__h487528 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526521 != 8'd255 || f2_sfd__h526522 == 23'd0) && + (f2_exp__h526521 != 8'd255 || f2_sfd__h526522 != 23'd0) && + (f2_exp__h526521 != 8'd0 || f2_sfd__h526522 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 = - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 == 23'd0) && - (f1_exp__h487526 != 8'd255 || f1_sfd__h487527 != 23'd0) && - (f1_exp__h487526 != 8'd0 || f1_sfd__h487527 != 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 == 23'd0) && + (f1_exp__h487527 != 8'd255 || f1_sfd__h487528 != 23'd0) && + (f1_exp__h487527 != 8'd0 || f1_sfd__h487528 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 | - ((f2_exp__h526520 != 8'd255 || f2_sfd__h526521 == 23'd0) && - (f2_exp__h526520 != 8'd255 || f2_sfd__h526521 != 23'd0) && - (f2_exp__h526520 != 8'd0 || f2_sfd__h526521 != 23'd0) && + ((f2_exp__h526521 != 8'd255 || f2_sfd__h526522 == 23'd0) && + (f2_exp__h526521 != 8'd255 || f2_sfd__h526522 != 23'd0) && + (f2_exp__h526521 != 8'd0 || f2_sfd__h526522 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 = - !f1_sfd__h487527[21] && !f1_sfd__h487527[20] && - !f1_sfd__h487527[19] && - !f1_sfd__h487527[18] && - !f1_sfd__h487527[17] && - !f1_sfd__h487527[16] && - !f1_sfd__h487527[15] && - !f1_sfd__h487527[14] && - !f1_sfd__h487527[13] && - !f1_sfd__h487527[12] && - !f1_sfd__h487527[11] && - !f1_sfd__h487527[10] && - !f1_sfd__h487527[9] && - !f1_sfd__h487527[8] && - !f1_sfd__h487527[7] && - !f1_sfd__h487527[6] && - !f1_sfd__h487527[5] && - !f1_sfd__h487527[4] && - !f1_sfd__h487527[3] && - !f1_sfd__h487527[2] && - !f1_sfd__h487527[1] && - !f1_sfd__h487527[0] ; + !f1_sfd__h487528[21] && !f1_sfd__h487528[20] && + !f1_sfd__h487528[19] && + !f1_sfd__h487528[18] && + !f1_sfd__h487528[17] && + !f1_sfd__h487528[16] && + !f1_sfd__h487528[15] && + !f1_sfd__h487528[14] && + !f1_sfd__h487528[13] && + !f1_sfd__h487528[12] && + !f1_sfd__h487528[11] && + !f1_sfd__h487528[10] && + !f1_sfd__h487528[9] && + !f1_sfd__h487528[8] && + !f1_sfd__h487528[7] && + !f1_sfd__h487528[6] && + !f1_sfd__h487528[5] && + !f1_sfd__h487528[4] && + !f1_sfd__h487528[3] && + !f1_sfd__h487528[2] && + !f1_sfd__h487528[1] && + !f1_sfd__h487528[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 = - !f3_sfd__h565825[21] && !f3_sfd__h565825[20] && - !f3_sfd__h565825[19] && - !f3_sfd__h565825[18] && - !f3_sfd__h565825[17] && - !f3_sfd__h565825[16] && - !f3_sfd__h565825[15] && - !f3_sfd__h565825[14] && - !f3_sfd__h565825[13] && - !f3_sfd__h565825[12] && - !f3_sfd__h565825[11] && - !f3_sfd__h565825[10] && - !f3_sfd__h565825[9] && - !f3_sfd__h565825[8] && - !f3_sfd__h565825[7] && - !f3_sfd__h565825[6] && - !f3_sfd__h565825[5] && - !f3_sfd__h565825[4] && - !f3_sfd__h565825[3] && - !f3_sfd__h565825[2] && - !f3_sfd__h565825[1] && - !f3_sfd__h565825[0] ; + !f3_sfd__h565826[21] && !f3_sfd__h565826[20] && + !f3_sfd__h565826[19] && + !f3_sfd__h565826[18] && + !f3_sfd__h565826[17] && + !f3_sfd__h565826[16] && + !f3_sfd__h565826[15] && + !f3_sfd__h565826[14] && + !f3_sfd__h565826[13] && + !f3_sfd__h565826[12] && + !f3_sfd__h565826[11] && + !f3_sfd__h565826[10] && + !f3_sfd__h565826[9] && + !f3_sfd__h565826[8] && + !f3_sfd__h565826[7] && + !f3_sfd__h565826[6] && + !f3_sfd__h565826[5] && + !f3_sfd__h565826[4] && + !f3_sfd__h565826[3] && + !f3_sfd__h565826[2] && + !f3_sfd__h565826[1] && + !f3_sfd__h565826[0] ; assign NOT_IF_rob_deqPort_0_deq_data__4451_BITS_97_TO_ETC___d14957 = - next_pc__h718598 != + next_pc__h718599 != rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954 ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13588 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13586 && @@ -23146,7 +23146,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 && !csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 && - csr_addr__h661835 != 12'h8FF) ; + csr_addr__h661836 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13526 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -23276,9 +23276,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h661836 == 5'd0 && - imm__h661837 == 32'd0 || - csr_addr__h661835[11:10] != 2'b11 ; + rs1__h661837 == 5'd0 && + imm__h661838 == 32'd0 || + csr_addr__h661836[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13533 = fetchStage$pipelines_0_first[199:195] != 5'd0 && fetchStage$pipelines_0_first[199:195] != 5'd21 && @@ -23343,7 +23343,7 @@ module mkCore(CLK, specTagManager$currentSpecBits } ; assign NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14192 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h670384 ; + fallthrough_pc__h670385 ; assign NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13581 = !fetchStage$pipelines_0_first[68] && !checkForException___d13160[4] && @@ -23425,7 +23425,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[173] ; assign NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14358 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h686130 ; + fallthrough_pc__h686131 ; assign NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14301 = !fetchStage$pipelines_1_first[68] && !checkForException___d13792[4] && @@ -23626,7 +23626,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031, - x__h296161 } ; + x__h296162 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15324 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254, @@ -23651,8 +23651,8 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13889 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 = - { {4{f2_exp26520_MINUS_127__q168[7]}}, - f2_exp26520_MINUS_127__q168 } ; + { {4{f2_exp26521_MINUS_127__q168[7]}}, + f2_exp26521_MINUS_127__q168 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 ^ 12'h800) <= @@ -23662,12 +23662,12 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187 = - b__h608520 * b__h608596 ; + b__h608521 * b__h608597 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200 = - b__h608520 * b__h608709 ; + b__h608521 * b__h608710 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 = - { {4{f1_exp87526_MINUS_127__q128[7]}}, - f1_exp87526_MINUS_127__q128 } ; + { {4{f1_exp87527_MINUS_127__q128[7]}}, + f1_exp87527_MINUS_127__q128 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 ^ 12'h800) <= @@ -23677,8 +23677,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 = - { {4{f3_exp65824_MINUS_127__q145[7]}}, - f3_exp65824_MINUS_127__q145 } ; + { {4{f3_exp65825_MINUS_127__q145[7]}}, + f3_exp65825_MINUS_127__q145 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ^ 12'h800) <= @@ -23763,15 +23763,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265 = { 3'd0, - _theResult___fst_exp__h358846 == 8'd0 && - (sfdin__h358840[56:34] == 23'd0 || guard__h350745 != 2'b0), + _theResult___fst_exp__h358847 == 8'd0 && + (sfdin__h358841[56:34] == 23'd0 || guard__h350746 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h359443 == 8'd255 && - _theResult___fst_sfd__h359444 == 23'd0, + _theResult___fst_exp__h359444 == 8'd255 && + _theResult___fst_sfd__h359445 == 23'd0, 1'd0, - _theResult___fst_exp__h358846 != 8'd255 && - guard__h350745 != 2'b0 } ; + _theResult___fst_exp__h358847 != 8'd255 && + guard__h350746 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ^ @@ -23779,15 +23779,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657 = { 3'd0, - _theResult___fst_exp__h404543 == 8'd0 && - (sfdin__h404537[56:34] == 23'd0 || guard__h396444 != 2'b0), + _theResult___fst_exp__h404544 == 8'd0 && + (sfdin__h404538[56:34] == 23'd0 || guard__h396445 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h405140 == 8'd255 && - _theResult___fst_sfd__h405141 == 23'd0, + _theResult___fst_exp__h405141 == 8'd255 && + _theResult___fst_sfd__h405142 == 23'd0, 1'd0, - _theResult___fst_exp__h404543 != 8'd255 && - guard__h396444 != 2'b0 } ; + _theResult___fst_exp__h404544 != 8'd255 && + guard__h396445 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ^ @@ -23795,15 +23795,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049 = { 3'd0, - _theResult___fst_exp__h450238 == 8'd0 && - (sfdin__h450232[56:34] == 23'd0 || guard__h442139 != 2'b0), + _theResult___fst_exp__h450239 == 8'd0 && + (sfdin__h450233[56:34] == 23'd0 || guard__h442140 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h450835 == 8'd255 && - _theResult___fst_sfd__h450836 == 23'd0, + _theResult___fst_exp__h450836 == 8'd255 && + _theResult___fst_sfd__h450837 == 23'd0, 1'd0, - _theResult___fst_exp__h450238 != 8'd255 && - guard__h442139 != 2'b0 } ; + _theResult___fst_exp__h450239 != 8'd255 && + guard__h442140 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ^ @@ -23811,37 +23811,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869 = { 3'd0, - _theResult___fst_exp__h516491 == 11'd0 && - (sfdin__h516485[56:5] == 52'd0 || guard__h508265 != 2'b0), + _theResult___fst_exp__h516492 == 11'd0 && + (sfdin__h516486[56:5] == 52'd0 || guard__h508266 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h517323 == 11'd2047 && - _theResult___fst_sfd__h517324 == 52'd0, + _theResult___fst_exp__h517324 == 11'd2047 && + _theResult___fst_sfd__h517325 == 52'd0, 1'd0, - _theResult___fst_exp__h516491 != 11'd2047 && - guard__h508265 != 2'b0 } ; + _theResult___fst_exp__h516492 != 11'd2047 && + guard__h508266 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910 = { 3'd0, - _theResult___fst_exp__h555344 == 11'd0 && - (sfdin__h555338[56:5] == 52'd0 || guard__h547118 != 2'b0), + _theResult___fst_exp__h555345 == 11'd0 && + (sfdin__h555339[56:5] == 52'd0 || guard__h547119 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h556176 == 11'd2047 && - _theResult___fst_sfd__h556177 == 52'd0, + _theResult___fst_exp__h556177 == 11'd2047 && + _theResult___fst_sfd__h556178 == 52'd0, 1'd0, - _theResult___fst_exp__h555344 != 11'd2047 && - guard__h547118 != 2'b0 } ; + _theResult___fst_exp__h555345 != 11'd2047 && + guard__h547119 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954 = { 3'd0, - _theResult___fst_exp__h594648 == 11'd0 && - (sfdin__h594642[56:5] == 52'd0 || guard__h586422 != 2'b0), + _theResult___fst_exp__h594649 == 11'd0 && + (sfdin__h594643[56:5] == 52'd0 || guard__h586423 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h595480 == 11'd2047 && - _theResult___fst_sfd__h595481 == 52'd0, + _theResult___fst_exp__h595481 == 11'd2047 && + _theResult___fst_sfd__h595482 == 52'd0, 1'd0, - _theResult___fst_exp__h594648 != 11'd2047 && - guard__h586422 != 2'b0 } ; + _theResult___fst_exp__h594649 != 11'd2047 && + guard__h586423 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ^ @@ -23859,15 +23859,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294 = { 3'd0, - _theResult___fst_exp__h376612 == 8'd0 && - (sfdin__h376606[56:34] == 23'd0 || guard__h368384 != 2'b0), + _theResult___fst_exp__h376613 == 8'd0 && + (sfdin__h376607[56:34] == 23'd0 || guard__h368385 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h377209 == 8'd255 && - _theResult___fst_sfd__h377210 == 23'd0, + _theResult___fst_exp__h377210 == 8'd255 && + _theResult___fst_sfd__h377211 == 23'd0, 1'd0, - _theResult___fst_exp__h376612 != 8'd255 && - guard__h368384 != 2'b0 } ; + _theResult___fst_exp__h376613 != 8'd255 && + guard__h368385 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ^ @@ -23875,15 +23875,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686 = { 3'd0, - _theResult___fst_exp__h422309 == 8'd0 && - (sfdin__h422303[56:34] == 23'd0 || guard__h414081 != 2'b0), + _theResult___fst_exp__h422310 == 8'd0 && + (sfdin__h422304[56:34] == 23'd0 || guard__h414082 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h422906 == 8'd255 && - _theResult___fst_sfd__h422907 == 23'd0, + _theResult___fst_exp__h422907 == 8'd255 && + _theResult___fst_sfd__h422908 == 23'd0, 1'd0, - _theResult___fst_exp__h422309 != 8'd255 && - guard__h414081 != 2'b0 } ; + _theResult___fst_exp__h422310 != 8'd255 && + guard__h414082 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ^ @@ -23891,15 +23891,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078 = { 3'd0, - _theResult___fst_exp__h468004 == 8'd0 && - (sfdin__h467998[56:34] == 23'd0 || guard__h459776 != 2'b0), + _theResult___fst_exp__h468005 == 8'd0 && + (sfdin__h467999[56:34] == 23'd0 || guard__h459777 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h468601 == 8'd255 && - _theResult___fst_sfd__h468602 == 23'd0, + _theResult___fst_exp__h468602 == 8'd255 && + _theResult___fst_sfd__h468603 == 23'd0, 1'd0, - _theResult___fst_exp__h468004 != 8'd255 && - guard__h459776 != 2'b0 } ; + _theResult___fst_exp__h468005 != 8'd255 && + guard__h459777 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ^ @@ -23913,37 +23913,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852 = { 3'd0, - _theResult___fst_exp__h506914 == 11'd0 && - guard__h498953 != 2'b0, + _theResult___fst_exp__h506915 == 11'd0 && + guard__h498954 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h507672 == 11'd2047 && - _theResult___fst_sfd__h507673 == 52'd0, + _theResult___fst_exp__h507673 == 11'd2047 && + _theResult___fst_sfd__h507674 == 52'd0, 1'd0, - _theResult___fst_exp__h506914 != 11'd2047 && - guard__h498953 != 2'b0 } ; + _theResult___fst_exp__h506915 != 11'd2047 && + guard__h498954 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893 = { 3'd0, - _theResult___fst_exp__h545767 == 11'd0 && - guard__h537806 != 2'b0, + _theResult___fst_exp__h545768 == 11'd0 && + guard__h537807 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h546525 == 11'd2047 && - _theResult___fst_sfd__h546526 == 52'd0, + _theResult___fst_exp__h546526 == 11'd2047 && + _theResult___fst_sfd__h546527 == 52'd0, 1'd0, - _theResult___fst_exp__h545767 != 11'd2047 && - guard__h537806 != 2'b0 } ; + _theResult___fst_exp__h545768 != 11'd2047 && + guard__h537807 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937 = { 3'd0, - _theResult___fst_exp__h585071 == 11'd0 && - guard__h577110 != 2'b0, + _theResult___fst_exp__h585072 == 11'd0 && + guard__h577111 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h585829 == 11'd2047 && - _theResult___fst_sfd__h585830 == 52'd0, + _theResult___fst_exp__h585830 == 11'd2047 && + _theResult___fst_sfd__h585831 == 52'd0, 1'd0, - _theResult___fst_exp__h585071 != 11'd2047 && - guard__h577110 != 2'b0 } ; + _theResult___fst_exp__h585072 != 11'd2047 && + guard__h577111 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ^ @@ -23979,15 +23979,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277 = { 3'd0, - _theResult___fst_exp__h367502 == 8'd0 && - guard__h359454 != 2'b0, + _theResult___fst_exp__h367503 == 8'd0 && + guard__h359455 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h368025 == 8'd255 && - _theResult___fst_sfd__h368026 == 23'd0, + _theResult___fst_exp__h368026 == 8'd255 && + _theResult___fst_sfd__h368027 == 23'd0, 1'd0, - _theResult___fst_exp__h367502 != 8'd255 && - guard__h359454 != 2'b0 } ; + _theResult___fst_exp__h367503 != 8'd255 && + guard__h359455 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ^ @@ -24001,15 +24001,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669 = { 3'd0, - _theResult___fst_exp__h413199 == 8'd0 && - guard__h405151 != 2'b0, + _theResult___fst_exp__h413200 == 8'd0 && + guard__h405152 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h413722 == 8'd255 && - _theResult___fst_sfd__h413723 == 23'd0, + _theResult___fst_exp__h413723 == 8'd255 && + _theResult___fst_sfd__h413724 == 23'd0, 1'd0, - _theResult___fst_exp__h413199 != 8'd255 && - guard__h405151 != 2'b0 } ; + _theResult___fst_exp__h413200 != 8'd255 && + guard__h405152 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ^ @@ -24023,21 +24023,21 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061 = { 3'd0, - _theResult___fst_exp__h458894 == 8'd0 && - guard__h450846 != 2'b0, + _theResult___fst_exp__h458895 == 8'd0 && + guard__h450847 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h459417 == 8'd255 && - _theResult___fst_sfd__h459418 == 23'd0, + _theResult___fst_exp__h459418 == 8'd255 && + _theResult___fst_sfd__h459419 == 23'd0, 1'd0, - _theResult___fst_exp__h458894 != 8'd255 && - guard__h450846 != 2'b0 } ; + _theResult___fst_exp__h458895 != 8'd255 && + guard__h450847 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193 = - b__h608697 * b__h608709 ; + b__h608698 * b__h608710 ; assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14009 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k74092_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; + CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14094 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && @@ -24049,33 +24049,33 @@ module mkCore(CLK, !regRenamingTable$rename_1_canRename || fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13889 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249 = - sfd__h526882 >> + sfd__h526883 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764 = - sfd__h487888 >> + sfd__h487889 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479 = - sfd__h566186 >> + sfd__h566187 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654 = - sfd__h343130 >> + sfd__h343131 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046 = - sfd__h388832 >> + sfd__h388833 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438 = - sfd__h434527 >> + sfd__h434528 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14629 = - medeleg_csr__read__h617227[i__h707773] ; + medeleg_csr__read__h617228[i__h707774] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14610 = - mideleg_csr__read__h617322[i__h707933] ; + mideleg_csr__read__h617323[i__h707934] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 = 12'd3074 - { 6'd0, @@ -24481,51 +24481,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120 = 12'd3970 - { 7'd0, - f2_sfd__h526521[22] ? + f2_sfd__h526522[22] ? 5'd0 : - (f2_sfd__h526521[21] ? + (f2_sfd__h526522[21] ? 5'd1 : - (f2_sfd__h526521[20] ? + (f2_sfd__h526522[20] ? 5'd2 : - (f2_sfd__h526521[19] ? + (f2_sfd__h526522[19] ? 5'd3 : - (f2_sfd__h526521[18] ? + (f2_sfd__h526522[18] ? 5'd4 : - (f2_sfd__h526521[17] ? + (f2_sfd__h526522[17] ? 5'd5 : - (f2_sfd__h526521[16] ? + (f2_sfd__h526522[16] ? 5'd6 : - (f2_sfd__h526521[15] ? + (f2_sfd__h526522[15] ? 5'd7 : - (f2_sfd__h526521[14] ? + (f2_sfd__h526522[14] ? 5'd8 : - (f2_sfd__h526521[13] ? + (f2_sfd__h526522[13] ? 5'd9 : - (f2_sfd__h526521[12] ? + (f2_sfd__h526522[12] ? 5'd10 : - (f2_sfd__h526521[11] ? + (f2_sfd__h526522[11] ? 5'd11 : - (f2_sfd__h526521[10] ? + (f2_sfd__h526522[10] ? 5'd12 : - (f2_sfd__h526521[9] ? + (f2_sfd__h526522[9] ? 5'd13 : - (f2_sfd__h526521[8] ? + (f2_sfd__h526522[8] ? 5'd14 : - (f2_sfd__h526521[7] ? + (f2_sfd__h526522[7] ? 5'd15 : - (f2_sfd__h526521[6] ? + (f2_sfd__h526522[6] ? 5'd16 : - (f2_sfd__h526521[5] ? + (f2_sfd__h526522[5] ? 5'd17 : - (f2_sfd__h526521[4] ? + (f2_sfd__h526522[4] ? 5'd18 : - (f2_sfd__h526521[3] ? + (f2_sfd__h526522[3] ? 5'd19 : - (f2_sfd__h526521[2] ? + (f2_sfd__h526522[2] ? 5'd20 : - (f2_sfd__h526521[1] ? + (f2_sfd__h526522[1] ? 5'd21 : - (f2_sfd__h526521[0] ? + (f2_sfd__h526522[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 = @@ -24539,51 +24539,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620 = 12'd3970 - { 7'd0, - f1_sfd__h487527[22] ? + f1_sfd__h487528[22] ? 5'd0 : - (f1_sfd__h487527[21] ? + (f1_sfd__h487528[21] ? 5'd1 : - (f1_sfd__h487527[20] ? + (f1_sfd__h487528[20] ? 5'd2 : - (f1_sfd__h487527[19] ? + (f1_sfd__h487528[19] ? 5'd3 : - (f1_sfd__h487527[18] ? + (f1_sfd__h487528[18] ? 5'd4 : - (f1_sfd__h487527[17] ? + (f1_sfd__h487528[17] ? 5'd5 : - (f1_sfd__h487527[16] ? + (f1_sfd__h487528[16] ? 5'd6 : - (f1_sfd__h487527[15] ? + (f1_sfd__h487528[15] ? 5'd7 : - (f1_sfd__h487527[14] ? + (f1_sfd__h487528[14] ? 5'd8 : - (f1_sfd__h487527[13] ? + (f1_sfd__h487528[13] ? 5'd9 : - (f1_sfd__h487527[12] ? + (f1_sfd__h487528[12] ? 5'd10 : - (f1_sfd__h487527[11] ? + (f1_sfd__h487528[11] ? 5'd11 : - (f1_sfd__h487527[10] ? + (f1_sfd__h487528[10] ? 5'd12 : - (f1_sfd__h487527[9] ? + (f1_sfd__h487528[9] ? 5'd13 : - (f1_sfd__h487527[8] ? + (f1_sfd__h487528[8] ? 5'd14 : - (f1_sfd__h487527[7] ? + (f1_sfd__h487528[7] ? 5'd15 : - (f1_sfd__h487527[6] ? + (f1_sfd__h487528[6] ? 5'd16 : - (f1_sfd__h487527[5] ? + (f1_sfd__h487528[5] ? 5'd17 : - (f1_sfd__h487527[4] ? + (f1_sfd__h487528[4] ? 5'd18 : - (f1_sfd__h487527[3] ? + (f1_sfd__h487528[3] ? 5'd19 : - (f1_sfd__h487527[2] ? + (f1_sfd__h487528[2] ? 5'd20 : - (f1_sfd__h487527[1] ? + (f1_sfd__h487528[1] ? 5'd21 : - (f1_sfd__h487527[0] ? + (f1_sfd__h487528[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 = @@ -24597,51 +24597,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350 = 12'd3970 - { 7'd0, - f3_sfd__h565825[22] ? + f3_sfd__h565826[22] ? 5'd0 : - (f3_sfd__h565825[21] ? + (f3_sfd__h565826[21] ? 5'd1 : - (f3_sfd__h565825[20] ? + (f3_sfd__h565826[20] ? 5'd2 : - (f3_sfd__h565825[19] ? + (f3_sfd__h565826[19] ? 5'd3 : - (f3_sfd__h565825[18] ? + (f3_sfd__h565826[18] ? 5'd4 : - (f3_sfd__h565825[17] ? + (f3_sfd__h565826[17] ? 5'd5 : - (f3_sfd__h565825[16] ? + (f3_sfd__h565826[16] ? 5'd6 : - (f3_sfd__h565825[15] ? + (f3_sfd__h565826[15] ? 5'd7 : - (f3_sfd__h565825[14] ? + (f3_sfd__h565826[14] ? 5'd8 : - (f3_sfd__h565825[13] ? + (f3_sfd__h565826[13] ? 5'd9 : - (f3_sfd__h565825[12] ? + (f3_sfd__h565826[12] ? 5'd10 : - (f3_sfd__h565825[11] ? + (f3_sfd__h565826[11] ? 5'd11 : - (f3_sfd__h565825[10] ? + (f3_sfd__h565826[10] ? 5'd12 : - (f3_sfd__h565825[9] ? + (f3_sfd__h565826[9] ? 5'd13 : - (f3_sfd__h565825[8] ? + (f3_sfd__h565826[8] ? 5'd14 : - (f3_sfd__h565825[7] ? + (f3_sfd__h565826[7] ? 5'd15 : - (f3_sfd__h565825[6] ? + (f3_sfd__h565826[6] ? 5'd16 : - (f3_sfd__h565825[5] ? + (f3_sfd__h565826[5] ? 5'd17 : - (f3_sfd__h565825[4] ? + (f3_sfd__h565826[4] ? 5'd18 : - (f3_sfd__h565825[3] ? + (f3_sfd__h565826[3] ? 5'd19 : - (f3_sfd__h565825[2] ? + (f3_sfd__h565826[2] ? 5'd20 : - (f3_sfd__h565825[1] ? + (f3_sfd__h565826[1] ? 5'd21 : - (f3_sfd__h565825[0] ? + (f3_sfd__h565826[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 = @@ -24670,7 +24670,7 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14371 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo18 = - k__h674092 == 1'd0 && + k__h674093 == 1'd0 && fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14171 || fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14290 == 1'd0 && @@ -24777,1421 +24777,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h301171 = + assign _theResult_____2__h301172 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142) ? - next_deqP___1__h301450 : + next_deqP___1__h301451 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h309167 = + assign _theResult_____2__h309168 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249) ? - next_deqP___1__h309446 : + next_deqP___1__h309447 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h315161 = + assign _theResult_____2__h315162 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420) ? - next_deqP___1__h315727 : + next_deqP___1__h315728 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h323015 = + assign _theResult_____2__h323016 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516) ? - next_deqP___1__h323581 : + next_deqP___1__h323582 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h333359 = + assign _theResult_____2__h333360 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745) ? - next_deqP___1__h333638 : + next_deqP___1__h333639 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h336584 = + assign _theResult_____2__h336585 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839) ? - next_deqP___1__h336863 : + next_deqP___1__h336864 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h350735 = - (value__h351357 == 54'd0) ? sfd__h343130 : 57'd1 ; - assign _theResult____h368374 = + assign _theResult____h350736 = + (value__h351358 == 54'd0) ? sfd__h343131 : 57'd1 ; + assign _theResult____h368375 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ^ 12'h800) < 12'd2105) ? - result__h368987 : - _theResult____h350735 ; - assign _theResult____h396434 = - (value__h397054 == 54'd0) ? sfd__h388832 : 57'd1 ; - assign _theResult____h414071 = + result__h368988 : + _theResult____h350736 ; + assign _theResult____h396435 = + (value__h397055 == 54'd0) ? sfd__h388833 : 57'd1 ; + assign _theResult____h414072 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ^ 12'h800) < 12'd2105) ? - result__h414684 : - _theResult____h396434 ; - assign _theResult____h442129 = - (value__h442749 == 54'd0) ? sfd__h434527 : 57'd1 ; - assign _theResult____h459766 = + result__h414685 : + _theResult____h396435 ; + assign _theResult____h442130 = + (value__h442750 == 54'd0) ? sfd__h434528 : 57'd1 ; + assign _theResult____h459767 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ^ 12'h800) < 12'd2105) ? - result__h460379 : - _theResult____h442129 ; - assign _theResult____h508255 = + result__h460380 : + _theResult____h442130 ; + assign _theResult____h508256 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ^ 12'h800) < 12'd2105) ? - result__h508868 : - ((value__h492471 == 25'd0) ? sfd__h487888 : 57'd1) ; - assign _theResult____h547108 = + result__h508869 : + ((value__h492472 == 25'd0) ? sfd__h487889 : 57'd1) ; + assign _theResult____h547109 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ^ 12'h800) < 12'd2105) ? - result__h547721 : - ((value__h531324 == 25'd0) ? sfd__h526882 : 57'd1) ; - assign _theResult____h586412 = + result__h547722 : + ((value__h531325 == 25'd0) ? sfd__h526883 : 57'd1) ; + assign _theResult____h586413 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ^ 12'h800) < 12'd2105) ? - result__h587025 : - ((value__h570628 == 25'd0) ? sfd__h566186 : 57'd1) ; - assign _theResult____h658026 = + result__h587026 : + ((value__h570629 == 25'd0) ? sfd__h566187 : 57'd1) ; + assign _theResult____h658027 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h658439 : + enabled_ints___1__h658440 : 12'd0 ; - assign _theResult___exp__h359362 = - sfd__h358938[24] ? - ((_theResult___fst_exp__h358846 == 8'd254) ? + assign _theResult___exp__h359363 = + sfd__h358939[24] ? + ((_theResult___fst_exp__h358847 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385879) : - ((_theResult___fst_exp__h358846 == 8'd0 && - sfd__h358938[24:23] == 2'b01) ? + din_inc___2_exp__h385880) : + ((_theResult___fst_exp__h358847 == 8'd0 && + sfd__h358939[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h358846) ; - assign _theResult___exp__h367944 = - sfd__h367520[24] ? - ((_theResult___fst_exp__h367502 == 8'd254) ? + _theResult___fst_exp__h358847) ; + assign _theResult___exp__h367945 = + sfd__h367521[24] ? + ((_theResult___fst_exp__h367503 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385903) : - ((_theResult___fst_exp__h367502 == 8'd0 && - sfd__h367520[24:23] == 2'b01) ? + din_inc___2_exp__h385904) : + ((_theResult___fst_exp__h367503 == 8'd0 && + sfd__h367521[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h367502) ; - assign _theResult___exp__h377128 = - sfd__h376704[24] ? - ((_theResult___fst_exp__h376612 == 8'd254) ? + _theResult___fst_exp__h367503) ; + assign _theResult___exp__h377129 = + sfd__h376705[24] ? + ((_theResult___fst_exp__h376613 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385933) : - ((_theResult___fst_exp__h376612 == 8'd0 && - sfd__h376704[24:23] == 2'b01) ? + din_inc___2_exp__h385934) : + ((_theResult___fst_exp__h376613 == 8'd0 && + sfd__h376705[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h376612) ; - assign _theResult___exp__h385764 = - sfd__h385316[24] ? - ((_theResult___fst_exp__h385297 == 8'd254) ? + _theResult___fst_exp__h376613) ; + assign _theResult___exp__h385765 = + sfd__h385317[24] ? + ((_theResult___fst_exp__h385298 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385957) : - ((_theResult___fst_exp__h385297 == 8'd0 && - sfd__h385316[24:23] == 2'b01) ? + din_inc___2_exp__h385958) : + ((_theResult___fst_exp__h385298 == 8'd0 && + sfd__h385317[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h385297) ; - assign _theResult___exp__h385866 = + _theResult___fst_exp__h385298) ; + assign _theResult___exp__h385867 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385857 ; - assign _theResult___exp__h405059 = - sfd__h404635[24] ? - ((_theResult___fst_exp__h404543 == 8'd254) ? + _theResult___fst_exp__h385858 ; + assign _theResult___exp__h405060 = + sfd__h404636[24] ? + ((_theResult___fst_exp__h404544 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431576) : - ((_theResult___fst_exp__h404543 == 8'd0 && - sfd__h404635[24:23] == 2'b01) ? + din_inc___2_exp__h431577) : + ((_theResult___fst_exp__h404544 == 8'd0 && + sfd__h404636[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h404543) ; - assign _theResult___exp__h413641 = - sfd__h413217[24] ? - ((_theResult___fst_exp__h413199 == 8'd254) ? + _theResult___fst_exp__h404544) ; + assign _theResult___exp__h413642 = + sfd__h413218[24] ? + ((_theResult___fst_exp__h413200 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431600) : - ((_theResult___fst_exp__h413199 == 8'd0 && - sfd__h413217[24:23] == 2'b01) ? + din_inc___2_exp__h431601) : + ((_theResult___fst_exp__h413200 == 8'd0 && + sfd__h413218[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h413199) ; - assign _theResult___exp__h422825 = - sfd__h422401[24] ? - ((_theResult___fst_exp__h422309 == 8'd254) ? + _theResult___fst_exp__h413200) ; + assign _theResult___exp__h422826 = + sfd__h422402[24] ? + ((_theResult___fst_exp__h422310 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431630) : - ((_theResult___fst_exp__h422309 == 8'd0 && - sfd__h422401[24:23] == 2'b01) ? + din_inc___2_exp__h431631) : + ((_theResult___fst_exp__h422310 == 8'd0 && + sfd__h422402[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h422309) ; - assign _theResult___exp__h431461 = - sfd__h431013[24] ? - ((_theResult___fst_exp__h430994 == 8'd254) ? + _theResult___fst_exp__h422310) ; + assign _theResult___exp__h431462 = + sfd__h431014[24] ? + ((_theResult___fst_exp__h430995 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431654) : - ((_theResult___fst_exp__h430994 == 8'd0 && - sfd__h431013[24:23] == 2'b01) ? + din_inc___2_exp__h431655) : + ((_theResult___fst_exp__h430995 == 8'd0 && + sfd__h431014[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h430994) ; - assign _theResult___exp__h431563 = + _theResult___fst_exp__h430995) ; + assign _theResult___exp__h431564 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431554 ; - assign _theResult___exp__h450754 = - sfd__h450330[24] ? - ((_theResult___fst_exp__h450238 == 8'd254) ? + _theResult___fst_exp__h431555 ; + assign _theResult___exp__h450755 = + sfd__h450331[24] ? + ((_theResult___fst_exp__h450239 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477271) : - ((_theResult___fst_exp__h450238 == 8'd0 && - sfd__h450330[24:23] == 2'b01) ? + din_inc___2_exp__h477272) : + ((_theResult___fst_exp__h450239 == 8'd0 && + sfd__h450331[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h450238) ; - assign _theResult___exp__h459336 = - sfd__h458912[24] ? - ((_theResult___fst_exp__h458894 == 8'd254) ? + _theResult___fst_exp__h450239) ; + assign _theResult___exp__h459337 = + sfd__h458913[24] ? + ((_theResult___fst_exp__h458895 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477295) : - ((_theResult___fst_exp__h458894 == 8'd0 && - sfd__h458912[24:23] == 2'b01) ? + din_inc___2_exp__h477296) : + ((_theResult___fst_exp__h458895 == 8'd0 && + sfd__h458913[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h458894) ; - assign _theResult___exp__h468520 = - sfd__h468096[24] ? - ((_theResult___fst_exp__h468004 == 8'd254) ? + _theResult___fst_exp__h458895) ; + assign _theResult___exp__h468521 = + sfd__h468097[24] ? + ((_theResult___fst_exp__h468005 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477325) : - ((_theResult___fst_exp__h468004 == 8'd0 && - sfd__h468096[24:23] == 2'b01) ? + din_inc___2_exp__h477326) : + ((_theResult___fst_exp__h468005 == 8'd0 && + sfd__h468097[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h468004) ; - assign _theResult___exp__h477156 = - sfd__h476708[24] ? - ((_theResult___fst_exp__h476689 == 8'd254) ? + _theResult___fst_exp__h468005) ; + assign _theResult___exp__h477157 = + sfd__h476709[24] ? + ((_theResult___fst_exp__h476690 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477349) : - ((_theResult___fst_exp__h476689 == 8'd0 && - sfd__h476708[24:23] == 2'b01) ? + din_inc___2_exp__h477350) : + ((_theResult___fst_exp__h476690 == 8'd0 && + sfd__h476709[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h476689) ; - assign _theResult___exp__h477258 = + _theResult___fst_exp__h476690) ; + assign _theResult___exp__h477259 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477249 ; - assign _theResult___exp__h507569 = - sfd__h506932[53] ? - ((_theResult___fst_exp__h506914 == 11'd2046) ? + _theResult___fst_exp__h477250 ; + assign _theResult___exp__h507570 = + sfd__h506933[53] ? + ((_theResult___fst_exp__h506915 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h526164) : - ((_theResult___fst_exp__h506914 == 11'd0 && - sfd__h506932[53:52] == 2'b01) ? + din_inc___2_exp__h526165) : + ((_theResult___fst_exp__h506915 == 11'd0 && + sfd__h506933[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h506914) ; - assign _theResult___exp__h517220 = - sfd__h516583[53] ? - ((_theResult___fst_exp__h516491 == 11'd2046) ? + _theResult___fst_exp__h506915) ; + assign _theResult___exp__h517221 = + sfd__h516584[53] ? + ((_theResult___fst_exp__h516492 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h526199) : - ((_theResult___fst_exp__h516491 == 11'd0 && - sfd__h516583[53:52] == 2'b01) ? + din_inc___2_exp__h526200) : + ((_theResult___fst_exp__h516492 == 11'd0 && + sfd__h516584[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h516491) ; - assign _theResult___exp__h526004 = - sfd__h525343[53] ? - ((_theResult___fst_exp__h525324 == 11'd2046) ? + _theResult___fst_exp__h516492) ; + assign _theResult___exp__h526005 = + sfd__h525344[53] ? + ((_theResult___fst_exp__h525325 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h526225) : - ((_theResult___fst_exp__h525324 == 11'd0 && - sfd__h525343[53:52] == 2'b01) ? + din_inc___2_exp__h526226) : + ((_theResult___fst_exp__h525325 == 11'd0 && + sfd__h525344[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h525324) ; - assign _theResult___exp__h546422 = - sfd__h545785[53] ? - ((_theResult___fst_exp__h545767 == 11'd2046) ? + _theResult___fst_exp__h525325) ; + assign _theResult___exp__h546423 = + sfd__h545786[53] ? + ((_theResult___fst_exp__h545768 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h565017) : - ((_theResult___fst_exp__h545767 == 11'd0 && - sfd__h545785[53:52] == 2'b01) ? + din_inc___2_exp__h565018) : + ((_theResult___fst_exp__h545768 == 11'd0 && + sfd__h545786[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h545767) ; - assign _theResult___exp__h556073 = - sfd__h555436[53] ? - ((_theResult___fst_exp__h555344 == 11'd2046) ? + _theResult___fst_exp__h545768) ; + assign _theResult___exp__h556074 = + sfd__h555437[53] ? + ((_theResult___fst_exp__h555345 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h565052) : - ((_theResult___fst_exp__h555344 == 11'd0 && - sfd__h555436[53:52] == 2'b01) ? + din_inc___2_exp__h565053) : + ((_theResult___fst_exp__h555345 == 11'd0 && + sfd__h555437[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h555344) ; - assign _theResult___exp__h564857 = - sfd__h564196[53] ? - ((_theResult___fst_exp__h564177 == 11'd2046) ? + _theResult___fst_exp__h555345) ; + assign _theResult___exp__h564858 = + sfd__h564197[53] ? + ((_theResult___fst_exp__h564178 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h565078) : - ((_theResult___fst_exp__h564177 == 11'd0 && - sfd__h564196[53:52] == 2'b01) ? + din_inc___2_exp__h565079) : + ((_theResult___fst_exp__h564178 == 11'd0 && + sfd__h564197[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h564177) ; - assign _theResult___exp__h585726 = - sfd__h585089[53] ? - ((_theResult___fst_exp__h585071 == 11'd2046) ? + _theResult___fst_exp__h564178) ; + assign _theResult___exp__h585727 = + sfd__h585090[53] ? + ((_theResult___fst_exp__h585072 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h604321) : - ((_theResult___fst_exp__h585071 == 11'd0 && - sfd__h585089[53:52] == 2'b01) ? + din_inc___2_exp__h604322) : + ((_theResult___fst_exp__h585072 == 11'd0 && + sfd__h585090[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h585071) ; - assign _theResult___exp__h595377 = - sfd__h594740[53] ? - ((_theResult___fst_exp__h594648 == 11'd2046) ? + _theResult___fst_exp__h585072) ; + assign _theResult___exp__h595378 = + sfd__h594741[53] ? + ((_theResult___fst_exp__h594649 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h604356) : - ((_theResult___fst_exp__h594648 == 11'd0 && - sfd__h594740[53:52] == 2'b01) ? + din_inc___2_exp__h604357) : + ((_theResult___fst_exp__h594649 == 11'd0 && + sfd__h594741[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h594648) ; - assign _theResult___exp__h604161 = - sfd__h603500[53] ? - ((_theResult___fst_exp__h603481 == 11'd2046) ? + _theResult___fst_exp__h594649) ; + assign _theResult___exp__h604162 = + sfd__h603501[53] ? + ((_theResult___fst_exp__h603482 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h604382) : - ((_theResult___fst_exp__h603481 == 11'd0 && - sfd__h603500[53:52] == 2'b01) ? + din_inc___2_exp__h604383) : + ((_theResult___fst_exp__h603482 == 11'd0 && + sfd__h603501[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h603481) ; - assign _theResult___fst__h608920 = - a__h608372[63] ? a___1__h608925 : a__h608372 ; - assign _theResult___fst_exp__h358846 = - _theResult____h350735[56] ? + _theResult___fst_exp__h603482) ; + assign _theResult___fst__h608921 = + a__h608373[63] ? a___1__h608926 : a__h608373 ; + assign _theResult___fst_exp__h358847 = + _theResult____h350736[56] ? 8'd2 : - _theResult___fst_exp__h358920 ; - assign _theResult___fst_exp__h358911 = + _theResult___fst_exp__h358921 ; + assign _theResult___fst_exp__h358912 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 } ; - assign _theResult___fst_exp__h358917 = - (!_theResult____h350735[56] && !_theResult____h350735[55] && - !_theResult____h350735[54] && - !_theResult____h350735[53] && - !_theResult____h350735[52] && - !_theResult____h350735[51] && - !_theResult____h350735[50] && - !_theResult____h350735[49] && - !_theResult____h350735[48] && - !_theResult____h350735[47] && - !_theResult____h350735[46] && - !_theResult____h350735[45] && - !_theResult____h350735[44] && - !_theResult____h350735[43] && - !_theResult____h350735[42] && - !_theResult____h350735[41] && - !_theResult____h350735[40] && - !_theResult____h350735[39] && - !_theResult____h350735[38] && - !_theResult____h350735[37] && - !_theResult____h350735[36] && - !_theResult____h350735[35] && - !_theResult____h350735[34] && - !_theResult____h350735[33] && - !_theResult____h350735[32] && - !_theResult____h350735[31] && - !_theResult____h350735[30] && - !_theResult____h350735[29] && - !_theResult____h350735[28] && - !_theResult____h350735[27] && - !_theResult____h350735[26] && - !_theResult____h350735[25] && - !_theResult____h350735[24] && - !_theResult____h350735[23] && - !_theResult____h350735[22] && - !_theResult____h350735[21] && - !_theResult____h350735[20] && - !_theResult____h350735[19] && - !_theResult____h350735[18] && - !_theResult____h350735[17] && - !_theResult____h350735[16] && - !_theResult____h350735[15] && - !_theResult____h350735[14] && - !_theResult____h350735[13] && - !_theResult____h350735[12] && - !_theResult____h350735[11] && - !_theResult____h350735[10] && - !_theResult____h350735[9] && - !_theResult____h350735[8] && - !_theResult____h350735[7] && - !_theResult____h350735[6] && - !_theResult____h350735[5] && - !_theResult____h350735[4] && - !_theResult____h350735[3] && - !_theResult____h350735[2] && - !_theResult____h350735[1] && - !_theResult____h350735[0] || + assign _theResult___fst_exp__h358918 = + (!_theResult____h350736[56] && !_theResult____h350736[55] && + !_theResult____h350736[54] && + !_theResult____h350736[53] && + !_theResult____h350736[52] && + !_theResult____h350736[51] && + !_theResult____h350736[50] && + !_theResult____h350736[49] && + !_theResult____h350736[48] && + !_theResult____h350736[47] && + !_theResult____h350736[46] && + !_theResult____h350736[45] && + !_theResult____h350736[44] && + !_theResult____h350736[43] && + !_theResult____h350736[42] && + !_theResult____h350736[41] && + !_theResult____h350736[40] && + !_theResult____h350736[39] && + !_theResult____h350736[38] && + !_theResult____h350736[37] && + !_theResult____h350736[36] && + !_theResult____h350736[35] && + !_theResult____h350736[34] && + !_theResult____h350736[33] && + !_theResult____h350736[32] && + !_theResult____h350736[31] && + !_theResult____h350736[30] && + !_theResult____h350736[29] && + !_theResult____h350736[28] && + !_theResult____h350736[27] && + !_theResult____h350736[26] && + !_theResult____h350736[25] && + !_theResult____h350736[24] && + !_theResult____h350736[23] && + !_theResult____h350736[22] && + !_theResult____h350736[21] && + !_theResult____h350736[20] && + !_theResult____h350736[19] && + !_theResult____h350736[18] && + !_theResult____h350736[17] && + !_theResult____h350736[16] && + !_theResult____h350736[15] && + !_theResult____h350736[14] && + !_theResult____h350736[13] && + !_theResult____h350736[12] && + !_theResult____h350736[11] && + !_theResult____h350736[10] && + !_theResult____h350736[9] && + !_theResult____h350736[8] && + !_theResult____h350736[7] && + !_theResult____h350736[6] && + !_theResult____h350736[5] && + !_theResult____h350736[4] && + !_theResult____h350736[3] && + !_theResult____h350736[2] && + !_theResult____h350736[1] && + !_theResult____h350736[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345) ? 8'd0 : - _theResult___fst_exp__h358911 ; - assign _theResult___fst_exp__h358920 = - (!_theResult____h350735[56] && _theResult____h350735[55]) ? + _theResult___fst_exp__h358912 ; + assign _theResult___fst_exp__h358921 = + (!_theResult____h350736[56] && _theResult____h350736[55]) ? 8'd1 : - _theResult___fst_exp__h358917 ; - assign _theResult___fst_exp__h359443 = - (_theResult___fst_exp__h358846 == 8'd255) ? - _theResult___fst_exp__h358846 : - _theResult___fst_exp__h359440 ; - assign _theResult___fst_exp__h367493 = + _theResult___fst_exp__h358918 ; + assign _theResult___fst_exp__h359444 = + (_theResult___fst_exp__h358847 == 8'd255) ? + _theResult___fst_exp__h358847 : + _theResult___fst_exp__h359441 ; + assign _theResult___fst_exp__h367494 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h367499 = + assign _theResult___fst_exp__h367500 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576) ? 8'd0 : - _theResult___fst_exp__h367493 ; - assign _theResult___fst_exp__h367502 = + _theResult___fst_exp__h367494 ; + assign _theResult___fst_exp__h367503 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h367499 : + _theResult___fst_exp__h367500 : 8'd129 ; - assign _theResult___fst_exp__h368025 = - (_theResult___fst_exp__h367502 == 8'd255) ? - _theResult___fst_exp__h367502 : - _theResult___fst_exp__h368022 ; - assign _theResult___fst_exp__h376612 = - _theResult____h368374[56] ? + assign _theResult___fst_exp__h368026 = + (_theResult___fst_exp__h367503 == 8'd255) ? + _theResult___fst_exp__h367503 : + _theResult___fst_exp__h368023 ; + assign _theResult___fst_exp__h376613 = + _theResult____h368375[56] ? 8'd2 : - _theResult___fst_exp__h376686 ; - assign _theResult___fst_exp__h376677 = + _theResult___fst_exp__h376687 ; + assign _theResult___fst_exp__h376678 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 } ; - assign _theResult___fst_exp__h376683 = - (!_theResult____h368374[56] && !_theResult____h368374[55] && - !_theResult____h368374[54] && - !_theResult____h368374[53] && - !_theResult____h368374[52] && - !_theResult____h368374[51] && - !_theResult____h368374[50] && - !_theResult____h368374[49] && - !_theResult____h368374[48] && - !_theResult____h368374[47] && - !_theResult____h368374[46] && - !_theResult____h368374[45] && - !_theResult____h368374[44] && - !_theResult____h368374[43] && - !_theResult____h368374[42] && - !_theResult____h368374[41] && - !_theResult____h368374[40] && - !_theResult____h368374[39] && - !_theResult____h368374[38] && - !_theResult____h368374[37] && - !_theResult____h368374[36] && - !_theResult____h368374[35] && - !_theResult____h368374[34] && - !_theResult____h368374[33] && - !_theResult____h368374[32] && - !_theResult____h368374[31] && - !_theResult____h368374[30] && - !_theResult____h368374[29] && - !_theResult____h368374[28] && - !_theResult____h368374[27] && - !_theResult____h368374[26] && - !_theResult____h368374[25] && - !_theResult____h368374[24] && - !_theResult____h368374[23] && - !_theResult____h368374[22] && - !_theResult____h368374[21] && - !_theResult____h368374[20] && - !_theResult____h368374[19] && - !_theResult____h368374[18] && - !_theResult____h368374[17] && - !_theResult____h368374[16] && - !_theResult____h368374[15] && - !_theResult____h368374[14] && - !_theResult____h368374[13] && - !_theResult____h368374[12] && - !_theResult____h368374[11] && - !_theResult____h368374[10] && - !_theResult____h368374[9] && - !_theResult____h368374[8] && - !_theResult____h368374[7] && - !_theResult____h368374[6] && - !_theResult____h368374[5] && - !_theResult____h368374[4] && - !_theResult____h368374[3] && - !_theResult____h368374[2] && - !_theResult____h368374[1] && - !_theResult____h368374[0] || + assign _theResult___fst_exp__h376684 = + (!_theResult____h368375[56] && !_theResult____h368375[55] && + !_theResult____h368375[54] && + !_theResult____h368375[53] && + !_theResult____h368375[52] && + !_theResult____h368375[51] && + !_theResult____h368375[50] && + !_theResult____h368375[49] && + !_theResult____h368375[48] && + !_theResult____h368375[47] && + !_theResult____h368375[46] && + !_theResult____h368375[45] && + !_theResult____h368375[44] && + !_theResult____h368375[43] && + !_theResult____h368375[42] && + !_theResult____h368375[41] && + !_theResult____h368375[40] && + !_theResult____h368375[39] && + !_theResult____h368375[38] && + !_theResult____h368375[37] && + !_theResult____h368375[36] && + !_theResult____h368375[35] && + !_theResult____h368375[34] && + !_theResult____h368375[33] && + !_theResult____h368375[32] && + !_theResult____h368375[31] && + !_theResult____h368375[30] && + !_theResult____h368375[29] && + !_theResult____h368375[28] && + !_theResult____h368375[27] && + !_theResult____h368375[26] && + !_theResult____h368375[25] && + !_theResult____h368375[24] && + !_theResult____h368375[23] && + !_theResult____h368375[22] && + !_theResult____h368375[21] && + !_theResult____h368375[20] && + !_theResult____h368375[19] && + !_theResult____h368375[18] && + !_theResult____h368375[17] && + !_theResult____h368375[16] && + !_theResult____h368375[15] && + !_theResult____h368375[14] && + !_theResult____h368375[13] && + !_theResult____h368375[12] && + !_theResult____h368375[11] && + !_theResult____h368375[10] && + !_theResult____h368375[9] && + !_theResult____h368375[8] && + !_theResult____h368375[7] && + !_theResult____h368375[6] && + !_theResult____h368375[5] && + !_theResult____h368375[4] && + !_theResult____h368375[3] && + !_theResult____h368375[2] && + !_theResult____h368375[1] && + !_theResult____h368375[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896) ? 8'd0 : - _theResult___fst_exp__h376677 ; - assign _theResult___fst_exp__h376686 = - (!_theResult____h368374[56] && _theResult____h368374[55]) ? + _theResult___fst_exp__h376678 ; + assign _theResult___fst_exp__h376687 = + (!_theResult____h368375[56] && _theResult____h368375[55]) ? 8'd1 : - _theResult___fst_exp__h376683 ; - assign _theResult___fst_exp__h377209 = - (_theResult___fst_exp__h376612 == 8'd255) ? - _theResult___fst_exp__h376612 : - _theResult___fst_exp__h377206 ; - assign _theResult___fst_exp__h385249 = + _theResult___fst_exp__h376684 ; + assign _theResult___fst_exp__h377210 = + (_theResult___fst_exp__h376613 == 8'd255) ? + _theResult___fst_exp__h376613 : + _theResult___fst_exp__h377207 ; + assign _theResult___fst_exp__h385250 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ; - assign _theResult___fst_exp__h385288 = + assign _theResult___fst_exp__h385289 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ; - assign _theResult___fst_exp__h385294 = + assign _theResult___fst_exp__h385295 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969) ? 8'd0 : - _theResult___fst_exp__h385288 ; - assign _theResult___fst_exp__h385297 = + _theResult___fst_exp__h385289 ; + assign _theResult___fst_exp__h385298 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h385294 : - _theResult___fst_exp__h385249 ; - assign _theResult___fst_exp__h385845 = - (_theResult___fst_exp__h385297 == 8'd255) ? - _theResult___fst_exp__h385297 : - _theResult___fst_exp__h385842 ; - assign _theResult___fst_exp__h385854 = + _theResult___fst_exp__h385295 : + _theResult___fst_exp__h385250 ; + assign _theResult___fst_exp__h385846 = + (_theResult___fst_exp__h385298 == 8'd255) ? + _theResult___fst_exp__h385298 : + _theResult___fst_exp__h385843 ; + assign _theResult___fst_exp__h385855 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_exp__h368028 : - _theResult___fst_exp__h350717) : + _theResult___snd_fst_exp__h368029 : + _theResult___fst_exp__h350718) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_exp__h385848 : - _theResult___fst_exp__h350717) ; - assign _theResult___fst_exp__h385857 = + _theResult___snd_fst_exp__h385849 : + _theResult___fst_exp__h350718) ; + assign _theResult___fst_exp__h385858 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h385854 ; - assign _theResult___fst_exp__h404543 = - _theResult____h396434[56] ? + _theResult___fst_exp__h385855 ; + assign _theResult___fst_exp__h404544 = + _theResult____h396435[56] ? 8'd2 : - _theResult___fst_exp__h404617 ; - assign _theResult___fst_exp__h404608 = + _theResult___fst_exp__h404618 ; + assign _theResult___fst_exp__h404609 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ; - assign _theResult___fst_exp__h404614 = - (!_theResult____h396434[56] && !_theResult____h396434[55] && - !_theResult____h396434[54] && - !_theResult____h396434[53] && - !_theResult____h396434[52] && - !_theResult____h396434[51] && - !_theResult____h396434[50] && - !_theResult____h396434[49] && - !_theResult____h396434[48] && - !_theResult____h396434[47] && - !_theResult____h396434[46] && - !_theResult____h396434[45] && - !_theResult____h396434[44] && - !_theResult____h396434[43] && - !_theResult____h396434[42] && - !_theResult____h396434[41] && - !_theResult____h396434[40] && - !_theResult____h396434[39] && - !_theResult____h396434[38] && - !_theResult____h396434[37] && - !_theResult____h396434[36] && - !_theResult____h396434[35] && - !_theResult____h396434[34] && - !_theResult____h396434[33] && - !_theResult____h396434[32] && - !_theResult____h396434[31] && - !_theResult____h396434[30] && - !_theResult____h396434[29] && - !_theResult____h396434[28] && - !_theResult____h396434[27] && - !_theResult____h396434[26] && - !_theResult____h396434[25] && - !_theResult____h396434[24] && - !_theResult____h396434[23] && - !_theResult____h396434[22] && - !_theResult____h396434[21] && - !_theResult____h396434[20] && - !_theResult____h396434[19] && - !_theResult____h396434[18] && - !_theResult____h396434[17] && - !_theResult____h396434[16] && - !_theResult____h396434[15] && - !_theResult____h396434[14] && - !_theResult____h396434[13] && - !_theResult____h396434[12] && - !_theResult____h396434[11] && - !_theResult____h396434[10] && - !_theResult____h396434[9] && - !_theResult____h396434[8] && - !_theResult____h396434[7] && - !_theResult____h396434[6] && - !_theResult____h396434[5] && - !_theResult____h396434[4] && - !_theResult____h396434[3] && - !_theResult____h396434[2] && - !_theResult____h396434[1] && - !_theResult____h396434[0] || + assign _theResult___fst_exp__h404615 = + (!_theResult____h396435[56] && !_theResult____h396435[55] && + !_theResult____h396435[54] && + !_theResult____h396435[53] && + !_theResult____h396435[52] && + !_theResult____h396435[51] && + !_theResult____h396435[50] && + !_theResult____h396435[49] && + !_theResult____h396435[48] && + !_theResult____h396435[47] && + !_theResult____h396435[46] && + !_theResult____h396435[45] && + !_theResult____h396435[44] && + !_theResult____h396435[43] && + !_theResult____h396435[42] && + !_theResult____h396435[41] && + !_theResult____h396435[40] && + !_theResult____h396435[39] && + !_theResult____h396435[38] && + !_theResult____h396435[37] && + !_theResult____h396435[36] && + !_theResult____h396435[35] && + !_theResult____h396435[34] && + !_theResult____h396435[33] && + !_theResult____h396435[32] && + !_theResult____h396435[31] && + !_theResult____h396435[30] && + !_theResult____h396435[29] && + !_theResult____h396435[28] && + !_theResult____h396435[27] && + !_theResult____h396435[26] && + !_theResult____h396435[25] && + !_theResult____h396435[24] && + !_theResult____h396435[23] && + !_theResult____h396435[22] && + !_theResult____h396435[21] && + !_theResult____h396435[20] && + !_theResult____h396435[19] && + !_theResult____h396435[18] && + !_theResult____h396435[17] && + !_theResult____h396435[16] && + !_theResult____h396435[15] && + !_theResult____h396435[14] && + !_theResult____h396435[13] && + !_theResult____h396435[12] && + !_theResult____h396435[11] && + !_theResult____h396435[10] && + !_theResult____h396435[9] && + !_theResult____h396435[8] && + !_theResult____h396435[7] && + !_theResult____h396435[6] && + !_theResult____h396435[5] && + !_theResult____h396435[4] && + !_theResult____h396435[3] && + !_theResult____h396435[2] && + !_theResult____h396435[1] && + !_theResult____h396435[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737) ? 8'd0 : - _theResult___fst_exp__h404608 ; - assign _theResult___fst_exp__h404617 = - (!_theResult____h396434[56] && _theResult____h396434[55]) ? + _theResult___fst_exp__h404609 ; + assign _theResult___fst_exp__h404618 = + (!_theResult____h396435[56] && _theResult____h396435[55]) ? 8'd1 : - _theResult___fst_exp__h404614 ; - assign _theResult___fst_exp__h405140 = - (_theResult___fst_exp__h404543 == 8'd255) ? - _theResult___fst_exp__h404543 : - _theResult___fst_exp__h405137 ; - assign _theResult___fst_exp__h413190 = + _theResult___fst_exp__h404615 ; + assign _theResult___fst_exp__h405141 = + (_theResult___fst_exp__h404544 == 8'd255) ? + _theResult___fst_exp__h404544 : + _theResult___fst_exp__h405138 ; + assign _theResult___fst_exp__h413191 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h413196 = + assign _theResult___fst_exp__h413197 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968) ? 8'd0 : - _theResult___fst_exp__h413190 ; - assign _theResult___fst_exp__h413199 = + _theResult___fst_exp__h413191 ; + assign _theResult___fst_exp__h413200 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h413196 : + _theResult___fst_exp__h413197 : 8'd129 ; - assign _theResult___fst_exp__h413722 = - (_theResult___fst_exp__h413199 == 8'd255) ? - _theResult___fst_exp__h413199 : - _theResult___fst_exp__h413719 ; - assign _theResult___fst_exp__h422309 = - _theResult____h414071[56] ? + assign _theResult___fst_exp__h413723 = + (_theResult___fst_exp__h413200 == 8'd255) ? + _theResult___fst_exp__h413200 : + _theResult___fst_exp__h413720 ; + assign _theResult___fst_exp__h422310 = + _theResult____h414072[56] ? 8'd2 : - _theResult___fst_exp__h422383 ; - assign _theResult___fst_exp__h422374 = + _theResult___fst_exp__h422384 ; + assign _theResult___fst_exp__h422375 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ; - assign _theResult___fst_exp__h422380 = - (!_theResult____h414071[56] && !_theResult____h414071[55] && - !_theResult____h414071[54] && - !_theResult____h414071[53] && - !_theResult____h414071[52] && - !_theResult____h414071[51] && - !_theResult____h414071[50] && - !_theResult____h414071[49] && - !_theResult____h414071[48] && - !_theResult____h414071[47] && - !_theResult____h414071[46] && - !_theResult____h414071[45] && - !_theResult____h414071[44] && - !_theResult____h414071[43] && - !_theResult____h414071[42] && - !_theResult____h414071[41] && - !_theResult____h414071[40] && - !_theResult____h414071[39] && - !_theResult____h414071[38] && - !_theResult____h414071[37] && - !_theResult____h414071[36] && - !_theResult____h414071[35] && - !_theResult____h414071[34] && - !_theResult____h414071[33] && - !_theResult____h414071[32] && - !_theResult____h414071[31] && - !_theResult____h414071[30] && - !_theResult____h414071[29] && - !_theResult____h414071[28] && - !_theResult____h414071[27] && - !_theResult____h414071[26] && - !_theResult____h414071[25] && - !_theResult____h414071[24] && - !_theResult____h414071[23] && - !_theResult____h414071[22] && - !_theResult____h414071[21] && - !_theResult____h414071[20] && - !_theResult____h414071[19] && - !_theResult____h414071[18] && - !_theResult____h414071[17] && - !_theResult____h414071[16] && - !_theResult____h414071[15] && - !_theResult____h414071[14] && - !_theResult____h414071[13] && - !_theResult____h414071[12] && - !_theResult____h414071[11] && - !_theResult____h414071[10] && - !_theResult____h414071[9] && - !_theResult____h414071[8] && - !_theResult____h414071[7] && - !_theResult____h414071[6] && - !_theResult____h414071[5] && - !_theResult____h414071[4] && - !_theResult____h414071[3] && - !_theResult____h414071[2] && - !_theResult____h414071[1] && - !_theResult____h414071[0] || + assign _theResult___fst_exp__h422381 = + (!_theResult____h414072[56] && !_theResult____h414072[55] && + !_theResult____h414072[54] && + !_theResult____h414072[53] && + !_theResult____h414072[52] && + !_theResult____h414072[51] && + !_theResult____h414072[50] && + !_theResult____h414072[49] && + !_theResult____h414072[48] && + !_theResult____h414072[47] && + !_theResult____h414072[46] && + !_theResult____h414072[45] && + !_theResult____h414072[44] && + !_theResult____h414072[43] && + !_theResult____h414072[42] && + !_theResult____h414072[41] && + !_theResult____h414072[40] && + !_theResult____h414072[39] && + !_theResult____h414072[38] && + !_theResult____h414072[37] && + !_theResult____h414072[36] && + !_theResult____h414072[35] && + !_theResult____h414072[34] && + !_theResult____h414072[33] && + !_theResult____h414072[32] && + !_theResult____h414072[31] && + !_theResult____h414072[30] && + !_theResult____h414072[29] && + !_theResult____h414072[28] && + !_theResult____h414072[27] && + !_theResult____h414072[26] && + !_theResult____h414072[25] && + !_theResult____h414072[24] && + !_theResult____h414072[23] && + !_theResult____h414072[22] && + !_theResult____h414072[21] && + !_theResult____h414072[20] && + !_theResult____h414072[19] && + !_theResult____h414072[18] && + !_theResult____h414072[17] && + !_theResult____h414072[16] && + !_theResult____h414072[15] && + !_theResult____h414072[14] && + !_theResult____h414072[13] && + !_theResult____h414072[12] && + !_theResult____h414072[11] && + !_theResult____h414072[10] && + !_theResult____h414072[9] && + !_theResult____h414072[8] && + !_theResult____h414072[7] && + !_theResult____h414072[6] && + !_theResult____h414072[5] && + !_theResult____h414072[4] && + !_theResult____h414072[3] && + !_theResult____h414072[2] && + !_theResult____h414072[1] && + !_theResult____h414072[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288) ? 8'd0 : - _theResult___fst_exp__h422374 ; - assign _theResult___fst_exp__h422383 = - (!_theResult____h414071[56] && _theResult____h414071[55]) ? + _theResult___fst_exp__h422375 ; + assign _theResult___fst_exp__h422384 = + (!_theResult____h414072[56] && _theResult____h414072[55]) ? 8'd1 : - _theResult___fst_exp__h422380 ; - assign _theResult___fst_exp__h422906 = - (_theResult___fst_exp__h422309 == 8'd255) ? - _theResult___fst_exp__h422309 : - _theResult___fst_exp__h422903 ; - assign _theResult___fst_exp__h430946 = + _theResult___fst_exp__h422381 ; + assign _theResult___fst_exp__h422907 = + (_theResult___fst_exp__h422310 == 8'd255) ? + _theResult___fst_exp__h422310 : + _theResult___fst_exp__h422904 ; + assign _theResult___fst_exp__h430947 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ; - assign _theResult___fst_exp__h430985 = + assign _theResult___fst_exp__h430986 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ; - assign _theResult___fst_exp__h430991 = + assign _theResult___fst_exp__h430992 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361) ? 8'd0 : - _theResult___fst_exp__h430985 ; - assign _theResult___fst_exp__h430994 = + _theResult___fst_exp__h430986 ; + assign _theResult___fst_exp__h430995 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h430991 : - _theResult___fst_exp__h430946 ; - assign _theResult___fst_exp__h431542 = - (_theResult___fst_exp__h430994 == 8'd255) ? - _theResult___fst_exp__h430994 : - _theResult___fst_exp__h431539 ; - assign _theResult___fst_exp__h431551 = + _theResult___fst_exp__h430992 : + _theResult___fst_exp__h430947 ; + assign _theResult___fst_exp__h431543 = + (_theResult___fst_exp__h430995 == 8'd255) ? + _theResult___fst_exp__h430995 : + _theResult___fst_exp__h431540 ; + assign _theResult___fst_exp__h431552 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_exp__h413725 : - _theResult___fst_exp__h396416) : + _theResult___snd_fst_exp__h413726 : + _theResult___fst_exp__h396417) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_exp__h431545 : - _theResult___fst_exp__h396416) ; - assign _theResult___fst_exp__h431554 = + _theResult___snd_fst_exp__h431546 : + _theResult___fst_exp__h396417) ; + assign _theResult___fst_exp__h431555 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h431551 ; - assign _theResult___fst_exp__h450238 = - _theResult____h442129[56] ? + _theResult___fst_exp__h431552 ; + assign _theResult___fst_exp__h450239 = + _theResult____h442130[56] ? 8'd2 : - _theResult___fst_exp__h450312 ; - assign _theResult___fst_exp__h450303 = + _theResult___fst_exp__h450313 ; + assign _theResult___fst_exp__h450304 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ; - assign _theResult___fst_exp__h450309 = - (!_theResult____h442129[56] && !_theResult____h442129[55] && - !_theResult____h442129[54] && - !_theResult____h442129[53] && - !_theResult____h442129[52] && - !_theResult____h442129[51] && - !_theResult____h442129[50] && - !_theResult____h442129[49] && - !_theResult____h442129[48] && - !_theResult____h442129[47] && - !_theResult____h442129[46] && - !_theResult____h442129[45] && - !_theResult____h442129[44] && - !_theResult____h442129[43] && - !_theResult____h442129[42] && - !_theResult____h442129[41] && - !_theResult____h442129[40] && - !_theResult____h442129[39] && - !_theResult____h442129[38] && - !_theResult____h442129[37] && - !_theResult____h442129[36] && - !_theResult____h442129[35] && - !_theResult____h442129[34] && - !_theResult____h442129[33] && - !_theResult____h442129[32] && - !_theResult____h442129[31] && - !_theResult____h442129[30] && - !_theResult____h442129[29] && - !_theResult____h442129[28] && - !_theResult____h442129[27] && - !_theResult____h442129[26] && - !_theResult____h442129[25] && - !_theResult____h442129[24] && - !_theResult____h442129[23] && - !_theResult____h442129[22] && - !_theResult____h442129[21] && - !_theResult____h442129[20] && - !_theResult____h442129[19] && - !_theResult____h442129[18] && - !_theResult____h442129[17] && - !_theResult____h442129[16] && - !_theResult____h442129[15] && - !_theResult____h442129[14] && - !_theResult____h442129[13] && - !_theResult____h442129[12] && - !_theResult____h442129[11] && - !_theResult____h442129[10] && - !_theResult____h442129[9] && - !_theResult____h442129[8] && - !_theResult____h442129[7] && - !_theResult____h442129[6] && - !_theResult____h442129[5] && - !_theResult____h442129[4] && - !_theResult____h442129[3] && - !_theResult____h442129[2] && - !_theResult____h442129[1] && - !_theResult____h442129[0] || + assign _theResult___fst_exp__h450310 = + (!_theResult____h442130[56] && !_theResult____h442130[55] && + !_theResult____h442130[54] && + !_theResult____h442130[53] && + !_theResult____h442130[52] && + !_theResult____h442130[51] && + !_theResult____h442130[50] && + !_theResult____h442130[49] && + !_theResult____h442130[48] && + !_theResult____h442130[47] && + !_theResult____h442130[46] && + !_theResult____h442130[45] && + !_theResult____h442130[44] && + !_theResult____h442130[43] && + !_theResult____h442130[42] && + !_theResult____h442130[41] && + !_theResult____h442130[40] && + !_theResult____h442130[39] && + !_theResult____h442130[38] && + !_theResult____h442130[37] && + !_theResult____h442130[36] && + !_theResult____h442130[35] && + !_theResult____h442130[34] && + !_theResult____h442130[33] && + !_theResult____h442130[32] && + !_theResult____h442130[31] && + !_theResult____h442130[30] && + !_theResult____h442130[29] && + !_theResult____h442130[28] && + !_theResult____h442130[27] && + !_theResult____h442130[26] && + !_theResult____h442130[25] && + !_theResult____h442130[24] && + !_theResult____h442130[23] && + !_theResult____h442130[22] && + !_theResult____h442130[21] && + !_theResult____h442130[20] && + !_theResult____h442130[19] && + !_theResult____h442130[18] && + !_theResult____h442130[17] && + !_theResult____h442130[16] && + !_theResult____h442130[15] && + !_theResult____h442130[14] && + !_theResult____h442130[13] && + !_theResult____h442130[12] && + !_theResult____h442130[11] && + !_theResult____h442130[10] && + !_theResult____h442130[9] && + !_theResult____h442130[8] && + !_theResult____h442130[7] && + !_theResult____h442130[6] && + !_theResult____h442130[5] && + !_theResult____h442130[4] && + !_theResult____h442130[3] && + !_theResult____h442130[2] && + !_theResult____h442130[1] && + !_theResult____h442130[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129) ? 8'd0 : - _theResult___fst_exp__h450303 ; - assign _theResult___fst_exp__h450312 = - (!_theResult____h442129[56] && _theResult____h442129[55]) ? + _theResult___fst_exp__h450304 ; + assign _theResult___fst_exp__h450313 = + (!_theResult____h442130[56] && _theResult____h442130[55]) ? 8'd1 : - _theResult___fst_exp__h450309 ; - assign _theResult___fst_exp__h450835 = - (_theResult___fst_exp__h450238 == 8'd255) ? - _theResult___fst_exp__h450238 : - _theResult___fst_exp__h450832 ; - assign _theResult___fst_exp__h458885 = + _theResult___fst_exp__h450310 ; + assign _theResult___fst_exp__h450836 = + (_theResult___fst_exp__h450239 == 8'd255) ? + _theResult___fst_exp__h450239 : + _theResult___fst_exp__h450833 ; + assign _theResult___fst_exp__h458886 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h458891 = + assign _theResult___fst_exp__h458892 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360) ? 8'd0 : - _theResult___fst_exp__h458885 ; - assign _theResult___fst_exp__h458894 = + _theResult___fst_exp__h458886 ; + assign _theResult___fst_exp__h458895 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h458891 : + _theResult___fst_exp__h458892 : 8'd129 ; - assign _theResult___fst_exp__h459417 = - (_theResult___fst_exp__h458894 == 8'd255) ? - _theResult___fst_exp__h458894 : - _theResult___fst_exp__h459414 ; - assign _theResult___fst_exp__h468004 = - _theResult____h459766[56] ? + assign _theResult___fst_exp__h459418 = + (_theResult___fst_exp__h458895 == 8'd255) ? + _theResult___fst_exp__h458895 : + _theResult___fst_exp__h459415 ; + assign _theResult___fst_exp__h468005 = + _theResult____h459767[56] ? 8'd2 : - _theResult___fst_exp__h468078 ; - assign _theResult___fst_exp__h468069 = + _theResult___fst_exp__h468079 ; + assign _theResult___fst_exp__h468070 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ; - assign _theResult___fst_exp__h468075 = - (!_theResult____h459766[56] && !_theResult____h459766[55] && - !_theResult____h459766[54] && - !_theResult____h459766[53] && - !_theResult____h459766[52] && - !_theResult____h459766[51] && - !_theResult____h459766[50] && - !_theResult____h459766[49] && - !_theResult____h459766[48] && - !_theResult____h459766[47] && - !_theResult____h459766[46] && - !_theResult____h459766[45] && - !_theResult____h459766[44] && - !_theResult____h459766[43] && - !_theResult____h459766[42] && - !_theResult____h459766[41] && - !_theResult____h459766[40] && - !_theResult____h459766[39] && - !_theResult____h459766[38] && - !_theResult____h459766[37] && - !_theResult____h459766[36] && - !_theResult____h459766[35] && - !_theResult____h459766[34] && - !_theResult____h459766[33] && - !_theResult____h459766[32] && - !_theResult____h459766[31] && - !_theResult____h459766[30] && - !_theResult____h459766[29] && - !_theResult____h459766[28] && - !_theResult____h459766[27] && - !_theResult____h459766[26] && - !_theResult____h459766[25] && - !_theResult____h459766[24] && - !_theResult____h459766[23] && - !_theResult____h459766[22] && - !_theResult____h459766[21] && - !_theResult____h459766[20] && - !_theResult____h459766[19] && - !_theResult____h459766[18] && - !_theResult____h459766[17] && - !_theResult____h459766[16] && - !_theResult____h459766[15] && - !_theResult____h459766[14] && - !_theResult____h459766[13] && - !_theResult____h459766[12] && - !_theResult____h459766[11] && - !_theResult____h459766[10] && - !_theResult____h459766[9] && - !_theResult____h459766[8] && - !_theResult____h459766[7] && - !_theResult____h459766[6] && - !_theResult____h459766[5] && - !_theResult____h459766[4] && - !_theResult____h459766[3] && - !_theResult____h459766[2] && - !_theResult____h459766[1] && - !_theResult____h459766[0] || + assign _theResult___fst_exp__h468076 = + (!_theResult____h459767[56] && !_theResult____h459767[55] && + !_theResult____h459767[54] && + !_theResult____h459767[53] && + !_theResult____h459767[52] && + !_theResult____h459767[51] && + !_theResult____h459767[50] && + !_theResult____h459767[49] && + !_theResult____h459767[48] && + !_theResult____h459767[47] && + !_theResult____h459767[46] && + !_theResult____h459767[45] && + !_theResult____h459767[44] && + !_theResult____h459767[43] && + !_theResult____h459767[42] && + !_theResult____h459767[41] && + !_theResult____h459767[40] && + !_theResult____h459767[39] && + !_theResult____h459767[38] && + !_theResult____h459767[37] && + !_theResult____h459767[36] && + !_theResult____h459767[35] && + !_theResult____h459767[34] && + !_theResult____h459767[33] && + !_theResult____h459767[32] && + !_theResult____h459767[31] && + !_theResult____h459767[30] && + !_theResult____h459767[29] && + !_theResult____h459767[28] && + !_theResult____h459767[27] && + !_theResult____h459767[26] && + !_theResult____h459767[25] && + !_theResult____h459767[24] && + !_theResult____h459767[23] && + !_theResult____h459767[22] && + !_theResult____h459767[21] && + !_theResult____h459767[20] && + !_theResult____h459767[19] && + !_theResult____h459767[18] && + !_theResult____h459767[17] && + !_theResult____h459767[16] && + !_theResult____h459767[15] && + !_theResult____h459767[14] && + !_theResult____h459767[13] && + !_theResult____h459767[12] && + !_theResult____h459767[11] && + !_theResult____h459767[10] && + !_theResult____h459767[9] && + !_theResult____h459767[8] && + !_theResult____h459767[7] && + !_theResult____h459767[6] && + !_theResult____h459767[5] && + !_theResult____h459767[4] && + !_theResult____h459767[3] && + !_theResult____h459767[2] && + !_theResult____h459767[1] && + !_theResult____h459767[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680) ? 8'd0 : - _theResult___fst_exp__h468069 ; - assign _theResult___fst_exp__h468078 = - (!_theResult____h459766[56] && _theResult____h459766[55]) ? + _theResult___fst_exp__h468070 ; + assign _theResult___fst_exp__h468079 = + (!_theResult____h459767[56] && _theResult____h459767[55]) ? 8'd1 : - _theResult___fst_exp__h468075 ; - assign _theResult___fst_exp__h468601 = - (_theResult___fst_exp__h468004 == 8'd255) ? - _theResult___fst_exp__h468004 : - _theResult___fst_exp__h468598 ; - assign _theResult___fst_exp__h476641 = + _theResult___fst_exp__h468076 ; + assign _theResult___fst_exp__h468602 = + (_theResult___fst_exp__h468005 == 8'd255) ? + _theResult___fst_exp__h468005 : + _theResult___fst_exp__h468599 ; + assign _theResult___fst_exp__h476642 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ; - assign _theResult___fst_exp__h476680 = + assign _theResult___fst_exp__h476681 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ; - assign _theResult___fst_exp__h476686 = + assign _theResult___fst_exp__h476687 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753) ? 8'd0 : - _theResult___fst_exp__h476680 ; - assign _theResult___fst_exp__h476689 = + _theResult___fst_exp__h476681 ; + assign _theResult___fst_exp__h476690 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h476686 : - _theResult___fst_exp__h476641 ; - assign _theResult___fst_exp__h477237 = - (_theResult___fst_exp__h476689 == 8'd255) ? - _theResult___fst_exp__h476689 : - _theResult___fst_exp__h477234 ; - assign _theResult___fst_exp__h477246 = + _theResult___fst_exp__h476687 : + _theResult___fst_exp__h476642 ; + assign _theResult___fst_exp__h477238 = + (_theResult___fst_exp__h476690 == 8'd255) ? + _theResult___fst_exp__h476690 : + _theResult___fst_exp__h477235 ; + assign _theResult___fst_exp__h477247 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_exp__h459420 : - _theResult___fst_exp__h442111) : + _theResult___snd_fst_exp__h459421 : + _theResult___fst_exp__h442112) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_exp__h477240 : - _theResult___fst_exp__h442111) ; - assign _theResult___fst_exp__h477249 = + _theResult___snd_fst_exp__h477241 : + _theResult___fst_exp__h442112) ; + assign _theResult___fst_exp__h477250 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h477246 ; - assign _theResult___fst_exp__h491841 = + _theResult___fst_exp__h477247 ; + assign _theResult___fst_exp__h491842 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ; - assign _theResult___fst_exp__h506905 = + assign _theResult___fst_exp__h506906 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h506911 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___fst_exp__h506912 = + (f1_exp__h487527 == 8'd0 && !f1_sfd__h487528[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696) ? 11'd0 : - _theResult___fst_exp__h506905 ; - assign _theResult___fst_exp__h506914 = - (f1_exp__h487526 == 8'd0) ? - _theResult___fst_exp__h506911 : + _theResult___fst_exp__h506906 ; + assign _theResult___fst_exp__h506915 = + (f1_exp__h487527 == 8'd0) ? + _theResult___fst_exp__h506912 : 11'd897 ; - assign _theResult___fst_exp__h507669 = + assign _theResult___fst_exp__h507670 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 : + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q136 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 ; - assign _theResult___fst_exp__h507672 = - (_theResult___fst_exp__h506914 == 11'd2047) ? - _theResult___fst_exp__h506914 : - _theResult___fst_exp__h507669 ; - assign _theResult___fst_exp__h516491 = - _theResult____h508255[56] ? + assign _theResult___fst_exp__h507673 = + (_theResult___fst_exp__h506915 == 11'd2047) ? + _theResult___fst_exp__h506915 : + _theResult___fst_exp__h507670 ; + assign _theResult___fst_exp__h516492 = + _theResult____h508256[56] ? 11'd2 : - _theResult___fst_exp__h516565 ; - assign _theResult___fst_exp__h516556 = + _theResult___fst_exp__h516566 ; + assign _theResult___fst_exp__h516557 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ; - assign _theResult___fst_exp__h516562 = - (!_theResult____h508255[56] && !_theResult____h508255[55] && - !_theResult____h508255[54] && - !_theResult____h508255[53] && - !_theResult____h508255[52] && - !_theResult____h508255[51] && - !_theResult____h508255[50] && - !_theResult____h508255[49] && - !_theResult____h508255[48] && - !_theResult____h508255[47] && - !_theResult____h508255[46] && - !_theResult____h508255[45] && - !_theResult____h508255[44] && - !_theResult____h508255[43] && - !_theResult____h508255[42] && - !_theResult____h508255[41] && - !_theResult____h508255[40] && - !_theResult____h508255[39] && - !_theResult____h508255[38] && - !_theResult____h508255[37] && - !_theResult____h508255[36] && - !_theResult____h508255[35] && - !_theResult____h508255[34] && - !_theResult____h508255[33] && - !_theResult____h508255[32] && - !_theResult____h508255[31] && - !_theResult____h508255[30] && - !_theResult____h508255[29] && - !_theResult____h508255[28] && - !_theResult____h508255[27] && - !_theResult____h508255[26] && - !_theResult____h508255[25] && - !_theResult____h508255[24] && - !_theResult____h508255[23] && - !_theResult____h508255[22] && - !_theResult____h508255[21] && - !_theResult____h508255[20] && - !_theResult____h508255[19] && - !_theResult____h508255[18] && - !_theResult____h508255[17] && - !_theResult____h508255[16] && - !_theResult____h508255[15] && - !_theResult____h508255[14] && - !_theResult____h508255[13] && - !_theResult____h508255[12] && - !_theResult____h508255[11] && - !_theResult____h508255[10] && - !_theResult____h508255[9] && - !_theResult____h508255[8] && - !_theResult____h508255[7] && - !_theResult____h508255[6] && - !_theResult____h508255[5] && - !_theResult____h508255[4] && - !_theResult____h508255[3] && - !_theResult____h508255[2] && - !_theResult____h508255[1] && - !_theResult____h508255[0] || + assign _theResult___fst_exp__h516563 = + (!_theResult____h508256[56] && !_theResult____h508256[55] && + !_theResult____h508256[54] && + !_theResult____h508256[53] && + !_theResult____h508256[52] && + !_theResult____h508256[51] && + !_theResult____h508256[50] && + !_theResult____h508256[49] && + !_theResult____h508256[48] && + !_theResult____h508256[47] && + !_theResult____h508256[46] && + !_theResult____h508256[45] && + !_theResult____h508256[44] && + !_theResult____h508256[43] && + !_theResult____h508256[42] && + !_theResult____h508256[41] && + !_theResult____h508256[40] && + !_theResult____h508256[39] && + !_theResult____h508256[38] && + !_theResult____h508256[37] && + !_theResult____h508256[36] && + !_theResult____h508256[35] && + !_theResult____h508256[34] && + !_theResult____h508256[33] && + !_theResult____h508256[32] && + !_theResult____h508256[31] && + !_theResult____h508256[30] && + !_theResult____h508256[29] && + !_theResult____h508256[28] && + !_theResult____h508256[27] && + !_theResult____h508256[26] && + !_theResult____h508256[25] && + !_theResult____h508256[24] && + !_theResult____h508256[23] && + !_theResult____h508256[22] && + !_theResult____h508256[21] && + !_theResult____h508256[20] && + !_theResult____h508256[19] && + !_theResult____h508256[18] && + !_theResult____h508256[17] && + !_theResult____h508256[16] && + !_theResult____h508256[15] && + !_theResult____h508256[14] && + !_theResult____h508256[13] && + !_theResult____h508256[12] && + !_theResult____h508256[11] && + !_theResult____h508256[10] && + !_theResult____h508256[9] && + !_theResult____h508256[8] && + !_theResult____h508256[7] && + !_theResult____h508256[6] && + !_theResult____h508256[5] && + !_theResult____h508256[4] && + !_theResult____h508256[3] && + !_theResult____h508256[2] && + !_theResult____h508256[1] && + !_theResult____h508256[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008) ? 11'd0 : - _theResult___fst_exp__h516556 ; - assign _theResult___fst_exp__h516565 = - (!_theResult____h508255[56] && _theResult____h508255[55]) ? + _theResult___fst_exp__h516557 ; + assign _theResult___fst_exp__h516566 = + (!_theResult____h508256[56] && _theResult____h508256[55]) ? 11'd1 : - _theResult___fst_exp__h516562 ; - assign _theResult___fst_exp__h517320 = + _theResult___fst_exp__h516563 ; + assign _theResult___fst_exp__h517321 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 : + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q204 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 ; - assign _theResult___fst_exp__h517323 = - (_theResult___fst_exp__h516491 == 11'd2047) ? - _theResult___fst_exp__h516491 : - _theResult___fst_exp__h517320 ; - assign _theResult___fst_exp__h525276 = + assign _theResult___fst_exp__h517324 = + (_theResult___fst_exp__h516492 == 11'd2047) ? + _theResult___fst_exp__h516492 : + _theResult___fst_exp__h517321 ; + assign _theResult___fst_exp__h525277 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] ; - assign _theResult___fst_exp__h525315 = + assign _theResult___fst_exp__h525316 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ; - assign _theResult___fst_exp__h525321 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___fst_exp__h525322 = + (f1_exp__h487527 == 8'd0 && !f1_sfd__h487528[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058) ? 11'd0 : - _theResult___fst_exp__h525315 ; - assign _theResult___fst_exp__h525324 = - (f1_exp__h487526 == 8'd0) ? - _theResult___fst_exp__h525321 : - _theResult___fst_exp__h525276 ; - assign _theResult___fst_exp__h526104 = + _theResult___fst_exp__h525316 ; + assign _theResult___fst_exp__h525325 = + (f1_exp__h487527 == 8'd0) ? + _theResult___fst_exp__h525322 : + _theResult___fst_exp__h525277 ; + assign _theResult___fst_exp__h526105 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 : + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 ; - assign _theResult___fst_exp__h526107 = - (_theResult___fst_exp__h525324 == 11'd2047) ? - _theResult___fst_exp__h525324 : - _theResult___fst_exp__h526104 ; - assign _theResult___fst_exp__h526116 = - (f1_exp__h487526 == 8'd0) ? + assign _theResult___fst_exp__h526108 = + (_theResult___fst_exp__h525325 == 11'd2047) ? + _theResult___fst_exp__h525325 : + _theResult___fst_exp__h526105 ; + assign _theResult___fst_exp__h526117 = + (f1_exp__h487527 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_exp__h507675 : - _theResult___fst_exp__h491841) : + _theResult___snd_fst_exp__h507676 : + _theResult___fst_exp__h491842) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_exp__h526110 : - _theResult___fst_exp__h491841) ; - assign _theResult___fst_exp__h526119 = - (f1_exp__h487526 == 8'd0 && f1_sfd__h487527 == 23'd0) ? + _theResult___snd_fst_exp__h526111 : + _theResult___fst_exp__h491842) ; + assign _theResult___fst_exp__h526120 = + (f1_exp__h487527 == 8'd0 && f1_sfd__h487528 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h526116 ; - assign _theResult___fst_exp__h530694 = + _theResult___fst_exp__h526117 ; + assign _theResult___fst_exp__h530695 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ; - assign _theResult___fst_exp__h545758 = + assign _theResult___fst_exp__h545759 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h545764 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___fst_exp__h545765 = + (f2_exp__h526521 == 8'd0 && !f2_sfd__h526522[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196) ? 11'd0 : - _theResult___fst_exp__h545758 ; - assign _theResult___fst_exp__h545767 = - (f2_exp__h526520 == 8'd0) ? - _theResult___fst_exp__h545764 : + _theResult___fst_exp__h545759 ; + assign _theResult___fst_exp__h545768 = + (f2_exp__h526521 == 8'd0) ? + _theResult___fst_exp__h545765 : 11'd897 ; - assign _theResult___fst_exp__h546522 = + assign _theResult___fst_exp__h546523 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 : + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q176 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 ; - assign _theResult___fst_exp__h546525 = - (_theResult___fst_exp__h545767 == 11'd2047) ? - _theResult___fst_exp__h545767 : - _theResult___fst_exp__h546522 ; - assign _theResult___fst_exp__h555344 = - _theResult____h547108[56] ? + assign _theResult___fst_exp__h546526 = + (_theResult___fst_exp__h545768 == 11'd2047) ? + _theResult___fst_exp__h545768 : + _theResult___fst_exp__h546523 ; + assign _theResult___fst_exp__h555345 = + _theResult____h547109[56] ? 11'd2 : - _theResult___fst_exp__h555418 ; - assign _theResult___fst_exp__h555409 = + _theResult___fst_exp__h555419 ; + assign _theResult___fst_exp__h555410 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ; - assign _theResult___fst_exp__h555415 = - (!_theResult____h547108[56] && !_theResult____h547108[55] && - !_theResult____h547108[54] && - !_theResult____h547108[53] && - !_theResult____h547108[52] && - !_theResult____h547108[51] && - !_theResult____h547108[50] && - !_theResult____h547108[49] && - !_theResult____h547108[48] && - !_theResult____h547108[47] && - !_theResult____h547108[46] && - !_theResult____h547108[45] && - !_theResult____h547108[44] && - !_theResult____h547108[43] && - !_theResult____h547108[42] && - !_theResult____h547108[41] && - !_theResult____h547108[40] && - !_theResult____h547108[39] && - !_theResult____h547108[38] && - !_theResult____h547108[37] && - !_theResult____h547108[36] && - !_theResult____h547108[35] && - !_theResult____h547108[34] && - !_theResult____h547108[33] && - !_theResult____h547108[32] && - !_theResult____h547108[31] && - !_theResult____h547108[30] && - !_theResult____h547108[29] && - !_theResult____h547108[28] && - !_theResult____h547108[27] && - !_theResult____h547108[26] && - !_theResult____h547108[25] && - !_theResult____h547108[24] && - !_theResult____h547108[23] && - !_theResult____h547108[22] && - !_theResult____h547108[21] && - !_theResult____h547108[20] && - !_theResult____h547108[19] && - !_theResult____h547108[18] && - !_theResult____h547108[17] && - !_theResult____h547108[16] && - !_theResult____h547108[15] && - !_theResult____h547108[14] && - !_theResult____h547108[13] && - !_theResult____h547108[12] && - !_theResult____h547108[11] && - !_theResult____h547108[10] && - !_theResult____h547108[9] && - !_theResult____h547108[8] && - !_theResult____h547108[7] && - !_theResult____h547108[6] && - !_theResult____h547108[5] && - !_theResult____h547108[4] && - !_theResult____h547108[3] && - !_theResult____h547108[2] && - !_theResult____h547108[1] && - !_theResult____h547108[0] || + assign _theResult___fst_exp__h555416 = + (!_theResult____h547109[56] && !_theResult____h547109[55] && + !_theResult____h547109[54] && + !_theResult____h547109[53] && + !_theResult____h547109[52] && + !_theResult____h547109[51] && + !_theResult____h547109[50] && + !_theResult____h547109[49] && + !_theResult____h547109[48] && + !_theResult____h547109[47] && + !_theResult____h547109[46] && + !_theResult____h547109[45] && + !_theResult____h547109[44] && + !_theResult____h547109[43] && + !_theResult____h547109[42] && + !_theResult____h547109[41] && + !_theResult____h547109[40] && + !_theResult____h547109[39] && + !_theResult____h547109[38] && + !_theResult____h547109[37] && + !_theResult____h547109[36] && + !_theResult____h547109[35] && + !_theResult____h547109[34] && + !_theResult____h547109[33] && + !_theResult____h547109[32] && + !_theResult____h547109[31] && + !_theResult____h547109[30] && + !_theResult____h547109[29] && + !_theResult____h547109[28] && + !_theResult____h547109[27] && + !_theResult____h547109[26] && + !_theResult____h547109[25] && + !_theResult____h547109[24] && + !_theResult____h547109[23] && + !_theResult____h547109[22] && + !_theResult____h547109[21] && + !_theResult____h547109[20] && + !_theResult____h547109[19] && + !_theResult____h547109[18] && + !_theResult____h547109[17] && + !_theResult____h547109[16] && + !_theResult____h547109[15] && + !_theResult____h547109[14] && + !_theResult____h547109[13] && + !_theResult____h547109[12] && + !_theResult____h547109[11] && + !_theResult____h547109[10] && + !_theResult____h547109[9] && + !_theResult____h547109[8] && + !_theResult____h547109[7] && + !_theResult____h547109[6] && + !_theResult____h547109[5] && + !_theResult____h547109[4] && + !_theResult____h547109[3] && + !_theResult____h547109[2] && + !_theResult____h547109[1] && + !_theResult____h547109[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493) ? 11'd0 : - _theResult___fst_exp__h555409 ; - assign _theResult___fst_exp__h555418 = - (!_theResult____h547108[56] && _theResult____h547108[55]) ? + _theResult___fst_exp__h555410 ; + assign _theResult___fst_exp__h555419 = + (!_theResult____h547109[56] && _theResult____h547109[55]) ? 11'd1 : - _theResult___fst_exp__h555415 ; - assign _theResult___fst_exp__h556173 = + _theResult___fst_exp__h555416 ; + assign _theResult___fst_exp__h556174 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 : + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q178 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 ; - assign _theResult___fst_exp__h556176 = - (_theResult___fst_exp__h555344 == 11'd2047) ? - _theResult___fst_exp__h555344 : - _theResult___fst_exp__h556173 ; - assign _theResult___fst_exp__h564129 = + assign _theResult___fst_exp__h556177 = + (_theResult___fst_exp__h555345 == 11'd2047) ? + _theResult___fst_exp__h555345 : + _theResult___fst_exp__h556174 ; + assign _theResult___fst_exp__h564130 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] ; - assign _theResult___fst_exp__h564168 = + assign _theResult___fst_exp__h564169 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ; - assign _theResult___fst_exp__h564174 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___fst_exp__h564175 = + (f2_exp__h526521 == 8'd0 && !f2_sfd__h526522[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543) ? 11'd0 : - _theResult___fst_exp__h564168 ; - assign _theResult___fst_exp__h564177 = - (f2_exp__h526520 == 8'd0) ? - _theResult___fst_exp__h564174 : - _theResult___fst_exp__h564129 ; - assign _theResult___fst_exp__h564957 = + _theResult___fst_exp__h564169 ; + assign _theResult___fst_exp__h564178 = + (f2_exp__h526521 == 8'd0) ? + _theResult___fst_exp__h564175 : + _theResult___fst_exp__h564130 ; + assign _theResult___fst_exp__h564958 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 : + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q180 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 ; - assign _theResult___fst_exp__h564960 = - (_theResult___fst_exp__h564177 == 11'd2047) ? - _theResult___fst_exp__h564177 : - _theResult___fst_exp__h564957 ; - assign _theResult___fst_exp__h564969 = - (f2_exp__h526520 == 8'd0) ? + assign _theResult___fst_exp__h564961 = + (_theResult___fst_exp__h564178 == 11'd2047) ? + _theResult___fst_exp__h564178 : + _theResult___fst_exp__h564958 ; + assign _theResult___fst_exp__h564970 = + (f2_exp__h526521 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_exp__h546528 : - _theResult___fst_exp__h530694) : + _theResult___snd_fst_exp__h546529 : + _theResult___fst_exp__h530695) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_exp__h564963 : - _theResult___fst_exp__h530694) ; - assign _theResult___fst_exp__h564972 = - (f2_exp__h526520 == 8'd0 && f2_sfd__h526521 == 23'd0) ? + _theResult___snd_fst_exp__h564964 : + _theResult___fst_exp__h530695) ; + assign _theResult___fst_exp__h564973 = + (f2_exp__h526521 == 8'd0 && f2_sfd__h526522 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h564969 ; - assign _theResult___fst_exp__h569998 = + _theResult___fst_exp__h564970 ; + assign _theResult___fst_exp__h569999 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ; - assign _theResult___fst_exp__h585062 = + assign _theResult___fst_exp__h585063 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h585068 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___fst_exp__h585069 = + (f3_exp__h565825 == 8'd0 && !f3_sfd__h565826[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426) ? 11'd0 : - _theResult___fst_exp__h585062 ; - assign _theResult___fst_exp__h585071 = - (f3_exp__h565824 == 8'd0) ? - _theResult___fst_exp__h585068 : + _theResult___fst_exp__h585063 ; + assign _theResult___fst_exp__h585072 = + (f3_exp__h565825 == 8'd0) ? + _theResult___fst_exp__h585069 : 11'd897 ; - assign _theResult___fst_exp__h585826 = + assign _theResult___fst_exp__h585827 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 : + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q153 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 ; - assign _theResult___fst_exp__h585829 = - (_theResult___fst_exp__h585071 == 11'd2047) ? - _theResult___fst_exp__h585071 : - _theResult___fst_exp__h585826 ; - assign _theResult___fst_exp__h594648 = - _theResult____h586412[56] ? + assign _theResult___fst_exp__h585830 = + (_theResult___fst_exp__h585072 == 11'd2047) ? + _theResult___fst_exp__h585072 : + _theResult___fst_exp__h585827 ; + assign _theResult___fst_exp__h594649 = + _theResult____h586413[56] ? 11'd2 : - _theResult___fst_exp__h594722 ; - assign _theResult___fst_exp__h594713 = + _theResult___fst_exp__h594723 ; + assign _theResult___fst_exp__h594714 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 } ; - assign _theResult___fst_exp__h594719 = - (!_theResult____h586412[56] && !_theResult____h586412[55] && - !_theResult____h586412[54] && - !_theResult____h586412[53] && - !_theResult____h586412[52] && - !_theResult____h586412[51] && - !_theResult____h586412[50] && - !_theResult____h586412[49] && - !_theResult____h586412[48] && - !_theResult____h586412[47] && - !_theResult____h586412[46] && - !_theResult____h586412[45] && - !_theResult____h586412[44] && - !_theResult____h586412[43] && - !_theResult____h586412[42] && - !_theResult____h586412[41] && - !_theResult____h586412[40] && - !_theResult____h586412[39] && - !_theResult____h586412[38] && - !_theResult____h586412[37] && - !_theResult____h586412[36] && - !_theResult____h586412[35] && - !_theResult____h586412[34] && - !_theResult____h586412[33] && - !_theResult____h586412[32] && - !_theResult____h586412[31] && - !_theResult____h586412[30] && - !_theResult____h586412[29] && - !_theResult____h586412[28] && - !_theResult____h586412[27] && - !_theResult____h586412[26] && - !_theResult____h586412[25] && - !_theResult____h586412[24] && - !_theResult____h586412[23] && - !_theResult____h586412[22] && - !_theResult____h586412[21] && - !_theResult____h586412[20] && - !_theResult____h586412[19] && - !_theResult____h586412[18] && - !_theResult____h586412[17] && - !_theResult____h586412[16] && - !_theResult____h586412[15] && - !_theResult____h586412[14] && - !_theResult____h586412[13] && - !_theResult____h586412[12] && - !_theResult____h586412[11] && - !_theResult____h586412[10] && - !_theResult____h586412[9] && - !_theResult____h586412[8] && - !_theResult____h586412[7] && - !_theResult____h586412[6] && - !_theResult____h586412[5] && - !_theResult____h586412[4] && - !_theResult____h586412[3] && - !_theResult____h586412[2] && - !_theResult____h586412[1] && - !_theResult____h586412[0] || + assign _theResult___fst_exp__h594720 = + (!_theResult____h586413[56] && !_theResult____h586413[55] && + !_theResult____h586413[54] && + !_theResult____h586413[53] && + !_theResult____h586413[52] && + !_theResult____h586413[51] && + !_theResult____h586413[50] && + !_theResult____h586413[49] && + !_theResult____h586413[48] && + !_theResult____h586413[47] && + !_theResult____h586413[46] && + !_theResult____h586413[45] && + !_theResult____h586413[44] && + !_theResult____h586413[43] && + !_theResult____h586413[42] && + !_theResult____h586413[41] && + !_theResult____h586413[40] && + !_theResult____h586413[39] && + !_theResult____h586413[38] && + !_theResult____h586413[37] && + !_theResult____h586413[36] && + !_theResult____h586413[35] && + !_theResult____h586413[34] && + !_theResult____h586413[33] && + !_theResult____h586413[32] && + !_theResult____h586413[31] && + !_theResult____h586413[30] && + !_theResult____h586413[29] && + !_theResult____h586413[28] && + !_theResult____h586413[27] && + !_theResult____h586413[26] && + !_theResult____h586413[25] && + !_theResult____h586413[24] && + !_theResult____h586413[23] && + !_theResult____h586413[22] && + !_theResult____h586413[21] && + !_theResult____h586413[20] && + !_theResult____h586413[19] && + !_theResult____h586413[18] && + !_theResult____h586413[17] && + !_theResult____h586413[16] && + !_theResult____h586413[15] && + !_theResult____h586413[14] && + !_theResult____h586413[13] && + !_theResult____h586413[12] && + !_theResult____h586413[11] && + !_theResult____h586413[10] && + !_theResult____h586413[9] && + !_theResult____h586413[8] && + !_theResult____h586413[7] && + !_theResult____h586413[6] && + !_theResult____h586413[5] && + !_theResult____h586413[4] && + !_theResult____h586413[3] && + !_theResult____h586413[2] && + !_theResult____h586413[1] && + !_theResult____h586413[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723) ? 11'd0 : - _theResult___fst_exp__h594713 ; - assign _theResult___fst_exp__h594722 = - (!_theResult____h586412[56] && _theResult____h586412[55]) ? + _theResult___fst_exp__h594714 ; + assign _theResult___fst_exp__h594723 = + (!_theResult____h586413[56] && _theResult____h586413[55]) ? 11'd1 : - _theResult___fst_exp__h594719 ; - assign _theResult___fst_exp__h595477 = + _theResult___fst_exp__h594720 ; + assign _theResult___fst_exp__h595478 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 : + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 ; - assign _theResult___fst_exp__h595480 = - (_theResult___fst_exp__h594648 == 11'd2047) ? - _theResult___fst_exp__h594648 : - _theResult___fst_exp__h595477 ; - assign _theResult___fst_exp__h603433 = + assign _theResult___fst_exp__h595481 = + (_theResult___fst_exp__h594649 == 11'd2047) ? + _theResult___fst_exp__h594649 : + _theResult___fst_exp__h595478 ; + assign _theResult___fst_exp__h603434 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] ; - assign _theResult___fst_exp__h603472 = + assign _theResult___fst_exp__h603473 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ; - assign _theResult___fst_exp__h603478 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___fst_exp__h603479 = + (f3_exp__h565825 == 8'd0 && !f3_sfd__h565826[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773) ? 11'd0 : - _theResult___fst_exp__h603472 ; - assign _theResult___fst_exp__h603481 = - (f3_exp__h565824 == 8'd0) ? - _theResult___fst_exp__h603478 : - _theResult___fst_exp__h603433 ; - assign _theResult___fst_exp__h604261 = + _theResult___fst_exp__h603473 ; + assign _theResult___fst_exp__h603482 = + (f3_exp__h565825 == 8'd0) ? + _theResult___fst_exp__h603479 : + _theResult___fst_exp__h603434 ; + assign _theResult___fst_exp__h604262 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 : + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q182 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 ; - assign _theResult___fst_exp__h604264 = - (_theResult___fst_exp__h603481 == 11'd2047) ? - _theResult___fst_exp__h603481 : - _theResult___fst_exp__h604261 ; - assign _theResult___fst_exp__h604273 = - (f3_exp__h565824 == 8'd0) ? + assign _theResult___fst_exp__h604265 = + (_theResult___fst_exp__h603482 == 11'd2047) ? + _theResult___fst_exp__h603482 : + _theResult___fst_exp__h604262 ; + assign _theResult___fst_exp__h604274 = + (f3_exp__h565825 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_exp__h585832 : - _theResult___fst_exp__h569998) : + _theResult___snd_fst_exp__h585833 : + _theResult___fst_exp__h569999) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_exp__h604267 : - _theResult___fst_exp__h569998) ; - assign _theResult___fst_exp__h604276 = - (f3_exp__h565824 == 8'd0 && f3_sfd__h565825 == 23'd0) ? + _theResult___snd_fst_exp__h604268 : + _theResult___fst_exp__h569999) ; + assign _theResult___fst_exp__h604277 = + (f3_exp__h565825 == 8'd0 && f3_sfd__h565826 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h604273 ; - assign _theResult___fst_sfd__h359444 = - (_theResult___fst_exp__h358846 == 8'd255) ? - sfdin__h358840[56:34] : - _theResult___fst_sfd__h359441 ; - assign _theResult___fst_sfd__h368026 = - (_theResult___fst_exp__h367502 == 8'd255) ? - _theResult___snd__h367453[56:34] : - _theResult___fst_sfd__h368023 ; - assign _theResult___fst_sfd__h377210 = - (_theResult___fst_exp__h376612 == 8'd255) ? - sfdin__h376606[56:34] : - _theResult___fst_sfd__h377207 ; - assign _theResult___fst_sfd__h385846 = - (_theResult___fst_exp__h385297 == 8'd255) ? - _theResult___snd__h385243[56:34] : - _theResult___fst_sfd__h385843 ; - assign _theResult___fst_sfd__h385855 = + _theResult___fst_exp__h604274 ; + assign _theResult___fst_sfd__h359445 = + (_theResult___fst_exp__h358847 == 8'd255) ? + sfdin__h358841[56:34] : + _theResult___fst_sfd__h359442 ; + assign _theResult___fst_sfd__h368027 = + (_theResult___fst_exp__h367503 == 8'd255) ? + _theResult___snd__h367454[56:34] : + _theResult___fst_sfd__h368024 ; + assign _theResult___fst_sfd__h377211 = + (_theResult___fst_exp__h376613 == 8'd255) ? + sfdin__h376607[56:34] : + _theResult___fst_sfd__h377208 ; + assign _theResult___fst_sfd__h385847 = + (_theResult___fst_exp__h385298 == 8'd255) ? + _theResult___snd__h385244[56:34] : + _theResult___fst_sfd__h385844 ; + assign _theResult___fst_sfd__h385856 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ? - _theResult___snd_fst_sfd__h368029 : - _theResult___fst_sfd__h350718) : + _theResult___snd_fst_sfd__h368030 : + _theResult___fst_sfd__h350719) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ? - _theResult___snd_fst_sfd__h385849 : - _theResult___fst_sfd__h350718) ; - assign _theResult___fst_sfd__h385861 = + _theResult___snd_fst_sfd__h385850 : + _theResult___fst_sfd__h350719) ; + assign _theResult___fst_sfd__h385862 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -26199,33 +26199,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h385855 ; - assign _theResult___fst_sfd__h405141 = - (_theResult___fst_exp__h404543 == 8'd255) ? - sfdin__h404537[56:34] : - _theResult___fst_sfd__h405138 ; - assign _theResult___fst_sfd__h413723 = - (_theResult___fst_exp__h413199 == 8'd255) ? - _theResult___snd__h413150[56:34] : - _theResult___fst_sfd__h413720 ; - assign _theResult___fst_sfd__h422907 = - (_theResult___fst_exp__h422309 == 8'd255) ? - sfdin__h422303[56:34] : - _theResult___fst_sfd__h422904 ; - assign _theResult___fst_sfd__h431543 = - (_theResult___fst_exp__h430994 == 8'd255) ? - _theResult___snd__h430940[56:34] : - _theResult___fst_sfd__h431540 ; - assign _theResult___fst_sfd__h431552 = + _theResult___fst_sfd__h385856 ; + assign _theResult___fst_sfd__h405142 = + (_theResult___fst_exp__h404544 == 8'd255) ? + sfdin__h404538[56:34] : + _theResult___fst_sfd__h405139 ; + assign _theResult___fst_sfd__h413724 = + (_theResult___fst_exp__h413200 == 8'd255) ? + _theResult___snd__h413151[56:34] : + _theResult___fst_sfd__h413721 ; + assign _theResult___fst_sfd__h422908 = + (_theResult___fst_exp__h422310 == 8'd255) ? + sfdin__h422304[56:34] : + _theResult___fst_sfd__h422905 ; + assign _theResult___fst_sfd__h431544 = + (_theResult___fst_exp__h430995 == 8'd255) ? + _theResult___snd__h430941[56:34] : + _theResult___fst_sfd__h431541 ; + assign _theResult___fst_sfd__h431553 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ? - _theResult___snd_fst_sfd__h413726 : - _theResult___fst_sfd__h396417) : + _theResult___snd_fst_sfd__h413727 : + _theResult___fst_sfd__h396418) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ? - _theResult___snd_fst_sfd__h431546 : - _theResult___fst_sfd__h396417) ; - assign _theResult___fst_sfd__h431558 = + _theResult___snd_fst_sfd__h431547 : + _theResult___fst_sfd__h396418) ; + assign _theResult___fst_sfd__h431559 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -26233,33 +26233,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h431552 ; - assign _theResult___fst_sfd__h450836 = - (_theResult___fst_exp__h450238 == 8'd255) ? - sfdin__h450232[56:34] : - _theResult___fst_sfd__h450833 ; - assign _theResult___fst_sfd__h459418 = - (_theResult___fst_exp__h458894 == 8'd255) ? - _theResult___snd__h458845[56:34] : - _theResult___fst_sfd__h459415 ; - assign _theResult___fst_sfd__h468602 = - (_theResult___fst_exp__h468004 == 8'd255) ? - sfdin__h467998[56:34] : - _theResult___fst_sfd__h468599 ; - assign _theResult___fst_sfd__h477238 = - (_theResult___fst_exp__h476689 == 8'd255) ? - _theResult___snd__h476635[56:34] : - _theResult___fst_sfd__h477235 ; - assign _theResult___fst_sfd__h477247 = + _theResult___fst_sfd__h431553 ; + assign _theResult___fst_sfd__h450837 = + (_theResult___fst_exp__h450239 == 8'd255) ? + sfdin__h450233[56:34] : + _theResult___fst_sfd__h450834 ; + assign _theResult___fst_sfd__h459419 = + (_theResult___fst_exp__h458895 == 8'd255) ? + _theResult___snd__h458846[56:34] : + _theResult___fst_sfd__h459416 ; + assign _theResult___fst_sfd__h468603 = + (_theResult___fst_exp__h468005 == 8'd255) ? + sfdin__h467999[56:34] : + _theResult___fst_sfd__h468600 ; + assign _theResult___fst_sfd__h477239 = + (_theResult___fst_exp__h476690 == 8'd255) ? + _theResult___snd__h476636[56:34] : + _theResult___fst_sfd__h477236 ; + assign _theResult___fst_sfd__h477248 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ? - _theResult___snd_fst_sfd__h459421 : - _theResult___fst_sfd__h442112) : + _theResult___snd_fst_sfd__h459422 : + _theResult___fst_sfd__h442113) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ? - _theResult___snd_fst_sfd__h477241 : - _theResult___fst_sfd__h442112) ; - assign _theResult___fst_sfd__h477253 = + _theResult___snd_fst_sfd__h477242 : + _theResult___fst_sfd__h442113) ; + assign _theResult___fst_sfd__h477254 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -26267,1312 +26267,1312 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h477247 ; - assign _theResult___fst_sfd__h491842 = + _theResult___fst_sfd__h477248 ; + assign _theResult___fst_sfd__h491843 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ; - assign _theResult___fst_sfd__h507670 = + assign _theResult___fst_sfd__h507671 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q208 : + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 ; - assign _theResult___fst_sfd__h507673 = - (_theResult___fst_exp__h506914 == 11'd2047) ? - _theResult___snd__h506865[56:5] : - _theResult___fst_sfd__h507670 ; - assign _theResult___fst_sfd__h517321 = + assign _theResult___fst_sfd__h507674 = + (_theResult___fst_exp__h506915 == 11'd2047) ? + _theResult___snd__h506866[56:5] : + _theResult___fst_sfd__h507671 ; + assign _theResult___fst_sfd__h517322 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q210 : + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 ; - assign _theResult___fst_sfd__h517324 = - (_theResult___fst_exp__h516491 == 11'd2047) ? - sfdin__h516485[56:5] : - _theResult___fst_sfd__h517321 ; - assign _theResult___fst_sfd__h526105 = + assign _theResult___fst_sfd__h517325 = + (_theResult___fst_exp__h516492 == 11'd2047) ? + sfdin__h516486[56:5] : + _theResult___fst_sfd__h517322 ; + assign _theResult___fst_sfd__h526106 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 : + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 ; - assign _theResult___fst_sfd__h526108 = - (_theResult___fst_exp__h525324 == 11'd2047) ? - _theResult___snd__h525270[56:5] : - _theResult___fst_sfd__h526105 ; - assign _theResult___fst_sfd__h526117 = - (f1_exp__h487526 == 8'd0) ? + assign _theResult___fst_sfd__h526109 = + (_theResult___fst_exp__h525325 == 11'd2047) ? + _theResult___snd__h525271[56:5] : + _theResult___fst_sfd__h526106 ; + assign _theResult___fst_sfd__h526118 = + (f1_exp__h487527 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ? - _theResult___snd_fst_sfd__h507676 : - _theResult___fst_sfd__h491842) : + _theResult___snd_fst_sfd__h507677 : + _theResult___fst_sfd__h491843) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ? - _theResult___snd_fst_sfd__h526111 : - _theResult___fst_sfd__h491842) ; - assign _theResult___fst_sfd__h526123 = - ((f1_exp__h487526 == 8'd255 || f1_exp__h487526 == 8'd0) && - f1_sfd__h487527 == 23'd0) ? + _theResult___snd_fst_sfd__h526112 : + _theResult___fst_sfd__h491843) ; + assign _theResult___fst_sfd__h526124 = + ((f1_exp__h487527 == 8'd255 || f1_exp__h487527 == 8'd0) && + f1_sfd__h487528 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h526117 ; - assign _theResult___fst_sfd__h530695 = + _theResult___fst_sfd__h526118 ; + assign _theResult___fst_sfd__h530696 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ; - assign _theResult___fst_sfd__h546523 = + assign _theResult___fst_sfd__h546524 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 : + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q198 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 ; - assign _theResult___fst_sfd__h546526 = - (_theResult___fst_exp__h545767 == 11'd2047) ? - _theResult___snd__h545718[56:5] : - _theResult___fst_sfd__h546523 ; - assign _theResult___fst_sfd__h556174 = + assign _theResult___fst_sfd__h546527 = + (_theResult___fst_exp__h545768 == 11'd2047) ? + _theResult___snd__h545719[56:5] : + _theResult___fst_sfd__h546524 ; + assign _theResult___fst_sfd__h556175 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 : + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q200 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 ; - assign _theResult___fst_sfd__h556177 = - (_theResult___fst_exp__h555344 == 11'd2047) ? - sfdin__h555338[56:5] : - _theResult___fst_sfd__h556174 ; - assign _theResult___fst_sfd__h564958 = + assign _theResult___fst_sfd__h556178 = + (_theResult___fst_exp__h555345 == 11'd2047) ? + sfdin__h555339[56:5] : + _theResult___fst_sfd__h556175 ; + assign _theResult___fst_sfd__h564959 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 : + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q202 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 ; - assign _theResult___fst_sfd__h564961 = - (_theResult___fst_exp__h564177 == 11'd2047) ? - _theResult___snd__h564123[56:5] : - _theResult___fst_sfd__h564958 ; - assign _theResult___fst_sfd__h564970 = - (f2_exp__h526520 == 8'd0) ? + assign _theResult___fst_sfd__h564962 = + (_theResult___fst_exp__h564178 == 11'd2047) ? + _theResult___snd__h564124[56:5] : + _theResult___fst_sfd__h564959 ; + assign _theResult___fst_sfd__h564971 = + (f2_exp__h526521 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ? - _theResult___snd_fst_sfd__h546529 : - _theResult___fst_sfd__h530695) : + _theResult___snd_fst_sfd__h546530 : + _theResult___fst_sfd__h530696) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ? - _theResult___snd_fst_sfd__h564964 : - _theResult___fst_sfd__h530695) ; - assign _theResult___fst_sfd__h564976 = - ((f2_exp__h526520 == 8'd255 || f2_exp__h526520 == 8'd0) && - f2_sfd__h526521 == 23'd0) ? + _theResult___snd_fst_sfd__h564965 : + _theResult___fst_sfd__h530696) ; + assign _theResult___fst_sfd__h564977 = + ((f2_exp__h526521 == 8'd255 || f2_exp__h526521 == 8'd0) && + f2_sfd__h526522 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h564970 ; - assign _theResult___fst_sfd__h569999 = + _theResult___fst_sfd__h564971 ; + assign _theResult___fst_sfd__h570000 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 ; - assign _theResult___fst_sfd__h585827 = + assign _theResult___fst_sfd__h585828 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 : + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 ; - assign _theResult___fst_sfd__h585830 = - (_theResult___fst_exp__h585071 == 11'd2047) ? - _theResult___snd__h585022[56:5] : - _theResult___fst_sfd__h585827 ; - assign _theResult___fst_sfd__h595478 = + assign _theResult___fst_sfd__h585831 = + (_theResult___fst_exp__h585072 == 11'd2047) ? + _theResult___snd__h585023[56:5] : + _theResult___fst_sfd__h585828 ; + assign _theResult___fst_sfd__h595479 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 : + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 ; - assign _theResult___fst_sfd__h595481 = - (_theResult___fst_exp__h594648 == 11'd2047) ? - sfdin__h594642[56:5] : - _theResult___fst_sfd__h595478 ; - assign _theResult___fst_sfd__h604262 = + assign _theResult___fst_sfd__h595482 = + (_theResult___fst_exp__h594649 == 11'd2047) ? + sfdin__h594643[56:5] : + _theResult___fst_sfd__h595479 ; + assign _theResult___fst_sfd__h604263 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 : + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 ; - assign _theResult___fst_sfd__h604265 = - (_theResult___fst_exp__h603481 == 11'd2047) ? - _theResult___snd__h603427[56:5] : - _theResult___fst_sfd__h604262 ; - assign _theResult___fst_sfd__h604274 = - (f3_exp__h565824 == 8'd0) ? + assign _theResult___fst_sfd__h604266 = + (_theResult___fst_exp__h603482 == 11'd2047) ? + _theResult___snd__h603428[56:5] : + _theResult___fst_sfd__h604263 ; + assign _theResult___fst_sfd__h604275 = + (f3_exp__h565825 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ? - _theResult___snd_fst_sfd__h585833 : - _theResult___fst_sfd__h569999) : + _theResult___snd_fst_sfd__h585834 : + _theResult___fst_sfd__h570000) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ? - _theResult___snd_fst_sfd__h604268 : - _theResult___fst_sfd__h569999) ; - assign _theResult___fst_sfd__h604280 = - ((f3_exp__h565824 == 8'd255 || f3_exp__h565824 == 8'd0) && - f3_sfd__h565825 == 23'd0) ? + _theResult___snd_fst_sfd__h604269 : + _theResult___fst_sfd__h570000) ; + assign _theResult___fst_sfd__h604281 = + ((f3_exp__h565825 == 8'd255 || f3_exp__h565825 == 8'd0) && + f3_sfd__h565826 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h604274 ; - assign _theResult___sfd__h359363 = - sfd__h358938[24] ? - ((_theResult___fst_exp__h358846 == 8'd254) ? + _theResult___fst_sfd__h604275 ; + assign _theResult___sfd__h359364 = + sfd__h358939[24] ? + ((_theResult___fst_exp__h358847 == 8'd254) ? 23'd0 : - sfd__h358938[23:1]) : - sfd__h358938[22:0] ; - assign _theResult___sfd__h367945 = - sfd__h367520[24] ? - ((_theResult___fst_exp__h367502 == 8'd254) ? + sfd__h358939[23:1]) : + sfd__h358939[22:0] ; + assign _theResult___sfd__h367946 = + sfd__h367521[24] ? + ((_theResult___fst_exp__h367503 == 8'd254) ? 23'd0 : - sfd__h367520[23:1]) : - sfd__h367520[22:0] ; - assign _theResult___sfd__h377129 = - sfd__h376704[24] ? - ((_theResult___fst_exp__h376612 == 8'd254) ? + sfd__h367521[23:1]) : + sfd__h367521[22:0] ; + assign _theResult___sfd__h377130 = + sfd__h376705[24] ? + ((_theResult___fst_exp__h376613 == 8'd254) ? 23'd0 : - sfd__h376704[23:1]) : - sfd__h376704[22:0] ; - assign _theResult___sfd__h385765 = - sfd__h385316[24] ? - ((_theResult___fst_exp__h385297 == 8'd254) ? + sfd__h376705[23:1]) : + sfd__h376705[22:0] ; + assign _theResult___sfd__h385766 = + sfd__h385317[24] ? + ((_theResult___fst_exp__h385298 == 8'd254) ? 23'd0 : - sfd__h385316[23:1]) : - sfd__h385316[22:0] ; - assign _theResult___sfd__h385867 = + sfd__h385317[23:1]) : + sfd__h385317[22:0] ; + assign _theResult___sfd__h385868 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h343080 : - _theResult___fst_sfd__h385861 ; - assign _theResult___sfd__h405060 = - sfd__h404635[24] ? - ((_theResult___fst_exp__h404543 == 8'd254) ? + _theResult___snd_fst_sfd__h343081 : + _theResult___fst_sfd__h385862 ; + assign _theResult___sfd__h405061 = + sfd__h404636[24] ? + ((_theResult___fst_exp__h404544 == 8'd254) ? 23'd0 : - sfd__h404635[23:1]) : - sfd__h404635[22:0] ; - assign _theResult___sfd__h413642 = - sfd__h413217[24] ? - ((_theResult___fst_exp__h413199 == 8'd254) ? + sfd__h404636[23:1]) : + sfd__h404636[22:0] ; + assign _theResult___sfd__h413643 = + sfd__h413218[24] ? + ((_theResult___fst_exp__h413200 == 8'd254) ? 23'd0 : - sfd__h413217[23:1]) : - sfd__h413217[22:0] ; - assign _theResult___sfd__h422826 = - sfd__h422401[24] ? - ((_theResult___fst_exp__h422309 == 8'd254) ? + sfd__h413218[23:1]) : + sfd__h413218[22:0] ; + assign _theResult___sfd__h422827 = + sfd__h422402[24] ? + ((_theResult___fst_exp__h422310 == 8'd254) ? 23'd0 : - sfd__h422401[23:1]) : - sfd__h422401[22:0] ; - assign _theResult___sfd__h431462 = - sfd__h431013[24] ? - ((_theResult___fst_exp__h430994 == 8'd254) ? + sfd__h422402[23:1]) : + sfd__h422402[22:0] ; + assign _theResult___sfd__h431463 = + sfd__h431014[24] ? + ((_theResult___fst_exp__h430995 == 8'd254) ? 23'd0 : - sfd__h431013[23:1]) : - sfd__h431013[22:0] ; - assign _theResult___sfd__h431564 = + sfd__h431014[23:1]) : + sfd__h431014[22:0] ; + assign _theResult___sfd__h431565 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h388782 : - _theResult___fst_sfd__h431558 ; - assign _theResult___sfd__h450755 = - sfd__h450330[24] ? - ((_theResult___fst_exp__h450238 == 8'd254) ? + _theResult___snd_fst_sfd__h388783 : + _theResult___fst_sfd__h431559 ; + assign _theResult___sfd__h450756 = + sfd__h450331[24] ? + ((_theResult___fst_exp__h450239 == 8'd254) ? 23'd0 : - sfd__h450330[23:1]) : - sfd__h450330[22:0] ; - assign _theResult___sfd__h459337 = - sfd__h458912[24] ? - ((_theResult___fst_exp__h458894 == 8'd254) ? + sfd__h450331[23:1]) : + sfd__h450331[22:0] ; + assign _theResult___sfd__h459338 = + sfd__h458913[24] ? + ((_theResult___fst_exp__h458895 == 8'd254) ? 23'd0 : - sfd__h458912[23:1]) : - sfd__h458912[22:0] ; - assign _theResult___sfd__h468521 = - sfd__h468096[24] ? - ((_theResult___fst_exp__h468004 == 8'd254) ? + sfd__h458913[23:1]) : + sfd__h458913[22:0] ; + assign _theResult___sfd__h468522 = + sfd__h468097[24] ? + ((_theResult___fst_exp__h468005 == 8'd254) ? 23'd0 : - sfd__h468096[23:1]) : - sfd__h468096[22:0] ; - assign _theResult___sfd__h477157 = - sfd__h476708[24] ? - ((_theResult___fst_exp__h476689 == 8'd254) ? + sfd__h468097[23:1]) : + sfd__h468097[22:0] ; + assign _theResult___sfd__h477158 = + sfd__h476709[24] ? + ((_theResult___fst_exp__h476690 == 8'd254) ? 23'd0 : - sfd__h476708[23:1]) : - sfd__h476708[22:0] ; - assign _theResult___sfd__h477259 = + sfd__h476709[23:1]) : + sfd__h476709[22:0] ; + assign _theResult___sfd__h477260 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h434477 : - _theResult___fst_sfd__h477253 ; - assign _theResult___sfd__h507570 = - sfd__h506932[53] ? - ((_theResult___fst_exp__h506914 == 11'd2046) ? + _theResult___snd_fst_sfd__h434478 : + _theResult___fst_sfd__h477254 ; + assign _theResult___sfd__h507571 = + sfd__h506933[53] ? + ((_theResult___fst_exp__h506915 == 11'd2046) ? 52'd0 : - sfd__h506932[52:1]) : - sfd__h506932[51:0] ; - assign _theResult___sfd__h517221 = - sfd__h516583[53] ? - ((_theResult___fst_exp__h516491 == 11'd2046) ? + sfd__h506933[52:1]) : + sfd__h506933[51:0] ; + assign _theResult___sfd__h517222 = + sfd__h516584[53] ? + ((_theResult___fst_exp__h516492 == 11'd2046) ? 52'd0 : - sfd__h516583[52:1]) : - sfd__h516583[51:0] ; - assign _theResult___sfd__h526005 = - sfd__h525343[53] ? - ((_theResult___fst_exp__h525324 == 11'd2046) ? + sfd__h516584[52:1]) : + sfd__h516584[51:0] ; + assign _theResult___sfd__h526006 = + sfd__h525344[53] ? + ((_theResult___fst_exp__h525325 == 11'd2046) ? 52'd0 : - sfd__h525343[52:1]) : - sfd__h525343[51:0] ; - assign _theResult___sfd__h546423 = - sfd__h545785[53] ? - ((_theResult___fst_exp__h545767 == 11'd2046) ? + sfd__h525344[52:1]) : + sfd__h525344[51:0] ; + assign _theResult___sfd__h546424 = + sfd__h545786[53] ? + ((_theResult___fst_exp__h545768 == 11'd2046) ? 52'd0 : - sfd__h545785[52:1]) : - sfd__h545785[51:0] ; - assign _theResult___sfd__h556074 = - sfd__h555436[53] ? - ((_theResult___fst_exp__h555344 == 11'd2046) ? + sfd__h545786[52:1]) : + sfd__h545786[51:0] ; + assign _theResult___sfd__h556075 = + sfd__h555437[53] ? + ((_theResult___fst_exp__h555345 == 11'd2046) ? 52'd0 : - sfd__h555436[52:1]) : - sfd__h555436[51:0] ; - assign _theResult___sfd__h564858 = - sfd__h564196[53] ? - ((_theResult___fst_exp__h564177 == 11'd2046) ? + sfd__h555437[52:1]) : + sfd__h555437[51:0] ; + assign _theResult___sfd__h564859 = + sfd__h564197[53] ? + ((_theResult___fst_exp__h564178 == 11'd2046) ? 52'd0 : - sfd__h564196[52:1]) : - sfd__h564196[51:0] ; - assign _theResult___sfd__h585727 = - sfd__h585089[53] ? - ((_theResult___fst_exp__h585071 == 11'd2046) ? + sfd__h564197[52:1]) : + sfd__h564197[51:0] ; + assign _theResult___sfd__h585728 = + sfd__h585090[53] ? + ((_theResult___fst_exp__h585072 == 11'd2046) ? 52'd0 : - sfd__h585089[52:1]) : - sfd__h585089[51:0] ; - assign _theResult___sfd__h595378 = - sfd__h594740[53] ? - ((_theResult___fst_exp__h594648 == 11'd2046) ? + sfd__h585090[52:1]) : + sfd__h585090[51:0] ; + assign _theResult___sfd__h595379 = + sfd__h594741[53] ? + ((_theResult___fst_exp__h594649 == 11'd2046) ? 52'd0 : - sfd__h594740[52:1]) : - sfd__h594740[51:0] ; - assign _theResult___sfd__h604162 = - sfd__h603500[53] ? - ((_theResult___fst_exp__h603481 == 11'd2046) ? + sfd__h594741[52:1]) : + sfd__h594741[51:0] ; + assign _theResult___sfd__h604163 = + sfd__h603501[53] ? + ((_theResult___fst_exp__h603482 == 11'd2046) ? 52'd0 : - sfd__h603500[52:1]) : - sfd__h603500[51:0] ; - assign _theResult___snd__h358857 = { _theResult____h350735[55:0], 1'd0 } ; - assign _theResult___snd__h358868 = - (!_theResult____h350735[56] && _theResult____h350735[55]) ? - _theResult___snd__h358870 : - _theResult___snd__h358880 ; - assign _theResult___snd__h358870 = { _theResult____h350735[54:0], 2'd0 } ; - assign _theResult___snd__h358880 = - (!_theResult____h350735[56] && !_theResult____h350735[55] && - !_theResult____h350735[54] && - !_theResult____h350735[53] && - !_theResult____h350735[52] && - !_theResult____h350735[51] && - !_theResult____h350735[50] && - !_theResult____h350735[49] && - !_theResult____h350735[48] && - !_theResult____h350735[47] && - !_theResult____h350735[46] && - !_theResult____h350735[45] && - !_theResult____h350735[44] && - !_theResult____h350735[43] && - !_theResult____h350735[42] && - !_theResult____h350735[41] && - !_theResult____h350735[40] && - !_theResult____h350735[39] && - !_theResult____h350735[38] && - !_theResult____h350735[37] && - !_theResult____h350735[36] && - !_theResult____h350735[35] && - !_theResult____h350735[34] && - !_theResult____h350735[33] && - !_theResult____h350735[32] && - !_theResult____h350735[31] && - !_theResult____h350735[30] && - !_theResult____h350735[29] && - !_theResult____h350735[28] && - !_theResult____h350735[27] && - !_theResult____h350735[26] && - !_theResult____h350735[25] && - !_theResult____h350735[24] && - !_theResult____h350735[23] && - !_theResult____h350735[22] && - !_theResult____h350735[21] && - !_theResult____h350735[20] && - !_theResult____h350735[19] && - !_theResult____h350735[18] && - !_theResult____h350735[17] && - !_theResult____h350735[16] && - !_theResult____h350735[15] && - !_theResult____h350735[14] && - !_theResult____h350735[13] && - !_theResult____h350735[12] && - !_theResult____h350735[11] && - !_theResult____h350735[10] && - !_theResult____h350735[9] && - !_theResult____h350735[8] && - !_theResult____h350735[7] && - !_theResult____h350735[6] && - !_theResult____h350735[5] && - !_theResult____h350735[4] && - !_theResult____h350735[3] && - !_theResult____h350735[2] && - !_theResult____h350735[1] && - !_theResult____h350735[0]) ? - _theResult____h350735 : - _theResult___snd__h358886 ; - assign _theResult___snd__h358886 = + sfd__h603501[52:1]) : + sfd__h603501[51:0] ; + assign _theResult___snd__h358858 = { _theResult____h350736[55:0], 1'd0 } ; + assign _theResult___snd__h358869 = + (!_theResult____h350736[56] && _theResult____h350736[55]) ? + _theResult___snd__h358871 : + _theResult___snd__h358881 ; + assign _theResult___snd__h358871 = { _theResult____h350736[54:0], 2'd0 } ; + assign _theResult___snd__h358881 = + (!_theResult____h350736[56] && !_theResult____h350736[55] && + !_theResult____h350736[54] && + !_theResult____h350736[53] && + !_theResult____h350736[52] && + !_theResult____h350736[51] && + !_theResult____h350736[50] && + !_theResult____h350736[49] && + !_theResult____h350736[48] && + !_theResult____h350736[47] && + !_theResult____h350736[46] && + !_theResult____h350736[45] && + !_theResult____h350736[44] && + !_theResult____h350736[43] && + !_theResult____h350736[42] && + !_theResult____h350736[41] && + !_theResult____h350736[40] && + !_theResult____h350736[39] && + !_theResult____h350736[38] && + !_theResult____h350736[37] && + !_theResult____h350736[36] && + !_theResult____h350736[35] && + !_theResult____h350736[34] && + !_theResult____h350736[33] && + !_theResult____h350736[32] && + !_theResult____h350736[31] && + !_theResult____h350736[30] && + !_theResult____h350736[29] && + !_theResult____h350736[28] && + !_theResult____h350736[27] && + !_theResult____h350736[26] && + !_theResult____h350736[25] && + !_theResult____h350736[24] && + !_theResult____h350736[23] && + !_theResult____h350736[22] && + !_theResult____h350736[21] && + !_theResult____h350736[20] && + !_theResult____h350736[19] && + !_theResult____h350736[18] && + !_theResult____h350736[17] && + !_theResult____h350736[16] && + !_theResult____h350736[15] && + !_theResult____h350736[14] && + !_theResult____h350736[13] && + !_theResult____h350736[12] && + !_theResult____h350736[11] && + !_theResult____h350736[10] && + !_theResult____h350736[9] && + !_theResult____h350736[8] && + !_theResult____h350736[7] && + !_theResult____h350736[6] && + !_theResult____h350736[5] && + !_theResult____h350736[4] && + !_theResult____h350736[3] && + !_theResult____h350736[2] && + !_theResult____h350736[1] && + !_theResult____h350736[0]) ? + _theResult____h350736 : + _theResult___snd__h358887 ; + assign _theResult___snd__h358887 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0], 2'd0 } ; - assign _theResult___snd__h358909 = - _theResult____h350735 << + assign _theResult___snd__h358910 = + _theResult____h350736 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 ; - assign _theResult___snd__h367453 = + assign _theResult___snd__h367454 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h367462 : - _theResult___snd__h367455 ; - assign _theResult___snd__h367455 = + _theResult___snd__h367463 : + _theResult___snd__h367456 ; + assign _theResult___snd__h367456 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h367462 = + assign _theResult___snd__h367463 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h343130 : - _theResult___snd__h367468 ; - assign _theResult___snd__h367468 = + sfd__h343131 : + _theResult___snd__h367469 ; + assign _theResult___snd__h367469 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0], 2'd0 } ; - assign _theResult___snd__h367491 = - sfd__h343130 << + assign _theResult___snd__h367492 = + sfd__h343131 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 ; - assign _theResult___snd__h376623 = { _theResult____h368374[55:0], 1'd0 } ; - assign _theResult___snd__h376634 = - (!_theResult____h368374[56] && _theResult____h368374[55]) ? - _theResult___snd__h376636 : - _theResult___snd__h376646 ; - assign _theResult___snd__h376636 = { _theResult____h368374[54:0], 2'd0 } ; - assign _theResult___snd__h376646 = - (!_theResult____h368374[56] && !_theResult____h368374[55] && - !_theResult____h368374[54] && - !_theResult____h368374[53] && - !_theResult____h368374[52] && - !_theResult____h368374[51] && - !_theResult____h368374[50] && - !_theResult____h368374[49] && - !_theResult____h368374[48] && - !_theResult____h368374[47] && - !_theResult____h368374[46] && - !_theResult____h368374[45] && - !_theResult____h368374[44] && - !_theResult____h368374[43] && - !_theResult____h368374[42] && - !_theResult____h368374[41] && - !_theResult____h368374[40] && - !_theResult____h368374[39] && - !_theResult____h368374[38] && - !_theResult____h368374[37] && - !_theResult____h368374[36] && - !_theResult____h368374[35] && - !_theResult____h368374[34] && - !_theResult____h368374[33] && - !_theResult____h368374[32] && - !_theResult____h368374[31] && - !_theResult____h368374[30] && - !_theResult____h368374[29] && - !_theResult____h368374[28] && - !_theResult____h368374[27] && - !_theResult____h368374[26] && - !_theResult____h368374[25] && - !_theResult____h368374[24] && - !_theResult____h368374[23] && - !_theResult____h368374[22] && - !_theResult____h368374[21] && - !_theResult____h368374[20] && - !_theResult____h368374[19] && - !_theResult____h368374[18] && - !_theResult____h368374[17] && - !_theResult____h368374[16] && - !_theResult____h368374[15] && - !_theResult____h368374[14] && - !_theResult____h368374[13] && - !_theResult____h368374[12] && - !_theResult____h368374[11] && - !_theResult____h368374[10] && - !_theResult____h368374[9] && - !_theResult____h368374[8] && - !_theResult____h368374[7] && - !_theResult____h368374[6] && - !_theResult____h368374[5] && - !_theResult____h368374[4] && - !_theResult____h368374[3] && - !_theResult____h368374[2] && - !_theResult____h368374[1] && - !_theResult____h368374[0]) ? - _theResult____h368374 : - _theResult___snd__h376652 ; - assign _theResult___snd__h376652 = + assign _theResult___snd__h376624 = { _theResult____h368375[55:0], 1'd0 } ; + assign _theResult___snd__h376635 = + (!_theResult____h368375[56] && _theResult____h368375[55]) ? + _theResult___snd__h376637 : + _theResult___snd__h376647 ; + assign _theResult___snd__h376637 = { _theResult____h368375[54:0], 2'd0 } ; + assign _theResult___snd__h376647 = + (!_theResult____h368375[56] && !_theResult____h368375[55] && + !_theResult____h368375[54] && + !_theResult____h368375[53] && + !_theResult____h368375[52] && + !_theResult____h368375[51] && + !_theResult____h368375[50] && + !_theResult____h368375[49] && + !_theResult____h368375[48] && + !_theResult____h368375[47] && + !_theResult____h368375[46] && + !_theResult____h368375[45] && + !_theResult____h368375[44] && + !_theResult____h368375[43] && + !_theResult____h368375[42] && + !_theResult____h368375[41] && + !_theResult____h368375[40] && + !_theResult____h368375[39] && + !_theResult____h368375[38] && + !_theResult____h368375[37] && + !_theResult____h368375[36] && + !_theResult____h368375[35] && + !_theResult____h368375[34] && + !_theResult____h368375[33] && + !_theResult____h368375[32] && + !_theResult____h368375[31] && + !_theResult____h368375[30] && + !_theResult____h368375[29] && + !_theResult____h368375[28] && + !_theResult____h368375[27] && + !_theResult____h368375[26] && + !_theResult____h368375[25] && + !_theResult____h368375[24] && + !_theResult____h368375[23] && + !_theResult____h368375[22] && + !_theResult____h368375[21] && + !_theResult____h368375[20] && + !_theResult____h368375[19] && + !_theResult____h368375[18] && + !_theResult____h368375[17] && + !_theResult____h368375[16] && + !_theResult____h368375[15] && + !_theResult____h368375[14] && + !_theResult____h368375[13] && + !_theResult____h368375[12] && + !_theResult____h368375[11] && + !_theResult____h368375[10] && + !_theResult____h368375[9] && + !_theResult____h368375[8] && + !_theResult____h368375[7] && + !_theResult____h368375[6] && + !_theResult____h368375[5] && + !_theResult____h368375[4] && + !_theResult____h368375[3] && + !_theResult____h368375[2] && + !_theResult____h368375[1] && + !_theResult____h368375[0]) ? + _theResult____h368375 : + _theResult___snd__h376653 ; + assign _theResult___snd__h376653 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31[54:0], 2'd0 } ; - assign _theResult___snd__h376675 = - _theResult____h368374 << + assign _theResult___snd__h376676 = + _theResult____h368375 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 ; - assign _theResult___snd__h385243 = + assign _theResult___snd__h385244 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h385257 : - _theResult___snd__h367455 ; - assign _theResult___snd__h385257 = + _theResult___snd__h385258 : + _theResult___snd__h367456 ; + assign _theResult___snd__h385258 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ? - sfd__h343130 : - _theResult___snd__h385263 ; - assign _theResult___snd__h385263 = + sfd__h343131 : + _theResult___snd__h385264 ; + assign _theResult___snd__h385264 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36[54:0], 2'd0 } ; - assign _theResult___snd__h385281 = - sfd__h343130 << + assign _theResult___snd__h385282 = + sfd__h343131 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968) ; - assign _theResult___snd__h404554 = { _theResult____h396434[55:0], 1'd0 } ; - assign _theResult___snd__h404565 = - (!_theResult____h396434[56] && _theResult____h396434[55]) ? - _theResult___snd__h404567 : - _theResult___snd__h404577 ; - assign _theResult___snd__h404567 = { _theResult____h396434[54:0], 2'd0 } ; - assign _theResult___snd__h404577 = - (!_theResult____h396434[56] && !_theResult____h396434[55] && - !_theResult____h396434[54] && - !_theResult____h396434[53] && - !_theResult____h396434[52] && - !_theResult____h396434[51] && - !_theResult____h396434[50] && - !_theResult____h396434[49] && - !_theResult____h396434[48] && - !_theResult____h396434[47] && - !_theResult____h396434[46] && - !_theResult____h396434[45] && - !_theResult____h396434[44] && - !_theResult____h396434[43] && - !_theResult____h396434[42] && - !_theResult____h396434[41] && - !_theResult____h396434[40] && - !_theResult____h396434[39] && - !_theResult____h396434[38] && - !_theResult____h396434[37] && - !_theResult____h396434[36] && - !_theResult____h396434[35] && - !_theResult____h396434[34] && - !_theResult____h396434[33] && - !_theResult____h396434[32] && - !_theResult____h396434[31] && - !_theResult____h396434[30] && - !_theResult____h396434[29] && - !_theResult____h396434[28] && - !_theResult____h396434[27] && - !_theResult____h396434[26] && - !_theResult____h396434[25] && - !_theResult____h396434[24] && - !_theResult____h396434[23] && - !_theResult____h396434[22] && - !_theResult____h396434[21] && - !_theResult____h396434[20] && - !_theResult____h396434[19] && - !_theResult____h396434[18] && - !_theResult____h396434[17] && - !_theResult____h396434[16] && - !_theResult____h396434[15] && - !_theResult____h396434[14] && - !_theResult____h396434[13] && - !_theResult____h396434[12] && - !_theResult____h396434[11] && - !_theResult____h396434[10] && - !_theResult____h396434[9] && - !_theResult____h396434[8] && - !_theResult____h396434[7] && - !_theResult____h396434[6] && - !_theResult____h396434[5] && - !_theResult____h396434[4] && - !_theResult____h396434[3] && - !_theResult____h396434[2] && - !_theResult____h396434[1] && - !_theResult____h396434[0]) ? - _theResult____h396434 : - _theResult___snd__h404583 ; - assign _theResult___snd__h404583 = + assign _theResult___snd__h404555 = { _theResult____h396435[55:0], 1'd0 } ; + assign _theResult___snd__h404566 = + (!_theResult____h396435[56] && _theResult____h396435[55]) ? + _theResult___snd__h404568 : + _theResult___snd__h404578 ; + assign _theResult___snd__h404568 = { _theResult____h396435[54:0], 2'd0 } ; + assign _theResult___snd__h404578 = + (!_theResult____h396435[56] && !_theResult____h396435[55] && + !_theResult____h396435[54] && + !_theResult____h396435[53] && + !_theResult____h396435[52] && + !_theResult____h396435[51] && + !_theResult____h396435[50] && + !_theResult____h396435[49] && + !_theResult____h396435[48] && + !_theResult____h396435[47] && + !_theResult____h396435[46] && + !_theResult____h396435[45] && + !_theResult____h396435[44] && + !_theResult____h396435[43] && + !_theResult____h396435[42] && + !_theResult____h396435[41] && + !_theResult____h396435[40] && + !_theResult____h396435[39] && + !_theResult____h396435[38] && + !_theResult____h396435[37] && + !_theResult____h396435[36] && + !_theResult____h396435[35] && + !_theResult____h396435[34] && + !_theResult____h396435[33] && + !_theResult____h396435[32] && + !_theResult____h396435[31] && + !_theResult____h396435[30] && + !_theResult____h396435[29] && + !_theResult____h396435[28] && + !_theResult____h396435[27] && + !_theResult____h396435[26] && + !_theResult____h396435[25] && + !_theResult____h396435[24] && + !_theResult____h396435[23] && + !_theResult____h396435[22] && + !_theResult____h396435[21] && + !_theResult____h396435[20] && + !_theResult____h396435[19] && + !_theResult____h396435[18] && + !_theResult____h396435[17] && + !_theResult____h396435[16] && + !_theResult____h396435[15] && + !_theResult____h396435[14] && + !_theResult____h396435[13] && + !_theResult____h396435[12] && + !_theResult____h396435[11] && + !_theResult____h396435[10] && + !_theResult____h396435[9] && + !_theResult____h396435[8] && + !_theResult____h396435[7] && + !_theResult____h396435[6] && + !_theResult____h396435[5] && + !_theResult____h396435[4] && + !_theResult____h396435[3] && + !_theResult____h396435[2] && + !_theResult____h396435[1] && + !_theResult____h396435[0]) ? + _theResult____h396435 : + _theResult___snd__h404584 ; + assign _theResult___snd__h404584 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56[54:0], 2'd0 } ; - assign _theResult___snd__h404606 = - _theResult____h396434 << + assign _theResult___snd__h404607 = + _theResult____h396435 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 ; - assign _theResult___snd__h413150 = + assign _theResult___snd__h413151 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h413159 : - _theResult___snd__h413152 ; - assign _theResult___snd__h413152 = + _theResult___snd__h413160 : + _theResult___snd__h413153 ; + assign _theResult___snd__h413153 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h413159 = + assign _theResult___snd__h413160 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h388832 : - _theResult___snd__h413165 ; - assign _theResult___snd__h413165 = + sfd__h388833 : + _theResult___snd__h413166 ; + assign _theResult___snd__h413166 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58[54:0], 2'd0 } ; - assign _theResult___snd__h413188 = - sfd__h388832 << + assign _theResult___snd__h413189 = + sfd__h388833 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 ; - assign _theResult___snd__h422320 = { _theResult____h414071[55:0], 1'd0 } ; - assign _theResult___snd__h422331 = - (!_theResult____h414071[56] && _theResult____h414071[55]) ? - _theResult___snd__h422333 : - _theResult___snd__h422343 ; - assign _theResult___snd__h422333 = { _theResult____h414071[54:0], 2'd0 } ; - assign _theResult___snd__h422343 = - (!_theResult____h414071[56] && !_theResult____h414071[55] && - !_theResult____h414071[54] && - !_theResult____h414071[53] && - !_theResult____h414071[52] && - !_theResult____h414071[51] && - !_theResult____h414071[50] && - !_theResult____h414071[49] && - !_theResult____h414071[48] && - !_theResult____h414071[47] && - !_theResult____h414071[46] && - !_theResult____h414071[45] && - !_theResult____h414071[44] && - !_theResult____h414071[43] && - !_theResult____h414071[42] && - !_theResult____h414071[41] && - !_theResult____h414071[40] && - !_theResult____h414071[39] && - !_theResult____h414071[38] && - !_theResult____h414071[37] && - !_theResult____h414071[36] && - !_theResult____h414071[35] && - !_theResult____h414071[34] && - !_theResult____h414071[33] && - !_theResult____h414071[32] && - !_theResult____h414071[31] && - !_theResult____h414071[30] && - !_theResult____h414071[29] && - !_theResult____h414071[28] && - !_theResult____h414071[27] && - !_theResult____h414071[26] && - !_theResult____h414071[25] && - !_theResult____h414071[24] && - !_theResult____h414071[23] && - !_theResult____h414071[22] && - !_theResult____h414071[21] && - !_theResult____h414071[20] && - !_theResult____h414071[19] && - !_theResult____h414071[18] && - !_theResult____h414071[17] && - !_theResult____h414071[16] && - !_theResult____h414071[15] && - !_theResult____h414071[14] && - !_theResult____h414071[13] && - !_theResult____h414071[12] && - !_theResult____h414071[11] && - !_theResult____h414071[10] && - !_theResult____h414071[9] && - !_theResult____h414071[8] && - !_theResult____h414071[7] && - !_theResult____h414071[6] && - !_theResult____h414071[5] && - !_theResult____h414071[4] && - !_theResult____h414071[3] && - !_theResult____h414071[2] && - !_theResult____h414071[1] && - !_theResult____h414071[0]) ? - _theResult____h414071 : - _theResult___snd__h422349 ; - assign _theResult___snd__h422349 = + assign _theResult___snd__h422321 = { _theResult____h414072[55:0], 1'd0 } ; + assign _theResult___snd__h422332 = + (!_theResult____h414072[56] && _theResult____h414072[55]) ? + _theResult___snd__h422334 : + _theResult___snd__h422344 ; + assign _theResult___snd__h422334 = { _theResult____h414072[54:0], 2'd0 } ; + assign _theResult___snd__h422344 = + (!_theResult____h414072[56] && !_theResult____h414072[55] && + !_theResult____h414072[54] && + !_theResult____h414072[53] && + !_theResult____h414072[52] && + !_theResult____h414072[51] && + !_theResult____h414072[50] && + !_theResult____h414072[49] && + !_theResult____h414072[48] && + !_theResult____h414072[47] && + !_theResult____h414072[46] && + !_theResult____h414072[45] && + !_theResult____h414072[44] && + !_theResult____h414072[43] && + !_theResult____h414072[42] && + !_theResult____h414072[41] && + !_theResult____h414072[40] && + !_theResult____h414072[39] && + !_theResult____h414072[38] && + !_theResult____h414072[37] && + !_theResult____h414072[36] && + !_theResult____h414072[35] && + !_theResult____h414072[34] && + !_theResult____h414072[33] && + !_theResult____h414072[32] && + !_theResult____h414072[31] && + !_theResult____h414072[30] && + !_theResult____h414072[29] && + !_theResult____h414072[28] && + !_theResult____h414072[27] && + !_theResult____h414072[26] && + !_theResult____h414072[25] && + !_theResult____h414072[24] && + !_theResult____h414072[23] && + !_theResult____h414072[22] && + !_theResult____h414072[21] && + !_theResult____h414072[20] && + !_theResult____h414072[19] && + !_theResult____h414072[18] && + !_theResult____h414072[17] && + !_theResult____h414072[16] && + !_theResult____h414072[15] && + !_theResult____h414072[14] && + !_theResult____h414072[13] && + !_theResult____h414072[12] && + !_theResult____h414072[11] && + !_theResult____h414072[10] && + !_theResult____h414072[9] && + !_theResult____h414072[8] && + !_theResult____h414072[7] && + !_theResult____h414072[6] && + !_theResult____h414072[5] && + !_theResult____h414072[4] && + !_theResult____h414072[3] && + !_theResult____h414072[2] && + !_theResult____h414072[1] && + !_theResult____h414072[0]) ? + _theResult____h414072 : + _theResult___snd__h422350 ; + assign _theResult___snd__h422350 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66[54:0], 2'd0 } ; - assign _theResult___snd__h422372 = - _theResult____h414071 << + assign _theResult___snd__h422373 = + _theResult____h414072 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 ; - assign _theResult___snd__h430940 = + assign _theResult___snd__h430941 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h430954 : - _theResult___snd__h413152 ; - assign _theResult___snd__h430954 = + _theResult___snd__h430955 : + _theResult___snd__h413153 ; + assign _theResult___snd__h430955 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ? - sfd__h388832 : - _theResult___snd__h430960 ; - assign _theResult___snd__h430960 = + sfd__h388833 : + _theResult___snd__h430961 ; + assign _theResult___snd__h430961 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71[54:0], 2'd0 } ; - assign _theResult___snd__h430978 = - sfd__h388832 << + assign _theResult___snd__h430979 = + sfd__h388833 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360) ; - assign _theResult___snd__h450249 = { _theResult____h442129[55:0], 1'd0 } ; - assign _theResult___snd__h450260 = - (!_theResult____h442129[56] && _theResult____h442129[55]) ? - _theResult___snd__h450262 : - _theResult___snd__h450272 ; - assign _theResult___snd__h450262 = { _theResult____h442129[54:0], 2'd0 } ; - assign _theResult___snd__h450272 = - (!_theResult____h442129[56] && !_theResult____h442129[55] && - !_theResult____h442129[54] && - !_theResult____h442129[53] && - !_theResult____h442129[52] && - !_theResult____h442129[51] && - !_theResult____h442129[50] && - !_theResult____h442129[49] && - !_theResult____h442129[48] && - !_theResult____h442129[47] && - !_theResult____h442129[46] && - !_theResult____h442129[45] && - !_theResult____h442129[44] && - !_theResult____h442129[43] && - !_theResult____h442129[42] && - !_theResult____h442129[41] && - !_theResult____h442129[40] && - !_theResult____h442129[39] && - !_theResult____h442129[38] && - !_theResult____h442129[37] && - !_theResult____h442129[36] && - !_theResult____h442129[35] && - !_theResult____h442129[34] && - !_theResult____h442129[33] && - !_theResult____h442129[32] && - !_theResult____h442129[31] && - !_theResult____h442129[30] && - !_theResult____h442129[29] && - !_theResult____h442129[28] && - !_theResult____h442129[27] && - !_theResult____h442129[26] && - !_theResult____h442129[25] && - !_theResult____h442129[24] && - !_theResult____h442129[23] && - !_theResult____h442129[22] && - !_theResult____h442129[21] && - !_theResult____h442129[20] && - !_theResult____h442129[19] && - !_theResult____h442129[18] && - !_theResult____h442129[17] && - !_theResult____h442129[16] && - !_theResult____h442129[15] && - !_theResult____h442129[14] && - !_theResult____h442129[13] && - !_theResult____h442129[12] && - !_theResult____h442129[11] && - !_theResult____h442129[10] && - !_theResult____h442129[9] && - !_theResult____h442129[8] && - !_theResult____h442129[7] && - !_theResult____h442129[6] && - !_theResult____h442129[5] && - !_theResult____h442129[4] && - !_theResult____h442129[3] && - !_theResult____h442129[2] && - !_theResult____h442129[1] && - !_theResult____h442129[0]) ? - _theResult____h442129 : - _theResult___snd__h450278 ; - assign _theResult___snd__h450278 = + assign _theResult___snd__h450250 = { _theResult____h442130[55:0], 1'd0 } ; + assign _theResult___snd__h450261 = + (!_theResult____h442130[56] && _theResult____h442130[55]) ? + _theResult___snd__h450263 : + _theResult___snd__h450273 ; + assign _theResult___snd__h450263 = { _theResult____h442130[54:0], 2'd0 } ; + assign _theResult___snd__h450273 = + (!_theResult____h442130[56] && !_theResult____h442130[55] && + !_theResult____h442130[54] && + !_theResult____h442130[53] && + !_theResult____h442130[52] && + !_theResult____h442130[51] && + !_theResult____h442130[50] && + !_theResult____h442130[49] && + !_theResult____h442130[48] && + !_theResult____h442130[47] && + !_theResult____h442130[46] && + !_theResult____h442130[45] && + !_theResult____h442130[44] && + !_theResult____h442130[43] && + !_theResult____h442130[42] && + !_theResult____h442130[41] && + !_theResult____h442130[40] && + !_theResult____h442130[39] && + !_theResult____h442130[38] && + !_theResult____h442130[37] && + !_theResult____h442130[36] && + !_theResult____h442130[35] && + !_theResult____h442130[34] && + !_theResult____h442130[33] && + !_theResult____h442130[32] && + !_theResult____h442130[31] && + !_theResult____h442130[30] && + !_theResult____h442130[29] && + !_theResult____h442130[28] && + !_theResult____h442130[27] && + !_theResult____h442130[26] && + !_theResult____h442130[25] && + !_theResult____h442130[24] && + !_theResult____h442130[23] && + !_theResult____h442130[22] && + !_theResult____h442130[21] && + !_theResult____h442130[20] && + !_theResult____h442130[19] && + !_theResult____h442130[18] && + !_theResult____h442130[17] && + !_theResult____h442130[16] && + !_theResult____h442130[15] && + !_theResult____h442130[14] && + !_theResult____h442130[13] && + !_theResult____h442130[12] && + !_theResult____h442130[11] && + !_theResult____h442130[10] && + !_theResult____h442130[9] && + !_theResult____h442130[8] && + !_theResult____h442130[7] && + !_theResult____h442130[6] && + !_theResult____h442130[5] && + !_theResult____h442130[4] && + !_theResult____h442130[3] && + !_theResult____h442130[2] && + !_theResult____h442130[1] && + !_theResult____h442130[0]) ? + _theResult____h442130 : + _theResult___snd__h450279 ; + assign _theResult___snd__h450279 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91[54:0], 2'd0 } ; - assign _theResult___snd__h450301 = - _theResult____h442129 << + assign _theResult___snd__h450302 = + _theResult____h442130 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 ; - assign _theResult___snd__h458845 = + assign _theResult___snd__h458846 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h458854 : - _theResult___snd__h458847 ; - assign _theResult___snd__h458847 = + _theResult___snd__h458855 : + _theResult___snd__h458848 ; + assign _theResult___snd__h458848 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h458854 = + assign _theResult___snd__h458855 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h434527 : - _theResult___snd__h458860 ; - assign _theResult___snd__h458860 = + sfd__h434528 : + _theResult___snd__h458861 ; + assign _theResult___snd__h458861 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93[54:0], 2'd0 } ; - assign _theResult___snd__h458883 = - sfd__h434527 << + assign _theResult___snd__h458884 = + sfd__h434528 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 ; - assign _theResult___snd__h468015 = { _theResult____h459766[55:0], 1'd0 } ; - assign _theResult___snd__h468026 = - (!_theResult____h459766[56] && _theResult____h459766[55]) ? - _theResult___snd__h468028 : - _theResult___snd__h468038 ; - assign _theResult___snd__h468028 = { _theResult____h459766[54:0], 2'd0 } ; - assign _theResult___snd__h468038 = - (!_theResult____h459766[56] && !_theResult____h459766[55] && - !_theResult____h459766[54] && - !_theResult____h459766[53] && - !_theResult____h459766[52] && - !_theResult____h459766[51] && - !_theResult____h459766[50] && - !_theResult____h459766[49] && - !_theResult____h459766[48] && - !_theResult____h459766[47] && - !_theResult____h459766[46] && - !_theResult____h459766[45] && - !_theResult____h459766[44] && - !_theResult____h459766[43] && - !_theResult____h459766[42] && - !_theResult____h459766[41] && - !_theResult____h459766[40] && - !_theResult____h459766[39] && - !_theResult____h459766[38] && - !_theResult____h459766[37] && - !_theResult____h459766[36] && - !_theResult____h459766[35] && - !_theResult____h459766[34] && - !_theResult____h459766[33] && - !_theResult____h459766[32] && - !_theResult____h459766[31] && - !_theResult____h459766[30] && - !_theResult____h459766[29] && - !_theResult____h459766[28] && - !_theResult____h459766[27] && - !_theResult____h459766[26] && - !_theResult____h459766[25] && - !_theResult____h459766[24] && - !_theResult____h459766[23] && - !_theResult____h459766[22] && - !_theResult____h459766[21] && - !_theResult____h459766[20] && - !_theResult____h459766[19] && - !_theResult____h459766[18] && - !_theResult____h459766[17] && - !_theResult____h459766[16] && - !_theResult____h459766[15] && - !_theResult____h459766[14] && - !_theResult____h459766[13] && - !_theResult____h459766[12] && - !_theResult____h459766[11] && - !_theResult____h459766[10] && - !_theResult____h459766[9] && - !_theResult____h459766[8] && - !_theResult____h459766[7] && - !_theResult____h459766[6] && - !_theResult____h459766[5] && - !_theResult____h459766[4] && - !_theResult____h459766[3] && - !_theResult____h459766[2] && - !_theResult____h459766[1] && - !_theResult____h459766[0]) ? - _theResult____h459766 : - _theResult___snd__h468044 ; - assign _theResult___snd__h468044 = + assign _theResult___snd__h468016 = { _theResult____h459767[55:0], 1'd0 } ; + assign _theResult___snd__h468027 = + (!_theResult____h459767[56] && _theResult____h459767[55]) ? + _theResult___snd__h468029 : + _theResult___snd__h468039 ; + assign _theResult___snd__h468029 = { _theResult____h459767[54:0], 2'd0 } ; + assign _theResult___snd__h468039 = + (!_theResult____h459767[56] && !_theResult____h459767[55] && + !_theResult____h459767[54] && + !_theResult____h459767[53] && + !_theResult____h459767[52] && + !_theResult____h459767[51] && + !_theResult____h459767[50] && + !_theResult____h459767[49] && + !_theResult____h459767[48] && + !_theResult____h459767[47] && + !_theResult____h459767[46] && + !_theResult____h459767[45] && + !_theResult____h459767[44] && + !_theResult____h459767[43] && + !_theResult____h459767[42] && + !_theResult____h459767[41] && + !_theResult____h459767[40] && + !_theResult____h459767[39] && + !_theResult____h459767[38] && + !_theResult____h459767[37] && + !_theResult____h459767[36] && + !_theResult____h459767[35] && + !_theResult____h459767[34] && + !_theResult____h459767[33] && + !_theResult____h459767[32] && + !_theResult____h459767[31] && + !_theResult____h459767[30] && + !_theResult____h459767[29] && + !_theResult____h459767[28] && + !_theResult____h459767[27] && + !_theResult____h459767[26] && + !_theResult____h459767[25] && + !_theResult____h459767[24] && + !_theResult____h459767[23] && + !_theResult____h459767[22] && + !_theResult____h459767[21] && + !_theResult____h459767[20] && + !_theResult____h459767[19] && + !_theResult____h459767[18] && + !_theResult____h459767[17] && + !_theResult____h459767[16] && + !_theResult____h459767[15] && + !_theResult____h459767[14] && + !_theResult____h459767[13] && + !_theResult____h459767[12] && + !_theResult____h459767[11] && + !_theResult____h459767[10] && + !_theResult____h459767[9] && + !_theResult____h459767[8] && + !_theResult____h459767[7] && + !_theResult____h459767[6] && + !_theResult____h459767[5] && + !_theResult____h459767[4] && + !_theResult____h459767[3] && + !_theResult____h459767[2] && + !_theResult____h459767[1] && + !_theResult____h459767[0]) ? + _theResult____h459767 : + _theResult___snd__h468045 ; + assign _theResult___snd__h468045 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101[54:0], 2'd0 } ; - assign _theResult___snd__h468067 = - _theResult____h459766 << + assign _theResult___snd__h468068 = + _theResult____h459767 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 ; - assign _theResult___snd__h476635 = + assign _theResult___snd__h476636 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h476649 : - _theResult___snd__h458847 ; - assign _theResult___snd__h476649 = + _theResult___snd__h476650 : + _theResult___snd__h458848 ; + assign _theResult___snd__h476650 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ? - sfd__h434527 : - _theResult___snd__h476655 ; - assign _theResult___snd__h476655 = + sfd__h434528 : + _theResult___snd__h476656 ; + assign _theResult___snd__h476656 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106[54:0], 2'd0 } ; - assign _theResult___snd__h476673 = - sfd__h434527 << + assign _theResult___snd__h476674 = + sfd__h434528 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752) ; - assign _theResult___snd__h506865 = - (f1_exp__h487526 == 8'd0) ? - _theResult___snd__h506874 : - _theResult___snd__h506867 ; - assign _theResult___snd__h506867 = { f1_sfd__h487527, 34'd0 } ; - assign _theResult___snd__h506874 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___snd__h506866 = + (f1_exp__h487527 == 8'd0) ? + _theResult___snd__h506875 : + _theResult___snd__h506868 ; + assign _theResult___snd__h506868 = { f1_sfd__h487528, 34'd0 } ; + assign _theResult___snd__h506875 = + (f1_exp__h487527 == 8'd0 && !f1_sfd__h487528[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h487888 : - _theResult___snd__h506880 ; - assign _theResult___snd__h506880 = + sfd__h487889 : + _theResult___snd__h506881 ; + assign _theResult___snd__h506881 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126[54:0], 2'd0 } ; - assign _theResult___snd__h506903 = - sfd__h487888 << + assign _theResult___snd__h506904 = + sfd__h487889 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 ; - assign _theResult___snd__h516502 = { _theResult____h508255[55:0], 1'd0 } ; - assign _theResult___snd__h516513 = - (!_theResult____h508255[56] && _theResult____h508255[55]) ? - _theResult___snd__h516515 : - _theResult___snd__h516525 ; - assign _theResult___snd__h516515 = { _theResult____h508255[54:0], 2'd0 } ; - assign _theResult___snd__h516525 = - (!_theResult____h508255[56] && !_theResult____h508255[55] && - !_theResult____h508255[54] && - !_theResult____h508255[53] && - !_theResult____h508255[52] && - !_theResult____h508255[51] && - !_theResult____h508255[50] && - !_theResult____h508255[49] && - !_theResult____h508255[48] && - !_theResult____h508255[47] && - !_theResult____h508255[46] && - !_theResult____h508255[45] && - !_theResult____h508255[44] && - !_theResult____h508255[43] && - !_theResult____h508255[42] && - !_theResult____h508255[41] && - !_theResult____h508255[40] && - !_theResult____h508255[39] && - !_theResult____h508255[38] && - !_theResult____h508255[37] && - !_theResult____h508255[36] && - !_theResult____h508255[35] && - !_theResult____h508255[34] && - !_theResult____h508255[33] && - !_theResult____h508255[32] && - !_theResult____h508255[31] && - !_theResult____h508255[30] && - !_theResult____h508255[29] && - !_theResult____h508255[28] && - !_theResult____h508255[27] && - !_theResult____h508255[26] && - !_theResult____h508255[25] && - !_theResult____h508255[24] && - !_theResult____h508255[23] && - !_theResult____h508255[22] && - !_theResult____h508255[21] && - !_theResult____h508255[20] && - !_theResult____h508255[19] && - !_theResult____h508255[18] && - !_theResult____h508255[17] && - !_theResult____h508255[16] && - !_theResult____h508255[15] && - !_theResult____h508255[14] && - !_theResult____h508255[13] && - !_theResult____h508255[12] && - !_theResult____h508255[11] && - !_theResult____h508255[10] && - !_theResult____h508255[9] && - !_theResult____h508255[8] && - !_theResult____h508255[7] && - !_theResult____h508255[6] && - !_theResult____h508255[5] && - !_theResult____h508255[4] && - !_theResult____h508255[3] && - !_theResult____h508255[2] && - !_theResult____h508255[1] && - !_theResult____h508255[0]) ? - _theResult____h508255 : - _theResult___snd__h516531 ; - assign _theResult___snd__h516531 = + assign _theResult___snd__h516503 = { _theResult____h508256[55:0], 1'd0 } ; + assign _theResult___snd__h516514 = + (!_theResult____h508256[56] && _theResult____h508256[55]) ? + _theResult___snd__h516516 : + _theResult___snd__h516526 ; + assign _theResult___snd__h516516 = { _theResult____h508256[54:0], 2'd0 } ; + assign _theResult___snd__h516526 = + (!_theResult____h508256[56] && !_theResult____h508256[55] && + !_theResult____h508256[54] && + !_theResult____h508256[53] && + !_theResult____h508256[52] && + !_theResult____h508256[51] && + !_theResult____h508256[50] && + !_theResult____h508256[49] && + !_theResult____h508256[48] && + !_theResult____h508256[47] && + !_theResult____h508256[46] && + !_theResult____h508256[45] && + !_theResult____h508256[44] && + !_theResult____h508256[43] && + !_theResult____h508256[42] && + !_theResult____h508256[41] && + !_theResult____h508256[40] && + !_theResult____h508256[39] && + !_theResult____h508256[38] && + !_theResult____h508256[37] && + !_theResult____h508256[36] && + !_theResult____h508256[35] && + !_theResult____h508256[34] && + !_theResult____h508256[33] && + !_theResult____h508256[32] && + !_theResult____h508256[31] && + !_theResult____h508256[30] && + !_theResult____h508256[29] && + !_theResult____h508256[28] && + !_theResult____h508256[27] && + !_theResult____h508256[26] && + !_theResult____h508256[25] && + !_theResult____h508256[24] && + !_theResult____h508256[23] && + !_theResult____h508256[22] && + !_theResult____h508256[21] && + !_theResult____h508256[20] && + !_theResult____h508256[19] && + !_theResult____h508256[18] && + !_theResult____h508256[17] && + !_theResult____h508256[16] && + !_theResult____h508256[15] && + !_theResult____h508256[14] && + !_theResult____h508256[13] && + !_theResult____h508256[12] && + !_theResult____h508256[11] && + !_theResult____h508256[10] && + !_theResult____h508256[9] && + !_theResult____h508256[8] && + !_theResult____h508256[7] && + !_theResult____h508256[6] && + !_theResult____h508256[5] && + !_theResult____h508256[4] && + !_theResult____h508256[3] && + !_theResult____h508256[2] && + !_theResult____h508256[1] && + !_theResult____h508256[0]) ? + _theResult____h508256 : + _theResult___snd__h516532 ; + assign _theResult___snd__h516532 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130[54:0], 2'd0 } ; - assign _theResult___snd__h516554 = - _theResult____h508255 << + assign _theResult___snd__h516555 = + _theResult____h508256 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 ; - assign _theResult___snd__h525270 = - (f1_exp__h487526 == 8'd0) ? - _theResult___snd__h525284 : - _theResult___snd__h506867 ; - assign _theResult___snd__h525284 = - (f1_exp__h487526 == 8'd0 && !f1_sfd__h487527[22] && + assign _theResult___snd__h525271 = + (f1_exp__h487527 == 8'd0) ? + _theResult___snd__h525285 : + _theResult___snd__h506868 ; + assign _theResult___snd__h525285 = + (f1_exp__h487527 == 8'd0 && !f1_sfd__h487528[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ? - sfd__h487888 : - _theResult___snd__h525290 ; - assign _theResult___snd__h525290 = + sfd__h487889 : + _theResult___snd__h525291 ; + assign _theResult___snd__h525291 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133[54:0], 2'd0 } ; - assign _theResult___snd__h525308 = - sfd__h487888 << + assign _theResult___snd__h525309 = + sfd__h487889 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 ; - assign _theResult___snd__h545718 = - (f2_exp__h526520 == 8'd0) ? - _theResult___snd__h545727 : - _theResult___snd__h545720 ; - assign _theResult___snd__h545720 = { f2_sfd__h526521, 34'd0 } ; - assign _theResult___snd__h545727 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___snd__h545719 = + (f2_exp__h526521 == 8'd0) ? + _theResult___snd__h545728 : + _theResult___snd__h545721 ; + assign _theResult___snd__h545721 = { f2_sfd__h526522, 34'd0 } ; + assign _theResult___snd__h545728 = + (f2_exp__h526521 == 8'd0 && !f2_sfd__h526522[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h526882 : - _theResult___snd__h545733 ; - assign _theResult___snd__h545733 = + sfd__h526883 : + _theResult___snd__h545734 ; + assign _theResult___snd__h545734 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166[54:0], 2'd0 } ; - assign _theResult___snd__h545756 = - sfd__h526882 << + assign _theResult___snd__h545757 = + sfd__h526883 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 ; - assign _theResult___snd__h555355 = { _theResult____h547108[55:0], 1'd0 } ; - assign _theResult___snd__h555366 = - (!_theResult____h547108[56] && _theResult____h547108[55]) ? - _theResult___snd__h555368 : - _theResult___snd__h555378 ; - assign _theResult___snd__h555368 = { _theResult____h547108[54:0], 2'd0 } ; - assign _theResult___snd__h555378 = - (!_theResult____h547108[56] && !_theResult____h547108[55] && - !_theResult____h547108[54] && - !_theResult____h547108[53] && - !_theResult____h547108[52] && - !_theResult____h547108[51] && - !_theResult____h547108[50] && - !_theResult____h547108[49] && - !_theResult____h547108[48] && - !_theResult____h547108[47] && - !_theResult____h547108[46] && - !_theResult____h547108[45] && - !_theResult____h547108[44] && - !_theResult____h547108[43] && - !_theResult____h547108[42] && - !_theResult____h547108[41] && - !_theResult____h547108[40] && - !_theResult____h547108[39] && - !_theResult____h547108[38] && - !_theResult____h547108[37] && - !_theResult____h547108[36] && - !_theResult____h547108[35] && - !_theResult____h547108[34] && - !_theResult____h547108[33] && - !_theResult____h547108[32] && - !_theResult____h547108[31] && - !_theResult____h547108[30] && - !_theResult____h547108[29] && - !_theResult____h547108[28] && - !_theResult____h547108[27] && - !_theResult____h547108[26] && - !_theResult____h547108[25] && - !_theResult____h547108[24] && - !_theResult____h547108[23] && - !_theResult____h547108[22] && - !_theResult____h547108[21] && - !_theResult____h547108[20] && - !_theResult____h547108[19] && - !_theResult____h547108[18] && - !_theResult____h547108[17] && - !_theResult____h547108[16] && - !_theResult____h547108[15] && - !_theResult____h547108[14] && - !_theResult____h547108[13] && - !_theResult____h547108[12] && - !_theResult____h547108[11] && - !_theResult____h547108[10] && - !_theResult____h547108[9] && - !_theResult____h547108[8] && - !_theResult____h547108[7] && - !_theResult____h547108[6] && - !_theResult____h547108[5] && - !_theResult____h547108[4] && - !_theResult____h547108[3] && - !_theResult____h547108[2] && - !_theResult____h547108[1] && - !_theResult____h547108[0]) ? - _theResult____h547108 : - _theResult___snd__h555384 ; - assign _theResult___snd__h555384 = + assign _theResult___snd__h555356 = { _theResult____h547109[55:0], 1'd0 } ; + assign _theResult___snd__h555367 = + (!_theResult____h547109[56] && _theResult____h547109[55]) ? + _theResult___snd__h555369 : + _theResult___snd__h555379 ; + assign _theResult___snd__h555369 = { _theResult____h547109[54:0], 2'd0 } ; + assign _theResult___snd__h555379 = + (!_theResult____h547109[56] && !_theResult____h547109[55] && + !_theResult____h547109[54] && + !_theResult____h547109[53] && + !_theResult____h547109[52] && + !_theResult____h547109[51] && + !_theResult____h547109[50] && + !_theResult____h547109[49] && + !_theResult____h547109[48] && + !_theResult____h547109[47] && + !_theResult____h547109[46] && + !_theResult____h547109[45] && + !_theResult____h547109[44] && + !_theResult____h547109[43] && + !_theResult____h547109[42] && + !_theResult____h547109[41] && + !_theResult____h547109[40] && + !_theResult____h547109[39] && + !_theResult____h547109[38] && + !_theResult____h547109[37] && + !_theResult____h547109[36] && + !_theResult____h547109[35] && + !_theResult____h547109[34] && + !_theResult____h547109[33] && + !_theResult____h547109[32] && + !_theResult____h547109[31] && + !_theResult____h547109[30] && + !_theResult____h547109[29] && + !_theResult____h547109[28] && + !_theResult____h547109[27] && + !_theResult____h547109[26] && + !_theResult____h547109[25] && + !_theResult____h547109[24] && + !_theResult____h547109[23] && + !_theResult____h547109[22] && + !_theResult____h547109[21] && + !_theResult____h547109[20] && + !_theResult____h547109[19] && + !_theResult____h547109[18] && + !_theResult____h547109[17] && + !_theResult____h547109[16] && + !_theResult____h547109[15] && + !_theResult____h547109[14] && + !_theResult____h547109[13] && + !_theResult____h547109[12] && + !_theResult____h547109[11] && + !_theResult____h547109[10] && + !_theResult____h547109[9] && + !_theResult____h547109[8] && + !_theResult____h547109[7] && + !_theResult____h547109[6] && + !_theResult____h547109[5] && + !_theResult____h547109[4] && + !_theResult____h547109[3] && + !_theResult____h547109[2] && + !_theResult____h547109[1] && + !_theResult____h547109[0]) ? + _theResult____h547109 : + _theResult___snd__h555385 ; + assign _theResult___snd__h555385 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170[54:0], 2'd0 } ; - assign _theResult___snd__h555407 = - _theResult____h547108 << + assign _theResult___snd__h555408 = + _theResult____h547109 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 ; - assign _theResult___snd__h564123 = - (f2_exp__h526520 == 8'd0) ? - _theResult___snd__h564137 : - _theResult___snd__h545720 ; - assign _theResult___snd__h564137 = - (f2_exp__h526520 == 8'd0 && !f2_sfd__h526521[22] && + assign _theResult___snd__h564124 = + (f2_exp__h526521 == 8'd0) ? + _theResult___snd__h564138 : + _theResult___snd__h545721 ; + assign _theResult___snd__h564138 = + (f2_exp__h526521 == 8'd0 && !f2_sfd__h526522[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ? - sfd__h526882 : - _theResult___snd__h564143 ; - assign _theResult___snd__h564143 = + sfd__h526883 : + _theResult___snd__h564144 ; + assign _theResult___snd__h564144 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173[54:0], 2'd0 } ; - assign _theResult___snd__h564161 = - sfd__h526882 << + assign _theResult___snd__h564162 = + sfd__h526883 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 ; - assign _theResult___snd__h585022 = - (f3_exp__h565824 == 8'd0) ? - _theResult___snd__h585031 : - _theResult___snd__h585024 ; - assign _theResult___snd__h585024 = { f3_sfd__h565825, 34'd0 } ; - assign _theResult___snd__h585031 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___snd__h585023 = + (f3_exp__h565825 == 8'd0) ? + _theResult___snd__h585032 : + _theResult___snd__h585025 ; + assign _theResult___snd__h585025 = { f3_sfd__h565826, 34'd0 } ; + assign _theResult___snd__h585032 = + (f3_exp__h565825 == 8'd0 && !f3_sfd__h565826[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h566186 : - _theResult___snd__h585037 ; - assign _theResult___snd__h585037 = + sfd__h566187 : + _theResult___snd__h585038 ; + assign _theResult___snd__h585038 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143[54:0], 2'd0 } ; - assign _theResult___snd__h585060 = - sfd__h566186 << + assign _theResult___snd__h585061 = + sfd__h566187 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 ; - assign _theResult___snd__h594659 = { _theResult____h586412[55:0], 1'd0 } ; - assign _theResult___snd__h594670 = - (!_theResult____h586412[56] && _theResult____h586412[55]) ? - _theResult___snd__h594672 : - _theResult___snd__h594682 ; - assign _theResult___snd__h594672 = { _theResult____h586412[54:0], 2'd0 } ; - assign _theResult___snd__h594682 = - (!_theResult____h586412[56] && !_theResult____h586412[55] && - !_theResult____h586412[54] && - !_theResult____h586412[53] && - !_theResult____h586412[52] && - !_theResult____h586412[51] && - !_theResult____h586412[50] && - !_theResult____h586412[49] && - !_theResult____h586412[48] && - !_theResult____h586412[47] && - !_theResult____h586412[46] && - !_theResult____h586412[45] && - !_theResult____h586412[44] && - !_theResult____h586412[43] && - !_theResult____h586412[42] && - !_theResult____h586412[41] && - !_theResult____h586412[40] && - !_theResult____h586412[39] && - !_theResult____h586412[38] && - !_theResult____h586412[37] && - !_theResult____h586412[36] && - !_theResult____h586412[35] && - !_theResult____h586412[34] && - !_theResult____h586412[33] && - !_theResult____h586412[32] && - !_theResult____h586412[31] && - !_theResult____h586412[30] && - !_theResult____h586412[29] && - !_theResult____h586412[28] && - !_theResult____h586412[27] && - !_theResult____h586412[26] && - !_theResult____h586412[25] && - !_theResult____h586412[24] && - !_theResult____h586412[23] && - !_theResult____h586412[22] && - !_theResult____h586412[21] && - !_theResult____h586412[20] && - !_theResult____h586412[19] && - !_theResult____h586412[18] && - !_theResult____h586412[17] && - !_theResult____h586412[16] && - !_theResult____h586412[15] && - !_theResult____h586412[14] && - !_theResult____h586412[13] && - !_theResult____h586412[12] && - !_theResult____h586412[11] && - !_theResult____h586412[10] && - !_theResult____h586412[9] && - !_theResult____h586412[8] && - !_theResult____h586412[7] && - !_theResult____h586412[6] && - !_theResult____h586412[5] && - !_theResult____h586412[4] && - !_theResult____h586412[3] && - !_theResult____h586412[2] && - !_theResult____h586412[1] && - !_theResult____h586412[0]) ? - _theResult____h586412 : - _theResult___snd__h594688 ; - assign _theResult___snd__h594688 = + assign _theResult___snd__h594660 = { _theResult____h586413[55:0], 1'd0 } ; + assign _theResult___snd__h594671 = + (!_theResult____h586413[56] && _theResult____h586413[55]) ? + _theResult___snd__h594673 : + _theResult___snd__h594683 ; + assign _theResult___snd__h594673 = { _theResult____h586413[54:0], 2'd0 } ; + assign _theResult___snd__h594683 = + (!_theResult____h586413[56] && !_theResult____h586413[55] && + !_theResult____h586413[54] && + !_theResult____h586413[53] && + !_theResult____h586413[52] && + !_theResult____h586413[51] && + !_theResult____h586413[50] && + !_theResult____h586413[49] && + !_theResult____h586413[48] && + !_theResult____h586413[47] && + !_theResult____h586413[46] && + !_theResult____h586413[45] && + !_theResult____h586413[44] && + !_theResult____h586413[43] && + !_theResult____h586413[42] && + !_theResult____h586413[41] && + !_theResult____h586413[40] && + !_theResult____h586413[39] && + !_theResult____h586413[38] && + !_theResult____h586413[37] && + !_theResult____h586413[36] && + !_theResult____h586413[35] && + !_theResult____h586413[34] && + !_theResult____h586413[33] && + !_theResult____h586413[32] && + !_theResult____h586413[31] && + !_theResult____h586413[30] && + !_theResult____h586413[29] && + !_theResult____h586413[28] && + !_theResult____h586413[27] && + !_theResult____h586413[26] && + !_theResult____h586413[25] && + !_theResult____h586413[24] && + !_theResult____h586413[23] && + !_theResult____h586413[22] && + !_theResult____h586413[21] && + !_theResult____h586413[20] && + !_theResult____h586413[19] && + !_theResult____h586413[18] && + !_theResult____h586413[17] && + !_theResult____h586413[16] && + !_theResult____h586413[15] && + !_theResult____h586413[14] && + !_theResult____h586413[13] && + !_theResult____h586413[12] && + !_theResult____h586413[11] && + !_theResult____h586413[10] && + !_theResult____h586413[9] && + !_theResult____h586413[8] && + !_theResult____h586413[7] && + !_theResult____h586413[6] && + !_theResult____h586413[5] && + !_theResult____h586413[4] && + !_theResult____h586413[3] && + !_theResult____h586413[2] && + !_theResult____h586413[1] && + !_theResult____h586413[0]) ? + _theResult____h586413 : + _theResult___snd__h594689 ; + assign _theResult___snd__h594689 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147[54:0], 2'd0 } ; - assign _theResult___snd__h594711 = - _theResult____h586412 << + assign _theResult___snd__h594712 = + _theResult____h586413 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 ; - assign _theResult___snd__h603427 = - (f3_exp__h565824 == 8'd0) ? - _theResult___snd__h603441 : - _theResult___snd__h585024 ; - assign _theResult___snd__h603441 = - (f3_exp__h565824 == 8'd0 && !f3_sfd__h565825[22] && + assign _theResult___snd__h603428 = + (f3_exp__h565825 == 8'd0) ? + _theResult___snd__h603442 : + _theResult___snd__h585025 ; + assign _theResult___snd__h603442 = + (f3_exp__h565825 == 8'd0 && !f3_sfd__h565826[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ? - sfd__h566186 : - _theResult___snd__h603447 ; - assign _theResult___snd__h603447 = + sfd__h566187 : + _theResult___snd__h603448 ; + assign _theResult___snd__h603448 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150[54:0], 2'd0 } ; - assign _theResult___snd__h603465 = - sfd__h566186 << + assign _theResult___snd__h603466 = + sfd__h566187 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 ; - assign _theResult___snd__h608921 = - b__h608373[63] ? b___1__h608986 : b__h608373 ; - assign _theResult___snd_fst_exp__h368028 = + assign _theResult___snd__h608922 = + b__h608374[63] ? b___1__h608987 : b__h608374 ; + assign _theResult___snd_fst_exp__h368029 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_exp__h359443 : - _theResult___fst_exp__h368025 ; - assign _theResult___snd_fst_exp__h385848 = + _theResult___fst_exp__h359444 : + _theResult___fst_exp__h368026 ; + assign _theResult___snd_fst_exp__h385849 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_exp__h377209 : - _theResult___fst_exp__h385845 ; - assign _theResult___snd_fst_exp__h413725 = + _theResult___fst_exp__h377210 : + _theResult___fst_exp__h385846 ; + assign _theResult___snd_fst_exp__h413726 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_exp__h405140 : - _theResult___fst_exp__h413722 ; - assign _theResult___snd_fst_exp__h431545 = + _theResult___fst_exp__h405141 : + _theResult___fst_exp__h413723 ; + assign _theResult___snd_fst_exp__h431546 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_exp__h422906 : - _theResult___fst_exp__h431542 ; - assign _theResult___snd_fst_exp__h459420 = + _theResult___fst_exp__h422907 : + _theResult___fst_exp__h431543 ; + assign _theResult___snd_fst_exp__h459421 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_exp__h450835 : - _theResult___fst_exp__h459417 ; - assign _theResult___snd_fst_exp__h477240 = + _theResult___fst_exp__h450836 : + _theResult___fst_exp__h459418 ; + assign _theResult___snd_fst_exp__h477241 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_exp__h468601 : - _theResult___fst_exp__h477237 ; - assign _theResult___snd_fst_exp__h507675 = + _theResult___fst_exp__h468602 : + _theResult___fst_exp__h477238 ; + assign _theResult___snd_fst_exp__h507676 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 11'd0 : - _theResult___fst_exp__h507672 ; - assign _theResult___snd_fst_exp__h526110 = + _theResult___fst_exp__h507673 ; + assign _theResult___snd_fst_exp__h526111 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_exp__h517323 : - _theResult___fst_exp__h526107 ; - assign _theResult___snd_fst_exp__h546528 = + _theResult___fst_exp__h517324 : + _theResult___fst_exp__h526108 ; + assign _theResult___snd_fst_exp__h546529 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 11'd0 : - _theResult___fst_exp__h546525 ; - assign _theResult___snd_fst_exp__h564963 = + _theResult___fst_exp__h546526 ; + assign _theResult___snd_fst_exp__h564964 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_exp__h556176 : - _theResult___fst_exp__h564960 ; - assign _theResult___snd_fst_exp__h585832 = + _theResult___fst_exp__h556177 : + _theResult___fst_exp__h564961 ; + assign _theResult___snd_fst_exp__h585833 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 11'd0 : - _theResult___fst_exp__h585829 ; - assign _theResult___snd_fst_exp__h604267 = + _theResult___fst_exp__h585830 ; + assign _theResult___snd_fst_exp__h604268 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_exp__h595480 : - _theResult___fst_exp__h604264 ; - assign _theResult___snd_fst_sfd__h343080 = + _theResult___fst_exp__h595481 : + _theResult___fst_exp__h604265 ; + assign _theResult___snd_fst_sfd__h343081 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h368029 = + assign _theResult___snd_fst_sfd__h368030 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ? - _theResult___fst_sfd__h359444 : - _theResult___fst_sfd__h368026 ; - assign _theResult___snd_fst_sfd__h385849 = + _theResult___fst_sfd__h359445 : + _theResult___fst_sfd__h368027 ; + assign _theResult___snd_fst_sfd__h385850 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ? - _theResult___fst_sfd__h377210 : - _theResult___fst_sfd__h385846 ; - assign _theResult___snd_fst_sfd__h388782 = + _theResult___fst_sfd__h377211 : + _theResult___fst_sfd__h385847 ; + assign _theResult___snd_fst_sfd__h388783 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h413726 = + assign _theResult___snd_fst_sfd__h413727 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ? - _theResult___fst_sfd__h405141 : - _theResult___fst_sfd__h413723 ; - assign _theResult___snd_fst_sfd__h431546 = + _theResult___fst_sfd__h405142 : + _theResult___fst_sfd__h413724 ; + assign _theResult___snd_fst_sfd__h431547 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ? - _theResult___fst_sfd__h422907 : - _theResult___fst_sfd__h431543 ; - assign _theResult___snd_fst_sfd__h434477 = + _theResult___fst_sfd__h422908 : + _theResult___fst_sfd__h431544 ; + assign _theResult___snd_fst_sfd__h434478 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h459421 = + assign _theResult___snd_fst_sfd__h459422 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ? - _theResult___fst_sfd__h450836 : - _theResult___fst_sfd__h459418 ; - assign _theResult___snd_fst_sfd__h477241 = + _theResult___fst_sfd__h450837 : + _theResult___fst_sfd__h459419 ; + assign _theResult___snd_fst_sfd__h477242 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ? - _theResult___fst_sfd__h468602 : - _theResult___fst_sfd__h477238 ; - assign _theResult___snd_fst_sfd__h487842 = - (f1_sfd__h487527 == 23'd0) ? + _theResult___fst_sfd__h468603 : + _theResult___fst_sfd__h477239 ; + assign _theResult___snd_fst_sfd__h487843 = + (f1_sfd__h487528 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h487590 ; - assign _theResult___snd_fst_sfd__h507676 = + out___1_sfd__h487591 ; + assign _theResult___snd_fst_sfd__h507677 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ? 52'd0 : - _theResult___fst_sfd__h507673 ; - assign _theResult___snd_fst_sfd__h526111 = + _theResult___fst_sfd__h507674 ; + assign _theResult___snd_fst_sfd__h526112 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ? - _theResult___fst_sfd__h517324 : - _theResult___fst_sfd__h526108 ; - assign _theResult___snd_fst_sfd__h526836 = - (f2_sfd__h526521 == 23'd0) ? + _theResult___fst_sfd__h517325 : + _theResult___fst_sfd__h526109 ; + assign _theResult___snd_fst_sfd__h526837 = + (f2_sfd__h526522 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h526584 ; - assign _theResult___snd_fst_sfd__h546529 = + out___1_sfd__h526585 ; + assign _theResult___snd_fst_sfd__h546530 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ? 52'd0 : - _theResult___fst_sfd__h546526 ; - assign _theResult___snd_fst_sfd__h564964 = + _theResult___fst_sfd__h546527 ; + assign _theResult___snd_fst_sfd__h564965 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ? - _theResult___fst_sfd__h556177 : - _theResult___fst_sfd__h564961 ; - assign _theResult___snd_fst_sfd__h566140 = - (f3_sfd__h565825 == 23'd0) ? + _theResult___fst_sfd__h556178 : + _theResult___fst_sfd__h564962 ; + assign _theResult___snd_fst_sfd__h566141 = + (f3_sfd__h565826 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h565888 ; - assign _theResult___snd_fst_sfd__h585833 = + out___1_sfd__h565889 ; + assign _theResult___snd_fst_sfd__h585834 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ? 52'd0 : - _theResult___fst_sfd__h585830 ; - assign _theResult___snd_fst_sfd__h604268 = + _theResult___fst_sfd__h585831 ; + assign _theResult___snd_fst_sfd__h604269 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ? - _theResult___fst_sfd__h595481 : - _theResult___fst_sfd__h604265 ; - assign a___1__h608534 = + _theResult___fst_sfd__h595482 : + _theResult___fst_sfd__h604266 ; + assign a___1__h608535 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 } ; - assign a___1__h608925 = 64'd0 - a__h608372 ; - assign a__h608372 = + assign a___1__h608926 = 64'd0 - a__h608373 ; + assign a__h608373 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h608534 : + a___1__h608535 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h608535 = + assign b___1__h608536 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h608986 = 64'd0 - b__h608373 ; - assign b__h608373 = + assign b___1__h608987 = 64'd0 - b__h608374 ; + assign b__h608374 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h608535 : + b___1__h608536 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h608520 = { {64{a__h608372[63]}}, a__h608372 } ; - assign b__h608596 = { {64{b__h608373[63]}}, b__h608373 } ; - assign b__h608697 = { 64'd0, a__h608372 } ; - assign b__h608709 = { 64'd0, b__h608373 } ; - assign base__h710681 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h710701 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h707758 = - commitStage_commitTrap[36] ? i__h707933 : i__h707773 ; + assign b__h608521 = { {64{a__h608373[63]}}, a__h608373 } ; + assign b__h608597 = { {64{b__h608374[63]}}, b__h608374 } ; + assign b__h608698 = { 64'd0, a__h608373 } ; + assign b__h608710 = { 64'd0, b__h608374 } ; + assign base__h710682 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h710702 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h707759 = + commitStage_commitTrap[36] ? i__h707934 : i__h707774 ; assign coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -27759,9 +27759,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565825 != 8'd255 || f3_sfd__h565826 == 23'd0) && + (f3_exp__h565825 != 8'd255 || f3_sfd__h565826 != 23'd0) && + (f3_exp__h565825 != 8'd0 || f3_sfd__h565826 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27769,9 +27769,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565825 != 8'd255 || f3_sfd__h565826 == 23'd0) && + (f3_exp__h565825 != 8'd255 || f3_sfd__h565826 != 23'd0) && + (f3_exp__h565825 != 8'd0 || f3_sfd__h565826 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27779,9 +27779,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565825 != 8'd255 || f3_sfd__h565826 == 23'd0) && + (f3_exp__h565825 != 8'd255 || f3_sfd__h565826 != 23'd0) && + (f3_exp__h565825 != 8'd0 || f3_sfd__h565826 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27789,9 +27789,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565825 != 8'd255 || f3_sfd__h565826 == 23'd0) && + (f3_exp__h565825 != 8'd255 || f3_sfd__h565826 != 23'd0) && + (f3_exp__h565825 != 8'd0 || f3_sfd__h565826 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -27799,9 +27799,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 | - ((f3_exp__h565824 != 8'd255 || f3_sfd__h565825 == 23'd0) && - (f3_exp__h565824 != 8'd255 || f3_sfd__h565825 != 23'd0) && - (f3_exp__h565824 != 8'd0 || f3_sfd__h565825 != 23'd0) && + ((f3_exp__h565825 != 8'd255 || f3_sfd__h565826 == 23'd0) && + (f3_exp__h565825 != 8'd255 || f3_sfd__h565826 != 23'd0) && + (f3_exp__h565825 != 8'd0 || f3_sfd__h565826 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -27847,7 +27847,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h258434 ; + y__h258435 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 || @@ -28206,7 +28206,7 @@ module mkCore(CLK, fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq && NOT_rob_deqPort_0_deq_data__4451_BITS_257_TO_2_ETC___d14773 ; - assign csr_addr__h661835 = + assign csr_addr__h661836 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 : 12'hCFF ; @@ -28231,7 +28231,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 || csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 || - csr_addr__h661835 == 12'h8FF) ; + csr_addr__h661836 == 12'h8FF) ; assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13605 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -28263,90 +28263,90 @@ module mkCore(CLK, _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14629) ; assign csrf_prv_reg_read__2956_ULE_1___d14592 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 = - csrf_prv_reg < csr_addr__h661835[9:8] ; - assign data79261_BITS_31_TO_0__q2 = data__h479261[31:0] ; - assign data80193_BITS_31_TO_0__q6 = data__h480193[31:0] ; - assign data___1__h479773 = - { {32{data79261_BITS_31_TO_0__q2[31]}}, - data79261_BITS_31_TO_0__q2 } ; - assign data___1__h480705 = - { {32{data80193_BITS_31_TO_0__q6[31]}}, - data80193_BITS_31_TO_0__q6 } ; - assign data__h479261 = + csrf_prv_reg < csr_addr__h661836[9:8] ; + assign data79262_BITS_31_TO_0__q2 = data__h479262[31:0] ; + assign data80194_BITS_31_TO_0__q6 = data__h480194[31:0] ; + assign data___1__h479774 = + { {32{data79262_BITS_31_TO_0__q2[31]}}, + data79262_BITS_31_TO_0__q2 } ; + assign data___1__h480706 = + { {32{data80194_BITS_31_TO_0__q6[31]}}, + data80194_BITS_31_TO_0__q6 } ; + assign data__h479262 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h480193 = + assign data__h480194 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h479957 : - x_remainder__h479958 ; - assign din_inc___2_exp__h385879 = _theResult___fst_exp__h358846 + 8'd1 ; - assign din_inc___2_exp__h385903 = _theResult___fst_exp__h367502 + 8'd1 ; - assign din_inc___2_exp__h385933 = _theResult___fst_exp__h376612 + 8'd1 ; - assign din_inc___2_exp__h385957 = _theResult___fst_exp__h385297 + 8'd1 ; - assign din_inc___2_exp__h431576 = _theResult___fst_exp__h404543 + 8'd1 ; - assign din_inc___2_exp__h431600 = _theResult___fst_exp__h413199 + 8'd1 ; - assign din_inc___2_exp__h431630 = _theResult___fst_exp__h422309 + 8'd1 ; - assign din_inc___2_exp__h431654 = _theResult___fst_exp__h430994 + 8'd1 ; - assign din_inc___2_exp__h477271 = _theResult___fst_exp__h450238 + 8'd1 ; - assign din_inc___2_exp__h477295 = _theResult___fst_exp__h458894 + 8'd1 ; - assign din_inc___2_exp__h477325 = _theResult___fst_exp__h468004 + 8'd1 ; - assign din_inc___2_exp__h477349 = _theResult___fst_exp__h476689 + 8'd1 ; - assign din_inc___2_exp__h526164 = _theResult___fst_exp__h506914 + 11'd1 ; - assign din_inc___2_exp__h526199 = _theResult___fst_exp__h516491 + 11'd1 ; - assign din_inc___2_exp__h526225 = _theResult___fst_exp__h525324 + 11'd1 ; - assign din_inc___2_exp__h565017 = _theResult___fst_exp__h545767 + 11'd1 ; - assign din_inc___2_exp__h565052 = _theResult___fst_exp__h555344 + 11'd1 ; - assign din_inc___2_exp__h565078 = _theResult___fst_exp__h564177 + 11'd1 ; - assign din_inc___2_exp__h604321 = _theResult___fst_exp__h585071 + 11'd1 ; - assign din_inc___2_exp__h604356 = _theResult___fst_exp__h594648 + 11'd1 ; - assign din_inc___2_exp__h604382 = _theResult___fst_exp__h603481 + 11'd1 ; - assign enabled_ints___1__h658439 = pend_ints__h658024 & y__h658451 ; - assign enabled_ints__h658485 = - pend_ints__h658024 & - { r1__read_BITS_9_TO_0___h658461, csrf_mideleg_1_0_reg } ; - assign f1_exp87526_MINUS_127__q128 = f1_exp__h487526 - 8'd127 ; - assign f1_exp__h487526 = + x_quotient__h479958 : + x_remainder__h479959 ; + assign din_inc___2_exp__h385880 = _theResult___fst_exp__h358847 + 8'd1 ; + assign din_inc___2_exp__h385904 = _theResult___fst_exp__h367503 + 8'd1 ; + assign din_inc___2_exp__h385934 = _theResult___fst_exp__h376613 + 8'd1 ; + assign din_inc___2_exp__h385958 = _theResult___fst_exp__h385298 + 8'd1 ; + assign din_inc___2_exp__h431577 = _theResult___fst_exp__h404544 + 8'd1 ; + assign din_inc___2_exp__h431601 = _theResult___fst_exp__h413200 + 8'd1 ; + assign din_inc___2_exp__h431631 = _theResult___fst_exp__h422310 + 8'd1 ; + assign din_inc___2_exp__h431655 = _theResult___fst_exp__h430995 + 8'd1 ; + assign din_inc___2_exp__h477272 = _theResult___fst_exp__h450239 + 8'd1 ; + assign din_inc___2_exp__h477296 = _theResult___fst_exp__h458895 + 8'd1 ; + assign din_inc___2_exp__h477326 = _theResult___fst_exp__h468005 + 8'd1 ; + assign din_inc___2_exp__h477350 = _theResult___fst_exp__h476690 + 8'd1 ; + assign din_inc___2_exp__h526165 = _theResult___fst_exp__h506915 + 11'd1 ; + assign din_inc___2_exp__h526200 = _theResult___fst_exp__h516492 + 11'd1 ; + assign din_inc___2_exp__h526226 = _theResult___fst_exp__h525325 + 11'd1 ; + assign din_inc___2_exp__h565018 = _theResult___fst_exp__h545768 + 11'd1 ; + assign din_inc___2_exp__h565053 = _theResult___fst_exp__h555345 + 11'd1 ; + assign din_inc___2_exp__h565079 = _theResult___fst_exp__h564178 + 11'd1 ; + assign din_inc___2_exp__h604322 = _theResult___fst_exp__h585072 + 11'd1 ; + assign din_inc___2_exp__h604357 = _theResult___fst_exp__h594649 + 11'd1 ; + assign din_inc___2_exp__h604383 = _theResult___fst_exp__h603482 + 11'd1 ; + assign enabled_ints___1__h658440 = pend_ints__h658025 & y__h658452 ; + assign enabled_ints__h658486 = + pend_ints__h658025 & + { r1__read_BITS_9_TO_0___h658462, csrf_mideleg_1_0_reg } ; + assign f1_exp87527_MINUS_127__q128 = f1_exp__h487527 - 8'd127 ; + assign f1_exp__h487527 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h487527 = + assign f1_sfd__h487528 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp26520_MINUS_127__q168 = f2_exp__h526520 - 8'd127 ; - assign f2_exp__h526520 = + assign f2_exp26521_MINUS_127__q168 = f2_exp__h526521 - 8'd127 ; + assign f2_exp__h526521 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h526521 = + assign f2_sfd__h526522 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp65824_MINUS_127__q145 = f3_exp__h565824 - 8'd127 ; - assign f3_exp__h565824 = + assign f3_exp65825_MINUS_127__q145 = f3_exp__h565825 - 8'd127 ; + assign f3_exp__h565825 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h565825 = + assign f3_sfd__h565826 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; - assign fallthrough_pc__h670384 = + assign fallthrough_pc__h670385 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h686130 = + assign fallthrough_pc__h686131 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; - assign fcsr_csr__read__h616233 = { 56'd0, x__h619373 } ; + assign fcsr_csr__read__h616234 = { 56'd0, x__h619374 } ; assign fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13536 = fetchStage$RDY_pipelines_0_first && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -28443,9 +28443,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h661836 != 5'd0 || - imm__h661837 != 32'd0) && - csr_addr__h661835[11:10] == 2'b11 ; + rs1__h661837 != 5'd0 || + imm__h661838 != 32'd0) && + csr_addr__h661836[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13836 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -28567,82 +28567,82 @@ module mkCore(CLK, !epochManager$checkEpoch_1_check || fetchStage$pipelines_0_canDeq && fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14043 ; - assign fflags__h722585 = + assign fflags__h722586 = NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_fst__h722532 : + y_avValue_fst__h722533 : IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 ; - assign fflags_csr__read__h616208 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h616219 = { 61'd0, csrf_frm_reg } ; - assign guard__h350745 = - { IF_sfdin58840_BIT_33_THEN_2_ELSE_0__q22[1], - { sfdin__h358840[32:0], 23'd0 } != 56'd0 } ; - assign guard__h359454 = - { IF_theResult___snd67453_BIT_33_THEN_2_ELSE_0__q24[1], - { _theResult___snd__h367453[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368384 = - { IF_sfdin76606_BIT_33_THEN_2_ELSE_0__q32[1], - { sfdin__h376606[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368982 = x__h369084 != 57'd0 ; - assign guard__h377220 = - { IF_theResult___snd85243_BIT_33_THEN_2_ELSE_0__q37[1], - { _theResult___snd__h385243[32:0], 23'd0 } != 56'd0 } ; - assign guard__h396444 = - { IF_sfdin04537_BIT_33_THEN_2_ELSE_0__q57[1], - { sfdin__h404537[32:0], 23'd0 } != 56'd0 } ; - assign guard__h405151 = - { IF_theResult___snd13150_BIT_33_THEN_2_ELSE_0__q59[1], - { _theResult___snd__h413150[32:0], 23'd0 } != 56'd0 } ; - assign guard__h414081 = - { IF_sfdin22303_BIT_33_THEN_2_ELSE_0__q67[1], - { sfdin__h422303[32:0], 23'd0 } != 56'd0 } ; - assign guard__h414679 = x__h414781 != 57'd0 ; - assign guard__h422917 = - { IF_theResult___snd30940_BIT_33_THEN_2_ELSE_0__q72[1], - { _theResult___snd__h430940[32:0], 23'd0 } != 56'd0 } ; - assign guard__h442139 = - { IF_sfdin50232_BIT_33_THEN_2_ELSE_0__q92[1], - { sfdin__h450232[32:0], 23'd0 } != 56'd0 } ; - assign guard__h450846 = - { IF_theResult___snd58845_BIT_33_THEN_2_ELSE_0__q94[1], - { _theResult___snd__h458845[32:0], 23'd0 } != 56'd0 } ; - assign guard__h459776 = - { IF_sfdin67998_BIT_33_THEN_2_ELSE_0__q102[1], - { sfdin__h467998[32:0], 23'd0 } != 56'd0 } ; - assign guard__h460374 = x__h460476 != 57'd0 ; - assign guard__h468612 = - { IF_theResult___snd76635_BIT_33_THEN_2_ELSE_0__q107[1], - { _theResult___snd__h476635[32:0], 23'd0 } != 56'd0 } ; - assign guard__h498953 = - { IF_theResult___snd06865_BIT_4_THEN_2_ELSE_0__q127[1], - { _theResult___snd__h506865[3:0], 52'd0 } != 56'd0 } ; - assign guard__h508265 = - { IF_sfdin16485_BIT_4_THEN_2_ELSE_0__q131[1], - { sfdin__h516485[3:0], 52'd0 } != 56'd0 } ; - assign guard__h508863 = x__h508963 != 57'd0 ; - assign guard__h517334 = - { IF_theResult___snd25270_BIT_4_THEN_2_ELSE_0__q134[1], - { _theResult___snd__h525270[3:0], 52'd0 } != 56'd0 } ; - assign guard__h537806 = - { IF_theResult___snd45718_BIT_4_THEN_2_ELSE_0__q167[1], - { _theResult___snd__h545718[3:0], 52'd0 } != 56'd0 } ; - assign guard__h547118 = - { IF_sfdin55338_BIT_4_THEN_2_ELSE_0__q171[1], - { sfdin__h555338[3:0], 52'd0 } != 56'd0 } ; - assign guard__h547716 = x__h547816 != 57'd0 ; - assign guard__h556187 = - { IF_theResult___snd64123_BIT_4_THEN_2_ELSE_0__q174[1], - { _theResult___snd__h564123[3:0], 52'd0 } != 56'd0 } ; - assign guard__h577110 = - { IF_theResult___snd85022_BIT_4_THEN_2_ELSE_0__q144[1], - { _theResult___snd__h585022[3:0], 52'd0 } != 56'd0 } ; - assign guard__h586422 = - { IF_sfdin94642_BIT_4_THEN_2_ELSE_0__q148[1], - { sfdin__h594642[3:0], 52'd0 } != 56'd0 } ; - assign guard__h587020 = x__h587120 != 57'd0 ; - assign guard__h595491 = - { IF_theResult___snd03427_BIT_4_THEN_2_ELSE_0__q151[1], - { _theResult___snd__h603427[3:0], 52'd0 } != 56'd0 } ; - assign idx__h689687 = + assign fflags_csr__read__h616209 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h616220 = { 61'd0, csrf_frm_reg } ; + assign guard__h350746 = + { IF_sfdin58841_BIT_33_THEN_2_ELSE_0__q22[1], + { sfdin__h358841[32:0], 23'd0 } != 56'd0 } ; + assign guard__h359455 = + { IF_theResult___snd67454_BIT_33_THEN_2_ELSE_0__q24[1], + { _theResult___snd__h367454[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368385 = + { IF_sfdin76607_BIT_33_THEN_2_ELSE_0__q32[1], + { sfdin__h376607[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368983 = x__h369085 != 57'd0 ; + assign guard__h377221 = + { IF_theResult___snd85244_BIT_33_THEN_2_ELSE_0__q37[1], + { _theResult___snd__h385244[32:0], 23'd0 } != 56'd0 } ; + assign guard__h396445 = + { IF_sfdin04538_BIT_33_THEN_2_ELSE_0__q57[1], + { sfdin__h404538[32:0], 23'd0 } != 56'd0 } ; + assign guard__h405152 = + { IF_theResult___snd13151_BIT_33_THEN_2_ELSE_0__q59[1], + { _theResult___snd__h413151[32:0], 23'd0 } != 56'd0 } ; + assign guard__h414082 = + { IF_sfdin22304_BIT_33_THEN_2_ELSE_0__q67[1], + { sfdin__h422304[32:0], 23'd0 } != 56'd0 } ; + assign guard__h414680 = x__h414782 != 57'd0 ; + assign guard__h422918 = + { IF_theResult___snd30941_BIT_33_THEN_2_ELSE_0__q72[1], + { _theResult___snd__h430941[32:0], 23'd0 } != 56'd0 } ; + assign guard__h442140 = + { IF_sfdin50233_BIT_33_THEN_2_ELSE_0__q92[1], + { sfdin__h450233[32:0], 23'd0 } != 56'd0 } ; + assign guard__h450847 = + { IF_theResult___snd58846_BIT_33_THEN_2_ELSE_0__q94[1], + { _theResult___snd__h458846[32:0], 23'd0 } != 56'd0 } ; + assign guard__h459777 = + { IF_sfdin67999_BIT_33_THEN_2_ELSE_0__q102[1], + { sfdin__h467999[32:0], 23'd0 } != 56'd0 } ; + assign guard__h460375 = x__h460477 != 57'd0 ; + assign guard__h468613 = + { IF_theResult___snd76636_BIT_33_THEN_2_ELSE_0__q107[1], + { _theResult___snd__h476636[32:0], 23'd0 } != 56'd0 } ; + assign guard__h498954 = + { IF_theResult___snd06866_BIT_4_THEN_2_ELSE_0__q127[1], + { _theResult___snd__h506866[3:0], 52'd0 } != 56'd0 } ; + assign guard__h508266 = + { IF_sfdin16486_BIT_4_THEN_2_ELSE_0__q131[1], + { sfdin__h516486[3:0], 52'd0 } != 56'd0 } ; + assign guard__h508864 = x__h508964 != 57'd0 ; + assign guard__h517335 = + { IF_theResult___snd25271_BIT_4_THEN_2_ELSE_0__q134[1], + { _theResult___snd__h525271[3:0], 52'd0 } != 56'd0 } ; + assign guard__h537807 = + { IF_theResult___snd45719_BIT_4_THEN_2_ELSE_0__q167[1], + { _theResult___snd__h545719[3:0], 52'd0 } != 56'd0 } ; + assign guard__h547119 = + { IF_sfdin55339_BIT_4_THEN_2_ELSE_0__q171[1], + { sfdin__h555339[3:0], 52'd0 } != 56'd0 } ; + assign guard__h547717 = x__h547817 != 57'd0 ; + assign guard__h556188 = + { IF_theResult___snd64124_BIT_4_THEN_2_ELSE_0__q174[1], + { _theResult___snd__h564124[3:0], 52'd0 } != 56'd0 } ; + assign guard__h577111 = + { IF_theResult___snd85023_BIT_4_THEN_2_ELSE_0__q144[1], + { _theResult___snd__h585023[3:0], 52'd0 } != 56'd0 } ; + assign guard__h586423 = + { IF_sfdin94643_BIT_4_THEN_2_ELSE_0__q148[1], + { sfdin__h594643[3:0], 52'd0 } != 56'd0 } ; + assign guard__h587021 = x__h587121 != 57'd0 ; + assign guard__h595492 = + { IF_theResult___snd03428_BIT_4_THEN_2_ELSE_0__q151[1], + { _theResult___snd__h603428[3:0], 52'd0 } != 56'd0 } ; + assign idx__h689688 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13837 || !coreFix_aluExe_0_rsAlu$canEnq || @@ -28650,24 +28650,24 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13857) && coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3547__ETC___d13549 ; - assign imm__h661837 = + assign imm__h661838 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h674092 = + assign k__h674093 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3547__ETC___d13549 ; - assign mcause_csr__read__h617875 = - { r1__read__h620836, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h617620 = - { r1__read__h620823, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h617227 = - { r1__read__h620684, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h617322 = - { r1__read__h620701, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h617446 = { r1__read__h620725, 1'b0 } ; - assign mip_csr__read__h618108 = { r1__read__h620842, 1'b0 } ; + assign mcause_csr__read__h617876 = + { r1__read__h620837, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h617621 = + { r1__read__h620824, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h617228 = + { r1__read__h620685, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h617323 = + { r1__read__h620702, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h617447 = { r1__read__h620726, 1'b0 } ; + assign mip_csr__read__h618109 = { r1__read__h620843, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -28743,410 +28743,410 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h75669 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h617079 = { r1__read__h620559, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h617528 = - { r1__read__h620818, csrf_mtvec_mode_low_reg } ; - assign n___1__h201749 = + assign msip__h75670 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h617080 = { r1__read__h620560, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h617529 = + { r1__read__h620819, csrf_mtvec_mode_low_reg } ; + assign n___1__h201750 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h200346[63:56], + x__h200347[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h200346[55:48], + x__h200347[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h200346[47:40], + x__h200347[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h200346[39:32], + x__h200347[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h200346[31:24], + x__h200347[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h200346[23:16], + x__h200347[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h200346[15:8], + x__h200347[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h200346[7:0] } ; - assign n__read__h618212 = + x__h200347[7:0] } ; + assign n__read__h618213 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h618403 = + assign n__read__h618404 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6330 = + assign n__read__h6331 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? rob$deqPort_0_deq_data[95:32] : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h719388 = + assign n__read__h719389 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h301450 = + assign next_deqP___1__h301451 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h309446 = + assign next_deqP___1__h309447 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h315727 = + assign next_deqP___1__h315728 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h323581 = + assign next_deqP___1__h323582 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h333638 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h336863 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h718598 = + assign next_deqP___1__h333639 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h336864 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h718599 = (rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954 ; - assign out___1_sfd__h487590 = { f1_sfd__h487527, 29'd0 } ; - assign out___1_sfd__h526584 = { f2_sfd__h526521, 29'd0 } ; - assign out___1_sfd__h565888 = { f3_sfd__h565825, 29'd0 } ; - assign out_exp__h359365 = - sfdin__h358840[34] ? - _theResult___exp__h359362 : - _theResult___fst_exp__h358846 ; - assign out_exp__h367947 = - _theResult___snd__h367453[34] ? - _theResult___exp__h367944 : - _theResult___fst_exp__h367502 ; - assign out_exp__h377131 = - sfdin__h376606[34] ? - _theResult___exp__h377128 : - _theResult___fst_exp__h376612 ; - assign out_exp__h385767 = - _theResult___snd__h385243[34] ? - _theResult___exp__h385764 : - _theResult___fst_exp__h385297 ; - assign out_exp__h405062 = - sfdin__h404537[34] ? - _theResult___exp__h405059 : - _theResult___fst_exp__h404543 ; - assign out_exp__h413644 = - _theResult___snd__h413150[34] ? - _theResult___exp__h413641 : - _theResult___fst_exp__h413199 ; - assign out_exp__h422828 = - sfdin__h422303[34] ? - _theResult___exp__h422825 : - _theResult___fst_exp__h422309 ; - assign out_exp__h431464 = - _theResult___snd__h430940[34] ? - _theResult___exp__h431461 : - _theResult___fst_exp__h430994 ; - assign out_exp__h450757 = - sfdin__h450232[34] ? - _theResult___exp__h450754 : - _theResult___fst_exp__h450238 ; - assign out_exp__h459339 = - _theResult___snd__h458845[34] ? - _theResult___exp__h459336 : - _theResult___fst_exp__h458894 ; - assign out_exp__h468523 = - sfdin__h467998[34] ? - _theResult___exp__h468520 : - _theResult___fst_exp__h468004 ; - assign out_exp__h477159 = - _theResult___snd__h476635[34] ? - _theResult___exp__h477156 : - _theResult___fst_exp__h476689 ; - assign out_exp__h507572 = - _theResult___snd__h506865[5] ? - _theResult___exp__h507569 : - _theResult___fst_exp__h506914 ; - assign out_exp__h517223 = - sfdin__h516485[5] ? - _theResult___exp__h517220 : - _theResult___fst_exp__h516491 ; - assign out_exp__h526007 = - _theResult___snd__h525270[5] ? - _theResult___exp__h526004 : - _theResult___fst_exp__h525324 ; - assign out_exp__h546425 = - _theResult___snd__h545718[5] ? - _theResult___exp__h546422 : - _theResult___fst_exp__h545767 ; - assign out_exp__h556076 = - sfdin__h555338[5] ? - _theResult___exp__h556073 : - _theResult___fst_exp__h555344 ; - assign out_exp__h564860 = - _theResult___snd__h564123[5] ? - _theResult___exp__h564857 : - _theResult___fst_exp__h564177 ; - assign out_exp__h585729 = - _theResult___snd__h585022[5] ? - _theResult___exp__h585726 : - _theResult___fst_exp__h585071 ; - assign out_exp__h595380 = - sfdin__h594642[5] ? - _theResult___exp__h595377 : - _theResult___fst_exp__h594648 ; - assign out_exp__h604164 = - _theResult___snd__h603427[5] ? - _theResult___exp__h604161 : - _theResult___fst_exp__h603481 ; - assign out_f_exp__h386143 = - (_theResult___exp__h385866 == 8'd255 && - _theResult___sfd__h385867 != 23'd0 || + assign out___1_sfd__h487591 = { f1_sfd__h487528, 29'd0 } ; + assign out___1_sfd__h526585 = { f2_sfd__h526522, 29'd0 } ; + assign out___1_sfd__h565889 = { f3_sfd__h565826, 29'd0 } ; + assign out_exp__h359366 = + sfdin__h358841[34] ? + _theResult___exp__h359363 : + _theResult___fst_exp__h358847 ; + assign out_exp__h367948 = + _theResult___snd__h367454[34] ? + _theResult___exp__h367945 : + _theResult___fst_exp__h367503 ; + assign out_exp__h377132 = + sfdin__h376607[34] ? + _theResult___exp__h377129 : + _theResult___fst_exp__h376613 ; + assign out_exp__h385768 = + _theResult___snd__h385244[34] ? + _theResult___exp__h385765 : + _theResult___fst_exp__h385298 ; + assign out_exp__h405063 = + sfdin__h404538[34] ? + _theResult___exp__h405060 : + _theResult___fst_exp__h404544 ; + assign out_exp__h413645 = + _theResult___snd__h413151[34] ? + _theResult___exp__h413642 : + _theResult___fst_exp__h413200 ; + assign out_exp__h422829 = + sfdin__h422304[34] ? + _theResult___exp__h422826 : + _theResult___fst_exp__h422310 ; + assign out_exp__h431465 = + _theResult___snd__h430941[34] ? + _theResult___exp__h431462 : + _theResult___fst_exp__h430995 ; + assign out_exp__h450758 = + sfdin__h450233[34] ? + _theResult___exp__h450755 : + _theResult___fst_exp__h450239 ; + assign out_exp__h459340 = + _theResult___snd__h458846[34] ? + _theResult___exp__h459337 : + _theResult___fst_exp__h458895 ; + assign out_exp__h468524 = + sfdin__h467999[34] ? + _theResult___exp__h468521 : + _theResult___fst_exp__h468005 ; + assign out_exp__h477160 = + _theResult___snd__h476636[34] ? + _theResult___exp__h477157 : + _theResult___fst_exp__h476690 ; + assign out_exp__h507573 = + _theResult___snd__h506866[5] ? + _theResult___exp__h507570 : + _theResult___fst_exp__h506915 ; + assign out_exp__h517224 = + sfdin__h516486[5] ? + _theResult___exp__h517221 : + _theResult___fst_exp__h516492 ; + assign out_exp__h526008 = + _theResult___snd__h525271[5] ? + _theResult___exp__h526005 : + _theResult___fst_exp__h525325 ; + assign out_exp__h546426 = + _theResult___snd__h545719[5] ? + _theResult___exp__h546423 : + _theResult___fst_exp__h545768 ; + assign out_exp__h556077 = + sfdin__h555339[5] ? + _theResult___exp__h556074 : + _theResult___fst_exp__h555345 ; + assign out_exp__h564861 = + _theResult___snd__h564124[5] ? + _theResult___exp__h564858 : + _theResult___fst_exp__h564178 ; + assign out_exp__h585730 = + _theResult___snd__h585023[5] ? + _theResult___exp__h585727 : + _theResult___fst_exp__h585072 ; + assign out_exp__h595381 = + sfdin__h594643[5] ? + _theResult___exp__h595378 : + _theResult___fst_exp__h594649 ; + assign out_exp__h604165 = + _theResult___snd__h603428[5] ? + _theResult___exp__h604162 : + _theResult___fst_exp__h603482 ; + assign out_f_exp__h386144 = + (_theResult___exp__h385867 == 8'd255 && + _theResult___sfd__h385868 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385857 ; - assign out_f_exp__h431840 = - (_theResult___exp__h431563 == 8'd255 && - _theResult___sfd__h431564 != 23'd0 || + _theResult___fst_exp__h385858 ; + assign out_f_exp__h431841 = + (_theResult___exp__h431564 == 8'd255 && + _theResult___sfd__h431565 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431554 ; - assign out_f_exp__h477535 = - (_theResult___exp__h477258 == 8'd255 && - _theResult___sfd__h477259 != 23'd0 || + _theResult___fst_exp__h431555 ; + assign out_f_exp__h477536 = + (_theResult___exp__h477259 == 8'd255 && + _theResult___sfd__h477260 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477249 ; - assign out_f_sfd__h386144 = - (_theResult___exp__h385866 == 8'd255 && - _theResult___sfd__h385867 != 23'd0) ? + _theResult___fst_exp__h477250 ; + assign out_f_sfd__h386145 = + (_theResult___exp__h385867 == 8'd255 && + _theResult___sfd__h385868 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h385867 ; - assign out_f_sfd__h431841 = - (_theResult___exp__h431563 == 8'd255 && - _theResult___sfd__h431564 != 23'd0) ? + _theResult___sfd__h385868 ; + assign out_f_sfd__h431842 = + (_theResult___exp__h431564 == 8'd255 && + _theResult___sfd__h431565 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h431564 ; - assign out_f_sfd__h477536 = - (_theResult___exp__h477258 == 8'd255 && - _theResult___sfd__h477259 != 23'd0) ? + _theResult___sfd__h431565 ; + assign out_f_sfd__h477537 = + (_theResult___exp__h477259 == 8'd255 && + _theResult___sfd__h477260 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h477259 ; - assign out_sfd__h359366 = - sfdin__h358840[34] ? - _theResult___sfd__h359363 : - sfdin__h358840[56:34] ; - assign out_sfd__h367948 = - _theResult___snd__h367453[34] ? - _theResult___sfd__h367945 : - _theResult___snd__h367453[56:34] ; - assign out_sfd__h377132 = - sfdin__h376606[34] ? - _theResult___sfd__h377129 : - sfdin__h376606[56:34] ; - assign out_sfd__h385768 = - _theResult___snd__h385243[34] ? - _theResult___sfd__h385765 : - _theResult___snd__h385243[56:34] ; - assign out_sfd__h405063 = - sfdin__h404537[34] ? - _theResult___sfd__h405060 : - sfdin__h404537[56:34] ; - assign out_sfd__h413645 = - _theResult___snd__h413150[34] ? - _theResult___sfd__h413642 : - _theResult___snd__h413150[56:34] ; - assign out_sfd__h422829 = - sfdin__h422303[34] ? - _theResult___sfd__h422826 : - sfdin__h422303[56:34] ; - assign out_sfd__h431465 = - _theResult___snd__h430940[34] ? - _theResult___sfd__h431462 : - _theResult___snd__h430940[56:34] ; - assign out_sfd__h450758 = - sfdin__h450232[34] ? - _theResult___sfd__h450755 : - sfdin__h450232[56:34] ; - assign out_sfd__h459340 = - _theResult___snd__h458845[34] ? - _theResult___sfd__h459337 : - _theResult___snd__h458845[56:34] ; - assign out_sfd__h468524 = - sfdin__h467998[34] ? - _theResult___sfd__h468521 : - sfdin__h467998[56:34] ; - assign out_sfd__h477160 = - _theResult___snd__h476635[34] ? - _theResult___sfd__h477157 : - _theResult___snd__h476635[56:34] ; - assign out_sfd__h507573 = - _theResult___snd__h506865[5] ? - _theResult___sfd__h507570 : - _theResult___snd__h506865[56:5] ; - assign out_sfd__h517224 = - sfdin__h516485[5] ? - _theResult___sfd__h517221 : - sfdin__h516485[56:5] ; - assign out_sfd__h526008 = - _theResult___snd__h525270[5] ? - _theResult___sfd__h526005 : - _theResult___snd__h525270[56:5] ; - assign out_sfd__h546426 = - _theResult___snd__h545718[5] ? - _theResult___sfd__h546423 : - _theResult___snd__h545718[56:5] ; - assign out_sfd__h556077 = - sfdin__h555338[5] ? - _theResult___sfd__h556074 : - sfdin__h555338[56:5] ; - assign out_sfd__h564861 = - _theResult___snd__h564123[5] ? - _theResult___sfd__h564858 : - _theResult___snd__h564123[56:5] ; - assign out_sfd__h585730 = - _theResult___snd__h585022[5] ? - _theResult___sfd__h585727 : - _theResult___snd__h585022[56:5] ; - assign out_sfd__h595381 = - sfdin__h594642[5] ? - _theResult___sfd__h595378 : - sfdin__h594642[56:5] ; - assign out_sfd__h604165 = - _theResult___snd__h603427[5] ? - _theResult___sfd__h604162 : - _theResult___snd__h603427[56:5] ; - assign pend_ints__h658024 = + _theResult___sfd__h477260 ; + assign out_sfd__h359367 = + sfdin__h358841[34] ? + _theResult___sfd__h359364 : + sfdin__h358841[56:34] ; + assign out_sfd__h367949 = + _theResult___snd__h367454[34] ? + _theResult___sfd__h367946 : + _theResult___snd__h367454[56:34] ; + assign out_sfd__h377133 = + sfdin__h376607[34] ? + _theResult___sfd__h377130 : + sfdin__h376607[56:34] ; + assign out_sfd__h385769 = + _theResult___snd__h385244[34] ? + _theResult___sfd__h385766 : + _theResult___snd__h385244[56:34] ; + assign out_sfd__h405064 = + sfdin__h404538[34] ? + _theResult___sfd__h405061 : + sfdin__h404538[56:34] ; + assign out_sfd__h413646 = + _theResult___snd__h413151[34] ? + _theResult___sfd__h413643 : + _theResult___snd__h413151[56:34] ; + assign out_sfd__h422830 = + sfdin__h422304[34] ? + _theResult___sfd__h422827 : + sfdin__h422304[56:34] ; + assign out_sfd__h431466 = + _theResult___snd__h430941[34] ? + _theResult___sfd__h431463 : + _theResult___snd__h430941[56:34] ; + assign out_sfd__h450759 = + sfdin__h450233[34] ? + _theResult___sfd__h450756 : + sfdin__h450233[56:34] ; + assign out_sfd__h459341 = + _theResult___snd__h458846[34] ? + _theResult___sfd__h459338 : + _theResult___snd__h458846[56:34] ; + assign out_sfd__h468525 = + sfdin__h467999[34] ? + _theResult___sfd__h468522 : + sfdin__h467999[56:34] ; + assign out_sfd__h477161 = + _theResult___snd__h476636[34] ? + _theResult___sfd__h477158 : + _theResult___snd__h476636[56:34] ; + assign out_sfd__h507574 = + _theResult___snd__h506866[5] ? + _theResult___sfd__h507571 : + _theResult___snd__h506866[56:5] ; + assign out_sfd__h517225 = + sfdin__h516486[5] ? + _theResult___sfd__h517222 : + sfdin__h516486[56:5] ; + assign out_sfd__h526009 = + _theResult___snd__h525271[5] ? + _theResult___sfd__h526006 : + _theResult___snd__h525271[56:5] ; + assign out_sfd__h546427 = + _theResult___snd__h545719[5] ? + _theResult___sfd__h546424 : + _theResult___snd__h545719[56:5] ; + assign out_sfd__h556078 = + sfdin__h555339[5] ? + _theResult___sfd__h556075 : + sfdin__h555339[56:5] ; + assign out_sfd__h564862 = + _theResult___snd__h564124[5] ? + _theResult___sfd__h564859 : + _theResult___snd__h564124[56:5] ; + assign out_sfd__h585731 = + _theResult___snd__h585023[5] ? + _theResult___sfd__h585728 : + _theResult___snd__h585023[56:5] ; + assign out_sfd__h595382 = + sfdin__h594643[5] ? + _theResult___sfd__h595379 : + sfdin__h594643[56:5] ; + assign out_sfd__h604166 = + _theResult___snd__h603428[5] ? + _theResult___sfd__h604163 : + _theResult___snd__h603428[56:5] ; + assign pend_ints__h658025 = { csrf_external_int_en_vec_3_read__1844_AND_csrf_ETC___d12967, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign prv__h724099 = csrf_prv_reg ; - assign prv__h724143 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h480780 = + assign prv__h724100 = csrf_prv_reg ; + assign prv__h724144 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h480781 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_12___h661705 = csrf_fs_reg ; - assign r1__read_BITS_9_TO_0___h658461 = + assign r1__read_BITS_13_TO_12___h661706 = csrf_fs_reg ; + assign r1__read_BITS_9_TO_0___h658462 = { csrf_mideleg_11_reg, 1'b0, csrf_mideleg_9_7_reg, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BIT_20___h662369 = csrf_tw_reg ; - assign r1__read__h619388 = { r1__read__h619390, csrf_ie_vec_1 } ; - assign r1__read__h619390 = { r1__read__h619392, 2'b0 } ; - assign r1__read__h619392 = { r1__read__h619394, csrf_prev_ie_vec_0 } ; - assign r1__read__h619394 = { r1__read__h619396, csrf_prev_ie_vec_1 } ; - assign r1__read__h619396 = { r1__read__h619398, 2'b0 } ; - assign r1__read__h619398 = { r1__read__h619400, csrf_spp_reg } ; - assign r1__read__h619400 = { r1__read__h619402, 4'b0 } ; - assign r1__read__h619402 = { r1__read__h619404, csrf_fs_reg } ; - assign r1__read__h619404 = { r1__read__h619406, 2'd0 } ; - assign r1__read__h619406 = { r1__read__h619408, 1'b0 } ; - assign r1__read__h619408 = { r1__read__h619410, csrf_sum_reg } ; - assign r1__read__h619410 = { r1__read__h619412, csrf_mxr_reg } ; - assign r1__read__h619412 = { r1__read__h619414, 12'b0 } ; - assign r1__read__h619414 = { r1__read__h619416, 2'b10 } ; - assign r1__read__h619416 = { r__h619420, 29'b0 } ; - assign r1__read__h619792 = - { r1__read__h619794, csrf_software_int_en_vec_1 } ; - assign r1__read__h619794 = { r1__read__h619796, 2'b0 } ; - assign r1__read__h619796 = { r1__read__h619798, 1'b0 } ; - assign r1__read__h619798 = { r1__read__h619800, csrf_timer_int_en_vec_1 } ; - assign r1__read__h619800 = { r1__read__h619802, 2'b0 } ; - assign r1__read__h619802 = { r1__read__h619804, 1'b0 } ; - assign r1__read__h619804 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h620302 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620307 = { r1__read__h620309, csrf_scounteren_tm_reg } ; - assign r1__read__h620309 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h620320 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h620326 = - { r1__read__h620328, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620328 = { r1__read__h620330, 2'b0 } ; - assign r1__read__h620330 = { r1__read__h620332, 1'b0 } ; - assign r1__read__h620332 = - { r1__read__h620334, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620334 = { r1__read__h620336, 2'b0 } ; - assign r1__read__h620336 = { r1__read__h620338, 1'b0 } ; - assign r1__read__h620338 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620536 = { vm_mode_reg__read__h620542, 16'd0 } ; - assign r1__read__h620559 = { r1__read__h620561, csrf_ie_vec_1 } ; - assign r1__read__h620561 = { r1__read__h620563, 1'b0 } ; - assign r1__read__h620563 = { r1__read__h620565, csrf_ie_vec_3 } ; - assign r1__read__h620565 = { r1__read__h620567, csrf_prev_ie_vec_0 } ; - assign r1__read__h620567 = { r1__read__h620569, csrf_prev_ie_vec_1 } ; - assign r1__read__h620569 = { r1__read__h620571, 1'b0 } ; - assign r1__read__h620571 = { r1__read__h620573, csrf_prev_ie_vec_3 } ; - assign r1__read__h620573 = { r1__read__h620575, csrf_spp_reg } ; - assign r1__read__h620575 = { r1__read__h620577, 2'b0 } ; - assign r1__read__h620577 = { r1__read__h620579, csrf_mpp_reg } ; - assign r1__read__h620579 = { r1__read__h620581, csrf_fs_reg } ; - assign r1__read__h620581 = { r1__read__h620583, 2'd0 } ; - assign r1__read__h620583 = { r1__read__h620585, csrf_mprv_reg } ; - assign r1__read__h620585 = { r1__read__h620587, csrf_sum_reg } ; - assign r1__read__h620587 = { r1__read__h620589, csrf_mxr_reg } ; - assign r1__read__h620589 = { r1__read__h620591, csrf_tvm_reg } ; - assign r1__read__h620591 = { r1__read__h620593, csrf_tw_reg } ; - assign r1__read__h620593 = { r1__read__h620595, csrf_tsr_reg } ; - assign r1__read__h620595 = { r1__read__h620597, 9'b0 } ; - assign r1__read__h620597 = { r1__read__h620599, 2'b10 } ; - assign r1__read__h620599 = { r1__read__h620601, 2'b10 } ; - assign r1__read__h620601 = { r__h619420, 27'b0 } ; - assign r1__read__h620684 = { r1__read__h620686, 1'b0 } ; - assign r1__read__h620686 = { r1__read__h620688, csrf_medeleg_13_11_reg } ; - assign r1__read__h620688 = { r1__read__h620690, 1'b0 } ; - assign r1__read__h620690 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h620701 = { r1__read__h620703, 1'b0 } ; - assign r1__read__h620703 = { r1__read__h620705, csrf_mideleg_5_3_reg } ; - assign r1__read__h620705 = { r1__read__h620707, 1'b0 } ; - assign r1__read__h620707 = { r1__read__h620709, csrf_mideleg_9_7_reg } ; - assign r1__read__h620709 = { r1__read__h620711, 1'b0 } ; - assign r1__read__h620711 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h620725 = - { r1__read__h620727, csrf_software_int_en_vec_1 } ; - assign r1__read__h620727 = { r1__read__h620729, 1'b0 } ; - assign r1__read__h620729 = - { r1__read__h620731, csrf_software_int_en_vec_3 } ; - assign r1__read__h620731 = { r1__read__h620733, 1'b0 } ; - assign r1__read__h620733 = { r1__read__h620735, csrf_timer_int_en_vec_1 } ; - assign r1__read__h620735 = { r1__read__h620737, 1'b0 } ; - assign r1__read__h620737 = { r1__read__h620739, csrf_timer_int_en_vec_3 } ; - assign r1__read__h620739 = { r1__read__h620741, 1'b0 } ; - assign r1__read__h620741 = - { r1__read__h620743, csrf_external_int_en_vec_1 } ; - assign r1__read__h620743 = { r1__read__h620745, 1'b0 } ; - assign r1__read__h620745 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h620818 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620823 = { r1__read__h620825, csrf_mcounteren_tm_reg } ; - assign r1__read__h620825 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h620836 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h620842 = - { r1__read__h620844, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620844 = { r1__read__h620846, 1'b0 } ; - assign r1__read__h620846 = - { r1__read__h620848, csrf_software_int_pend_vec_3 } ; - assign r1__read__h620848 = { r1__read__h620850, 1'b0 } ; - assign r1__read__h620850 = - { r1__read__h620852, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620852 = { r1__read__h620854, 1'b0 } ; - assign r1__read__h620854 = - { r1__read__h620856, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h620856 = { r1__read__h620858, 1'b0 } ; - assign r1__read__h620858 = - { r1__read__h620860, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620860 = { r1__read__h620862, 1'b0 } ; - assign r1__read__h620862 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h620939 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h487142 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h487143 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h480807 = + assign r1__read_BIT_20___h662370 = csrf_tw_reg ; + assign r1__read__h619389 = { r1__read__h619391, csrf_ie_vec_1 } ; + assign r1__read__h619391 = { r1__read__h619393, 2'b0 } ; + assign r1__read__h619393 = { r1__read__h619395, csrf_prev_ie_vec_0 } ; + assign r1__read__h619395 = { r1__read__h619397, csrf_prev_ie_vec_1 } ; + assign r1__read__h619397 = { r1__read__h619399, 2'b0 } ; + assign r1__read__h619399 = { r1__read__h619401, csrf_spp_reg } ; + assign r1__read__h619401 = { r1__read__h619403, 4'b0 } ; + assign r1__read__h619403 = { r1__read__h619405, csrf_fs_reg } ; + assign r1__read__h619405 = { r1__read__h619407, 2'd0 } ; + assign r1__read__h619407 = { r1__read__h619409, 1'b0 } ; + assign r1__read__h619409 = { r1__read__h619411, csrf_sum_reg } ; + assign r1__read__h619411 = { r1__read__h619413, csrf_mxr_reg } ; + assign r1__read__h619413 = { r1__read__h619415, 12'b0 } ; + assign r1__read__h619415 = { r1__read__h619417, 2'b10 } ; + assign r1__read__h619417 = { r__h619421, 29'b0 } ; + assign r1__read__h619793 = + { r1__read__h619795, csrf_software_int_en_vec_1 } ; + assign r1__read__h619795 = { r1__read__h619797, 2'b0 } ; + assign r1__read__h619797 = { r1__read__h619799, 1'b0 } ; + assign r1__read__h619799 = { r1__read__h619801, csrf_timer_int_en_vec_1 } ; + assign r1__read__h619801 = { r1__read__h619803, 2'b0 } ; + assign r1__read__h619803 = { r1__read__h619805, 1'b0 } ; + assign r1__read__h619805 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h620303 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620308 = { r1__read__h620310, csrf_scounteren_tm_reg } ; + assign r1__read__h620310 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h620321 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h620327 = + { r1__read__h620329, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620329 = { r1__read__h620331, 2'b0 } ; + assign r1__read__h620331 = { r1__read__h620333, 1'b0 } ; + assign r1__read__h620333 = + { r1__read__h620335, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620335 = { r1__read__h620337, 2'b0 } ; + assign r1__read__h620337 = { r1__read__h620339, 1'b0 } ; + assign r1__read__h620339 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620537 = { vm_mode_reg__read__h620543, 16'd0 } ; + assign r1__read__h620560 = { r1__read__h620562, csrf_ie_vec_1 } ; + assign r1__read__h620562 = { r1__read__h620564, 1'b0 } ; + assign r1__read__h620564 = { r1__read__h620566, csrf_ie_vec_3 } ; + assign r1__read__h620566 = { r1__read__h620568, csrf_prev_ie_vec_0 } ; + assign r1__read__h620568 = { r1__read__h620570, csrf_prev_ie_vec_1 } ; + assign r1__read__h620570 = { r1__read__h620572, 1'b0 } ; + assign r1__read__h620572 = { r1__read__h620574, csrf_prev_ie_vec_3 } ; + assign r1__read__h620574 = { r1__read__h620576, csrf_spp_reg } ; + assign r1__read__h620576 = { r1__read__h620578, 2'b0 } ; + assign r1__read__h620578 = { r1__read__h620580, csrf_mpp_reg } ; + assign r1__read__h620580 = { r1__read__h620582, csrf_fs_reg } ; + assign r1__read__h620582 = { r1__read__h620584, 2'd0 } ; + assign r1__read__h620584 = { r1__read__h620586, csrf_mprv_reg } ; + assign r1__read__h620586 = { r1__read__h620588, csrf_sum_reg } ; + assign r1__read__h620588 = { r1__read__h620590, csrf_mxr_reg } ; + assign r1__read__h620590 = { r1__read__h620592, csrf_tvm_reg } ; + assign r1__read__h620592 = { r1__read__h620594, csrf_tw_reg } ; + assign r1__read__h620594 = { r1__read__h620596, csrf_tsr_reg } ; + assign r1__read__h620596 = { r1__read__h620598, 9'b0 } ; + assign r1__read__h620598 = { r1__read__h620600, 2'b10 } ; + assign r1__read__h620600 = { r1__read__h620602, 2'b10 } ; + assign r1__read__h620602 = { r__h619421, 27'b0 } ; + assign r1__read__h620685 = { r1__read__h620687, 1'b0 } ; + assign r1__read__h620687 = { r1__read__h620689, csrf_medeleg_13_11_reg } ; + assign r1__read__h620689 = { r1__read__h620691, 1'b0 } ; + assign r1__read__h620691 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h620702 = { r1__read__h620704, 1'b0 } ; + assign r1__read__h620704 = { r1__read__h620706, csrf_mideleg_5_3_reg } ; + assign r1__read__h620706 = { r1__read__h620708, 1'b0 } ; + assign r1__read__h620708 = { r1__read__h620710, csrf_mideleg_9_7_reg } ; + assign r1__read__h620710 = { r1__read__h620712, 1'b0 } ; + assign r1__read__h620712 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h620726 = + { r1__read__h620728, csrf_software_int_en_vec_1 } ; + assign r1__read__h620728 = { r1__read__h620730, 1'b0 } ; + assign r1__read__h620730 = + { r1__read__h620732, csrf_software_int_en_vec_3 } ; + assign r1__read__h620732 = { r1__read__h620734, 1'b0 } ; + assign r1__read__h620734 = { r1__read__h620736, csrf_timer_int_en_vec_1 } ; + assign r1__read__h620736 = { r1__read__h620738, 1'b0 } ; + assign r1__read__h620738 = { r1__read__h620740, csrf_timer_int_en_vec_3 } ; + assign r1__read__h620740 = { r1__read__h620742, 1'b0 } ; + assign r1__read__h620742 = + { r1__read__h620744, csrf_external_int_en_vec_1 } ; + assign r1__read__h620744 = { r1__read__h620746, 1'b0 } ; + assign r1__read__h620746 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h620819 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620824 = { r1__read__h620826, csrf_mcounteren_tm_reg } ; + assign r1__read__h620826 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h620837 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h620843 = + { r1__read__h620845, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620845 = { r1__read__h620847, 1'b0 } ; + assign r1__read__h620847 = + { r1__read__h620849, csrf_software_int_pend_vec_3 } ; + assign r1__read__h620849 = { r1__read__h620851, 1'b0 } ; + assign r1__read__h620851 = + { r1__read__h620853, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620853 = { r1__read__h620855, 1'b0 } ; + assign r1__read__h620855 = + { r1__read__h620857, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h620857 = { r1__read__h620859, 1'b0 } ; + assign r1__read__h620859 = + { r1__read__h620861, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620861 = { r1__read__h620863, 1'b0 } ; + assign r1__read__h620863 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h620940 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h487143 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h487144 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h480808 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; - assign r__h619420 = csrf_fs_reg == 2'b11 ; + assign r__h619421 = csrf_fs_reg == 2'b11 ; assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d13407 = regRenamingTable$RDY_rename_0_getRename && regRenamingTable$RDY_rename_0_claimRename && @@ -29297,12 +29297,12 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14371 && (fetchStage$pipelines_1_first[199:195] != 5'd14) != fetchStage$pipelines_1_first[160] ; - assign renaming_spec_bits__h689556 = + assign renaming_spec_bits__h689557 = fetchStage$pipelines_0_canDeq ? - y_avValue_snd_fst__h686254 : + y_avValue_snd_fst__h686255 : specTagManager$currentSpecBits ; - assign res_data__h342519 = { 32'hFFFFFFFF, x__h342534 } ; - assign res_data__h342524 = + assign res_data__h342520 = { 32'hFFFFFFFF, x__h342535 } ; + assign res_data__h342525 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -29315,8 +29315,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h388221 = { 32'hFFFFFFFF, x__h388236 } ; - assign res_data__h388226 = + assign res_data__h388222 = { 32'hFFFFFFFF, x__h388237 } ; + assign res_data__h388227 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -29329,8 +29329,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h433916 = { 32'hFFFFFFFF, x__h433931 } ; - assign res_data__h433921 = + assign res_data__h433917 = { 32'hFFFFFFFF, x__h433932 } ; + assign res_data__h433922 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -29343,7 +29343,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h342520 = + assign res_fflags__h342521 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -29411,7 +29411,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351 } ; - assign res_fflags__h388222 = + assign res_fflags__h388223 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -29479,7 +29479,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743 } ; - assign res_fflags__h433917 = + assign res_fflags__h433918 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -29547,37 +29547,37 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135 } ; - assign resp_addr__h296627 = + assign resp_addr__h296628 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h368987 = + assign result__h368988 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[0] | - guard__h368982 } ; - assign result__h414684 = + guard__h368983 } ; + assign result__h414685 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[0] | - guard__h414679 } ; - assign result__h460379 = + guard__h414680 } ; + assign result__h460380 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[0] | - guard__h460374 } ; - assign result__h508868 = + guard__h460375 } ; + assign result__h508869 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[0] | - guard__h508863 } ; - assign result__h547721 = + guard__h508864 } ; + assign result__h547722 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[0] | - guard__h547716 } ; - assign result__h587025 = + guard__h547717 } ; + assign result__h587026 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[0] | - guard__h587020 } ; - assign result__h653733 = w__h653728 & y__h653762 ; - assign result__h653784 = ~x__h653783 ; - assign rg_tdata1__read__h619063 = - { r1__read__h620939, csrf_rg_tdata1_data } ; + guard__h587021 } ; + assign result__h653734 = w__h653729 & y__h653763 ; + assign result__h653785 = ~x__h653784 ; + assign rg_tdata1__read__h619064 = + { r1__read__h620940, csrf_rg_tdata1_data } ; assign rob_deqPort_0_deq_data__4451_BITS_353_TO_290_4_ETC___d14954 = rob$deqPort_0_deq_data[353:290] + 64'd4 ; assign rob_enqPort_1_canEnq__3821_AND_epochManager_ch_ETC___d13826 = @@ -29603,469 +29603,469 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13973) ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q262 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h661836 = + assign rs1__h661837 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h616936 = { r1__read__h620536, csrf_ppn_reg } ; - assign sbIdx__h158517 = + assign satp_csr__read__h616937 = { r1__read__h620537, csrf_ppn_reg } ; + assign sbIdx__h158518 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h616733 = - { r1__read__h620320, csrf_scause_code_reg } ; - assign scounteren_csr__read__h616595 = - { r1__read__h620307, csrf_scounteren_cy_reg } ; - assign sfd__h343130 = { value__h351357, 3'd0 } ; - assign sfd__h358938 = + assign scause_csr__read__h616734 = + { r1__read__h620321, csrf_scause_code_reg } ; + assign scounteren_csr__read__h616596 = + { r1__read__h620308, csrf_scounteren_cy_reg } ; + assign sfd__h343131 = { value__h351358, 3'd0 } ; + assign sfd__h358939 = { 1'b0, - _theResult___fst_exp__h358846 != 8'd0, - sfdin__h358840[56:34] } + + _theResult___fst_exp__h358847 != 8'd0, + sfdin__h358841[56:34] } + 25'd1 ; - assign sfd__h367520 = + assign sfd__h367521 = { 1'b0, - _theResult___fst_exp__h367502 != 8'd0, - _theResult___snd__h367453[56:34] } + + _theResult___fst_exp__h367503 != 8'd0, + _theResult___snd__h367454[56:34] } + 25'd1 ; - assign sfd__h376704 = + assign sfd__h376705 = { 1'b0, - _theResult___fst_exp__h376612 != 8'd0, - sfdin__h376606[56:34] } + + _theResult___fst_exp__h376613 != 8'd0, + sfdin__h376607[56:34] } + 25'd1 ; - assign sfd__h385316 = + assign sfd__h385317 = { 1'b0, - _theResult___fst_exp__h385297 != 8'd0, - _theResult___snd__h385243[56:34] } + + _theResult___fst_exp__h385298 != 8'd0, + _theResult___snd__h385244[56:34] } + 25'd1 ; - assign sfd__h388832 = { value__h397054, 3'd0 } ; - assign sfd__h404635 = + assign sfd__h388833 = { value__h397055, 3'd0 } ; + assign sfd__h404636 = { 1'b0, - _theResult___fst_exp__h404543 != 8'd0, - sfdin__h404537[56:34] } + + _theResult___fst_exp__h404544 != 8'd0, + sfdin__h404538[56:34] } + 25'd1 ; - assign sfd__h413217 = + assign sfd__h413218 = { 1'b0, - _theResult___fst_exp__h413199 != 8'd0, - _theResult___snd__h413150[56:34] } + + _theResult___fst_exp__h413200 != 8'd0, + _theResult___snd__h413151[56:34] } + 25'd1 ; - assign sfd__h422401 = + assign sfd__h422402 = { 1'b0, - _theResult___fst_exp__h422309 != 8'd0, - sfdin__h422303[56:34] } + + _theResult___fst_exp__h422310 != 8'd0, + sfdin__h422304[56:34] } + 25'd1 ; - assign sfd__h431013 = + assign sfd__h431014 = { 1'b0, - _theResult___fst_exp__h430994 != 8'd0, - _theResult___snd__h430940[56:34] } + + _theResult___fst_exp__h430995 != 8'd0, + _theResult___snd__h430941[56:34] } + 25'd1 ; - assign sfd__h434527 = { value__h442749, 3'd0 } ; - assign sfd__h450330 = + assign sfd__h434528 = { value__h442750, 3'd0 } ; + assign sfd__h450331 = { 1'b0, - _theResult___fst_exp__h450238 != 8'd0, - sfdin__h450232[56:34] } + + _theResult___fst_exp__h450239 != 8'd0, + sfdin__h450233[56:34] } + 25'd1 ; - assign sfd__h458912 = + assign sfd__h458913 = { 1'b0, - _theResult___fst_exp__h458894 != 8'd0, - _theResult___snd__h458845[56:34] } + + _theResult___fst_exp__h458895 != 8'd0, + _theResult___snd__h458846[56:34] } + 25'd1 ; - assign sfd__h468096 = + assign sfd__h468097 = { 1'b0, - _theResult___fst_exp__h468004 != 8'd0, - sfdin__h467998[56:34] } + + _theResult___fst_exp__h468005 != 8'd0, + sfdin__h467999[56:34] } + 25'd1 ; - assign sfd__h476708 = + assign sfd__h476709 = { 1'b0, - _theResult___fst_exp__h476689 != 8'd0, - _theResult___snd__h476635[56:34] } + + _theResult___fst_exp__h476690 != 8'd0, + _theResult___snd__h476636[56:34] } + 25'd1 ; - assign sfd__h487888 = { value__h492471, 32'd0 } ; - assign sfd__h506932 = + assign sfd__h487889 = { value__h492472, 32'd0 } ; + assign sfd__h506933 = { 1'b0, - _theResult___fst_exp__h506914 != 11'd0, - _theResult___snd__h506865[56:5] } + + _theResult___fst_exp__h506915 != 11'd0, + _theResult___snd__h506866[56:5] } + 54'd1 ; - assign sfd__h516583 = + assign sfd__h516584 = { 1'b0, - _theResult___fst_exp__h516491 != 11'd0, - sfdin__h516485[56:5] } + + _theResult___fst_exp__h516492 != 11'd0, + sfdin__h516486[56:5] } + 54'd1 ; - assign sfd__h525343 = + assign sfd__h525344 = { 1'b0, - _theResult___fst_exp__h525324 != 11'd0, - _theResult___snd__h525270[56:5] } + + _theResult___fst_exp__h525325 != 11'd0, + _theResult___snd__h525271[56:5] } + 54'd1 ; - assign sfd__h526882 = { value__h531324, 32'd0 } ; - assign sfd__h545785 = + assign sfd__h526883 = { value__h531325, 32'd0 } ; + assign sfd__h545786 = { 1'b0, - _theResult___fst_exp__h545767 != 11'd0, - _theResult___snd__h545718[56:5] } + + _theResult___fst_exp__h545768 != 11'd0, + _theResult___snd__h545719[56:5] } + 54'd1 ; - assign sfd__h555436 = + assign sfd__h555437 = { 1'b0, - _theResult___fst_exp__h555344 != 11'd0, - sfdin__h555338[56:5] } + + _theResult___fst_exp__h555345 != 11'd0, + sfdin__h555339[56:5] } + 54'd1 ; - assign sfd__h564196 = + assign sfd__h564197 = { 1'b0, - _theResult___fst_exp__h564177 != 11'd0, - _theResult___snd__h564123[56:5] } + + _theResult___fst_exp__h564178 != 11'd0, + _theResult___snd__h564124[56:5] } + 54'd1 ; - assign sfd__h566186 = { value__h570628, 32'd0 } ; - assign sfd__h585089 = + assign sfd__h566187 = { value__h570629, 32'd0 } ; + assign sfd__h585090 = { 1'b0, - _theResult___fst_exp__h585071 != 11'd0, - _theResult___snd__h585022[56:5] } + + _theResult___fst_exp__h585072 != 11'd0, + _theResult___snd__h585023[56:5] } + 54'd1 ; - assign sfd__h594740 = + assign sfd__h594741 = { 1'b0, - _theResult___fst_exp__h594648 != 11'd0, - sfdin__h594642[56:5] } + + _theResult___fst_exp__h594649 != 11'd0, + sfdin__h594643[56:5] } + 54'd1 ; - assign sfd__h603500 = + assign sfd__h603501 = { 1'b0, - _theResult___fst_exp__h603481 != 11'd0, - _theResult___snd__h603427[56:5] } + + _theResult___fst_exp__h603482 != 11'd0, + _theResult___snd__h603428[56:5] } + 54'd1 ; - assign sfdin__h358840 = - _theResult____h350735[56] ? - _theResult___snd__h358857 : - _theResult___snd__h358868 ; - assign sfdin__h376606 = - _theResult____h368374[56] ? - _theResult___snd__h376623 : - _theResult___snd__h376634 ; - assign sfdin__h404537 = - _theResult____h396434[56] ? - _theResult___snd__h404554 : - _theResult___snd__h404565 ; - assign sfdin__h422303 = - _theResult____h414071[56] ? - _theResult___snd__h422320 : - _theResult___snd__h422331 ; - assign sfdin__h450232 = - _theResult____h442129[56] ? - _theResult___snd__h450249 : - _theResult___snd__h450260 ; - assign sfdin__h467998 = - _theResult____h459766[56] ? - _theResult___snd__h468015 : - _theResult___snd__h468026 ; - assign sfdin__h516485 = - _theResult____h508255[56] ? - _theResult___snd__h516502 : - _theResult___snd__h516513 ; - assign sfdin__h555338 = - _theResult____h547108[56] ? - _theResult___snd__h555355 : - _theResult___snd__h555366 ; - assign sfdin__h594642 = - _theResult____h586412[56] ? - _theResult___snd__h594659 : - _theResult___snd__h594670 ; - assign shiftData__h184742 = - coreFix_memExe_regToExeQ$first[75:12] << x__h184871 ; - assign sie_csr__read__h616499 = { r1__read__h619792, 1'b0 } ; - assign sip_csr__read__h616873 = { r1__read__h620326, 1'b0 } ; - assign spec_bits__h692683 = specTagManager$currentSpecBits | y__h692696 ; - assign sstatus_csr__read__h616429 = { r1__read__h619388, csrf_ie_vec_0 } ; - assign stvec_csr__read__h616542 = - { r1__read__h620302, csrf_stvec_mode_low_reg } ; + assign sfdin__h358841 = + _theResult____h350736[56] ? + _theResult___snd__h358858 : + _theResult___snd__h358869 ; + assign sfdin__h376607 = + _theResult____h368375[56] ? + _theResult___snd__h376624 : + _theResult___snd__h376635 ; + assign sfdin__h404538 = + _theResult____h396435[56] ? + _theResult___snd__h404555 : + _theResult___snd__h404566 ; + assign sfdin__h422304 = + _theResult____h414072[56] ? + _theResult___snd__h422321 : + _theResult___snd__h422332 ; + assign sfdin__h450233 = + _theResult____h442130[56] ? + _theResult___snd__h450250 : + _theResult___snd__h450261 ; + assign sfdin__h467999 = + _theResult____h459767[56] ? + _theResult___snd__h468016 : + _theResult___snd__h468027 ; + assign sfdin__h516486 = + _theResult____h508256[56] ? + _theResult___snd__h516503 : + _theResult___snd__h516514 ; + assign sfdin__h555339 = + _theResult____h547109[56] ? + _theResult___snd__h555356 : + _theResult___snd__h555367 ; + assign sfdin__h594643 = + _theResult____h586413[56] ? + _theResult___snd__h594660 : + _theResult___snd__h594671 ; + assign shiftData__h184743 = + coreFix_memExe_regToExeQ$first[75:12] << x__h184872 ; + assign sie_csr__read__h616500 = { r1__read__h619793, 1'b0 } ; + assign sip_csr__read__h616874 = { r1__read__h620327, 1'b0 } ; + assign spec_bits__h692684 = specTagManager$currentSpecBits | y__h692697 ; + assign sstatus_csr__read__h616430 = { r1__read__h619389, csrf_ie_vec_0 } ; + assign stvec_csr__read__h616543 = + { r1__read__h620303, csrf_stvec_mode_low_reg } ; assign upd__h3681 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h4998 = n__read__h6330 + 64'd1 ; - assign v__h300591 = + assign upd__h4998 = n__read__h6331 + 64'd1 ; + assign v__h300592 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127) ? - v__h300822 : + v__h300823 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h300822 = + assign v__h300823 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h303936 = + assign v__h303937 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234) ? - v__h304454 : + v__h304455 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h304454 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h314450 = + assign v__h304455 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h314451 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405) ? - v__h314681 : + v__h314682 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h314681 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h318326 = + assign v__h314682 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h318327 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501) ? - v__h318557 : + v__h318558 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h318557 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h332927 = + assign v__h318558 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h332928 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730) ? - v__h333158 : + v__h333159 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h333158 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h336152 = + assign v__h333159 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h336153 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824) ? - v__h336383 : + v__h336384 : coreFix_memExe_forwardQ_enqP ; - assign v__h336383 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h609619 = + assign v__h336384 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h609620 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h609629 : + v__h609630 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h609629 = + assign v__h609630 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h610687 = v__h609619 - 2'd1 ; - assign v__h614703 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615874 ; - assign v__h639701 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640720 ; - assign vaddr__h184737 = + assign v__h610688 = v__h609620 - 2'd1 ; + assign v__h614704 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615875 ; + assign v__h639702 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640721 ; + assign vaddr__h184738 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 } ; - assign value__h351357 = + assign value__h351358 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h397054 = + assign value__h397055 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h442749 = + assign value__h442750 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h492471 = { 1'b0, f1_exp__h487526 != 8'd0, f1_sfd__h487527 } ; - assign value__h531324 = { 1'b0, f2_exp__h526520 != 8'd0, f2_sfd__h526521 } ; - assign value__h570628 = { 1'b0, f3_exp__h565824 != 8'd0, f3_sfd__h565825 } ; - assign vm_mode_reg__read__h620542 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h653728 = + assign value__h492472 = { 1'b0, f1_exp__h487527 != 8'd0, f1_sfd__h487528 } ; + assign value__h531325 = { 1'b0, f2_exp__h526521 != 8'd0, f2_sfd__h526522 } ; + assign value__h570629 = { 1'b0, f3_exp__h565825 != 8'd0, f3_sfd__h565826 } ; + assign vm_mode_reg__read__h620543 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h653729 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h653784 : + result__h653785 : 12'd4095 ; - assign x__h155091 = + assign x__h155092 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h155097 = + assign x__h155098 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h158638 = { 3'd0, sbIdx__h158517 } ; - assign x__h158644 = + assign x__h158639 = { 3'd0, sbIdx__h158518 } ; + assign x__h158645 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h161454 = + assign x__h161455 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h161458 = + assign x__h161459 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h163306 = + assign x__h163307 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h17932 = + assign x__h17933 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h184649 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183777 ; assign x__h184650 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184496 ; - assign x__h184871 = { vaddr__h184737[2:0], 3'b0 } ; - assign x__h196066 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183778 ; + assign x__h184651 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184497 ; + assign x__h184872 = { vaddr__h184738[2:0], 3'b0 } ; + assign x__h196067 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h195303[63:32] : - curData__h195303[31:0] ; - assign x__h20470 = + curData__h195304[63:32] : + curData__h195304[31:0] ; + assign x__h20471 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h291824 = + assign x__h291825 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h291836 = + assign x__h291837 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h293690 = + assign x__h293691 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h306801 = + assign x__h306802 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h342534 = - { (_theResult___exp__h385866 != 8'd255 || - _theResult___sfd__h385867 == 23'd0) && + assign x__h342535 = + { (_theResult___exp__h385867 != 8'd255 || + _theResult___sfd__h385868 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236, - out_f_exp__h386143, - out_f_sfd__h386144 } ; - assign x__h369084 = - sfd__h343130 << (x__h369117[11] ? 12'hAAA : x__h369117) ; - assign x__h369117 = + out_f_exp__h386144, + out_f_sfd__h386145 } ; + assign x__h369085 = + sfd__h343131 << (x__h369118[11] ? 12'hAAA : x__h369118) ; + assign x__h369118 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ; - assign x__h388236 = - { (_theResult___exp__h431563 != 8'd255 || - _theResult___sfd__h431564 == 23'd0) && + assign x__h388237 = + { (_theResult___exp__h431564 != 8'd255 || + _theResult___sfd__h431565 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628, - out_f_exp__h431840, - out_f_sfd__h431841 } ; - assign x__h414781 = - sfd__h388832 << (x__h414814[11] ? 12'hAAA : x__h414814) ; - assign x__h414814 = + out_f_exp__h431841, + out_f_sfd__h431842 } ; + assign x__h414782 = + sfd__h388833 << (x__h414815[11] ? 12'hAAA : x__h414815) ; + assign x__h414815 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ; - assign x__h433931 = - { (_theResult___exp__h477258 != 8'd255 || - _theResult___sfd__h477259 == 23'd0) && + assign x__h433932 = + { (_theResult___exp__h477259 != 8'd255 || + _theResult___sfd__h477260 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020, - out_f_exp__h477535, - out_f_sfd__h477536 } ; - assign x__h45839 = + out_f_exp__h477536, + out_f_sfd__h477537 } ; + assign x__h45840 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h460476 = - sfd__h434527 << (x__h460509[11] ? 12'hAAA : x__h460509) ; - assign x__h460509 = + assign x__h460477 = + sfd__h434528 << (x__h460510[11] ? 12'hAAA : x__h460510) ; + assign x__h460510 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ; - assign x__h48375 = + assign x__h48376 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h487048 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h484111 ; assign x__h487049 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484832 ; + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h484112 ; assign x__h487050 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485547 ; - assign x__h508963 = sfd__h487888 << x__h508996 ; - assign x__h508996 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484833 ; + assign x__h487051 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485548 ; + assign x__h508964 = sfd__h487889 << x__h508997 ; + assign x__h508997 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ; - assign x__h547816 = sfd__h526882 << x__h547849 ; - assign x__h547849 = + assign x__h547817 = sfd__h526883 << x__h547850 ; + assign x__h547850 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ; - assign x__h587120 = sfd__h566186 << x__h587153 ; - assign x__h587153 = + assign x__h587121 = sfd__h566187 << x__h587154 ; + assign x__h587154 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ; - assign x__h608909 = + assign x__h608910 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h608920 : - a__h608372 ; - assign x__h608935 = a__h608372[63] ^ b__h608373[63] ; - assign x__h609549 = + _theResult___fst__h608921 : + a__h608373 ; + assign x__h608936 = a__h608373[63] ^ b__h608374[63] ; + assign x__h609550 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257 } ; - assign x__h619373 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h623642 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h615931 : - v__h614703 ; + assign x__h619374 = { csrf_frm_reg, csrf_fflags_reg } ; assign x__h623643 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621652 ; - assign x__h646271 = - coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h640775 : - v__h639701 ; + coreFix_aluExe_1_dispToRegQ$first[131] ? + rVal1__h615932 : + v__h614704 ; + assign x__h623644 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621653 ; assign x__h646272 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644291 ; - assign x__h653732 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h653783 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h704087 = + coreFix_aluExe_0_dispToRegQ$first[131] ? + rVal1__h640776 : + v__h639702 ; + assign x__h646273 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644292 ; + assign x__h653733 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h653784 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h704088 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h710696 = { cause_code__h707758, 2'b0 } ; - assign x__h718767 = { 1'b0, csrf_spp_reg } ; - assign x__h722832 = + assign x__h710697 = { cause_code__h707759, 2'b0 } ; + assign x__h718768 = { 1'b0, csrf_spp_reg } ; + assign x__h722833 = NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_snd_snd_snd_fst__h722655 : + y_avValue_snd_snd_snd_fst__h722656 : IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 ; - assign x__h75784 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h318724 = + assign x__h75785 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h318725 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h65633 = + assign x_data__h65634 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h681437 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h697341 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h661520 = csrf_frm_reg ; - assign x_quotient__h479957 = + assign x_data_imm__h681438 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h697342 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h661521 = csrf_frm_reg ; + assign x_quotient__h479958 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h480780 : + q___1__h480781 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h616338 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h479958 = + assign x_reg_ifc__read__h616339 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h479959 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h480807 : + r___1__h480808 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h258434 = + assign y__h258435 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h626444 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; - assign y__h648780 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; - assign y__h653762 = ~x__h653732 ; - assign y__h658451 = + assign y__h626445 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; + assign y__h648781 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; + assign y__h653763 = ~x__h653733 ; + assign y__h658452 = { ~csrf_mideleg_11_reg, 1'd1, ~csrf_mideleg_9_7_reg, @@ -30073,52 +30073,52 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h692696 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h722608 = + assign y__h692697 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h722609 = NOT_rob_deqPort_0_canDeq__4986_4987_OR_rob_deq_ETC___d15178 ? - y_avValue_snd_snd_snd_snd_snd__h722661 : + y_avValue_snd_snd_snd_snd_snd__h722662 : IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 ; - assign y_avValue__h183777 = + assign y_avValue__h183778 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679 ; - assign y_avValue__h184496 = + assign y_avValue__h184497 = NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687 ; - assign y_avValue__h484111 = + assign y_avValue__h484112 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 ; - assign y_avValue__h484832 = + assign y_avValue__h484833 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 ; - assign y_avValue__h485547 = + assign y_avValue__h485548 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 ; - assign y_avValue__h615874 = + assign y_avValue__h615875 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11943 ; - assign y_avValue__h621652 = + assign y_avValue__h621653 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11952 ; - assign y_avValue__h640720 = + assign y_avValue__h640721 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12617 ; - assign y_avValue__h644291 = + assign y_avValue__h644292 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12626 ; - assign y_avValue_fst__h685980 = + assign y_avValue_fst__h685981 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h692683 : + spec_bits__h692684 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h721562 = + assign y_avValue_fst__h721563 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30132,10 +30132,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h722504 = + assign y_avValue_fst__h722505 = IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h722532 = + assign y_avValue_fst__h722533 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30148,27 +30148,27 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15184 : - y_avValue_fst__h722504 ; - assign y_avValue_new_pc__h710462 = + y_avValue_fst__h722505 ; + assign y_avValue_new_pc__h710463 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h710681 + { 58'd0, x__h710696 } : - base__h710681 ; - assign y_avValue_new_pc__h710648 = + base__h710682 + { 58'd0, x__h710697 } : + base__h710682 ; + assign y_avValue_new_pc__h710649 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h710701 + { 58'd0, x__h710696 } : - base__h710701 ; - assign y_avValue_snd_fst__h686254 = + base__h710702 + { 58'd0, x__h710697 } : + base__h710702 ; + assign y_avValue_snd_fst__h686255 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable$rename_0_canRename && NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13533) ? - y_avValue_snd_fst__h686289 : + y_avValue_snd_fst__h686290 : specTagManager$currentSpecBits ; - assign y_avValue_snd_fst__h686289 = + assign y_avValue_snd_fst__h686290 = IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13593 ? - y_avValue_fst__h685980 : + y_avValue_fst__h685981 : specTagManager$currentSpecBits ; - assign y_avValue_snd_snd_snd_fst__h721996 = + assign y_avValue_snd_snd_snd_fst__h721997 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30182,7 +30182,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h722655 = + assign y_avValue_snd_snd_snd_fst__h722656 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30195,11 +30195,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 : - y_avValue_snd_snd_snd_fst__h722684 ; - assign y_avValue_snd_snd_snd_fst__h722684 = + y_avValue_snd_snd_snd_fst__h722685 ; + assign y_avValue_snd_snd_snd_fst__h722685 = IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15205 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h722002 = + assign y_avValue_snd_snd_snd_snd_snd__h722003 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[257:253] == 5'd0 || @@ -30213,7 +30213,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[257:253] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd__h722661 = + assign y_avValue_snd_snd_snd_snd_snd__h722662 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[257:253] == 5'd0 || @@ -30226,8 +30226,8 @@ module mkCore(CLK, rob$deqPort_1_deq_data[257:253] == 5'd19 || rob$deqPort_1_deq_data[257:253] == 5'd20) ? IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 : - y_avValue_snd_snd_snd_snd_snd__h722690 ; - assign y_avValue_snd_snd_snd_snd_snd__h722690 = + y_avValue_snd_snd_snd_snd_snd__h722691 ; + assign y_avValue_snd_snd_snd_snd_snd__h722691 = IF_rob_deqPort_0_canDeq__4986_THEN_IF_NOT_rob__ETC___d15095 + 64'd1 ; always@(mmio_cRqQ_data_0) @@ -30246,28 +30246,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h200346 = + x__h200347 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -30283,28 +30283,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h290391 = + x__h290392 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -30314,10 +30314,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h294612 = + addr__h294613 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h294612 = + addr__h294613 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -30326,37 +30326,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h195303 = + curData__h195304 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h708781 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h708781 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h708781 = + 4'd0, 4'd3: trap_val__h708782 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h708782 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h708782 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -30370,265 +30370,265 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h296161 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h296162 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h296161 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h296162 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h616208 or - frm_csr__read__h616219 or - fcsr_csr__read__h616233 or - sstatus_csr__read__h616429 or - sie_csr__read__h616499 or - stvec_csr__read__h616542 or - scounteren_csr__read__h616595 or + fflags_csr__read__h616209 or + frm_csr__read__h616220 or + fcsr_csr__read__h616234 or + sstatus_csr__read__h616430 or + sie_csr__read__h616500 or + stvec_csr__read__h616543 or + scounteren_csr__read__h616596 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616733 or + scause_csr__read__h616734 or csrf_stval_csr or - sip_csr__read__h616873 or - satp_csr__read__h616936 or - mstatus_csr__read__h617079 or - medeleg_csr__read__h617227 or - mideleg_csr__read__h617322 or - mie_csr__read__h617446 or - mtvec_csr__read__h617528 or - mcounteren_csr__read__h617620 or + sip_csr__read__h616874 or + satp_csr__read__h616937 or + mstatus_csr__read__h617080 or + medeleg_csr__read__h617228 or + mideleg_csr__read__h617323 or + mie_csr__read__h617447 or + mtvec_csr__read__h617529 or + mcounteren_csr__read__h617621 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617875 or + mcause_csr__read__h617876 or csrf_mtval_csr or - mip_csr__read__h618108 or + mip_csr__read__h618109 or csrf_rg_tselect or - rg_tdata1__read__h619063 or + rg_tdata1__read__h619064 or csrf_rg_tdata2 or csrf_rg_tdata3 or - x_reg_ifc__read__h616338 or - n__read__h618212 or n__read__h618403 or csrf_time_reg) + x_reg_ifc__read__h616339 or + n__read__h618213 or n__read__h618404 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h615931 = fflags_csr__read__h616208; - 12'd2: rVal1__h615931 = frm_csr__read__h616219; - 12'd3: rVal1__h615931 = fcsr_csr__read__h616233; - 12'd256: rVal1__h615931 = sstatus_csr__read__h616429; - 12'd260: rVal1__h615931 = sie_csr__read__h616499; - 12'd261: rVal1__h615931 = stvec_csr__read__h616542; - 12'd262: rVal1__h615931 = scounteren_csr__read__h616595; - 12'd320: rVal1__h615931 = csrf_sscratch_csr; - 12'd321: rVal1__h615931 = csrf_sepc_csr; - 12'd322: rVal1__h615931 = scause_csr__read__h616733; - 12'd323: rVal1__h615931 = csrf_stval_csr; - 12'd324: rVal1__h615931 = sip_csr__read__h616873; - 12'd384: rVal1__h615931 = satp_csr__read__h616936; - 12'd768: rVal1__h615931 = mstatus_csr__read__h617079; - 12'd769: rVal1__h615931 = 64'h800000000014112D; - 12'd770: rVal1__h615931 = medeleg_csr__read__h617227; - 12'd771: rVal1__h615931 = mideleg_csr__read__h617322; - 12'd772: rVal1__h615931 = mie_csr__read__h617446; - 12'd773: rVal1__h615931 = mtvec_csr__read__h617528; - 12'd774: rVal1__h615931 = mcounteren_csr__read__h617620; - 12'd832: rVal1__h615931 = csrf_mscratch_csr; - 12'd833: rVal1__h615931 = csrf_mepc_csr; - 12'd834: rVal1__h615931 = mcause_csr__read__h617875; - 12'd835: rVal1__h615931 = csrf_mtval_csr; - 12'd836: rVal1__h615931 = mip_csr__read__h618108; - 12'd1952: rVal1__h615931 = csrf_rg_tselect; - 12'd1953: rVal1__h615931 = rg_tdata1__read__h619063; - 12'd1954: rVal1__h615931 = csrf_rg_tdata2; - 12'd1955: rVal1__h615931 = csrf_rg_tdata3; + 12'd1: rVal1__h615932 = fflags_csr__read__h616209; + 12'd2: rVal1__h615932 = frm_csr__read__h616220; + 12'd3: rVal1__h615932 = fcsr_csr__read__h616234; + 12'd256: rVal1__h615932 = sstatus_csr__read__h616430; + 12'd260: rVal1__h615932 = sie_csr__read__h616500; + 12'd261: rVal1__h615932 = stvec_csr__read__h616543; + 12'd262: rVal1__h615932 = scounteren_csr__read__h616596; + 12'd320: rVal1__h615932 = csrf_sscratch_csr; + 12'd321: rVal1__h615932 = csrf_sepc_csr; + 12'd322: rVal1__h615932 = scause_csr__read__h616734; + 12'd323: rVal1__h615932 = csrf_stval_csr; + 12'd324: rVal1__h615932 = sip_csr__read__h616874; + 12'd384: rVal1__h615932 = satp_csr__read__h616937; + 12'd768: rVal1__h615932 = mstatus_csr__read__h617080; + 12'd769: rVal1__h615932 = 64'h800000000014112D; + 12'd770: rVal1__h615932 = medeleg_csr__read__h617228; + 12'd771: rVal1__h615932 = mideleg_csr__read__h617323; + 12'd772: rVal1__h615932 = mie_csr__read__h617447; + 12'd773: rVal1__h615932 = mtvec_csr__read__h617529; + 12'd774: rVal1__h615932 = mcounteren_csr__read__h617621; + 12'd832: rVal1__h615932 = csrf_mscratch_csr; + 12'd833: rVal1__h615932 = csrf_mepc_csr; + 12'd834: rVal1__h615932 = mcause_csr__read__h617876; + 12'd835: rVal1__h615932 = csrf_mtval_csr; + 12'd836: rVal1__h615932 = mip_csr__read__h618109; + 12'd1952: rVal1__h615932 = csrf_rg_tselect; + 12'd1953: rVal1__h615932 = rg_tdata1__read__h619064; + 12'd1954: rVal1__h615932 = csrf_rg_tdata2; + 12'd1955: rVal1__h615932 = csrf_rg_tdata3; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h615931 = 64'd0; - 12'd2049: rVal1__h615931 = x_reg_ifc__read__h616338; - 12'd2816, 12'd3072: rVal1__h615931 = n__read__h618212; - 12'd2818, 12'd3074: rVal1__h615931 = n__read__h618403; - 12'd3073: rVal1__h615931 = csrf_time_reg; - default: rVal1__h615931 = 64'b0; + rVal1__h615932 = 64'd0; + 12'd2049: rVal1__h615932 = x_reg_ifc__read__h616339; + 12'd2816, 12'd3072: rVal1__h615932 = n__read__h618213; + 12'd2818, 12'd3074: rVal1__h615932 = n__read__h618404; + 12'd3073: rVal1__h615932 = csrf_time_reg; + default: rVal1__h615932 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h616208 or - frm_csr__read__h616219 or - fcsr_csr__read__h616233 or - sstatus_csr__read__h616429 or - sie_csr__read__h616499 or - stvec_csr__read__h616542 or - scounteren_csr__read__h616595 or + fflags_csr__read__h616209 or + frm_csr__read__h616220 or + fcsr_csr__read__h616234 or + sstatus_csr__read__h616430 or + sie_csr__read__h616500 or + stvec_csr__read__h616543 or + scounteren_csr__read__h616596 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616733 or + scause_csr__read__h616734 or csrf_stval_csr or - sip_csr__read__h616873 or - satp_csr__read__h616936 or - mstatus_csr__read__h617079 or - medeleg_csr__read__h617227 or - mideleg_csr__read__h617322 or - mie_csr__read__h617446 or - mtvec_csr__read__h617528 or - mcounteren_csr__read__h617620 or + sip_csr__read__h616874 or + satp_csr__read__h616937 or + mstatus_csr__read__h617080 or + medeleg_csr__read__h617228 or + mideleg_csr__read__h617323 or + mie_csr__read__h617447 or + mtvec_csr__read__h617529 or + mcounteren_csr__read__h617621 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617875 or + mcause_csr__read__h617876 or csrf_mtval_csr or - mip_csr__read__h618108 or + mip_csr__read__h618109 or csrf_rg_tselect or - rg_tdata1__read__h619063 or + rg_tdata1__read__h619064 or csrf_rg_tdata2 or csrf_rg_tdata3 or - x_reg_ifc__read__h616338 or - n__read__h618212 or n__read__h618403 or csrf_time_reg) + x_reg_ifc__read__h616339 or + n__read__h618213 or n__read__h618404 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h640775 = fflags_csr__read__h616208; - 12'd2: rVal1__h640775 = frm_csr__read__h616219; - 12'd3: rVal1__h640775 = fcsr_csr__read__h616233; - 12'd256: rVal1__h640775 = sstatus_csr__read__h616429; - 12'd260: rVal1__h640775 = sie_csr__read__h616499; - 12'd261: rVal1__h640775 = stvec_csr__read__h616542; - 12'd262: rVal1__h640775 = scounteren_csr__read__h616595; - 12'd320: rVal1__h640775 = csrf_sscratch_csr; - 12'd321: rVal1__h640775 = csrf_sepc_csr; - 12'd322: rVal1__h640775 = scause_csr__read__h616733; - 12'd323: rVal1__h640775 = csrf_stval_csr; - 12'd324: rVal1__h640775 = sip_csr__read__h616873; - 12'd384: rVal1__h640775 = satp_csr__read__h616936; - 12'd768: rVal1__h640775 = mstatus_csr__read__h617079; - 12'd769: rVal1__h640775 = 64'h800000000014112D; - 12'd770: rVal1__h640775 = medeleg_csr__read__h617227; - 12'd771: rVal1__h640775 = mideleg_csr__read__h617322; - 12'd772: rVal1__h640775 = mie_csr__read__h617446; - 12'd773: rVal1__h640775 = mtvec_csr__read__h617528; - 12'd774: rVal1__h640775 = mcounteren_csr__read__h617620; - 12'd832: rVal1__h640775 = csrf_mscratch_csr; - 12'd833: rVal1__h640775 = csrf_mepc_csr; - 12'd834: rVal1__h640775 = mcause_csr__read__h617875; - 12'd835: rVal1__h640775 = csrf_mtval_csr; - 12'd836: rVal1__h640775 = mip_csr__read__h618108; - 12'd1952: rVal1__h640775 = csrf_rg_tselect; - 12'd1953: rVal1__h640775 = rg_tdata1__read__h619063; - 12'd1954: rVal1__h640775 = csrf_rg_tdata2; - 12'd1955: rVal1__h640775 = csrf_rg_tdata3; + 12'd1: rVal1__h640776 = fflags_csr__read__h616209; + 12'd2: rVal1__h640776 = frm_csr__read__h616220; + 12'd3: rVal1__h640776 = fcsr_csr__read__h616234; + 12'd256: rVal1__h640776 = sstatus_csr__read__h616430; + 12'd260: rVal1__h640776 = sie_csr__read__h616500; + 12'd261: rVal1__h640776 = stvec_csr__read__h616543; + 12'd262: rVal1__h640776 = scounteren_csr__read__h616596; + 12'd320: rVal1__h640776 = csrf_sscratch_csr; + 12'd321: rVal1__h640776 = csrf_sepc_csr; + 12'd322: rVal1__h640776 = scause_csr__read__h616734; + 12'd323: rVal1__h640776 = csrf_stval_csr; + 12'd324: rVal1__h640776 = sip_csr__read__h616874; + 12'd384: rVal1__h640776 = satp_csr__read__h616937; + 12'd768: rVal1__h640776 = mstatus_csr__read__h617080; + 12'd769: rVal1__h640776 = 64'h800000000014112D; + 12'd770: rVal1__h640776 = medeleg_csr__read__h617228; + 12'd771: rVal1__h640776 = mideleg_csr__read__h617323; + 12'd772: rVal1__h640776 = mie_csr__read__h617447; + 12'd773: rVal1__h640776 = mtvec_csr__read__h617529; + 12'd774: rVal1__h640776 = mcounteren_csr__read__h617621; + 12'd832: rVal1__h640776 = csrf_mscratch_csr; + 12'd833: rVal1__h640776 = csrf_mepc_csr; + 12'd834: rVal1__h640776 = mcause_csr__read__h617876; + 12'd835: rVal1__h640776 = csrf_mtval_csr; + 12'd836: rVal1__h640776 = mip_csr__read__h618109; + 12'd1952: rVal1__h640776 = csrf_rg_tselect; + 12'd1953: rVal1__h640776 = rg_tdata1__read__h619064; + 12'd1954: rVal1__h640776 = csrf_rg_tdata2; + 12'd1955: rVal1__h640776 = csrf_rg_tdata3; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h640775 = 64'd0; - 12'd2049: rVal1__h640775 = x_reg_ifc__read__h616338; - 12'd2816, 12'd3072: rVal1__h640775 = n__read__h618212; - 12'd2818, 12'd3074: rVal1__h640775 = n__read__h618403; - 12'd3073: rVal1__h640775 = csrf_time_reg; - default: rVal1__h640775 = 64'b0; + rVal1__h640776 = 64'd0; + 12'd2049: rVal1__h640776 = x_reg_ifc__read__h616339; + 12'd2816, 12'd3072: rVal1__h640776 = n__read__h618213; + 12'd2818, 12'd3074: rVal1__h640776 = n__read__h618404; + 12'd3073: rVal1__h640776 = csrf_time_reg; + default: rVal1__h640776 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h442111 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h442112 = 8'd255; 3'd2: - _theResult___fst_exp__h442111 = + _theResult___fst_exp__h442112 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h442111 = + _theResult___fst_exp__h442112 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h442111 = 8'd254; - default: _theResult___fst_exp__h442111 = 8'd0; + 3'd4: _theResult___fst_exp__h442112 = 8'd254; + default: _theResult___fst_exp__h442112 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h350717 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h350718 = 8'd255; 3'd2: - _theResult___fst_exp__h350717 = + _theResult___fst_exp__h350718 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h350717 = + _theResult___fst_exp__h350718 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h350717 = 8'd254; - default: _theResult___fst_exp__h350717 = 8'd0; + 3'd4: _theResult___fst_exp__h350718 = 8'd254; + default: _theResult___fst_exp__h350718 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h350718 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h350719 = 23'd0; 3'd2: - _theResult___fst_sfd__h350718 = + _theResult___fst_sfd__h350719 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h350718 = + _theResult___fst_sfd__h350719 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h350718 = 23'd8388607; - default: _theResult___fst_sfd__h350718 = 23'd0; + 3'd4: _theResult___fst_sfd__h350719 = 23'd8388607; + default: _theResult___fst_sfd__h350719 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h396416 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h396417 = 8'd255; 3'd2: - _theResult___fst_exp__h396416 = + _theResult___fst_exp__h396417 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h396416 = + _theResult___fst_exp__h396417 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h396416 = 8'd254; - default: _theResult___fst_exp__h396416 = 8'd0; + 3'd4: _theResult___fst_exp__h396417 = 8'd254; + default: _theResult___fst_exp__h396417 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h396417 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h396418 = 23'd0; 3'd2: - _theResult___fst_sfd__h396417 = + _theResult___fst_sfd__h396418 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h396417 = + _theResult___fst_sfd__h396418 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h396417 = 23'd8388607; - default: _theResult___fst_sfd__h396417 = 23'd0; + 3'd4: _theResult___fst_sfd__h396418 = 23'd8388607; + default: _theResult___fst_sfd__h396418 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h442112 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h442113 = 23'd0; 3'd2: - _theResult___fst_sfd__h442112 = + _theResult___fst_sfd__h442113 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h442112 = + _theResult___fst_sfd__h442113 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h442112 = 23'd8388607; - default: _theResult___fst_sfd__h442112 = 23'd0; + 3'd4: _theResult___fst_sfd__h442113 = 23'd8388607; + default: _theResult___fst_sfd__h442113 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -30779,16 +30779,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h707773 = commitStage_commitTrap[35:32]; - default: i__h707773 = 4'd15; + i__h707774 = commitStage_commitTrap[35:32]; + default: i__h707774 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9: - i__h707933 = commitStage_commitTrap[35:32]; - default: i__h707933 = 4'd11; + i__h707934 = commitStage_commitTrap[35:32]; + default: i__h707934 = 4'd11; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -31029,446 +31029,446 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359454 or - _theResult___fst_exp__h367502 or - out_exp__h367947 or _theResult___exp__h367944) + always@(guard__h359455 or + _theResult___fst_exp__h367503 or + out_exp__h367948 or _theResult___exp__h367945) begin - case (guard__h359454) + case (guard__h359455) 2'b0, 2'b01: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 = - _theResult___fst_exp__h367502; + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q25 = + _theResult___fst_exp__h367503; 2'b10: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 = - out_exp__h367947; + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q25 = + out_exp__h367948; 2'b11: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 = - _theResult___exp__h367944; + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q25 = + _theResult___exp__h367945; endcase end - always@(guard__h359454 or - _theResult___fst_exp__h367502 or _theResult___exp__h367944) + always@(guard__h359455 or + _theResult___fst_exp__h367503 or _theResult___exp__h367945) begin - case (guard__h359454) + case (guard__h359455) 2'b0: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26 = - _theResult___fst_exp__h367502; + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q26 = + _theResult___fst_exp__h367503; 2'b01, 2'b10, 2'b11: - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26 = - _theResult___exp__h367944; + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q26 = + _theResult___exp__h367945; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25 or - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26 or + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q25 or + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q26 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or - _theResult___fst_exp__h367502) + _theResult___fst_exp__h367503) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h368022 = - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q25; + _theResult___fst_exp__h368023 = + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q25; 3'd1: - _theResult___fst_exp__h368022 = - CASE_guard59454_0b0_theResult___fst_exp67502_0_ETC__q26; + _theResult___fst_exp__h368023 = + CASE_guard59455_0b0_theResult___fst_exp67503_0_ETC__q26; 3'd2: - _theResult___fst_exp__h368022 = + _theResult___fst_exp__h368023 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628; 3'd3: - _theResult___fst_exp__h368022 = + _theResult___fst_exp__h368023 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630; - 3'd4: _theResult___fst_exp__h368022 = _theResult___fst_exp__h367502; - default: _theResult___fst_exp__h368022 = 8'd0; + 3'd4: _theResult___fst_exp__h368023 = _theResult___fst_exp__h367503; + default: _theResult___fst_exp__h368023 = 8'd0; endcase end - always@(guard__h350745 or - _theResult___fst_exp__h358846 or - out_exp__h359365 or _theResult___exp__h359362) + always@(guard__h350746 or + _theResult___fst_exp__h358847 or + out_exp__h359366 or _theResult___exp__h359363) begin - case (guard__h350745) + case (guard__h350746) 2'b0, 2'b01: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 = - _theResult___fst_exp__h358846; + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q27 = + _theResult___fst_exp__h358847; 2'b10: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 = - out_exp__h359365; + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q27 = + out_exp__h359366; 2'b11: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 = - _theResult___exp__h359362; + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q27 = + _theResult___exp__h359363; endcase end - always@(guard__h350745 or - _theResult___fst_exp__h358846 or _theResult___exp__h359362) + always@(guard__h350746 or + _theResult___fst_exp__h358847 or _theResult___exp__h359363) begin - case (guard__h350745) + case (guard__h350746) 2'b0: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28 = - _theResult___fst_exp__h358846; + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q28 = + _theResult___fst_exp__h358847; 2'b01, 2'b10, 2'b11: - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28 = - _theResult___exp__h359362; + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q28 = + _theResult___exp__h359363; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27 or - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28 or + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q27 or + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q28 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 or - _theResult___fst_exp__h358846) + _theResult___fst_exp__h358847) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h359440 = - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q27; + _theResult___fst_exp__h359441 = + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q27; 3'd1: - _theResult___fst_exp__h359440 = - CASE_guard50745_0b0_theResult___fst_exp58846_0_ETC__q28; + _theResult___fst_exp__h359441 = + CASE_guard50746_0b0_theResult___fst_exp58847_0_ETC__q28; 3'd2: - _theResult___fst_exp__h359440 = + _theResult___fst_exp__h359441 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406; 3'd3: - _theResult___fst_exp__h359440 = + _theResult___fst_exp__h359441 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409; - 3'd4: _theResult___fst_exp__h359440 = _theResult___fst_exp__h358846; - default: _theResult___fst_exp__h359440 = 8'd0; + 3'd4: _theResult___fst_exp__h359441 = _theResult___fst_exp__h358847; + default: _theResult___fst_exp__h359441 = 8'd0; endcase end - always@(guard__h368384 or - _theResult___fst_exp__h376612 or - out_exp__h377131 or _theResult___exp__h377128) + always@(guard__h368385 or + _theResult___fst_exp__h376613 or + out_exp__h377132 or _theResult___exp__h377129) begin - case (guard__h368384) + case (guard__h368385) 2'b0, 2'b01: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 = - _theResult___fst_exp__h376612; + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q33 = + _theResult___fst_exp__h376613; 2'b10: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 = - out_exp__h377131; + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q33 = + out_exp__h377132; 2'b11: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 = - _theResult___exp__h377128; + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q33 = + _theResult___exp__h377129; endcase end - always@(guard__h368384 or - _theResult___fst_exp__h376612 or _theResult___exp__h377128) + always@(guard__h368385 or + _theResult___fst_exp__h376613 or _theResult___exp__h377129) begin - case (guard__h368384) + case (guard__h368385) 2'b0: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34 = - _theResult___fst_exp__h376612; + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q34 = + _theResult___fst_exp__h376613; 2'b01, 2'b10, 2'b11: - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34 = - _theResult___exp__h377128; + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q34 = + _theResult___exp__h377129; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33 or - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34 or + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q33 or + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q34 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 or - _theResult___fst_exp__h376612) + _theResult___fst_exp__h376613) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h377206 = - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q33; + _theResult___fst_exp__h377207 = + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q33; 3'd1: - _theResult___fst_exp__h377206 = - CASE_guard68384_0b0_theResult___fst_exp76612_0_ETC__q34; + _theResult___fst_exp__h377207 = + CASE_guard68385_0b0_theResult___fst_exp76613_0_ETC__q34; 3'd2: - _theResult___fst_exp__h377206 = + _theResult___fst_exp__h377207 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953; 3'd3: - _theResult___fst_exp__h377206 = + _theResult___fst_exp__h377207 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955; - 3'd4: _theResult___fst_exp__h377206 = _theResult___fst_exp__h376612; - default: _theResult___fst_exp__h377206 = 8'd0; + 3'd4: _theResult___fst_exp__h377207 = _theResult___fst_exp__h376613; + default: _theResult___fst_exp__h377207 = 8'd0; endcase end - always@(guard__h377220 or - _theResult___fst_exp__h385297 or - out_exp__h385767 or _theResult___exp__h385764) + always@(guard__h377221 or + _theResult___fst_exp__h385298 or + out_exp__h385768 or _theResult___exp__h385765) begin - case (guard__h377220) + case (guard__h377221) 2'b0, 2'b01: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 = - _theResult___fst_exp__h385297; + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q38 = + _theResult___fst_exp__h385298; 2'b10: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 = - out_exp__h385767; + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q38 = + out_exp__h385768; 2'b11: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 = - _theResult___exp__h385764; + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q38 = + _theResult___exp__h385765; endcase end - always@(guard__h377220 or - _theResult___fst_exp__h385297 or _theResult___exp__h385764) + always@(guard__h377221 or + _theResult___fst_exp__h385298 or _theResult___exp__h385765) begin - case (guard__h377220) + case (guard__h377221) 2'b0: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39 = - _theResult___fst_exp__h385297; + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q39 = + _theResult___fst_exp__h385298; 2'b01, 2'b10, 2'b11: - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39 = - _theResult___exp__h385764; + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q39 = + _theResult___exp__h385765; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38 or - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39 or + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q38 or + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q39 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___fst_exp__h385297) + _theResult___fst_exp__h385298) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h385842 = - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q38; + _theResult___fst_exp__h385843 = + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q38; 3'd1: - _theResult___fst_exp__h385842 = - CASE_guard77220_0b0_theResult___fst_exp85297_0_ETC__q39; + _theResult___fst_exp__h385843 = + CASE_guard77221_0b0_theResult___fst_exp85298_0_ETC__q39; 3'd2: - _theResult___fst_exp__h385842 = + _theResult___fst_exp__h385843 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_exp__h385842 = + _theResult___fst_exp__h385843 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_exp__h385842 = _theResult___fst_exp__h385297; - default: _theResult___fst_exp__h385842 = 8'd0; + 3'd4: _theResult___fst_exp__h385843 = _theResult___fst_exp__h385298; + default: _theResult___fst_exp__h385843 = 8'd0; endcase end - always@(guard__h359454 or - _theResult___snd__h367453 or - out_sfd__h367948 or _theResult___sfd__h367945) + always@(guard__h359455 or + _theResult___snd__h367454 or + out_sfd__h367949 or _theResult___sfd__h367946) begin - case (guard__h359454) + case (guard__h359455) 2'b0, 2'b01: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 = - _theResult___snd__h367453[56:34]; + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q40 = + _theResult___snd__h367454[56:34]; 2'b10: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 = - out_sfd__h367948; + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q40 = + out_sfd__h367949; 2'b11: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 = - _theResult___sfd__h367945; + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q40 = + _theResult___sfd__h367946; endcase end - always@(guard__h359454 or - _theResult___snd__h367453 or _theResult___sfd__h367945) + always@(guard__h359455 or + _theResult___snd__h367454 or _theResult___sfd__h367946) begin - case (guard__h359454) + case (guard__h359455) 2'b0: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41 = - _theResult___snd__h367453[56:34]; + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q41 = + _theResult___snd__h367454[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41 = - _theResult___sfd__h367945; + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q41 = + _theResult___sfd__h367946; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40 or - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41 or + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q40 or + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q41 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or - _theResult___snd__h367453) + _theResult___snd__h367454) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h368023 = - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q40; + _theResult___fst_sfd__h368024 = + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q40; 3'd1: - _theResult___fst_sfd__h368023 = - CASE_guard59454_0b0_theResult___snd67453_BITS__ETC__q41; + _theResult___fst_sfd__h368024 = + CASE_guard59455_0b0_theResult___snd67454_BITS__ETC__q41; 3'd2: - _theResult___fst_sfd__h368023 = + _theResult___fst_sfd__h368024 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072; 3'd3: - _theResult___fst_sfd__h368023 = + _theResult___fst_sfd__h368024 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074; - 3'd4: _theResult___fst_sfd__h368023 = _theResult___snd__h367453[56:34]; - default: _theResult___fst_sfd__h368023 = 23'd0; + 3'd4: _theResult___fst_sfd__h368024 = _theResult___snd__h367454[56:34]; + default: _theResult___fst_sfd__h368024 = 23'd0; endcase end - always@(guard__h350745 or - sfdin__h358840 or out_sfd__h359366 or _theResult___sfd__h359363) + always@(guard__h350746 or + sfdin__h358841 or out_sfd__h359367 or _theResult___sfd__h359364) begin - case (guard__h350745) + case (guard__h350746) 2'b0, 2'b01: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 = - sfdin__h358840[56:34]; + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q42 = + sfdin__h358841[56:34]; 2'b10: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 = - out_sfd__h359366; + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q42 = + out_sfd__h359367; 2'b11: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 = - _theResult___sfd__h359363; + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q42 = + _theResult___sfd__h359364; endcase end - always@(guard__h350745 or sfdin__h358840 or _theResult___sfd__h359363) + always@(guard__h350746 or sfdin__h358841 or _theResult___sfd__h359364) begin - case (guard__h350745) + case (guard__h350746) 2'b0: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43 = - sfdin__h358840[56:34]; + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q43 = + sfdin__h358841[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43 = - _theResult___sfd__h359363; + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q43 = + _theResult___sfd__h359364; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42 or - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43 or + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q42 or + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q43 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or - sfdin__h358840) + sfdin__h358841) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h359441 = - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q42; + _theResult___fst_sfd__h359442 = + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q42; 3'd1: - _theResult___fst_sfd__h359441 = - CASE_guard50745_0b0_sfdin58840_BITS_56_TO_34_0_ETC__q43; + _theResult___fst_sfd__h359442 = + CASE_guard50746_0b0_sfdin58841_BITS_56_TO_34_0_ETC__q43; 3'd2: - _theResult___fst_sfd__h359441 = + _theResult___fst_sfd__h359442 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053; 3'd3: - _theResult___fst_sfd__h359441 = + _theResult___fst_sfd__h359442 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055; - 3'd4: _theResult___fst_sfd__h359441 = sfdin__h358840[56:34]; - default: _theResult___fst_sfd__h359441 = 23'd0; + 3'd4: _theResult___fst_sfd__h359442 = sfdin__h358841[56:34]; + default: _theResult___fst_sfd__h359442 = 23'd0; endcase end - always@(guard__h368384 or - sfdin__h376606 or out_sfd__h377132 or _theResult___sfd__h377129) + always@(guard__h368385 or + sfdin__h376607 or out_sfd__h377133 or _theResult___sfd__h377130) begin - case (guard__h368384) + case (guard__h368385) 2'b0, 2'b01: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 = - sfdin__h376606[56:34]; + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q44 = + sfdin__h376607[56:34]; 2'b10: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 = - out_sfd__h377132; + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q44 = + out_sfd__h377133; 2'b11: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 = - _theResult___sfd__h377129; + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q44 = + _theResult___sfd__h377130; endcase end - always@(guard__h368384 or sfdin__h376606 or _theResult___sfd__h377129) + always@(guard__h368385 or sfdin__h376607 or _theResult___sfd__h377130) begin - case (guard__h368384) + case (guard__h368385) 2'b0: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45 = - sfdin__h376606[56:34]; + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q45 = + sfdin__h376607[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45 = - _theResult___sfd__h377129; + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q45 = + _theResult___sfd__h377130; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44 or - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45 or + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q44 or + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q45 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 or - sfdin__h376606) + sfdin__h376607) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h377207 = - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q44; + _theResult___fst_sfd__h377208 = + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q44; 3'd1: - _theResult___fst_sfd__h377207 = - CASE_guard68384_0b0_sfdin76606_BITS_56_TO_34_0_ETC__q45; + _theResult___fst_sfd__h377208 = + CASE_guard68385_0b0_sfdin76607_BITS_56_TO_34_0_ETC__q45; 3'd2: - _theResult___fst_sfd__h377207 = + _theResult___fst_sfd__h377208 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099; 3'd3: - _theResult___fst_sfd__h377207 = + _theResult___fst_sfd__h377208 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101; - 3'd4: _theResult___fst_sfd__h377207 = sfdin__h376606[56:34]; - default: _theResult___fst_sfd__h377207 = 23'd0; + 3'd4: _theResult___fst_sfd__h377208 = sfdin__h376607[56:34]; + default: _theResult___fst_sfd__h377208 = 23'd0; endcase end - always@(guard__h377220 or - _theResult___snd__h385243 or - out_sfd__h385768 or _theResult___sfd__h385765) + always@(guard__h377221 or + _theResult___snd__h385244 or + out_sfd__h385769 or _theResult___sfd__h385766) begin - case (guard__h377220) + case (guard__h377221) 2'b0, 2'b01: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 = - _theResult___snd__h385243[56:34]; + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q46 = + _theResult___snd__h385244[56:34]; 2'b10: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 = - out_sfd__h385768; + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q46 = + out_sfd__h385769; 2'b11: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 = - _theResult___sfd__h385765; + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q46 = + _theResult___sfd__h385766; endcase end - always@(guard__h377220 or - _theResult___snd__h385243 or _theResult___sfd__h385765) + always@(guard__h377221 or + _theResult___snd__h385244 or _theResult___sfd__h385766) begin - case (guard__h377220) + case (guard__h377221) 2'b0: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47 = - _theResult___snd__h385243[56:34]; + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q47 = + _theResult___snd__h385244[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47 = - _theResult___sfd__h385765; + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q47 = + _theResult___sfd__h385766; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46 or - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47 or + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q46 or + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q47 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or - _theResult___snd__h385243) + _theResult___snd__h385244) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h385843 = - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q46; + _theResult___fst_sfd__h385844 = + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q46; 3'd1: - _theResult___fst_sfd__h385843 = - CASE_guard77220_0b0_theResult___snd85243_BITS__ETC__q47; + _theResult___fst_sfd__h385844 = + CASE_guard77221_0b0_theResult___snd85244_BITS__ETC__q47; 3'd2: - _theResult___fst_sfd__h385843 = + _theResult___fst_sfd__h385844 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118; 3'd3: - _theResult___fst_sfd__h385843 = + _theResult___fst_sfd__h385844 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120; - 3'd4: _theResult___fst_sfd__h385843 = _theResult___snd__h385243[56:34]; - default: _theResult___fst_sfd__h385843 = 23'd0; + 3'd4: _theResult___fst_sfd__h385844 = _theResult___snd__h385244[56:34]; + default: _theResult___fst_sfd__h385844 = 23'd0; endcase end - always@(guard__h350745 or + always@(guard__h350746 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350745) + case (guard__h350746) 2'b0, 2'b01, 2'b10: - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + CASE_guard50746_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = - guard__h350745 == 2'b11 && + CASE_guard50746_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 = + guard__h350746 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or - guard__h350745) + CASE_guard50746_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or + guard__h350746) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - CASE_guard50745_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; + CASE_guard50746_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = - (guard__h350745 == 2'b0) ? + (guard__h350746 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h350745 == 2'b01 || guard__h350745 == 2'b10 || - guard__h350745 == 2'b11) && + (guard__h350746 == 2'b01 || guard__h350746 == 2'b10 || + guard__h350746 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 = @@ -31479,34 +31479,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h350745 or + always@(guard__h350746 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350745) + case (guard__h350746) 2'b0, 2'b01, 2'b10: - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + CASE_guard50746_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = - guard__h350745 != 2'b11 || + CASE_guard50746_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 = + guard__h350746 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or - guard__h350745) + CASE_guard50746_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or + guard__h350746) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - CASE_guard50745_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; + CASE_guard50746_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = - (guard__h350745 == 2'b0) ? + (guard__h350746 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h350745 != 2'b01 && guard__h350745 != 2'b10 && - guard__h350745 != 2'b11 || + guard__h350746 != 2'b01 && guard__h350746 != 2'b10 && + guard__h350746 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 = @@ -31517,34 +31517,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359454 or + always@(guard__h359455 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359454) + case (guard__h359455) 2'b0, 2'b01, 2'b10: - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + CASE_guard59455_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = - guard__h359454 == 2'b11 && + CASE_guard59455_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 = + guard__h359455 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or - guard__h359454) + CASE_guard59455_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or + guard__h359455) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - CASE_guard59454_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; + CASE_guard59455_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = - (guard__h359454 == 2'b0) ? + (guard__h359455 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h359454 == 2'b01 || guard__h359454 == 2'b10 || - guard__h359454 == 2'b11) && + (guard__h359455 == 2'b01 || guard__h359455 == 2'b10 || + guard__h359455 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 = @@ -31555,34 +31555,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359454 or + always@(guard__h359455 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359454) + case (guard__h359455) 2'b0, 2'b01, 2'b10: - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + CASE_guard59455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = - guard__h359454 != 2'b11 || + CASE_guard59455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 = + guard__h359455 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or - guard__h359454) + CASE_guard59455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or + guard__h359455) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - CASE_guard59454_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; + CASE_guard59455_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = - (guard__h359454 == 2'b0) ? + (guard__h359455 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h359454 != 2'b01 && guard__h359454 != 2'b10 && - guard__h359454 != 2'b11 || + guard__h359455 != 2'b01 && guard__h359455 != 2'b10 && + guard__h359455 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 = @@ -31593,34 +31593,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368384 or + always@(guard__h368385 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368384) + case (guard__h368385) 2'b0, 2'b01, 2'b10: - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = - guard__h368384 == 2'b11 && + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 = + guard__h368385 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or - guard__h368384) + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or + guard__h368385) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = - (guard__h368384 == 2'b0) ? + (guard__h368385 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h368384 == 2'b01 || guard__h368384 == 2'b10 || - guard__h368384 == 2'b11) && + (guard__h368385 == 2'b01 || guard__h368385 == 2'b10 || + guard__h368385 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 = @@ -31631,34 +31631,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368384 or + always@(guard__h368385 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368384) + case (guard__h368385) 2'b0, 2'b01, 2'b10: - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = - guard__h368384 != 2'b11 || + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 = + guard__h368385 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or - guard__h368384) + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or + guard__h368385) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = - (guard__h368384 == 2'b0) ? + (guard__h368385 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h368384 != 2'b01 && guard__h368384 != 2'b10 && - guard__h368384 != 2'b11 || + guard__h368385 != 2'b01 && guard__h368385 != 2'b10 && + guard__h368385 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 = @@ -31669,34 +31669,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h377220 or + always@(guard__h377221 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h377220) + case (guard__h377221) 2'b0, 2'b01, 2'b10: - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + CASE_guard77221_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = - guard__h377220 == 2'b11 && + CASE_guard77221_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 = + guard__h377221 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or - guard__h377220) + CASE_guard77221_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or + guard__h377221) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - CASE_guard77220_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; + CASE_guard77221_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = - (guard__h377220 == 2'b0) ? + (guard__h377221 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h377220 == 2'b01 || guard__h377220 == 2'b10 || - guard__h377220 == 2'b11) && + (guard__h377221 == 2'b01 || guard__h377221 == 2'b10 || + guard__h377221 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 = @@ -31707,34 +31707,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h377220 or + always@(guard__h377221 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h377220) + case (guard__h377221) 2'b0, 2'b01, 2'b10: - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + CASE_guard77221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = - guard__h377220 != 2'b11 || + CASE_guard77221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 = + guard__h377221 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or - guard__h377220) + CASE_guard77221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or + guard__h377221) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - CASE_guard77220_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; + CASE_guard77221_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = - (guard__h377220 == 2'b0) ? + (guard__h377221 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h377220 != 2'b01 && guard__h377220 != 2'b10 && - guard__h377220 != 2'b11 || + guard__h377221 != 2'b01 && guard__h377221 != 2'b10 && + guard__h377221 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 = @@ -31758,446 +31758,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h405151 or - _theResult___fst_exp__h413199 or - out_exp__h413644 or _theResult___exp__h413641) + always@(guard__h405152 or + _theResult___fst_exp__h413200 or + out_exp__h413645 or _theResult___exp__h413642) begin - case (guard__h405151) + case (guard__h405152) 2'b0, 2'b01: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 = - _theResult___fst_exp__h413199; + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q60 = + _theResult___fst_exp__h413200; 2'b10: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 = - out_exp__h413644; + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q60 = + out_exp__h413645; 2'b11: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 = - _theResult___exp__h413641; + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q60 = + _theResult___exp__h413642; endcase end - always@(guard__h405151 or - _theResult___fst_exp__h413199 or _theResult___exp__h413641) + always@(guard__h405152 or + _theResult___fst_exp__h413200 or _theResult___exp__h413642) begin - case (guard__h405151) + case (guard__h405152) 2'b0: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61 = - _theResult___fst_exp__h413199; + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q61 = + _theResult___fst_exp__h413200; 2'b01, 2'b10, 2'b11: - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61 = - _theResult___exp__h413641; + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q61 = + _theResult___exp__h413642; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60 or - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61 or + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q60 or + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q61 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 or - _theResult___fst_exp__h413199) + _theResult___fst_exp__h413200) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h413719 = - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q60; + _theResult___fst_exp__h413720 = + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q60; 3'd1: - _theResult___fst_exp__h413719 = - CASE_guard05151_0b0_theResult___fst_exp13199_0_ETC__q61; + _theResult___fst_exp__h413720 = + CASE_guard05152_0b0_theResult___fst_exp13200_0_ETC__q61; 3'd2: - _theResult___fst_exp__h413719 = + _theResult___fst_exp__h413720 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020; 3'd3: - _theResult___fst_exp__h413719 = + _theResult___fst_exp__h413720 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022; - 3'd4: _theResult___fst_exp__h413719 = _theResult___fst_exp__h413199; - default: _theResult___fst_exp__h413719 = 8'd0; + 3'd4: _theResult___fst_exp__h413720 = _theResult___fst_exp__h413200; + default: _theResult___fst_exp__h413720 = 8'd0; endcase end - always@(guard__h396444 or - _theResult___fst_exp__h404543 or - out_exp__h405062 or _theResult___exp__h405059) + always@(guard__h396445 or + _theResult___fst_exp__h404544 or + out_exp__h405063 or _theResult___exp__h405060) begin - case (guard__h396444) + case (guard__h396445) 2'b0, 2'b01: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 = - _theResult___fst_exp__h404543; + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q62 = + _theResult___fst_exp__h404544; 2'b10: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 = - out_exp__h405062; + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q62 = + out_exp__h405063; 2'b11: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 = - _theResult___exp__h405059; + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q62 = + _theResult___exp__h405060; endcase end - always@(guard__h396444 or - _theResult___fst_exp__h404543 or _theResult___exp__h405059) + always@(guard__h396445 or + _theResult___fst_exp__h404544 or _theResult___exp__h405060) begin - case (guard__h396444) + case (guard__h396445) 2'b0: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63 = - _theResult___fst_exp__h404543; + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q63 = + _theResult___fst_exp__h404544; 2'b01, 2'b10, 2'b11: - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63 = - _theResult___exp__h405059; + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q63 = + _theResult___exp__h405060; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62 or - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63 or + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q62 or + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q63 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 or - _theResult___fst_exp__h404543) + _theResult___fst_exp__h404544) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h405137 = - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q62; + _theResult___fst_exp__h405138 = + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q62; 3'd1: - _theResult___fst_exp__h405137 = - CASE_guard96444_0b0_theResult___fst_exp04543_0_ETC__q63; + _theResult___fst_exp__h405138 = + CASE_guard96445_0b0_theResult___fst_exp04544_0_ETC__q63; 3'd2: - _theResult___fst_exp__h405137 = + _theResult___fst_exp__h405138 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798; 3'd3: - _theResult___fst_exp__h405137 = + _theResult___fst_exp__h405138 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801; - 3'd4: _theResult___fst_exp__h405137 = _theResult___fst_exp__h404543; - default: _theResult___fst_exp__h405137 = 8'd0; + 3'd4: _theResult___fst_exp__h405138 = _theResult___fst_exp__h404544; + default: _theResult___fst_exp__h405138 = 8'd0; endcase end - always@(guard__h414081 or - _theResult___fst_exp__h422309 or - out_exp__h422828 or _theResult___exp__h422825) + always@(guard__h414082 or + _theResult___fst_exp__h422310 or + out_exp__h422829 or _theResult___exp__h422826) begin - case (guard__h414081) + case (guard__h414082) 2'b0, 2'b01: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 = - _theResult___fst_exp__h422309; + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q68 = + _theResult___fst_exp__h422310; 2'b10: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 = - out_exp__h422828; + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q68 = + out_exp__h422829; 2'b11: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 = - _theResult___exp__h422825; + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q68 = + _theResult___exp__h422826; endcase end - always@(guard__h414081 or - _theResult___fst_exp__h422309 or _theResult___exp__h422825) + always@(guard__h414082 or + _theResult___fst_exp__h422310 or _theResult___exp__h422826) begin - case (guard__h414081) + case (guard__h414082) 2'b0: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69 = - _theResult___fst_exp__h422309; + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q69 = + _theResult___fst_exp__h422310; 2'b01, 2'b10, 2'b11: - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69 = - _theResult___exp__h422825; + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q69 = + _theResult___exp__h422826; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68 or - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69 or + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q68 or + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q69 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 or - _theResult___fst_exp__h422309) + _theResult___fst_exp__h422310) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h422903 = - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q68; + _theResult___fst_exp__h422904 = + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q68; 3'd1: - _theResult___fst_exp__h422903 = - CASE_guard14081_0b0_theResult___fst_exp22309_0_ETC__q69; + _theResult___fst_exp__h422904 = + CASE_guard14082_0b0_theResult___fst_exp22310_0_ETC__q69; 3'd2: - _theResult___fst_exp__h422903 = + _theResult___fst_exp__h422904 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345; 3'd3: - _theResult___fst_exp__h422903 = + _theResult___fst_exp__h422904 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347; - 3'd4: _theResult___fst_exp__h422903 = _theResult___fst_exp__h422309; - default: _theResult___fst_exp__h422903 = 8'd0; + 3'd4: _theResult___fst_exp__h422904 = _theResult___fst_exp__h422310; + default: _theResult___fst_exp__h422904 = 8'd0; endcase end - always@(guard__h422917 or - _theResult___fst_exp__h430994 or - out_exp__h431464 or _theResult___exp__h431461) + always@(guard__h422918 or + _theResult___fst_exp__h430995 or + out_exp__h431465 or _theResult___exp__h431462) begin - case (guard__h422917) + case (guard__h422918) 2'b0, 2'b01: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 = - _theResult___fst_exp__h430994; + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q73 = + _theResult___fst_exp__h430995; 2'b10: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 = - out_exp__h431464; + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q73 = + out_exp__h431465; 2'b11: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 = - _theResult___exp__h431461; + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q73 = + _theResult___exp__h431462; endcase end - always@(guard__h422917 or - _theResult___fst_exp__h430994 or _theResult___exp__h431461) + always@(guard__h422918 or + _theResult___fst_exp__h430995 or _theResult___exp__h431462) begin - case (guard__h422917) + case (guard__h422918) 2'b0: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74 = - _theResult___fst_exp__h430994; + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q74 = + _theResult___fst_exp__h430995; 2'b01, 2'b10, 2'b11: - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74 = - _theResult___exp__h431461; + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q74 = + _theResult___exp__h431462; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73 or - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74 or + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q73 or + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q74 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___fst_exp__h430994) + _theResult___fst_exp__h430995) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h431539 = - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q73; + _theResult___fst_exp__h431540 = + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q73; 3'd1: - _theResult___fst_exp__h431539 = - CASE_guard22917_0b0_theResult___fst_exp30994_0_ETC__q74; + _theResult___fst_exp__h431540 = + CASE_guard22918_0b0_theResult___fst_exp30995_0_ETC__q74; 3'd2: - _theResult___fst_exp__h431539 = + _theResult___fst_exp__h431540 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_exp__h431539 = + _theResult___fst_exp__h431540 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_exp__h431539 = _theResult___fst_exp__h430994; - default: _theResult___fst_exp__h431539 = 8'd0; + 3'd4: _theResult___fst_exp__h431540 = _theResult___fst_exp__h430995; + default: _theResult___fst_exp__h431540 = 8'd0; endcase end - always@(guard__h405151 or - _theResult___snd__h413150 or - out_sfd__h413645 or _theResult___sfd__h413642) + always@(guard__h405152 or + _theResult___snd__h413151 or + out_sfd__h413646 or _theResult___sfd__h413643) begin - case (guard__h405151) + case (guard__h405152) 2'b0, 2'b01: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 = - _theResult___snd__h413150[56:34]; + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q75 = + _theResult___snd__h413151[56:34]; 2'b10: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 = - out_sfd__h413645; + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q75 = + out_sfd__h413646; 2'b11: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 = - _theResult___sfd__h413642; + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q75 = + _theResult___sfd__h413643; endcase end - always@(guard__h405151 or - _theResult___snd__h413150 or _theResult___sfd__h413642) + always@(guard__h405152 or + _theResult___snd__h413151 or _theResult___sfd__h413643) begin - case (guard__h405151) + case (guard__h405152) 2'b0: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76 = - _theResult___snd__h413150[56:34]; + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q76 = + _theResult___snd__h413151[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76 = - _theResult___sfd__h413642; + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q76 = + _theResult___sfd__h413643; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75 or - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76 or + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q75 or + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q76 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or - _theResult___snd__h413150) + _theResult___snd__h413151) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h413720 = - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q75; + _theResult___fst_sfd__h413721 = + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q75; 3'd1: - _theResult___fst_sfd__h413720 = - CASE_guard05151_0b0_theResult___snd13150_BITS__ETC__q76; + _theResult___fst_sfd__h413721 = + CASE_guard05152_0b0_theResult___snd13151_BITS__ETC__q76; 3'd2: - _theResult___fst_sfd__h413720 = + _theResult___fst_sfd__h413721 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464; 3'd3: - _theResult___fst_sfd__h413720 = + _theResult___fst_sfd__h413721 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466; - 3'd4: _theResult___fst_sfd__h413720 = _theResult___snd__h413150[56:34]; - default: _theResult___fst_sfd__h413720 = 23'd0; + 3'd4: _theResult___fst_sfd__h413721 = _theResult___snd__h413151[56:34]; + default: _theResult___fst_sfd__h413721 = 23'd0; endcase end - always@(guard__h396444 or - sfdin__h404537 or out_sfd__h405063 or _theResult___sfd__h405060) + always@(guard__h396445 or + sfdin__h404538 or out_sfd__h405064 or _theResult___sfd__h405061) begin - case (guard__h396444) + case (guard__h396445) 2'b0, 2'b01: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 = - sfdin__h404537[56:34]; + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q77 = + sfdin__h404538[56:34]; 2'b10: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 = - out_sfd__h405063; + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q77 = + out_sfd__h405064; 2'b11: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 = - _theResult___sfd__h405060; + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q77 = + _theResult___sfd__h405061; endcase end - always@(guard__h396444 or sfdin__h404537 or _theResult___sfd__h405060) + always@(guard__h396445 or sfdin__h404538 or _theResult___sfd__h405061) begin - case (guard__h396444) + case (guard__h396445) 2'b0: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78 = - sfdin__h404537[56:34]; + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q78 = + sfdin__h404538[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78 = - _theResult___sfd__h405060; + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q78 = + _theResult___sfd__h405061; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77 or - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78 or + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q77 or + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q78 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or - sfdin__h404537) + sfdin__h404538) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h405138 = - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q77; + _theResult___fst_sfd__h405139 = + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q77; 3'd1: - _theResult___fst_sfd__h405138 = - CASE_guard96444_0b0_sfdin04537_BITS_56_TO_34_0_ETC__q78; + _theResult___fst_sfd__h405139 = + CASE_guard96445_0b0_sfdin04538_BITS_56_TO_34_0_ETC__q78; 3'd2: - _theResult___fst_sfd__h405138 = + _theResult___fst_sfd__h405139 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445; 3'd3: - _theResult___fst_sfd__h405138 = + _theResult___fst_sfd__h405139 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447; - 3'd4: _theResult___fst_sfd__h405138 = sfdin__h404537[56:34]; - default: _theResult___fst_sfd__h405138 = 23'd0; + 3'd4: _theResult___fst_sfd__h405139 = sfdin__h404538[56:34]; + default: _theResult___fst_sfd__h405139 = 23'd0; endcase end - always@(guard__h414081 or - sfdin__h422303 or out_sfd__h422829 or _theResult___sfd__h422826) + always@(guard__h414082 or + sfdin__h422304 or out_sfd__h422830 or _theResult___sfd__h422827) begin - case (guard__h414081) + case (guard__h414082) 2'b0, 2'b01: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 = - sfdin__h422303[56:34]; + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q79 = + sfdin__h422304[56:34]; 2'b10: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 = - out_sfd__h422829; + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q79 = + out_sfd__h422830; 2'b11: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 = - _theResult___sfd__h422826; + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q79 = + _theResult___sfd__h422827; endcase end - always@(guard__h414081 or sfdin__h422303 or _theResult___sfd__h422826) + always@(guard__h414082 or sfdin__h422304 or _theResult___sfd__h422827) begin - case (guard__h414081) + case (guard__h414082) 2'b0: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80 = - sfdin__h422303[56:34]; + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q80 = + sfdin__h422304[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80 = - _theResult___sfd__h422826; + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q80 = + _theResult___sfd__h422827; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79 or - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80 or + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q79 or + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q80 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 or - sfdin__h422303) + sfdin__h422304) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h422904 = - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q79; + _theResult___fst_sfd__h422905 = + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q79; 3'd1: - _theResult___fst_sfd__h422904 = - CASE_guard14081_0b0_sfdin22303_BITS_56_TO_34_0_ETC__q80; + _theResult___fst_sfd__h422905 = + CASE_guard14082_0b0_sfdin22304_BITS_56_TO_34_0_ETC__q80; 3'd2: - _theResult___fst_sfd__h422904 = + _theResult___fst_sfd__h422905 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491; 3'd3: - _theResult___fst_sfd__h422904 = + _theResult___fst_sfd__h422905 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493; - 3'd4: _theResult___fst_sfd__h422904 = sfdin__h422303[56:34]; - default: _theResult___fst_sfd__h422904 = 23'd0; + 3'd4: _theResult___fst_sfd__h422905 = sfdin__h422304[56:34]; + default: _theResult___fst_sfd__h422905 = 23'd0; endcase end - always@(guard__h422917 or - _theResult___snd__h430940 or - out_sfd__h431465 or _theResult___sfd__h431462) + always@(guard__h422918 or + _theResult___snd__h430941 or + out_sfd__h431466 or _theResult___sfd__h431463) begin - case (guard__h422917) + case (guard__h422918) 2'b0, 2'b01: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 = - _theResult___snd__h430940[56:34]; + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q81 = + _theResult___snd__h430941[56:34]; 2'b10: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 = - out_sfd__h431465; + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q81 = + out_sfd__h431466; 2'b11: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 = - _theResult___sfd__h431462; + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q81 = + _theResult___sfd__h431463; endcase end - always@(guard__h422917 or - _theResult___snd__h430940 or _theResult___sfd__h431462) + always@(guard__h422918 or + _theResult___snd__h430941 or _theResult___sfd__h431463) begin - case (guard__h422917) + case (guard__h422918) 2'b0: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82 = - _theResult___snd__h430940[56:34]; + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q82 = + _theResult___snd__h430941[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82 = - _theResult___sfd__h431462; + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q82 = + _theResult___sfd__h431463; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81 or - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82 or + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q81 or + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q82 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 or - _theResult___snd__h430940) + _theResult___snd__h430941) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h431540 = - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q81; + _theResult___fst_sfd__h431541 = + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q81; 3'd1: - _theResult___fst_sfd__h431540 = - CASE_guard22917_0b0_theResult___snd30940_BITS__ETC__q82; + _theResult___fst_sfd__h431541 = + CASE_guard22918_0b0_theResult___snd30941_BITS__ETC__q82; 3'd2: - _theResult___fst_sfd__h431540 = + _theResult___fst_sfd__h431541 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510; 3'd3: - _theResult___fst_sfd__h431540 = + _theResult___fst_sfd__h431541 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512; - 3'd4: _theResult___fst_sfd__h431540 = _theResult___snd__h430940[56:34]; - default: _theResult___fst_sfd__h431540 = 23'd0; + 3'd4: _theResult___fst_sfd__h431541 = _theResult___snd__h430941[56:34]; + default: _theResult___fst_sfd__h431541 = 23'd0; endcase end - always@(guard__h396444 or + always@(guard__h396445 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396444) + case (guard__h396445) 2'b0, 2'b01, 2'b10: - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + CASE_guard96445_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = - guard__h396444 == 2'b11 && + CASE_guard96445_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 = + guard__h396445 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or - guard__h396444) + CASE_guard96445_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or + guard__h396445) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - CASE_guard96444_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; + CASE_guard96445_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = - (guard__h396444 == 2'b0) ? + (guard__h396445 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h396444 == 2'b01 || guard__h396444 == 2'b10 || - guard__h396444 == 2'b11) && + (guard__h396445 == 2'b01 || guard__h396445 == 2'b10 || + guard__h396445 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 = @@ -32208,34 +32208,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h396444 or + always@(guard__h396445 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396444) + case (guard__h396445) 2'b0, 2'b01, 2'b10: - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = + CASE_guard96445_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = - guard__h396444 != 2'b11 || + CASE_guard96445_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 = + guard__h396445 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or - guard__h396444) + CASE_guard96445_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or + guard__h396445) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - CASE_guard96444_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84; + CASE_guard96445_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = - (guard__h396444 == 2'b0) ? + (guard__h396445 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h396444 != 2'b01 && guard__h396444 != 2'b10 && - guard__h396444 != 2'b11 || + guard__h396445 != 2'b01 && guard__h396445 != 2'b10 && + guard__h396445 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 = @@ -32246,34 +32246,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h405151 or + always@(guard__h405152 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h405151) + case (guard__h405152) 2'b0, 2'b01, 2'b10: - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + CASE_guard05152_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = - guard__h405151 == 2'b11 && + CASE_guard05152_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 = + guard__h405152 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or - guard__h405151) + CASE_guard05152_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or + guard__h405152) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - CASE_guard05151_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85; + CASE_guard05152_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = - (guard__h405151 == 2'b0) ? + (guard__h405152 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h405151 == 2'b01 || guard__h405151 == 2'b10 || - guard__h405151 == 2'b11) && + (guard__h405152 == 2'b01 || guard__h405152 == 2'b10 || + guard__h405152 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 = @@ -32284,34 +32284,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h405151 or + always@(guard__h405152 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h405151) + case (guard__h405152) 2'b0, 2'b01, 2'b10: - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + CASE_guard05152_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = - guard__h405151 != 2'b11 || + CASE_guard05152_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 = + guard__h405152 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or - guard__h405151) + CASE_guard05152_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or + guard__h405152) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - CASE_guard05151_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; + CASE_guard05152_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = - (guard__h405151 == 2'b0) ? + (guard__h405152 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h405151 != 2'b01 && guard__h405151 != 2'b10 && - guard__h405151 != 2'b11 || + guard__h405152 != 2'b01 && guard__h405152 != 2'b10 && + guard__h405152 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 = @@ -32322,34 +32322,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h414081 or + always@(guard__h414082 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h414081) + case (guard__h414082) 2'b0, 2'b01, 2'b10: - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + CASE_guard14082_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = - guard__h414081 == 2'b11 && + CASE_guard14082_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 = + guard__h414082 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or - guard__h414081) + CASE_guard14082_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or + guard__h414082) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - CASE_guard14081_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; + CASE_guard14082_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = - (guard__h414081 == 2'b0) ? + (guard__h414082 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h414081 == 2'b01 || guard__h414081 == 2'b10 || - guard__h414081 == 2'b11) && + (guard__h414082 == 2'b01 || guard__h414082 == 2'b10 || + guard__h414082 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 = @@ -32360,34 +32360,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h414081 or + always@(guard__h414082 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h414081) + case (guard__h414082) 2'b0, 2'b01, 2'b10: - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = + CASE_guard14082_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = - guard__h414081 != 2'b11 || + CASE_guard14082_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 = + guard__h414082 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or - guard__h414081) + CASE_guard14082_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or + guard__h414082) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - CASE_guard14081_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; + CASE_guard14082_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = - (guard__h414081 == 2'b0) ? + (guard__h414082 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h414081 != 2'b01 && guard__h414081 != 2'b10 && - guard__h414081 != 2'b11 || + guard__h414082 != 2'b01 && guard__h414082 != 2'b10 && + guard__h414082 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 = @@ -32398,34 +32398,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422917 or + always@(guard__h422918 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422917) + case (guard__h422918) 2'b0, 2'b01, 2'b10: - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + CASE_guard22918_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = - guard__h422917 == 2'b11 && + CASE_guard22918_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 = + guard__h422918 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or - guard__h422917) + CASE_guard22918_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or + guard__h422918) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - CASE_guard22917_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; + CASE_guard22918_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = - (guard__h422917 == 2'b0) ? + (guard__h422918 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h422917 == 2'b01 || guard__h422917 == 2'b10 || - guard__h422917 == 2'b11) && + (guard__h422918 == 2'b01 || guard__h422918 == 2'b10 || + guard__h422918 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 = @@ -32436,34 +32436,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422917 or + always@(guard__h422918 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422917) + case (guard__h422918) 2'b0, 2'b01, 2'b10: - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + CASE_guard22918_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = - guard__h422917 != 2'b11 || + CASE_guard22918_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 = + guard__h422918 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or - guard__h422917) + CASE_guard22918_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or + guard__h422918) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - CASE_guard22917_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; + CASE_guard22918_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = - (guard__h422917 == 2'b0) ? + (guard__h422918 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h422917 != 2'b01 && guard__h422917 != 2'b10 && - guard__h422917 != 2'b11 || + guard__h422918 != 2'b01 && guard__h422918 != 2'b10 && + guard__h422918 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 = @@ -32500,446 +32500,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h450846 or - _theResult___fst_exp__h458894 or - out_exp__h459339 or _theResult___exp__h459336) + always@(guard__h450847 or + _theResult___fst_exp__h458895 or + out_exp__h459340 or _theResult___exp__h459337) begin - case (guard__h450846) + case (guard__h450847) 2'b0, 2'b01: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 = - _theResult___fst_exp__h458894; + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q95 = + _theResult___fst_exp__h458895; 2'b10: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 = - out_exp__h459339; + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q95 = + out_exp__h459340; 2'b11: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 = - _theResult___exp__h459336; + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q95 = + _theResult___exp__h459337; endcase end - always@(guard__h450846 or - _theResult___fst_exp__h458894 or _theResult___exp__h459336) + always@(guard__h450847 or + _theResult___fst_exp__h458895 or _theResult___exp__h459337) begin - case (guard__h450846) + case (guard__h450847) 2'b0: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96 = - _theResult___fst_exp__h458894; + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q96 = + _theResult___fst_exp__h458895; 2'b01, 2'b10, 2'b11: - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96 = - _theResult___exp__h459336; + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q96 = + _theResult___exp__h459337; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95 or - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96 or + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q95 or + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q96 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 or - _theResult___fst_exp__h458894) + _theResult___fst_exp__h458895) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h459414 = - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q95; + _theResult___fst_exp__h459415 = + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q95; 3'd1: - _theResult___fst_exp__h459414 = - CASE_guard50846_0b0_theResult___fst_exp58894_0_ETC__q96; + _theResult___fst_exp__h459415 = + CASE_guard50847_0b0_theResult___fst_exp58895_0_ETC__q96; 3'd2: - _theResult___fst_exp__h459414 = + _theResult___fst_exp__h459415 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412; 3'd3: - _theResult___fst_exp__h459414 = + _theResult___fst_exp__h459415 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414; - 3'd4: _theResult___fst_exp__h459414 = _theResult___fst_exp__h458894; - default: _theResult___fst_exp__h459414 = 8'd0; + 3'd4: _theResult___fst_exp__h459415 = _theResult___fst_exp__h458895; + default: _theResult___fst_exp__h459415 = 8'd0; endcase end - always@(guard__h442139 or - _theResult___fst_exp__h450238 or - out_exp__h450757 or _theResult___exp__h450754) + always@(guard__h442140 or + _theResult___fst_exp__h450239 or + out_exp__h450758 or _theResult___exp__h450755) begin - case (guard__h442139) + case (guard__h442140) 2'b0, 2'b01: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 = - _theResult___fst_exp__h450238; + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q97 = + _theResult___fst_exp__h450239; 2'b10: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 = - out_exp__h450757; + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q97 = + out_exp__h450758; 2'b11: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 = - _theResult___exp__h450754; + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q97 = + _theResult___exp__h450755; endcase end - always@(guard__h442139 or - _theResult___fst_exp__h450238 or _theResult___exp__h450754) + always@(guard__h442140 or + _theResult___fst_exp__h450239 or _theResult___exp__h450755) begin - case (guard__h442139) + case (guard__h442140) 2'b0: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98 = - _theResult___fst_exp__h450238; + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q98 = + _theResult___fst_exp__h450239; 2'b01, 2'b10, 2'b11: - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98 = - _theResult___exp__h450754; + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q98 = + _theResult___exp__h450755; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97 or - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98 or + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q97 or + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q98 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 or - _theResult___fst_exp__h450238) + _theResult___fst_exp__h450239) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h450832 = - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q97; + _theResult___fst_exp__h450833 = + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q97; 3'd1: - _theResult___fst_exp__h450832 = - CASE_guard42139_0b0_theResult___fst_exp50238_0_ETC__q98; + _theResult___fst_exp__h450833 = + CASE_guard42140_0b0_theResult___fst_exp50239_0_ETC__q98; 3'd2: - _theResult___fst_exp__h450832 = + _theResult___fst_exp__h450833 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190; 3'd3: - _theResult___fst_exp__h450832 = + _theResult___fst_exp__h450833 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193; - 3'd4: _theResult___fst_exp__h450832 = _theResult___fst_exp__h450238; - default: _theResult___fst_exp__h450832 = 8'd0; + 3'd4: _theResult___fst_exp__h450833 = _theResult___fst_exp__h450239; + default: _theResult___fst_exp__h450833 = 8'd0; endcase end - always@(guard__h459776 or - _theResult___fst_exp__h468004 or - out_exp__h468523 or _theResult___exp__h468520) + always@(guard__h459777 or + _theResult___fst_exp__h468005 or + out_exp__h468524 or _theResult___exp__h468521) begin - case (guard__h459776) + case (guard__h459777) 2'b0, 2'b01: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 = - _theResult___fst_exp__h468004; + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q103 = + _theResult___fst_exp__h468005; 2'b10: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 = - out_exp__h468523; + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q103 = + out_exp__h468524; 2'b11: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 = - _theResult___exp__h468520; + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q103 = + _theResult___exp__h468521; endcase end - always@(guard__h459776 or - _theResult___fst_exp__h468004 or _theResult___exp__h468520) + always@(guard__h459777 or + _theResult___fst_exp__h468005 or _theResult___exp__h468521) begin - case (guard__h459776) + case (guard__h459777) 2'b0: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104 = - _theResult___fst_exp__h468004; + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q104 = + _theResult___fst_exp__h468005; 2'b01, 2'b10, 2'b11: - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104 = - _theResult___exp__h468520; + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q104 = + _theResult___exp__h468521; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103 or - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104 or + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q103 or + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q104 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 or - _theResult___fst_exp__h468004) + _theResult___fst_exp__h468005) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h468598 = - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q103; + _theResult___fst_exp__h468599 = + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q103; 3'd1: - _theResult___fst_exp__h468598 = - CASE_guard59776_0b0_theResult___fst_exp68004_0_ETC__q104; + _theResult___fst_exp__h468599 = + CASE_guard59777_0b0_theResult___fst_exp68005_0_ETC__q104; 3'd2: - _theResult___fst_exp__h468598 = + _theResult___fst_exp__h468599 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737; 3'd3: - _theResult___fst_exp__h468598 = + _theResult___fst_exp__h468599 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739; - 3'd4: _theResult___fst_exp__h468598 = _theResult___fst_exp__h468004; - default: _theResult___fst_exp__h468598 = 8'd0; + 3'd4: _theResult___fst_exp__h468599 = _theResult___fst_exp__h468005; + default: _theResult___fst_exp__h468599 = 8'd0; endcase end - always@(guard__h468612 or - _theResult___fst_exp__h476689 or - out_exp__h477159 or _theResult___exp__h477156) + always@(guard__h468613 or + _theResult___fst_exp__h476690 or + out_exp__h477160 or _theResult___exp__h477157) begin - case (guard__h468612) + case (guard__h468613) 2'b0, 2'b01: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 = - _theResult___fst_exp__h476689; + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q108 = + _theResult___fst_exp__h476690; 2'b10: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 = - out_exp__h477159; + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q108 = + out_exp__h477160; 2'b11: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 = - _theResult___exp__h477156; + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q108 = + _theResult___exp__h477157; endcase end - always@(guard__h468612 or - _theResult___fst_exp__h476689 or _theResult___exp__h477156) + always@(guard__h468613 or + _theResult___fst_exp__h476690 or _theResult___exp__h477157) begin - case (guard__h468612) + case (guard__h468613) 2'b0: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109 = - _theResult___fst_exp__h476689; + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q109 = + _theResult___fst_exp__h476690; 2'b01, 2'b10, 2'b11: - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109 = - _theResult___exp__h477156; + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q109 = + _theResult___exp__h477157; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108 or - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109 or + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q108 or + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q109 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___fst_exp__h476689) + _theResult___fst_exp__h476690) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h477234 = - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q108; + _theResult___fst_exp__h477235 = + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q108; 3'd1: - _theResult___fst_exp__h477234 = - CASE_guard68612_0b0_theResult___fst_exp76689_0_ETC__q109; + _theResult___fst_exp__h477235 = + CASE_guard68613_0b0_theResult___fst_exp76690_0_ETC__q109; 3'd2: - _theResult___fst_exp__h477234 = + _theResult___fst_exp__h477235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; 3'd3: - _theResult___fst_exp__h477234 = + _theResult___fst_exp__h477235 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_exp__h477234 = _theResult___fst_exp__h476689; - default: _theResult___fst_exp__h477234 = 8'd0; + 3'd4: _theResult___fst_exp__h477235 = _theResult___fst_exp__h476690; + default: _theResult___fst_exp__h477235 = 8'd0; endcase end - always@(guard__h450846 or - _theResult___snd__h458845 or - out_sfd__h459340 or _theResult___sfd__h459337) + always@(guard__h450847 or + _theResult___snd__h458846 or + out_sfd__h459341 or _theResult___sfd__h459338) begin - case (guard__h450846) + case (guard__h450847) 2'b0, 2'b01: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 = - _theResult___snd__h458845[56:34]; + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q110 = + _theResult___snd__h458846[56:34]; 2'b10: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 = - out_sfd__h459340; + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q110 = + out_sfd__h459341; 2'b11: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 = - _theResult___sfd__h459337; + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q110 = + _theResult___sfd__h459338; endcase end - always@(guard__h450846 or - _theResult___snd__h458845 or _theResult___sfd__h459337) + always@(guard__h450847 or + _theResult___snd__h458846 or _theResult___sfd__h459338) begin - case (guard__h450846) + case (guard__h450847) 2'b0: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111 = - _theResult___snd__h458845[56:34]; + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q111 = + _theResult___snd__h458846[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111 = - _theResult___sfd__h459337; + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q111 = + _theResult___sfd__h459338; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110 or - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111 or + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q110 or + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q111 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 or - _theResult___snd__h458845) + _theResult___snd__h458846) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h459415 = - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q110; + _theResult___fst_sfd__h459416 = + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q110; 3'd1: - _theResult___fst_sfd__h459415 = - CASE_guard50846_0b0_theResult___snd58845_BITS__ETC__q111; + _theResult___fst_sfd__h459416 = + CASE_guard50847_0b0_theResult___snd58846_BITS__ETC__q111; 3'd2: - _theResult___fst_sfd__h459415 = + _theResult___fst_sfd__h459416 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856; 3'd3: - _theResult___fst_sfd__h459415 = + _theResult___fst_sfd__h459416 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858; - 3'd4: _theResult___fst_sfd__h459415 = _theResult___snd__h458845[56:34]; - default: _theResult___fst_sfd__h459415 = 23'd0; + 3'd4: _theResult___fst_sfd__h459416 = _theResult___snd__h458846[56:34]; + default: _theResult___fst_sfd__h459416 = 23'd0; endcase end - always@(guard__h442139 or - sfdin__h450232 or out_sfd__h450758 or _theResult___sfd__h450755) + always@(guard__h442140 or + sfdin__h450233 or out_sfd__h450759 or _theResult___sfd__h450756) begin - case (guard__h442139) + case (guard__h442140) 2'b0, 2'b01: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 = - sfdin__h450232[56:34]; + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q112 = + sfdin__h450233[56:34]; 2'b10: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 = - out_sfd__h450758; + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q112 = + out_sfd__h450759; 2'b11: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 = - _theResult___sfd__h450755; + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q112 = + _theResult___sfd__h450756; endcase end - always@(guard__h442139 or sfdin__h450232 or _theResult___sfd__h450755) + always@(guard__h442140 or sfdin__h450233 or _theResult___sfd__h450756) begin - case (guard__h442139) + case (guard__h442140) 2'b0: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113 = - sfdin__h450232[56:34]; + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q113 = + sfdin__h450233[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113 = - _theResult___sfd__h450755; + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q113 = + _theResult___sfd__h450756; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112 or - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113 or + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q112 or + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q113 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 or - sfdin__h450232) + sfdin__h450233) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h450833 = - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q112; + _theResult___fst_sfd__h450834 = + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q112; 3'd1: - _theResult___fst_sfd__h450833 = - CASE_guard42139_0b0_sfdin50232_BITS_56_TO_34_0_ETC__q113; + _theResult___fst_sfd__h450834 = + CASE_guard42140_0b0_sfdin50233_BITS_56_TO_34_0_ETC__q113; 3'd2: - _theResult___fst_sfd__h450833 = + _theResult___fst_sfd__h450834 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837; 3'd3: - _theResult___fst_sfd__h450833 = + _theResult___fst_sfd__h450834 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839; - 3'd4: _theResult___fst_sfd__h450833 = sfdin__h450232[56:34]; - default: _theResult___fst_sfd__h450833 = 23'd0; + 3'd4: _theResult___fst_sfd__h450834 = sfdin__h450233[56:34]; + default: _theResult___fst_sfd__h450834 = 23'd0; endcase end - always@(guard__h459776 or - sfdin__h467998 or out_sfd__h468524 or _theResult___sfd__h468521) + always@(guard__h459777 or + sfdin__h467999 or out_sfd__h468525 or _theResult___sfd__h468522) begin - case (guard__h459776) + case (guard__h459777) 2'b0, 2'b01: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 = - sfdin__h467998[56:34]; + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q114 = + sfdin__h467999[56:34]; 2'b10: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 = - out_sfd__h468524; + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q114 = + out_sfd__h468525; 2'b11: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 = - _theResult___sfd__h468521; + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q114 = + _theResult___sfd__h468522; endcase end - always@(guard__h459776 or sfdin__h467998 or _theResult___sfd__h468521) + always@(guard__h459777 or sfdin__h467999 or _theResult___sfd__h468522) begin - case (guard__h459776) + case (guard__h459777) 2'b0: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115 = - sfdin__h467998[56:34]; + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q115 = + sfdin__h467999[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115 = - _theResult___sfd__h468521; + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q115 = + _theResult___sfd__h468522; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114 or - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115 or + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q114 or + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q115 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 or - sfdin__h467998) + sfdin__h467999) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h468599 = - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q114; + _theResult___fst_sfd__h468600 = + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q114; 3'd1: - _theResult___fst_sfd__h468599 = - CASE_guard59776_0b0_sfdin67998_BITS_56_TO_34_0_ETC__q115; + _theResult___fst_sfd__h468600 = + CASE_guard59777_0b0_sfdin67999_BITS_56_TO_34_0_ETC__q115; 3'd2: - _theResult___fst_sfd__h468599 = + _theResult___fst_sfd__h468600 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883; 3'd3: - _theResult___fst_sfd__h468599 = + _theResult___fst_sfd__h468600 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885; - 3'd4: _theResult___fst_sfd__h468599 = sfdin__h467998[56:34]; - default: _theResult___fst_sfd__h468599 = 23'd0; + 3'd4: _theResult___fst_sfd__h468600 = sfdin__h467999[56:34]; + default: _theResult___fst_sfd__h468600 = 23'd0; endcase end - always@(guard__h468612 or - _theResult___snd__h476635 or - out_sfd__h477160 or _theResult___sfd__h477157) + always@(guard__h468613 or + _theResult___snd__h476636 or + out_sfd__h477161 or _theResult___sfd__h477158) begin - case (guard__h468612) + case (guard__h468613) 2'b0, 2'b01: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 = - _theResult___snd__h476635[56:34]; + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q116 = + _theResult___snd__h476636[56:34]; 2'b10: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 = - out_sfd__h477160; + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q116 = + out_sfd__h477161; 2'b11: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 = - _theResult___sfd__h477157; + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q116 = + _theResult___sfd__h477158; endcase end - always@(guard__h468612 or - _theResult___snd__h476635 or _theResult___sfd__h477157) + always@(guard__h468613 or + _theResult___snd__h476636 or _theResult___sfd__h477158) begin - case (guard__h468612) + case (guard__h468613) 2'b0: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117 = - _theResult___snd__h476635[56:34]; + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q117 = + _theResult___snd__h476636[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117 = - _theResult___sfd__h477157; + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q117 = + _theResult___sfd__h477158; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116 or - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117 or + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q116 or + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q117 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 or - _theResult___snd__h476635) + _theResult___snd__h476636) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h477235 = - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q116; + _theResult___fst_sfd__h477236 = + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q116; 3'd1: - _theResult___fst_sfd__h477235 = - CASE_guard68612_0b0_theResult___snd76635_BITS__ETC__q117; + _theResult___fst_sfd__h477236 = + CASE_guard68613_0b0_theResult___snd76636_BITS__ETC__q117; 3'd2: - _theResult___fst_sfd__h477235 = + _theResult___fst_sfd__h477236 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902; 3'd3: - _theResult___fst_sfd__h477235 = + _theResult___fst_sfd__h477236 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904; - 3'd4: _theResult___fst_sfd__h477235 = _theResult___snd__h476635[56:34]; - default: _theResult___fst_sfd__h477235 = 23'd0; + 3'd4: _theResult___fst_sfd__h477236 = _theResult___snd__h476636[56:34]; + default: _theResult___fst_sfd__h477236 = 23'd0; endcase end - always@(guard__h442139 or + always@(guard__h442140 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h442139) + case (guard__h442140) 2'b0, 2'b01, 2'b10: - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + CASE_guard42140_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = - guard__h442139 == 2'b11 && + CASE_guard42140_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 = + guard__h442140 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or - guard__h442139) + CASE_guard42140_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118 or + guard__h442140) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - CASE_guard42139_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; + CASE_guard42140_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q118; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = - (guard__h442139 == 2'b0) ? + (guard__h442140 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h442139 == 2'b01 || guard__h442139 == 2'b10 || - guard__h442139 == 2'b11) && + (guard__h442140 == 2'b01 || guard__h442140 == 2'b10 || + guard__h442140 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 = @@ -32950,34 +32950,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h450846 or + always@(guard__h450847 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h450846) + case (guard__h450847) 2'b0, 2'b01, 2'b10: - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + CASE_guard50847_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = - guard__h450846 == 2'b11 && + CASE_guard50847_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 = + guard__h450847 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or - guard__h450846) + CASE_guard50847_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or + guard__h450847) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - CASE_guard50846_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; + CASE_guard50847_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = - (guard__h450846 == 2'b0) ? + (guard__h450847 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h450846 == 2'b01 || guard__h450846 == 2'b10 || - guard__h450846 == 2'b11) && + (guard__h450847 == 2'b01 || guard__h450847 == 2'b10 || + guard__h450847 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 = @@ -32988,34 +32988,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h442139 or + always@(guard__h442140 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h442139) + case (guard__h442140) 2'b0, 2'b01, 2'b10: - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + CASE_guard42140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = - guard__h442139 != 2'b11 || + CASE_guard42140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 = + guard__h442140 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or - guard__h442139) + CASE_guard42140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or + guard__h442140) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - CASE_guard42139_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; + CASE_guard42140_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = - (guard__h442139 == 2'b0) ? + (guard__h442140 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h442139 != 2'b01 && guard__h442139 != 2'b10 && - guard__h442139 != 2'b11 || + guard__h442140 != 2'b01 && guard__h442140 != 2'b10 && + guard__h442140 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 = @@ -33026,34 +33026,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h450846 or + always@(guard__h450847 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h450846) + case (guard__h450847) 2'b0, 2'b01, 2'b10: - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + CASE_guard50847_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = - guard__h450846 != 2'b11 || + CASE_guard50847_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 = + guard__h450847 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or - guard__h450846) + CASE_guard50847_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or + guard__h450847) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - CASE_guard50846_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; + CASE_guard50847_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = - (guard__h450846 == 2'b0) ? + (guard__h450847 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h450846 != 2'b01 && guard__h450846 != 2'b10 && - guard__h450846 != 2'b11 || + guard__h450847 != 2'b01 && guard__h450847 != 2'b10 && + guard__h450847 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 = @@ -33064,34 +33064,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459776 or + always@(guard__h459777 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459776) + case (guard__h459777) 2'b0, 2'b01, 2'b10: - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + CASE_guard59777_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = - guard__h459776 == 2'b11 && + CASE_guard59777_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 = + guard__h459777 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or - guard__h459776) + CASE_guard59777_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or + guard__h459777) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - CASE_guard59776_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; + CASE_guard59777_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = - (guard__h459776 == 2'b0) ? + (guard__h459777 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h459776 == 2'b01 || guard__h459776 == 2'b10 || - guard__h459776 == 2'b11) && + (guard__h459777 == 2'b01 || guard__h459777 == 2'b10 || + guard__h459777 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 = @@ -33102,34 +33102,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459776 or + always@(guard__h459777 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459776) + case (guard__h459777) 2'b0, 2'b01, 2'b10: - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + CASE_guard59777_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = - guard__h459776 != 2'b11 || + CASE_guard59777_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 = + guard__h459777 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or - guard__h459776) + CASE_guard59777_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or + guard__h459777) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - CASE_guard59776_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; + CASE_guard59777_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = - (guard__h459776 == 2'b0) ? + (guard__h459777 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h459776 != 2'b01 && guard__h459776 != 2'b10 && - guard__h459776 != 2'b11 || + guard__h459777 != 2'b01 && guard__h459777 != 2'b10 && + guard__h459777 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 = @@ -33140,34 +33140,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468612 or + always@(guard__h468613 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468612) + case (guard__h468613) 2'b0, 2'b01, 2'b10: - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + CASE_guard68613_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = - guard__h468612 == 2'b11 && + CASE_guard68613_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 = + guard__h468613 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or - guard__h468612) + CASE_guard68613_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or + guard__h468613) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - CASE_guard68612_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; + CASE_guard68613_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = - (guard__h468612 == 2'b0) ? + (guard__h468613 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h468612 == 2'b01 || guard__h468612 == 2'b10 || - guard__h468612 == 2'b11) && + (guard__h468613 == 2'b01 || guard__h468613 == 2'b10 || + guard__h468613 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 = @@ -33178,34 +33178,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468612 or + always@(guard__h468613 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468612) + case (guard__h468613) 2'b0, 2'b01, 2'b10: - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + CASE_guard68613_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = - guard__h468612 != 2'b11 || + CASE_guard68613_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 = + guard__h468613 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or - guard__h468612) + CASE_guard68613_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or + guard__h468613) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - CASE_guard68612_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; + CASE_guard68613_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = - (guard__h468612 == 2'b0) ? + (guard__h468613 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h468612 != 2'b01 && guard__h468612 != 2'b10 && - guard__h468612 != 2'b11 || + guard__h468613 != 2'b01 && guard__h468613 != 2'b10 && + guard__h468613 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 = @@ -33262,28 +33262,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h498953 or - _theResult___fst_exp__h506914 or _theResult___exp__h507569) + always@(guard__h498954 or + _theResult___fst_exp__h506915 or _theResult___exp__h507570) begin - case (guard__h498953) + case (guard__h498954) 2'b0: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135 = - _theResult___fst_exp__h506914; + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q135 = + _theResult___fst_exp__h506915; 2'b01, 2'b10, 2'b11: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135 = - _theResult___exp__h507569; + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q135 = + _theResult___exp__h507570; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h506914 or + _theResult___fst_exp__h506915 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 or - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135) + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q135) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - _theResult___fst_exp__h506914; + _theResult___fst_exp__h506915; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126; @@ -33292,44 +33292,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q135; + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q135; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 = 11'd0; endcase end - always@(guard__h498953 or - _theResult___fst_exp__h506914 or - out_exp__h507572 or _theResult___exp__h507569) + always@(guard__h498954 or + _theResult___fst_exp__h506915 or + out_exp__h507573 or _theResult___exp__h507570) begin - case (guard__h498953) + case (guard__h498954) 2'b0, 2'b01: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 = - _theResult___fst_exp__h506914; + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q136 = + _theResult___fst_exp__h506915; 2'b10: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 = - out_exp__h507572; + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q136 = + out_exp__h507573; 2'b11: - CASE_guard98953_0b0_theResult___fst_exp06914_0_ETC__q136 = - _theResult___exp__h507569; + CASE_guard98954_0b0_theResult___fst_exp06915_0_ETC__q136 = + _theResult___exp__h507570; endcase end - always@(guard__h498953 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h498954 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h498953) + case (guard__h498954) 2'b0, 2'b01, 2'b10: - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + CASE_guard98954_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard98953_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = - guard__h498953 == 2'b11 && + CASE_guard98954_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 = + guard__h498954 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498953) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498954) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33339,12 +33339,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 = - (guard__h498953 == 2'b0) ? + (guard__h498954 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h498953 == 2'b01 || guard__h498953 == 2'b10 || - guard__h498953 == 2'b11) && + (guard__h498954 == 2'b01 || guard__h498954 == 2'b10 || + guard__h498954 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33355,23 +33355,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h508265 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h508266 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h508265) + case (guard__h508266) 2'b0, 2'b01, 2'b10: - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + CASE_guard08266_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard08265_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = - guard__h508265 == 2'b11 && + CASE_guard08266_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 = + guard__h508266 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h508265) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h508266) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33381,12 +33381,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 = - (guard__h508265 == 2'b0) ? + (guard__h508266 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h508265 == 2'b01 || guard__h508265 == 2'b10 || - guard__h508265 == 2'b11) && + (guard__h508266 == 2'b01 || guard__h508266 == 2'b10 || + guard__h508266 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33397,23 +33397,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h517334 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h517335 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h517334) + case (guard__h517335) 2'b0, 2'b01, 2'b10: - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + CASE_guard17335_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard17334_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = - guard__h517334 == 2'b11 && + CASE_guard17335_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 = + guard__h517335 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h517334) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h517335) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33423,12 +33423,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 = - (guard__h517334 == 2'b0) ? + (guard__h517335 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h517334 == 2'b01 || guard__h517334 == 2'b10 || - guard__h517334 == 2'b11) && + (guard__h517335 == 2'b01 || guard__h517335 == 2'b10 || + guard__h517335 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -33439,28 +33439,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h577110 or - _theResult___fst_exp__h585071 or _theResult___exp__h585726) + always@(guard__h577111 or + _theResult___fst_exp__h585072 or _theResult___exp__h585727) begin - case (guard__h577110) + case (guard__h577111) 2'b0: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152 = - _theResult___fst_exp__h585071; + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q152 = + _theResult___fst_exp__h585072; 2'b01, 2'b10, 2'b11: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152 = - _theResult___exp__h585726; + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q152 = + _theResult___exp__h585727; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h585071 or + _theResult___fst_exp__h585072 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 or - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152) + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q152) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - _theResult___fst_exp__h585071; + _theResult___fst_exp__h585072; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841; @@ -33469,42 +33469,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q152; + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q152; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 = 11'd0; endcase end - always@(guard__h577110 or - _theResult___fst_exp__h585071 or - out_exp__h585729 or _theResult___exp__h585726) + always@(guard__h577111 or + _theResult___fst_exp__h585072 or + out_exp__h585730 or _theResult___exp__h585727) begin - case (guard__h577110) + case (guard__h577111) 2'b0, 2'b01: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 = - _theResult___fst_exp__h585071; + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q153 = + _theResult___fst_exp__h585072; 2'b10: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 = - out_exp__h585729; + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q153 = + out_exp__h585730; 2'b11: - CASE_guard77110_0b0_theResult___fst_exp85071_0_ETC__q153 = - _theResult___exp__h585726; + CASE_guard77111_0b0_theResult___fst_exp85072_0_ETC__q153 = + _theResult___exp__h585727; endcase end - always@(guard__h577110 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577111 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577110) + case (guard__h577111) 2'b0, 2'b01, 2'b10: - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + CASE_guard77111_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77110_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = - guard__h577110 == 2'b11 && + CASE_guard77111_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 = + guard__h577111 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577110) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577111) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33513,12 +33513,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 = - (guard__h577110 == 2'b0) ? + (guard__h577111 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h577110 == 2'b01 || guard__h577110 == 2'b10 || - guard__h577110 == 2'b11) && + (guard__h577111 == 2'b01 || guard__h577111 == 2'b10 || + guard__h577111 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33529,21 +33529,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h586422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h586423 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h586422) + case (guard__h586423) 2'b0, 2'b01, 2'b10: - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + CASE_guard86423_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard86422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = - guard__h586422 == 2'b11 && + CASE_guard86423_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 = + guard__h586423 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586422) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586423) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33552,12 +33552,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 = - (guard__h586422 == 2'b0) ? + (guard__h586423 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h586422 == 2'b01 || guard__h586422 == 2'b10 || - guard__h586422 == 2'b11) && + (guard__h586423 == 2'b01 || guard__h586423 == 2'b10 || + guard__h586423 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33568,21 +33568,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595492 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595491) + case (guard__h595492) 2'b0, 2'b01, 2'b10: - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + CASE_guard95492_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95491_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = - guard__h595491 == 2'b11 && + CASE_guard95492_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 = + guard__h595492 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595492) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33591,12 +33591,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 = - (guard__h595491 == 2'b0) ? + (guard__h595492 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h595491 == 2'b01 || guard__h595491 == 2'b10 || - guard__h595491 == 2'b11) && + (guard__h595492 == 2'b01 || guard__h595492 == 2'b10 || + guard__h595492 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33607,21 +33607,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h586422 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h586423 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h586422) + case (guard__h586423) 2'b0, 2'b01, 2'b10: - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + CASE_guard86423_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard86422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = - guard__h586422 != 2'b11 || + CASE_guard86423_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 = + guard__h586423 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586422) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586423) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33630,12 +33630,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 = - (guard__h586422 == 2'b0) ? + (guard__h586423 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h586422 != 2'b01 && guard__h586422 != 2'b10 && - guard__h586422 != 2'b11 || + guard__h586423 != 2'b01 && guard__h586423 != 2'b10 && + guard__h586423 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33646,21 +33646,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595491 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595492 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595491) + case (guard__h595492) 2'b0, 2'b01, 2'b10: - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + CASE_guard95492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = - guard__h595491 != 2'b11 || + CASE_guard95492_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 = + guard__h595492 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595491) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595492) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33669,12 +33669,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h595491 == 2'b0) ? + (guard__h595492 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595491 != 2'b01 && guard__h595491 != 2'b10 && - guard__h595491 != 2'b11 || + guard__h595492 != 2'b01 && guard__h595492 != 2'b10 && + guard__h595492 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33685,21 +33685,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h577110 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h577111 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h577110) + case (guard__h577111) 2'b0, 2'b01, 2'b10: - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + CASE_guard77111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard77110_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = - guard__h577110 != 2'b11 || + CASE_guard77111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 = + guard__h577111 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577110) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577111) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -33708,12 +33708,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h577110 == 2'b0) ? + (guard__h577111 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h577110 != 2'b01 && guard__h577110 != 2'b10 && - guard__h577110 != 2'b11 || + guard__h577111 != 2'b01 && guard__h577111 != 2'b10 && + guard__h577111 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -33724,28 +33724,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h537806 or - _theResult___fst_exp__h545767 or _theResult___exp__h546422) + always@(guard__h537807 or + _theResult___fst_exp__h545768 or _theResult___exp__h546423) begin - case (guard__h537806) + case (guard__h537807) 2'b0: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175 = - _theResult___fst_exp__h545767; + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q175 = + _theResult___fst_exp__h545768; 2'b01, 2'b10, 2'b11: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175 = - _theResult___exp__h546422; + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q175 = + _theResult___exp__h546423; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h545767 or + _theResult___fst_exp__h545768 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 or - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175) + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q175) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - _theResult___fst_exp__h545767; + _theResult___fst_exp__h545768; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611; @@ -33754,49 +33754,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q175; + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q175; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 = 11'd0; endcase end - always@(guard__h537806 or - _theResult___fst_exp__h545767 or - out_exp__h546425 or _theResult___exp__h546422) + always@(guard__h537807 or + _theResult___fst_exp__h545768 or + out_exp__h546426 or _theResult___exp__h546423) begin - case (guard__h537806) + case (guard__h537807) 2'b0, 2'b01: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 = - _theResult___fst_exp__h545767; + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q176 = + _theResult___fst_exp__h545768; 2'b10: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 = - out_exp__h546425; + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q176 = + out_exp__h546426; 2'b11: - CASE_guard37806_0b0_theResult___fst_exp45767_0_ETC__q176 = - _theResult___exp__h546422; + CASE_guard37807_0b0_theResult___fst_exp45768_0_ETC__q176 = + _theResult___exp__h546423; endcase end - always@(guard__h547118 or - _theResult___fst_exp__h555344 or _theResult___exp__h556073) + always@(guard__h547119 or + _theResult___fst_exp__h555345 or _theResult___exp__h556074) begin - case (guard__h547118) + case (guard__h547119) 2'b0: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177 = - _theResult___fst_exp__h555344; + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q177 = + _theResult___fst_exp__h555345; 2'b01, 2'b10, 2'b11: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177 = - _theResult___exp__h556073; + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q177 = + _theResult___exp__h556074; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h555344 or + _theResult___fst_exp__h555345 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 or - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177) + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q177) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - _theResult___fst_exp__h555344; + _theResult___fst_exp__h555345; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649; @@ -33805,49 +33805,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q177; + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q177; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 = 11'd0; endcase end - always@(guard__h547118 or - _theResult___fst_exp__h555344 or - out_exp__h556076 or _theResult___exp__h556073) + always@(guard__h547119 or + _theResult___fst_exp__h555345 or + out_exp__h556077 or _theResult___exp__h556074) begin - case (guard__h547118) + case (guard__h547119) 2'b0, 2'b01: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 = - _theResult___fst_exp__h555344; + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q178 = + _theResult___fst_exp__h555345; 2'b10: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 = - out_exp__h556076; + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q178 = + out_exp__h556077; 2'b11: - CASE_guard47118_0b0_theResult___fst_exp55344_0_ETC__q178 = - _theResult___exp__h556073; + CASE_guard47119_0b0_theResult___fst_exp55345_0_ETC__q178 = + _theResult___exp__h556074; endcase end - always@(guard__h556187 or - _theResult___fst_exp__h564177 or _theResult___exp__h564857) + always@(guard__h556188 or + _theResult___fst_exp__h564178 or _theResult___exp__h564858) begin - case (guard__h556187) + case (guard__h556188) 2'b0: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179 = - _theResult___fst_exp__h564177; + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q179 = + _theResult___fst_exp__h564178; 2'b01, 2'b10, 2'b11: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179 = - _theResult___exp__h564857; + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q179 = + _theResult___exp__h564858; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h564177 or + _theResult___fst_exp__h564178 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 or - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179) + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q179) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - _theResult___fst_exp__h564177; + _theResult___fst_exp__h564178; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680; @@ -33856,49 +33856,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q179; + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q179; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 = 11'd0; endcase end - always@(guard__h556187 or - _theResult___fst_exp__h564177 or - out_exp__h564860 or _theResult___exp__h564857) + always@(guard__h556188 or + _theResult___fst_exp__h564178 or + out_exp__h564861 or _theResult___exp__h564858) begin - case (guard__h556187) + case (guard__h556188) 2'b0, 2'b01: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 = - _theResult___fst_exp__h564177; + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q180 = + _theResult___fst_exp__h564178; 2'b10: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 = - out_exp__h564860; + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q180 = + out_exp__h564861; 2'b11: - CASE_guard56187_0b0_theResult___fst_exp64177_0_ETC__q180 = - _theResult___exp__h564857; + CASE_guard56188_0b0_theResult___fst_exp64178_0_ETC__q180 = + _theResult___exp__h564858; endcase end - always@(guard__h595491 or - _theResult___fst_exp__h603481 or _theResult___exp__h604161) + always@(guard__h595492 or + _theResult___fst_exp__h603482 or _theResult___exp__h604162) begin - case (guard__h595491) + case (guard__h595492) 2'b0: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181 = - _theResult___fst_exp__h603481; + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q181 = + _theResult___fst_exp__h603482; 2'b01, 2'b10, 2'b11: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181 = - _theResult___exp__h604161; + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q181 = + _theResult___exp__h604162; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h603481 or + _theResult___fst_exp__h603482 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 or - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181) + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q181) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - _theResult___fst_exp__h603481; + _theResult___fst_exp__h603482; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910; @@ -33907,49 +33907,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q181; + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q181; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 = 11'd0; endcase end - always@(guard__h595491 or - _theResult___fst_exp__h603481 or - out_exp__h604164 or _theResult___exp__h604161) + always@(guard__h595492 or + _theResult___fst_exp__h603482 or + out_exp__h604165 or _theResult___exp__h604162) begin - case (guard__h595491) + case (guard__h595492) 2'b0, 2'b01: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 = - _theResult___fst_exp__h603481; + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q182 = + _theResult___fst_exp__h603482; 2'b10: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 = - out_exp__h604164; + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q182 = + out_exp__h604165; 2'b11: - CASE_guard95491_0b0_theResult___fst_exp03481_0_ETC__q182 = - _theResult___exp__h604161; + CASE_guard95492_0b0_theResult___fst_exp03482_0_ETC__q182 = + _theResult___exp__h604162; endcase end - always@(guard__h586422 or - _theResult___fst_exp__h594648 or _theResult___exp__h595377) + always@(guard__h586423 or + _theResult___fst_exp__h594649 or _theResult___exp__h595378) begin - case (guard__h586422) + case (guard__h586423) 2'b0: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183 = - _theResult___fst_exp__h594648; + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q183 = + _theResult___fst_exp__h594649; 2'b01, 2'b10, 2'b11: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183 = - _theResult___exp__h595377; + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q183 = + _theResult___exp__h595378; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h594648 or + _theResult___fst_exp__h594649 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 or - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183) + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - _theResult___fst_exp__h594648; + _theResult___fst_exp__h594649; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879; @@ -33958,44 +33958,44 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q183; + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 = 11'd0; endcase end - always@(guard__h586422 or - _theResult___fst_exp__h594648 or - out_exp__h595380 or _theResult___exp__h595377) + always@(guard__h586423 or + _theResult___fst_exp__h594649 or + out_exp__h595381 or _theResult___exp__h595378) begin - case (guard__h586422) + case (guard__h586423) 2'b0, 2'b01: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 = - _theResult___fst_exp__h594648; + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q184 = + _theResult___fst_exp__h594649; 2'b10: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 = - out_exp__h595380; + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q184 = + out_exp__h595381; 2'b11: - CASE_guard86422_0b0_theResult___fst_exp94648_0_ETC__q184 = - _theResult___exp__h595377; + CASE_guard86423_0b0_theResult___fst_exp94649_0_ETC__q184 = + _theResult___exp__h595378; endcase end - always@(guard__h537806 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537807 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537806) + case (guard__h537807) 2'b0, 2'b01, 2'b10: - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + CASE_guard37807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37806_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = - guard__h537806 == 2'b11 && + CASE_guard37807_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 = + guard__h537807 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537806) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537807) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34005,12 +34005,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 = - (guard__h537806 == 2'b0) ? + (guard__h537807 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h537806 == 2'b01 || guard__h537806 == 2'b10 || - guard__h537806 == 2'b11) && + (guard__h537807 == 2'b01 || guard__h537807 == 2'b10 || + guard__h537807 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34021,23 +34021,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547118 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547119 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547118) + case (guard__h547119) 2'b0, 2'b01, 2'b10: - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + CASE_guard47119_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47118_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = - guard__h547118 == 2'b11 && + CASE_guard47119_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 = + guard__h547119 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547118) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547119) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34047,12 +34047,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 = - (guard__h547118 == 2'b0) ? + (guard__h547119 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h547118 == 2'b01 || guard__h547118 == 2'b10 || - guard__h547118 == 2'b11) && + (guard__h547119 == 2'b01 || guard__h547119 == 2'b10 || + guard__h547119 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34063,23 +34063,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h556187 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h556188 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h556187) + case (guard__h556188) 2'b0, 2'b01, 2'b10: - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + CASE_guard56188_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard56187_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = - guard__h556187 == 2'b11 && + CASE_guard56188_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 = + guard__h556188 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556187) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556188) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34089,12 +34089,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 = - (guard__h556187 == 2'b0) ? + (guard__h556188 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h556187 == 2'b01 || guard__h556187 == 2'b10 || - guard__h556187 == 2'b11) && + (guard__h556188 == 2'b01 || guard__h556188 == 2'b10 || + guard__h556188 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34105,23 +34105,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h547118 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h547119 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h547118) + case (guard__h547119) 2'b0, 2'b01, 2'b10: - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + CASE_guard47119_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard47118_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = - guard__h547118 != 2'b11 || + CASE_guard47119_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 = + guard__h547119 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547118) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547119) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34131,12 +34131,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 = - (guard__h547118 == 2'b0) ? + (guard__h547119 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h547118 != 2'b01 && guard__h547118 != 2'b10 && - guard__h547118 != 2'b11 || + guard__h547119 != 2'b01 && guard__h547119 != 2'b10 && + guard__h547119 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34147,23 +34147,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h556187 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h556188 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h556187) + case (guard__h556188) 2'b0, 2'b01, 2'b10: - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + CASE_guard56188_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard56187_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = - guard__h556187 != 2'b11 || + CASE_guard56188_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 = + guard__h556188 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556187) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556188) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34173,12 +34173,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h556187 == 2'b0) ? + (guard__h556188 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h556187 != 2'b01 && guard__h556187 != 2'b10 && - guard__h556187 != 2'b11 || + guard__h556188 != 2'b01 && guard__h556188 != 2'b10 && + guard__h556188 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34189,23 +34189,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537806 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537807 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537806) + case (guard__h537807) 2'b0, 2'b01, 2'b10: - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + CASE_guard37807_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = - guard__h537806 != 2'b11 || + CASE_guard37807_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 = + guard__h537807 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537806) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537807) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -34215,12 +34215,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h537806 == 2'b0) ? + (guard__h537807 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h537806 != 2'b01 && guard__h537806 != 2'b10 && - guard__h537806 != 2'b11 || + guard__h537807 != 2'b01 && guard__h537807 != 2'b10 && + guard__h537807 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -34231,28 +34231,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537806 or - _theResult___snd__h545718 or _theResult___sfd__h546423) + always@(guard__h537807 or + _theResult___snd__h545719 or _theResult___sfd__h546424) begin - case (guard__h537806) + case (guard__h537807) 2'b0: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197 = - _theResult___snd__h545718[56:5]; + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q197 = + _theResult___snd__h545719[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197 = - _theResult___sfd__h546423; + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q197 = + _theResult___sfd__h546424; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h545718 or + _theResult___snd__h545719 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 or - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197) + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q197) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - _theResult___snd__h545718[56:5]; + _theResult___snd__h545719[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706; @@ -34261,48 +34261,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q197; + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q197; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 = 52'd0; endcase end - always@(guard__h537806 or - _theResult___snd__h545718 or - out_sfd__h546426 or _theResult___sfd__h546423) + always@(guard__h537807 or + _theResult___snd__h545719 or + out_sfd__h546427 or _theResult___sfd__h546424) begin - case (guard__h537806) + case (guard__h537807) 2'b0, 2'b01: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 = - _theResult___snd__h545718[56:5]; + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q198 = + _theResult___snd__h545719[56:5]; 2'b10: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 = - out_sfd__h546426; + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q198 = + out_sfd__h546427; 2'b11: - CASE_guard37806_0b0_theResult___snd45718_BITS__ETC__q198 = - _theResult___sfd__h546423; + CASE_guard37807_0b0_theResult___snd45719_BITS__ETC__q198 = + _theResult___sfd__h546424; endcase end - always@(guard__h547118 or sfdin__h555338 or _theResult___sfd__h556074) + always@(guard__h547119 or sfdin__h555339 or _theResult___sfd__h556075) begin - case (guard__h547118) + case (guard__h547119) 2'b0: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199 = - sfdin__h555338[56:5]; + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q199 = + sfdin__h555339[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199 = - _theResult___sfd__h556074; + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q199 = + _theResult___sfd__h556075; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h555338 or + sfdin__h555339 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 or - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199) + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q199) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - sfdin__h555338[56:5]; + sfdin__h555339[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732; @@ -34311,48 +34311,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q199; + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q199; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 = 52'd0; endcase end - always@(guard__h547118 or - sfdin__h555338 or out_sfd__h556077 or _theResult___sfd__h556074) + always@(guard__h547119 or + sfdin__h555339 or out_sfd__h556078 or _theResult___sfd__h556075) begin - case (guard__h547118) + case (guard__h547119) 2'b0, 2'b01: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 = - sfdin__h555338[56:5]; + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q200 = + sfdin__h555339[56:5]; 2'b10: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 = - out_sfd__h556077; + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q200 = + out_sfd__h556078; 2'b11: - CASE_guard47118_0b0_sfdin55338_BITS_56_TO_5_0b_ETC__q200 = - _theResult___sfd__h556074; + CASE_guard47119_0b0_sfdin55339_BITS_56_TO_5_0b_ETC__q200 = + _theResult___sfd__h556075; endcase end - always@(guard__h556187 or - _theResult___snd__h564123 or _theResult___sfd__h564858) + always@(guard__h556188 or + _theResult___snd__h564124 or _theResult___sfd__h564859) begin - case (guard__h556187) + case (guard__h556188) 2'b0: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201 = - _theResult___snd__h564123[56:5]; + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q201 = + _theResult___snd__h564124[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201 = - _theResult___sfd__h564858; + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q201 = + _theResult___sfd__h564859; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h564123 or + _theResult___snd__h564124 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 or - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201) + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q201) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - _theResult___snd__h564123[56:5]; + _theResult___snd__h564124[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751; @@ -34361,49 +34361,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q201; + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q201; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 = 52'd0; endcase end - always@(guard__h556187 or - _theResult___snd__h564123 or - out_sfd__h564861 or _theResult___sfd__h564858) + always@(guard__h556188 or + _theResult___snd__h564124 or + out_sfd__h564862 or _theResult___sfd__h564859) begin - case (guard__h556187) + case (guard__h556188) 2'b0, 2'b01: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 = - _theResult___snd__h564123[56:5]; + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q202 = + _theResult___snd__h564124[56:5]; 2'b10: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 = - out_sfd__h564861; + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q202 = + out_sfd__h564862; 2'b11: - CASE_guard56187_0b0_theResult___snd64123_BITS__ETC__q202 = - _theResult___sfd__h564858; + CASE_guard56188_0b0_theResult___snd64124_BITS__ETC__q202 = + _theResult___sfd__h564859; endcase end - always@(guard__h508265 or - _theResult___fst_exp__h516491 or _theResult___exp__h517220) + always@(guard__h508266 or + _theResult___fst_exp__h516492 or _theResult___exp__h517221) begin - case (guard__h508265) + case (guard__h508266) 2'b0: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203 = - _theResult___fst_exp__h516491; + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q203 = + _theResult___fst_exp__h516492; 2'b01, 2'b10, 2'b11: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203 = - _theResult___exp__h517220; + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q203 = + _theResult___exp__h517221; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h516491 or + _theResult___fst_exp__h516492 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 or - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203) + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q203) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - _theResult___fst_exp__h516491; + _theResult___fst_exp__h516492; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169; @@ -34412,49 +34412,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q203; + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q203; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 = 11'd0; endcase end - always@(guard__h508265 or - _theResult___fst_exp__h516491 or - out_exp__h517223 or _theResult___exp__h517220) + always@(guard__h508266 or + _theResult___fst_exp__h516492 or + out_exp__h517224 or _theResult___exp__h517221) begin - case (guard__h508265) + case (guard__h508266) 2'b0, 2'b01: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 = - _theResult___fst_exp__h516491; + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q204 = + _theResult___fst_exp__h516492; 2'b10: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 = - out_exp__h517223; + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q204 = + out_exp__h517224; 2'b11: - CASE_guard08265_0b0_theResult___fst_exp16491_0_ETC__q204 = - _theResult___exp__h517220; + CASE_guard08266_0b0_theResult___fst_exp16492_0_ETC__q204 = + _theResult___exp__h517221; endcase end - always@(guard__h517334 or - _theResult___fst_exp__h525324 or _theResult___exp__h526004) + always@(guard__h517335 or + _theResult___fst_exp__h525325 or _theResult___exp__h526005) begin - case (guard__h517334) + case (guard__h517335) 2'b0: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205 = - _theResult___fst_exp__h525324; + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q205 = + _theResult___fst_exp__h525325; 2'b01, 2'b10, 2'b11: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205 = - _theResult___exp__h526004; + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q205 = + _theResult___exp__h526005; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h525324 or + _theResult___fst_exp__h525325 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 or - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205) + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - _theResult___fst_exp__h525324; + _theResult___fst_exp__h525325; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200; @@ -34463,49 +34463,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q205; + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 = 11'd0; endcase end - always@(guard__h517334 or - _theResult___fst_exp__h525324 or - out_exp__h526007 or _theResult___exp__h526004) + always@(guard__h517335 or + _theResult___fst_exp__h525325 or + out_exp__h526008 or _theResult___exp__h526005) begin - case (guard__h517334) + case (guard__h517335) 2'b0, 2'b01: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 = - _theResult___fst_exp__h525324; + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q206 = + _theResult___fst_exp__h525325; 2'b10: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 = - out_exp__h526007; + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q206 = + out_exp__h526008; 2'b11: - CASE_guard17334_0b0_theResult___fst_exp25324_0_ETC__q206 = - _theResult___exp__h526004; + CASE_guard17335_0b0_theResult___fst_exp25325_0_ETC__q206 = + _theResult___exp__h526005; endcase end - always@(guard__h498953 or - _theResult___snd__h506865 or _theResult___sfd__h507570) + always@(guard__h498954 or + _theResult___snd__h506866 or _theResult___sfd__h507571) begin - case (guard__h498953) + case (guard__h498954) 2'b0: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q207 = - _theResult___snd__h506865[56:5]; + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q207 = + _theResult___snd__h506866[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q207 = - _theResult___sfd__h507570; + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q207 = + _theResult___sfd__h507571; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h506865 or + _theResult___snd__h506866 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 or - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q207) + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - _theResult___snd__h506865[56:5]; + _theResult___snd__h506866[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226; @@ -34514,48 +34514,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q207; + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 = 52'd0; endcase end - always@(guard__h498953 or - _theResult___snd__h506865 or - out_sfd__h507573 or _theResult___sfd__h507570) + always@(guard__h498954 or + _theResult___snd__h506866 or + out_sfd__h507574 or _theResult___sfd__h507571) begin - case (guard__h498953) + case (guard__h498954) 2'b0, 2'b01: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q208 = - _theResult___snd__h506865[56:5]; + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q208 = + _theResult___snd__h506866[56:5]; 2'b10: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q208 = - out_sfd__h507573; + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q208 = + out_sfd__h507574; 2'b11: - CASE_guard98953_0b0_theResult___snd06865_BITS__ETC__q208 = - _theResult___sfd__h507570; + CASE_guard98954_0b0_theResult___snd06866_BITS__ETC__q208 = + _theResult___sfd__h507571; endcase end - always@(guard__h508265 or sfdin__h516485 or _theResult___sfd__h517221) + always@(guard__h508266 or sfdin__h516486 or _theResult___sfd__h517222) begin - case (guard__h508265) + case (guard__h508266) 2'b0: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q209 = - sfdin__h516485[56:5]; + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q209 = + sfdin__h516486[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q209 = - _theResult___sfd__h517221; + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q209 = + _theResult___sfd__h517222; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h516485 or + sfdin__h516486 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q209) + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - sfdin__h516485[56:5]; + sfdin__h516486[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253; @@ -34564,48 +34564,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q209; + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 = 52'd0; endcase end - always@(guard__h508265 or - sfdin__h516485 or out_sfd__h517224 or _theResult___sfd__h517221) + always@(guard__h508266 or + sfdin__h516486 or out_sfd__h517225 or _theResult___sfd__h517222) begin - case (guard__h508265) + case (guard__h508266) 2'b0, 2'b01: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q210 = - sfdin__h516485[56:5]; + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q210 = + sfdin__h516486[56:5]; 2'b10: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q210 = - out_sfd__h517224; + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q210 = + out_sfd__h517225; 2'b11: - CASE_guard08265_0b0_sfdin16485_BITS_56_TO_5_0b_ETC__q210 = - _theResult___sfd__h517221; + CASE_guard08266_0b0_sfdin16486_BITS_56_TO_5_0b_ETC__q210 = + _theResult___sfd__h517222; endcase end - always@(guard__h517334 or - _theResult___snd__h525270 or _theResult___sfd__h526005) + always@(guard__h517335 or + _theResult___snd__h525271 or _theResult___sfd__h526006) begin - case (guard__h517334) + case (guard__h517335) 2'b0: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211 = - _theResult___snd__h525270[56:5]; + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q211 = + _theResult___snd__h525271[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211 = - _theResult___sfd__h526005; + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q211 = + _theResult___sfd__h526006; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h525270 or + _theResult___snd__h525271 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 or - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211) + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - _theResult___snd__h525270[56:5]; + _theResult___snd__h525271[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272; @@ -34614,49 +34614,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q211; + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 = 52'd0; endcase end - always@(guard__h517334 or - _theResult___snd__h525270 or - out_sfd__h526008 or _theResult___sfd__h526005) + always@(guard__h517335 or + _theResult___snd__h525271 or + out_sfd__h526009 or _theResult___sfd__h526006) begin - case (guard__h517334) + case (guard__h517335) 2'b0, 2'b01: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 = - _theResult___snd__h525270[56:5]; + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q212 = + _theResult___snd__h525271[56:5]; 2'b10: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 = - out_sfd__h526008; + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q212 = + out_sfd__h526009; 2'b11: - CASE_guard17334_0b0_theResult___snd25270_BITS__ETC__q212 = - _theResult___sfd__h526005; + CASE_guard17335_0b0_theResult___snd25271_BITS__ETC__q212 = + _theResult___sfd__h526006; endcase end - always@(guard__h577110 or - _theResult___snd__h585022 or _theResult___sfd__h585727) + always@(guard__h577111 or + _theResult___snd__h585023 or _theResult___sfd__h585728) begin - case (guard__h577110) + case (guard__h577111) 2'b0: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213 = - _theResult___snd__h585022[56:5]; + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q213 = + _theResult___snd__h585023[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213 = - _theResult___sfd__h585727; + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q213 = + _theResult___sfd__h585728; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h585022 or + _theResult___snd__h585023 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 or - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213) + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - _theResult___snd__h585022[56:5]; + _theResult___snd__h585023[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936; @@ -34665,48 +34665,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q213; + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 = 52'd0; endcase end - always@(guard__h577110 or - _theResult___snd__h585022 or - out_sfd__h585730 or _theResult___sfd__h585727) + always@(guard__h577111 or + _theResult___snd__h585023 or + out_sfd__h585731 or _theResult___sfd__h585728) begin - case (guard__h577110) + case (guard__h577111) 2'b0, 2'b01: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 = - _theResult___snd__h585022[56:5]; + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q214 = + _theResult___snd__h585023[56:5]; 2'b10: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 = - out_sfd__h585730; + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q214 = + out_sfd__h585731; 2'b11: - CASE_guard77110_0b0_theResult___snd85022_BITS__ETC__q214 = - _theResult___sfd__h585727; + CASE_guard77111_0b0_theResult___snd85023_BITS__ETC__q214 = + _theResult___sfd__h585728; endcase end - always@(guard__h586422 or sfdin__h594642 or _theResult___sfd__h595378) + always@(guard__h586423 or sfdin__h594643 or _theResult___sfd__h595379) begin - case (guard__h586422) + case (guard__h586423) 2'b0: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215 = - sfdin__h594642[56:5]; + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q215 = + sfdin__h594643[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215 = - _theResult___sfd__h595378; + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q215 = + _theResult___sfd__h595379; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h594642 or + sfdin__h594643 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 or - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215) + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - sfdin__h594642[56:5]; + sfdin__h594643[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962; @@ -34715,24 +34715,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q215; + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 = 52'd0; endcase end - always@(guard__h586422 or - sfdin__h594642 or out_sfd__h595381 or _theResult___sfd__h595378) + always@(guard__h586423 or + sfdin__h594643 or out_sfd__h595382 or _theResult___sfd__h595379) begin - case (guard__h586422) + case (guard__h586423) 2'b0, 2'b01: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 = - sfdin__h594642[56:5]; + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q216 = + sfdin__h594643[56:5]; 2'b10: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 = - out_sfd__h595381; + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q216 = + out_sfd__h595382; 2'b11: - CASE_guard86422_0b0_sfdin94642_BITS_56_TO_5_0b_ETC__q216 = - _theResult___sfd__h595378; + CASE_guard86423_0b0_sfdin94643_BITS_56_TO_5_0b_ETC__q216 = + _theResult___sfd__h595379; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -34767,28 +34767,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963; endcase end - always@(guard__h595491 or - _theResult___snd__h603427 or _theResult___sfd__h604162) + always@(guard__h595492 or + _theResult___snd__h603428 or _theResult___sfd__h604163) begin - case (guard__h595491) + case (guard__h595492) 2'b0: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217 = - _theResult___snd__h603427[56:5]; + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q217 = + _theResult___snd__h603428[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217 = - _theResult___sfd__h604162; + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q217 = + _theResult___sfd__h604163; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h603427 or + _theResult___snd__h603428 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 or - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217) + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - _theResult___snd__h603427[56:5]; + _theResult___snd__h603428[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981; @@ -34797,25 +34797,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q217; + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 = 52'd0; endcase end - always@(guard__h595491 or - _theResult___snd__h603427 or - out_sfd__h604165 or _theResult___sfd__h604162) + always@(guard__h595492 or + _theResult___snd__h603428 or + out_sfd__h604166 or _theResult___sfd__h604163) begin - case (guard__h595491) + case (guard__h595492) 2'b0, 2'b01: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 = - _theResult___snd__h603427[56:5]; + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q218 = + _theResult___snd__h603428[56:5]; 2'b10: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 = - out_sfd__h604165; + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q218 = + out_sfd__h604166; 2'b11: - CASE_guard95491_0b0_theResult___snd03427_BITS__ETC__q218 = - _theResult___sfd__h604162; + CASE_guard95492_0b0_theResult___snd03428_BITS__ETC__q218 = + _theResult___sfd__h604163; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -35139,10 +35139,10 @@ module mkCore(CLK, 4'd11; endcase end - always@(k__h674092 or + always@(k__h674093 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h674092) + case (k__h674093) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3543_co_ETC___d13553 = coreFix_aluExe_0_rsAlu$canEnq; @@ -35181,10 +35181,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13565; endcase end - always@(k__h674092 or + always@(k__h674093 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h674092) + case (k__h674093) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__354_ETC___d13586 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -35330,14 +35330,14 @@ module mkCore(CLK, 12'd2303; endcase end - always@(idx__h689687 or + always@(idx__h689688 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13837 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13843 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h689687) + case (idx__h689688) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13862 = fetchStage$pipelines_0_canDeq && @@ -35470,15 +35470,15 @@ module mkCore(CLK, NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13828; endcase end - always@(k__h674092 or + always@(k__h674093 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h674092) + case (k__h674093) 1'd0: - CASE_k74092_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k74092_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = + CASE_k74093_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -35581,14 +35581,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13565; endcase end - always@(idx__h689687 or + always@(idx__h689688 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14065 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14072 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h689687) + case (idx__h689688) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14076 = (!fetchStage$pipelines_0_canDeq || @@ -39060,21 +39060,21 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12101[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626444)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626445)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12101[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626444)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626445)) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 283, column 84\nCsr inst ppc = pc+4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu && coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12101[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626444)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626445)) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -39111,21 +39111,21 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12775[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648780)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648781)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12775[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648780)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648781)) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 283, column 84\nCsr inst ppc = pc+4"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12775[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648780)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648781)) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -39921,15 +39921,15 @@ module mkCore(CLK, $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609619 == 2'd0) + v__h609620 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609619 == 2'd0) + v__h609620 == 2'd0) $display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv\", line 172, column 38\ncredit underflow"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609619 == 2'd0) + v__h609620 == 2'd0) $finish(32'd0); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && diff --git a/src_Core/CPU/CsrFile.bsv b/src_Core/CPU/CsrFile.bsv index f6f18a9..11e635a 100644 --- a/src_Core/CPU/CsrFile.bsv +++ b/src_Core/CPU/CsrFile.bsv @@ -571,6 +571,12 @@ module mkCsrFile #(Data hartid)(CsrFile); readOnlyReg(2'b0), software_int_pend_vec[prvS], readOnlyReg(1'b0) // only if misa.N: software_int_pend_vec[prvU] ); + + // SIP and SIE fields are WARL (Write Any Read Legal) + // We support S-privilege bits only; + // this mask allows only those bits through. + Data sip_sie_warl_mask = zeroExtend (12'h_222); + // satp (sptbr in spike): FIXME we only support Bare and Sv39, so we hack // the encoding of mode[3:0] field. Only mode[3] is relevant, other bits // are always 0 @@ -834,8 +840,8 @@ module mkCsrFile #(Data hartid)(CsrFile); x [1], // ie_vec[prvS] x [0]); // ie_vec[prvU] CSRstvec: { x[63:2], 1'b0, x[0]}; - CSRsip: { 52'b0, 2'b0, x[9:8], 2'b0, x[5:4], 2'b0, x[1:0]}; - CSRsie: { 52'b0, 2'b0, x[9:8], 2'b0, x[5:4], 2'b0, x[1:0]}; + CSRsip: (x & sip_sie_warl_mask); + CSRsie: (x & sip_sie_warl_mask); CSRscounteren: { 61'b0, x[2:0]}; CSRscause: { x[63], 59'b0, x[3:0] }; CSRsatp: { x[63], 3'b0, asid, x [43:0] }; diff --git a/src_SSITH_P3/Verilog_RTL/mkCore.v b/src_SSITH_P3/Verilog_RTL/mkCore.v index 1768535..3477744 100644 --- a/src_SSITH_P3/Verilog_RTL/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL/mkCore.v @@ -4514,36 +4514,36 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875, - addr__h290068, - curData__h192917, - data_out__h737401, - data_warl_xformed__h722429, - rVal1__h609051, - rVal1__h633779, - trap_val__h710482, - x__h197127, - x__h723033; + addr__h290069, + curData__h192918, + data_out__h737272, + data_warl_xformed__h722430, + rVal1__h609052, + rVal1__h633780, + trap_val__h710483, + x__h197128, + x__h723034; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217, - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218, - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219, - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220, - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205, - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206, - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207, - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208, - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209, - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210, - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221, - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222, - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223, - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224, - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225, - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226, - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215, - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220, + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205, + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210, + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221, + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222, + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223, + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224, + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225, + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4555,45 +4555,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82, - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83, - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86, - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87, - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88, - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89, - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119, - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120, - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49, - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50, - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117, - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118, - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47, - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48, - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121, - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122, - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51, - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52, - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123, - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124, - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53, - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54, - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84, - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85, - _theResult___fst_sfd__h346069, - _theResult___fst_sfd__h354792, - _theResult___fst_sfd__h363374, - _theResult___fst_sfd__h372558, - _theResult___fst_sfd__h381194, - _theResult___fst_sfd__h391768, - _theResult___fst_sfd__h400489, - _theResult___fst_sfd__h409071, - _theResult___fst_sfd__h418255, - _theResult___fst_sfd__h426891, - _theResult___fst_sfd__h437463, - _theResult___fst_sfd__h446184, - _theResult___fst_sfd__h454766, - _theResult___fst_sfd__h463950, - _theResult___fst_sfd__h472586; + reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82, + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83, + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86, + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87, + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88, + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89, + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119, + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50, + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117, + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48, + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121, + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122, + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51, + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52, + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123, + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124, + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53, + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85, + _theResult___fst_sfd__h346070, + _theResult___fst_sfd__h354793, + _theResult___fst_sfd__h363375, + _theResult___fst_sfd__h372559, + _theResult___fst_sfd__h381195, + _theResult___fst_sfd__h391769, + _theResult___fst_sfd__h400490, + _theResult___fst_sfd__h409072, + _theResult___fst_sfd__h418256, + _theResult___fst_sfd__h426892, + _theResult___fst_sfd__h437464, + _theResult___fst_sfd__h446185, + _theResult___fst_sfd__h454767, + _theResult___fst_sfd__h463951, + _theResult___fst_sfd__h472587; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282, @@ -4622,24 +4622,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211, - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212, - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213, - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214, - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183, - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184, - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185, - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186, - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187, - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188, - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160, - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161, - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189, - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190, - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191, - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192, - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143, - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144, + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211, + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212, + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213, + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214, + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183, + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184, + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185, + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186, + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187, + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188, + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160, + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161, + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189, + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192, + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143, + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573, @@ -4649,47 +4649,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803; - reg [7 : 0] CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67, - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68, - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75, - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76, - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80, - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81, - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104, - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105, - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34, - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35, - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102, - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103, - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32, - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33, - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110, - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111, - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40, - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41, - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115, - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116, - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45, - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46, - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69, - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70, + reg [7 : 0] CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67, + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68, + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75, + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76, + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80, + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81, + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104, + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105, + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34, + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35, + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102, + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103, + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32, + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33, + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110, + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111, + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40, + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41, + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115, + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116, + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45, + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46, + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69, + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h346068, - _theResult___fst_exp__h354791, - _theResult___fst_exp__h363373, - _theResult___fst_exp__h372557, - _theResult___fst_exp__h381193, - _theResult___fst_exp__h391767, - _theResult___fst_exp__h400488, - _theResult___fst_exp__h409070, - _theResult___fst_exp__h418254, - _theResult___fst_exp__h426890, - _theResult___fst_exp__h437462, - _theResult___fst_exp__h446183, - _theResult___fst_exp__h454765, - _theResult___fst_exp__h463949, - _theResult___fst_exp__h472585; + _theResult___fst_exp__h346069, + _theResult___fst_exp__h354792, + _theResult___fst_exp__h363374, + _theResult___fst_exp__h372558, + _theResult___fst_exp__h381194, + _theResult___fst_exp__h391768, + _theResult___fst_exp__h400489, + _theResult___fst_exp__h409071, + _theResult___fst_exp__h418255, + _theResult___fst_exp__h426891, + _theResult___fst_exp__h437463, + _theResult___fst_exp__h446184, + _theResult___fst_exp__h454766, + _theResult___fst_exp__h463950, + _theResult___fst_exp__h472586; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, @@ -4712,8 +4712,8 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262, - i__h709458, - i__h709618; + i__h709459, + i__h709619; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281, @@ -4727,8 +4727,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717, - x__h285847, - x__h291617; + x__h285848, + x__h291618; reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, @@ -4766,46 +4766,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463, @@ -4927,166 +4927,166 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191, - _theResult___fst__h603371, - _theResult___snd__h603372, - a___1__h603090, - a___1__h603376, - a__h602949, + _theResult___fst__h603372, + _theResult___snd__h603373, + a___1__h603091, + a___1__h603377, + a__h602950, amoExec___d880, - b___1__h603091, - b___1__h603421, - b__h602950, - base__h712403, - base__h712423, + b___1__h603092, + b___1__h603422, + b__h602951, + base__h712404, + base__h712424, commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15456, - data___1__h475009, - data___1__h475817, - data__h475283, - fcsr_csr__read__h609377, - fflags_csr__read__h609352, - frm_csr__read__h609363, - mcause_csr__read__h611019, - mcounteren_csr__read__h610764, - medeleg_csr__read__h610371, - mideleg_csr__read__h610466, - mie_csr__read__h610590, - mip_csr__read__h611252, - mstatus_csr__read__h610223, - mtvec_csr__read__h610672, - n___1__h198530, - n__h194455, - n__read__h611356, - n__read__h611547, - n__read__h6760, - n__read__h726694, - next_pc__h722452, - pc__h712387, - q___1__h475882, - rVal1__h481762, - rVal2__h481763, - r___1__h475908, - res_data__h337870, - res_data__h337875, - res_data__h383572, - res_data__h383577, - res_data__h429267, - res_data__h429272, - resp_addr__h291972, - rg_tdata1__read__h612207, + data___1__h475010, + data___1__h475818, + data__h475284, + fcsr_csr__read__h609378, + fflags_csr__read__h609353, + frm_csr__read__h609364, + mcause_csr__read__h611020, + mcounteren_csr__read__h610765, + medeleg_csr__read__h610372, + mideleg_csr__read__h610467, + mie_csr__read__h610591, + mip_csr__read__h611253, + mstatus_csr__read__h610224, + mtvec_csr__read__h610673, + n___1__h198531, + n__h194456, + n__read__h611357, + n__read__h611548, + n__read__h6761, + n__read__h726565, + next_pc__h722453, + pc__h712388, + q___1__h475883, + rVal1__h481763, + rVal2__h481764, + r___1__h475909, + res_data__h337871, + res_data__h337876, + res_data__h383573, + res_data__h383578, + res_data__h429268, + res_data__h429273, + resp_addr__h291973, + rg_tdata1__read__h612208, robdeqPort_0_deq_data_BITS_95_TO_32__q245, - satp_csr__read__h610080, - scause_csr__read__h609877, - scounteren_csr__read__h609739, - shiftData__h181568, - sie_csr__read__h609643, - sip_csr__read__h610017, - sstatus_csr__read__h609573, - stvec_csr__read__h609686, - trap_val__h709444, + satp_csr__read__h610081, + scause_csr__read__h609878, + scounteren_csr__read__h609740, + shiftData__h181569, + sie_csr__read__h609644, + sip_csr__read__h610018, + sstatus_csr__read__h609574, + stvec_csr__read__h609687, + trap_val__h709445, upd__h3994, upd__h5311, - upd__h6874, - upd__h726805, - v__h607935, - v__h632818, - x__h153732, - x__h157279, - x__h160093, - x__h161941, - x__h181477, + upd__h6875, + upd__h726676, + v__h607936, + v__h632819, + x__h153733, + x__h157280, + x__h160094, + x__h161942, x__h181478, - x__h18386, - x__h183903, - x__h20924, - x__h287292, - x__h289146, - x__h46293, - x__h481671, + x__h181479, + x__h18387, + x__h183904, + x__h20925, + x__h287293, + x__h289147, + x__h46294, x__h481672, x__h481673, - x__h48829, - x__h617232, + x__h481674, + x__h48830, x__h617233, - x__h639741, + x__h617234, x__h639742, - x__h702377, - x__h714645, - x__h714837, - x__h726188, - x__h729657, - x__h732802, - x_addr__h314075, - x_quotient__h475197, - x_reg_ifc__read__h609482, - x_remainder__h475198, - y__h730489, - y__h733310, - y_avValue__h180565, - y_avValue__h181171, - y_avValue__h478807, - y_avValue__h479415, - y_avValue__h480017, - y_avValue__h608841, - y_avValue__h615057, - y_avValue__h633571, - y_avValue__h637576, - y_avValue_new_pc__h712179, - y_avValue_new_pc__h712365, - y_avValue_snd_snd_snd_snd_snd_fst__h730512, - y_avValue_snd_snd_snd_snd_snd_fst__h733371, - y_avValue_snd_snd_snd_snd_snd_fst__h733407, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784; + x__h639743, + x__h702378, + x__h714646, + x__h714838, + x__h726059, + x__h729528, + x__h732673, + x_addr__h314076, + x_quotient__h475198, + x_reg_ifc__read__h609483, + x_remainder__h475199, + y__h730360, + y__h733181, + y_avValue__h180566, + y_avValue__h181172, + y_avValue__h478808, + y_avValue__h479416, + y_avValue__h480018, + y_avValue__h608842, + y_avValue__h615058, + y_avValue__h633572, + y_avValue__h637577, + y_avValue_new_pc__h712180, + y_avValue_new_pc__h712366, + y_avValue_snd_snd_snd_snd_snd_fst__h730383, + y_avValue_snd_snd_snd_snd_snd_fst__h733242, + y_avValue_snd_snd_snd_snd_snd_fst__h733278, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882, IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920, - r1__read__h613050, - r1__read__h613454, - r1__read__h613964, - r1__read__h613969, - r1__read__h613988, - r1__read__h614221, - r1__read__h614387, - r1__read__h614480, - r1__read__h614485, - r1__read__h614504; - wire [61 : 0] r1__read__h613052, - r1__read__h613456, - r1__read__h613971, - r1__read__h613990, - r1__read__h614223, - r1__read__h614363, - r1__read__h614389, - r1__read__h614487, - r1__read__h614506; - wire [60 : 0] r1__read__h614225, - r1__read__h614365, - r1__read__h614391, - r1__read__h614508; - wire [59 : 0] r1__read__h613054, - r1__read__h613458, - r1__read__h613982, - r1__read__h613992, - r1__read__h614227, - r1__read__h614393, - r1__read__h614498, - r1__read__h614510; - wire [58 : 0] r1__read__h613056, - r1__read__h613460, - r1__read__h613994, - r1__read__h614229, - r1__read__h614395, - r1__read__h614512; + r1__read__h613051, + r1__read__h613455, + r1__read__h613965, + r1__read__h613970, + r1__read__h613989, + r1__read__h614222, + r1__read__h614388, + r1__read__h614481, + r1__read__h614486, + r1__read__h614505; + wire [61 : 0] r1__read__h613053, + r1__read__h613457, + r1__read__h613972, + r1__read__h613991, + r1__read__h614224, + r1__read__h614364, + r1__read__h614390, + r1__read__h614488, + r1__read__h614507; + wire [60 : 0] r1__read__h614226, + r1__read__h614366, + r1__read__h614392, + r1__read__h614509; + wire [59 : 0] r1__read__h613055, + r1__read__h613459, + r1__read__h613983, + r1__read__h613993, + r1__read__h614228, + r1__read__h614394, + r1__read__h614499, + r1__read__h614511; + wire [58 : 0] r1__read__h613057, + r1__read__h613461, + r1__read__h613995, + r1__read__h614230, + r1__read__h614396, + r1__read__h614513; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, - r1__read__h613058, - r1__read__h613462, - r1__read__h613996, - r1__read__h614231, - r1__read__h614367, - r1__read__h614397, - r1__read__h614514, - y__h254804; + r1__read__h613059, + r1__read__h613463, + r1__read__h613997, + r1__read__h614232, + r1__read__h614368, + r1__read__h614398, + r1__read__h614515, + y__h254805; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98, @@ -5114,187 +5114,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342, - _theResult____h346086, - _theResult____h363725, - _theResult____h391785, - _theResult____h409422, - _theResult____h437480, - _theResult____h455117, - _theResult____h502870, - _theResult____h541723, - _theResult____h581027, - _theResult___snd__h354208, - _theResult___snd__h354219, - _theResult___snd__h354221, - _theResult___snd__h354231, - _theResult___snd__h354237, - _theResult___snd__h354260, - _theResult___snd__h362804, - _theResult___snd__h362806, - _theResult___snd__h362813, - _theResult___snd__h362819, - _theResult___snd__h362842, - _theResult___snd__h371974, - _theResult___snd__h371985, - _theResult___snd__h371987, - _theResult___snd__h371997, - _theResult___snd__h372003, - _theResult___snd__h372026, - _theResult___snd__h380594, - _theResult___snd__h380608, - _theResult___snd__h380614, - _theResult___snd__h380632, - _theResult___snd__h399905, - _theResult___snd__h399916, - _theResult___snd__h399918, - _theResult___snd__h399928, - _theResult___snd__h399934, - _theResult___snd__h399957, - _theResult___snd__h408501, - _theResult___snd__h408503, - _theResult___snd__h408510, - _theResult___snd__h408516, - _theResult___snd__h408539, - _theResult___snd__h417671, - _theResult___snd__h417682, - _theResult___snd__h417684, - _theResult___snd__h417694, - _theResult___snd__h417700, - _theResult___snd__h417723, - _theResult___snd__h426291, - _theResult___snd__h426305, - _theResult___snd__h426311, - _theResult___snd__h426329, - _theResult___snd__h445600, - _theResult___snd__h445611, - _theResult___snd__h445613, - _theResult___snd__h445623, - _theResult___snd__h445629, - _theResult___snd__h445652, - _theResult___snd__h454196, - _theResult___snd__h454198, - _theResult___snd__h454205, - _theResult___snd__h454211, - _theResult___snd__h454234, - _theResult___snd__h463366, - _theResult___snd__h463377, - _theResult___snd__h463379, - _theResult___snd__h463389, - _theResult___snd__h463395, - _theResult___snd__h463418, - _theResult___snd__h471986, - _theResult___snd__h472000, - _theResult___snd__h472006, - _theResult___snd__h472024, - _theResult___snd__h501480, - _theResult___snd__h501482, - _theResult___snd__h501489, - _theResult___snd__h501495, - _theResult___snd__h501518, - _theResult___snd__h511117, - _theResult___snd__h511128, - _theResult___snd__h511130, - _theResult___snd__h511140, - _theResult___snd__h511146, - _theResult___snd__h511169, - _theResult___snd__h519885, - _theResult___snd__h519899, - _theResult___snd__h519905, - _theResult___snd__h519923, - _theResult___snd__h540333, - _theResult___snd__h540335, - _theResult___snd__h540342, - _theResult___snd__h540348, - _theResult___snd__h540371, - _theResult___snd__h549970, - _theResult___snd__h549981, - _theResult___snd__h549983, - _theResult___snd__h549993, - _theResult___snd__h549999, - _theResult___snd__h550022, - _theResult___snd__h558738, - _theResult___snd__h558752, - _theResult___snd__h558758, - _theResult___snd__h558776, - _theResult___snd__h579637, - _theResult___snd__h579639, - _theResult___snd__h579646, - _theResult___snd__h579652, - _theResult___snd__h579675, - _theResult___snd__h589274, - _theResult___snd__h589285, - _theResult___snd__h589287, - _theResult___snd__h589297, - _theResult___snd__h589303, - _theResult___snd__h589326, - _theResult___snd__h598042, - _theResult___snd__h598056, - _theResult___snd__h598062, - _theResult___snd__h598080, - r1__read__h614233, - r1__read__h614369, - r1__read__h614399, - r1__read__h614516, - result__h364338, - result__h410035, - result__h455730, - result__h503483, - result__h542336, - result__h581640, - sfd__h338481, - sfd__h384183, - sfd__h429878, - sfd__h482503, - sfd__h521497, - sfd__h560801, - sfdin__h354191, - sfdin__h371957, - sfdin__h399888, - sfdin__h417654, - sfdin__h445583, - sfdin__h463349, - sfdin__h511100, - sfdin__h549953, - sfdin__h589257, - x__h364435, - x__h410132, - x__h455827, - x__h503578, - x__h542431, - x__h581735; - wire [55 : 0] r1__read__h613060, - r1__read__h613464, - r1__read__h613998, - r1__read__h614235, - r1__read__h614401, - r1__read__h614518; - wire [54 : 0] r1__read__h613062, - r1__read__h613466, - r1__read__h614000, - r1__read__h614237, - r1__read__h614403, - r1__read__h614520; - wire [53 : 0] r1__read__h614346, - r1__read__h614371, - r1__read__h614405, - r1__read__h614522, - sfd__h501547, - sfd__h511198, - sfd__h519958, - sfd__h540400, - sfd__h550051, - sfd__h558811, - sfd__h579704, - sfd__h589355, - sfd__h598115, - value__h346708, - value__h392405, - value__h438100; - wire [52 : 0] r1__read__h614239, - r1__read__h614348, - r1__read__h614373, - r1__read__h614407, - r1__read__h614524; + _theResult____h346087, + _theResult____h363726, + _theResult____h391786, + _theResult____h409423, + _theResult____h437481, + _theResult____h455118, + _theResult____h502871, + _theResult____h541724, + _theResult____h581028, + _theResult___snd__h354209, + _theResult___snd__h354220, + _theResult___snd__h354222, + _theResult___snd__h354232, + _theResult___snd__h354238, + _theResult___snd__h354261, + _theResult___snd__h362805, + _theResult___snd__h362807, + _theResult___snd__h362814, + _theResult___snd__h362820, + _theResult___snd__h362843, + _theResult___snd__h371975, + _theResult___snd__h371986, + _theResult___snd__h371988, + _theResult___snd__h371998, + _theResult___snd__h372004, + _theResult___snd__h372027, + _theResult___snd__h380595, + _theResult___snd__h380609, + _theResult___snd__h380615, + _theResult___snd__h380633, + _theResult___snd__h399906, + _theResult___snd__h399917, + _theResult___snd__h399919, + _theResult___snd__h399929, + _theResult___snd__h399935, + _theResult___snd__h399958, + _theResult___snd__h408502, + _theResult___snd__h408504, + _theResult___snd__h408511, + _theResult___snd__h408517, + _theResult___snd__h408540, + _theResult___snd__h417672, + _theResult___snd__h417683, + _theResult___snd__h417685, + _theResult___snd__h417695, + _theResult___snd__h417701, + _theResult___snd__h417724, + _theResult___snd__h426292, + _theResult___snd__h426306, + _theResult___snd__h426312, + _theResult___snd__h426330, + _theResult___snd__h445601, + _theResult___snd__h445612, + _theResult___snd__h445614, + _theResult___snd__h445624, + _theResult___snd__h445630, + _theResult___snd__h445653, + _theResult___snd__h454197, + _theResult___snd__h454199, + _theResult___snd__h454206, + _theResult___snd__h454212, + _theResult___snd__h454235, + _theResult___snd__h463367, + _theResult___snd__h463378, + _theResult___snd__h463380, + _theResult___snd__h463390, + _theResult___snd__h463396, + _theResult___snd__h463419, + _theResult___snd__h471987, + _theResult___snd__h472001, + _theResult___snd__h472007, + _theResult___snd__h472025, + _theResult___snd__h501481, + _theResult___snd__h501483, + _theResult___snd__h501490, + _theResult___snd__h501496, + _theResult___snd__h501519, + _theResult___snd__h511118, + _theResult___snd__h511129, + _theResult___snd__h511131, + _theResult___snd__h511141, + _theResult___snd__h511147, + _theResult___snd__h511170, + _theResult___snd__h519886, + _theResult___snd__h519900, + _theResult___snd__h519906, + _theResult___snd__h519924, + _theResult___snd__h540334, + _theResult___snd__h540336, + _theResult___snd__h540343, + _theResult___snd__h540349, + _theResult___snd__h540372, + _theResult___snd__h549971, + _theResult___snd__h549982, + _theResult___snd__h549984, + _theResult___snd__h549994, + _theResult___snd__h550000, + _theResult___snd__h550023, + _theResult___snd__h558739, + _theResult___snd__h558753, + _theResult___snd__h558759, + _theResult___snd__h558777, + _theResult___snd__h579638, + _theResult___snd__h579640, + _theResult___snd__h579647, + _theResult___snd__h579653, + _theResult___snd__h579676, + _theResult___snd__h589275, + _theResult___snd__h589286, + _theResult___snd__h589288, + _theResult___snd__h589298, + _theResult___snd__h589304, + _theResult___snd__h589327, + _theResult___snd__h598043, + _theResult___snd__h598057, + _theResult___snd__h598063, + _theResult___snd__h598081, + r1__read__h614234, + r1__read__h614370, + r1__read__h614400, + r1__read__h614517, + result__h364339, + result__h410036, + result__h455731, + result__h503484, + result__h542337, + result__h581641, + sfd__h338482, + sfd__h384184, + sfd__h429879, + sfd__h482504, + sfd__h521498, + sfd__h560802, + sfdin__h354192, + sfdin__h371958, + sfdin__h399889, + sfdin__h417655, + sfdin__h445584, + sfdin__h463350, + sfdin__h511101, + sfdin__h549954, + sfdin__h589258, + x__h364436, + x__h410133, + x__h455828, + x__h503579, + x__h542432, + x__h581736; + wire [55 : 0] r1__read__h613061, + r1__read__h613465, + r1__read__h613999, + r1__read__h614236, + r1__read__h614402, + r1__read__h614519; + wire [54 : 0] r1__read__h613063, + r1__read__h613467, + r1__read__h614001, + r1__read__h614238, + r1__read__h614404, + r1__read__h614521; + wire [53 : 0] r1__read__h614347, + r1__read__h614372, + r1__read__h614406, + r1__read__h614523, + sfd__h501548, + sfd__h511199, + sfd__h519959, + sfd__h540401, + sfd__h550052, + sfd__h558812, + sfd__h579705, + sfd__h589356, + sfd__h598116, + value__h346709, + value__h392406, + value__h438101; + wire [52 : 0] r1__read__h614240, + r1__read__h614349, + r1__read__h614374, + r1__read__h614408, + r1__read__h614525; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140, @@ -5316,111 +5316,111 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881, - _theResult___fst_sfd__h486457, - _theResult___fst_sfd__h502285, - _theResult___fst_sfd__h502288, - _theResult___fst_sfd__h511936, - _theResult___fst_sfd__h511939, - _theResult___fst_sfd__h520720, - _theResult___fst_sfd__h520723, - _theResult___fst_sfd__h520732, - _theResult___fst_sfd__h520738, - _theResult___fst_sfd__h525310, - _theResult___fst_sfd__h541138, - _theResult___fst_sfd__h541141, - _theResult___fst_sfd__h550789, - _theResult___fst_sfd__h550792, - _theResult___fst_sfd__h559573, - _theResult___fst_sfd__h559576, - _theResult___fst_sfd__h559585, - _theResult___fst_sfd__h559591, - _theResult___fst_sfd__h564614, - _theResult___fst_sfd__h580442, - _theResult___fst_sfd__h580445, - _theResult___fst_sfd__h590093, - _theResult___fst_sfd__h590096, - _theResult___fst_sfd__h598877, - _theResult___fst_sfd__h598880, - _theResult___fst_sfd__h598889, - _theResult___fst_sfd__h598895, - _theResult___sfd__h502185, - _theResult___sfd__h511836, - _theResult___sfd__h520620, - _theResult___sfd__h541038, - _theResult___sfd__h550689, - _theResult___sfd__h559473, - _theResult___sfd__h580342, - _theResult___sfd__h589993, - _theResult___sfd__h598777, - _theResult___snd_fst_sfd__h482457, - _theResult___snd_fst_sfd__h502291, - _theResult___snd_fst_sfd__h520726, - _theResult___snd_fst_sfd__h521451, - _theResult___snd_fst_sfd__h541144, - _theResult___snd_fst_sfd__h559579, - _theResult___snd_fst_sfd__h560755, - _theResult___snd_fst_sfd__h580448, - _theResult___snd_fst_sfd__h598883, - out___1_sfd__h482205, - out___1_sfd__h521199, - out___1_sfd__h560503, - out_sfd__h502188, - out_sfd__h511839, - out_sfd__h520623, - out_sfd__h541041, - out_sfd__h550692, - out_sfd__h559476, - out_sfd__h580345, - out_sfd__h589996, - out_sfd__h598780; - wire [50 : 0] r1__read__h613064, r1__read__h614241; - wire [49 : 0] r1__read__h614350; - wire [48 : 0] r1__read_BITS_62_TO_14___h729677, - r1__read__h613066, - r1__read__h614352; - wire [46 : 0] r1__read__h613068, r1__read__h614245; - wire [45 : 0] r1__read__h613070, r1__read__h614247; - wire [44 : 0] r1__read__h613072, r1__read__h614249; - wire [43 : 0] r1__read__h613074, r1__read__h614251; - wire [42 : 0] r1__read__h614253; - wire [41 : 0] r1__read__h614255; - wire [40 : 0] r1__read__h614257; + _theResult___fst_sfd__h486458, + _theResult___fst_sfd__h502286, + _theResult___fst_sfd__h502289, + _theResult___fst_sfd__h511937, + _theResult___fst_sfd__h511940, + _theResult___fst_sfd__h520721, + _theResult___fst_sfd__h520724, + _theResult___fst_sfd__h520733, + _theResult___fst_sfd__h520739, + _theResult___fst_sfd__h525311, + _theResult___fst_sfd__h541139, + _theResult___fst_sfd__h541142, + _theResult___fst_sfd__h550790, + _theResult___fst_sfd__h550793, + _theResult___fst_sfd__h559574, + _theResult___fst_sfd__h559577, + _theResult___fst_sfd__h559586, + _theResult___fst_sfd__h559592, + _theResult___fst_sfd__h564615, + _theResult___fst_sfd__h580443, + _theResult___fst_sfd__h580446, + _theResult___fst_sfd__h590094, + _theResult___fst_sfd__h590097, + _theResult___fst_sfd__h598878, + _theResult___fst_sfd__h598881, + _theResult___fst_sfd__h598890, + _theResult___fst_sfd__h598896, + _theResult___sfd__h502186, + _theResult___sfd__h511837, + _theResult___sfd__h520621, + _theResult___sfd__h541039, + _theResult___sfd__h550690, + _theResult___sfd__h559474, + _theResult___sfd__h580343, + _theResult___sfd__h589994, + _theResult___sfd__h598778, + _theResult___snd_fst_sfd__h482458, + _theResult___snd_fst_sfd__h502292, + _theResult___snd_fst_sfd__h520727, + _theResult___snd_fst_sfd__h521452, + _theResult___snd_fst_sfd__h541145, + _theResult___snd_fst_sfd__h559580, + _theResult___snd_fst_sfd__h560756, + _theResult___snd_fst_sfd__h580449, + _theResult___snd_fst_sfd__h598884, + out___1_sfd__h482206, + out___1_sfd__h521200, + out___1_sfd__h560504, + out_sfd__h502189, + out_sfd__h511840, + out_sfd__h520624, + out_sfd__h541042, + out_sfd__h550693, + out_sfd__h559477, + out_sfd__h580346, + out_sfd__h589997, + out_sfd__h598781; + wire [50 : 0] r1__read__h613065, r1__read__h614242; + wire [49 : 0] r1__read__h614351; + wire [48 : 0] r1__read_BITS_62_TO_14___h729548, + r1__read__h613067, + r1__read__h614353; + wire [46 : 0] r1__read__h613069, r1__read__h614246; + wire [45 : 0] r1__read__h613071, r1__read__h614248; + wire [44 : 0] r1__read__h613073, r1__read__h614250; + wire [43 : 0] r1__read__h613075, r1__read__h614252; + wire [42 : 0] r1__read__h614254; + wire [41 : 0] r1__read__h614256; + wire [40 : 0] r1__read__h614258; wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14134, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data75283_BITS_31_TO_0__q13, - imm__h655329, - r1__read__h613076, - r1__read__h614259, - x__h193680, - x__h337885, - x__h383587, - x__h429282, - x__h76238, - x_data__h66087, - x_data_imm__h676657, - x_data_imm__h692711; - wire [29 : 0] r1__read__h613078, r1__read__h614261; - wire [27 : 0] r1__read__h614263; + data75284_BITS_31_TO_0__q13, + imm__h655330, + r1__read__h613077, + r1__read__h614260, + x__h193681, + x__h337886, + x__h383588, + x__h429283, + x__h76239, + x_data__h66088, + x_data_imm__h676658, + x_data_imm__h692712; + wire [29 : 0] r1__read__h613079, r1__read__h614262; + wire [27 : 0] r1__read__h614264; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14166, - sfd__h354289, - sfd__h362871, - sfd__h372055, - sfd__h380667, - sfd__h399986, - sfd__h408568, - sfd__h417752, - sfd__h426364, - sfd__h445681, - sfd__h454263, - sfd__h463447, - sfd__h472059, - value__h487086, - value__h525939, - value__h565243; + sfd__h354290, + sfd__h362872, + sfd__h372056, + sfd__h380668, + sfd__h399987, + sfd__h408569, + sfd__h417753, + sfd__h426365, + sfd__h445682, + sfd__h454264, + sfd__h463448, + sfd__h472060, + value__h487087, + value__h525940, + value__h565244; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349, @@ -5445,74 +5445,74 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808, - _theResult___fst_sfd__h354795, - _theResult___fst_sfd__h363377, - _theResult___fst_sfd__h372561, - _theResult___fst_sfd__h381197, - _theResult___fst_sfd__h381206, - _theResult___fst_sfd__h381212, - _theResult___fst_sfd__h400492, - _theResult___fst_sfd__h409074, - _theResult___fst_sfd__h418258, - _theResult___fst_sfd__h426894, - _theResult___fst_sfd__h426903, - _theResult___fst_sfd__h426909, - _theResult___fst_sfd__h446187, - _theResult___fst_sfd__h454769, - _theResult___fst_sfd__h463953, - _theResult___fst_sfd__h472589, - _theResult___fst_sfd__h472598, - _theResult___fst_sfd__h472604, - _theResult___sfd__h354714, - _theResult___sfd__h363296, - _theResult___sfd__h372480, - _theResult___sfd__h381116, - _theResult___sfd__h381218, - _theResult___sfd__h400411, - _theResult___sfd__h408993, - _theResult___sfd__h418177, - _theResult___sfd__h426813, - _theResult___sfd__h426915, - _theResult___sfd__h446106, - _theResult___sfd__h454688, - _theResult___sfd__h463872, - _theResult___sfd__h472508, - _theResult___sfd__h472610, - _theResult___snd_fst_sfd__h338431, - _theResult___snd_fst_sfd__h363380, - _theResult___snd_fst_sfd__h381200, - _theResult___snd_fst_sfd__h384133, - _theResult___snd_fst_sfd__h409077, - _theResult___snd_fst_sfd__h426897, - _theResult___snd_fst_sfd__h429828, - _theResult___snd_fst_sfd__h454772, - _theResult___snd_fst_sfd__h472592, - f1_sfd__h482142, - f2_sfd__h521136, - f3_sfd__h560440, - out_f_sfd__h381495, - out_f_sfd__h427192, - out_f_sfd__h472887, - out_sfd__h354717, - out_sfd__h363299, - out_sfd__h372483, - out_sfd__h381119, - out_sfd__h400414, - out_sfd__h408996, - out_sfd__h418180, - out_sfd__h426816, - out_sfd__h446109, - out_sfd__h454691, - out_sfd__h463875, - out_sfd__h472511; - wire [19 : 0] r1__read__h614198; + _theResult___fst_sfd__h354796, + _theResult___fst_sfd__h363378, + _theResult___fst_sfd__h372562, + _theResult___fst_sfd__h381198, + _theResult___fst_sfd__h381207, + _theResult___fst_sfd__h381213, + _theResult___fst_sfd__h400493, + _theResult___fst_sfd__h409075, + _theResult___fst_sfd__h418259, + _theResult___fst_sfd__h426895, + _theResult___fst_sfd__h426904, + _theResult___fst_sfd__h426910, + _theResult___fst_sfd__h446188, + _theResult___fst_sfd__h454770, + _theResult___fst_sfd__h463954, + _theResult___fst_sfd__h472590, + _theResult___fst_sfd__h472599, + _theResult___fst_sfd__h472605, + _theResult___sfd__h354715, + _theResult___sfd__h363297, + _theResult___sfd__h372481, + _theResult___sfd__h381117, + _theResult___sfd__h381219, + _theResult___sfd__h400412, + _theResult___sfd__h408994, + _theResult___sfd__h418178, + _theResult___sfd__h426814, + _theResult___sfd__h426916, + _theResult___sfd__h446107, + _theResult___sfd__h454689, + _theResult___sfd__h463873, + _theResult___sfd__h472509, + _theResult___sfd__h472611, + _theResult___snd_fst_sfd__h338432, + _theResult___snd_fst_sfd__h363381, + _theResult___snd_fst_sfd__h381201, + _theResult___snd_fst_sfd__h384134, + _theResult___snd_fst_sfd__h409078, + _theResult___snd_fst_sfd__h426898, + _theResult___snd_fst_sfd__h429829, + _theResult___snd_fst_sfd__h454773, + _theResult___snd_fst_sfd__h472593, + f1_sfd__h482143, + f2_sfd__h521137, + f3_sfd__h560441, + out_f_sfd__h381496, + out_f_sfd__h427193, + out_f_sfd__h472888, + out_sfd__h354718, + out_sfd__h363300, + out_sfd__h372484, + out_sfd__h381120, + out_sfd__h400415, + out_sfd__h408997, + out_sfd__h418181, + out_sfd__h426817, + out_sfd__h446110, + out_sfd__h454692, + out_sfd__h463876, + out_sfd__h472512; + wire [19 : 0] r1__read__h614199; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824, - _theResult____h651118, - enabled_ints___1__h651643, - enabled_ints__h651689, - pend_ints__h651116, - y__h651655; - wire [13 : 0] r1__read_BITS_13_TO_0___h651665; + _theResult____h651119, + enabled_ints___1__h651644, + enabled_ints__h651690, + pend_ints__h651117, + y__h651656; + wire [13 : 0] r1__read_BITS_13_TO_0___h651666; wire [12 : 0] IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15288, fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505; @@ -5545,25 +5545,25 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338, - csr_addr__h655327, - renaming_spec_bits__h685239, - result__h646695, - result__h646746, - spec_bits__h688398, - w__h646690, - x__h364468, - x__h410165, - x__h455860, - x__h503611, - x__h542464, - x__h581768, - x__h646694, - x__h646745, - y__h646724, - y__h688411, - y_avValue_fst__h681571, - y_avValue_fst__h681600, - y_avValue_fst__h681634; + csr_addr__h655328, + renaming_spec_bits__h685240, + result__h646696, + result__h646747, + spec_bits__h688399, + w__h646691, + x__h364469, + x__h410166, + x__h455861, + x__h503612, + x__h542465, + x__h581769, + x__h646695, + x__h646746, + y__h646725, + y__h688412, + y_avValue_fst__h681572, + y_avValue_fst__h681601, + y_avValue_fst__h681635; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056, @@ -5585,102 +5585,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h502184, - _theResult___exp__h511835, - _theResult___exp__h520619, - _theResult___exp__h541037, - _theResult___exp__h550688, - _theResult___exp__h559472, - _theResult___exp__h580341, - _theResult___exp__h589992, - _theResult___exp__h598776, - _theResult___fst_exp__h486456, - _theResult___fst_exp__h501520, - _theResult___fst_exp__h501526, - _theResult___fst_exp__h501529, - _theResult___fst_exp__h502284, - _theResult___fst_exp__h502287, - _theResult___fst_exp__h511106, - _theResult___fst_exp__h511171, - _theResult___fst_exp__h511177, - _theResult___fst_exp__h511180, - _theResult___fst_exp__h511935, - _theResult___fst_exp__h511938, - _theResult___fst_exp__h519891, - _theResult___fst_exp__h519930, - _theResult___fst_exp__h519936, - _theResult___fst_exp__h519939, - _theResult___fst_exp__h520719, - _theResult___fst_exp__h520722, - _theResult___fst_exp__h520731, - _theResult___fst_exp__h520734, - _theResult___fst_exp__h525309, - _theResult___fst_exp__h540373, - _theResult___fst_exp__h540379, - _theResult___fst_exp__h540382, - _theResult___fst_exp__h541137, - _theResult___fst_exp__h541140, - _theResult___fst_exp__h549959, - _theResult___fst_exp__h550024, - _theResult___fst_exp__h550030, - _theResult___fst_exp__h550033, - _theResult___fst_exp__h550788, - _theResult___fst_exp__h550791, - _theResult___fst_exp__h558744, - _theResult___fst_exp__h558783, - _theResult___fst_exp__h558789, - _theResult___fst_exp__h558792, - _theResult___fst_exp__h559572, - _theResult___fst_exp__h559575, - _theResult___fst_exp__h559584, - _theResult___fst_exp__h559587, - _theResult___fst_exp__h564613, - _theResult___fst_exp__h579677, - _theResult___fst_exp__h579683, - _theResult___fst_exp__h579686, - _theResult___fst_exp__h580441, - _theResult___fst_exp__h580444, - _theResult___fst_exp__h589263, - _theResult___fst_exp__h589328, - _theResult___fst_exp__h589334, - _theResult___fst_exp__h589337, - _theResult___fst_exp__h590092, - _theResult___fst_exp__h590095, - _theResult___fst_exp__h598048, - _theResult___fst_exp__h598087, - _theResult___fst_exp__h598093, - _theResult___fst_exp__h598096, - _theResult___fst_exp__h598876, - _theResult___fst_exp__h598879, - _theResult___fst_exp__h598888, - _theResult___fst_exp__h598891, - _theResult___snd_fst_exp__h502290, - _theResult___snd_fst_exp__h520725, - _theResult___snd_fst_exp__h541143, - _theResult___snd_fst_exp__h559578, - _theResult___snd_fst_exp__h580447, - _theResult___snd_fst_exp__h598882, + _theResult___exp__h502185, + _theResult___exp__h511836, + _theResult___exp__h520620, + _theResult___exp__h541038, + _theResult___exp__h550689, + _theResult___exp__h559473, + _theResult___exp__h580342, + _theResult___exp__h589993, + _theResult___exp__h598777, + _theResult___fst_exp__h486457, + _theResult___fst_exp__h501521, + _theResult___fst_exp__h501527, + _theResult___fst_exp__h501530, + _theResult___fst_exp__h502285, + _theResult___fst_exp__h502288, + _theResult___fst_exp__h511107, + _theResult___fst_exp__h511172, + _theResult___fst_exp__h511178, + _theResult___fst_exp__h511181, + _theResult___fst_exp__h511936, + _theResult___fst_exp__h511939, + _theResult___fst_exp__h519892, + _theResult___fst_exp__h519931, + _theResult___fst_exp__h519937, + _theResult___fst_exp__h519940, + _theResult___fst_exp__h520720, + _theResult___fst_exp__h520723, + _theResult___fst_exp__h520732, + _theResult___fst_exp__h520735, + _theResult___fst_exp__h525310, + _theResult___fst_exp__h540374, + _theResult___fst_exp__h540380, + _theResult___fst_exp__h540383, + _theResult___fst_exp__h541138, + _theResult___fst_exp__h541141, + _theResult___fst_exp__h549960, + _theResult___fst_exp__h550025, + _theResult___fst_exp__h550031, + _theResult___fst_exp__h550034, + _theResult___fst_exp__h550789, + _theResult___fst_exp__h550792, + _theResult___fst_exp__h558745, + _theResult___fst_exp__h558784, + _theResult___fst_exp__h558790, + _theResult___fst_exp__h558793, + _theResult___fst_exp__h559573, + _theResult___fst_exp__h559576, + _theResult___fst_exp__h559585, + _theResult___fst_exp__h559588, + _theResult___fst_exp__h564614, + _theResult___fst_exp__h579678, + _theResult___fst_exp__h579684, + _theResult___fst_exp__h579687, + _theResult___fst_exp__h580442, + _theResult___fst_exp__h580445, + _theResult___fst_exp__h589264, + _theResult___fst_exp__h589329, + _theResult___fst_exp__h589335, + _theResult___fst_exp__h589338, + _theResult___fst_exp__h590093, + _theResult___fst_exp__h590096, + _theResult___fst_exp__h598049, + _theResult___fst_exp__h598088, + _theResult___fst_exp__h598094, + _theResult___fst_exp__h598097, + _theResult___fst_exp__h598877, + _theResult___fst_exp__h598880, + _theResult___fst_exp__h598889, + _theResult___fst_exp__h598892, + _theResult___snd_fst_exp__h502291, + _theResult___snd_fst_exp__h520726, + _theResult___snd_fst_exp__h541144, + _theResult___snd_fst_exp__h559579, + _theResult___snd_fst_exp__h580448, + _theResult___snd_fst_exp__h598883, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106, - din_inc___2_exp__h520779, - din_inc___2_exp__h520814, - din_inc___2_exp__h520840, - din_inc___2_exp__h559632, - din_inc___2_exp__h559667, - din_inc___2_exp__h559693, - din_inc___2_exp__h598936, - din_inc___2_exp__h598971, - din_inc___2_exp__h598997, - out_exp__h502187, - out_exp__h511838, - out_exp__h520622, - out_exp__h541040, - out_exp__h550691, - out_exp__h559475, - out_exp__h580344, - out_exp__h589995, - out_exp__h598779; + din_inc___2_exp__h520780, + din_inc___2_exp__h520815, + din_inc___2_exp__h520841, + din_inc___2_exp__h559633, + din_inc___2_exp__h559668, + din_inc___2_exp__h559694, + din_inc___2_exp__h598937, + din_inc___2_exp__h598972, + din_inc___2_exp__h598998, + out_exp__h502188, + out_exp__h511839, + out_exp__h520623, + out_exp__h541041, + out_exp__h550692, + out_exp__h559476, + out_exp__h580345, + out_exp__h589996, + out_exp__h598780; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656; @@ -5711,124 +5711,124 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112, - _theResult___exp__h354713, - _theResult___exp__h363295, - _theResult___exp__h372479, - _theResult___exp__h381115, - _theResult___exp__h381217, - _theResult___exp__h400410, - _theResult___exp__h408992, - _theResult___exp__h418176, - _theResult___exp__h426812, - _theResult___exp__h426914, - _theResult___exp__h446105, - _theResult___exp__h454687, - _theResult___exp__h463871, - _theResult___exp__h472507, - _theResult___exp__h472609, - _theResult___fst_exp__h354197, - _theResult___fst_exp__h354262, - _theResult___fst_exp__h354268, - _theResult___fst_exp__h354271, - _theResult___fst_exp__h354794, - _theResult___fst_exp__h362844, - _theResult___fst_exp__h362850, - _theResult___fst_exp__h362853, - _theResult___fst_exp__h363376, - _theResult___fst_exp__h371963, - _theResult___fst_exp__h372028, - _theResult___fst_exp__h372034, - _theResult___fst_exp__h372037, - _theResult___fst_exp__h372560, - _theResult___fst_exp__h380600, - _theResult___fst_exp__h380639, - _theResult___fst_exp__h380645, - _theResult___fst_exp__h380648, - _theResult___fst_exp__h381196, - _theResult___fst_exp__h381205, - _theResult___fst_exp__h381208, - _theResult___fst_exp__h399894, - _theResult___fst_exp__h399959, - _theResult___fst_exp__h399965, - _theResult___fst_exp__h399968, - _theResult___fst_exp__h400491, - _theResult___fst_exp__h408541, - _theResult___fst_exp__h408547, - _theResult___fst_exp__h408550, - _theResult___fst_exp__h409073, - _theResult___fst_exp__h417660, - _theResult___fst_exp__h417725, - _theResult___fst_exp__h417731, - _theResult___fst_exp__h417734, - _theResult___fst_exp__h418257, - _theResult___fst_exp__h426297, - _theResult___fst_exp__h426336, - _theResult___fst_exp__h426342, - _theResult___fst_exp__h426345, - _theResult___fst_exp__h426893, - _theResult___fst_exp__h426902, - _theResult___fst_exp__h426905, - _theResult___fst_exp__h445589, - _theResult___fst_exp__h445654, - _theResult___fst_exp__h445660, - _theResult___fst_exp__h445663, - _theResult___fst_exp__h446186, - _theResult___fst_exp__h454236, - _theResult___fst_exp__h454242, - _theResult___fst_exp__h454245, - _theResult___fst_exp__h454768, - _theResult___fst_exp__h463355, - _theResult___fst_exp__h463420, - _theResult___fst_exp__h463426, - _theResult___fst_exp__h463429, - _theResult___fst_exp__h463952, - _theResult___fst_exp__h471992, - _theResult___fst_exp__h472031, - _theResult___fst_exp__h472037, - _theResult___fst_exp__h472040, - _theResult___fst_exp__h472588, - _theResult___fst_exp__h472597, - _theResult___fst_exp__h472600, - _theResult___snd_fst_exp__h363379, - _theResult___snd_fst_exp__h381199, - _theResult___snd_fst_exp__h409076, - _theResult___snd_fst_exp__h426896, - _theResult___snd_fst_exp__h454771, - _theResult___snd_fst_exp__h472591, - din_inc___2_exp__h381230, - din_inc___2_exp__h381254, - din_inc___2_exp__h381284, - din_inc___2_exp__h381308, - din_inc___2_exp__h426927, - din_inc___2_exp__h426951, - din_inc___2_exp__h426981, - din_inc___2_exp__h427005, - din_inc___2_exp__h472622, - din_inc___2_exp__h472646, - din_inc___2_exp__h472676, - din_inc___2_exp__h472700, - f1_exp82141_MINUS_127__q136, - f1_exp__h482141, - f2_exp21135_MINUS_127__q176, - f2_exp__h521135, - f3_exp60439_MINUS_127__q153, - f3_exp__h560439, - out_exp__h354716, - out_exp__h363298, - out_exp__h372482, - out_exp__h381118, - out_exp__h400413, - out_exp__h408995, - out_exp__h418179, - out_exp__h426815, - out_exp__h446108, - out_exp__h454690, - out_exp__h463874, - out_exp__h472510, - out_f_exp__h381494, - out_f_exp__h427191, - out_f_exp__h472886, - x__h613035; + _theResult___exp__h354714, + _theResult___exp__h363296, + _theResult___exp__h372480, + _theResult___exp__h381116, + _theResult___exp__h381218, + _theResult___exp__h400411, + _theResult___exp__h408993, + _theResult___exp__h418177, + _theResult___exp__h426813, + _theResult___exp__h426915, + _theResult___exp__h446106, + _theResult___exp__h454688, + _theResult___exp__h463872, + _theResult___exp__h472508, + _theResult___exp__h472610, + _theResult___fst_exp__h354198, + _theResult___fst_exp__h354263, + _theResult___fst_exp__h354269, + _theResult___fst_exp__h354272, + _theResult___fst_exp__h354795, + _theResult___fst_exp__h362845, + _theResult___fst_exp__h362851, + _theResult___fst_exp__h362854, + _theResult___fst_exp__h363377, + _theResult___fst_exp__h371964, + _theResult___fst_exp__h372029, + _theResult___fst_exp__h372035, + _theResult___fst_exp__h372038, + _theResult___fst_exp__h372561, + _theResult___fst_exp__h380601, + _theResult___fst_exp__h380640, + _theResult___fst_exp__h380646, + _theResult___fst_exp__h380649, + _theResult___fst_exp__h381197, + _theResult___fst_exp__h381206, + _theResult___fst_exp__h381209, + _theResult___fst_exp__h399895, + _theResult___fst_exp__h399960, + _theResult___fst_exp__h399966, + _theResult___fst_exp__h399969, + _theResult___fst_exp__h400492, + _theResult___fst_exp__h408542, + _theResult___fst_exp__h408548, + _theResult___fst_exp__h408551, + _theResult___fst_exp__h409074, + _theResult___fst_exp__h417661, + _theResult___fst_exp__h417726, + _theResult___fst_exp__h417732, + _theResult___fst_exp__h417735, + _theResult___fst_exp__h418258, + _theResult___fst_exp__h426298, + _theResult___fst_exp__h426337, + _theResult___fst_exp__h426343, + _theResult___fst_exp__h426346, + _theResult___fst_exp__h426894, + _theResult___fst_exp__h426903, + _theResult___fst_exp__h426906, + _theResult___fst_exp__h445590, + _theResult___fst_exp__h445655, + _theResult___fst_exp__h445661, + _theResult___fst_exp__h445664, + _theResult___fst_exp__h446187, + _theResult___fst_exp__h454237, + _theResult___fst_exp__h454243, + _theResult___fst_exp__h454246, + _theResult___fst_exp__h454769, + _theResult___fst_exp__h463356, + _theResult___fst_exp__h463421, + _theResult___fst_exp__h463427, + _theResult___fst_exp__h463430, + _theResult___fst_exp__h463953, + _theResult___fst_exp__h471993, + _theResult___fst_exp__h472032, + _theResult___fst_exp__h472038, + _theResult___fst_exp__h472041, + _theResult___fst_exp__h472589, + _theResult___fst_exp__h472598, + _theResult___fst_exp__h472601, + _theResult___snd_fst_exp__h363380, + _theResult___snd_fst_exp__h381200, + _theResult___snd_fst_exp__h409077, + _theResult___snd_fst_exp__h426897, + _theResult___snd_fst_exp__h454772, + _theResult___snd_fst_exp__h472592, + din_inc___2_exp__h381231, + din_inc___2_exp__h381255, + din_inc___2_exp__h381285, + din_inc___2_exp__h381309, + din_inc___2_exp__h426928, + din_inc___2_exp__h426952, + din_inc___2_exp__h426982, + din_inc___2_exp__h427006, + din_inc___2_exp__h472623, + din_inc___2_exp__h472647, + din_inc___2_exp__h472677, + din_inc___2_exp__h472701, + f1_exp82142_MINUS_127__q136, + f1_exp__h482142, + f2_exp21136_MINUS_127__q176, + f2_exp__h521136, + f3_exp60440_MINUS_127__q153, + f3_exp__h560440, + out_exp__h354717, + out_exp__h363299, + out_exp__h372483, + out_exp__h381119, + out_exp__h400414, + out_exp__h408996, + out_exp__h418180, + out_exp__h426816, + out_exp__h446109, + out_exp__h454691, + out_exp__h463875, + out_exp__h472511, + out_f_exp__h381495, + out_f_exp__h427192, + out_f_exp__h472887, + x__h613036; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031, @@ -5849,8 +5849,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16102, - x__h181700, - x__h712418; + x__h181701, + x__h712419; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169, @@ -5870,25 +5870,25 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965, checkForException___d13008, checkForException___d13698, - fflags__h728014, - fflags__h730667, - fflags__h733287, - old_fflags__h732774, - po_fflags__h727999, - po_fflags__h730652, - r1__read__h614601, - res_fflags__h337871, - res_fflags__h383573, - res_fflags__h429268, + fflags__h727885, + fflags__h730538, + fflags__h733158, + old_fflags__h732645, + po_fflags__h727870, + po_fflags__h730523, + r1__read__h614602, + res_fflags__h337872, + res_fflags__h383574, + res_fflags__h429269, rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, - rs1__h655328, - x__h153726, - x__h157273, - x__h160089, - x__h287280, - y_avValue_fst__h730027, - y_avValue_fst__h733192, - y_avValue_fst__h733224; + rs1__h655329, + x__h153727, + x__h157274, + x__h160090, + x__h287281, + y_avValue_fst__h729898, + y_avValue_fst__h733063, + y_avValue_fst__h733095; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855, @@ -5915,77 +5915,77 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h709443, - vm_mode_reg__read__h614204; + cause_code__h709444, + vm_mode_reg__read__h614205; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h296522, - dcsr_cause__h708962, - next_deqP___1__h296801, - v__h295942, - v__h296173, - x__h302152, - x_decodeInfo_frm__h655012; + _theResult_____2__h296523, + dcsr_cause__h708963, + next_deqP___1__h296802, + v__h295943, + v__h296174, + x__h302153, + x_decodeInfo_frm__h655013; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689, - IF_sfdin11100_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin17654_BIT_33_THEN_2_ELSE_0__q74, - IF_sfdin45583_BIT_33_THEN_2_ELSE_0__q99, - IF_sfdin49953_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin54191_BIT_33_THEN_2_ELSE_0__q29, - IF_sfdin63349_BIT_33_THEN_2_ELSE_0__q109, - IF_sfdin71957_BIT_33_THEN_2_ELSE_0__q39, - IF_sfdin89257_BIT_4_THEN_2_ELSE_0__q156, - IF_sfdin99888_BIT_33_THEN_2_ELSE_0__q64, - IF_theResult___snd01480_BIT_4_THEN_2_ELSE_0__q135, - IF_theResult___snd08501_BIT_33_THEN_2_ELSE_0__q66, - IF_theResult___snd19885_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd26291_BIT_33_THEN_2_ELSE_0__q79, - IF_theResult___snd40333_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd54196_BIT_33_THEN_2_ELSE_0__q101, - IF_theResult___snd58738_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd62804_BIT_33_THEN_2_ELSE_0__q31, - IF_theResult___snd71986_BIT_33_THEN_2_ELSE_0__q114, - IF_theResult___snd79637_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd80594_BIT_33_THEN_2_ELSE_0__q44, - IF_theResult___snd98042_BIT_4_THEN_2_ELSE_0__q159, - guard__h346096, - guard__h354805, - guard__h363735, - guard__h372571, - guard__h391795, - guard__h400502, - guard__h409432, - guard__h418268, - guard__h437490, - guard__h446197, - guard__h455127, - guard__h463963, - guard__h493568, - guard__h502880, - guard__h511949, - guard__h532421, - guard__h541733, - guard__h550802, - guard__h571725, - guard__h581037, - guard__h590106, - prv__h734956, - prv__h735000, - r1__read_BITS_13_TO_12___h655197, - sbIdx__h157152, - v__h603884, - v__h603894, - v__h604529, - x__h722556, - x__h733551, - x_prv__h712487, - x_prv__h723013, - y_avValue_snd_snd_snd_fst__h730502, - y_avValue_snd_snd_snd_fst__h733361, - y_avValue_snd_snd_snd_fst__h733397; + IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74, + IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99, + IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29, + IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109, + IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39, + IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156, + IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64, + IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135, + IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66, + IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79, + IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101, + IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31, + IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114, + IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44, + IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159, + guard__h346097, + guard__h354806, + guard__h363736, + guard__h372572, + guard__h391796, + guard__h400503, + guard__h409433, + guard__h418269, + guard__h437491, + guard__h446198, + guard__h455128, + guard__h463964, + guard__h493569, + guard__h502881, + guard__h511950, + guard__h532422, + guard__h541734, + guard__h550803, + guard__h571726, + guard__h581038, + guard__h590107, + prv__h734827, + prv__h734871, + r1__read_BITS_13_TO_12___h655198, + sbIdx__h157153, + v__h603885, + v__h603895, + v__h604530, + x__h722557, + x__h733422, + x_prv__h712488, + x_prv__h723014, + y_avValue_snd_snd_snd_fst__h730373, + y_avValue_snd_snd_snd_fst__h733232, + y_avValue_snd_snd_snd_fst__h733268; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461, @@ -6425,11 +6425,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h304518, - _theResult_____2__h310512, - _theResult_____2__h318366, - _theResult_____2__h328710, - _theResult_____2__h331935, + _theResult_____2__h304519, + _theResult_____2__h310513, + _theResult_____2__h318367, + _theResult_____2__h328711, + _theResult_____2__h331936, commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244, @@ -6565,14 +6565,14 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13835, fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13973, fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13985, - guard__h364333, - guard__h410030, - guard__h455725, - guard__h503478, - guard__h542331, - guard__h581635, - idx__h685370, - k__h669625, + guard__h364334, + guard__h410031, + guard__h455726, + guard__h503479, + guard__h542332, + guard__h581636, + idx__h685371, + k__h669626, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6585,13 +6585,13 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14094, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h76123, - next_deqP___1__h304797, - next_deqP___1__h311078, - next_deqP___1__h318932, - next_deqP___1__h328989, - next_deqP___1__h332214, - r1__read_BIT_20___h655893, + msip__h76124, + next_deqP___1__h304798, + next_deqP___1__h311079, + next_deqP___1__h318933, + next_deqP___1__h328990, + next_deqP___1__h332215, + r1__read_BIT_20___h655894, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941, regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022, @@ -6621,19 +6621,19 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, - tsr_val__h726308, - tvm_val__h726310, - v__h299287, - v__h299805, - v__h309801, - v__h310032, - v__h313677, - v__h313908, - v__h328278, - v__h328509, - v__h331503, - v__h331734, - x__h603385; + tsr_val__h726179, + tvm_val__h726181, + v__h299288, + v__h299806, + v__h309802, + v__h310033, + v__h313678, + v__h313909, + v__h328279, + v__h328510, + v__h331504, + v__h331735, + x__h603386; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -12027,13 +12027,13 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h702377, + x__h702378, rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h733310 ; + commitStage_rg_serial_num + y__h733181 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12047,7 +12047,7 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h669625 == 1'd0 && + (k__h669626 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12068,7 +12068,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -12159,7 +12159,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, @@ -12173,10 +12173,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h285847 } ; + x__h285848 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h287292, + x__h287293, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12184,7 +12184,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h290068, + addr__h290069, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12197,12 +12197,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h153726, x__h153732, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h153727, x__h153733, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h157273, x__h157279, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h157274, x__h157280, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h160089, - x__h160093, + { x__h160090, + x__h160094, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -12213,7 +12213,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161941, + x__h161942, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -12226,7 +12226,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h291972, + resp_addr__h291973, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -12234,8 +12234,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h735000, - prv__h735000 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h734871, + prv__h734871 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12312,7 +12312,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h197127 } ; + x__h197128 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12347,8 +12347,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h192917 : - { {32{x__h193680[31]}}, x__h193680 } } ; + curData__h192918 : + { {32{x__h193681[31]}}, x__h193681 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12381,7 +12381,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h733287 ; + csrf_fflags_reg | fflags__h733158 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1) ? @@ -12424,9 +12424,9 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h726694 + 64'd1 ; + n__read__h726565 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h726694 + { 62'd0, x__h733551 } ; + n__read__h726565 + { 62'd0, x__h733422 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == @@ -12452,12 +12452,12 @@ module mkCore(CLK, 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h722556 : + x__h722557 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h708962, + dcsr_cause__h708963, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12473,7 +12473,7 @@ module mkCore(CLK, 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h737401 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h737272 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12482,12 +12482,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h722452 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h722453 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h722452; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h722453; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12522,24 +12522,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h337875 : - res_data__h337870 ; + res_data__h337876 : + res_data__h337871 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h383577 : - res_data__h383572 ; + res_data__h383578 : + res_data__h383573 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h429272 : - res_data__h429267 ; + res_data__h429273 : + res_data__h429268 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h475009 : + data___1__h475010 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h475817 : - data__h475283 ; + data___1__h475818 : + data__h475284 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -12608,15 +12608,15 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h337871 ; + res_fflags__h337872 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h383573 ; + res_fflags__h383574 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h429268 ; + res_fflags__h429269 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, @@ -12632,19 +12632,19 @@ module mkCore(CLK, rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[161:98], IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512, - fflags__h728014, + fflags__h727885, rob$deqPort_0_deq_data[26], - x__h729657, + x__h729528, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, 13'd4932, - mip_csr__read__h611252, + mip_csr__read__h611253, 721'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_5 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, - x__h723033, + x__h723034, rob$deqPort_0_deq_data[361:182], rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[167], @@ -12940,7 +12940,7 @@ module mkCore(CLK, CAN_FIRE_RL_commitStage_rl_send_tv_reset ; // register commitStage_rg_old_mip_csr_val - assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h611252 ; + assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h611253 ; assign commitStage_rg_old_mip_csr_val$EN = CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; @@ -13003,8 +13003,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h604529 : - v__h603884 ; + v__h604530 : + v__h603885 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -13111,7 +13111,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h296522 ; + _theResult_____2__h296523 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -13133,7 +13133,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h295942 ; + v__h295943 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -13179,7 +13179,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - _theResult_____2__h304518 ; + _theResult_____2__h304519 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -13197,7 +13197,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - v__h299287 ; + v__h299288 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13297,7 +13297,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - _theResult_____2__h310512 ; + _theResult_____2__h310513 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13315,7 +13315,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - v__h309801 ; + v__h309802 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13336,7 +13336,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h314075, + { x_addr__h314076, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13366,7 +13366,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - _theResult_____2__h318366 ; + _theResult_____2__h318367 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13384,7 +13384,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - v__h313677 ; + v__h313678 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13461,7 +13461,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - _theResult_____2__h331935 ; + _theResult_____2__h331936 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13479,7 +13479,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - v__h331503 ; + v__h331504 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13522,7 +13522,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - _theResult_____2__h328710 ; + _theResult_____2__h328711 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13540,7 +13540,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - v__h328278 ; + v__h328279 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13899,13 +13899,13 @@ module mkCore(CLK, always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h709443 or + cause_code__h709444 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h709443; + csrf_mcause_code_reg$D_IN = cause_code__h709444; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14168,12 +14168,12 @@ module mkCore(CLK, always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h709444 or + trap_val__h709445 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h709444; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h709445; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14300,13 +14300,13 @@ module mkCore(CLK, always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h712487 or + x_prv__h712488 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h712487; + csrf_prv_reg$D_IN = x_prv__h712488; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; @@ -14463,13 +14463,13 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h709443 or + cause_code__h709444 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h709443; + csrf_scause_code_reg$D_IN = cause_code__h709444; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14693,12 +14693,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h709444 or + trap_val__h709445 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h709444; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h709445; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14896,7 +14896,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46293, + { x__h46294, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14908,7 +14908,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48829 } ; + x__h48830 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -15001,7 +15001,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18386, + { x__h18387, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15013,7 +15013,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20924 } ; + x__h20925 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -15097,7 +15097,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h66087 } ; + x_data__h66088 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -15340,8 +15340,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h639741, x__h639742, + x__h639743, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -15631,8 +15631,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h617232, x__h617233, + x__h617234, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -15674,7 +15674,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h669625 == 1'd1 && + (k__h669626 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -15695,7 +15695,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16174,19 +16174,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h603371 : - a__h602949 ; + _theResult___fst__h603372 : + a__h602950 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h602950 == 64'd0, - a__h602949, + { b__h602951 == 64'd0, + a__h602950, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h603385, - a__h602949[63], + x__h603386, + a__h602950[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h603372 : - b__h602950 ; + _theResult___snd__h603373 : + b__h602951 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -16247,20 +16247,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602949 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602950 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602950 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602951 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h602949 ; + a__h602950 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h602950 ; + b__h602951 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h602949 ; + a__h602950 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h602950 ; + b__h602951 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -16289,9 +16289,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h481671, x__h481672, x__h481673, + x__h481674, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -16343,7 +16343,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16497,8 +16497,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h287280, - x__h287292, + { x__h287281, + x__h287293, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797, @@ -16509,13 +16509,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828, - x__h289146, + x__h289147, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h285847 ; + x__h285848 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -17309,7 +17309,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685239 ; + renaming_spec_bits__h685240 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? @@ -17329,7 +17329,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685239 ; + renaming_spec_bits__h685240 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17409,7 +17409,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h181568 ; + shiftData__h181569 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17509,8 +17509,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h181477, x__h181478, + x__h181479, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -17774,7 +17774,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -18222,7 +18222,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h712387 or + pc__h712388 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18236,7 +18236,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h712387; + fetchStage$redirect_pc = pc__h712388; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18656,7 +18656,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h685239 ; + renaming_spec_bits__h685240 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -18928,7 +18928,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, 7'd32, - renaming_spec_bits__h685239 } ; + renaming_spec_bits__h685240 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -19588,9 +19588,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, rob$deqPort_1_deq_data[95:32], - fflags__h730667, + fflags__h730538, rob$deqPort_1_deq_data[26], - x__h732802, + x__h732673, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19612,15 +19612,15 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h192917), + .amoExec_current_data(curData__h192918), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h194455)); + .amoExec(n__h194456)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h76123 }), - .amoExec_in_data({ 32'd0, x__h76238 }), + msip__h76124 }), + .amoExec_in_data({ 32'd0, x__h76239 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d880)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], @@ -19652,7 +19652,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 }, fetchStage$pipelines_0_first[160], - x_data_imm__h676657 } }), + x_data_imm__h676658 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19661,13 +19661,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655012, - r1__read_BITS_13_TO_12___h655197 != + .checkForException_csrState({ x_decodeInfo_frm__h655013, + r1__read_BITS_13_TO_12___h655198 != 2'd0, - { prv__h734956, - tvm_val__h726310, - { r1__read_BIT_20___h655893, - tsr_val__h726308, + { prv__h734827, + tvm_val__h726181, + { r1__read_BIT_20___h655894, + tsr_val__h726179, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19682,7 +19682,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, { fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, fetchStage$pipelines_1_first[160], - x_data_imm__h692711 } }), + x_data_imm__h692712 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19691,13 +19691,13 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655012, - r1__read_BITS_13_TO_12___h655197 != + .checkForException_csrState({ x_decodeInfo_frm__h655013, + r1__read_BITS_13_TO_12___h655198 != 2'd0, - { prv__h734956, - tvm_val__h726310, - { r1__read_BIT_20___h655893, - tsr_val__h726308, + { prv__h734827, + tvm_val__h726181, + { r1__read_BIT_20___h655894, + tsr_val__h726179, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19711,1196 +19711,1196 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h481762), - .execFpuSimple_rVal2(rVal2__h481763), + .execFpuSimple_rVal1(rVal1__h481763), + .execFpuSimple_rVal2(rVal2__h481764), .execFpuSimple(execFpuSimple___d11056)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 ? - _theResult___snd__h354260 : - _theResult____h346086 ; + _theResult___snd__h354261 : + _theResult____h346087 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 ? - _theResult___snd__h399957 : - _theResult____h391785 ; + _theResult___snd__h399958 : + _theResult____h391786 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 ? - _theResult___snd__h445652 : - _theResult____h437480 ; + _theResult___snd__h445653 : + _theResult____h437481 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 ? - _theResult___snd__h511169 : - _theResult____h502870 ; + _theResult___snd__h511170 : + _theResult____h502871 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 ? - _theResult___snd__h589326 : - _theResult____h581027 ; + _theResult___snd__h589327 : + _theResult____h581028 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 ? - _theResult___snd__h550022 : - _theResult____h541723 ; + _theResult___snd__h550023 : + _theResult____h541724 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 ? - _theResult___snd__h463418 : - _theResult____h455117 ; + _theResult___snd__h463419 : + _theResult____h455118 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 ? - _theResult___snd__h372026 : - _theResult____h363725 ; + _theResult___snd__h372027 : + _theResult____h363726 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 ? - _theResult___snd__h417723 : - _theResult____h409422 ; + _theResult___snd__h417724 : + _theResult____h409423 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 ? - _theResult___snd__h501518 : + _theResult___snd__h501519 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 ? - _theResult___snd__h501518 : - _theResult___snd__h519923 ; + _theResult___snd__h501519 : + _theResult___snd__h519924 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 ? - _theResult___snd__h579675 : + _theResult___snd__h579676 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 ? - _theResult___snd__h579675 : - _theResult___snd__h598080 ; + _theResult___snd__h579676 : + _theResult___snd__h598081 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 ? - _theResult___snd__h540371 : + _theResult___snd__h540372 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 ? - _theResult___snd__h540371 : - _theResult___snd__h558776 ; + _theResult___snd__h540372 : + _theResult___snd__h558777 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 ? - _theResult___snd__h454234 : + _theResult___snd__h454235 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 ? - _theResult___snd__h454234 : - _theResult___snd__h472024 ; + _theResult___snd__h454235 : + _theResult___snd__h472025 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 ? - _theResult___snd__h362842 : + _theResult___snd__h362843 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 ? - _theResult___snd__h362842 : - _theResult___snd__h380632 ; + _theResult___snd__h362843 : + _theResult___snd__h380633 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 ? - _theResult___snd__h408539 : + _theResult___snd__h408540 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 ? - _theResult___snd__h408539 : - _theResult___snd__h426329 ; + _theResult___snd__h408540 : + _theResult___snd__h426330 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354197 == 8'd255) ? + ((_theResult___fst_exp__h354198 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054) : - ((_theResult___fst_exp__h362853 == 8'd255) ? + ((_theResult___fst_exp__h362854 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354197 == 8'd255) ? + ((_theResult___fst_exp__h354198 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110) : - ((_theResult___fst_exp__h362853 == 8'd255) ? + ((_theResult___fst_exp__h362854 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399894 == 8'd255) ? + ((_theResult___fst_exp__h399895 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446) : - ((_theResult___fst_exp__h408550 == 8'd255) ? + ((_theResult___fst_exp__h408551 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399894 == 8'd255) ? + ((_theResult___fst_exp__h399895 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502) : - ((_theResult___fst_exp__h408550 == 8'd255) ? + ((_theResult___fst_exp__h408551 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445589 == 8'd255) ? + ((_theResult___fst_exp__h445590 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838) : - ((_theResult___fst_exp__h454245 == 8'd255) ? + ((_theResult___fst_exp__h454246 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445589 == 8'd255) ? + ((_theResult___fst_exp__h445590 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894) : - ((_theResult___fst_exp__h454245 == 8'd255) ? + ((_theResult___fst_exp__h454246 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 = - (_theResult____h346086[56] ? + (_theResult____h346087[56] ? 6'd0 : - (_theResult____h346086[55] ? + (_theResult____h346087[55] ? 6'd1 : - (_theResult____h346086[54] ? + (_theResult____h346087[54] ? 6'd2 : - (_theResult____h346086[53] ? + (_theResult____h346087[53] ? 6'd3 : - (_theResult____h346086[52] ? + (_theResult____h346087[52] ? 6'd4 : - (_theResult____h346086[51] ? + (_theResult____h346087[51] ? 6'd5 : - (_theResult____h346086[50] ? + (_theResult____h346087[50] ? 6'd6 : - (_theResult____h346086[49] ? + (_theResult____h346087[49] ? 6'd7 : - (_theResult____h346086[48] ? + (_theResult____h346087[48] ? 6'd8 : - (_theResult____h346086[47] ? + (_theResult____h346087[47] ? 6'd9 : - (_theResult____h346086[46] ? + (_theResult____h346087[46] ? 6'd10 : - (_theResult____h346086[45] ? + (_theResult____h346087[45] ? 6'd11 : - (_theResult____h346086[44] ? + (_theResult____h346087[44] ? 6'd12 : - (_theResult____h346086[43] ? + (_theResult____h346087[43] ? 6'd13 : - (_theResult____h346086[42] ? + (_theResult____h346087[42] ? 6'd14 : - (_theResult____h346086[41] ? + (_theResult____h346087[41] ? 6'd15 : - (_theResult____h346086[40] ? + (_theResult____h346087[40] ? 6'd16 : - (_theResult____h346086[39] ? + (_theResult____h346087[39] ? 6'd17 : - (_theResult____h346086[38] ? + (_theResult____h346087[38] ? 6'd18 : - (_theResult____h346086[37] ? + (_theResult____h346087[37] ? 6'd19 : - (_theResult____h346086[36] ? + (_theResult____h346087[36] ? 6'd20 : - (_theResult____h346086[35] ? + (_theResult____h346087[35] ? 6'd21 : - (_theResult____h346086[34] ? + (_theResult____h346087[34] ? 6'd22 : - (_theResult____h346086[33] ? + (_theResult____h346087[33] ? 6'd23 : - (_theResult____h346086[32] ? + (_theResult____h346087[32] ? 6'd24 : - (_theResult____h346086[31] ? + (_theResult____h346087[31] ? 6'd25 : - (_theResult____h346086[30] ? + (_theResult____h346087[30] ? 6'd26 : - (_theResult____h346086[29] ? + (_theResult____h346087[29] ? 6'd27 : - (_theResult____h346086[28] ? + (_theResult____h346087[28] ? 6'd28 : - (_theResult____h346086[27] ? + (_theResult____h346087[27] ? 6'd29 : - (_theResult____h346086[26] ? + (_theResult____h346087[26] ? 6'd30 : - (_theResult____h346086[25] ? + (_theResult____h346087[25] ? 6'd31 : - (_theResult____h346086[24] ? + (_theResult____h346087[24] ? 6'd32 : - (_theResult____h346086[23] ? + (_theResult____h346087[23] ? 6'd33 : - (_theResult____h346086[22] ? + (_theResult____h346087[22] ? 6'd34 : - (_theResult____h346086[21] ? + (_theResult____h346087[21] ? 6'd35 : - (_theResult____h346086[20] ? + (_theResult____h346087[20] ? 6'd36 : - (_theResult____h346086[19] ? + (_theResult____h346087[19] ? 6'd37 : - (_theResult____h346086[18] ? + (_theResult____h346087[18] ? 6'd38 : - (_theResult____h346086[17] ? + (_theResult____h346087[17] ? 6'd39 : - (_theResult____h346086[16] ? + (_theResult____h346087[16] ? 6'd40 : - (_theResult____h346086[15] ? + (_theResult____h346087[15] ? 6'd41 : - (_theResult____h346086[14] ? + (_theResult____h346087[14] ? 6'd42 : - (_theResult____h346086[13] ? + (_theResult____h346087[13] ? 6'd43 : - (_theResult____h346086[12] ? + (_theResult____h346087[12] ? 6'd44 : - (_theResult____h346086[11] ? + (_theResult____h346087[11] ? 6'd45 : - (_theResult____h346086[10] ? + (_theResult____h346087[10] ? 6'd46 : - (_theResult____h346086[9] ? + (_theResult____h346087[9] ? 6'd47 : - (_theResult____h346086[8] ? + (_theResult____h346087[8] ? 6'd48 : - (_theResult____h346086[7] ? + (_theResult____h346087[7] ? 6'd49 : - (_theResult____h346086[6] ? + (_theResult____h346087[6] ? 6'd50 : - (_theResult____h346086[5] ? + (_theResult____h346087[5] ? 6'd51 : - (_theResult____h346086[4] ? + (_theResult____h346087[4] ? 6'd52 : - (_theResult____h346086[3] ? + (_theResult____h346087[3] ? 6'd53 : - (_theResult____h346086[2] ? + (_theResult____h346087[2] ? 6'd54 : - (_theResult____h346086[1] ? + (_theResult____h346087[1] ? 6'd55 : - (_theResult____h346086[0] ? + (_theResult____h346087[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 = - (_theResult____h391785[56] ? + (_theResult____h391786[56] ? 6'd0 : - (_theResult____h391785[55] ? + (_theResult____h391786[55] ? 6'd1 : - (_theResult____h391785[54] ? + (_theResult____h391786[54] ? 6'd2 : - (_theResult____h391785[53] ? + (_theResult____h391786[53] ? 6'd3 : - (_theResult____h391785[52] ? + (_theResult____h391786[52] ? 6'd4 : - (_theResult____h391785[51] ? + (_theResult____h391786[51] ? 6'd5 : - (_theResult____h391785[50] ? + (_theResult____h391786[50] ? 6'd6 : - (_theResult____h391785[49] ? + (_theResult____h391786[49] ? 6'd7 : - (_theResult____h391785[48] ? + (_theResult____h391786[48] ? 6'd8 : - (_theResult____h391785[47] ? + (_theResult____h391786[47] ? 6'd9 : - (_theResult____h391785[46] ? + (_theResult____h391786[46] ? 6'd10 : - (_theResult____h391785[45] ? + (_theResult____h391786[45] ? 6'd11 : - (_theResult____h391785[44] ? + (_theResult____h391786[44] ? 6'd12 : - (_theResult____h391785[43] ? + (_theResult____h391786[43] ? 6'd13 : - (_theResult____h391785[42] ? + (_theResult____h391786[42] ? 6'd14 : - (_theResult____h391785[41] ? + (_theResult____h391786[41] ? 6'd15 : - (_theResult____h391785[40] ? + (_theResult____h391786[40] ? 6'd16 : - (_theResult____h391785[39] ? + (_theResult____h391786[39] ? 6'd17 : - (_theResult____h391785[38] ? + (_theResult____h391786[38] ? 6'd18 : - (_theResult____h391785[37] ? + (_theResult____h391786[37] ? 6'd19 : - (_theResult____h391785[36] ? + (_theResult____h391786[36] ? 6'd20 : - (_theResult____h391785[35] ? + (_theResult____h391786[35] ? 6'd21 : - (_theResult____h391785[34] ? + (_theResult____h391786[34] ? 6'd22 : - (_theResult____h391785[33] ? + (_theResult____h391786[33] ? 6'd23 : - (_theResult____h391785[32] ? + (_theResult____h391786[32] ? 6'd24 : - (_theResult____h391785[31] ? + (_theResult____h391786[31] ? 6'd25 : - (_theResult____h391785[30] ? + (_theResult____h391786[30] ? 6'd26 : - (_theResult____h391785[29] ? + (_theResult____h391786[29] ? 6'd27 : - (_theResult____h391785[28] ? + (_theResult____h391786[28] ? 6'd28 : - (_theResult____h391785[27] ? + (_theResult____h391786[27] ? 6'd29 : - (_theResult____h391785[26] ? + (_theResult____h391786[26] ? 6'd30 : - (_theResult____h391785[25] ? + (_theResult____h391786[25] ? 6'd31 : - (_theResult____h391785[24] ? + (_theResult____h391786[24] ? 6'd32 : - (_theResult____h391785[23] ? + (_theResult____h391786[23] ? 6'd33 : - (_theResult____h391785[22] ? + (_theResult____h391786[22] ? 6'd34 : - (_theResult____h391785[21] ? + (_theResult____h391786[21] ? 6'd35 : - (_theResult____h391785[20] ? + (_theResult____h391786[20] ? 6'd36 : - (_theResult____h391785[19] ? + (_theResult____h391786[19] ? 6'd37 : - (_theResult____h391785[18] ? + (_theResult____h391786[18] ? 6'd38 : - (_theResult____h391785[17] ? + (_theResult____h391786[17] ? 6'd39 : - (_theResult____h391785[16] ? + (_theResult____h391786[16] ? 6'd40 : - (_theResult____h391785[15] ? + (_theResult____h391786[15] ? 6'd41 : - (_theResult____h391785[14] ? + (_theResult____h391786[14] ? 6'd42 : - (_theResult____h391785[13] ? + (_theResult____h391786[13] ? 6'd43 : - (_theResult____h391785[12] ? + (_theResult____h391786[12] ? 6'd44 : - (_theResult____h391785[11] ? + (_theResult____h391786[11] ? 6'd45 : - (_theResult____h391785[10] ? + (_theResult____h391786[10] ? 6'd46 : - (_theResult____h391785[9] ? + (_theResult____h391786[9] ? 6'd47 : - (_theResult____h391785[8] ? + (_theResult____h391786[8] ? 6'd48 : - (_theResult____h391785[7] ? + (_theResult____h391786[7] ? 6'd49 : - (_theResult____h391785[6] ? + (_theResult____h391786[6] ? 6'd50 : - (_theResult____h391785[5] ? + (_theResult____h391786[5] ? 6'd51 : - (_theResult____h391785[4] ? + (_theResult____h391786[4] ? 6'd52 : - (_theResult____h391785[3] ? + (_theResult____h391786[3] ? 6'd53 : - (_theResult____h391785[2] ? + (_theResult____h391786[2] ? 6'd54 : - (_theResult____h391785[1] ? + (_theResult____h391786[1] ? 6'd55 : - (_theResult____h391785[0] ? + (_theResult____h391786[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 = - (_theResult____h437480[56] ? + (_theResult____h437481[56] ? 6'd0 : - (_theResult____h437480[55] ? + (_theResult____h437481[55] ? 6'd1 : - (_theResult____h437480[54] ? + (_theResult____h437481[54] ? 6'd2 : - (_theResult____h437480[53] ? + (_theResult____h437481[53] ? 6'd3 : - (_theResult____h437480[52] ? + (_theResult____h437481[52] ? 6'd4 : - (_theResult____h437480[51] ? + (_theResult____h437481[51] ? 6'd5 : - (_theResult____h437480[50] ? + (_theResult____h437481[50] ? 6'd6 : - (_theResult____h437480[49] ? + (_theResult____h437481[49] ? 6'd7 : - (_theResult____h437480[48] ? + (_theResult____h437481[48] ? 6'd8 : - (_theResult____h437480[47] ? + (_theResult____h437481[47] ? 6'd9 : - (_theResult____h437480[46] ? + (_theResult____h437481[46] ? 6'd10 : - (_theResult____h437480[45] ? + (_theResult____h437481[45] ? 6'd11 : - (_theResult____h437480[44] ? + (_theResult____h437481[44] ? 6'd12 : - (_theResult____h437480[43] ? + (_theResult____h437481[43] ? 6'd13 : - (_theResult____h437480[42] ? + (_theResult____h437481[42] ? 6'd14 : - (_theResult____h437480[41] ? + (_theResult____h437481[41] ? 6'd15 : - (_theResult____h437480[40] ? + (_theResult____h437481[40] ? 6'd16 : - (_theResult____h437480[39] ? + (_theResult____h437481[39] ? 6'd17 : - (_theResult____h437480[38] ? + (_theResult____h437481[38] ? 6'd18 : - (_theResult____h437480[37] ? + (_theResult____h437481[37] ? 6'd19 : - (_theResult____h437480[36] ? + (_theResult____h437481[36] ? 6'd20 : - (_theResult____h437480[35] ? + (_theResult____h437481[35] ? 6'd21 : - (_theResult____h437480[34] ? + (_theResult____h437481[34] ? 6'd22 : - (_theResult____h437480[33] ? + (_theResult____h437481[33] ? 6'd23 : - (_theResult____h437480[32] ? + (_theResult____h437481[32] ? 6'd24 : - (_theResult____h437480[31] ? + (_theResult____h437481[31] ? 6'd25 : - (_theResult____h437480[30] ? + (_theResult____h437481[30] ? 6'd26 : - (_theResult____h437480[29] ? + (_theResult____h437481[29] ? 6'd27 : - (_theResult____h437480[28] ? + (_theResult____h437481[28] ? 6'd28 : - (_theResult____h437480[27] ? + (_theResult____h437481[27] ? 6'd29 : - (_theResult____h437480[26] ? + (_theResult____h437481[26] ? 6'd30 : - (_theResult____h437480[25] ? + (_theResult____h437481[25] ? 6'd31 : - (_theResult____h437480[24] ? + (_theResult____h437481[24] ? 6'd32 : - (_theResult____h437480[23] ? + (_theResult____h437481[23] ? 6'd33 : - (_theResult____h437480[22] ? + (_theResult____h437481[22] ? 6'd34 : - (_theResult____h437480[21] ? + (_theResult____h437481[21] ? 6'd35 : - (_theResult____h437480[20] ? + (_theResult____h437481[20] ? 6'd36 : - (_theResult____h437480[19] ? + (_theResult____h437481[19] ? 6'd37 : - (_theResult____h437480[18] ? + (_theResult____h437481[18] ? 6'd38 : - (_theResult____h437480[17] ? + (_theResult____h437481[17] ? 6'd39 : - (_theResult____h437480[16] ? + (_theResult____h437481[16] ? 6'd40 : - (_theResult____h437480[15] ? + (_theResult____h437481[15] ? 6'd41 : - (_theResult____h437480[14] ? + (_theResult____h437481[14] ? 6'd42 : - (_theResult____h437480[13] ? + (_theResult____h437481[13] ? 6'd43 : - (_theResult____h437480[12] ? + (_theResult____h437481[12] ? 6'd44 : - (_theResult____h437480[11] ? + (_theResult____h437481[11] ? 6'd45 : - (_theResult____h437480[10] ? + (_theResult____h437481[10] ? 6'd46 : - (_theResult____h437480[9] ? + (_theResult____h437481[9] ? 6'd47 : - (_theResult____h437480[8] ? + (_theResult____h437481[8] ? 6'd48 : - (_theResult____h437480[7] ? + (_theResult____h437481[7] ? 6'd49 : - (_theResult____h437480[6] ? + (_theResult____h437481[6] ? 6'd50 : - (_theResult____h437480[5] ? + (_theResult____h437481[5] ? 6'd51 : - (_theResult____h437480[4] ? + (_theResult____h437481[4] ? 6'd52 : - (_theResult____h437480[3] ? + (_theResult____h437481[3] ? 6'd53 : - (_theResult____h437480[2] ? + (_theResult____h437481[2] ? 6'd54 : - (_theResult____h437480[1] ? + (_theResult____h437481[1] ? 6'd55 : - (_theResult____h437480[0] ? + (_theResult____h437481[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 = - (_theResult____h541723[56] ? + (_theResult____h541724[56] ? 6'd0 : - (_theResult____h541723[55] ? + (_theResult____h541724[55] ? 6'd1 : - (_theResult____h541723[54] ? + (_theResult____h541724[54] ? 6'd2 : - (_theResult____h541723[53] ? + (_theResult____h541724[53] ? 6'd3 : - (_theResult____h541723[52] ? + (_theResult____h541724[52] ? 6'd4 : - (_theResult____h541723[51] ? + (_theResult____h541724[51] ? 6'd5 : - (_theResult____h541723[50] ? + (_theResult____h541724[50] ? 6'd6 : - (_theResult____h541723[49] ? + (_theResult____h541724[49] ? 6'd7 : - (_theResult____h541723[48] ? + (_theResult____h541724[48] ? 6'd8 : - (_theResult____h541723[47] ? + (_theResult____h541724[47] ? 6'd9 : - (_theResult____h541723[46] ? + (_theResult____h541724[46] ? 6'd10 : - (_theResult____h541723[45] ? + (_theResult____h541724[45] ? 6'd11 : - (_theResult____h541723[44] ? + (_theResult____h541724[44] ? 6'd12 : - (_theResult____h541723[43] ? + (_theResult____h541724[43] ? 6'd13 : - (_theResult____h541723[42] ? + (_theResult____h541724[42] ? 6'd14 : - (_theResult____h541723[41] ? + (_theResult____h541724[41] ? 6'd15 : - (_theResult____h541723[40] ? + (_theResult____h541724[40] ? 6'd16 : - (_theResult____h541723[39] ? + (_theResult____h541724[39] ? 6'd17 : - (_theResult____h541723[38] ? + (_theResult____h541724[38] ? 6'd18 : - (_theResult____h541723[37] ? + (_theResult____h541724[37] ? 6'd19 : - (_theResult____h541723[36] ? + (_theResult____h541724[36] ? 6'd20 : - (_theResult____h541723[35] ? + (_theResult____h541724[35] ? 6'd21 : - (_theResult____h541723[34] ? + (_theResult____h541724[34] ? 6'd22 : - (_theResult____h541723[33] ? + (_theResult____h541724[33] ? 6'd23 : - (_theResult____h541723[32] ? + (_theResult____h541724[32] ? 6'd24 : - (_theResult____h541723[31] ? + (_theResult____h541724[31] ? 6'd25 : - (_theResult____h541723[30] ? + (_theResult____h541724[30] ? 6'd26 : - (_theResult____h541723[29] ? + (_theResult____h541724[29] ? 6'd27 : - (_theResult____h541723[28] ? + (_theResult____h541724[28] ? 6'd28 : - (_theResult____h541723[27] ? + (_theResult____h541724[27] ? 6'd29 : - (_theResult____h541723[26] ? + (_theResult____h541724[26] ? 6'd30 : - (_theResult____h541723[25] ? + (_theResult____h541724[25] ? 6'd31 : - (_theResult____h541723[24] ? + (_theResult____h541724[24] ? 6'd32 : - (_theResult____h541723[23] ? + (_theResult____h541724[23] ? 6'd33 : - (_theResult____h541723[22] ? + (_theResult____h541724[22] ? 6'd34 : - (_theResult____h541723[21] ? + (_theResult____h541724[21] ? 6'd35 : - (_theResult____h541723[20] ? + (_theResult____h541724[20] ? 6'd36 : - (_theResult____h541723[19] ? + (_theResult____h541724[19] ? 6'd37 : - (_theResult____h541723[18] ? + (_theResult____h541724[18] ? 6'd38 : - (_theResult____h541723[17] ? + (_theResult____h541724[17] ? 6'd39 : - (_theResult____h541723[16] ? + (_theResult____h541724[16] ? 6'd40 : - (_theResult____h541723[15] ? + (_theResult____h541724[15] ? 6'd41 : - (_theResult____h541723[14] ? + (_theResult____h541724[14] ? 6'd42 : - (_theResult____h541723[13] ? + (_theResult____h541724[13] ? 6'd43 : - (_theResult____h541723[12] ? + (_theResult____h541724[12] ? 6'd44 : - (_theResult____h541723[11] ? + (_theResult____h541724[11] ? 6'd45 : - (_theResult____h541723[10] ? + (_theResult____h541724[10] ? 6'd46 : - (_theResult____h541723[9] ? + (_theResult____h541724[9] ? 6'd47 : - (_theResult____h541723[8] ? + (_theResult____h541724[8] ? 6'd48 : - (_theResult____h541723[7] ? + (_theResult____h541724[7] ? 6'd49 : - (_theResult____h541723[6] ? + (_theResult____h541724[6] ? 6'd50 : - (_theResult____h541723[5] ? + (_theResult____h541724[5] ? 6'd51 : - (_theResult____h541723[4] ? + (_theResult____h541724[4] ? 6'd52 : - (_theResult____h541723[3] ? + (_theResult____h541724[3] ? 6'd53 : - (_theResult____h541723[2] ? + (_theResult____h541724[2] ? 6'd54 : - (_theResult____h541723[1] ? + (_theResult____h541724[1] ? 6'd55 : - (_theResult____h541723[0] ? + (_theResult____h541724[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 = - (_theResult____h502870[56] ? + (_theResult____h502871[56] ? 6'd0 : - (_theResult____h502870[55] ? + (_theResult____h502871[55] ? 6'd1 : - (_theResult____h502870[54] ? + (_theResult____h502871[54] ? 6'd2 : - (_theResult____h502870[53] ? + (_theResult____h502871[53] ? 6'd3 : - (_theResult____h502870[52] ? + (_theResult____h502871[52] ? 6'd4 : - (_theResult____h502870[51] ? + (_theResult____h502871[51] ? 6'd5 : - (_theResult____h502870[50] ? + (_theResult____h502871[50] ? 6'd6 : - (_theResult____h502870[49] ? + (_theResult____h502871[49] ? 6'd7 : - (_theResult____h502870[48] ? + (_theResult____h502871[48] ? 6'd8 : - (_theResult____h502870[47] ? + (_theResult____h502871[47] ? 6'd9 : - (_theResult____h502870[46] ? + (_theResult____h502871[46] ? 6'd10 : - (_theResult____h502870[45] ? + (_theResult____h502871[45] ? 6'd11 : - (_theResult____h502870[44] ? + (_theResult____h502871[44] ? 6'd12 : - (_theResult____h502870[43] ? + (_theResult____h502871[43] ? 6'd13 : - (_theResult____h502870[42] ? + (_theResult____h502871[42] ? 6'd14 : - (_theResult____h502870[41] ? + (_theResult____h502871[41] ? 6'd15 : - (_theResult____h502870[40] ? + (_theResult____h502871[40] ? 6'd16 : - (_theResult____h502870[39] ? + (_theResult____h502871[39] ? 6'd17 : - (_theResult____h502870[38] ? + (_theResult____h502871[38] ? 6'd18 : - (_theResult____h502870[37] ? + (_theResult____h502871[37] ? 6'd19 : - (_theResult____h502870[36] ? + (_theResult____h502871[36] ? 6'd20 : - (_theResult____h502870[35] ? + (_theResult____h502871[35] ? 6'd21 : - (_theResult____h502870[34] ? + (_theResult____h502871[34] ? 6'd22 : - (_theResult____h502870[33] ? + (_theResult____h502871[33] ? 6'd23 : - (_theResult____h502870[32] ? + (_theResult____h502871[32] ? 6'd24 : - (_theResult____h502870[31] ? + (_theResult____h502871[31] ? 6'd25 : - (_theResult____h502870[30] ? + (_theResult____h502871[30] ? 6'd26 : - (_theResult____h502870[29] ? + (_theResult____h502871[29] ? 6'd27 : - (_theResult____h502870[28] ? + (_theResult____h502871[28] ? 6'd28 : - (_theResult____h502870[27] ? + (_theResult____h502871[27] ? 6'd29 : - (_theResult____h502870[26] ? + (_theResult____h502871[26] ? 6'd30 : - (_theResult____h502870[25] ? + (_theResult____h502871[25] ? 6'd31 : - (_theResult____h502870[24] ? + (_theResult____h502871[24] ? 6'd32 : - (_theResult____h502870[23] ? + (_theResult____h502871[23] ? 6'd33 : - (_theResult____h502870[22] ? + (_theResult____h502871[22] ? 6'd34 : - (_theResult____h502870[21] ? + (_theResult____h502871[21] ? 6'd35 : - (_theResult____h502870[20] ? + (_theResult____h502871[20] ? 6'd36 : - (_theResult____h502870[19] ? + (_theResult____h502871[19] ? 6'd37 : - (_theResult____h502870[18] ? + (_theResult____h502871[18] ? 6'd38 : - (_theResult____h502870[17] ? + (_theResult____h502871[17] ? 6'd39 : - (_theResult____h502870[16] ? + (_theResult____h502871[16] ? 6'd40 : - (_theResult____h502870[15] ? + (_theResult____h502871[15] ? 6'd41 : - (_theResult____h502870[14] ? + (_theResult____h502871[14] ? 6'd42 : - (_theResult____h502870[13] ? + (_theResult____h502871[13] ? 6'd43 : - (_theResult____h502870[12] ? + (_theResult____h502871[12] ? 6'd44 : - (_theResult____h502870[11] ? + (_theResult____h502871[11] ? 6'd45 : - (_theResult____h502870[10] ? + (_theResult____h502871[10] ? 6'd46 : - (_theResult____h502870[9] ? + (_theResult____h502871[9] ? 6'd47 : - (_theResult____h502870[8] ? + (_theResult____h502871[8] ? 6'd48 : - (_theResult____h502870[7] ? + (_theResult____h502871[7] ? 6'd49 : - (_theResult____h502870[6] ? + (_theResult____h502871[6] ? 6'd50 : - (_theResult____h502870[5] ? + (_theResult____h502871[5] ? 6'd51 : - (_theResult____h502870[4] ? + (_theResult____h502871[4] ? 6'd52 : - (_theResult____h502870[3] ? + (_theResult____h502871[3] ? 6'd53 : - (_theResult____h502870[2] ? + (_theResult____h502871[2] ? 6'd54 : - (_theResult____h502870[1] ? + (_theResult____h502871[1] ? 6'd55 : - (_theResult____h502870[0] ? + (_theResult____h502871[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 = - (_theResult____h581027[56] ? + (_theResult____h581028[56] ? 6'd0 : - (_theResult____h581027[55] ? + (_theResult____h581028[55] ? 6'd1 : - (_theResult____h581027[54] ? + (_theResult____h581028[54] ? 6'd2 : - (_theResult____h581027[53] ? + (_theResult____h581028[53] ? 6'd3 : - (_theResult____h581027[52] ? + (_theResult____h581028[52] ? 6'd4 : - (_theResult____h581027[51] ? + (_theResult____h581028[51] ? 6'd5 : - (_theResult____h581027[50] ? + (_theResult____h581028[50] ? 6'd6 : - (_theResult____h581027[49] ? + (_theResult____h581028[49] ? 6'd7 : - (_theResult____h581027[48] ? + (_theResult____h581028[48] ? 6'd8 : - (_theResult____h581027[47] ? + (_theResult____h581028[47] ? 6'd9 : - (_theResult____h581027[46] ? + (_theResult____h581028[46] ? 6'd10 : - (_theResult____h581027[45] ? + (_theResult____h581028[45] ? 6'd11 : - (_theResult____h581027[44] ? + (_theResult____h581028[44] ? 6'd12 : - (_theResult____h581027[43] ? + (_theResult____h581028[43] ? 6'd13 : - (_theResult____h581027[42] ? + (_theResult____h581028[42] ? 6'd14 : - (_theResult____h581027[41] ? + (_theResult____h581028[41] ? 6'd15 : - (_theResult____h581027[40] ? + (_theResult____h581028[40] ? 6'd16 : - (_theResult____h581027[39] ? + (_theResult____h581028[39] ? 6'd17 : - (_theResult____h581027[38] ? + (_theResult____h581028[38] ? 6'd18 : - (_theResult____h581027[37] ? + (_theResult____h581028[37] ? 6'd19 : - (_theResult____h581027[36] ? + (_theResult____h581028[36] ? 6'd20 : - (_theResult____h581027[35] ? + (_theResult____h581028[35] ? 6'd21 : - (_theResult____h581027[34] ? + (_theResult____h581028[34] ? 6'd22 : - (_theResult____h581027[33] ? + (_theResult____h581028[33] ? 6'd23 : - (_theResult____h581027[32] ? + (_theResult____h581028[32] ? 6'd24 : - (_theResult____h581027[31] ? + (_theResult____h581028[31] ? 6'd25 : - (_theResult____h581027[30] ? + (_theResult____h581028[30] ? 6'd26 : - (_theResult____h581027[29] ? + (_theResult____h581028[29] ? 6'd27 : - (_theResult____h581027[28] ? + (_theResult____h581028[28] ? 6'd28 : - (_theResult____h581027[27] ? + (_theResult____h581028[27] ? 6'd29 : - (_theResult____h581027[26] ? + (_theResult____h581028[26] ? 6'd30 : - (_theResult____h581027[25] ? + (_theResult____h581028[25] ? 6'd31 : - (_theResult____h581027[24] ? + (_theResult____h581028[24] ? 6'd32 : - (_theResult____h581027[23] ? + (_theResult____h581028[23] ? 6'd33 : - (_theResult____h581027[22] ? + (_theResult____h581028[22] ? 6'd34 : - (_theResult____h581027[21] ? + (_theResult____h581028[21] ? 6'd35 : - (_theResult____h581027[20] ? + (_theResult____h581028[20] ? 6'd36 : - (_theResult____h581027[19] ? + (_theResult____h581028[19] ? 6'd37 : - (_theResult____h581027[18] ? + (_theResult____h581028[18] ? 6'd38 : - (_theResult____h581027[17] ? + (_theResult____h581028[17] ? 6'd39 : - (_theResult____h581027[16] ? + (_theResult____h581028[16] ? 6'd40 : - (_theResult____h581027[15] ? + (_theResult____h581028[15] ? 6'd41 : - (_theResult____h581027[14] ? + (_theResult____h581028[14] ? 6'd42 : - (_theResult____h581027[13] ? + (_theResult____h581028[13] ? 6'd43 : - (_theResult____h581027[12] ? + (_theResult____h581028[12] ? 6'd44 : - (_theResult____h581027[11] ? + (_theResult____h581028[11] ? 6'd45 : - (_theResult____h581027[10] ? + (_theResult____h581028[10] ? 6'd46 : - (_theResult____h581027[9] ? + (_theResult____h581028[9] ? 6'd47 : - (_theResult____h581027[8] ? + (_theResult____h581028[8] ? 6'd48 : - (_theResult____h581027[7] ? + (_theResult____h581028[7] ? 6'd49 : - (_theResult____h581027[6] ? + (_theResult____h581028[6] ? 6'd50 : - (_theResult____h581027[5] ? + (_theResult____h581028[5] ? 6'd51 : - (_theResult____h581027[4] ? + (_theResult____h581028[4] ? 6'd52 : - (_theResult____h581027[3] ? + (_theResult____h581028[3] ? 6'd53 : - (_theResult____h581027[2] ? + (_theResult____h581028[2] ? 6'd54 : - (_theResult____h581027[1] ? + (_theResult____h581028[1] ? 6'd55 : - (_theResult____h581027[0] ? + (_theResult____h581028[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 = - (_theResult____h363725[56] ? + (_theResult____h363726[56] ? 6'd0 : - (_theResult____h363725[55] ? + (_theResult____h363726[55] ? 6'd1 : - (_theResult____h363725[54] ? + (_theResult____h363726[54] ? 6'd2 : - (_theResult____h363725[53] ? + (_theResult____h363726[53] ? 6'd3 : - (_theResult____h363725[52] ? + (_theResult____h363726[52] ? 6'd4 : - (_theResult____h363725[51] ? + (_theResult____h363726[51] ? 6'd5 : - (_theResult____h363725[50] ? + (_theResult____h363726[50] ? 6'd6 : - (_theResult____h363725[49] ? + (_theResult____h363726[49] ? 6'd7 : - (_theResult____h363725[48] ? + (_theResult____h363726[48] ? 6'd8 : - (_theResult____h363725[47] ? + (_theResult____h363726[47] ? 6'd9 : - (_theResult____h363725[46] ? + (_theResult____h363726[46] ? 6'd10 : - (_theResult____h363725[45] ? + (_theResult____h363726[45] ? 6'd11 : - (_theResult____h363725[44] ? + (_theResult____h363726[44] ? 6'd12 : - (_theResult____h363725[43] ? + (_theResult____h363726[43] ? 6'd13 : - (_theResult____h363725[42] ? + (_theResult____h363726[42] ? 6'd14 : - (_theResult____h363725[41] ? + (_theResult____h363726[41] ? 6'd15 : - (_theResult____h363725[40] ? + (_theResult____h363726[40] ? 6'd16 : - (_theResult____h363725[39] ? + (_theResult____h363726[39] ? 6'd17 : - (_theResult____h363725[38] ? + (_theResult____h363726[38] ? 6'd18 : - (_theResult____h363725[37] ? + (_theResult____h363726[37] ? 6'd19 : - (_theResult____h363725[36] ? + (_theResult____h363726[36] ? 6'd20 : - (_theResult____h363725[35] ? + (_theResult____h363726[35] ? 6'd21 : - (_theResult____h363725[34] ? + (_theResult____h363726[34] ? 6'd22 : - (_theResult____h363725[33] ? + (_theResult____h363726[33] ? 6'd23 : - (_theResult____h363725[32] ? + (_theResult____h363726[32] ? 6'd24 : - (_theResult____h363725[31] ? + (_theResult____h363726[31] ? 6'd25 : - (_theResult____h363725[30] ? + (_theResult____h363726[30] ? 6'd26 : - (_theResult____h363725[29] ? + (_theResult____h363726[29] ? 6'd27 : - (_theResult____h363725[28] ? + (_theResult____h363726[28] ? 6'd28 : - (_theResult____h363725[27] ? + (_theResult____h363726[27] ? 6'd29 : - (_theResult____h363725[26] ? + (_theResult____h363726[26] ? 6'd30 : - (_theResult____h363725[25] ? + (_theResult____h363726[25] ? 6'd31 : - (_theResult____h363725[24] ? + (_theResult____h363726[24] ? 6'd32 : - (_theResult____h363725[23] ? + (_theResult____h363726[23] ? 6'd33 : - (_theResult____h363725[22] ? + (_theResult____h363726[22] ? 6'd34 : - (_theResult____h363725[21] ? + (_theResult____h363726[21] ? 6'd35 : - (_theResult____h363725[20] ? + (_theResult____h363726[20] ? 6'd36 : - (_theResult____h363725[19] ? + (_theResult____h363726[19] ? 6'd37 : - (_theResult____h363725[18] ? + (_theResult____h363726[18] ? 6'd38 : - (_theResult____h363725[17] ? + (_theResult____h363726[17] ? 6'd39 : - (_theResult____h363725[16] ? + (_theResult____h363726[16] ? 6'd40 : - (_theResult____h363725[15] ? + (_theResult____h363726[15] ? 6'd41 : - (_theResult____h363725[14] ? + (_theResult____h363726[14] ? 6'd42 : - (_theResult____h363725[13] ? + (_theResult____h363726[13] ? 6'd43 : - (_theResult____h363725[12] ? + (_theResult____h363726[12] ? 6'd44 : - (_theResult____h363725[11] ? + (_theResult____h363726[11] ? 6'd45 : - (_theResult____h363725[10] ? + (_theResult____h363726[10] ? 6'd46 : - (_theResult____h363725[9] ? + (_theResult____h363726[9] ? 6'd47 : - (_theResult____h363725[8] ? + (_theResult____h363726[8] ? 6'd48 : - (_theResult____h363725[7] ? + (_theResult____h363726[7] ? 6'd49 : - (_theResult____h363725[6] ? + (_theResult____h363726[6] ? 6'd50 : - (_theResult____h363725[5] ? + (_theResult____h363726[5] ? 6'd51 : - (_theResult____h363725[4] ? + (_theResult____h363726[4] ? 6'd52 : - (_theResult____h363725[3] ? + (_theResult____h363726[3] ? 6'd53 : - (_theResult____h363725[2] ? + (_theResult____h363726[2] ? 6'd54 : - (_theResult____h363725[1] ? + (_theResult____h363726[1] ? 6'd55 : - (_theResult____h363725[0] ? + (_theResult____h363726[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 = - (_theResult____h409422[56] ? + (_theResult____h409423[56] ? 6'd0 : - (_theResult____h409422[55] ? + (_theResult____h409423[55] ? 6'd1 : - (_theResult____h409422[54] ? + (_theResult____h409423[54] ? 6'd2 : - (_theResult____h409422[53] ? + (_theResult____h409423[53] ? 6'd3 : - (_theResult____h409422[52] ? + (_theResult____h409423[52] ? 6'd4 : - (_theResult____h409422[51] ? + (_theResult____h409423[51] ? 6'd5 : - (_theResult____h409422[50] ? + (_theResult____h409423[50] ? 6'd6 : - (_theResult____h409422[49] ? + (_theResult____h409423[49] ? 6'd7 : - (_theResult____h409422[48] ? + (_theResult____h409423[48] ? 6'd8 : - (_theResult____h409422[47] ? + (_theResult____h409423[47] ? 6'd9 : - (_theResult____h409422[46] ? + (_theResult____h409423[46] ? 6'd10 : - (_theResult____h409422[45] ? + (_theResult____h409423[45] ? 6'd11 : - (_theResult____h409422[44] ? + (_theResult____h409423[44] ? 6'd12 : - (_theResult____h409422[43] ? + (_theResult____h409423[43] ? 6'd13 : - (_theResult____h409422[42] ? + (_theResult____h409423[42] ? 6'd14 : - (_theResult____h409422[41] ? + (_theResult____h409423[41] ? 6'd15 : - (_theResult____h409422[40] ? + (_theResult____h409423[40] ? 6'd16 : - (_theResult____h409422[39] ? + (_theResult____h409423[39] ? 6'd17 : - (_theResult____h409422[38] ? + (_theResult____h409423[38] ? 6'd18 : - (_theResult____h409422[37] ? + (_theResult____h409423[37] ? 6'd19 : - (_theResult____h409422[36] ? + (_theResult____h409423[36] ? 6'd20 : - (_theResult____h409422[35] ? + (_theResult____h409423[35] ? 6'd21 : - (_theResult____h409422[34] ? + (_theResult____h409423[34] ? 6'd22 : - (_theResult____h409422[33] ? + (_theResult____h409423[33] ? 6'd23 : - (_theResult____h409422[32] ? + (_theResult____h409423[32] ? 6'd24 : - (_theResult____h409422[31] ? + (_theResult____h409423[31] ? 6'd25 : - (_theResult____h409422[30] ? + (_theResult____h409423[30] ? 6'd26 : - (_theResult____h409422[29] ? + (_theResult____h409423[29] ? 6'd27 : - (_theResult____h409422[28] ? + (_theResult____h409423[28] ? 6'd28 : - (_theResult____h409422[27] ? + (_theResult____h409423[27] ? 6'd29 : - (_theResult____h409422[26] ? + (_theResult____h409423[26] ? 6'd30 : - (_theResult____h409422[25] ? + (_theResult____h409423[25] ? 6'd31 : - (_theResult____h409422[24] ? + (_theResult____h409423[24] ? 6'd32 : - (_theResult____h409422[23] ? + (_theResult____h409423[23] ? 6'd33 : - (_theResult____h409422[22] ? + (_theResult____h409423[22] ? 6'd34 : - (_theResult____h409422[21] ? + (_theResult____h409423[21] ? 6'd35 : - (_theResult____h409422[20] ? + (_theResult____h409423[20] ? 6'd36 : - (_theResult____h409422[19] ? + (_theResult____h409423[19] ? 6'd37 : - (_theResult____h409422[18] ? + (_theResult____h409423[18] ? 6'd38 : - (_theResult____h409422[17] ? + (_theResult____h409423[17] ? 6'd39 : - (_theResult____h409422[16] ? + (_theResult____h409423[16] ? 6'd40 : - (_theResult____h409422[15] ? + (_theResult____h409423[15] ? 6'd41 : - (_theResult____h409422[14] ? + (_theResult____h409423[14] ? 6'd42 : - (_theResult____h409422[13] ? + (_theResult____h409423[13] ? 6'd43 : - (_theResult____h409422[12] ? + (_theResult____h409423[12] ? 6'd44 : - (_theResult____h409422[11] ? + (_theResult____h409423[11] ? 6'd45 : - (_theResult____h409422[10] ? + (_theResult____h409423[10] ? 6'd46 : - (_theResult____h409422[9] ? + (_theResult____h409423[9] ? 6'd47 : - (_theResult____h409422[8] ? + (_theResult____h409423[8] ? 6'd48 : - (_theResult____h409422[7] ? + (_theResult____h409423[7] ? 6'd49 : - (_theResult____h409422[6] ? + (_theResult____h409423[6] ? 6'd50 : - (_theResult____h409422[5] ? + (_theResult____h409423[5] ? 6'd51 : - (_theResult____h409422[4] ? + (_theResult____h409423[4] ? 6'd52 : - (_theResult____h409422[3] ? + (_theResult____h409423[3] ? 6'd53 : - (_theResult____h409422[2] ? + (_theResult____h409423[2] ? 6'd54 : - (_theResult____h409422[1] ? + (_theResult____h409423[1] ? 6'd55 : - (_theResult____h409422[0] ? + (_theResult____h409423[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 = - (_theResult____h455117[56] ? + (_theResult____h455118[56] ? 6'd0 : - (_theResult____h455117[55] ? + (_theResult____h455118[55] ? 6'd1 : - (_theResult____h455117[54] ? + (_theResult____h455118[54] ? 6'd2 : - (_theResult____h455117[53] ? + (_theResult____h455118[53] ? 6'd3 : - (_theResult____h455117[52] ? + (_theResult____h455118[52] ? 6'd4 : - (_theResult____h455117[51] ? + (_theResult____h455118[51] ? 6'd5 : - (_theResult____h455117[50] ? + (_theResult____h455118[50] ? 6'd6 : - (_theResult____h455117[49] ? + (_theResult____h455118[49] ? 6'd7 : - (_theResult____h455117[48] ? + (_theResult____h455118[48] ? 6'd8 : - (_theResult____h455117[47] ? + (_theResult____h455118[47] ? 6'd9 : - (_theResult____h455117[46] ? + (_theResult____h455118[46] ? 6'd10 : - (_theResult____h455117[45] ? + (_theResult____h455118[45] ? 6'd11 : - (_theResult____h455117[44] ? + (_theResult____h455118[44] ? 6'd12 : - (_theResult____h455117[43] ? + (_theResult____h455118[43] ? 6'd13 : - (_theResult____h455117[42] ? + (_theResult____h455118[42] ? 6'd14 : - (_theResult____h455117[41] ? + (_theResult____h455118[41] ? 6'd15 : - (_theResult____h455117[40] ? + (_theResult____h455118[40] ? 6'd16 : - (_theResult____h455117[39] ? + (_theResult____h455118[39] ? 6'd17 : - (_theResult____h455117[38] ? + (_theResult____h455118[38] ? 6'd18 : - (_theResult____h455117[37] ? + (_theResult____h455118[37] ? 6'd19 : - (_theResult____h455117[36] ? + (_theResult____h455118[36] ? 6'd20 : - (_theResult____h455117[35] ? + (_theResult____h455118[35] ? 6'd21 : - (_theResult____h455117[34] ? + (_theResult____h455118[34] ? 6'd22 : - (_theResult____h455117[33] ? + (_theResult____h455118[33] ? 6'd23 : - (_theResult____h455117[32] ? + (_theResult____h455118[32] ? 6'd24 : - (_theResult____h455117[31] ? + (_theResult____h455118[31] ? 6'd25 : - (_theResult____h455117[30] ? + (_theResult____h455118[30] ? 6'd26 : - (_theResult____h455117[29] ? + (_theResult____h455118[29] ? 6'd27 : - (_theResult____h455117[28] ? + (_theResult____h455118[28] ? 6'd28 : - (_theResult____h455117[27] ? + (_theResult____h455118[27] ? 6'd29 : - (_theResult____h455117[26] ? + (_theResult____h455118[26] ? 6'd30 : - (_theResult____h455117[25] ? + (_theResult____h455118[25] ? 6'd31 : - (_theResult____h455117[24] ? + (_theResult____h455118[24] ? 6'd32 : - (_theResult____h455117[23] ? + (_theResult____h455118[23] ? 6'd33 : - (_theResult____h455117[22] ? + (_theResult____h455118[22] ? 6'd34 : - (_theResult____h455117[21] ? + (_theResult____h455118[21] ? 6'd35 : - (_theResult____h455117[20] ? + (_theResult____h455118[20] ? 6'd36 : - (_theResult____h455117[19] ? + (_theResult____h455118[19] ? 6'd37 : - (_theResult____h455117[18] ? + (_theResult____h455118[18] ? 6'd38 : - (_theResult____h455117[17] ? + (_theResult____h455118[17] ? 6'd39 : - (_theResult____h455117[16] ? + (_theResult____h455118[16] ? 6'd40 : - (_theResult____h455117[15] ? + (_theResult____h455118[15] ? 6'd41 : - (_theResult____h455117[14] ? + (_theResult____h455118[14] ? 6'd42 : - (_theResult____h455117[13] ? + (_theResult____h455118[13] ? 6'd43 : - (_theResult____h455117[12] ? + (_theResult____h455118[12] ? 6'd44 : - (_theResult____h455117[11] ? + (_theResult____h455118[11] ? 6'd45 : - (_theResult____h455117[10] ? + (_theResult____h455118[10] ? 6'd46 : - (_theResult____h455117[9] ? + (_theResult____h455118[9] ? 6'd47 : - (_theResult____h455117[8] ? + (_theResult____h455118[8] ? 6'd48 : - (_theResult____h455117[7] ? + (_theResult____h455118[7] ? 6'd49 : - (_theResult____h455117[6] ? + (_theResult____h455118[6] ? 6'd50 : - (_theResult____h455117[5] ? + (_theResult____h455118[5] ? 6'd51 : - (_theResult____h455117[4] ? + (_theResult____h455118[4] ? 6'd52 : - (_theResult____h455117[3] ? + (_theResult____h455118[3] ? 6'd53 : - (_theResult____h455117[2] ? + (_theResult____h455118[2] ? 6'd54 : - (_theResult____h455117[1] ? + (_theResult____h455118[1] ? 6'd55 : - (_theResult____h455117[0] ? + (_theResult____h455118[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 = - (_theResult___fst_exp__h549959 == 11'd2047) ? + (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20908,10 +20908,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = - (_theResult___fst_exp__h549959 == 11'd2047) ? + (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20919,10 +20919,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 = - (_theResult___fst_exp__h511106 == 11'd2047) ? + (_theResult___fst_exp__h511107 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20930,10 +20930,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 = - (_theResult___fst_exp__h589263 == 11'd2047) ? + (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20941,10 +20941,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = - (_theResult___fst_exp__h589263 == 11'd2047) ? + (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20952,538 +20952,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 = - (guard__h346096 == 2'b0 || + (guard__h346097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h354197 : - _theResult___exp__h354713 ; + _theResult___fst_exp__h354198 : + _theResult___exp__h354714 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 = - (guard__h346096 == 2'b0) ? - _theResult___fst_exp__h354197 : + (guard__h346097 == 2'b0) ? + _theResult___fst_exp__h354198 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h354713 : - _theResult___fst_exp__h354197) ; + _theResult___exp__h354714 : + _theResult___fst_exp__h354198) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 = - (guard__h346096 == 2'b0 || + (guard__h346097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h354191[56:34] : - _theResult___sfd__h354714 ; + sfdin__h354192[56:34] : + _theResult___sfd__h354715 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 = - (guard__h346096 == 2'b0) ? - sfdin__h354191[56:34] : + (guard__h346097 == 2'b0) ? + sfdin__h354192[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h354714 : - sfdin__h354191[56:34]) ; + _theResult___sfd__h354715 : + sfdin__h354192[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 = - (guard__h391795 == 2'b0 || + (guard__h391796 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h399894 : - _theResult___exp__h400410 ; + _theResult___fst_exp__h399895 : + _theResult___exp__h400411 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 = - (guard__h391795 == 2'b0) ? - _theResult___fst_exp__h399894 : + (guard__h391796 == 2'b0) ? + _theResult___fst_exp__h399895 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h400410 : - _theResult___fst_exp__h399894) ; + _theResult___exp__h400411 : + _theResult___fst_exp__h399895) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 = - (guard__h391795 == 2'b0 || + (guard__h391796 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h399888[56:34] : - _theResult___sfd__h400411 ; + sfdin__h399889[56:34] : + _theResult___sfd__h400412 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 = - (guard__h391795 == 2'b0) ? - sfdin__h399888[56:34] : + (guard__h391796 == 2'b0) ? + sfdin__h399889[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h400411 : - sfdin__h399888[56:34]) ; + _theResult___sfd__h400412 : + sfdin__h399889[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 = - (guard__h437490 == 2'b0 || + (guard__h437491 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h445589 : - _theResult___exp__h446105 ; + _theResult___fst_exp__h445590 : + _theResult___exp__h446106 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 = - (guard__h437490 == 2'b0) ? - _theResult___fst_exp__h445589 : + (guard__h437491 == 2'b0) ? + _theResult___fst_exp__h445590 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h446105 : - _theResult___fst_exp__h445589) ; + _theResult___exp__h446106 : + _theResult___fst_exp__h445590) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 = - (guard__h437490 == 2'b0 || + (guard__h437491 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h445583[56:34] : - _theResult___sfd__h446106 ; + sfdin__h445584[56:34] : + _theResult___sfd__h446107 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 = - (guard__h437490 == 2'b0) ? - sfdin__h445583[56:34] : + (guard__h437491 == 2'b0) ? + sfdin__h445584[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h446106 : - sfdin__h445583[56:34]) ; + _theResult___sfd__h446107 : + sfdin__h445584[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 = - (guard__h541733 == 2'b0 || + (guard__h541734 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h549959 : - _theResult___exp__h550688 ; + _theResult___fst_exp__h549960 : + _theResult___exp__h550689 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 = - (guard__h541733 == 2'b0) ? - _theResult___fst_exp__h549959 : + (guard__h541734 == 2'b0) ? + _theResult___fst_exp__h549960 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h550688 : - _theResult___fst_exp__h549959) ; + _theResult___exp__h550689 : + _theResult___fst_exp__h549960) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 = - (guard__h541733 == 2'b0 || + (guard__h541734 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h549953[56:5] : - _theResult___sfd__h550689 ; + sfdin__h549954[56:5] : + _theResult___sfd__h550690 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 = - (guard__h541733 == 2'b0) ? - sfdin__h549953[56:5] : + (guard__h541734 == 2'b0) ? + sfdin__h549954[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h550689 : - sfdin__h549953[56:5]) ; + _theResult___sfd__h550690 : + sfdin__h549954[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 = - (guard__h502880 == 2'b0 || + (guard__h502881 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h511106 : - _theResult___exp__h511835 ; + _theResult___fst_exp__h511107 : + _theResult___exp__h511836 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 = - (guard__h502880 == 2'b0) ? - _theResult___fst_exp__h511106 : + (guard__h502881 == 2'b0) ? + _theResult___fst_exp__h511107 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h511835 : - _theResult___fst_exp__h511106) ; + _theResult___exp__h511836 : + _theResult___fst_exp__h511107) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 = - (guard__h502880 == 2'b0 || + (guard__h502881 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h511100[56:5] : - _theResult___sfd__h511836 ; + sfdin__h511101[56:5] : + _theResult___sfd__h511837 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 = - (guard__h502880 == 2'b0) ? - sfdin__h511100[56:5] : + (guard__h502881 == 2'b0) ? + sfdin__h511101[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h511836 : - sfdin__h511100[56:5]) ; + _theResult___sfd__h511837 : + sfdin__h511101[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 = - (guard__h581037 == 2'b0 || + (guard__h581038 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h589263 : - _theResult___exp__h589992 ; + _theResult___fst_exp__h589264 : + _theResult___exp__h589993 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 = - (guard__h581037 == 2'b0) ? - _theResult___fst_exp__h589263 : + (guard__h581038 == 2'b0) ? + _theResult___fst_exp__h589264 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h589992 : - _theResult___fst_exp__h589263) ; + _theResult___exp__h589993 : + _theResult___fst_exp__h589264) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 = - (guard__h581037 == 2'b0 || + (guard__h581038 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h589257[56:5] : - _theResult___sfd__h589993 ; + sfdin__h589258[56:5] : + _theResult___sfd__h589994 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 = - (guard__h581037 == 2'b0) ? - sfdin__h589257[56:5] : + (guard__h581038 == 2'b0) ? + sfdin__h589258[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h589993 : - sfdin__h589257[56:5]) ; + _theResult___sfd__h589994 : + sfdin__h589258[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 = - (guard__h363735 == 2'b0 || + (guard__h363736 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h371963 : - _theResult___exp__h372479 ; + _theResult___fst_exp__h371964 : + _theResult___exp__h372480 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 = - (guard__h363735 == 2'b0) ? - _theResult___fst_exp__h371963 : + (guard__h363736 == 2'b0) ? + _theResult___fst_exp__h371964 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h372479 : - _theResult___fst_exp__h371963) ; + _theResult___exp__h372480 : + _theResult___fst_exp__h371964) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 = - (guard__h363735 == 2'b0 || + (guard__h363736 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h371957[56:34] : - _theResult___sfd__h372480 ; + sfdin__h371958[56:34] : + _theResult___sfd__h372481 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 = - (guard__h363735 == 2'b0) ? - sfdin__h371957[56:34] : + (guard__h363736 == 2'b0) ? + sfdin__h371958[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h372480 : - sfdin__h371957[56:34]) ; + _theResult___sfd__h372481 : + sfdin__h371958[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 = - (guard__h409432 == 2'b0 || + (guard__h409433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h417660 : - _theResult___exp__h418176 ; + _theResult___fst_exp__h417661 : + _theResult___exp__h418177 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 = - (guard__h409432 == 2'b0) ? - _theResult___fst_exp__h417660 : + (guard__h409433 == 2'b0) ? + _theResult___fst_exp__h417661 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h418176 : - _theResult___fst_exp__h417660) ; + _theResult___exp__h418177 : + _theResult___fst_exp__h417661) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 = - (guard__h409432 == 2'b0 || + (guard__h409433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h417654[56:34] : - _theResult___sfd__h418177 ; + sfdin__h417655[56:34] : + _theResult___sfd__h418178 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 = - (guard__h409432 == 2'b0) ? - sfdin__h417654[56:34] : + (guard__h409433 == 2'b0) ? + sfdin__h417655[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h418177 : - sfdin__h417654[56:34]) ; + _theResult___sfd__h418178 : + sfdin__h417655[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 = - (guard__h455127 == 2'b0 || + (guard__h455128 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h463355 : - _theResult___exp__h463871 ; + _theResult___fst_exp__h463356 : + _theResult___exp__h463872 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 = - (guard__h455127 == 2'b0) ? - _theResult___fst_exp__h463355 : + (guard__h455128 == 2'b0) ? + _theResult___fst_exp__h463356 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h463871 : - _theResult___fst_exp__h463355) ; + _theResult___exp__h463872 : + _theResult___fst_exp__h463356) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 = - (guard__h455127 == 2'b0 || + (guard__h455128 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h463349[56:34] : - _theResult___sfd__h463872 ; + sfdin__h463350[56:34] : + _theResult___sfd__h463873 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 = - (guard__h455127 == 2'b0) ? - sfdin__h463349[56:34] : + (guard__h455128 == 2'b0) ? + sfdin__h463350[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h463872 : - sfdin__h463349[56:34]) ; + _theResult___sfd__h463873 : + sfdin__h463350[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 = - (guard__h532421 == 2'b0 || + (guard__h532422 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h540382 : - _theResult___exp__h541037 ; + _theResult___fst_exp__h540383 : + _theResult___exp__h541038 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 = - (guard__h532421 == 2'b0) ? - _theResult___fst_exp__h540382 : + (guard__h532422 == 2'b0) ? + _theResult___fst_exp__h540383 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h541037 : - _theResult___fst_exp__h540382) ; + _theResult___exp__h541038 : + _theResult___fst_exp__h540383) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 = - (guard__h550802 == 2'b0 || + (guard__h550803 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h558792 : - _theResult___exp__h559472 ; + _theResult___fst_exp__h558793 : + _theResult___exp__h559473 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 = - (guard__h550802 == 2'b0) ? - _theResult___fst_exp__h558792 : + (guard__h550803 == 2'b0) ? + _theResult___fst_exp__h558793 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h559472 : - _theResult___fst_exp__h558792) ; + _theResult___exp__h559473 : + _theResult___fst_exp__h558793) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 = - (guard__h532421 == 2'b0 || + (guard__h532422 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h540333[56:5] : - _theResult___sfd__h541038 ; + _theResult___snd__h540334[56:5] : + _theResult___sfd__h541039 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 = - (guard__h532421 == 2'b0) ? - _theResult___snd__h540333[56:5] : + (guard__h532422 == 2'b0) ? + _theResult___snd__h540334[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h541038 : - _theResult___snd__h540333[56:5]) ; + _theResult___sfd__h541039 : + _theResult___snd__h540334[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 = - (guard__h550802 == 2'b0 || + (guard__h550803 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h558738[56:5] : - _theResult___sfd__h559473 ; + _theResult___snd__h558739[56:5] : + _theResult___sfd__h559474 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 = - (guard__h550802 == 2'b0) ? - _theResult___snd__h558738[56:5] : + (guard__h550803 == 2'b0) ? + _theResult___snd__h558739[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h559473 : - _theResult___snd__h558738[56:5]) ; + _theResult___sfd__h559474 : + _theResult___snd__h558739[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 = - (guard__h493568 == 2'b0 || + (guard__h493569 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h501529 : - _theResult___exp__h502184 ; + _theResult___fst_exp__h501530 : + _theResult___exp__h502185 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 = - (guard__h493568 == 2'b0) ? - _theResult___fst_exp__h501529 : + (guard__h493569 == 2'b0) ? + _theResult___fst_exp__h501530 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h502184 : - _theResult___fst_exp__h501529) ; + _theResult___exp__h502185 : + _theResult___fst_exp__h501530) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 = - (guard__h511949 == 2'b0 || + (guard__h511950 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h519939 : - _theResult___exp__h520619 ; + _theResult___fst_exp__h519940 : + _theResult___exp__h520620 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 = - (guard__h511949 == 2'b0) ? - _theResult___fst_exp__h519939 : + (guard__h511950 == 2'b0) ? + _theResult___fst_exp__h519940 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h520619 : - _theResult___fst_exp__h519939) ; + _theResult___exp__h520620 : + _theResult___fst_exp__h519940) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 = - (guard__h493568 == 2'b0 || + (guard__h493569 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h501480[56:5] : - _theResult___sfd__h502185 ; + _theResult___snd__h501481[56:5] : + _theResult___sfd__h502186 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 = - (guard__h493568 == 2'b0) ? - _theResult___snd__h501480[56:5] : + (guard__h493569 == 2'b0) ? + _theResult___snd__h501481[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h502185 : - _theResult___snd__h501480[56:5]) ; + _theResult___sfd__h502186 : + _theResult___snd__h501481[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 = - (guard__h511949 == 2'b0 || + (guard__h511950 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h519885[56:5] : - _theResult___sfd__h520620 ; + _theResult___snd__h519886[56:5] : + _theResult___sfd__h520621 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 = - (guard__h511949 == 2'b0) ? - _theResult___snd__h519885[56:5] : + (guard__h511950 == 2'b0) ? + _theResult___snd__h519886[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h520620 : - _theResult___snd__h519885[56:5]) ; + _theResult___sfd__h520621 : + _theResult___snd__h519886[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 = - (guard__h571725 == 2'b0 || + (guard__h571726 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h579686 : - _theResult___exp__h580341 ; + _theResult___fst_exp__h579687 : + _theResult___exp__h580342 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 = - (guard__h571725 == 2'b0) ? - _theResult___fst_exp__h579686 : + (guard__h571726 == 2'b0) ? + _theResult___fst_exp__h579687 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h580341 : - _theResult___fst_exp__h579686) ; + _theResult___exp__h580342 : + _theResult___fst_exp__h579687) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 = - (guard__h590106 == 2'b0 || + (guard__h590107 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h598096 : - _theResult___exp__h598776 ; + _theResult___fst_exp__h598097 : + _theResult___exp__h598777 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 = - (guard__h590106 == 2'b0) ? - _theResult___fst_exp__h598096 : + (guard__h590107 == 2'b0) ? + _theResult___fst_exp__h598097 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h598776 : - _theResult___fst_exp__h598096) ; + _theResult___exp__h598777 : + _theResult___fst_exp__h598097) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 = - (guard__h571725 == 2'b0 || + (guard__h571726 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h579637[56:5] : - _theResult___sfd__h580342 ; + _theResult___snd__h579638[56:5] : + _theResult___sfd__h580343 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 = - (guard__h571725 == 2'b0) ? - _theResult___snd__h579637[56:5] : + (guard__h571726 == 2'b0) ? + _theResult___snd__h579638[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h580342 : - _theResult___snd__h579637[56:5]) ; + _theResult___sfd__h580343 : + _theResult___snd__h579638[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 = - (guard__h590106 == 2'b0 || + (guard__h590107 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h598042[56:5] : - _theResult___sfd__h598777 ; + _theResult___snd__h598043[56:5] : + _theResult___sfd__h598778 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 = - (guard__h590106 == 2'b0) ? - _theResult___snd__h598042[56:5] : + (guard__h590107 == 2'b0) ? + _theResult___snd__h598043[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h598777 : - _theResult___snd__h598042[56:5]) ; + _theResult___sfd__h598778 : + _theResult___snd__h598043[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 = - (guard__h354805 == 2'b0 || + (guard__h354806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h362853 : - _theResult___exp__h363295 ; + _theResult___fst_exp__h362854 : + _theResult___exp__h363296 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 = - (guard__h354805 == 2'b0) ? - _theResult___fst_exp__h362853 : + (guard__h354806 == 2'b0) ? + _theResult___fst_exp__h362854 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h363295 : - _theResult___fst_exp__h362853) ; + _theResult___exp__h363296 : + _theResult___fst_exp__h362854) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 = - (guard__h372571 == 2'b0 || + (guard__h372572 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h380648 : - _theResult___exp__h381115 ; + _theResult___fst_exp__h380649 : + _theResult___exp__h381116 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 = - (guard__h372571 == 2'b0) ? - _theResult___fst_exp__h380648 : + (guard__h372572 == 2'b0) ? + _theResult___fst_exp__h380649 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h381115 : - _theResult___fst_exp__h380648) ; + _theResult___exp__h381116 : + _theResult___fst_exp__h380649) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 = - (guard__h354805 == 2'b0 || + (guard__h354806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h362804[56:34] : - _theResult___sfd__h363296 ; + _theResult___snd__h362805[56:34] : + _theResult___sfd__h363297 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 = - (guard__h354805 == 2'b0) ? - _theResult___snd__h362804[56:34] : + (guard__h354806 == 2'b0) ? + _theResult___snd__h362805[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h363296 : - _theResult___snd__h362804[56:34]) ; + _theResult___sfd__h363297 : + _theResult___snd__h362805[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h372571 == 2'b0 || + (guard__h372572 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h380594[56:34] : - _theResult___sfd__h381116 ; + _theResult___snd__h380595[56:34] : + _theResult___sfd__h381117 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h372571 == 2'b0) ? - _theResult___snd__h380594[56:34] : + (guard__h372572 == 2'b0) ? + _theResult___snd__h380595[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h381116 : - _theResult___snd__h380594[56:34]) ; + _theResult___sfd__h381117 : + _theResult___snd__h380595[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 = - (guard__h400502 == 2'b0 || + (guard__h400503 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h408550 : - _theResult___exp__h408992 ; + _theResult___fst_exp__h408551 : + _theResult___exp__h408993 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 = - (guard__h400502 == 2'b0) ? - _theResult___fst_exp__h408550 : + (guard__h400503 == 2'b0) ? + _theResult___fst_exp__h408551 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h408992 : - _theResult___fst_exp__h408550) ; + _theResult___exp__h408993 : + _theResult___fst_exp__h408551) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 = - (guard__h418268 == 2'b0 || + (guard__h418269 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h426345 : - _theResult___exp__h426812 ; + _theResult___fst_exp__h426346 : + _theResult___exp__h426813 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 = - (guard__h418268 == 2'b0) ? - _theResult___fst_exp__h426345 : + (guard__h418269 == 2'b0) ? + _theResult___fst_exp__h426346 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h426812 : - _theResult___fst_exp__h426345) ; + _theResult___exp__h426813 : + _theResult___fst_exp__h426346) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 = - (guard__h400502 == 2'b0 || + (guard__h400503 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h408501[56:34] : - _theResult___sfd__h408993 ; + _theResult___snd__h408502[56:34] : + _theResult___sfd__h408994 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 = - (guard__h400502 == 2'b0) ? - _theResult___snd__h408501[56:34] : + (guard__h400503 == 2'b0) ? + _theResult___snd__h408502[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h408993 : - _theResult___snd__h408501[56:34]) ; + _theResult___sfd__h408994 : + _theResult___snd__h408502[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h418268 == 2'b0 || + (guard__h418269 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h426291[56:34] : - _theResult___sfd__h426813 ; + _theResult___snd__h426292[56:34] : + _theResult___sfd__h426814 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h418268 == 2'b0) ? - _theResult___snd__h426291[56:34] : + (guard__h418269 == 2'b0) ? + _theResult___snd__h426292[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h426813 : - _theResult___snd__h426291[56:34]) ; + _theResult___sfd__h426814 : + _theResult___snd__h426292[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 = - (guard__h446197 == 2'b0 || + (guard__h446198 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h454245 : - _theResult___exp__h454687 ; + _theResult___fst_exp__h454246 : + _theResult___exp__h454688 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 = - (guard__h446197 == 2'b0) ? - _theResult___fst_exp__h454245 : + (guard__h446198 == 2'b0) ? + _theResult___fst_exp__h454246 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h454687 : - _theResult___fst_exp__h454245) ; + _theResult___exp__h454688 : + _theResult___fst_exp__h454246) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 = - (guard__h463963 == 2'b0 || + (guard__h463964 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h472040 : - _theResult___exp__h472507 ; + _theResult___fst_exp__h472041 : + _theResult___exp__h472508 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 = - (guard__h463963 == 2'b0) ? - _theResult___fst_exp__h472040 : + (guard__h463964 == 2'b0) ? + _theResult___fst_exp__h472041 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h472507 : - _theResult___fst_exp__h472040) ; + _theResult___exp__h472508 : + _theResult___fst_exp__h472041) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 = - (guard__h446197 == 2'b0 || + (guard__h446198 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h454196[56:34] : - _theResult___sfd__h454688 ; + _theResult___snd__h454197[56:34] : + _theResult___sfd__h454689 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 = - (guard__h446197 == 2'b0) ? - _theResult___snd__h454196[56:34] : + (guard__h446198 == 2'b0) ? + _theResult___snd__h454197[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h454688 : - _theResult___snd__h454196[56:34]) ; + _theResult___sfd__h454689 : + _theResult___snd__h454197[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h463963 == 2'b0 || + (guard__h463964 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h471986[56:34] : - _theResult___sfd__h472508 ; + _theResult___snd__h471987[56:34] : + _theResult___sfd__h472509 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h463963 == 2'b0) ? - _theResult___snd__h471986[56:34] : + (guard__h463964 == 2'b0) ? + _theResult___snd__h471987[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h472508 : - _theResult___snd__h471986[56:34]) ; + _theResult___sfd__h472509 : + _theResult___snd__h471987[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470 = - (_theResult___fst_exp__h558792 == 11'd2047) ? + (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21491,10 +21491,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676 = - (_theResult___fst_exp__h540382 == 11'd2047) ? + (_theResult___fst_exp__h540383 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21502,10 +21502,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = - (_theResult___fst_exp__h558792 == 11'd2047) ? + (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21513,10 +21513,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = - (_theResult___fst_exp__h519939 == 11'd2047) ? + (_theResult___fst_exp__h519940 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21524,10 +21524,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 = - (_theResult___fst_exp__h598096 == 11'd2047) ? + (_theResult___fst_exp__h598097 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21535,10 +21535,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907 = - (_theResult___fst_exp__h579686 == 11'd2047) ? + (_theResult___fst_exp__h579687 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21546,10 +21546,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 = - (_theResult___fst_exp__h598096 == 11'd2047) ? + (_theResult___fst_exp__h598097 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21557,14 +21557,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 = - (_theResult____h651118 == 16'd0 && + (_theResult____h651119 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h651689 : - _theResult____h651118 ; + enabled_ints__h651690 : + _theResult____h651119 ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || @@ -21626,77 +21626,77 @@ module mkCore(CLK, checkForException___d13698[4] || csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 = - ((f2_exp__h521135 == 8'd0) ? - (f2_sfd__h521136[22] ? + ((f2_exp__h521136 == 8'd0) ? + (f2_sfd__h521137[22] ? 6'd2 : - (f2_sfd__h521136[21] ? + (f2_sfd__h521137[21] ? 6'd3 : - (f2_sfd__h521136[20] ? + (f2_sfd__h521137[20] ? 6'd4 : - (f2_sfd__h521136[19] ? + (f2_sfd__h521137[19] ? 6'd5 : - (f2_sfd__h521136[18] ? + (f2_sfd__h521137[18] ? 6'd6 : - (f2_sfd__h521136[17] ? + (f2_sfd__h521137[17] ? 6'd7 : - (f2_sfd__h521136[16] ? + (f2_sfd__h521137[16] ? 6'd8 : - (f2_sfd__h521136[15] ? + (f2_sfd__h521137[15] ? 6'd9 : - (f2_sfd__h521136[14] ? + (f2_sfd__h521137[14] ? 6'd10 : - (f2_sfd__h521136[13] ? + (f2_sfd__h521137[13] ? 6'd11 : - (f2_sfd__h521136[12] ? + (f2_sfd__h521137[12] ? 6'd12 : - (f2_sfd__h521136[11] ? + (f2_sfd__h521137[11] ? 6'd13 : - (f2_sfd__h521136[10] ? + (f2_sfd__h521137[10] ? 6'd14 : - (f2_sfd__h521136[9] ? + (f2_sfd__h521137[9] ? 6'd15 : - (f2_sfd__h521136[8] ? + (f2_sfd__h521137[8] ? 6'd16 : - (f2_sfd__h521136[7] ? + (f2_sfd__h521137[7] ? 6'd17 : - (f2_sfd__h521136[6] ? + (f2_sfd__h521137[6] ? 6'd18 : - (f2_sfd__h521136[5] ? + (f2_sfd__h521137[5] ? 6'd19 : - (f2_sfd__h521136[4] ? + (f2_sfd__h521137[4] ? 6'd20 : - (f2_sfd__h521136[3] ? + (f2_sfd__h521137[3] ? 6'd21 : - (f2_sfd__h521136[2] ? + (f2_sfd__h521137[2] ? 6'd22 : - (f2_sfd__h521136[1] ? + (f2_sfd__h521137[1] ? 6'd23 : - (f2_sfd__h521136[0] ? + (f2_sfd__h521137[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474 = - (f2_exp__h521135 == 8'd255 && f2_sfd__h521136 != 23'd0 || - (f2_exp__h521135 == 8'd255 || f2_exp__h521135 == 8'd0) && - f2_sfd__h521136 == 23'd0) ? + (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0 || + (f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) && + f2_sfd__h521137 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h521135 == 8'd0) ? + ((f2_exp__h521136 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 = - (f2_exp__h521135 == 8'd255 && f2_sfd__h521136 != 23'd0) ? - _theResult___snd_fst_sfd__h521451 : - _theResult___fst_sfd__h559591 ; + (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0) ? + _theResult___snd_fst_sfd__h521452 : + _theResult___fst_sfd__h559592 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 = - { (f2_exp__h521135 == 8'd255) ? + { (f2_exp__h521136 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h559587, + _theResult___fst_exp__h559588, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21706,15 +21706,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 = - (f2_exp__h521135 == 8'd255 && f2_sfd__h521136 != 23'd0 || - (f2_exp__h521135 == 8'd255 || f2_exp__h521135 == 8'd0) && - f2_sfd__h521136 == 23'd0) ? + (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0 || + (f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) && + f2_sfd__h521137 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[4] : @@ -21722,7 +21722,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[4] : @@ -21730,7 +21730,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[4] : @@ -21738,7 +21738,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[3] : @@ -21746,7 +21746,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[3] : @@ -21754,7 +21754,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[3] : @@ -21762,211 +21762,211 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 = - ((f1_exp__h482141 == 8'd0) ? - (f1_sfd__h482142[22] ? + ((f1_exp__h482142 == 8'd0) ? + (f1_sfd__h482143[22] ? 6'd2 : - (f1_sfd__h482142[21] ? + (f1_sfd__h482143[21] ? 6'd3 : - (f1_sfd__h482142[20] ? + (f1_sfd__h482143[20] ? 6'd4 : - (f1_sfd__h482142[19] ? + (f1_sfd__h482143[19] ? 6'd5 : - (f1_sfd__h482142[18] ? + (f1_sfd__h482143[18] ? 6'd6 : - (f1_sfd__h482142[17] ? + (f1_sfd__h482143[17] ? 6'd7 : - (f1_sfd__h482142[16] ? + (f1_sfd__h482143[16] ? 6'd8 : - (f1_sfd__h482142[15] ? + (f1_sfd__h482143[15] ? 6'd9 : - (f1_sfd__h482142[14] ? + (f1_sfd__h482143[14] ? 6'd10 : - (f1_sfd__h482142[13] ? + (f1_sfd__h482143[13] ? 6'd11 : - (f1_sfd__h482142[12] ? + (f1_sfd__h482143[12] ? 6'd12 : - (f1_sfd__h482142[11] ? + (f1_sfd__h482143[11] ? 6'd13 : - (f1_sfd__h482142[10] ? + (f1_sfd__h482143[10] ? 6'd14 : - (f1_sfd__h482142[9] ? + (f1_sfd__h482143[9] ? 6'd15 : - (f1_sfd__h482142[8] ? + (f1_sfd__h482143[8] ? 6'd16 : - (f1_sfd__h482142[7] ? + (f1_sfd__h482143[7] ? 6'd17 : - (f1_sfd__h482142[6] ? + (f1_sfd__h482143[6] ? 6'd18 : - (f1_sfd__h482142[5] ? + (f1_sfd__h482143[5] ? 6'd19 : - (f1_sfd__h482142[4] ? + (f1_sfd__h482143[4] ? 6'd20 : - (f1_sfd__h482142[3] ? + (f1_sfd__h482143[3] ? 6'd21 : - (f1_sfd__h482142[2] ? + (f1_sfd__h482143[2] ? 6'd22 : - (f1_sfd__h482142[1] ? + (f1_sfd__h482143[1] ? 6'd23 : - (f1_sfd__h482142[0] ? + (f1_sfd__h482143[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989 = - (f1_exp__h482141 == 8'd255 && f1_sfd__h482142 != 23'd0 || - (f1_exp__h482141 == 8'd255 || f1_exp__h482141 == 8'd0) && - f1_sfd__h482142 == 23'd0) ? + (f1_exp__h482142 == 8'd255 && f1_sfd__h482143 != 23'd0 || + (f1_exp__h482142 == 8'd255 || f1_exp__h482142 == 8'd0) && + f1_sfd__h482143 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h482141 == 8'd0) ? + ((f1_exp__h482142 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 = - (f1_exp__h482141 == 8'd255 && f1_sfd__h482142 != 23'd0) ? - _theResult___snd_fst_sfd__h482457 : - _theResult___fst_sfd__h520738 ; + (f1_exp__h482142 == 8'd255 && f1_sfd__h482143 != 23'd0) ? + _theResult___snd_fst_sfd__h482458 : + _theResult___fst_sfd__h520739 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989, - (f1_exp__h482141 == 8'd255) ? + (f1_exp__h482142 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h520734, + _theResult___fst_exp__h520735, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 = - ((f3_exp__h560439 == 8'd0) ? - (f3_sfd__h560440[22] ? + ((f3_exp__h560440 == 8'd0) ? + (f3_sfd__h560441[22] ? 6'd2 : - (f3_sfd__h560440[21] ? + (f3_sfd__h560441[21] ? 6'd3 : - (f3_sfd__h560440[20] ? + (f3_sfd__h560441[20] ? 6'd4 : - (f3_sfd__h560440[19] ? + (f3_sfd__h560441[19] ? 6'd5 : - (f3_sfd__h560440[18] ? + (f3_sfd__h560441[18] ? 6'd6 : - (f3_sfd__h560440[17] ? + (f3_sfd__h560441[17] ? 6'd7 : - (f3_sfd__h560440[16] ? + (f3_sfd__h560441[16] ? 6'd8 : - (f3_sfd__h560440[15] ? + (f3_sfd__h560441[15] ? 6'd9 : - (f3_sfd__h560440[14] ? + (f3_sfd__h560441[14] ? 6'd10 : - (f3_sfd__h560440[13] ? + (f3_sfd__h560441[13] ? 6'd11 : - (f3_sfd__h560440[12] ? + (f3_sfd__h560441[12] ? 6'd12 : - (f3_sfd__h560440[11] ? + (f3_sfd__h560441[11] ? 6'd13 : - (f3_sfd__h560440[10] ? + (f3_sfd__h560441[10] ? 6'd14 : - (f3_sfd__h560440[9] ? + (f3_sfd__h560441[9] ? 6'd15 : - (f3_sfd__h560440[8] ? + (f3_sfd__h560441[8] ? 6'd16 : - (f3_sfd__h560440[7] ? + (f3_sfd__h560441[7] ? 6'd17 : - (f3_sfd__h560440[6] ? + (f3_sfd__h560441[6] ? 6'd18 : - (f3_sfd__h560440[5] ? + (f3_sfd__h560441[5] ? 6'd19 : - (f3_sfd__h560440[4] ? + (f3_sfd__h560441[4] ? 6'd20 : - (f3_sfd__h560440[3] ? + (f3_sfd__h560441[3] ? 6'd21 : - (f3_sfd__h560440[2] ? + (f3_sfd__h560441[2] ? 6'd22 : - (f3_sfd__h560440[1] ? + (f3_sfd__h560441[1] ? 6'd23 : - (f3_sfd__h560440[0] ? + (f3_sfd__h560441[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704 = - (f3_exp__h560439 == 8'd255 && f3_sfd__h560440 != 23'd0 || - (f3_exp__h560439 == 8'd255 || f3_exp__h560439 == 8'd0) && - f3_sfd__h560440 == 23'd0) ? + (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0 || + (f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) && + f3_sfd__h560441 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h560439 == 8'd0) ? + ((f3_exp__h560440 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 = - (f3_exp__h560439 == 8'd255 && f3_sfd__h560440 != 23'd0) ? - _theResult___snd_fst_sfd__h560755 : - _theResult___fst_sfd__h598895 ; + (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0) ? + _theResult___snd_fst_sfd__h560756 : + _theResult___fst_sfd__h598896 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 = - { (f3_exp__h560439 == 8'd255) ? + { (f3_exp__h560440 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h598891, + _theResult___fst_exp__h598892, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21976,9 +21976,9 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938 = - (f3_exp__h560439 == 8'd255 && f3_sfd__h560440 != 23'd0 || - (f3_exp__h560439 == 8'd255 || f3_exp__h560439 == 8'd0) && - f3_sfd__h560440 == 23'd0) ? + (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0 || + (f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) && + f3_sfd__h560441 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22187,7 +22187,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || - _theResult___fst_exp__h540382 == 11'd2047) ? + _theResult___fst_exp__h540383 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22195,12 +22195,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || - _theResult___fst_exp__h501529 == 11'd2047) ? + _theResult___fst_exp__h501530 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -22208,12 +22208,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || - _theResult___fst_exp__h579686 == 11'd2047) ? + _theResult___fst_exp__h579687 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22221,7 +22221,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? @@ -22745,48 +22745,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[2] : - _theResult___fst_exp__h520722 == 11'd2047 && - _theResult___fst_sfd__h520723 == 52'd0 ; + _theResult___fst_exp__h520723 == 11'd2047 && + _theResult___fst_sfd__h520724 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[2] : - _theResult___fst_exp__h559575 == 11'd2047 && - _theResult___fst_sfd__h559576 == 52'd0 ; + _theResult___fst_exp__h559576 == 11'd2047 && + _theResult___fst_sfd__h559577 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[2] : - _theResult___fst_exp__h598879 == 11'd2047 && - _theResult___fst_sfd__h598880 == 52'd0 ; + _theResult___fst_exp__h598880 == 11'd2047 && + _theResult___fst_sfd__h598881 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[1] : - _theResult___fst_exp__h519939 == 11'd0 && - guard__h511949 != 2'b0 ; + _theResult___fst_exp__h519940 == 11'd0 && + guard__h511950 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[1] : - _theResult___fst_exp__h558792 == 11'd0 && - guard__h550802 != 2'b0 ; + _theResult___fst_exp__h558793 == 11'd0 && + guard__h550803 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[1] : - _theResult___fst_exp__h598096 == 11'd0 && - guard__h590106 != 2'b0 ; + _theResult___fst_exp__h598097 == 11'd0 && + guard__h590107 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[0] : - _theResult___fst_exp__h519939 != 11'd2047 && - guard__h511949 != 2'b0 ; + _theResult___fst_exp__h519940 != 11'd2047 && + guard__h511950 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[0] : - _theResult___fst_exp__h558792 != 11'd2047 && - guard__h550802 != 2'b0 ; + _theResult___fst_exp__h558793 != 11'd2047 && + guard__h550803 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[0] : - _theResult___fst_exp__h598096 != 11'd2047 && - guard__h590106 != 2'b0 ; + _theResult___fst_exp__h598097 != 11'd2047 && + guard__h590107 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -22832,35 +22832,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371963 == 8'd255) ? + ((_theResult___fst_exp__h371964 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084) : - ((_theResult___fst_exp__h380648 == 8'd255) ? + ((_theResult___fst_exp__h380649 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371963 == 8'd255) ? + ((_theResult___fst_exp__h371964 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127) : - ((_theResult___fst_exp__h380648 == 8'd255) ? + ((_theResult___fst_exp__h380649 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[2] : - _theResult___fst_exp__h381196 == 8'd255 && - _theResult___fst_sfd__h381197 == 23'd0 ; + _theResult___fst_exp__h381197 == 8'd255 && + _theResult___fst_sfd__h381198 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[1] : - _theResult___fst_exp__h380648 == 8'd0 && - guard__h372571 != 2'b0 ; + _theResult___fst_exp__h380649 == 8'd0 && + guard__h372572 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[0] : - _theResult___fst_exp__h380648 != 8'd255 && - guard__h372571 != 2'b0 ; + _theResult___fst_exp__h380649 != 8'd255 && + guard__h372572 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? @@ -22870,35 +22870,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417660 == 8'd255) ? + ((_theResult___fst_exp__h417661 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476) : - ((_theResult___fst_exp__h426345 == 8'd255) ? + ((_theResult___fst_exp__h426346 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417660 == 8'd255) ? + ((_theResult___fst_exp__h417661 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519) : - ((_theResult___fst_exp__h426345 == 8'd255) ? + ((_theResult___fst_exp__h426346 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[2] : - _theResult___fst_exp__h426893 == 8'd255 && - _theResult___fst_sfd__h426894 == 23'd0 ; + _theResult___fst_exp__h426894 == 8'd255 && + _theResult___fst_sfd__h426895 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[1] : - _theResult___fst_exp__h426345 == 8'd0 && - guard__h418268 != 2'b0 ; + _theResult___fst_exp__h426346 == 8'd0 && + guard__h418269 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[0] : - _theResult___fst_exp__h426345 != 8'd255 && - guard__h418268 != 2'b0 ; + _theResult___fst_exp__h426346 != 8'd255 && + guard__h418269 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? @@ -22908,35 +22908,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463355 == 8'd255) ? + ((_theResult___fst_exp__h463356 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868) : - ((_theResult___fst_exp__h472040 == 8'd255) ? + ((_theResult___fst_exp__h472041 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463355 == 8'd255) ? + ((_theResult___fst_exp__h463356 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911) : - ((_theResult___fst_exp__h472040 == 8'd255) ? + ((_theResult___fst_exp__h472041 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[2] : - _theResult___fst_exp__h472588 == 8'd255 && - _theResult___fst_sfd__h472589 == 23'd0 ; + _theResult___fst_exp__h472589 == 8'd255 && + _theResult___fst_sfd__h472590 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[1] : - _theResult___fst_exp__h472040 == 8'd0 && - guard__h463963 != 2'b0 ; + _theResult___fst_exp__h472041 == 8'd0 && + guard__h463964 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[0] : - _theResult___fst_exp__h472040 != 8'd255 && - guard__h463963 != 2'b0 ; + _theResult___fst_exp__h472041 != 8'd255 && + guard__h463964 != 2'b0 ; assign IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 = checkForException___d13008[4] ? CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 : @@ -22947,10 +22947,10 @@ module mkCore(CLK, 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h712487, - pc__h712387, - x__h714645, - x__h714837, + x_prv__h712488, + pc__h712388, + x__h714646, + x__h714838, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -23608,8 +23608,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h646695 : - w__h646690 ; + result__h646696 : + w__h646691 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23631,39 +23631,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23716,7 +23716,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h197127 : + x__h197128 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ? 64'd0 : 64'd1) ; @@ -23728,7 +23728,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 = - _theResult_____2__h296522 == v__h295942 ; + _theResult_____2__h296523 == v__h295943 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23737,7 +23737,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 = - _theResult_____2__h304518 == v__h299287 ; + _theResult_____2__h304519 == v__h299288 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23766,7 +23766,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h302152 } ; + x__h302153 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -23864,35 +23864,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -23920,7 +23920,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 = - _theResult_____2__h310512 == v__h309801 ; + _theResult_____2__h310513 == v__h309802 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23929,7 +23929,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 = - _theResult_____2__h318366 == v__h313677 ; + _theResult_____2__h318367 == v__h313678 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24081,7 +24081,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 = - _theResult_____2__h331935 == v__h331503 ; + _theResult_____2__h331936 == v__h331504 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -24130,7 +24130,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 = - _theResult_____2__h328710 == v__h328278 ; + _theResult_____2__h328711 == v__h328279 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -24162,7 +24162,7 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h726805 : + upd__h726676 : csrf_minstret_ehr_data_rl ; assign IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 = csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? @@ -24289,10 +24289,10 @@ module mkCore(CLK, mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 = - rob$deqPort_0_canDeq ? y_avValue_fst__h730027 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_fst__h729898 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h730502 : + y_avValue_snd_snd_snd_fst__h730373 : 2'd0 ; assign IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? @@ -24325,48 +24325,48 @@ module mkCore(CLK, rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__5328_BIT_25_532_ETC___d15680 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin11100_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h511100[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin17654_BIT_33_THEN_2_ELSE_0__q74 = - sfdin__h417654[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin45583_BIT_33_THEN_2_ELSE_0__q99 = - sfdin__h445583[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin49953_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h549953[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin54191_BIT_33_THEN_2_ELSE_0__q29 = - sfdin__h354191[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin63349_BIT_33_THEN_2_ELSE_0__q109 = - sfdin__h463349[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin71957_BIT_33_THEN_2_ELSE_0__q39 = - sfdin__h371957[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin89257_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h589257[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin99888_BIT_33_THEN_2_ELSE_0__q64 = - sfdin__h399888[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01480_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h501480[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd08501_BIT_33_THEN_2_ELSE_0__q66 = - _theResult___snd__h408501[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd19885_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h519885[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd26291_BIT_33_THEN_2_ELSE_0__q79 = - _theResult___snd__h426291[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40333_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h540333[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd54196_BIT_33_THEN_2_ELSE_0__q101 = - _theResult___snd__h454196[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58738_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h558738[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd62804_BIT_33_THEN_2_ELSE_0__q31 = - _theResult___snd__h362804[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd71986_BIT_33_THEN_2_ELSE_0__q114 = - _theResult___snd__h471986[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd79637_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h579637[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd80594_BIT_33_THEN_2_ELSE_0__q44 = - _theResult___snd__h380594[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98042_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h598042[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h511101[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74 = + sfdin__h417655[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99 = + sfdin__h445584[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h549954[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29 = + sfdin__h354192[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109 = + sfdin__h463350[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39 = + sfdin__h371958[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h589258[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64 = + sfdin__h399889[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h501481[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66 = + _theResult___snd__h408502[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h519886[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79 = + _theResult___snd__h426292[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h540334[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101 = + _theResult___snd__h454197[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h558739[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31 = + _theResult___snd__h362805[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114 = + _theResult___snd__h471987[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h579638[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44 = + _theResult___snd__h380595[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h598043[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? @@ -24458,131 +24458,131 @@ module mkCore(CLK, !checkForException___d13698[4] && NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__5320_5321_OR__ETC___d15686 = - (fflags__h733287 & csrf_fflags_reg) != fflags__h733287 || + (fflags__h733158 & csrf_fflags_reg) != fflags__h733158 || csrf_fs_reg != 2'b11 && (IF_rob_deqPort_1_canDeq__5325_THEN_IF_NOT_rob__ETC___d15681 || - fflags__h733287 != 5'd0) ; + fflags__h733158 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 = - !f2_sfd__h521136[21] && !f2_sfd__h521136[20] && - !f2_sfd__h521136[19] && - !f2_sfd__h521136[18] && - !f2_sfd__h521136[17] && - !f2_sfd__h521136[16] && - !f2_sfd__h521136[15] && - !f2_sfd__h521136[14] && - !f2_sfd__h521136[13] && - !f2_sfd__h521136[12] && - !f2_sfd__h521136[11] && - !f2_sfd__h521136[10] && - !f2_sfd__h521136[9] && - !f2_sfd__h521136[8] && - !f2_sfd__h521136[7] && - !f2_sfd__h521136[6] && - !f2_sfd__h521136[5] && - !f2_sfd__h521136[4] && - !f2_sfd__h521136[3] && - !f2_sfd__h521136[2] && - !f2_sfd__h521136[1] && - !f2_sfd__h521136[0] ; + !f2_sfd__h521137[21] && !f2_sfd__h521137[20] && + !f2_sfd__h521137[19] && + !f2_sfd__h521137[18] && + !f2_sfd__h521137[17] && + !f2_sfd__h521137[16] && + !f2_sfd__h521137[15] && + !f2_sfd__h521137[14] && + !f2_sfd__h521137[13] && + !f2_sfd__h521137[12] && + !f2_sfd__h521137[11] && + !f2_sfd__h521137[10] && + !f2_sfd__h521137[9] && + !f2_sfd__h521137[8] && + !f2_sfd__h521137[7] && + !f2_sfd__h521137[6] && + !f2_sfd__h521137[5] && + !f2_sfd__h521137[4] && + !f2_sfd__h521137[3] && + !f2_sfd__h521137[2] && + !f2_sfd__h521137[1] && + !f2_sfd__h521137[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 = - !f1_sfd__h482142[21] && !f1_sfd__h482142[20] && - !f1_sfd__h482142[19] && - !f1_sfd__h482142[18] && - !f1_sfd__h482142[17] && - !f1_sfd__h482142[16] && - !f1_sfd__h482142[15] && - !f1_sfd__h482142[14] && - !f1_sfd__h482142[13] && - !f1_sfd__h482142[12] && - !f1_sfd__h482142[11] && - !f1_sfd__h482142[10] && - !f1_sfd__h482142[9] && - !f1_sfd__h482142[8] && - !f1_sfd__h482142[7] && - !f1_sfd__h482142[6] && - !f1_sfd__h482142[5] && - !f1_sfd__h482142[4] && - !f1_sfd__h482142[3] && - !f1_sfd__h482142[2] && - !f1_sfd__h482142[1] && - !f1_sfd__h482142[0] ; + !f1_sfd__h482143[21] && !f1_sfd__h482143[20] && + !f1_sfd__h482143[19] && + !f1_sfd__h482143[18] && + !f1_sfd__h482143[17] && + !f1_sfd__h482143[16] && + !f1_sfd__h482143[15] && + !f1_sfd__h482143[14] && + !f1_sfd__h482143[13] && + !f1_sfd__h482143[12] && + !f1_sfd__h482143[11] && + !f1_sfd__h482143[10] && + !f1_sfd__h482143[9] && + !f1_sfd__h482143[8] && + !f1_sfd__h482143[7] && + !f1_sfd__h482143[6] && + !f1_sfd__h482143[5] && + !f1_sfd__h482143[4] && + !f1_sfd__h482143[3] && + !f1_sfd__h482143[2] && + !f1_sfd__h482143[1] && + !f1_sfd__h482143[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 = - !f3_sfd__h560440[21] && !f3_sfd__h560440[20] && - !f3_sfd__h560440[19] && - !f3_sfd__h560440[18] && - !f3_sfd__h560440[17] && - !f3_sfd__h560440[16] && - !f3_sfd__h560440[15] && - !f3_sfd__h560440[14] && - !f3_sfd__h560440[13] && - !f3_sfd__h560440[12] && - !f3_sfd__h560440[11] && - !f3_sfd__h560440[10] && - !f3_sfd__h560440[9] && - !f3_sfd__h560440[8] && - !f3_sfd__h560440[7] && - !f3_sfd__h560440[6] && - !f3_sfd__h560440[5] && - !f3_sfd__h560440[4] && - !f3_sfd__h560440[3] && - !f3_sfd__h560440[2] && - !f3_sfd__h560440[1] && - !f3_sfd__h560440[0] ; + !f3_sfd__h560441[21] && !f3_sfd__h560441[20] && + !f3_sfd__h560441[19] && + !f3_sfd__h560441[18] && + !f3_sfd__h560441[17] && + !f3_sfd__h560441[16] && + !f3_sfd__h560441[15] && + !f3_sfd__h560441[14] && + !f3_sfd__h560441[13] && + !f3_sfd__h560441[12] && + !f3_sfd__h560441[11] && + !f3_sfd__h560441[10] && + !f3_sfd__h560441[9] && + !f3_sfd__h560441[8] && + !f3_sfd__h560441[7] && + !f3_sfd__h560441[6] && + !f3_sfd__h560441[5] && + !f3_sfd__h560441[4] && + !f3_sfd__h560441[3] && + !f3_sfd__h560441[2] && + !f3_sfd__h560441[1] && + !f3_sfd__h560441[0] ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -25157,7 +25157,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 && !csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 && - csr_addr__h655327 != 12'h8FF) ; + csr_addr__h655328 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -25282,9 +25282,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h655328 == 5'd0 && - imm__h655329 == 32'd0 || - csr_addr__h655327[11:10] != 2'b11 ; + rs1__h655329 == 5'd0 && + imm__h655330 == 32'd0 || + csr_addr__h655328[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && @@ -25611,7 +25611,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - x__h291617 } ; + x__h291618 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16102 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, @@ -25630,8 +25630,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = - { {4{f2_exp21135_MINUS_127__q176[7]}}, - f2_exp21135_MINUS_127__q176 } ; + { {4{f2_exp21136_MINUS_127__q176[7]}}, + f2_exp21136_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^ 12'h800) <= @@ -25641,8 +25641,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 = - { {4{f1_exp82141_MINUS_127__q136[7]}}, - f1_exp82141_MINUS_127__q136 } ; + { {4{f1_exp82142_MINUS_127__q136[7]}}, + f1_exp82142_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^ 12'h800) <= @@ -25652,8 +25652,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 = - { {4{f3_exp60439_MINUS_127__q153[7]}}, - f3_exp60439_MINUS_127__q153 } ; + { {4{f3_exp60440_MINUS_127__q153[7]}}, + f3_exp60440_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^ 12'h800) <= @@ -25738,15 +25738,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169 = { 3'd0, - _theResult___fst_exp__h354197 == 8'd0 && - (sfdin__h354191[56:34] == 23'd0 || guard__h346096 != 2'b0), + _theResult___fst_exp__h354198 == 8'd0 && + (sfdin__h354192[56:34] == 23'd0 || guard__h346097 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h354794 == 8'd255 && - _theResult___fst_sfd__h354795 == 23'd0, + _theResult___fst_exp__h354795 == 8'd255 && + _theResult___fst_sfd__h354796 == 23'd0, 1'd0, - _theResult___fst_exp__h354197 != 8'd255 && - guard__h346096 != 2'b0 } ; + _theResult___fst_exp__h354198 != 8'd255 && + guard__h346097 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ^ @@ -25754,15 +25754,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561 = { 3'd0, - _theResult___fst_exp__h399894 == 8'd0 && - (sfdin__h399888[56:34] == 23'd0 || guard__h391795 != 2'b0), + _theResult___fst_exp__h399895 == 8'd0 && + (sfdin__h399889[56:34] == 23'd0 || guard__h391796 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h400491 == 8'd255 && - _theResult___fst_sfd__h400492 == 23'd0, + _theResult___fst_exp__h400492 == 8'd255 && + _theResult___fst_sfd__h400493 == 23'd0, 1'd0, - _theResult___fst_exp__h399894 != 8'd255 && - guard__h391795 != 2'b0 } ; + _theResult___fst_exp__h399895 != 8'd255 && + guard__h391796 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ^ @@ -25770,15 +25770,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953 = { 3'd0, - _theResult___fst_exp__h445589 == 8'd0 && - (sfdin__h445583[56:34] == 23'd0 || guard__h437490 != 2'b0), + _theResult___fst_exp__h445590 == 8'd0 && + (sfdin__h445584[56:34] == 23'd0 || guard__h437491 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h446186 == 8'd255 && - _theResult___fst_sfd__h446187 == 23'd0, + _theResult___fst_exp__h446187 == 8'd255 && + _theResult___fst_sfd__h446188 == 23'd0, 1'd0, - _theResult___fst_exp__h445589 != 8'd255 && - guard__h437490 != 2'b0 } ; + _theResult___fst_exp__h445590 != 8'd255 && + guard__h437491 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ^ @@ -25786,37 +25786,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758 = { 3'd0, - _theResult___fst_exp__h511106 == 11'd0 && - (sfdin__h511100[56:5] == 52'd0 || guard__h502880 != 2'b0), + _theResult___fst_exp__h511107 == 11'd0 && + (sfdin__h511101[56:5] == 52'd0 || guard__h502881 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h511938 == 11'd2047 && - _theResult___fst_sfd__h511939 == 52'd0, + _theResult___fst_exp__h511939 == 11'd2047 && + _theResult___fst_sfd__h511940 == 52'd0, 1'd0, - _theResult___fst_exp__h511106 != 11'd2047 && - guard__h502880 != 2'b0 } ; + _theResult___fst_exp__h511107 != 11'd2047 && + guard__h502881 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799 = { 3'd0, - _theResult___fst_exp__h549959 == 11'd0 && - (sfdin__h549953[56:5] == 52'd0 || guard__h541733 != 2'b0), + _theResult___fst_exp__h549960 == 11'd0 && + (sfdin__h549954[56:5] == 52'd0 || guard__h541734 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h550791 == 11'd2047 && - _theResult___fst_sfd__h550792 == 52'd0, + _theResult___fst_exp__h550792 == 11'd2047 && + _theResult___fst_sfd__h550793 == 52'd0, 1'd0, - _theResult___fst_exp__h549959 != 11'd2047 && - guard__h541733 != 2'b0 } ; + _theResult___fst_exp__h549960 != 11'd2047 && + guard__h541734 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843 = { 3'd0, - _theResult___fst_exp__h589263 == 11'd0 && - (sfdin__h589257[56:5] == 52'd0 || guard__h581037 != 2'b0), + _theResult___fst_exp__h589264 == 11'd0 && + (sfdin__h589258[56:5] == 52'd0 || guard__h581038 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h590095 == 11'd2047 && - _theResult___fst_sfd__h590096 == 52'd0, + _theResult___fst_exp__h590096 == 11'd2047 && + _theResult___fst_sfd__h590097 == 52'd0, 1'd0, - _theResult___fst_exp__h589263 != 11'd2047 && - guard__h581037 != 2'b0 } ; + _theResult___fst_exp__h589264 != 11'd2047 && + guard__h581038 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ^ @@ -25834,15 +25834,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198 = { 3'd0, - _theResult___fst_exp__h371963 == 8'd0 && - (sfdin__h371957[56:34] == 23'd0 || guard__h363735 != 2'b0), + _theResult___fst_exp__h371964 == 8'd0 && + (sfdin__h371958[56:34] == 23'd0 || guard__h363736 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h372560 == 8'd255 && - _theResult___fst_sfd__h372561 == 23'd0, + _theResult___fst_exp__h372561 == 8'd255 && + _theResult___fst_sfd__h372562 == 23'd0, 1'd0, - _theResult___fst_exp__h371963 != 8'd255 && - guard__h363735 != 2'b0 } ; + _theResult___fst_exp__h371964 != 8'd255 && + guard__h363736 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ^ @@ -25850,15 +25850,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590 = { 3'd0, - _theResult___fst_exp__h417660 == 8'd0 && - (sfdin__h417654[56:34] == 23'd0 || guard__h409432 != 2'b0), + _theResult___fst_exp__h417661 == 8'd0 && + (sfdin__h417655[56:34] == 23'd0 || guard__h409433 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h418257 == 8'd255 && - _theResult___fst_sfd__h418258 == 23'd0, + _theResult___fst_exp__h418258 == 8'd255 && + _theResult___fst_sfd__h418259 == 23'd0, 1'd0, - _theResult___fst_exp__h417660 != 8'd255 && - guard__h409432 != 2'b0 } ; + _theResult___fst_exp__h417661 != 8'd255 && + guard__h409433 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ^ @@ -25866,15 +25866,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982 = { 3'd0, - _theResult___fst_exp__h463355 == 8'd0 && - (sfdin__h463349[56:34] == 23'd0 || guard__h455127 != 2'b0), + _theResult___fst_exp__h463356 == 8'd0 && + (sfdin__h463350[56:34] == 23'd0 || guard__h455128 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h463952 == 8'd255 && - _theResult___fst_sfd__h463953 == 23'd0, + _theResult___fst_exp__h463953 == 8'd255 && + _theResult___fst_sfd__h463954 == 23'd0, 1'd0, - _theResult___fst_exp__h463355 != 8'd255 && - guard__h455127 != 2'b0 } ; + _theResult___fst_exp__h463356 != 8'd255 && + guard__h455128 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^ @@ -25888,37 +25888,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741 = { 3'd0, - _theResult___fst_exp__h501529 == 11'd0 && - guard__h493568 != 2'b0, + _theResult___fst_exp__h501530 == 11'd0 && + guard__h493569 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h502287 == 11'd2047 && - _theResult___fst_sfd__h502288 == 52'd0, + _theResult___fst_exp__h502288 == 11'd2047 && + _theResult___fst_sfd__h502289 == 52'd0, 1'd0, - _theResult___fst_exp__h501529 != 11'd2047 && - guard__h493568 != 2'b0 } ; + _theResult___fst_exp__h501530 != 11'd2047 && + guard__h493569 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782 = { 3'd0, - _theResult___fst_exp__h540382 == 11'd0 && - guard__h532421 != 2'b0, + _theResult___fst_exp__h540383 == 11'd0 && + guard__h532422 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h541140 == 11'd2047 && - _theResult___fst_sfd__h541141 == 52'd0, + _theResult___fst_exp__h541141 == 11'd2047 && + _theResult___fst_sfd__h541142 == 52'd0, 1'd0, - _theResult___fst_exp__h540382 != 11'd2047 && - guard__h532421 != 2'b0 } ; + _theResult___fst_exp__h540383 != 11'd2047 && + guard__h532422 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826 = { 3'd0, - _theResult___fst_exp__h579686 == 11'd0 && - guard__h571725 != 2'b0, + _theResult___fst_exp__h579687 == 11'd0 && + guard__h571726 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h580444 == 11'd2047 && - _theResult___fst_sfd__h580445 == 52'd0, + _theResult___fst_exp__h580445 == 11'd2047 && + _theResult___fst_sfd__h580446 == 52'd0, 1'd0, - _theResult___fst_exp__h579686 != 11'd2047 && - guard__h571725 != 2'b0 } ; + _theResult___fst_exp__h579687 != 11'd2047 && + guard__h571726 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^ @@ -25954,15 +25954,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181 = { 3'd0, - _theResult___fst_exp__h362853 == 8'd0 && - guard__h354805 != 2'b0, + _theResult___fst_exp__h362854 == 8'd0 && + guard__h354806 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h363376 == 8'd255 && - _theResult___fst_sfd__h363377 == 23'd0, + _theResult___fst_exp__h363377 == 8'd255 && + _theResult___fst_sfd__h363378 == 23'd0, 1'd0, - _theResult___fst_exp__h362853 != 8'd255 && - guard__h354805 != 2'b0 } ; + _theResult___fst_exp__h362854 != 8'd255 && + guard__h354806 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^ @@ -25976,15 +25976,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573 = { 3'd0, - _theResult___fst_exp__h408550 == 8'd0 && - guard__h400502 != 2'b0, + _theResult___fst_exp__h408551 == 8'd0 && + guard__h400503 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h409073 == 8'd255 && - _theResult___fst_sfd__h409074 == 23'd0, + _theResult___fst_exp__h409074 == 8'd255 && + _theResult___fst_sfd__h409075 == 23'd0, 1'd0, - _theResult___fst_exp__h408550 != 8'd255 && - guard__h400502 != 2'b0 } ; + _theResult___fst_exp__h408551 != 8'd255 && + guard__h400503 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^ @@ -25998,15 +25998,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965 = { 3'd0, - _theResult___fst_exp__h454245 == 8'd0 && - guard__h446197 != 2'b0, + _theResult___fst_exp__h454246 == 8'd0 && + guard__h446198 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h454768 == 8'd255 && - _theResult___fst_sfd__h454769 == 23'd0, + _theResult___fst_exp__h454769 == 8'd255 && + _theResult___fst_sfd__h454770 == 23'd0, 1'd0, - _theResult___fst_exp__h454245 != 8'd255 && - guard__h446197 != 2'b0 } ; + _theResult___fst_exp__h454246 != 8'd255 && + guard__h446198 != 2'b0 } ; assign _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798 = { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, @@ -26020,7 +26020,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -26034,35 +26034,35 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138 = - sfd__h521497 >> + sfd__h521498 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653 = - sfd__h482503 >> + sfd__h482504 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368 = - sfd__h560801 >> + sfd__h560802 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558 = - sfd__h338481 >> + sfd__h338482 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950 = - sfd__h384183 >> + sfd__h384184 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342 = - sfd__h429878 >> + sfd__h429879 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ; assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 = - mip_csr__read__h611252 == commitStage_rg_old_mip_csr_val ; + mip_csr__read__h611253 == commitStage_rg_old_mip_csr_val ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716 = - medeleg_csr__read__h610371[i__h709458] ; + medeleg_csr__read__h610372[i__h709459] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 = - mideleg_csr__read__h610466[i__h709618] ; + mideleg_csr__read__h610467[i__h709619] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 = 12'd3074 - { 6'd0, @@ -26468,51 +26468,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 = 12'd3970 - { 7'd0, - f2_sfd__h521136[22] ? + f2_sfd__h521137[22] ? 5'd0 : - (f2_sfd__h521136[21] ? + (f2_sfd__h521137[21] ? 5'd1 : - (f2_sfd__h521136[20] ? + (f2_sfd__h521137[20] ? 5'd2 : - (f2_sfd__h521136[19] ? + (f2_sfd__h521137[19] ? 5'd3 : - (f2_sfd__h521136[18] ? + (f2_sfd__h521137[18] ? 5'd4 : - (f2_sfd__h521136[17] ? + (f2_sfd__h521137[17] ? 5'd5 : - (f2_sfd__h521136[16] ? + (f2_sfd__h521137[16] ? 5'd6 : - (f2_sfd__h521136[15] ? + (f2_sfd__h521137[15] ? 5'd7 : - (f2_sfd__h521136[14] ? + (f2_sfd__h521137[14] ? 5'd8 : - (f2_sfd__h521136[13] ? + (f2_sfd__h521137[13] ? 5'd9 : - (f2_sfd__h521136[12] ? + (f2_sfd__h521137[12] ? 5'd10 : - (f2_sfd__h521136[11] ? + (f2_sfd__h521137[11] ? 5'd11 : - (f2_sfd__h521136[10] ? + (f2_sfd__h521137[10] ? 5'd12 : - (f2_sfd__h521136[9] ? + (f2_sfd__h521137[9] ? 5'd13 : - (f2_sfd__h521136[8] ? + (f2_sfd__h521137[8] ? 5'd14 : - (f2_sfd__h521136[7] ? + (f2_sfd__h521137[7] ? 5'd15 : - (f2_sfd__h521136[6] ? + (f2_sfd__h521137[6] ? 5'd16 : - (f2_sfd__h521136[5] ? + (f2_sfd__h521137[5] ? 5'd17 : - (f2_sfd__h521136[4] ? + (f2_sfd__h521137[4] ? 5'd18 : - (f2_sfd__h521136[3] ? + (f2_sfd__h521137[3] ? 5'd19 : - (f2_sfd__h521136[2] ? + (f2_sfd__h521137[2] ? 5'd20 : - (f2_sfd__h521136[1] ? + (f2_sfd__h521137[1] ? 5'd21 : - (f2_sfd__h521136[0] ? + (f2_sfd__h521137[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 = @@ -26526,51 +26526,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 = 12'd3970 - { 7'd0, - f1_sfd__h482142[22] ? + f1_sfd__h482143[22] ? 5'd0 : - (f1_sfd__h482142[21] ? + (f1_sfd__h482143[21] ? 5'd1 : - (f1_sfd__h482142[20] ? + (f1_sfd__h482143[20] ? 5'd2 : - (f1_sfd__h482142[19] ? + (f1_sfd__h482143[19] ? 5'd3 : - (f1_sfd__h482142[18] ? + (f1_sfd__h482143[18] ? 5'd4 : - (f1_sfd__h482142[17] ? + (f1_sfd__h482143[17] ? 5'd5 : - (f1_sfd__h482142[16] ? + (f1_sfd__h482143[16] ? 5'd6 : - (f1_sfd__h482142[15] ? + (f1_sfd__h482143[15] ? 5'd7 : - (f1_sfd__h482142[14] ? + (f1_sfd__h482143[14] ? 5'd8 : - (f1_sfd__h482142[13] ? + (f1_sfd__h482143[13] ? 5'd9 : - (f1_sfd__h482142[12] ? + (f1_sfd__h482143[12] ? 5'd10 : - (f1_sfd__h482142[11] ? + (f1_sfd__h482143[11] ? 5'd11 : - (f1_sfd__h482142[10] ? + (f1_sfd__h482143[10] ? 5'd12 : - (f1_sfd__h482142[9] ? + (f1_sfd__h482143[9] ? 5'd13 : - (f1_sfd__h482142[8] ? + (f1_sfd__h482143[8] ? 5'd14 : - (f1_sfd__h482142[7] ? + (f1_sfd__h482143[7] ? 5'd15 : - (f1_sfd__h482142[6] ? + (f1_sfd__h482143[6] ? 5'd16 : - (f1_sfd__h482142[5] ? + (f1_sfd__h482143[5] ? 5'd17 : - (f1_sfd__h482142[4] ? + (f1_sfd__h482143[4] ? 5'd18 : - (f1_sfd__h482142[3] ? + (f1_sfd__h482143[3] ? 5'd19 : - (f1_sfd__h482142[2] ? + (f1_sfd__h482143[2] ? 5'd20 : - (f1_sfd__h482142[1] ? + (f1_sfd__h482143[1] ? 5'd21 : - (f1_sfd__h482142[0] ? + (f1_sfd__h482143[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 = @@ -26584,51 +26584,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 = 12'd3970 - { 7'd0, - f3_sfd__h560440[22] ? + f3_sfd__h560441[22] ? 5'd0 : - (f3_sfd__h560440[21] ? + (f3_sfd__h560441[21] ? 5'd1 : - (f3_sfd__h560440[20] ? + (f3_sfd__h560441[20] ? 5'd2 : - (f3_sfd__h560440[19] ? + (f3_sfd__h560441[19] ? 5'd3 : - (f3_sfd__h560440[18] ? + (f3_sfd__h560441[18] ? 5'd4 : - (f3_sfd__h560440[17] ? + (f3_sfd__h560441[17] ? 5'd5 : - (f3_sfd__h560440[16] ? + (f3_sfd__h560441[16] ? 5'd6 : - (f3_sfd__h560440[15] ? + (f3_sfd__h560441[15] ? 5'd7 : - (f3_sfd__h560440[14] ? + (f3_sfd__h560441[14] ? 5'd8 : - (f3_sfd__h560440[13] ? + (f3_sfd__h560441[13] ? 5'd9 : - (f3_sfd__h560440[12] ? + (f3_sfd__h560441[12] ? 5'd10 : - (f3_sfd__h560440[11] ? + (f3_sfd__h560441[11] ? 5'd11 : - (f3_sfd__h560440[10] ? + (f3_sfd__h560441[10] ? 5'd12 : - (f3_sfd__h560440[9] ? + (f3_sfd__h560441[9] ? 5'd13 : - (f3_sfd__h560440[8] ? + (f3_sfd__h560441[8] ? 5'd14 : - (f3_sfd__h560440[7] ? + (f3_sfd__h560441[7] ? 5'd15 : - (f3_sfd__h560440[6] ? + (f3_sfd__h560441[6] ? 5'd16 : - (f3_sfd__h560440[5] ? + (f3_sfd__h560441[5] ? 5'd17 : - (f3_sfd__h560440[4] ? + (f3_sfd__h560441[4] ? 5'd18 : - (f3_sfd__h560440[3] ? + (f3_sfd__h560441[3] ? 5'd19 : - (f3_sfd__h560440[2] ? + (f3_sfd__h560441[2] ? 5'd20 : - (f3_sfd__h560440[1] ? + (f3_sfd__h560441[1] ? 5'd21 : - (f3_sfd__h560440[0] ? + (f3_sfd__h560441[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 = @@ -26657,14 +26657,14 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h669625 == 1'd1 && + k__h669626 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == 1'd1 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208 ; assign _dfoo18 = - k__h669625 == 1'd0 && + k__h669626 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == @@ -26781,1421 +26781,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h296522 = + assign _theResult_____2__h296523 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046) ? - next_deqP___1__h296801 : + next_deqP___1__h296802 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h304518 = + assign _theResult_____2__h304519 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153) ? - next_deqP___1__h304797 : + next_deqP___1__h304798 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h310512 = + assign _theResult_____2__h310513 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324) ? - next_deqP___1__h311078 : + next_deqP___1__h311079 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h318366 = + assign _theResult_____2__h318367 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420) ? - next_deqP___1__h318932 : + next_deqP___1__h318933 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h328710 = + assign _theResult_____2__h328711 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649) ? - next_deqP___1__h328989 : + next_deqP___1__h328990 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h331935 = + assign _theResult_____2__h331936 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743) ? - next_deqP___1__h332214 : + next_deqP___1__h332215 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h346086 = - (value__h346708 == 54'd0) ? sfd__h338481 : 57'd1 ; - assign _theResult____h363725 = + assign _theResult____h346087 = + (value__h346709 == 54'd0) ? sfd__h338482 : 57'd1 ; + assign _theResult____h363726 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ^ 12'h800) < 12'd2105) ? - result__h364338 : - _theResult____h346086 ; - assign _theResult____h391785 = - (value__h392405 == 54'd0) ? sfd__h384183 : 57'd1 ; - assign _theResult____h409422 = + result__h364339 : + _theResult____h346087 ; + assign _theResult____h391786 = + (value__h392406 == 54'd0) ? sfd__h384184 : 57'd1 ; + assign _theResult____h409423 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ^ 12'h800) < 12'd2105) ? - result__h410035 : - _theResult____h391785 ; - assign _theResult____h437480 = - (value__h438100 == 54'd0) ? sfd__h429878 : 57'd1 ; - assign _theResult____h455117 = + result__h410036 : + _theResult____h391786 ; + assign _theResult____h437481 = + (value__h438101 == 54'd0) ? sfd__h429879 : 57'd1 ; + assign _theResult____h455118 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ^ 12'h800) < 12'd2105) ? - result__h455730 : - _theResult____h437480 ; - assign _theResult____h502870 = + result__h455731 : + _theResult____h437481 ; + assign _theResult____h502871 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ^ 12'h800) < 12'd2105) ? - result__h503483 : - ((value__h487086 == 25'd0) ? sfd__h482503 : 57'd1) ; - assign _theResult____h541723 = + result__h503484 : + ((value__h487087 == 25'd0) ? sfd__h482504 : 57'd1) ; + assign _theResult____h541724 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ^ 12'h800) < 12'd2105) ? - result__h542336 : - ((value__h525939 == 25'd0) ? sfd__h521497 : 57'd1) ; - assign _theResult____h581027 = + result__h542337 : + ((value__h525940 == 25'd0) ? sfd__h521498 : 57'd1) ; + assign _theResult____h581028 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ^ 12'h800) < 12'd2105) ? - result__h581640 : - ((value__h565243 == 25'd0) ? sfd__h560801 : 57'd1) ; - assign _theResult____h651118 = + result__h581641 : + ((value__h565244 == 25'd0) ? sfd__h560802 : 57'd1) ; + assign _theResult____h651119 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h651643 : + enabled_ints___1__h651644 : 16'd0 ; - assign _theResult___exp__h354713 = - sfd__h354289[24] ? - ((_theResult___fst_exp__h354197 == 8'd254) ? + assign _theResult___exp__h354714 = + sfd__h354290[24] ? + ((_theResult___fst_exp__h354198 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381230) : - ((_theResult___fst_exp__h354197 == 8'd0 && - sfd__h354289[24:23] == 2'b01) ? + din_inc___2_exp__h381231) : + ((_theResult___fst_exp__h354198 == 8'd0 && + sfd__h354290[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h354197) ; - assign _theResult___exp__h363295 = - sfd__h362871[24] ? - ((_theResult___fst_exp__h362853 == 8'd254) ? + _theResult___fst_exp__h354198) ; + assign _theResult___exp__h363296 = + sfd__h362872[24] ? + ((_theResult___fst_exp__h362854 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381254) : - ((_theResult___fst_exp__h362853 == 8'd0 && - sfd__h362871[24:23] == 2'b01) ? + din_inc___2_exp__h381255) : + ((_theResult___fst_exp__h362854 == 8'd0 && + sfd__h362872[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h362853) ; - assign _theResult___exp__h372479 = - sfd__h372055[24] ? - ((_theResult___fst_exp__h371963 == 8'd254) ? + _theResult___fst_exp__h362854) ; + assign _theResult___exp__h372480 = + sfd__h372056[24] ? + ((_theResult___fst_exp__h371964 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381284) : - ((_theResult___fst_exp__h371963 == 8'd0 && - sfd__h372055[24:23] == 2'b01) ? + din_inc___2_exp__h381285) : + ((_theResult___fst_exp__h371964 == 8'd0 && + sfd__h372056[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h371963) ; - assign _theResult___exp__h381115 = - sfd__h380667[24] ? - ((_theResult___fst_exp__h380648 == 8'd254) ? + _theResult___fst_exp__h371964) ; + assign _theResult___exp__h381116 = + sfd__h380668[24] ? + ((_theResult___fst_exp__h380649 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381308) : - ((_theResult___fst_exp__h380648 == 8'd0 && - sfd__h380667[24:23] == 2'b01) ? + din_inc___2_exp__h381309) : + ((_theResult___fst_exp__h380649 == 8'd0 && + sfd__h380668[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h380648) ; - assign _theResult___exp__h381217 = + _theResult___fst_exp__h380649) ; + assign _theResult___exp__h381218 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381208 ; - assign _theResult___exp__h400410 = - sfd__h399986[24] ? - ((_theResult___fst_exp__h399894 == 8'd254) ? + _theResult___fst_exp__h381209 ; + assign _theResult___exp__h400411 = + sfd__h399987[24] ? + ((_theResult___fst_exp__h399895 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426927) : - ((_theResult___fst_exp__h399894 == 8'd0 && - sfd__h399986[24:23] == 2'b01) ? + din_inc___2_exp__h426928) : + ((_theResult___fst_exp__h399895 == 8'd0 && + sfd__h399987[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h399894) ; - assign _theResult___exp__h408992 = - sfd__h408568[24] ? - ((_theResult___fst_exp__h408550 == 8'd254) ? + _theResult___fst_exp__h399895) ; + assign _theResult___exp__h408993 = + sfd__h408569[24] ? + ((_theResult___fst_exp__h408551 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426951) : - ((_theResult___fst_exp__h408550 == 8'd0 && - sfd__h408568[24:23] == 2'b01) ? + din_inc___2_exp__h426952) : + ((_theResult___fst_exp__h408551 == 8'd0 && + sfd__h408569[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h408550) ; - assign _theResult___exp__h418176 = - sfd__h417752[24] ? - ((_theResult___fst_exp__h417660 == 8'd254) ? + _theResult___fst_exp__h408551) ; + assign _theResult___exp__h418177 = + sfd__h417753[24] ? + ((_theResult___fst_exp__h417661 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426981) : - ((_theResult___fst_exp__h417660 == 8'd0 && - sfd__h417752[24:23] == 2'b01) ? + din_inc___2_exp__h426982) : + ((_theResult___fst_exp__h417661 == 8'd0 && + sfd__h417753[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h417660) ; - assign _theResult___exp__h426812 = - sfd__h426364[24] ? - ((_theResult___fst_exp__h426345 == 8'd254) ? + _theResult___fst_exp__h417661) ; + assign _theResult___exp__h426813 = + sfd__h426365[24] ? + ((_theResult___fst_exp__h426346 == 8'd254) ? 8'd255 : - din_inc___2_exp__h427005) : - ((_theResult___fst_exp__h426345 == 8'd0 && - sfd__h426364[24:23] == 2'b01) ? + din_inc___2_exp__h427006) : + ((_theResult___fst_exp__h426346 == 8'd0 && + sfd__h426365[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h426345) ; - assign _theResult___exp__h426914 = + _theResult___fst_exp__h426346) ; + assign _theResult___exp__h426915 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426905 ; - assign _theResult___exp__h446105 = - sfd__h445681[24] ? - ((_theResult___fst_exp__h445589 == 8'd254) ? + _theResult___fst_exp__h426906 ; + assign _theResult___exp__h446106 = + sfd__h445682[24] ? + ((_theResult___fst_exp__h445590 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472622) : - ((_theResult___fst_exp__h445589 == 8'd0 && - sfd__h445681[24:23] == 2'b01) ? + din_inc___2_exp__h472623) : + ((_theResult___fst_exp__h445590 == 8'd0 && + sfd__h445682[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h445589) ; - assign _theResult___exp__h454687 = - sfd__h454263[24] ? - ((_theResult___fst_exp__h454245 == 8'd254) ? + _theResult___fst_exp__h445590) ; + assign _theResult___exp__h454688 = + sfd__h454264[24] ? + ((_theResult___fst_exp__h454246 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472646) : - ((_theResult___fst_exp__h454245 == 8'd0 && - sfd__h454263[24:23] == 2'b01) ? + din_inc___2_exp__h472647) : + ((_theResult___fst_exp__h454246 == 8'd0 && + sfd__h454264[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h454245) ; - assign _theResult___exp__h463871 = - sfd__h463447[24] ? - ((_theResult___fst_exp__h463355 == 8'd254) ? + _theResult___fst_exp__h454246) ; + assign _theResult___exp__h463872 = + sfd__h463448[24] ? + ((_theResult___fst_exp__h463356 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472676) : - ((_theResult___fst_exp__h463355 == 8'd0 && - sfd__h463447[24:23] == 2'b01) ? + din_inc___2_exp__h472677) : + ((_theResult___fst_exp__h463356 == 8'd0 && + sfd__h463448[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h463355) ; - assign _theResult___exp__h472507 = - sfd__h472059[24] ? - ((_theResult___fst_exp__h472040 == 8'd254) ? + _theResult___fst_exp__h463356) ; + assign _theResult___exp__h472508 = + sfd__h472060[24] ? + ((_theResult___fst_exp__h472041 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472700) : - ((_theResult___fst_exp__h472040 == 8'd0 && - sfd__h472059[24:23] == 2'b01) ? + din_inc___2_exp__h472701) : + ((_theResult___fst_exp__h472041 == 8'd0 && + sfd__h472060[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h472040) ; - assign _theResult___exp__h472609 = + _theResult___fst_exp__h472041) ; + assign _theResult___exp__h472610 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472600 ; - assign _theResult___exp__h502184 = - sfd__h501547[53] ? - ((_theResult___fst_exp__h501529 == 11'd2046) ? + _theResult___fst_exp__h472601 ; + assign _theResult___exp__h502185 = + sfd__h501548[53] ? + ((_theResult___fst_exp__h501530 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520779) : - ((_theResult___fst_exp__h501529 == 11'd0 && - sfd__h501547[53:52] == 2'b01) ? + din_inc___2_exp__h520780) : + ((_theResult___fst_exp__h501530 == 11'd0 && + sfd__h501548[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h501529) ; - assign _theResult___exp__h511835 = - sfd__h511198[53] ? - ((_theResult___fst_exp__h511106 == 11'd2046) ? + _theResult___fst_exp__h501530) ; + assign _theResult___exp__h511836 = + sfd__h511199[53] ? + ((_theResult___fst_exp__h511107 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520814) : - ((_theResult___fst_exp__h511106 == 11'd0 && - sfd__h511198[53:52] == 2'b01) ? + din_inc___2_exp__h520815) : + ((_theResult___fst_exp__h511107 == 11'd0 && + sfd__h511199[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h511106) ; - assign _theResult___exp__h520619 = - sfd__h519958[53] ? - ((_theResult___fst_exp__h519939 == 11'd2046) ? + _theResult___fst_exp__h511107) ; + assign _theResult___exp__h520620 = + sfd__h519959[53] ? + ((_theResult___fst_exp__h519940 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520840) : - ((_theResult___fst_exp__h519939 == 11'd0 && - sfd__h519958[53:52] == 2'b01) ? + din_inc___2_exp__h520841) : + ((_theResult___fst_exp__h519940 == 11'd0 && + sfd__h519959[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h519939) ; - assign _theResult___exp__h541037 = - sfd__h540400[53] ? - ((_theResult___fst_exp__h540382 == 11'd2046) ? + _theResult___fst_exp__h519940) ; + assign _theResult___exp__h541038 = + sfd__h540401[53] ? + ((_theResult___fst_exp__h540383 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559632) : - ((_theResult___fst_exp__h540382 == 11'd0 && - sfd__h540400[53:52] == 2'b01) ? + din_inc___2_exp__h559633) : + ((_theResult___fst_exp__h540383 == 11'd0 && + sfd__h540401[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h540382) ; - assign _theResult___exp__h550688 = - sfd__h550051[53] ? - ((_theResult___fst_exp__h549959 == 11'd2046) ? + _theResult___fst_exp__h540383) ; + assign _theResult___exp__h550689 = + sfd__h550052[53] ? + ((_theResult___fst_exp__h549960 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559667) : - ((_theResult___fst_exp__h549959 == 11'd0 && - sfd__h550051[53:52] == 2'b01) ? + din_inc___2_exp__h559668) : + ((_theResult___fst_exp__h549960 == 11'd0 && + sfd__h550052[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h549959) ; - assign _theResult___exp__h559472 = - sfd__h558811[53] ? - ((_theResult___fst_exp__h558792 == 11'd2046) ? + _theResult___fst_exp__h549960) ; + assign _theResult___exp__h559473 = + sfd__h558812[53] ? + ((_theResult___fst_exp__h558793 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559693) : - ((_theResult___fst_exp__h558792 == 11'd0 && - sfd__h558811[53:52] == 2'b01) ? + din_inc___2_exp__h559694) : + ((_theResult___fst_exp__h558793 == 11'd0 && + sfd__h558812[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h558792) ; - assign _theResult___exp__h580341 = - sfd__h579704[53] ? - ((_theResult___fst_exp__h579686 == 11'd2046) ? + _theResult___fst_exp__h558793) ; + assign _theResult___exp__h580342 = + sfd__h579705[53] ? + ((_theResult___fst_exp__h579687 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598936) : - ((_theResult___fst_exp__h579686 == 11'd0 && - sfd__h579704[53:52] == 2'b01) ? + din_inc___2_exp__h598937) : + ((_theResult___fst_exp__h579687 == 11'd0 && + sfd__h579705[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h579686) ; - assign _theResult___exp__h589992 = - sfd__h589355[53] ? - ((_theResult___fst_exp__h589263 == 11'd2046) ? + _theResult___fst_exp__h579687) ; + assign _theResult___exp__h589993 = + sfd__h589356[53] ? + ((_theResult___fst_exp__h589264 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598971) : - ((_theResult___fst_exp__h589263 == 11'd0 && - sfd__h589355[53:52] == 2'b01) ? + din_inc___2_exp__h598972) : + ((_theResult___fst_exp__h589264 == 11'd0 && + sfd__h589356[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h589263) ; - assign _theResult___exp__h598776 = - sfd__h598115[53] ? - ((_theResult___fst_exp__h598096 == 11'd2046) ? + _theResult___fst_exp__h589264) ; + assign _theResult___exp__h598777 = + sfd__h598116[53] ? + ((_theResult___fst_exp__h598097 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598997) : - ((_theResult___fst_exp__h598096 == 11'd0 && - sfd__h598115[53:52] == 2'b01) ? + din_inc___2_exp__h598998) : + ((_theResult___fst_exp__h598097 == 11'd0 && + sfd__h598116[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h598096) ; - assign _theResult___fst__h603371 = - a__h602949[63] ? a___1__h603376 : a__h602949 ; - assign _theResult___fst_exp__h354197 = - _theResult____h346086[56] ? + _theResult___fst_exp__h598097) ; + assign _theResult___fst__h603372 = + a__h602950[63] ? a___1__h603377 : a__h602950 ; + assign _theResult___fst_exp__h354198 = + _theResult____h346087[56] ? 8'd2 : - _theResult___fst_exp__h354271 ; - assign _theResult___fst_exp__h354262 = + _theResult___fst_exp__h354272 ; + assign _theResult___fst_exp__h354263 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ; - assign _theResult___fst_exp__h354268 = - (!_theResult____h346086[56] && !_theResult____h346086[55] && - !_theResult____h346086[54] && - !_theResult____h346086[53] && - !_theResult____h346086[52] && - !_theResult____h346086[51] && - !_theResult____h346086[50] && - !_theResult____h346086[49] && - !_theResult____h346086[48] && - !_theResult____h346086[47] && - !_theResult____h346086[46] && - !_theResult____h346086[45] && - !_theResult____h346086[44] && - !_theResult____h346086[43] && - !_theResult____h346086[42] && - !_theResult____h346086[41] && - !_theResult____h346086[40] && - !_theResult____h346086[39] && - !_theResult____h346086[38] && - !_theResult____h346086[37] && - !_theResult____h346086[36] && - !_theResult____h346086[35] && - !_theResult____h346086[34] && - !_theResult____h346086[33] && - !_theResult____h346086[32] && - !_theResult____h346086[31] && - !_theResult____h346086[30] && - !_theResult____h346086[29] && - !_theResult____h346086[28] && - !_theResult____h346086[27] && - !_theResult____h346086[26] && - !_theResult____h346086[25] && - !_theResult____h346086[24] && - !_theResult____h346086[23] && - !_theResult____h346086[22] && - !_theResult____h346086[21] && - !_theResult____h346086[20] && - !_theResult____h346086[19] && - !_theResult____h346086[18] && - !_theResult____h346086[17] && - !_theResult____h346086[16] && - !_theResult____h346086[15] && - !_theResult____h346086[14] && - !_theResult____h346086[13] && - !_theResult____h346086[12] && - !_theResult____h346086[11] && - !_theResult____h346086[10] && - !_theResult____h346086[9] && - !_theResult____h346086[8] && - !_theResult____h346086[7] && - !_theResult____h346086[6] && - !_theResult____h346086[5] && - !_theResult____h346086[4] && - !_theResult____h346086[3] && - !_theResult____h346086[2] && - !_theResult____h346086[1] && - !_theResult____h346086[0] || + assign _theResult___fst_exp__h354269 = + (!_theResult____h346087[56] && !_theResult____h346087[55] && + !_theResult____h346087[54] && + !_theResult____h346087[53] && + !_theResult____h346087[52] && + !_theResult____h346087[51] && + !_theResult____h346087[50] && + !_theResult____h346087[49] && + !_theResult____h346087[48] && + !_theResult____h346087[47] && + !_theResult____h346087[46] && + !_theResult____h346087[45] && + !_theResult____h346087[44] && + !_theResult____h346087[43] && + !_theResult____h346087[42] && + !_theResult____h346087[41] && + !_theResult____h346087[40] && + !_theResult____h346087[39] && + !_theResult____h346087[38] && + !_theResult____h346087[37] && + !_theResult____h346087[36] && + !_theResult____h346087[35] && + !_theResult____h346087[34] && + !_theResult____h346087[33] && + !_theResult____h346087[32] && + !_theResult____h346087[31] && + !_theResult____h346087[30] && + !_theResult____h346087[29] && + !_theResult____h346087[28] && + !_theResult____h346087[27] && + !_theResult____h346087[26] && + !_theResult____h346087[25] && + !_theResult____h346087[24] && + !_theResult____h346087[23] && + !_theResult____h346087[22] && + !_theResult____h346087[21] && + !_theResult____h346087[20] && + !_theResult____h346087[19] && + !_theResult____h346087[18] && + !_theResult____h346087[17] && + !_theResult____h346087[16] && + !_theResult____h346087[15] && + !_theResult____h346087[14] && + !_theResult____h346087[13] && + !_theResult____h346087[12] && + !_theResult____h346087[11] && + !_theResult____h346087[10] && + !_theResult____h346087[9] && + !_theResult____h346087[8] && + !_theResult____h346087[7] && + !_theResult____h346087[6] && + !_theResult____h346087[5] && + !_theResult____h346087[4] && + !_theResult____h346087[3] && + !_theResult____h346087[2] && + !_theResult____h346087[1] && + !_theResult____h346087[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249) ? 8'd0 : - _theResult___fst_exp__h354262 ; - assign _theResult___fst_exp__h354271 = - (!_theResult____h346086[56] && _theResult____h346086[55]) ? + _theResult___fst_exp__h354263 ; + assign _theResult___fst_exp__h354272 = + (!_theResult____h346087[56] && _theResult____h346087[55]) ? 8'd1 : - _theResult___fst_exp__h354268 ; - assign _theResult___fst_exp__h354794 = - (_theResult___fst_exp__h354197 == 8'd255) ? - _theResult___fst_exp__h354197 : - _theResult___fst_exp__h354791 ; - assign _theResult___fst_exp__h362844 = + _theResult___fst_exp__h354269 ; + assign _theResult___fst_exp__h354795 = + (_theResult___fst_exp__h354198 == 8'd255) ? + _theResult___fst_exp__h354198 : + _theResult___fst_exp__h354792 ; + assign _theResult___fst_exp__h362845 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h362850 = + assign _theResult___fst_exp__h362851 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480) ? 8'd0 : - _theResult___fst_exp__h362844 ; - assign _theResult___fst_exp__h362853 = + _theResult___fst_exp__h362845 ; + assign _theResult___fst_exp__h362854 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h362850 : + _theResult___fst_exp__h362851 : 8'd129 ; - assign _theResult___fst_exp__h363376 = - (_theResult___fst_exp__h362853 == 8'd255) ? - _theResult___fst_exp__h362853 : - _theResult___fst_exp__h363373 ; - assign _theResult___fst_exp__h371963 = - _theResult____h363725[56] ? + assign _theResult___fst_exp__h363377 = + (_theResult___fst_exp__h362854 == 8'd255) ? + _theResult___fst_exp__h362854 : + _theResult___fst_exp__h363374 ; + assign _theResult___fst_exp__h371964 = + _theResult____h363726[56] ? 8'd2 : - _theResult___fst_exp__h372037 ; - assign _theResult___fst_exp__h372028 = + _theResult___fst_exp__h372038 ; + assign _theResult___fst_exp__h372029 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ; - assign _theResult___fst_exp__h372034 = - (!_theResult____h363725[56] && !_theResult____h363725[55] && - !_theResult____h363725[54] && - !_theResult____h363725[53] && - !_theResult____h363725[52] && - !_theResult____h363725[51] && - !_theResult____h363725[50] && - !_theResult____h363725[49] && - !_theResult____h363725[48] && - !_theResult____h363725[47] && - !_theResult____h363725[46] && - !_theResult____h363725[45] && - !_theResult____h363725[44] && - !_theResult____h363725[43] && - !_theResult____h363725[42] && - !_theResult____h363725[41] && - !_theResult____h363725[40] && - !_theResult____h363725[39] && - !_theResult____h363725[38] && - !_theResult____h363725[37] && - !_theResult____h363725[36] && - !_theResult____h363725[35] && - !_theResult____h363725[34] && - !_theResult____h363725[33] && - !_theResult____h363725[32] && - !_theResult____h363725[31] && - !_theResult____h363725[30] && - !_theResult____h363725[29] && - !_theResult____h363725[28] && - !_theResult____h363725[27] && - !_theResult____h363725[26] && - !_theResult____h363725[25] && - !_theResult____h363725[24] && - !_theResult____h363725[23] && - !_theResult____h363725[22] && - !_theResult____h363725[21] && - !_theResult____h363725[20] && - !_theResult____h363725[19] && - !_theResult____h363725[18] && - !_theResult____h363725[17] && - !_theResult____h363725[16] && - !_theResult____h363725[15] && - !_theResult____h363725[14] && - !_theResult____h363725[13] && - !_theResult____h363725[12] && - !_theResult____h363725[11] && - !_theResult____h363725[10] && - !_theResult____h363725[9] && - !_theResult____h363725[8] && - !_theResult____h363725[7] && - !_theResult____h363725[6] && - !_theResult____h363725[5] && - !_theResult____h363725[4] && - !_theResult____h363725[3] && - !_theResult____h363725[2] && - !_theResult____h363725[1] && - !_theResult____h363725[0] || + assign _theResult___fst_exp__h372035 = + (!_theResult____h363726[56] && !_theResult____h363726[55] && + !_theResult____h363726[54] && + !_theResult____h363726[53] && + !_theResult____h363726[52] && + !_theResult____h363726[51] && + !_theResult____h363726[50] && + !_theResult____h363726[49] && + !_theResult____h363726[48] && + !_theResult____h363726[47] && + !_theResult____h363726[46] && + !_theResult____h363726[45] && + !_theResult____h363726[44] && + !_theResult____h363726[43] && + !_theResult____h363726[42] && + !_theResult____h363726[41] && + !_theResult____h363726[40] && + !_theResult____h363726[39] && + !_theResult____h363726[38] && + !_theResult____h363726[37] && + !_theResult____h363726[36] && + !_theResult____h363726[35] && + !_theResult____h363726[34] && + !_theResult____h363726[33] && + !_theResult____h363726[32] && + !_theResult____h363726[31] && + !_theResult____h363726[30] && + !_theResult____h363726[29] && + !_theResult____h363726[28] && + !_theResult____h363726[27] && + !_theResult____h363726[26] && + !_theResult____h363726[25] && + !_theResult____h363726[24] && + !_theResult____h363726[23] && + !_theResult____h363726[22] && + !_theResult____h363726[21] && + !_theResult____h363726[20] && + !_theResult____h363726[19] && + !_theResult____h363726[18] && + !_theResult____h363726[17] && + !_theResult____h363726[16] && + !_theResult____h363726[15] && + !_theResult____h363726[14] && + !_theResult____h363726[13] && + !_theResult____h363726[12] && + !_theResult____h363726[11] && + !_theResult____h363726[10] && + !_theResult____h363726[9] && + !_theResult____h363726[8] && + !_theResult____h363726[7] && + !_theResult____h363726[6] && + !_theResult____h363726[5] && + !_theResult____h363726[4] && + !_theResult____h363726[3] && + !_theResult____h363726[2] && + !_theResult____h363726[1] && + !_theResult____h363726[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800) ? 8'd0 : - _theResult___fst_exp__h372028 ; - assign _theResult___fst_exp__h372037 = - (!_theResult____h363725[56] && _theResult____h363725[55]) ? + _theResult___fst_exp__h372029 ; + assign _theResult___fst_exp__h372038 = + (!_theResult____h363726[56] && _theResult____h363726[55]) ? 8'd1 : - _theResult___fst_exp__h372034 ; - assign _theResult___fst_exp__h372560 = - (_theResult___fst_exp__h371963 == 8'd255) ? - _theResult___fst_exp__h371963 : - _theResult___fst_exp__h372557 ; - assign _theResult___fst_exp__h380600 = + _theResult___fst_exp__h372035 ; + assign _theResult___fst_exp__h372561 = + (_theResult___fst_exp__h371964 == 8'd255) ? + _theResult___fst_exp__h371964 : + _theResult___fst_exp__h372558 ; + assign _theResult___fst_exp__h380601 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ; - assign _theResult___fst_exp__h380639 = + assign _theResult___fst_exp__h380640 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h380645 = + assign _theResult___fst_exp__h380646 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873) ? 8'd0 : - _theResult___fst_exp__h380639 ; - assign _theResult___fst_exp__h380648 = + _theResult___fst_exp__h380640 ; + assign _theResult___fst_exp__h380649 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h380645 : - _theResult___fst_exp__h380600 ; - assign _theResult___fst_exp__h381196 = - (_theResult___fst_exp__h380648 == 8'd255) ? - _theResult___fst_exp__h380648 : - _theResult___fst_exp__h381193 ; - assign _theResult___fst_exp__h381205 = + _theResult___fst_exp__h380646 : + _theResult___fst_exp__h380601 ; + assign _theResult___fst_exp__h381197 = + (_theResult___fst_exp__h380649 == 8'd255) ? + _theResult___fst_exp__h380649 : + _theResult___fst_exp__h381194 ; + assign _theResult___fst_exp__h381206 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_exp__h363379 : - _theResult___fst_exp__h346068) : + _theResult___snd_fst_exp__h363380 : + _theResult___fst_exp__h346069) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_exp__h381199 : - _theResult___fst_exp__h346068) ; - assign _theResult___fst_exp__h381208 = + _theResult___snd_fst_exp__h381200 : + _theResult___fst_exp__h346069) ; + assign _theResult___fst_exp__h381209 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h381205 ; - assign _theResult___fst_exp__h399894 = - _theResult____h391785[56] ? + _theResult___fst_exp__h381206 ; + assign _theResult___fst_exp__h399895 = + _theResult____h391786[56] ? 8'd2 : - _theResult___fst_exp__h399968 ; - assign _theResult___fst_exp__h399959 = + _theResult___fst_exp__h399969 ; + assign _theResult___fst_exp__h399960 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ; - assign _theResult___fst_exp__h399965 = - (!_theResult____h391785[56] && !_theResult____h391785[55] && - !_theResult____h391785[54] && - !_theResult____h391785[53] && - !_theResult____h391785[52] && - !_theResult____h391785[51] && - !_theResult____h391785[50] && - !_theResult____h391785[49] && - !_theResult____h391785[48] && - !_theResult____h391785[47] && - !_theResult____h391785[46] && - !_theResult____h391785[45] && - !_theResult____h391785[44] && - !_theResult____h391785[43] && - !_theResult____h391785[42] && - !_theResult____h391785[41] && - !_theResult____h391785[40] && - !_theResult____h391785[39] && - !_theResult____h391785[38] && - !_theResult____h391785[37] && - !_theResult____h391785[36] && - !_theResult____h391785[35] && - !_theResult____h391785[34] && - !_theResult____h391785[33] && - !_theResult____h391785[32] && - !_theResult____h391785[31] && - !_theResult____h391785[30] && - !_theResult____h391785[29] && - !_theResult____h391785[28] && - !_theResult____h391785[27] && - !_theResult____h391785[26] && - !_theResult____h391785[25] && - !_theResult____h391785[24] && - !_theResult____h391785[23] && - !_theResult____h391785[22] && - !_theResult____h391785[21] && - !_theResult____h391785[20] && - !_theResult____h391785[19] && - !_theResult____h391785[18] && - !_theResult____h391785[17] && - !_theResult____h391785[16] && - !_theResult____h391785[15] && - !_theResult____h391785[14] && - !_theResult____h391785[13] && - !_theResult____h391785[12] && - !_theResult____h391785[11] && - !_theResult____h391785[10] && - !_theResult____h391785[9] && - !_theResult____h391785[8] && - !_theResult____h391785[7] && - !_theResult____h391785[6] && - !_theResult____h391785[5] && - !_theResult____h391785[4] && - !_theResult____h391785[3] && - !_theResult____h391785[2] && - !_theResult____h391785[1] && - !_theResult____h391785[0] || + assign _theResult___fst_exp__h399966 = + (!_theResult____h391786[56] && !_theResult____h391786[55] && + !_theResult____h391786[54] && + !_theResult____h391786[53] && + !_theResult____h391786[52] && + !_theResult____h391786[51] && + !_theResult____h391786[50] && + !_theResult____h391786[49] && + !_theResult____h391786[48] && + !_theResult____h391786[47] && + !_theResult____h391786[46] && + !_theResult____h391786[45] && + !_theResult____h391786[44] && + !_theResult____h391786[43] && + !_theResult____h391786[42] && + !_theResult____h391786[41] && + !_theResult____h391786[40] && + !_theResult____h391786[39] && + !_theResult____h391786[38] && + !_theResult____h391786[37] && + !_theResult____h391786[36] && + !_theResult____h391786[35] && + !_theResult____h391786[34] && + !_theResult____h391786[33] && + !_theResult____h391786[32] && + !_theResult____h391786[31] && + !_theResult____h391786[30] && + !_theResult____h391786[29] && + !_theResult____h391786[28] && + !_theResult____h391786[27] && + !_theResult____h391786[26] && + !_theResult____h391786[25] && + !_theResult____h391786[24] && + !_theResult____h391786[23] && + !_theResult____h391786[22] && + !_theResult____h391786[21] && + !_theResult____h391786[20] && + !_theResult____h391786[19] && + !_theResult____h391786[18] && + !_theResult____h391786[17] && + !_theResult____h391786[16] && + !_theResult____h391786[15] && + !_theResult____h391786[14] && + !_theResult____h391786[13] && + !_theResult____h391786[12] && + !_theResult____h391786[11] && + !_theResult____h391786[10] && + !_theResult____h391786[9] && + !_theResult____h391786[8] && + !_theResult____h391786[7] && + !_theResult____h391786[6] && + !_theResult____h391786[5] && + !_theResult____h391786[4] && + !_theResult____h391786[3] && + !_theResult____h391786[2] && + !_theResult____h391786[1] && + !_theResult____h391786[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641) ? 8'd0 : - _theResult___fst_exp__h399959 ; - assign _theResult___fst_exp__h399968 = - (!_theResult____h391785[56] && _theResult____h391785[55]) ? + _theResult___fst_exp__h399960 ; + assign _theResult___fst_exp__h399969 = + (!_theResult____h391786[56] && _theResult____h391786[55]) ? 8'd1 : - _theResult___fst_exp__h399965 ; - assign _theResult___fst_exp__h400491 = - (_theResult___fst_exp__h399894 == 8'd255) ? - _theResult___fst_exp__h399894 : - _theResult___fst_exp__h400488 ; - assign _theResult___fst_exp__h408541 = + _theResult___fst_exp__h399966 ; + assign _theResult___fst_exp__h400492 = + (_theResult___fst_exp__h399895 == 8'd255) ? + _theResult___fst_exp__h399895 : + _theResult___fst_exp__h400489 ; + assign _theResult___fst_exp__h408542 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h408547 = + assign _theResult___fst_exp__h408548 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872) ? 8'd0 : - _theResult___fst_exp__h408541 ; - assign _theResult___fst_exp__h408550 = + _theResult___fst_exp__h408542 ; + assign _theResult___fst_exp__h408551 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h408547 : + _theResult___fst_exp__h408548 : 8'd129 ; - assign _theResult___fst_exp__h409073 = - (_theResult___fst_exp__h408550 == 8'd255) ? - _theResult___fst_exp__h408550 : - _theResult___fst_exp__h409070 ; - assign _theResult___fst_exp__h417660 = - _theResult____h409422[56] ? + assign _theResult___fst_exp__h409074 = + (_theResult___fst_exp__h408551 == 8'd255) ? + _theResult___fst_exp__h408551 : + _theResult___fst_exp__h409071 ; + assign _theResult___fst_exp__h417661 = + _theResult____h409423[56] ? 8'd2 : - _theResult___fst_exp__h417734 ; - assign _theResult___fst_exp__h417725 = + _theResult___fst_exp__h417735 ; + assign _theResult___fst_exp__h417726 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ; - assign _theResult___fst_exp__h417731 = - (!_theResult____h409422[56] && !_theResult____h409422[55] && - !_theResult____h409422[54] && - !_theResult____h409422[53] && - !_theResult____h409422[52] && - !_theResult____h409422[51] && - !_theResult____h409422[50] && - !_theResult____h409422[49] && - !_theResult____h409422[48] && - !_theResult____h409422[47] && - !_theResult____h409422[46] && - !_theResult____h409422[45] && - !_theResult____h409422[44] && - !_theResult____h409422[43] && - !_theResult____h409422[42] && - !_theResult____h409422[41] && - !_theResult____h409422[40] && - !_theResult____h409422[39] && - !_theResult____h409422[38] && - !_theResult____h409422[37] && - !_theResult____h409422[36] && - !_theResult____h409422[35] && - !_theResult____h409422[34] && - !_theResult____h409422[33] && - !_theResult____h409422[32] && - !_theResult____h409422[31] && - !_theResult____h409422[30] && - !_theResult____h409422[29] && - !_theResult____h409422[28] && - !_theResult____h409422[27] && - !_theResult____h409422[26] && - !_theResult____h409422[25] && - !_theResult____h409422[24] && - !_theResult____h409422[23] && - !_theResult____h409422[22] && - !_theResult____h409422[21] && - !_theResult____h409422[20] && - !_theResult____h409422[19] && - !_theResult____h409422[18] && - !_theResult____h409422[17] && - !_theResult____h409422[16] && - !_theResult____h409422[15] && - !_theResult____h409422[14] && - !_theResult____h409422[13] && - !_theResult____h409422[12] && - !_theResult____h409422[11] && - !_theResult____h409422[10] && - !_theResult____h409422[9] && - !_theResult____h409422[8] && - !_theResult____h409422[7] && - !_theResult____h409422[6] && - !_theResult____h409422[5] && - !_theResult____h409422[4] && - !_theResult____h409422[3] && - !_theResult____h409422[2] && - !_theResult____h409422[1] && - !_theResult____h409422[0] || + assign _theResult___fst_exp__h417732 = + (!_theResult____h409423[56] && !_theResult____h409423[55] && + !_theResult____h409423[54] && + !_theResult____h409423[53] && + !_theResult____h409423[52] && + !_theResult____h409423[51] && + !_theResult____h409423[50] && + !_theResult____h409423[49] && + !_theResult____h409423[48] && + !_theResult____h409423[47] && + !_theResult____h409423[46] && + !_theResult____h409423[45] && + !_theResult____h409423[44] && + !_theResult____h409423[43] && + !_theResult____h409423[42] && + !_theResult____h409423[41] && + !_theResult____h409423[40] && + !_theResult____h409423[39] && + !_theResult____h409423[38] && + !_theResult____h409423[37] && + !_theResult____h409423[36] && + !_theResult____h409423[35] && + !_theResult____h409423[34] && + !_theResult____h409423[33] && + !_theResult____h409423[32] && + !_theResult____h409423[31] && + !_theResult____h409423[30] && + !_theResult____h409423[29] && + !_theResult____h409423[28] && + !_theResult____h409423[27] && + !_theResult____h409423[26] && + !_theResult____h409423[25] && + !_theResult____h409423[24] && + !_theResult____h409423[23] && + !_theResult____h409423[22] && + !_theResult____h409423[21] && + !_theResult____h409423[20] && + !_theResult____h409423[19] && + !_theResult____h409423[18] && + !_theResult____h409423[17] && + !_theResult____h409423[16] && + !_theResult____h409423[15] && + !_theResult____h409423[14] && + !_theResult____h409423[13] && + !_theResult____h409423[12] && + !_theResult____h409423[11] && + !_theResult____h409423[10] && + !_theResult____h409423[9] && + !_theResult____h409423[8] && + !_theResult____h409423[7] && + !_theResult____h409423[6] && + !_theResult____h409423[5] && + !_theResult____h409423[4] && + !_theResult____h409423[3] && + !_theResult____h409423[2] && + !_theResult____h409423[1] && + !_theResult____h409423[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192) ? 8'd0 : - _theResult___fst_exp__h417725 ; - assign _theResult___fst_exp__h417734 = - (!_theResult____h409422[56] && _theResult____h409422[55]) ? + _theResult___fst_exp__h417726 ; + assign _theResult___fst_exp__h417735 = + (!_theResult____h409423[56] && _theResult____h409423[55]) ? 8'd1 : - _theResult___fst_exp__h417731 ; - assign _theResult___fst_exp__h418257 = - (_theResult___fst_exp__h417660 == 8'd255) ? - _theResult___fst_exp__h417660 : - _theResult___fst_exp__h418254 ; - assign _theResult___fst_exp__h426297 = + _theResult___fst_exp__h417732 ; + assign _theResult___fst_exp__h418258 = + (_theResult___fst_exp__h417661 == 8'd255) ? + _theResult___fst_exp__h417661 : + _theResult___fst_exp__h418255 ; + assign _theResult___fst_exp__h426298 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ; - assign _theResult___fst_exp__h426336 = + assign _theResult___fst_exp__h426337 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h426342 = + assign _theResult___fst_exp__h426343 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265) ? 8'd0 : - _theResult___fst_exp__h426336 ; - assign _theResult___fst_exp__h426345 = + _theResult___fst_exp__h426337 ; + assign _theResult___fst_exp__h426346 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h426342 : - _theResult___fst_exp__h426297 ; - assign _theResult___fst_exp__h426893 = - (_theResult___fst_exp__h426345 == 8'd255) ? - _theResult___fst_exp__h426345 : - _theResult___fst_exp__h426890 ; - assign _theResult___fst_exp__h426902 = + _theResult___fst_exp__h426343 : + _theResult___fst_exp__h426298 ; + assign _theResult___fst_exp__h426894 = + (_theResult___fst_exp__h426346 == 8'd255) ? + _theResult___fst_exp__h426346 : + _theResult___fst_exp__h426891 ; + assign _theResult___fst_exp__h426903 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_exp__h409076 : - _theResult___fst_exp__h391767) : + _theResult___snd_fst_exp__h409077 : + _theResult___fst_exp__h391768) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_exp__h426896 : - _theResult___fst_exp__h391767) ; - assign _theResult___fst_exp__h426905 = + _theResult___snd_fst_exp__h426897 : + _theResult___fst_exp__h391768) ; + assign _theResult___fst_exp__h426906 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h426902 ; - assign _theResult___fst_exp__h445589 = - _theResult____h437480[56] ? + _theResult___fst_exp__h426903 ; + assign _theResult___fst_exp__h445590 = + _theResult____h437481[56] ? 8'd2 : - _theResult___fst_exp__h445663 ; - assign _theResult___fst_exp__h445654 = + _theResult___fst_exp__h445664 ; + assign _theResult___fst_exp__h445655 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ; - assign _theResult___fst_exp__h445660 = - (!_theResult____h437480[56] && !_theResult____h437480[55] && - !_theResult____h437480[54] && - !_theResult____h437480[53] && - !_theResult____h437480[52] && - !_theResult____h437480[51] && - !_theResult____h437480[50] && - !_theResult____h437480[49] && - !_theResult____h437480[48] && - !_theResult____h437480[47] && - !_theResult____h437480[46] && - !_theResult____h437480[45] && - !_theResult____h437480[44] && - !_theResult____h437480[43] && - !_theResult____h437480[42] && - !_theResult____h437480[41] && - !_theResult____h437480[40] && - !_theResult____h437480[39] && - !_theResult____h437480[38] && - !_theResult____h437480[37] && - !_theResult____h437480[36] && - !_theResult____h437480[35] && - !_theResult____h437480[34] && - !_theResult____h437480[33] && - !_theResult____h437480[32] && - !_theResult____h437480[31] && - !_theResult____h437480[30] && - !_theResult____h437480[29] && - !_theResult____h437480[28] && - !_theResult____h437480[27] && - !_theResult____h437480[26] && - !_theResult____h437480[25] && - !_theResult____h437480[24] && - !_theResult____h437480[23] && - !_theResult____h437480[22] && - !_theResult____h437480[21] && - !_theResult____h437480[20] && - !_theResult____h437480[19] && - !_theResult____h437480[18] && - !_theResult____h437480[17] && - !_theResult____h437480[16] && - !_theResult____h437480[15] && - !_theResult____h437480[14] && - !_theResult____h437480[13] && - !_theResult____h437480[12] && - !_theResult____h437480[11] && - !_theResult____h437480[10] && - !_theResult____h437480[9] && - !_theResult____h437480[8] && - !_theResult____h437480[7] && - !_theResult____h437480[6] && - !_theResult____h437480[5] && - !_theResult____h437480[4] && - !_theResult____h437480[3] && - !_theResult____h437480[2] && - !_theResult____h437480[1] && - !_theResult____h437480[0] || + assign _theResult___fst_exp__h445661 = + (!_theResult____h437481[56] && !_theResult____h437481[55] && + !_theResult____h437481[54] && + !_theResult____h437481[53] && + !_theResult____h437481[52] && + !_theResult____h437481[51] && + !_theResult____h437481[50] && + !_theResult____h437481[49] && + !_theResult____h437481[48] && + !_theResult____h437481[47] && + !_theResult____h437481[46] && + !_theResult____h437481[45] && + !_theResult____h437481[44] && + !_theResult____h437481[43] && + !_theResult____h437481[42] && + !_theResult____h437481[41] && + !_theResult____h437481[40] && + !_theResult____h437481[39] && + !_theResult____h437481[38] && + !_theResult____h437481[37] && + !_theResult____h437481[36] && + !_theResult____h437481[35] && + !_theResult____h437481[34] && + !_theResult____h437481[33] && + !_theResult____h437481[32] && + !_theResult____h437481[31] && + !_theResult____h437481[30] && + !_theResult____h437481[29] && + !_theResult____h437481[28] && + !_theResult____h437481[27] && + !_theResult____h437481[26] && + !_theResult____h437481[25] && + !_theResult____h437481[24] && + !_theResult____h437481[23] && + !_theResult____h437481[22] && + !_theResult____h437481[21] && + !_theResult____h437481[20] && + !_theResult____h437481[19] && + !_theResult____h437481[18] && + !_theResult____h437481[17] && + !_theResult____h437481[16] && + !_theResult____h437481[15] && + !_theResult____h437481[14] && + !_theResult____h437481[13] && + !_theResult____h437481[12] && + !_theResult____h437481[11] && + !_theResult____h437481[10] && + !_theResult____h437481[9] && + !_theResult____h437481[8] && + !_theResult____h437481[7] && + !_theResult____h437481[6] && + !_theResult____h437481[5] && + !_theResult____h437481[4] && + !_theResult____h437481[3] && + !_theResult____h437481[2] && + !_theResult____h437481[1] && + !_theResult____h437481[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033) ? 8'd0 : - _theResult___fst_exp__h445654 ; - assign _theResult___fst_exp__h445663 = - (!_theResult____h437480[56] && _theResult____h437480[55]) ? + _theResult___fst_exp__h445655 ; + assign _theResult___fst_exp__h445664 = + (!_theResult____h437481[56] && _theResult____h437481[55]) ? 8'd1 : - _theResult___fst_exp__h445660 ; - assign _theResult___fst_exp__h446186 = - (_theResult___fst_exp__h445589 == 8'd255) ? - _theResult___fst_exp__h445589 : - _theResult___fst_exp__h446183 ; - assign _theResult___fst_exp__h454236 = + _theResult___fst_exp__h445661 ; + assign _theResult___fst_exp__h446187 = + (_theResult___fst_exp__h445590 == 8'd255) ? + _theResult___fst_exp__h445590 : + _theResult___fst_exp__h446184 ; + assign _theResult___fst_exp__h454237 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h454242 = + assign _theResult___fst_exp__h454243 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264) ? 8'd0 : - _theResult___fst_exp__h454236 ; - assign _theResult___fst_exp__h454245 = + _theResult___fst_exp__h454237 ; + assign _theResult___fst_exp__h454246 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h454242 : + _theResult___fst_exp__h454243 : 8'd129 ; - assign _theResult___fst_exp__h454768 = - (_theResult___fst_exp__h454245 == 8'd255) ? - _theResult___fst_exp__h454245 : - _theResult___fst_exp__h454765 ; - assign _theResult___fst_exp__h463355 = - _theResult____h455117[56] ? + assign _theResult___fst_exp__h454769 = + (_theResult___fst_exp__h454246 == 8'd255) ? + _theResult___fst_exp__h454246 : + _theResult___fst_exp__h454766 ; + assign _theResult___fst_exp__h463356 = + _theResult____h455118[56] ? 8'd2 : - _theResult___fst_exp__h463429 ; - assign _theResult___fst_exp__h463420 = + _theResult___fst_exp__h463430 ; + assign _theResult___fst_exp__h463421 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ; - assign _theResult___fst_exp__h463426 = - (!_theResult____h455117[56] && !_theResult____h455117[55] && - !_theResult____h455117[54] && - !_theResult____h455117[53] && - !_theResult____h455117[52] && - !_theResult____h455117[51] && - !_theResult____h455117[50] && - !_theResult____h455117[49] && - !_theResult____h455117[48] && - !_theResult____h455117[47] && - !_theResult____h455117[46] && - !_theResult____h455117[45] && - !_theResult____h455117[44] && - !_theResult____h455117[43] && - !_theResult____h455117[42] && - !_theResult____h455117[41] && - !_theResult____h455117[40] && - !_theResult____h455117[39] && - !_theResult____h455117[38] && - !_theResult____h455117[37] && - !_theResult____h455117[36] && - !_theResult____h455117[35] && - !_theResult____h455117[34] && - !_theResult____h455117[33] && - !_theResult____h455117[32] && - !_theResult____h455117[31] && - !_theResult____h455117[30] && - !_theResult____h455117[29] && - !_theResult____h455117[28] && - !_theResult____h455117[27] && - !_theResult____h455117[26] && - !_theResult____h455117[25] && - !_theResult____h455117[24] && - !_theResult____h455117[23] && - !_theResult____h455117[22] && - !_theResult____h455117[21] && - !_theResult____h455117[20] && - !_theResult____h455117[19] && - !_theResult____h455117[18] && - !_theResult____h455117[17] && - !_theResult____h455117[16] && - !_theResult____h455117[15] && - !_theResult____h455117[14] && - !_theResult____h455117[13] && - !_theResult____h455117[12] && - !_theResult____h455117[11] && - !_theResult____h455117[10] && - !_theResult____h455117[9] && - !_theResult____h455117[8] && - !_theResult____h455117[7] && - !_theResult____h455117[6] && - !_theResult____h455117[5] && - !_theResult____h455117[4] && - !_theResult____h455117[3] && - !_theResult____h455117[2] && - !_theResult____h455117[1] && - !_theResult____h455117[0] || + assign _theResult___fst_exp__h463427 = + (!_theResult____h455118[56] && !_theResult____h455118[55] && + !_theResult____h455118[54] && + !_theResult____h455118[53] && + !_theResult____h455118[52] && + !_theResult____h455118[51] && + !_theResult____h455118[50] && + !_theResult____h455118[49] && + !_theResult____h455118[48] && + !_theResult____h455118[47] && + !_theResult____h455118[46] && + !_theResult____h455118[45] && + !_theResult____h455118[44] && + !_theResult____h455118[43] && + !_theResult____h455118[42] && + !_theResult____h455118[41] && + !_theResult____h455118[40] && + !_theResult____h455118[39] && + !_theResult____h455118[38] && + !_theResult____h455118[37] && + !_theResult____h455118[36] && + !_theResult____h455118[35] && + !_theResult____h455118[34] && + !_theResult____h455118[33] && + !_theResult____h455118[32] && + !_theResult____h455118[31] && + !_theResult____h455118[30] && + !_theResult____h455118[29] && + !_theResult____h455118[28] && + !_theResult____h455118[27] && + !_theResult____h455118[26] && + !_theResult____h455118[25] && + !_theResult____h455118[24] && + !_theResult____h455118[23] && + !_theResult____h455118[22] && + !_theResult____h455118[21] && + !_theResult____h455118[20] && + !_theResult____h455118[19] && + !_theResult____h455118[18] && + !_theResult____h455118[17] && + !_theResult____h455118[16] && + !_theResult____h455118[15] && + !_theResult____h455118[14] && + !_theResult____h455118[13] && + !_theResult____h455118[12] && + !_theResult____h455118[11] && + !_theResult____h455118[10] && + !_theResult____h455118[9] && + !_theResult____h455118[8] && + !_theResult____h455118[7] && + !_theResult____h455118[6] && + !_theResult____h455118[5] && + !_theResult____h455118[4] && + !_theResult____h455118[3] && + !_theResult____h455118[2] && + !_theResult____h455118[1] && + !_theResult____h455118[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584) ? 8'd0 : - _theResult___fst_exp__h463420 ; - assign _theResult___fst_exp__h463429 = - (!_theResult____h455117[56] && _theResult____h455117[55]) ? + _theResult___fst_exp__h463421 ; + assign _theResult___fst_exp__h463430 = + (!_theResult____h455118[56] && _theResult____h455118[55]) ? 8'd1 : - _theResult___fst_exp__h463426 ; - assign _theResult___fst_exp__h463952 = - (_theResult___fst_exp__h463355 == 8'd255) ? - _theResult___fst_exp__h463355 : - _theResult___fst_exp__h463949 ; - assign _theResult___fst_exp__h471992 = + _theResult___fst_exp__h463427 ; + assign _theResult___fst_exp__h463953 = + (_theResult___fst_exp__h463356 == 8'd255) ? + _theResult___fst_exp__h463356 : + _theResult___fst_exp__h463950 ; + assign _theResult___fst_exp__h471993 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ; - assign _theResult___fst_exp__h472031 = + assign _theResult___fst_exp__h472032 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h472037 = + assign _theResult___fst_exp__h472038 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657) ? 8'd0 : - _theResult___fst_exp__h472031 ; - assign _theResult___fst_exp__h472040 = + _theResult___fst_exp__h472032 ; + assign _theResult___fst_exp__h472041 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h472037 : - _theResult___fst_exp__h471992 ; - assign _theResult___fst_exp__h472588 = - (_theResult___fst_exp__h472040 == 8'd255) ? - _theResult___fst_exp__h472040 : - _theResult___fst_exp__h472585 ; - assign _theResult___fst_exp__h472597 = + _theResult___fst_exp__h472038 : + _theResult___fst_exp__h471993 ; + assign _theResult___fst_exp__h472589 = + (_theResult___fst_exp__h472041 == 8'd255) ? + _theResult___fst_exp__h472041 : + _theResult___fst_exp__h472586 ; + assign _theResult___fst_exp__h472598 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_exp__h454771 : - _theResult___fst_exp__h437462) : + _theResult___snd_fst_exp__h454772 : + _theResult___fst_exp__h437463) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_exp__h472591 : - _theResult___fst_exp__h437462) ; - assign _theResult___fst_exp__h472600 = + _theResult___snd_fst_exp__h472592 : + _theResult___fst_exp__h437463) ; + assign _theResult___fst_exp__h472601 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h472597 ; - assign _theResult___fst_exp__h486456 = + _theResult___fst_exp__h472598 ; + assign _theResult___fst_exp__h486457 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; - assign _theResult___fst_exp__h501520 = + assign _theResult___fst_exp__h501521 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h501526 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___fst_exp__h501527 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585) ? 11'd0 : - _theResult___fst_exp__h501520 ; - assign _theResult___fst_exp__h501529 = - (f1_exp__h482141 == 8'd0) ? - _theResult___fst_exp__h501526 : + _theResult___fst_exp__h501521 ; + assign _theResult___fst_exp__h501530 = + (f1_exp__h482142 == 8'd0) ? + _theResult___fst_exp__h501527 : 11'd897 ; - assign _theResult___fst_exp__h502284 = + assign _theResult___fst_exp__h502285 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 : + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 ; - assign _theResult___fst_exp__h502287 = - (_theResult___fst_exp__h501529 == 11'd2047) ? - _theResult___fst_exp__h501529 : - _theResult___fst_exp__h502284 ; - assign _theResult___fst_exp__h511106 = - _theResult____h502870[56] ? + assign _theResult___fst_exp__h502288 = + (_theResult___fst_exp__h501530 == 11'd2047) ? + _theResult___fst_exp__h501530 : + _theResult___fst_exp__h502285 ; + assign _theResult___fst_exp__h511107 = + _theResult____h502871[56] ? 11'd2 : - _theResult___fst_exp__h511180 ; - assign _theResult___fst_exp__h511171 = + _theResult___fst_exp__h511181 ; + assign _theResult___fst_exp__h511172 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ; - assign _theResult___fst_exp__h511177 = - (!_theResult____h502870[56] && !_theResult____h502870[55] && - !_theResult____h502870[54] && - !_theResult____h502870[53] && - !_theResult____h502870[52] && - !_theResult____h502870[51] && - !_theResult____h502870[50] && - !_theResult____h502870[49] && - !_theResult____h502870[48] && - !_theResult____h502870[47] && - !_theResult____h502870[46] && - !_theResult____h502870[45] && - !_theResult____h502870[44] && - !_theResult____h502870[43] && - !_theResult____h502870[42] && - !_theResult____h502870[41] && - !_theResult____h502870[40] && - !_theResult____h502870[39] && - !_theResult____h502870[38] && - !_theResult____h502870[37] && - !_theResult____h502870[36] && - !_theResult____h502870[35] && - !_theResult____h502870[34] && - !_theResult____h502870[33] && - !_theResult____h502870[32] && - !_theResult____h502870[31] && - !_theResult____h502870[30] && - !_theResult____h502870[29] && - !_theResult____h502870[28] && - !_theResult____h502870[27] && - !_theResult____h502870[26] && - !_theResult____h502870[25] && - !_theResult____h502870[24] && - !_theResult____h502870[23] && - !_theResult____h502870[22] && - !_theResult____h502870[21] && - !_theResult____h502870[20] && - !_theResult____h502870[19] && - !_theResult____h502870[18] && - !_theResult____h502870[17] && - !_theResult____h502870[16] && - !_theResult____h502870[15] && - !_theResult____h502870[14] && - !_theResult____h502870[13] && - !_theResult____h502870[12] && - !_theResult____h502870[11] && - !_theResult____h502870[10] && - !_theResult____h502870[9] && - !_theResult____h502870[8] && - !_theResult____h502870[7] && - !_theResult____h502870[6] && - !_theResult____h502870[5] && - !_theResult____h502870[4] && - !_theResult____h502870[3] && - !_theResult____h502870[2] && - !_theResult____h502870[1] && - !_theResult____h502870[0] || + assign _theResult___fst_exp__h511178 = + (!_theResult____h502871[56] && !_theResult____h502871[55] && + !_theResult____h502871[54] && + !_theResult____h502871[53] && + !_theResult____h502871[52] && + !_theResult____h502871[51] && + !_theResult____h502871[50] && + !_theResult____h502871[49] && + !_theResult____h502871[48] && + !_theResult____h502871[47] && + !_theResult____h502871[46] && + !_theResult____h502871[45] && + !_theResult____h502871[44] && + !_theResult____h502871[43] && + !_theResult____h502871[42] && + !_theResult____h502871[41] && + !_theResult____h502871[40] && + !_theResult____h502871[39] && + !_theResult____h502871[38] && + !_theResult____h502871[37] && + !_theResult____h502871[36] && + !_theResult____h502871[35] && + !_theResult____h502871[34] && + !_theResult____h502871[33] && + !_theResult____h502871[32] && + !_theResult____h502871[31] && + !_theResult____h502871[30] && + !_theResult____h502871[29] && + !_theResult____h502871[28] && + !_theResult____h502871[27] && + !_theResult____h502871[26] && + !_theResult____h502871[25] && + !_theResult____h502871[24] && + !_theResult____h502871[23] && + !_theResult____h502871[22] && + !_theResult____h502871[21] && + !_theResult____h502871[20] && + !_theResult____h502871[19] && + !_theResult____h502871[18] && + !_theResult____h502871[17] && + !_theResult____h502871[16] && + !_theResult____h502871[15] && + !_theResult____h502871[14] && + !_theResult____h502871[13] && + !_theResult____h502871[12] && + !_theResult____h502871[11] && + !_theResult____h502871[10] && + !_theResult____h502871[9] && + !_theResult____h502871[8] && + !_theResult____h502871[7] && + !_theResult____h502871[6] && + !_theResult____h502871[5] && + !_theResult____h502871[4] && + !_theResult____h502871[3] && + !_theResult____h502871[2] && + !_theResult____h502871[1] && + !_theResult____h502871[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897) ? 11'd0 : - _theResult___fst_exp__h511171 ; - assign _theResult___fst_exp__h511180 = - (!_theResult____h502870[56] && _theResult____h502870[55]) ? + _theResult___fst_exp__h511172 ; + assign _theResult___fst_exp__h511181 = + (!_theResult____h502871[56] && _theResult____h502871[55]) ? 11'd1 : - _theResult___fst_exp__h511177 ; - assign _theResult___fst_exp__h511935 = + _theResult___fst_exp__h511178 ; + assign _theResult___fst_exp__h511936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 : + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 ; - assign _theResult___fst_exp__h511938 = - (_theResult___fst_exp__h511106 == 11'd2047) ? - _theResult___fst_exp__h511106 : - _theResult___fst_exp__h511935 ; - assign _theResult___fst_exp__h519891 = + assign _theResult___fst_exp__h511939 = + (_theResult___fst_exp__h511107 == 11'd2047) ? + _theResult___fst_exp__h511107 : + _theResult___fst_exp__h511936 ; + assign _theResult___fst_exp__h519892 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h519930 = + assign _theResult___fst_exp__h519931 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h519936 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___fst_exp__h519937 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947) ? 11'd0 : - _theResult___fst_exp__h519930 ; - assign _theResult___fst_exp__h519939 = - (f1_exp__h482141 == 8'd0) ? - _theResult___fst_exp__h519936 : - _theResult___fst_exp__h519891 ; - assign _theResult___fst_exp__h520719 = + _theResult___fst_exp__h519931 ; + assign _theResult___fst_exp__h519940 = + (f1_exp__h482142 == 8'd0) ? + _theResult___fst_exp__h519937 : + _theResult___fst_exp__h519892 ; + assign _theResult___fst_exp__h520720 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 : + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 ; - assign _theResult___fst_exp__h520722 = - (_theResult___fst_exp__h519939 == 11'd2047) ? - _theResult___fst_exp__h519939 : - _theResult___fst_exp__h520719 ; - assign _theResult___fst_exp__h520731 = - (f1_exp__h482141 == 8'd0) ? + assign _theResult___fst_exp__h520723 = + (_theResult___fst_exp__h519940 == 11'd2047) ? + _theResult___fst_exp__h519940 : + _theResult___fst_exp__h520720 ; + assign _theResult___fst_exp__h520732 = + (f1_exp__h482142 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_exp__h502290 : - _theResult___fst_exp__h486456) : + _theResult___snd_fst_exp__h502291 : + _theResult___fst_exp__h486457) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_exp__h520725 : - _theResult___fst_exp__h486456) ; - assign _theResult___fst_exp__h520734 = - (f1_exp__h482141 == 8'd0 && f1_sfd__h482142 == 23'd0) ? + _theResult___snd_fst_exp__h520726 : + _theResult___fst_exp__h486457) ; + assign _theResult___fst_exp__h520735 = + (f1_exp__h482142 == 8'd0 && f1_sfd__h482143 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h520731 ; - assign _theResult___fst_exp__h525309 = + _theResult___fst_exp__h520732 ; + assign _theResult___fst_exp__h525310 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_exp__h540373 = + assign _theResult___fst_exp__h540374 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h540379 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___fst_exp__h540380 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085) ? 11'd0 : - _theResult___fst_exp__h540373 ; - assign _theResult___fst_exp__h540382 = - (f2_exp__h521135 == 8'd0) ? - _theResult___fst_exp__h540379 : + _theResult___fst_exp__h540374 ; + assign _theResult___fst_exp__h540383 = + (f2_exp__h521136 == 8'd0) ? + _theResult___fst_exp__h540380 : 11'd897 ; - assign _theResult___fst_exp__h541137 = + assign _theResult___fst_exp__h541138 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 : + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 ; - assign _theResult___fst_exp__h541140 = - (_theResult___fst_exp__h540382 == 11'd2047) ? - _theResult___fst_exp__h540382 : - _theResult___fst_exp__h541137 ; - assign _theResult___fst_exp__h549959 = - _theResult____h541723[56] ? + assign _theResult___fst_exp__h541141 = + (_theResult___fst_exp__h540383 == 11'd2047) ? + _theResult___fst_exp__h540383 : + _theResult___fst_exp__h541138 ; + assign _theResult___fst_exp__h549960 = + _theResult____h541724[56] ? 11'd2 : - _theResult___fst_exp__h550033 ; - assign _theResult___fst_exp__h550024 = + _theResult___fst_exp__h550034 ; + assign _theResult___fst_exp__h550025 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ; - assign _theResult___fst_exp__h550030 = - (!_theResult____h541723[56] && !_theResult____h541723[55] && - !_theResult____h541723[54] && - !_theResult____h541723[53] && - !_theResult____h541723[52] && - !_theResult____h541723[51] && - !_theResult____h541723[50] && - !_theResult____h541723[49] && - !_theResult____h541723[48] && - !_theResult____h541723[47] && - !_theResult____h541723[46] && - !_theResult____h541723[45] && - !_theResult____h541723[44] && - !_theResult____h541723[43] && - !_theResult____h541723[42] && - !_theResult____h541723[41] && - !_theResult____h541723[40] && - !_theResult____h541723[39] && - !_theResult____h541723[38] && - !_theResult____h541723[37] && - !_theResult____h541723[36] && - !_theResult____h541723[35] && - !_theResult____h541723[34] && - !_theResult____h541723[33] && - !_theResult____h541723[32] && - !_theResult____h541723[31] && - !_theResult____h541723[30] && - !_theResult____h541723[29] && - !_theResult____h541723[28] && - !_theResult____h541723[27] && - !_theResult____h541723[26] && - !_theResult____h541723[25] && - !_theResult____h541723[24] && - !_theResult____h541723[23] && - !_theResult____h541723[22] && - !_theResult____h541723[21] && - !_theResult____h541723[20] && - !_theResult____h541723[19] && - !_theResult____h541723[18] && - !_theResult____h541723[17] && - !_theResult____h541723[16] && - !_theResult____h541723[15] && - !_theResult____h541723[14] && - !_theResult____h541723[13] && - !_theResult____h541723[12] && - !_theResult____h541723[11] && - !_theResult____h541723[10] && - !_theResult____h541723[9] && - !_theResult____h541723[8] && - !_theResult____h541723[7] && - !_theResult____h541723[6] && - !_theResult____h541723[5] && - !_theResult____h541723[4] && - !_theResult____h541723[3] && - !_theResult____h541723[2] && - !_theResult____h541723[1] && - !_theResult____h541723[0] || + assign _theResult___fst_exp__h550031 = + (!_theResult____h541724[56] && !_theResult____h541724[55] && + !_theResult____h541724[54] && + !_theResult____h541724[53] && + !_theResult____h541724[52] && + !_theResult____h541724[51] && + !_theResult____h541724[50] && + !_theResult____h541724[49] && + !_theResult____h541724[48] && + !_theResult____h541724[47] && + !_theResult____h541724[46] && + !_theResult____h541724[45] && + !_theResult____h541724[44] && + !_theResult____h541724[43] && + !_theResult____h541724[42] && + !_theResult____h541724[41] && + !_theResult____h541724[40] && + !_theResult____h541724[39] && + !_theResult____h541724[38] && + !_theResult____h541724[37] && + !_theResult____h541724[36] && + !_theResult____h541724[35] && + !_theResult____h541724[34] && + !_theResult____h541724[33] && + !_theResult____h541724[32] && + !_theResult____h541724[31] && + !_theResult____h541724[30] && + !_theResult____h541724[29] && + !_theResult____h541724[28] && + !_theResult____h541724[27] && + !_theResult____h541724[26] && + !_theResult____h541724[25] && + !_theResult____h541724[24] && + !_theResult____h541724[23] && + !_theResult____h541724[22] && + !_theResult____h541724[21] && + !_theResult____h541724[20] && + !_theResult____h541724[19] && + !_theResult____h541724[18] && + !_theResult____h541724[17] && + !_theResult____h541724[16] && + !_theResult____h541724[15] && + !_theResult____h541724[14] && + !_theResult____h541724[13] && + !_theResult____h541724[12] && + !_theResult____h541724[11] && + !_theResult____h541724[10] && + !_theResult____h541724[9] && + !_theResult____h541724[8] && + !_theResult____h541724[7] && + !_theResult____h541724[6] && + !_theResult____h541724[5] && + !_theResult____h541724[4] && + !_theResult____h541724[3] && + !_theResult____h541724[2] && + !_theResult____h541724[1] && + !_theResult____h541724[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382) ? 11'd0 : - _theResult___fst_exp__h550024 ; - assign _theResult___fst_exp__h550033 = - (!_theResult____h541723[56] && _theResult____h541723[55]) ? + _theResult___fst_exp__h550025 ; + assign _theResult___fst_exp__h550034 = + (!_theResult____h541724[56] && _theResult____h541724[55]) ? 11'd1 : - _theResult___fst_exp__h550030 ; - assign _theResult___fst_exp__h550788 = + _theResult___fst_exp__h550031 ; + assign _theResult___fst_exp__h550789 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 : + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 ; - assign _theResult___fst_exp__h550791 = - (_theResult___fst_exp__h549959 == 11'd2047) ? - _theResult___fst_exp__h549959 : - _theResult___fst_exp__h550788 ; - assign _theResult___fst_exp__h558744 = + assign _theResult___fst_exp__h550792 = + (_theResult___fst_exp__h549960 == 11'd2047) ? + _theResult___fst_exp__h549960 : + _theResult___fst_exp__h550789 ; + assign _theResult___fst_exp__h558745 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h558783 = + assign _theResult___fst_exp__h558784 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h558789 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___fst_exp__h558790 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432) ? 11'd0 : - _theResult___fst_exp__h558783 ; - assign _theResult___fst_exp__h558792 = - (f2_exp__h521135 == 8'd0) ? - _theResult___fst_exp__h558789 : - _theResult___fst_exp__h558744 ; - assign _theResult___fst_exp__h559572 = + _theResult___fst_exp__h558784 ; + assign _theResult___fst_exp__h558793 = + (f2_exp__h521136 == 8'd0) ? + _theResult___fst_exp__h558790 : + _theResult___fst_exp__h558745 ; + assign _theResult___fst_exp__h559573 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 : + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ; - assign _theResult___fst_exp__h559575 = - (_theResult___fst_exp__h558792 == 11'd2047) ? - _theResult___fst_exp__h558792 : - _theResult___fst_exp__h559572 ; - assign _theResult___fst_exp__h559584 = - (f2_exp__h521135 == 8'd0) ? + assign _theResult___fst_exp__h559576 = + (_theResult___fst_exp__h558793 == 11'd2047) ? + _theResult___fst_exp__h558793 : + _theResult___fst_exp__h559573 ; + assign _theResult___fst_exp__h559585 = + (f2_exp__h521136 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_exp__h541143 : - _theResult___fst_exp__h525309) : + _theResult___snd_fst_exp__h541144 : + _theResult___fst_exp__h525310) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_exp__h559578 : - _theResult___fst_exp__h525309) ; - assign _theResult___fst_exp__h559587 = - (f2_exp__h521135 == 8'd0 && f2_sfd__h521136 == 23'd0) ? + _theResult___snd_fst_exp__h559579 : + _theResult___fst_exp__h525310) ; + assign _theResult___fst_exp__h559588 = + (f2_exp__h521136 == 8'd0 && f2_sfd__h521137 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h559584 ; - assign _theResult___fst_exp__h564613 = + _theResult___fst_exp__h559585 ; + assign _theResult___fst_exp__h564614 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_exp__h579677 = + assign _theResult___fst_exp__h579678 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h579683 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___fst_exp__h579684 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315) ? 11'd0 : - _theResult___fst_exp__h579677 ; - assign _theResult___fst_exp__h579686 = - (f3_exp__h560439 == 8'd0) ? - _theResult___fst_exp__h579683 : + _theResult___fst_exp__h579678 ; + assign _theResult___fst_exp__h579687 = + (f3_exp__h560440 == 8'd0) ? + _theResult___fst_exp__h579684 : 11'd897 ; - assign _theResult___fst_exp__h580441 = + assign _theResult___fst_exp__h580442 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 : + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 ; - assign _theResult___fst_exp__h580444 = - (_theResult___fst_exp__h579686 == 11'd2047) ? - _theResult___fst_exp__h579686 : - _theResult___fst_exp__h580441 ; - assign _theResult___fst_exp__h589263 = - _theResult____h581027[56] ? + assign _theResult___fst_exp__h580445 = + (_theResult___fst_exp__h579687 == 11'd2047) ? + _theResult___fst_exp__h579687 : + _theResult___fst_exp__h580442 ; + assign _theResult___fst_exp__h589264 = + _theResult____h581028[56] ? 11'd2 : - _theResult___fst_exp__h589337 ; - assign _theResult___fst_exp__h589328 = + _theResult___fst_exp__h589338 ; + assign _theResult___fst_exp__h589329 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ; - assign _theResult___fst_exp__h589334 = - (!_theResult____h581027[56] && !_theResult____h581027[55] && - !_theResult____h581027[54] && - !_theResult____h581027[53] && - !_theResult____h581027[52] && - !_theResult____h581027[51] && - !_theResult____h581027[50] && - !_theResult____h581027[49] && - !_theResult____h581027[48] && - !_theResult____h581027[47] && - !_theResult____h581027[46] && - !_theResult____h581027[45] && - !_theResult____h581027[44] && - !_theResult____h581027[43] && - !_theResult____h581027[42] && - !_theResult____h581027[41] && - !_theResult____h581027[40] && - !_theResult____h581027[39] && - !_theResult____h581027[38] && - !_theResult____h581027[37] && - !_theResult____h581027[36] && - !_theResult____h581027[35] && - !_theResult____h581027[34] && - !_theResult____h581027[33] && - !_theResult____h581027[32] && - !_theResult____h581027[31] && - !_theResult____h581027[30] && - !_theResult____h581027[29] && - !_theResult____h581027[28] && - !_theResult____h581027[27] && - !_theResult____h581027[26] && - !_theResult____h581027[25] && - !_theResult____h581027[24] && - !_theResult____h581027[23] && - !_theResult____h581027[22] && - !_theResult____h581027[21] && - !_theResult____h581027[20] && - !_theResult____h581027[19] && - !_theResult____h581027[18] && - !_theResult____h581027[17] && - !_theResult____h581027[16] && - !_theResult____h581027[15] && - !_theResult____h581027[14] && - !_theResult____h581027[13] && - !_theResult____h581027[12] && - !_theResult____h581027[11] && - !_theResult____h581027[10] && - !_theResult____h581027[9] && - !_theResult____h581027[8] && - !_theResult____h581027[7] && - !_theResult____h581027[6] && - !_theResult____h581027[5] && - !_theResult____h581027[4] && - !_theResult____h581027[3] && - !_theResult____h581027[2] && - !_theResult____h581027[1] && - !_theResult____h581027[0] || + assign _theResult___fst_exp__h589335 = + (!_theResult____h581028[56] && !_theResult____h581028[55] && + !_theResult____h581028[54] && + !_theResult____h581028[53] && + !_theResult____h581028[52] && + !_theResult____h581028[51] && + !_theResult____h581028[50] && + !_theResult____h581028[49] && + !_theResult____h581028[48] && + !_theResult____h581028[47] && + !_theResult____h581028[46] && + !_theResult____h581028[45] && + !_theResult____h581028[44] && + !_theResult____h581028[43] && + !_theResult____h581028[42] && + !_theResult____h581028[41] && + !_theResult____h581028[40] && + !_theResult____h581028[39] && + !_theResult____h581028[38] && + !_theResult____h581028[37] && + !_theResult____h581028[36] && + !_theResult____h581028[35] && + !_theResult____h581028[34] && + !_theResult____h581028[33] && + !_theResult____h581028[32] && + !_theResult____h581028[31] && + !_theResult____h581028[30] && + !_theResult____h581028[29] && + !_theResult____h581028[28] && + !_theResult____h581028[27] && + !_theResult____h581028[26] && + !_theResult____h581028[25] && + !_theResult____h581028[24] && + !_theResult____h581028[23] && + !_theResult____h581028[22] && + !_theResult____h581028[21] && + !_theResult____h581028[20] && + !_theResult____h581028[19] && + !_theResult____h581028[18] && + !_theResult____h581028[17] && + !_theResult____h581028[16] && + !_theResult____h581028[15] && + !_theResult____h581028[14] && + !_theResult____h581028[13] && + !_theResult____h581028[12] && + !_theResult____h581028[11] && + !_theResult____h581028[10] && + !_theResult____h581028[9] && + !_theResult____h581028[8] && + !_theResult____h581028[7] && + !_theResult____h581028[6] && + !_theResult____h581028[5] && + !_theResult____h581028[4] && + !_theResult____h581028[3] && + !_theResult____h581028[2] && + !_theResult____h581028[1] && + !_theResult____h581028[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612) ? 11'd0 : - _theResult___fst_exp__h589328 ; - assign _theResult___fst_exp__h589337 = - (!_theResult____h581027[56] && _theResult____h581027[55]) ? + _theResult___fst_exp__h589329 ; + assign _theResult___fst_exp__h589338 = + (!_theResult____h581028[56] && _theResult____h581028[55]) ? 11'd1 : - _theResult___fst_exp__h589334 ; - assign _theResult___fst_exp__h590092 = + _theResult___fst_exp__h589335 ; + assign _theResult___fst_exp__h590093 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 : + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ; - assign _theResult___fst_exp__h590095 = - (_theResult___fst_exp__h589263 == 11'd2047) ? - _theResult___fst_exp__h589263 : - _theResult___fst_exp__h590092 ; - assign _theResult___fst_exp__h598048 = + assign _theResult___fst_exp__h590096 = + (_theResult___fst_exp__h589264 == 11'd2047) ? + _theResult___fst_exp__h589264 : + _theResult___fst_exp__h590093 ; + assign _theResult___fst_exp__h598049 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h598087 = + assign _theResult___fst_exp__h598088 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h598093 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___fst_exp__h598094 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662) ? 11'd0 : - _theResult___fst_exp__h598087 ; - assign _theResult___fst_exp__h598096 = - (f3_exp__h560439 == 8'd0) ? - _theResult___fst_exp__h598093 : - _theResult___fst_exp__h598048 ; - assign _theResult___fst_exp__h598876 = + _theResult___fst_exp__h598088 ; + assign _theResult___fst_exp__h598097 = + (f3_exp__h560440 == 8'd0) ? + _theResult___fst_exp__h598094 : + _theResult___fst_exp__h598049 ; + assign _theResult___fst_exp__h598877 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 : + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; - assign _theResult___fst_exp__h598879 = - (_theResult___fst_exp__h598096 == 11'd2047) ? - _theResult___fst_exp__h598096 : - _theResult___fst_exp__h598876 ; - assign _theResult___fst_exp__h598888 = - (f3_exp__h560439 == 8'd0) ? + assign _theResult___fst_exp__h598880 = + (_theResult___fst_exp__h598097 == 11'd2047) ? + _theResult___fst_exp__h598097 : + _theResult___fst_exp__h598877 ; + assign _theResult___fst_exp__h598889 = + (f3_exp__h560440 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_exp__h580447 : - _theResult___fst_exp__h564613) : + _theResult___snd_fst_exp__h580448 : + _theResult___fst_exp__h564614) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_exp__h598882 : - _theResult___fst_exp__h564613) ; - assign _theResult___fst_exp__h598891 = - (f3_exp__h560439 == 8'd0 && f3_sfd__h560440 == 23'd0) ? + _theResult___snd_fst_exp__h598883 : + _theResult___fst_exp__h564614) ; + assign _theResult___fst_exp__h598892 = + (f3_exp__h560440 == 8'd0 && f3_sfd__h560441 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h598888 ; - assign _theResult___fst_sfd__h354795 = - (_theResult___fst_exp__h354197 == 8'd255) ? - sfdin__h354191[56:34] : - _theResult___fst_sfd__h354792 ; - assign _theResult___fst_sfd__h363377 = - (_theResult___fst_exp__h362853 == 8'd255) ? - _theResult___snd__h362804[56:34] : - _theResult___fst_sfd__h363374 ; - assign _theResult___fst_sfd__h372561 = - (_theResult___fst_exp__h371963 == 8'd255) ? - sfdin__h371957[56:34] : - _theResult___fst_sfd__h372558 ; - assign _theResult___fst_sfd__h381197 = - (_theResult___fst_exp__h380648 == 8'd255) ? - _theResult___snd__h380594[56:34] : - _theResult___fst_sfd__h381194 ; - assign _theResult___fst_sfd__h381206 = + _theResult___fst_exp__h598889 ; + assign _theResult___fst_sfd__h354796 = + (_theResult___fst_exp__h354198 == 8'd255) ? + sfdin__h354192[56:34] : + _theResult___fst_sfd__h354793 ; + assign _theResult___fst_sfd__h363378 = + (_theResult___fst_exp__h362854 == 8'd255) ? + _theResult___snd__h362805[56:34] : + _theResult___fst_sfd__h363375 ; + assign _theResult___fst_sfd__h372562 = + (_theResult___fst_exp__h371964 == 8'd255) ? + sfdin__h371958[56:34] : + _theResult___fst_sfd__h372559 ; + assign _theResult___fst_sfd__h381198 = + (_theResult___fst_exp__h380649 == 8'd255) ? + _theResult___snd__h380595[56:34] : + _theResult___fst_sfd__h381195 ; + assign _theResult___fst_sfd__h381207 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_sfd__h363380 : - _theResult___fst_sfd__h346069) : + _theResult___snd_fst_sfd__h363381 : + _theResult___fst_sfd__h346070) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_sfd__h381200 : - _theResult___fst_sfd__h346069) ; - assign _theResult___fst_sfd__h381212 = + _theResult___snd_fst_sfd__h381201 : + _theResult___fst_sfd__h346070) ; + assign _theResult___fst_sfd__h381213 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -28203,33 +28203,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h381206 ; - assign _theResult___fst_sfd__h400492 = - (_theResult___fst_exp__h399894 == 8'd255) ? - sfdin__h399888[56:34] : - _theResult___fst_sfd__h400489 ; - assign _theResult___fst_sfd__h409074 = - (_theResult___fst_exp__h408550 == 8'd255) ? - _theResult___snd__h408501[56:34] : - _theResult___fst_sfd__h409071 ; - assign _theResult___fst_sfd__h418258 = - (_theResult___fst_exp__h417660 == 8'd255) ? - sfdin__h417654[56:34] : - _theResult___fst_sfd__h418255 ; - assign _theResult___fst_sfd__h426894 = - (_theResult___fst_exp__h426345 == 8'd255) ? - _theResult___snd__h426291[56:34] : - _theResult___fst_sfd__h426891 ; - assign _theResult___fst_sfd__h426903 = + _theResult___fst_sfd__h381207 ; + assign _theResult___fst_sfd__h400493 = + (_theResult___fst_exp__h399895 == 8'd255) ? + sfdin__h399889[56:34] : + _theResult___fst_sfd__h400490 ; + assign _theResult___fst_sfd__h409075 = + (_theResult___fst_exp__h408551 == 8'd255) ? + _theResult___snd__h408502[56:34] : + _theResult___fst_sfd__h409072 ; + assign _theResult___fst_sfd__h418259 = + (_theResult___fst_exp__h417661 == 8'd255) ? + sfdin__h417655[56:34] : + _theResult___fst_sfd__h418256 ; + assign _theResult___fst_sfd__h426895 = + (_theResult___fst_exp__h426346 == 8'd255) ? + _theResult___snd__h426292[56:34] : + _theResult___fst_sfd__h426892 ; + assign _theResult___fst_sfd__h426904 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_sfd__h409077 : - _theResult___fst_sfd__h391768) : + _theResult___snd_fst_sfd__h409078 : + _theResult___fst_sfd__h391769) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_sfd__h426897 : - _theResult___fst_sfd__h391768) ; - assign _theResult___fst_sfd__h426909 = + _theResult___snd_fst_sfd__h426898 : + _theResult___fst_sfd__h391769) ; + assign _theResult___fst_sfd__h426910 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -28237,33 +28237,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h426903 ; - assign _theResult___fst_sfd__h446187 = - (_theResult___fst_exp__h445589 == 8'd255) ? - sfdin__h445583[56:34] : - _theResult___fst_sfd__h446184 ; - assign _theResult___fst_sfd__h454769 = - (_theResult___fst_exp__h454245 == 8'd255) ? - _theResult___snd__h454196[56:34] : - _theResult___fst_sfd__h454766 ; - assign _theResult___fst_sfd__h463953 = - (_theResult___fst_exp__h463355 == 8'd255) ? - sfdin__h463349[56:34] : - _theResult___fst_sfd__h463950 ; - assign _theResult___fst_sfd__h472589 = - (_theResult___fst_exp__h472040 == 8'd255) ? - _theResult___snd__h471986[56:34] : - _theResult___fst_sfd__h472586 ; - assign _theResult___fst_sfd__h472598 = + _theResult___fst_sfd__h426904 ; + assign _theResult___fst_sfd__h446188 = + (_theResult___fst_exp__h445590 == 8'd255) ? + sfdin__h445584[56:34] : + _theResult___fst_sfd__h446185 ; + assign _theResult___fst_sfd__h454770 = + (_theResult___fst_exp__h454246 == 8'd255) ? + _theResult___snd__h454197[56:34] : + _theResult___fst_sfd__h454767 ; + assign _theResult___fst_sfd__h463954 = + (_theResult___fst_exp__h463356 == 8'd255) ? + sfdin__h463350[56:34] : + _theResult___fst_sfd__h463951 ; + assign _theResult___fst_sfd__h472590 = + (_theResult___fst_exp__h472041 == 8'd255) ? + _theResult___snd__h471987[56:34] : + _theResult___fst_sfd__h472587 ; + assign _theResult___fst_sfd__h472599 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_sfd__h454772 : - _theResult___fst_sfd__h437463) : + _theResult___snd_fst_sfd__h454773 : + _theResult___fst_sfd__h437464) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_sfd__h472592 : - _theResult___fst_sfd__h437463) ; - assign _theResult___fst_sfd__h472604 = + _theResult___snd_fst_sfd__h472593 : + _theResult___fst_sfd__h437464) ; + assign _theResult___fst_sfd__h472605 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -28271,1308 +28271,1308 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h472598 ; - assign _theResult___fst_sfd__h486457 = + _theResult___fst_sfd__h472599 ; + assign _theResult___fst_sfd__h486458 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_sfd__h502285 = + assign _theResult___fst_sfd__h502286 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 : + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; - assign _theResult___fst_sfd__h502288 = - (_theResult___fst_exp__h501529 == 11'd2047) ? - _theResult___snd__h501480[56:5] : - _theResult___fst_sfd__h502285 ; - assign _theResult___fst_sfd__h511936 = + assign _theResult___fst_sfd__h502289 = + (_theResult___fst_exp__h501530 == 11'd2047) ? + _theResult___snd__h501481[56:5] : + _theResult___fst_sfd__h502286 ; + assign _theResult___fst_sfd__h511937 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; - assign _theResult___fst_sfd__h511939 = - (_theResult___fst_exp__h511106 == 11'd2047) ? - sfdin__h511100[56:5] : - _theResult___fst_sfd__h511936 ; - assign _theResult___fst_sfd__h520720 = + assign _theResult___fst_sfd__h511940 = + (_theResult___fst_exp__h511107 == 11'd2047) ? + sfdin__h511101[56:5] : + _theResult___fst_sfd__h511937 ; + assign _theResult___fst_sfd__h520721 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 : + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; - assign _theResult___fst_sfd__h520723 = - (_theResult___fst_exp__h519939 == 11'd2047) ? - _theResult___snd__h519885[56:5] : - _theResult___fst_sfd__h520720 ; - assign _theResult___fst_sfd__h520732 = - (f1_exp__h482141 == 8'd0) ? + assign _theResult___fst_sfd__h520724 = + (_theResult___fst_exp__h519940 == 11'd2047) ? + _theResult___snd__h519886[56:5] : + _theResult___fst_sfd__h520721 ; + assign _theResult___fst_sfd__h520733 = + (f1_exp__h482142 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_sfd__h502291 : - _theResult___fst_sfd__h486457) : + _theResult___snd_fst_sfd__h502292 : + _theResult___fst_sfd__h486458) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_sfd__h520726 : - _theResult___fst_sfd__h486457) ; - assign _theResult___fst_sfd__h520738 = - ((f1_exp__h482141 == 8'd255 || f1_exp__h482141 == 8'd0) && - f1_sfd__h482142 == 23'd0) ? + _theResult___snd_fst_sfd__h520727 : + _theResult___fst_sfd__h486458) ; + assign _theResult___fst_sfd__h520739 = + ((f1_exp__h482142 == 8'd255 || f1_exp__h482142 == 8'd0) && + f1_sfd__h482143 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h520732 ; - assign _theResult___fst_sfd__h525310 = + _theResult___fst_sfd__h520733 ; + assign _theResult___fst_sfd__h525311 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_sfd__h541138 = + assign _theResult___fst_sfd__h541139 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 : + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 ; - assign _theResult___fst_sfd__h541141 = - (_theResult___fst_exp__h540382 == 11'd2047) ? - _theResult___snd__h540333[56:5] : - _theResult___fst_sfd__h541138 ; - assign _theResult___fst_sfd__h550789 = + assign _theResult___fst_sfd__h541142 = + (_theResult___fst_exp__h540383 == 11'd2047) ? + _theResult___snd__h540334[56:5] : + _theResult___fst_sfd__h541139 ; + assign _theResult___fst_sfd__h550790 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; - assign _theResult___fst_sfd__h550792 = - (_theResult___fst_exp__h549959 == 11'd2047) ? - sfdin__h549953[56:5] : - _theResult___fst_sfd__h550789 ; - assign _theResult___fst_sfd__h559573 = + assign _theResult___fst_sfd__h550793 = + (_theResult___fst_exp__h549960 == 11'd2047) ? + sfdin__h549954[56:5] : + _theResult___fst_sfd__h550790 ; + assign _theResult___fst_sfd__h559574 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 : + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; - assign _theResult___fst_sfd__h559576 = - (_theResult___fst_exp__h558792 == 11'd2047) ? - _theResult___snd__h558738[56:5] : - _theResult___fst_sfd__h559573 ; - assign _theResult___fst_sfd__h559585 = - (f2_exp__h521135 == 8'd0) ? + assign _theResult___fst_sfd__h559577 = + (_theResult___fst_exp__h558793 == 11'd2047) ? + _theResult___snd__h558739[56:5] : + _theResult___fst_sfd__h559574 ; + assign _theResult___fst_sfd__h559586 = + (f2_exp__h521136 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_sfd__h541144 : - _theResult___fst_sfd__h525310) : + _theResult___snd_fst_sfd__h541145 : + _theResult___fst_sfd__h525311) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_sfd__h559579 : - _theResult___fst_sfd__h525310) ; - assign _theResult___fst_sfd__h559591 = - ((f2_exp__h521135 == 8'd255 || f2_exp__h521135 == 8'd0) && - f2_sfd__h521136 == 23'd0) ? + _theResult___snd_fst_sfd__h559580 : + _theResult___fst_sfd__h525311) ; + assign _theResult___fst_sfd__h559592 = + ((f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) && + f2_sfd__h521137 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h559585 ; - assign _theResult___fst_sfd__h564614 = + _theResult___fst_sfd__h559586 ; + assign _theResult___fst_sfd__h564615 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_sfd__h580442 = + assign _theResult___fst_sfd__h580443 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 : + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 ; - assign _theResult___fst_sfd__h580445 = - (_theResult___fst_exp__h579686 == 11'd2047) ? - _theResult___snd__h579637[56:5] : - _theResult___fst_sfd__h580442 ; - assign _theResult___fst_sfd__h590093 = + assign _theResult___fst_sfd__h580446 = + (_theResult___fst_exp__h579687 == 11'd2047) ? + _theResult___snd__h579638[56:5] : + _theResult___fst_sfd__h580443 ; + assign _theResult___fst_sfd__h590094 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 ; - assign _theResult___fst_sfd__h590096 = - (_theResult___fst_exp__h589263 == 11'd2047) ? - sfdin__h589257[56:5] : - _theResult___fst_sfd__h590093 ; - assign _theResult___fst_sfd__h598877 = + assign _theResult___fst_sfd__h590097 = + (_theResult___fst_exp__h589264 == 11'd2047) ? + sfdin__h589258[56:5] : + _theResult___fst_sfd__h590094 ; + assign _theResult___fst_sfd__h598878 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 : + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 ; - assign _theResult___fst_sfd__h598880 = - (_theResult___fst_exp__h598096 == 11'd2047) ? - _theResult___snd__h598042[56:5] : - _theResult___fst_sfd__h598877 ; - assign _theResult___fst_sfd__h598889 = - (f3_exp__h560439 == 8'd0) ? + assign _theResult___fst_sfd__h598881 = + (_theResult___fst_exp__h598097 == 11'd2047) ? + _theResult___snd__h598043[56:5] : + _theResult___fst_sfd__h598878 ; + assign _theResult___fst_sfd__h598890 = + (f3_exp__h560440 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_sfd__h580448 : - _theResult___fst_sfd__h564614) : + _theResult___snd_fst_sfd__h580449 : + _theResult___fst_sfd__h564615) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_sfd__h598883 : - _theResult___fst_sfd__h564614) ; - assign _theResult___fst_sfd__h598895 = - ((f3_exp__h560439 == 8'd255 || f3_exp__h560439 == 8'd0) && - f3_sfd__h560440 == 23'd0) ? + _theResult___snd_fst_sfd__h598884 : + _theResult___fst_sfd__h564615) ; + assign _theResult___fst_sfd__h598896 = + ((f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) && + f3_sfd__h560441 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h598889 ; - assign _theResult___sfd__h354714 = - sfd__h354289[24] ? - ((_theResult___fst_exp__h354197 == 8'd254) ? + _theResult___fst_sfd__h598890 ; + assign _theResult___sfd__h354715 = + sfd__h354290[24] ? + ((_theResult___fst_exp__h354198 == 8'd254) ? 23'd0 : - sfd__h354289[23:1]) : - sfd__h354289[22:0] ; - assign _theResult___sfd__h363296 = - sfd__h362871[24] ? - ((_theResult___fst_exp__h362853 == 8'd254) ? + sfd__h354290[23:1]) : + sfd__h354290[22:0] ; + assign _theResult___sfd__h363297 = + sfd__h362872[24] ? + ((_theResult___fst_exp__h362854 == 8'd254) ? 23'd0 : - sfd__h362871[23:1]) : - sfd__h362871[22:0] ; - assign _theResult___sfd__h372480 = - sfd__h372055[24] ? - ((_theResult___fst_exp__h371963 == 8'd254) ? + sfd__h362872[23:1]) : + sfd__h362872[22:0] ; + assign _theResult___sfd__h372481 = + sfd__h372056[24] ? + ((_theResult___fst_exp__h371964 == 8'd254) ? 23'd0 : - sfd__h372055[23:1]) : - sfd__h372055[22:0] ; - assign _theResult___sfd__h381116 = - sfd__h380667[24] ? - ((_theResult___fst_exp__h380648 == 8'd254) ? + sfd__h372056[23:1]) : + sfd__h372056[22:0] ; + assign _theResult___sfd__h381117 = + sfd__h380668[24] ? + ((_theResult___fst_exp__h380649 == 8'd254) ? 23'd0 : - sfd__h380667[23:1]) : - sfd__h380667[22:0] ; - assign _theResult___sfd__h381218 = + sfd__h380668[23:1]) : + sfd__h380668[22:0] ; + assign _theResult___sfd__h381219 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h338431 : - _theResult___fst_sfd__h381212 ; - assign _theResult___sfd__h400411 = - sfd__h399986[24] ? - ((_theResult___fst_exp__h399894 == 8'd254) ? + _theResult___snd_fst_sfd__h338432 : + _theResult___fst_sfd__h381213 ; + assign _theResult___sfd__h400412 = + sfd__h399987[24] ? + ((_theResult___fst_exp__h399895 == 8'd254) ? 23'd0 : - sfd__h399986[23:1]) : - sfd__h399986[22:0] ; - assign _theResult___sfd__h408993 = - sfd__h408568[24] ? - ((_theResult___fst_exp__h408550 == 8'd254) ? + sfd__h399987[23:1]) : + sfd__h399987[22:0] ; + assign _theResult___sfd__h408994 = + sfd__h408569[24] ? + ((_theResult___fst_exp__h408551 == 8'd254) ? 23'd0 : - sfd__h408568[23:1]) : - sfd__h408568[22:0] ; - assign _theResult___sfd__h418177 = - sfd__h417752[24] ? - ((_theResult___fst_exp__h417660 == 8'd254) ? + sfd__h408569[23:1]) : + sfd__h408569[22:0] ; + assign _theResult___sfd__h418178 = + sfd__h417753[24] ? + ((_theResult___fst_exp__h417661 == 8'd254) ? 23'd0 : - sfd__h417752[23:1]) : - sfd__h417752[22:0] ; - assign _theResult___sfd__h426813 = - sfd__h426364[24] ? - ((_theResult___fst_exp__h426345 == 8'd254) ? + sfd__h417753[23:1]) : + sfd__h417753[22:0] ; + assign _theResult___sfd__h426814 = + sfd__h426365[24] ? + ((_theResult___fst_exp__h426346 == 8'd254) ? 23'd0 : - sfd__h426364[23:1]) : - sfd__h426364[22:0] ; - assign _theResult___sfd__h426915 = + sfd__h426365[23:1]) : + sfd__h426365[22:0] ; + assign _theResult___sfd__h426916 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h384133 : - _theResult___fst_sfd__h426909 ; - assign _theResult___sfd__h446106 = - sfd__h445681[24] ? - ((_theResult___fst_exp__h445589 == 8'd254) ? + _theResult___snd_fst_sfd__h384134 : + _theResult___fst_sfd__h426910 ; + assign _theResult___sfd__h446107 = + sfd__h445682[24] ? + ((_theResult___fst_exp__h445590 == 8'd254) ? 23'd0 : - sfd__h445681[23:1]) : - sfd__h445681[22:0] ; - assign _theResult___sfd__h454688 = - sfd__h454263[24] ? - ((_theResult___fst_exp__h454245 == 8'd254) ? + sfd__h445682[23:1]) : + sfd__h445682[22:0] ; + assign _theResult___sfd__h454689 = + sfd__h454264[24] ? + ((_theResult___fst_exp__h454246 == 8'd254) ? 23'd0 : - sfd__h454263[23:1]) : - sfd__h454263[22:0] ; - assign _theResult___sfd__h463872 = - sfd__h463447[24] ? - ((_theResult___fst_exp__h463355 == 8'd254) ? + sfd__h454264[23:1]) : + sfd__h454264[22:0] ; + assign _theResult___sfd__h463873 = + sfd__h463448[24] ? + ((_theResult___fst_exp__h463356 == 8'd254) ? 23'd0 : - sfd__h463447[23:1]) : - sfd__h463447[22:0] ; - assign _theResult___sfd__h472508 = - sfd__h472059[24] ? - ((_theResult___fst_exp__h472040 == 8'd254) ? + sfd__h463448[23:1]) : + sfd__h463448[22:0] ; + assign _theResult___sfd__h472509 = + sfd__h472060[24] ? + ((_theResult___fst_exp__h472041 == 8'd254) ? 23'd0 : - sfd__h472059[23:1]) : - sfd__h472059[22:0] ; - assign _theResult___sfd__h472610 = + sfd__h472060[23:1]) : + sfd__h472060[22:0] ; + assign _theResult___sfd__h472611 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h429828 : - _theResult___fst_sfd__h472604 ; - assign _theResult___sfd__h502185 = - sfd__h501547[53] ? - ((_theResult___fst_exp__h501529 == 11'd2046) ? + _theResult___snd_fst_sfd__h429829 : + _theResult___fst_sfd__h472605 ; + assign _theResult___sfd__h502186 = + sfd__h501548[53] ? + ((_theResult___fst_exp__h501530 == 11'd2046) ? 52'd0 : - sfd__h501547[52:1]) : - sfd__h501547[51:0] ; - assign _theResult___sfd__h511836 = - sfd__h511198[53] ? - ((_theResult___fst_exp__h511106 == 11'd2046) ? + sfd__h501548[52:1]) : + sfd__h501548[51:0] ; + assign _theResult___sfd__h511837 = + sfd__h511199[53] ? + ((_theResult___fst_exp__h511107 == 11'd2046) ? 52'd0 : - sfd__h511198[52:1]) : - sfd__h511198[51:0] ; - assign _theResult___sfd__h520620 = - sfd__h519958[53] ? - ((_theResult___fst_exp__h519939 == 11'd2046) ? + sfd__h511199[52:1]) : + sfd__h511199[51:0] ; + assign _theResult___sfd__h520621 = + sfd__h519959[53] ? + ((_theResult___fst_exp__h519940 == 11'd2046) ? 52'd0 : - sfd__h519958[52:1]) : - sfd__h519958[51:0] ; - assign _theResult___sfd__h541038 = - sfd__h540400[53] ? - ((_theResult___fst_exp__h540382 == 11'd2046) ? + sfd__h519959[52:1]) : + sfd__h519959[51:0] ; + assign _theResult___sfd__h541039 = + sfd__h540401[53] ? + ((_theResult___fst_exp__h540383 == 11'd2046) ? 52'd0 : - sfd__h540400[52:1]) : - sfd__h540400[51:0] ; - assign _theResult___sfd__h550689 = - sfd__h550051[53] ? - ((_theResult___fst_exp__h549959 == 11'd2046) ? + sfd__h540401[52:1]) : + sfd__h540401[51:0] ; + assign _theResult___sfd__h550690 = + sfd__h550052[53] ? + ((_theResult___fst_exp__h549960 == 11'd2046) ? 52'd0 : - sfd__h550051[52:1]) : - sfd__h550051[51:0] ; - assign _theResult___sfd__h559473 = - sfd__h558811[53] ? - ((_theResult___fst_exp__h558792 == 11'd2046) ? + sfd__h550052[52:1]) : + sfd__h550052[51:0] ; + assign _theResult___sfd__h559474 = + sfd__h558812[53] ? + ((_theResult___fst_exp__h558793 == 11'd2046) ? 52'd0 : - sfd__h558811[52:1]) : - sfd__h558811[51:0] ; - assign _theResult___sfd__h580342 = - sfd__h579704[53] ? - ((_theResult___fst_exp__h579686 == 11'd2046) ? + sfd__h558812[52:1]) : + sfd__h558812[51:0] ; + assign _theResult___sfd__h580343 = + sfd__h579705[53] ? + ((_theResult___fst_exp__h579687 == 11'd2046) ? 52'd0 : - sfd__h579704[52:1]) : - sfd__h579704[51:0] ; - assign _theResult___sfd__h589993 = - sfd__h589355[53] ? - ((_theResult___fst_exp__h589263 == 11'd2046) ? + sfd__h579705[52:1]) : + sfd__h579705[51:0] ; + assign _theResult___sfd__h589994 = + sfd__h589356[53] ? + ((_theResult___fst_exp__h589264 == 11'd2046) ? 52'd0 : - sfd__h589355[52:1]) : - sfd__h589355[51:0] ; - assign _theResult___sfd__h598777 = - sfd__h598115[53] ? - ((_theResult___fst_exp__h598096 == 11'd2046) ? + sfd__h589356[52:1]) : + sfd__h589356[51:0] ; + assign _theResult___sfd__h598778 = + sfd__h598116[53] ? + ((_theResult___fst_exp__h598097 == 11'd2046) ? 52'd0 : - sfd__h598115[52:1]) : - sfd__h598115[51:0] ; - assign _theResult___snd__h354208 = { _theResult____h346086[55:0], 1'd0 } ; - assign _theResult___snd__h354219 = - (!_theResult____h346086[56] && _theResult____h346086[55]) ? - _theResult___snd__h354221 : - _theResult___snd__h354231 ; - assign _theResult___snd__h354221 = { _theResult____h346086[54:0], 2'd0 } ; - assign _theResult___snd__h354231 = - (!_theResult____h346086[56] && !_theResult____h346086[55] && - !_theResult____h346086[54] && - !_theResult____h346086[53] && - !_theResult____h346086[52] && - !_theResult____h346086[51] && - !_theResult____h346086[50] && - !_theResult____h346086[49] && - !_theResult____h346086[48] && - !_theResult____h346086[47] && - !_theResult____h346086[46] && - !_theResult____h346086[45] && - !_theResult____h346086[44] && - !_theResult____h346086[43] && - !_theResult____h346086[42] && - !_theResult____h346086[41] && - !_theResult____h346086[40] && - !_theResult____h346086[39] && - !_theResult____h346086[38] && - !_theResult____h346086[37] && - !_theResult____h346086[36] && - !_theResult____h346086[35] && - !_theResult____h346086[34] && - !_theResult____h346086[33] && - !_theResult____h346086[32] && - !_theResult____h346086[31] && - !_theResult____h346086[30] && - !_theResult____h346086[29] && - !_theResult____h346086[28] && - !_theResult____h346086[27] && - !_theResult____h346086[26] && - !_theResult____h346086[25] && - !_theResult____h346086[24] && - !_theResult____h346086[23] && - !_theResult____h346086[22] && - !_theResult____h346086[21] && - !_theResult____h346086[20] && - !_theResult____h346086[19] && - !_theResult____h346086[18] && - !_theResult____h346086[17] && - !_theResult____h346086[16] && - !_theResult____h346086[15] && - !_theResult____h346086[14] && - !_theResult____h346086[13] && - !_theResult____h346086[12] && - !_theResult____h346086[11] && - !_theResult____h346086[10] && - !_theResult____h346086[9] && - !_theResult____h346086[8] && - !_theResult____h346086[7] && - !_theResult____h346086[6] && - !_theResult____h346086[5] && - !_theResult____h346086[4] && - !_theResult____h346086[3] && - !_theResult____h346086[2] && - !_theResult____h346086[1] && - !_theResult____h346086[0]) ? - _theResult____h346086 : - _theResult___snd__h354237 ; - assign _theResult___snd__h354237 = + sfd__h598116[52:1]) : + sfd__h598116[51:0] ; + assign _theResult___snd__h354209 = { _theResult____h346087[55:0], 1'd0 } ; + assign _theResult___snd__h354220 = + (!_theResult____h346087[56] && _theResult____h346087[55]) ? + _theResult___snd__h354222 : + _theResult___snd__h354232 ; + assign _theResult___snd__h354222 = { _theResult____h346087[54:0], 2'd0 } ; + assign _theResult___snd__h354232 = + (!_theResult____h346087[56] && !_theResult____h346087[55] && + !_theResult____h346087[54] && + !_theResult____h346087[53] && + !_theResult____h346087[52] && + !_theResult____h346087[51] && + !_theResult____h346087[50] && + !_theResult____h346087[49] && + !_theResult____h346087[48] && + !_theResult____h346087[47] && + !_theResult____h346087[46] && + !_theResult____h346087[45] && + !_theResult____h346087[44] && + !_theResult____h346087[43] && + !_theResult____h346087[42] && + !_theResult____h346087[41] && + !_theResult____h346087[40] && + !_theResult____h346087[39] && + !_theResult____h346087[38] && + !_theResult____h346087[37] && + !_theResult____h346087[36] && + !_theResult____h346087[35] && + !_theResult____h346087[34] && + !_theResult____h346087[33] && + !_theResult____h346087[32] && + !_theResult____h346087[31] && + !_theResult____h346087[30] && + !_theResult____h346087[29] && + !_theResult____h346087[28] && + !_theResult____h346087[27] && + !_theResult____h346087[26] && + !_theResult____h346087[25] && + !_theResult____h346087[24] && + !_theResult____h346087[23] && + !_theResult____h346087[22] && + !_theResult____h346087[21] && + !_theResult____h346087[20] && + !_theResult____h346087[19] && + !_theResult____h346087[18] && + !_theResult____h346087[17] && + !_theResult____h346087[16] && + !_theResult____h346087[15] && + !_theResult____h346087[14] && + !_theResult____h346087[13] && + !_theResult____h346087[12] && + !_theResult____h346087[11] && + !_theResult____h346087[10] && + !_theResult____h346087[9] && + !_theResult____h346087[8] && + !_theResult____h346087[7] && + !_theResult____h346087[6] && + !_theResult____h346087[5] && + !_theResult____h346087[4] && + !_theResult____h346087[3] && + !_theResult____h346087[2] && + !_theResult____h346087[1] && + !_theResult____h346087[0]) ? + _theResult____h346087 : + _theResult___snd__h354238 ; + assign _theResult___snd__h354238 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0], 2'd0 } ; - assign _theResult___snd__h354260 = - _theResult____h346086 << + assign _theResult___snd__h354261 = + _theResult____h346087 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 ; - assign _theResult___snd__h362804 = + assign _theResult___snd__h362805 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h362813 : - _theResult___snd__h362806 ; - assign _theResult___snd__h362806 = + _theResult___snd__h362814 : + _theResult___snd__h362807 ; + assign _theResult___snd__h362807 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h362813 = + assign _theResult___snd__h362814 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338481 : - _theResult___snd__h362819 ; - assign _theResult___snd__h362819 = + sfd__h338482 : + _theResult___snd__h362820 ; + assign _theResult___snd__h362820 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h362842 = - sfd__h338481 << + assign _theResult___snd__h362843 = + sfd__h338482 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 ; - assign _theResult___snd__h371974 = { _theResult____h363725[55:0], 1'd0 } ; - assign _theResult___snd__h371985 = - (!_theResult____h363725[56] && _theResult____h363725[55]) ? - _theResult___snd__h371987 : - _theResult___snd__h371997 ; - assign _theResult___snd__h371987 = { _theResult____h363725[54:0], 2'd0 } ; - assign _theResult___snd__h371997 = - (!_theResult____h363725[56] && !_theResult____h363725[55] && - !_theResult____h363725[54] && - !_theResult____h363725[53] && - !_theResult____h363725[52] && - !_theResult____h363725[51] && - !_theResult____h363725[50] && - !_theResult____h363725[49] && - !_theResult____h363725[48] && - !_theResult____h363725[47] && - !_theResult____h363725[46] && - !_theResult____h363725[45] && - !_theResult____h363725[44] && - !_theResult____h363725[43] && - !_theResult____h363725[42] && - !_theResult____h363725[41] && - !_theResult____h363725[40] && - !_theResult____h363725[39] && - !_theResult____h363725[38] && - !_theResult____h363725[37] && - !_theResult____h363725[36] && - !_theResult____h363725[35] && - !_theResult____h363725[34] && - !_theResult____h363725[33] && - !_theResult____h363725[32] && - !_theResult____h363725[31] && - !_theResult____h363725[30] && - !_theResult____h363725[29] && - !_theResult____h363725[28] && - !_theResult____h363725[27] && - !_theResult____h363725[26] && - !_theResult____h363725[25] && - !_theResult____h363725[24] && - !_theResult____h363725[23] && - !_theResult____h363725[22] && - !_theResult____h363725[21] && - !_theResult____h363725[20] && - !_theResult____h363725[19] && - !_theResult____h363725[18] && - !_theResult____h363725[17] && - !_theResult____h363725[16] && - !_theResult____h363725[15] && - !_theResult____h363725[14] && - !_theResult____h363725[13] && - !_theResult____h363725[12] && - !_theResult____h363725[11] && - !_theResult____h363725[10] && - !_theResult____h363725[9] && - !_theResult____h363725[8] && - !_theResult____h363725[7] && - !_theResult____h363725[6] && - !_theResult____h363725[5] && - !_theResult____h363725[4] && - !_theResult____h363725[3] && - !_theResult____h363725[2] && - !_theResult____h363725[1] && - !_theResult____h363725[0]) ? - _theResult____h363725 : - _theResult___snd__h372003 ; - assign _theResult___snd__h372003 = + assign _theResult___snd__h371975 = { _theResult____h363726[55:0], 1'd0 } ; + assign _theResult___snd__h371986 = + (!_theResult____h363726[56] && _theResult____h363726[55]) ? + _theResult___snd__h371988 : + _theResult___snd__h371998 ; + assign _theResult___snd__h371988 = { _theResult____h363726[54:0], 2'd0 } ; + assign _theResult___snd__h371998 = + (!_theResult____h363726[56] && !_theResult____h363726[55] && + !_theResult____h363726[54] && + !_theResult____h363726[53] && + !_theResult____h363726[52] && + !_theResult____h363726[51] && + !_theResult____h363726[50] && + !_theResult____h363726[49] && + !_theResult____h363726[48] && + !_theResult____h363726[47] && + !_theResult____h363726[46] && + !_theResult____h363726[45] && + !_theResult____h363726[44] && + !_theResult____h363726[43] && + !_theResult____h363726[42] && + !_theResult____h363726[41] && + !_theResult____h363726[40] && + !_theResult____h363726[39] && + !_theResult____h363726[38] && + !_theResult____h363726[37] && + !_theResult____h363726[36] && + !_theResult____h363726[35] && + !_theResult____h363726[34] && + !_theResult____h363726[33] && + !_theResult____h363726[32] && + !_theResult____h363726[31] && + !_theResult____h363726[30] && + !_theResult____h363726[29] && + !_theResult____h363726[28] && + !_theResult____h363726[27] && + !_theResult____h363726[26] && + !_theResult____h363726[25] && + !_theResult____h363726[24] && + !_theResult____h363726[23] && + !_theResult____h363726[22] && + !_theResult____h363726[21] && + !_theResult____h363726[20] && + !_theResult____h363726[19] && + !_theResult____h363726[18] && + !_theResult____h363726[17] && + !_theResult____h363726[16] && + !_theResult____h363726[15] && + !_theResult____h363726[14] && + !_theResult____h363726[13] && + !_theResult____h363726[12] && + !_theResult____h363726[11] && + !_theResult____h363726[10] && + !_theResult____h363726[9] && + !_theResult____h363726[8] && + !_theResult____h363726[7] && + !_theResult____h363726[6] && + !_theResult____h363726[5] && + !_theResult____h363726[4] && + !_theResult____h363726[3] && + !_theResult____h363726[2] && + !_theResult____h363726[1] && + !_theResult____h363726[0]) ? + _theResult____h363726 : + _theResult___snd__h372004 ; + assign _theResult___snd__h372004 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0], 2'd0 } ; - assign _theResult___snd__h372026 = - _theResult____h363725 << + assign _theResult___snd__h372027 = + _theResult____h363726 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 ; - assign _theResult___snd__h380594 = + assign _theResult___snd__h380595 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h380608 : - _theResult___snd__h362806 ; - assign _theResult___snd__h380608 = + _theResult___snd__h380609 : + _theResult___snd__h362807 ; + assign _theResult___snd__h380609 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338481 : - _theResult___snd__h380614 ; - assign _theResult___snd__h380614 = + sfd__h338482 : + _theResult___snd__h380615 ; + assign _theResult___snd__h380615 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0], 2'd0 } ; - assign _theResult___snd__h380632 = - sfd__h338481 << + assign _theResult___snd__h380633 = + sfd__h338482 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872) ; - assign _theResult___snd__h399905 = { _theResult____h391785[55:0], 1'd0 } ; - assign _theResult___snd__h399916 = - (!_theResult____h391785[56] && _theResult____h391785[55]) ? - _theResult___snd__h399918 : - _theResult___snd__h399928 ; - assign _theResult___snd__h399918 = { _theResult____h391785[54:0], 2'd0 } ; - assign _theResult___snd__h399928 = - (!_theResult____h391785[56] && !_theResult____h391785[55] && - !_theResult____h391785[54] && - !_theResult____h391785[53] && - !_theResult____h391785[52] && - !_theResult____h391785[51] && - !_theResult____h391785[50] && - !_theResult____h391785[49] && - !_theResult____h391785[48] && - !_theResult____h391785[47] && - !_theResult____h391785[46] && - !_theResult____h391785[45] && - !_theResult____h391785[44] && - !_theResult____h391785[43] && - !_theResult____h391785[42] && - !_theResult____h391785[41] && - !_theResult____h391785[40] && - !_theResult____h391785[39] && - !_theResult____h391785[38] && - !_theResult____h391785[37] && - !_theResult____h391785[36] && - !_theResult____h391785[35] && - !_theResult____h391785[34] && - !_theResult____h391785[33] && - !_theResult____h391785[32] && - !_theResult____h391785[31] && - !_theResult____h391785[30] && - !_theResult____h391785[29] && - !_theResult____h391785[28] && - !_theResult____h391785[27] && - !_theResult____h391785[26] && - !_theResult____h391785[25] && - !_theResult____h391785[24] && - !_theResult____h391785[23] && - !_theResult____h391785[22] && - !_theResult____h391785[21] && - !_theResult____h391785[20] && - !_theResult____h391785[19] && - !_theResult____h391785[18] && - !_theResult____h391785[17] && - !_theResult____h391785[16] && - !_theResult____h391785[15] && - !_theResult____h391785[14] && - !_theResult____h391785[13] && - !_theResult____h391785[12] && - !_theResult____h391785[11] && - !_theResult____h391785[10] && - !_theResult____h391785[9] && - !_theResult____h391785[8] && - !_theResult____h391785[7] && - !_theResult____h391785[6] && - !_theResult____h391785[5] && - !_theResult____h391785[4] && - !_theResult____h391785[3] && - !_theResult____h391785[2] && - !_theResult____h391785[1] && - !_theResult____h391785[0]) ? - _theResult____h391785 : - _theResult___snd__h399934 ; - assign _theResult___snd__h399934 = + assign _theResult___snd__h399906 = { _theResult____h391786[55:0], 1'd0 } ; + assign _theResult___snd__h399917 = + (!_theResult____h391786[56] && _theResult____h391786[55]) ? + _theResult___snd__h399919 : + _theResult___snd__h399929 ; + assign _theResult___snd__h399919 = { _theResult____h391786[54:0], 2'd0 } ; + assign _theResult___snd__h399929 = + (!_theResult____h391786[56] && !_theResult____h391786[55] && + !_theResult____h391786[54] && + !_theResult____h391786[53] && + !_theResult____h391786[52] && + !_theResult____h391786[51] && + !_theResult____h391786[50] && + !_theResult____h391786[49] && + !_theResult____h391786[48] && + !_theResult____h391786[47] && + !_theResult____h391786[46] && + !_theResult____h391786[45] && + !_theResult____h391786[44] && + !_theResult____h391786[43] && + !_theResult____h391786[42] && + !_theResult____h391786[41] && + !_theResult____h391786[40] && + !_theResult____h391786[39] && + !_theResult____h391786[38] && + !_theResult____h391786[37] && + !_theResult____h391786[36] && + !_theResult____h391786[35] && + !_theResult____h391786[34] && + !_theResult____h391786[33] && + !_theResult____h391786[32] && + !_theResult____h391786[31] && + !_theResult____h391786[30] && + !_theResult____h391786[29] && + !_theResult____h391786[28] && + !_theResult____h391786[27] && + !_theResult____h391786[26] && + !_theResult____h391786[25] && + !_theResult____h391786[24] && + !_theResult____h391786[23] && + !_theResult____h391786[22] && + !_theResult____h391786[21] && + !_theResult____h391786[20] && + !_theResult____h391786[19] && + !_theResult____h391786[18] && + !_theResult____h391786[17] && + !_theResult____h391786[16] && + !_theResult____h391786[15] && + !_theResult____h391786[14] && + !_theResult____h391786[13] && + !_theResult____h391786[12] && + !_theResult____h391786[11] && + !_theResult____h391786[10] && + !_theResult____h391786[9] && + !_theResult____h391786[8] && + !_theResult____h391786[7] && + !_theResult____h391786[6] && + !_theResult____h391786[5] && + !_theResult____h391786[4] && + !_theResult____h391786[3] && + !_theResult____h391786[2] && + !_theResult____h391786[1] && + !_theResult____h391786[0]) ? + _theResult____h391786 : + _theResult___snd__h399935 ; + assign _theResult___snd__h399935 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0], 2'd0 } ; - assign _theResult___snd__h399957 = - _theResult____h391785 << + assign _theResult___snd__h399958 = + _theResult____h391786 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 ; - assign _theResult___snd__h408501 = + assign _theResult___snd__h408502 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h408510 : - _theResult___snd__h408503 ; - assign _theResult___snd__h408503 = + _theResult___snd__h408511 : + _theResult___snd__h408504 ; + assign _theResult___snd__h408504 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h408510 = + assign _theResult___snd__h408511 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384183 : - _theResult___snd__h408516 ; - assign _theResult___snd__h408516 = + sfd__h384184 : + _theResult___snd__h408517 ; + assign _theResult___snd__h408517 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h408539 = - sfd__h384183 << + assign _theResult___snd__h408540 = + sfd__h384184 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 ; - assign _theResult___snd__h417671 = { _theResult____h409422[55:0], 1'd0 } ; - assign _theResult___snd__h417682 = - (!_theResult____h409422[56] && _theResult____h409422[55]) ? - _theResult___snd__h417684 : - _theResult___snd__h417694 ; - assign _theResult___snd__h417684 = { _theResult____h409422[54:0], 2'd0 } ; - assign _theResult___snd__h417694 = - (!_theResult____h409422[56] && !_theResult____h409422[55] && - !_theResult____h409422[54] && - !_theResult____h409422[53] && - !_theResult____h409422[52] && - !_theResult____h409422[51] && - !_theResult____h409422[50] && - !_theResult____h409422[49] && - !_theResult____h409422[48] && - !_theResult____h409422[47] && - !_theResult____h409422[46] && - !_theResult____h409422[45] && - !_theResult____h409422[44] && - !_theResult____h409422[43] && - !_theResult____h409422[42] && - !_theResult____h409422[41] && - !_theResult____h409422[40] && - !_theResult____h409422[39] && - !_theResult____h409422[38] && - !_theResult____h409422[37] && - !_theResult____h409422[36] && - !_theResult____h409422[35] && - !_theResult____h409422[34] && - !_theResult____h409422[33] && - !_theResult____h409422[32] && - !_theResult____h409422[31] && - !_theResult____h409422[30] && - !_theResult____h409422[29] && - !_theResult____h409422[28] && - !_theResult____h409422[27] && - !_theResult____h409422[26] && - !_theResult____h409422[25] && - !_theResult____h409422[24] && - !_theResult____h409422[23] && - !_theResult____h409422[22] && - !_theResult____h409422[21] && - !_theResult____h409422[20] && - !_theResult____h409422[19] && - !_theResult____h409422[18] && - !_theResult____h409422[17] && - !_theResult____h409422[16] && - !_theResult____h409422[15] && - !_theResult____h409422[14] && - !_theResult____h409422[13] && - !_theResult____h409422[12] && - !_theResult____h409422[11] && - !_theResult____h409422[10] && - !_theResult____h409422[9] && - !_theResult____h409422[8] && - !_theResult____h409422[7] && - !_theResult____h409422[6] && - !_theResult____h409422[5] && - !_theResult____h409422[4] && - !_theResult____h409422[3] && - !_theResult____h409422[2] && - !_theResult____h409422[1] && - !_theResult____h409422[0]) ? - _theResult____h409422 : - _theResult___snd__h417700 ; - assign _theResult___snd__h417700 = + assign _theResult___snd__h417672 = { _theResult____h409423[55:0], 1'd0 } ; + assign _theResult___snd__h417683 = + (!_theResult____h409423[56] && _theResult____h409423[55]) ? + _theResult___snd__h417685 : + _theResult___snd__h417695 ; + assign _theResult___snd__h417685 = { _theResult____h409423[54:0], 2'd0 } ; + assign _theResult___snd__h417695 = + (!_theResult____h409423[56] && !_theResult____h409423[55] && + !_theResult____h409423[54] && + !_theResult____h409423[53] && + !_theResult____h409423[52] && + !_theResult____h409423[51] && + !_theResult____h409423[50] && + !_theResult____h409423[49] && + !_theResult____h409423[48] && + !_theResult____h409423[47] && + !_theResult____h409423[46] && + !_theResult____h409423[45] && + !_theResult____h409423[44] && + !_theResult____h409423[43] && + !_theResult____h409423[42] && + !_theResult____h409423[41] && + !_theResult____h409423[40] && + !_theResult____h409423[39] && + !_theResult____h409423[38] && + !_theResult____h409423[37] && + !_theResult____h409423[36] && + !_theResult____h409423[35] && + !_theResult____h409423[34] && + !_theResult____h409423[33] && + !_theResult____h409423[32] && + !_theResult____h409423[31] && + !_theResult____h409423[30] && + !_theResult____h409423[29] && + !_theResult____h409423[28] && + !_theResult____h409423[27] && + !_theResult____h409423[26] && + !_theResult____h409423[25] && + !_theResult____h409423[24] && + !_theResult____h409423[23] && + !_theResult____h409423[22] && + !_theResult____h409423[21] && + !_theResult____h409423[20] && + !_theResult____h409423[19] && + !_theResult____h409423[18] && + !_theResult____h409423[17] && + !_theResult____h409423[16] && + !_theResult____h409423[15] && + !_theResult____h409423[14] && + !_theResult____h409423[13] && + !_theResult____h409423[12] && + !_theResult____h409423[11] && + !_theResult____h409423[10] && + !_theResult____h409423[9] && + !_theResult____h409423[8] && + !_theResult____h409423[7] && + !_theResult____h409423[6] && + !_theResult____h409423[5] && + !_theResult____h409423[4] && + !_theResult____h409423[3] && + !_theResult____h409423[2] && + !_theResult____h409423[1] && + !_theResult____h409423[0]) ? + _theResult____h409423 : + _theResult___snd__h417701 ; + assign _theResult___snd__h417701 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0], 2'd0 } ; - assign _theResult___snd__h417723 = - _theResult____h409422 << + assign _theResult___snd__h417724 = + _theResult____h409423 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 ; - assign _theResult___snd__h426291 = + assign _theResult___snd__h426292 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h426305 : - _theResult___snd__h408503 ; - assign _theResult___snd__h426305 = + _theResult___snd__h426306 : + _theResult___snd__h408504 ; + assign _theResult___snd__h426306 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384183 : - _theResult___snd__h426311 ; - assign _theResult___snd__h426311 = + sfd__h384184 : + _theResult___snd__h426312 ; + assign _theResult___snd__h426312 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0], 2'd0 } ; - assign _theResult___snd__h426329 = - sfd__h384183 << + assign _theResult___snd__h426330 = + sfd__h384184 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264) ; - assign _theResult___snd__h445600 = { _theResult____h437480[55:0], 1'd0 } ; - assign _theResult___snd__h445611 = - (!_theResult____h437480[56] && _theResult____h437480[55]) ? - _theResult___snd__h445613 : - _theResult___snd__h445623 ; - assign _theResult___snd__h445613 = { _theResult____h437480[54:0], 2'd0 } ; - assign _theResult___snd__h445623 = - (!_theResult____h437480[56] && !_theResult____h437480[55] && - !_theResult____h437480[54] && - !_theResult____h437480[53] && - !_theResult____h437480[52] && - !_theResult____h437480[51] && - !_theResult____h437480[50] && - !_theResult____h437480[49] && - !_theResult____h437480[48] && - !_theResult____h437480[47] && - !_theResult____h437480[46] && - !_theResult____h437480[45] && - !_theResult____h437480[44] && - !_theResult____h437480[43] && - !_theResult____h437480[42] && - !_theResult____h437480[41] && - !_theResult____h437480[40] && - !_theResult____h437480[39] && - !_theResult____h437480[38] && - !_theResult____h437480[37] && - !_theResult____h437480[36] && - !_theResult____h437480[35] && - !_theResult____h437480[34] && - !_theResult____h437480[33] && - !_theResult____h437480[32] && - !_theResult____h437480[31] && - !_theResult____h437480[30] && - !_theResult____h437480[29] && - !_theResult____h437480[28] && - !_theResult____h437480[27] && - !_theResult____h437480[26] && - !_theResult____h437480[25] && - !_theResult____h437480[24] && - !_theResult____h437480[23] && - !_theResult____h437480[22] && - !_theResult____h437480[21] && - !_theResult____h437480[20] && - !_theResult____h437480[19] && - !_theResult____h437480[18] && - !_theResult____h437480[17] && - !_theResult____h437480[16] && - !_theResult____h437480[15] && - !_theResult____h437480[14] && - !_theResult____h437480[13] && - !_theResult____h437480[12] && - !_theResult____h437480[11] && - !_theResult____h437480[10] && - !_theResult____h437480[9] && - !_theResult____h437480[8] && - !_theResult____h437480[7] && - !_theResult____h437480[6] && - !_theResult____h437480[5] && - !_theResult____h437480[4] && - !_theResult____h437480[3] && - !_theResult____h437480[2] && - !_theResult____h437480[1] && - !_theResult____h437480[0]) ? - _theResult____h437480 : - _theResult___snd__h445629 ; - assign _theResult___snd__h445629 = + assign _theResult___snd__h445601 = { _theResult____h437481[55:0], 1'd0 } ; + assign _theResult___snd__h445612 = + (!_theResult____h437481[56] && _theResult____h437481[55]) ? + _theResult___snd__h445614 : + _theResult___snd__h445624 ; + assign _theResult___snd__h445614 = { _theResult____h437481[54:0], 2'd0 } ; + assign _theResult___snd__h445624 = + (!_theResult____h437481[56] && !_theResult____h437481[55] && + !_theResult____h437481[54] && + !_theResult____h437481[53] && + !_theResult____h437481[52] && + !_theResult____h437481[51] && + !_theResult____h437481[50] && + !_theResult____h437481[49] && + !_theResult____h437481[48] && + !_theResult____h437481[47] && + !_theResult____h437481[46] && + !_theResult____h437481[45] && + !_theResult____h437481[44] && + !_theResult____h437481[43] && + !_theResult____h437481[42] && + !_theResult____h437481[41] && + !_theResult____h437481[40] && + !_theResult____h437481[39] && + !_theResult____h437481[38] && + !_theResult____h437481[37] && + !_theResult____h437481[36] && + !_theResult____h437481[35] && + !_theResult____h437481[34] && + !_theResult____h437481[33] && + !_theResult____h437481[32] && + !_theResult____h437481[31] && + !_theResult____h437481[30] && + !_theResult____h437481[29] && + !_theResult____h437481[28] && + !_theResult____h437481[27] && + !_theResult____h437481[26] && + !_theResult____h437481[25] && + !_theResult____h437481[24] && + !_theResult____h437481[23] && + !_theResult____h437481[22] && + !_theResult____h437481[21] && + !_theResult____h437481[20] && + !_theResult____h437481[19] && + !_theResult____h437481[18] && + !_theResult____h437481[17] && + !_theResult____h437481[16] && + !_theResult____h437481[15] && + !_theResult____h437481[14] && + !_theResult____h437481[13] && + !_theResult____h437481[12] && + !_theResult____h437481[11] && + !_theResult____h437481[10] && + !_theResult____h437481[9] && + !_theResult____h437481[8] && + !_theResult____h437481[7] && + !_theResult____h437481[6] && + !_theResult____h437481[5] && + !_theResult____h437481[4] && + !_theResult____h437481[3] && + !_theResult____h437481[2] && + !_theResult____h437481[1] && + !_theResult____h437481[0]) ? + _theResult____h437481 : + _theResult___snd__h445630 ; + assign _theResult___snd__h445630 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0], 2'd0 } ; - assign _theResult___snd__h445652 = - _theResult____h437480 << + assign _theResult___snd__h445653 = + _theResult____h437481 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 ; - assign _theResult___snd__h454196 = + assign _theResult___snd__h454197 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h454205 : - _theResult___snd__h454198 ; - assign _theResult___snd__h454198 = + _theResult___snd__h454206 : + _theResult___snd__h454199 ; + assign _theResult___snd__h454199 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h454205 = + assign _theResult___snd__h454206 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429878 : - _theResult___snd__h454211 ; - assign _theResult___snd__h454211 = + sfd__h429879 : + _theResult___snd__h454212 ; + assign _theResult___snd__h454212 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h454234 = - sfd__h429878 << + assign _theResult___snd__h454235 = + sfd__h429879 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 ; - assign _theResult___snd__h463366 = { _theResult____h455117[55:0], 1'd0 } ; - assign _theResult___snd__h463377 = - (!_theResult____h455117[56] && _theResult____h455117[55]) ? - _theResult___snd__h463379 : - _theResult___snd__h463389 ; - assign _theResult___snd__h463379 = { _theResult____h455117[54:0], 2'd0 } ; - assign _theResult___snd__h463389 = - (!_theResult____h455117[56] && !_theResult____h455117[55] && - !_theResult____h455117[54] && - !_theResult____h455117[53] && - !_theResult____h455117[52] && - !_theResult____h455117[51] && - !_theResult____h455117[50] && - !_theResult____h455117[49] && - !_theResult____h455117[48] && - !_theResult____h455117[47] && - !_theResult____h455117[46] && - !_theResult____h455117[45] && - !_theResult____h455117[44] && - !_theResult____h455117[43] && - !_theResult____h455117[42] && - !_theResult____h455117[41] && - !_theResult____h455117[40] && - !_theResult____h455117[39] && - !_theResult____h455117[38] && - !_theResult____h455117[37] && - !_theResult____h455117[36] && - !_theResult____h455117[35] && - !_theResult____h455117[34] && - !_theResult____h455117[33] && - !_theResult____h455117[32] && - !_theResult____h455117[31] && - !_theResult____h455117[30] && - !_theResult____h455117[29] && - !_theResult____h455117[28] && - !_theResult____h455117[27] && - !_theResult____h455117[26] && - !_theResult____h455117[25] && - !_theResult____h455117[24] && - !_theResult____h455117[23] && - !_theResult____h455117[22] && - !_theResult____h455117[21] && - !_theResult____h455117[20] && - !_theResult____h455117[19] && - !_theResult____h455117[18] && - !_theResult____h455117[17] && - !_theResult____h455117[16] && - !_theResult____h455117[15] && - !_theResult____h455117[14] && - !_theResult____h455117[13] && - !_theResult____h455117[12] && - !_theResult____h455117[11] && - !_theResult____h455117[10] && - !_theResult____h455117[9] && - !_theResult____h455117[8] && - !_theResult____h455117[7] && - !_theResult____h455117[6] && - !_theResult____h455117[5] && - !_theResult____h455117[4] && - !_theResult____h455117[3] && - !_theResult____h455117[2] && - !_theResult____h455117[1] && - !_theResult____h455117[0]) ? - _theResult____h455117 : - _theResult___snd__h463395 ; - assign _theResult___snd__h463395 = + assign _theResult___snd__h463367 = { _theResult____h455118[55:0], 1'd0 } ; + assign _theResult___snd__h463378 = + (!_theResult____h455118[56] && _theResult____h455118[55]) ? + _theResult___snd__h463380 : + _theResult___snd__h463390 ; + assign _theResult___snd__h463380 = { _theResult____h455118[54:0], 2'd0 } ; + assign _theResult___snd__h463390 = + (!_theResult____h455118[56] && !_theResult____h455118[55] && + !_theResult____h455118[54] && + !_theResult____h455118[53] && + !_theResult____h455118[52] && + !_theResult____h455118[51] && + !_theResult____h455118[50] && + !_theResult____h455118[49] && + !_theResult____h455118[48] && + !_theResult____h455118[47] && + !_theResult____h455118[46] && + !_theResult____h455118[45] && + !_theResult____h455118[44] && + !_theResult____h455118[43] && + !_theResult____h455118[42] && + !_theResult____h455118[41] && + !_theResult____h455118[40] && + !_theResult____h455118[39] && + !_theResult____h455118[38] && + !_theResult____h455118[37] && + !_theResult____h455118[36] && + !_theResult____h455118[35] && + !_theResult____h455118[34] && + !_theResult____h455118[33] && + !_theResult____h455118[32] && + !_theResult____h455118[31] && + !_theResult____h455118[30] && + !_theResult____h455118[29] && + !_theResult____h455118[28] && + !_theResult____h455118[27] && + !_theResult____h455118[26] && + !_theResult____h455118[25] && + !_theResult____h455118[24] && + !_theResult____h455118[23] && + !_theResult____h455118[22] && + !_theResult____h455118[21] && + !_theResult____h455118[20] && + !_theResult____h455118[19] && + !_theResult____h455118[18] && + !_theResult____h455118[17] && + !_theResult____h455118[16] && + !_theResult____h455118[15] && + !_theResult____h455118[14] && + !_theResult____h455118[13] && + !_theResult____h455118[12] && + !_theResult____h455118[11] && + !_theResult____h455118[10] && + !_theResult____h455118[9] && + !_theResult____h455118[8] && + !_theResult____h455118[7] && + !_theResult____h455118[6] && + !_theResult____h455118[5] && + !_theResult____h455118[4] && + !_theResult____h455118[3] && + !_theResult____h455118[2] && + !_theResult____h455118[1] && + !_theResult____h455118[0]) ? + _theResult____h455118 : + _theResult___snd__h463396 ; + assign _theResult___snd__h463396 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0], 2'd0 } ; - assign _theResult___snd__h463418 = - _theResult____h455117 << + assign _theResult___snd__h463419 = + _theResult____h455118 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 ; - assign _theResult___snd__h471986 = + assign _theResult___snd__h471987 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h472000 : - _theResult___snd__h454198 ; - assign _theResult___snd__h472000 = + _theResult___snd__h472001 : + _theResult___snd__h454199 ; + assign _theResult___snd__h472001 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429878 : - _theResult___snd__h472006 ; - assign _theResult___snd__h472006 = + sfd__h429879 : + _theResult___snd__h472007 ; + assign _theResult___snd__h472007 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0], 2'd0 } ; - assign _theResult___snd__h472024 = - sfd__h429878 << + assign _theResult___snd__h472025 = + sfd__h429879 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656) ; - assign _theResult___snd__h501480 = - (f1_exp__h482141 == 8'd0) ? - _theResult___snd__h501489 : - _theResult___snd__h501482 ; - assign _theResult___snd__h501482 = { f1_sfd__h482142, 34'd0 } ; - assign _theResult___snd__h501489 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___snd__h501481 = + (f1_exp__h482142 == 8'd0) ? + _theResult___snd__h501490 : + _theResult___snd__h501483 ; + assign _theResult___snd__h501483 = { f1_sfd__h482143, 34'd0 } ; + assign _theResult___snd__h501490 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482503 : - _theResult___snd__h501495 ; - assign _theResult___snd__h501495 = + sfd__h482504 : + _theResult___snd__h501496 ; + assign _theResult___snd__h501496 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h501518 = - sfd__h482503 << + assign _theResult___snd__h501519 = + sfd__h482504 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 ; - assign _theResult___snd__h511117 = { _theResult____h502870[55:0], 1'd0 } ; - assign _theResult___snd__h511128 = - (!_theResult____h502870[56] && _theResult____h502870[55]) ? - _theResult___snd__h511130 : - _theResult___snd__h511140 ; - assign _theResult___snd__h511130 = { _theResult____h502870[54:0], 2'd0 } ; - assign _theResult___snd__h511140 = - (!_theResult____h502870[56] && !_theResult____h502870[55] && - !_theResult____h502870[54] && - !_theResult____h502870[53] && - !_theResult____h502870[52] && - !_theResult____h502870[51] && - !_theResult____h502870[50] && - !_theResult____h502870[49] && - !_theResult____h502870[48] && - !_theResult____h502870[47] && - !_theResult____h502870[46] && - !_theResult____h502870[45] && - !_theResult____h502870[44] && - !_theResult____h502870[43] && - !_theResult____h502870[42] && - !_theResult____h502870[41] && - !_theResult____h502870[40] && - !_theResult____h502870[39] && - !_theResult____h502870[38] && - !_theResult____h502870[37] && - !_theResult____h502870[36] && - !_theResult____h502870[35] && - !_theResult____h502870[34] && - !_theResult____h502870[33] && - !_theResult____h502870[32] && - !_theResult____h502870[31] && - !_theResult____h502870[30] && - !_theResult____h502870[29] && - !_theResult____h502870[28] && - !_theResult____h502870[27] && - !_theResult____h502870[26] && - !_theResult____h502870[25] && - !_theResult____h502870[24] && - !_theResult____h502870[23] && - !_theResult____h502870[22] && - !_theResult____h502870[21] && - !_theResult____h502870[20] && - !_theResult____h502870[19] && - !_theResult____h502870[18] && - !_theResult____h502870[17] && - !_theResult____h502870[16] && - !_theResult____h502870[15] && - !_theResult____h502870[14] && - !_theResult____h502870[13] && - !_theResult____h502870[12] && - !_theResult____h502870[11] && - !_theResult____h502870[10] && - !_theResult____h502870[9] && - !_theResult____h502870[8] && - !_theResult____h502870[7] && - !_theResult____h502870[6] && - !_theResult____h502870[5] && - !_theResult____h502870[4] && - !_theResult____h502870[3] && - !_theResult____h502870[2] && - !_theResult____h502870[1] && - !_theResult____h502870[0]) ? - _theResult____h502870 : - _theResult___snd__h511146 ; - assign _theResult___snd__h511146 = + assign _theResult___snd__h511118 = { _theResult____h502871[55:0], 1'd0 } ; + assign _theResult___snd__h511129 = + (!_theResult____h502871[56] && _theResult____h502871[55]) ? + _theResult___snd__h511131 : + _theResult___snd__h511141 ; + assign _theResult___snd__h511131 = { _theResult____h502871[54:0], 2'd0 } ; + assign _theResult___snd__h511141 = + (!_theResult____h502871[56] && !_theResult____h502871[55] && + !_theResult____h502871[54] && + !_theResult____h502871[53] && + !_theResult____h502871[52] && + !_theResult____h502871[51] && + !_theResult____h502871[50] && + !_theResult____h502871[49] && + !_theResult____h502871[48] && + !_theResult____h502871[47] && + !_theResult____h502871[46] && + !_theResult____h502871[45] && + !_theResult____h502871[44] && + !_theResult____h502871[43] && + !_theResult____h502871[42] && + !_theResult____h502871[41] && + !_theResult____h502871[40] && + !_theResult____h502871[39] && + !_theResult____h502871[38] && + !_theResult____h502871[37] && + !_theResult____h502871[36] && + !_theResult____h502871[35] && + !_theResult____h502871[34] && + !_theResult____h502871[33] && + !_theResult____h502871[32] && + !_theResult____h502871[31] && + !_theResult____h502871[30] && + !_theResult____h502871[29] && + !_theResult____h502871[28] && + !_theResult____h502871[27] && + !_theResult____h502871[26] && + !_theResult____h502871[25] && + !_theResult____h502871[24] && + !_theResult____h502871[23] && + !_theResult____h502871[22] && + !_theResult____h502871[21] && + !_theResult____h502871[20] && + !_theResult____h502871[19] && + !_theResult____h502871[18] && + !_theResult____h502871[17] && + !_theResult____h502871[16] && + !_theResult____h502871[15] && + !_theResult____h502871[14] && + !_theResult____h502871[13] && + !_theResult____h502871[12] && + !_theResult____h502871[11] && + !_theResult____h502871[10] && + !_theResult____h502871[9] && + !_theResult____h502871[8] && + !_theResult____h502871[7] && + !_theResult____h502871[6] && + !_theResult____h502871[5] && + !_theResult____h502871[4] && + !_theResult____h502871[3] && + !_theResult____h502871[2] && + !_theResult____h502871[1] && + !_theResult____h502871[0]) ? + _theResult____h502871 : + _theResult___snd__h511147 ; + assign _theResult___snd__h511147 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h511169 = - _theResult____h502870 << + assign _theResult___snd__h511170 = + _theResult____h502871 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 ; - assign _theResult___snd__h519885 = - (f1_exp__h482141 == 8'd0) ? - _theResult___snd__h519899 : - _theResult___snd__h501482 ; - assign _theResult___snd__h519899 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___snd__h519886 = + (f1_exp__h482142 == 8'd0) ? + _theResult___snd__h519900 : + _theResult___snd__h501483 ; + assign _theResult___snd__h519900 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482503 : - _theResult___snd__h519905 ; - assign _theResult___snd__h519905 = + sfd__h482504 : + _theResult___snd__h519906 ; + assign _theResult___snd__h519906 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h519923 = - sfd__h482503 << + assign _theResult___snd__h519924 = + sfd__h482504 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ; - assign _theResult___snd__h540333 = - (f2_exp__h521135 == 8'd0) ? - _theResult___snd__h540342 : - _theResult___snd__h540335 ; - assign _theResult___snd__h540335 = { f2_sfd__h521136, 34'd0 } ; - assign _theResult___snd__h540342 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___snd__h540334 = + (f2_exp__h521136 == 8'd0) ? + _theResult___snd__h540343 : + _theResult___snd__h540336 ; + assign _theResult___snd__h540336 = { f2_sfd__h521137, 34'd0 } ; + assign _theResult___snd__h540343 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521497 : - _theResult___snd__h540348 ; - assign _theResult___snd__h540348 = + sfd__h521498 : + _theResult___snd__h540349 ; + assign _theResult___snd__h540349 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h540371 = - sfd__h521497 << + assign _theResult___snd__h540372 = + sfd__h521498 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 ; - assign _theResult___snd__h549970 = { _theResult____h541723[55:0], 1'd0 } ; - assign _theResult___snd__h549981 = - (!_theResult____h541723[56] && _theResult____h541723[55]) ? - _theResult___snd__h549983 : - _theResult___snd__h549993 ; - assign _theResult___snd__h549983 = { _theResult____h541723[54:0], 2'd0 } ; - assign _theResult___snd__h549993 = - (!_theResult____h541723[56] && !_theResult____h541723[55] && - !_theResult____h541723[54] && - !_theResult____h541723[53] && - !_theResult____h541723[52] && - !_theResult____h541723[51] && - !_theResult____h541723[50] && - !_theResult____h541723[49] && - !_theResult____h541723[48] && - !_theResult____h541723[47] && - !_theResult____h541723[46] && - !_theResult____h541723[45] && - !_theResult____h541723[44] && - !_theResult____h541723[43] && - !_theResult____h541723[42] && - !_theResult____h541723[41] && - !_theResult____h541723[40] && - !_theResult____h541723[39] && - !_theResult____h541723[38] && - !_theResult____h541723[37] && - !_theResult____h541723[36] && - !_theResult____h541723[35] && - !_theResult____h541723[34] && - !_theResult____h541723[33] && - !_theResult____h541723[32] && - !_theResult____h541723[31] && - !_theResult____h541723[30] && - !_theResult____h541723[29] && - !_theResult____h541723[28] && - !_theResult____h541723[27] && - !_theResult____h541723[26] && - !_theResult____h541723[25] && - !_theResult____h541723[24] && - !_theResult____h541723[23] && - !_theResult____h541723[22] && - !_theResult____h541723[21] && - !_theResult____h541723[20] && - !_theResult____h541723[19] && - !_theResult____h541723[18] && - !_theResult____h541723[17] && - !_theResult____h541723[16] && - !_theResult____h541723[15] && - !_theResult____h541723[14] && - !_theResult____h541723[13] && - !_theResult____h541723[12] && - !_theResult____h541723[11] && - !_theResult____h541723[10] && - !_theResult____h541723[9] && - !_theResult____h541723[8] && - !_theResult____h541723[7] && - !_theResult____h541723[6] && - !_theResult____h541723[5] && - !_theResult____h541723[4] && - !_theResult____h541723[3] && - !_theResult____h541723[2] && - !_theResult____h541723[1] && - !_theResult____h541723[0]) ? - _theResult____h541723 : - _theResult___snd__h549999 ; - assign _theResult___snd__h549999 = + assign _theResult___snd__h549971 = { _theResult____h541724[55:0], 1'd0 } ; + assign _theResult___snd__h549982 = + (!_theResult____h541724[56] && _theResult____h541724[55]) ? + _theResult___snd__h549984 : + _theResult___snd__h549994 ; + assign _theResult___snd__h549984 = { _theResult____h541724[54:0], 2'd0 } ; + assign _theResult___snd__h549994 = + (!_theResult____h541724[56] && !_theResult____h541724[55] && + !_theResult____h541724[54] && + !_theResult____h541724[53] && + !_theResult____h541724[52] && + !_theResult____h541724[51] && + !_theResult____h541724[50] && + !_theResult____h541724[49] && + !_theResult____h541724[48] && + !_theResult____h541724[47] && + !_theResult____h541724[46] && + !_theResult____h541724[45] && + !_theResult____h541724[44] && + !_theResult____h541724[43] && + !_theResult____h541724[42] && + !_theResult____h541724[41] && + !_theResult____h541724[40] && + !_theResult____h541724[39] && + !_theResult____h541724[38] && + !_theResult____h541724[37] && + !_theResult____h541724[36] && + !_theResult____h541724[35] && + !_theResult____h541724[34] && + !_theResult____h541724[33] && + !_theResult____h541724[32] && + !_theResult____h541724[31] && + !_theResult____h541724[30] && + !_theResult____h541724[29] && + !_theResult____h541724[28] && + !_theResult____h541724[27] && + !_theResult____h541724[26] && + !_theResult____h541724[25] && + !_theResult____h541724[24] && + !_theResult____h541724[23] && + !_theResult____h541724[22] && + !_theResult____h541724[21] && + !_theResult____h541724[20] && + !_theResult____h541724[19] && + !_theResult____h541724[18] && + !_theResult____h541724[17] && + !_theResult____h541724[16] && + !_theResult____h541724[15] && + !_theResult____h541724[14] && + !_theResult____h541724[13] && + !_theResult____h541724[12] && + !_theResult____h541724[11] && + !_theResult____h541724[10] && + !_theResult____h541724[9] && + !_theResult____h541724[8] && + !_theResult____h541724[7] && + !_theResult____h541724[6] && + !_theResult____h541724[5] && + !_theResult____h541724[4] && + !_theResult____h541724[3] && + !_theResult____h541724[2] && + !_theResult____h541724[1] && + !_theResult____h541724[0]) ? + _theResult____h541724 : + _theResult___snd__h550000 ; + assign _theResult___snd__h550000 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h550022 = - _theResult____h541723 << + assign _theResult___snd__h550023 = + _theResult____h541724 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 ; - assign _theResult___snd__h558738 = - (f2_exp__h521135 == 8'd0) ? - _theResult___snd__h558752 : - _theResult___snd__h540335 ; - assign _theResult___snd__h558752 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___snd__h558739 = + (f2_exp__h521136 == 8'd0) ? + _theResult___snd__h558753 : + _theResult___snd__h540336 ; + assign _theResult___snd__h558753 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521497 : - _theResult___snd__h558758 ; - assign _theResult___snd__h558758 = + sfd__h521498 : + _theResult___snd__h558759 ; + assign _theResult___snd__h558759 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h558776 = - sfd__h521497 << + assign _theResult___snd__h558777 = + sfd__h521498 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ; - assign _theResult___snd__h579637 = - (f3_exp__h560439 == 8'd0) ? - _theResult___snd__h579646 : - _theResult___snd__h579639 ; - assign _theResult___snd__h579639 = { f3_sfd__h560440, 34'd0 } ; - assign _theResult___snd__h579646 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___snd__h579638 = + (f3_exp__h560440 == 8'd0) ? + _theResult___snd__h579647 : + _theResult___snd__h579640 ; + assign _theResult___snd__h579640 = { f3_sfd__h560441, 34'd0 } ; + assign _theResult___snd__h579647 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560801 : - _theResult___snd__h579652 ; - assign _theResult___snd__h579652 = + sfd__h560802 : + _theResult___snd__h579653 ; + assign _theResult___snd__h579653 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h579675 = - sfd__h560801 << + assign _theResult___snd__h579676 = + sfd__h560802 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 ; - assign _theResult___snd__h589274 = { _theResult____h581027[55:0], 1'd0 } ; - assign _theResult___snd__h589285 = - (!_theResult____h581027[56] && _theResult____h581027[55]) ? - _theResult___snd__h589287 : - _theResult___snd__h589297 ; - assign _theResult___snd__h589287 = { _theResult____h581027[54:0], 2'd0 } ; - assign _theResult___snd__h589297 = - (!_theResult____h581027[56] && !_theResult____h581027[55] && - !_theResult____h581027[54] && - !_theResult____h581027[53] && - !_theResult____h581027[52] && - !_theResult____h581027[51] && - !_theResult____h581027[50] && - !_theResult____h581027[49] && - !_theResult____h581027[48] && - !_theResult____h581027[47] && - !_theResult____h581027[46] && - !_theResult____h581027[45] && - !_theResult____h581027[44] && - !_theResult____h581027[43] && - !_theResult____h581027[42] && - !_theResult____h581027[41] && - !_theResult____h581027[40] && - !_theResult____h581027[39] && - !_theResult____h581027[38] && - !_theResult____h581027[37] && - !_theResult____h581027[36] && - !_theResult____h581027[35] && - !_theResult____h581027[34] && - !_theResult____h581027[33] && - !_theResult____h581027[32] && - !_theResult____h581027[31] && - !_theResult____h581027[30] && - !_theResult____h581027[29] && - !_theResult____h581027[28] && - !_theResult____h581027[27] && - !_theResult____h581027[26] && - !_theResult____h581027[25] && - !_theResult____h581027[24] && - !_theResult____h581027[23] && - !_theResult____h581027[22] && - !_theResult____h581027[21] && - !_theResult____h581027[20] && - !_theResult____h581027[19] && - !_theResult____h581027[18] && - !_theResult____h581027[17] && - !_theResult____h581027[16] && - !_theResult____h581027[15] && - !_theResult____h581027[14] && - !_theResult____h581027[13] && - !_theResult____h581027[12] && - !_theResult____h581027[11] && - !_theResult____h581027[10] && - !_theResult____h581027[9] && - !_theResult____h581027[8] && - !_theResult____h581027[7] && - !_theResult____h581027[6] && - !_theResult____h581027[5] && - !_theResult____h581027[4] && - !_theResult____h581027[3] && - !_theResult____h581027[2] && - !_theResult____h581027[1] && - !_theResult____h581027[0]) ? - _theResult____h581027 : - _theResult___snd__h589303 ; - assign _theResult___snd__h589303 = + assign _theResult___snd__h589275 = { _theResult____h581028[55:0], 1'd0 } ; + assign _theResult___snd__h589286 = + (!_theResult____h581028[56] && _theResult____h581028[55]) ? + _theResult___snd__h589288 : + _theResult___snd__h589298 ; + assign _theResult___snd__h589288 = { _theResult____h581028[54:0], 2'd0 } ; + assign _theResult___snd__h589298 = + (!_theResult____h581028[56] && !_theResult____h581028[55] && + !_theResult____h581028[54] && + !_theResult____h581028[53] && + !_theResult____h581028[52] && + !_theResult____h581028[51] && + !_theResult____h581028[50] && + !_theResult____h581028[49] && + !_theResult____h581028[48] && + !_theResult____h581028[47] && + !_theResult____h581028[46] && + !_theResult____h581028[45] && + !_theResult____h581028[44] && + !_theResult____h581028[43] && + !_theResult____h581028[42] && + !_theResult____h581028[41] && + !_theResult____h581028[40] && + !_theResult____h581028[39] && + !_theResult____h581028[38] && + !_theResult____h581028[37] && + !_theResult____h581028[36] && + !_theResult____h581028[35] && + !_theResult____h581028[34] && + !_theResult____h581028[33] && + !_theResult____h581028[32] && + !_theResult____h581028[31] && + !_theResult____h581028[30] && + !_theResult____h581028[29] && + !_theResult____h581028[28] && + !_theResult____h581028[27] && + !_theResult____h581028[26] && + !_theResult____h581028[25] && + !_theResult____h581028[24] && + !_theResult____h581028[23] && + !_theResult____h581028[22] && + !_theResult____h581028[21] && + !_theResult____h581028[20] && + !_theResult____h581028[19] && + !_theResult____h581028[18] && + !_theResult____h581028[17] && + !_theResult____h581028[16] && + !_theResult____h581028[15] && + !_theResult____h581028[14] && + !_theResult____h581028[13] && + !_theResult____h581028[12] && + !_theResult____h581028[11] && + !_theResult____h581028[10] && + !_theResult____h581028[9] && + !_theResult____h581028[8] && + !_theResult____h581028[7] && + !_theResult____h581028[6] && + !_theResult____h581028[5] && + !_theResult____h581028[4] && + !_theResult____h581028[3] && + !_theResult____h581028[2] && + !_theResult____h581028[1] && + !_theResult____h581028[0]) ? + _theResult____h581028 : + _theResult___snd__h589304 ; + assign _theResult___snd__h589304 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h589326 = - _theResult____h581027 << + assign _theResult___snd__h589327 = + _theResult____h581028 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 ; - assign _theResult___snd__h598042 = - (f3_exp__h560439 == 8'd0) ? - _theResult___snd__h598056 : - _theResult___snd__h579639 ; - assign _theResult___snd__h598056 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___snd__h598043 = + (f3_exp__h560440 == 8'd0) ? + _theResult___snd__h598057 : + _theResult___snd__h579640 ; + assign _theResult___snd__h598057 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560801 : - _theResult___snd__h598062 ; - assign _theResult___snd__h598062 = + sfd__h560802 : + _theResult___snd__h598063 ; + assign _theResult___snd__h598063 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h598080 = - sfd__h560801 << + assign _theResult___snd__h598081 = + sfd__h560802 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ; - assign _theResult___snd__h603372 = - b__h602950[63] ? b___1__h603421 : b__h602950 ; - assign _theResult___snd_fst_exp__h363379 = + assign _theResult___snd__h603373 = + b__h602951[63] ? b___1__h603422 : b__h602951 ; + assign _theResult___snd_fst_exp__h363380 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_exp__h354794 : - _theResult___fst_exp__h363376 ; - assign _theResult___snd_fst_exp__h381199 = + _theResult___fst_exp__h354795 : + _theResult___fst_exp__h363377 ; + assign _theResult___snd_fst_exp__h381200 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_exp__h372560 : - _theResult___fst_exp__h381196 ; - assign _theResult___snd_fst_exp__h409076 = + _theResult___fst_exp__h372561 : + _theResult___fst_exp__h381197 ; + assign _theResult___snd_fst_exp__h409077 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_exp__h400491 : - _theResult___fst_exp__h409073 ; - assign _theResult___snd_fst_exp__h426896 = + _theResult___fst_exp__h400492 : + _theResult___fst_exp__h409074 ; + assign _theResult___snd_fst_exp__h426897 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_exp__h418257 : - _theResult___fst_exp__h426893 ; - assign _theResult___snd_fst_exp__h454771 = + _theResult___fst_exp__h418258 : + _theResult___fst_exp__h426894 ; + assign _theResult___snd_fst_exp__h454772 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_exp__h446186 : - _theResult___fst_exp__h454768 ; - assign _theResult___snd_fst_exp__h472591 = + _theResult___fst_exp__h446187 : + _theResult___fst_exp__h454769 ; + assign _theResult___snd_fst_exp__h472592 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_exp__h463952 : - _theResult___fst_exp__h472588 ; - assign _theResult___snd_fst_exp__h502290 = + _theResult___fst_exp__h463953 : + _theResult___fst_exp__h472589 ; + assign _theResult___snd_fst_exp__h502291 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 11'd0 : - _theResult___fst_exp__h502287 ; - assign _theResult___snd_fst_exp__h520725 = + _theResult___fst_exp__h502288 ; + assign _theResult___snd_fst_exp__h520726 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_exp__h511938 : - _theResult___fst_exp__h520722 ; - assign _theResult___snd_fst_exp__h541143 = + _theResult___fst_exp__h511939 : + _theResult___fst_exp__h520723 ; + assign _theResult___snd_fst_exp__h541144 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 11'd0 : - _theResult___fst_exp__h541140 ; - assign _theResult___snd_fst_exp__h559578 = + _theResult___fst_exp__h541141 ; + assign _theResult___snd_fst_exp__h559579 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_exp__h550791 : - _theResult___fst_exp__h559575 ; - assign _theResult___snd_fst_exp__h580447 = + _theResult___fst_exp__h550792 : + _theResult___fst_exp__h559576 ; + assign _theResult___snd_fst_exp__h580448 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 11'd0 : - _theResult___fst_exp__h580444 ; - assign _theResult___snd_fst_exp__h598882 = + _theResult___fst_exp__h580445 ; + assign _theResult___snd_fst_exp__h598883 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_exp__h590095 : - _theResult___fst_exp__h598879 ; - assign _theResult___snd_fst_sfd__h338431 = + _theResult___fst_exp__h590096 : + _theResult___fst_exp__h598880 ; + assign _theResult___snd_fst_sfd__h338432 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h363380 = + assign _theResult___snd_fst_sfd__h363381 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_sfd__h354795 : - _theResult___fst_sfd__h363377 ; - assign _theResult___snd_fst_sfd__h381200 = + _theResult___fst_sfd__h354796 : + _theResult___fst_sfd__h363378 ; + assign _theResult___snd_fst_sfd__h381201 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_sfd__h372561 : - _theResult___fst_sfd__h381197 ; - assign _theResult___snd_fst_sfd__h384133 = + _theResult___fst_sfd__h372562 : + _theResult___fst_sfd__h381198 ; + assign _theResult___snd_fst_sfd__h384134 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h409077 = + assign _theResult___snd_fst_sfd__h409078 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_sfd__h400492 : - _theResult___fst_sfd__h409074 ; - assign _theResult___snd_fst_sfd__h426897 = + _theResult___fst_sfd__h400493 : + _theResult___fst_sfd__h409075 ; + assign _theResult___snd_fst_sfd__h426898 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_sfd__h418258 : - _theResult___fst_sfd__h426894 ; - assign _theResult___snd_fst_sfd__h429828 = + _theResult___fst_sfd__h418259 : + _theResult___fst_sfd__h426895 ; + assign _theResult___snd_fst_sfd__h429829 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h454772 = + assign _theResult___snd_fst_sfd__h454773 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_sfd__h446187 : - _theResult___fst_sfd__h454769 ; - assign _theResult___snd_fst_sfd__h472592 = + _theResult___fst_sfd__h446188 : + _theResult___fst_sfd__h454770 ; + assign _theResult___snd_fst_sfd__h472593 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_sfd__h463953 : - _theResult___fst_sfd__h472589 ; - assign _theResult___snd_fst_sfd__h482457 = - (f1_sfd__h482142 == 23'd0) ? + _theResult___fst_sfd__h463954 : + _theResult___fst_sfd__h472590 ; + assign _theResult___snd_fst_sfd__h482458 = + (f1_sfd__h482143 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h482205 ; - assign _theResult___snd_fst_sfd__h502291 = + out___1_sfd__h482206 ; + assign _theResult___snd_fst_sfd__h502292 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 52'd0 : - _theResult___fst_sfd__h502288 ; - assign _theResult___snd_fst_sfd__h520726 = + _theResult___fst_sfd__h502289 ; + assign _theResult___snd_fst_sfd__h520727 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_sfd__h511939 : - _theResult___fst_sfd__h520723 ; - assign _theResult___snd_fst_sfd__h521451 = - (f2_sfd__h521136 == 23'd0) ? + _theResult___fst_sfd__h511940 : + _theResult___fst_sfd__h520724 ; + assign _theResult___snd_fst_sfd__h521452 = + (f2_sfd__h521137 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h521199 ; - assign _theResult___snd_fst_sfd__h541144 = + out___1_sfd__h521200 ; + assign _theResult___snd_fst_sfd__h541145 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 52'd0 : - _theResult___fst_sfd__h541141 ; - assign _theResult___snd_fst_sfd__h559579 = + _theResult___fst_sfd__h541142 ; + assign _theResult___snd_fst_sfd__h559580 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_sfd__h550792 : - _theResult___fst_sfd__h559576 ; - assign _theResult___snd_fst_sfd__h560755 = - (f3_sfd__h560440 == 23'd0) ? + _theResult___fst_sfd__h550793 : + _theResult___fst_sfd__h559577 ; + assign _theResult___snd_fst_sfd__h560756 = + (f3_sfd__h560441 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h560503 ; - assign _theResult___snd_fst_sfd__h580448 = + out___1_sfd__h560504 ; + assign _theResult___snd_fst_sfd__h580449 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 52'd0 : - _theResult___fst_sfd__h580445 ; - assign _theResult___snd_fst_sfd__h598883 = + _theResult___fst_sfd__h580446 ; + assign _theResult___snd_fst_sfd__h598884 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_sfd__h590096 : - _theResult___fst_sfd__h598880 ; - assign a___1__h603090 = + _theResult___fst_sfd__h590097 : + _theResult___fst_sfd__h598881 ; + assign a___1__h603091 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ; - assign a___1__h603376 = 64'd0 - a__h602949 ; - assign a__h602949 = + assign a___1__h603377 = 64'd0 - a__h602950 ; + assign a__h602950 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h603090 : + a___1__h603091 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h603091 = + assign b___1__h603092 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h603421 = 64'd0 - b__h602950 ; - assign b__h602950 = + assign b___1__h603422 = 64'd0 - b__h602951 ; + assign b__h602951 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h603091 : + b___1__h603092 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h712403 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h712423 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h709443 = - commitStage_commitTrap[36] ? i__h709618 : i__h709458 ; + assign base__h712404 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h712424 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h709444 = + commitStage_commitTrap[36] ? i__h709619 : i__h709459 ; assign commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && @@ -29592,10 +29592,10 @@ module mkCore(CLK, commitStage_f_rob_data$D_OUT[166] ? CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, - trap_val__h709444, + trap_val__h709445, IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926 } ; assign commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15456 = - commitStage_rg_serial_num + y__h730489 ; + commitStage_rg_serial_num + y__h730360 ; assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29743,9 +29743,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29753,9 +29753,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29763,9 +29763,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29773,9 +29773,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29783,9 +29783,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -29825,7 +29825,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h254804 ; + y__h254805 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 || @@ -30043,15 +30043,15 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_deqReq_rl) && coreFix_memExe_forwardQ_full ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706 = - { coreFix_memExe_lsq$getOrigBE << x__h183903[2:0], - x__h183903, + { coreFix_memExe_lsq$getOrigBE << x__h183904[2:0], + x__h183904, coreFix_memExe_regToExeQ$first[75:12], coreFix_memExe_lsq$getOrigBE, coreFix_memExe_lsq$getOrigBE[7] ? - x__h183903[2:0] != 3'd0 : + x__h183904[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - x__h183903[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && x__h183903[0]) } ; + x__h183904[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && x__h183904[0]) } ; assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 = coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 || @@ -30128,7 +30128,7 @@ module mkCore(CLK, v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign csr_addr__h655327 = + assign csr_addr__h655328 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 : 12'hCFF ; @@ -30144,7 +30144,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 || csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 || - csr_addr__h655327 == 12'h8FF) ; + csr_addr__h655328 == 12'h8FF) ; assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -30176,24 +30176,24 @@ module mkCore(CLK, _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716) ; assign csrf_prv_reg_read__2787_ULE_1___d14696 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 = - csrf_prv_reg < csr_addr__h655327[9:8] ; + csrf_prv_reg < csr_addr__h655328[9:8] ; assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435 ; - assign data75283_BITS_31_TO_0__q13 = data__h475283[31:0] ; - assign data___1__h475009 = + assign data75284_BITS_31_TO_0__q13 = data__h475284[31:0] ; + assign data___1__h475010 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; - assign data___1__h475817 = - { {32{data75283_BITS_31_TO_0__q13[31]}}, - data75283_BITS_31_TO_0__q13 } ; - assign data__h475283 = + assign data___1__h475818 = + { {32{data75284_BITS_31_TO_0__q13[31]}}, + data75284_BITS_31_TO_0__q13 } ; + assign data__h475284 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h475197 : - x_remainder__h475198 ; - assign dcsr_cause__h708962 = + x_quotient__h475198 : + x_remainder__h475199 ; + assign dcsr_cause__h708963 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30210,31 +30210,31 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h381230 = _theResult___fst_exp__h354197 + 8'd1 ; - assign din_inc___2_exp__h381254 = _theResult___fst_exp__h362853 + 8'd1 ; - assign din_inc___2_exp__h381284 = _theResult___fst_exp__h371963 + 8'd1 ; - assign din_inc___2_exp__h381308 = _theResult___fst_exp__h380648 + 8'd1 ; - assign din_inc___2_exp__h426927 = _theResult___fst_exp__h399894 + 8'd1 ; - assign din_inc___2_exp__h426951 = _theResult___fst_exp__h408550 + 8'd1 ; - assign din_inc___2_exp__h426981 = _theResult___fst_exp__h417660 + 8'd1 ; - assign din_inc___2_exp__h427005 = _theResult___fst_exp__h426345 + 8'd1 ; - assign din_inc___2_exp__h472622 = _theResult___fst_exp__h445589 + 8'd1 ; - assign din_inc___2_exp__h472646 = _theResult___fst_exp__h454245 + 8'd1 ; - assign din_inc___2_exp__h472676 = _theResult___fst_exp__h463355 + 8'd1 ; - assign din_inc___2_exp__h472700 = _theResult___fst_exp__h472040 + 8'd1 ; - assign din_inc___2_exp__h520779 = _theResult___fst_exp__h501529 + 11'd1 ; - assign din_inc___2_exp__h520814 = _theResult___fst_exp__h511106 + 11'd1 ; - assign din_inc___2_exp__h520840 = _theResult___fst_exp__h519939 + 11'd1 ; - assign din_inc___2_exp__h559632 = _theResult___fst_exp__h540382 + 11'd1 ; - assign din_inc___2_exp__h559667 = _theResult___fst_exp__h549959 + 11'd1 ; - assign din_inc___2_exp__h559693 = _theResult___fst_exp__h558792 + 11'd1 ; - assign din_inc___2_exp__h598936 = _theResult___fst_exp__h579686 + 11'd1 ; - assign din_inc___2_exp__h598971 = _theResult___fst_exp__h589263 + 11'd1 ; - assign din_inc___2_exp__h598997 = _theResult___fst_exp__h598096 + 11'd1 ; - assign enabled_ints___1__h651643 = pend_ints__h651116 & y__h651655 ; - assign enabled_ints__h651689 = - pend_ints__h651116 & - { r1__read_BITS_13_TO_0___h651665, csrf_mideleg_1_0_reg } ; + assign din_inc___2_exp__h381231 = _theResult___fst_exp__h354198 + 8'd1 ; + assign din_inc___2_exp__h381255 = _theResult___fst_exp__h362854 + 8'd1 ; + assign din_inc___2_exp__h381285 = _theResult___fst_exp__h371964 + 8'd1 ; + assign din_inc___2_exp__h381309 = _theResult___fst_exp__h380649 + 8'd1 ; + assign din_inc___2_exp__h426928 = _theResult___fst_exp__h399895 + 8'd1 ; + assign din_inc___2_exp__h426952 = _theResult___fst_exp__h408551 + 8'd1 ; + assign din_inc___2_exp__h426982 = _theResult___fst_exp__h417661 + 8'd1 ; + assign din_inc___2_exp__h427006 = _theResult___fst_exp__h426346 + 8'd1 ; + assign din_inc___2_exp__h472623 = _theResult___fst_exp__h445590 + 8'd1 ; + assign din_inc___2_exp__h472647 = _theResult___fst_exp__h454246 + 8'd1 ; + assign din_inc___2_exp__h472677 = _theResult___fst_exp__h463356 + 8'd1 ; + assign din_inc___2_exp__h472701 = _theResult___fst_exp__h472041 + 8'd1 ; + assign din_inc___2_exp__h520780 = _theResult___fst_exp__h501530 + 11'd1 ; + assign din_inc___2_exp__h520815 = _theResult___fst_exp__h511107 + 11'd1 ; + assign din_inc___2_exp__h520841 = _theResult___fst_exp__h519940 + 11'd1 ; + assign din_inc___2_exp__h559633 = _theResult___fst_exp__h540383 + 11'd1 ; + assign din_inc___2_exp__h559668 = _theResult___fst_exp__h549960 + 11'd1 ; + assign din_inc___2_exp__h559694 = _theResult___fst_exp__h558793 + 11'd1 ; + assign din_inc___2_exp__h598937 = _theResult___fst_exp__h579687 + 11'd1 ; + assign din_inc___2_exp__h598972 = _theResult___fst_exp__h589264 + 11'd1 ; + assign din_inc___2_exp__h598998 = _theResult___fst_exp__h598097 + 11'd1 ; + assign enabled_ints___1__h651644 = pend_ints__h651117 & y__h651656 ; + assign enabled_ints__h651690 = + pend_ints__h651117 & + { r1__read_BITS_13_TO_0___h651666, csrf_mideleg_1_0_reg } ; assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || @@ -30256,34 +30256,34 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 && IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890) ; - assign f1_exp82141_MINUS_127__q136 = f1_exp__h482141 - 8'd127 ; - assign f1_exp__h482141 = + assign f1_exp82142_MINUS_127__q136 = f1_exp__h482142 - 8'd127 ; + assign f1_exp__h482142 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h482142 = + assign f1_sfd__h482143 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp21135_MINUS_127__q176 = f2_exp__h521135 - 8'd127 ; - assign f2_exp__h521135 = + assign f2_exp21136_MINUS_127__q176 = f2_exp__h521136 - 8'd127 ; + assign f2_exp__h521136 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h521136 = + assign f2_sfd__h521137 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp60439_MINUS_127__q153 = f3_exp__h560439 - 8'd127 ; - assign f3_exp__h560439 = + assign f3_exp60440_MINUS_127__q153 = f3_exp__h560440 - 8'd127 ; + assign f3_exp__h560440 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h560440 = + assign f3_sfd__h560441 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; @@ -30293,7 +30293,7 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h609377 = { 56'd0, x__h613035 } ; + assign fcsr_csr__read__h609378 = { 56'd0, x__h613036 } ; assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || @@ -30374,9 +30374,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h655328 != 5'd0 || - imm__h655329 != 32'd0) && - csr_addr__h655327[11:10] == 2'b11 ; + rs1__h655329 != 5'd0 || + imm__h655330 != 32'd0) && + csr_addr__h655328[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -30483,7 +30483,7 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h728014 = + assign fflags__h727885 = ({ rob$deqPort_0_deq_data[361:356], 1'd0, rob$deqPort_0_deq_data[354:350], @@ -30493,8 +30493,8 @@ module mkCore(CLK, rob$deqPort_0_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h727999 ; - assign fflags__h730667 = + po_fflags__h727870 ; + assign fflags__h730538 = ({ rob$deqPort_1_deq_data[361:356], 1'd0, rob$deqPort_1_deq_data[354:350], @@ -30504,105 +30504,105 @@ module mkCore(CLK, rob$deqPort_1_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h730652 ; - assign fflags__h733287 = + po_fflags__h730523 ; + assign fflags__h733158 = NOT_rob_deqPort_0_canDeq__5320_5321_OR_rob_deq_ETC___d15664 ? - y_avValue_fst__h733224 : + y_avValue_fst__h733095 : IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 ; - assign fflags_csr__read__h609352 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h609363 = { 61'd0, csrf_frm_reg } ; - assign guard__h346096 = - { IF_sfdin54191_BIT_33_THEN_2_ELSE_0__q29[1], - { sfdin__h354191[32:0], 23'd0 } != 56'd0 } ; - assign guard__h354805 = - { IF_theResult___snd62804_BIT_33_THEN_2_ELSE_0__q31[1], - { _theResult___snd__h362804[32:0], 23'd0 } != 56'd0 } ; - assign guard__h363735 = - { IF_sfdin71957_BIT_33_THEN_2_ELSE_0__q39[1], - { sfdin__h371957[32:0], 23'd0 } != 56'd0 } ; - assign guard__h364333 = x__h364435 != 57'd0 ; - assign guard__h372571 = - { IF_theResult___snd80594_BIT_33_THEN_2_ELSE_0__q44[1], - { _theResult___snd__h380594[32:0], 23'd0 } != 56'd0 } ; - assign guard__h391795 = - { IF_sfdin99888_BIT_33_THEN_2_ELSE_0__q64[1], - { sfdin__h399888[32:0], 23'd0 } != 56'd0 } ; - assign guard__h400502 = - { IF_theResult___snd08501_BIT_33_THEN_2_ELSE_0__q66[1], - { _theResult___snd__h408501[32:0], 23'd0 } != 56'd0 } ; - assign guard__h409432 = - { IF_sfdin17654_BIT_33_THEN_2_ELSE_0__q74[1], - { sfdin__h417654[32:0], 23'd0 } != 56'd0 } ; - assign guard__h410030 = x__h410132 != 57'd0 ; - assign guard__h418268 = - { IF_theResult___snd26291_BIT_33_THEN_2_ELSE_0__q79[1], - { _theResult___snd__h426291[32:0], 23'd0 } != 56'd0 } ; - assign guard__h437490 = - { IF_sfdin45583_BIT_33_THEN_2_ELSE_0__q99[1], - { sfdin__h445583[32:0], 23'd0 } != 56'd0 } ; - assign guard__h446197 = - { IF_theResult___snd54196_BIT_33_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h454196[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455127 = - { IF_sfdin63349_BIT_33_THEN_2_ELSE_0__q109[1], - { sfdin__h463349[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455725 = x__h455827 != 57'd0 ; - assign guard__h463963 = - { IF_theResult___snd71986_BIT_33_THEN_2_ELSE_0__q114[1], - { _theResult___snd__h471986[32:0], 23'd0 } != 56'd0 } ; - assign guard__h493568 = - { IF_theResult___snd01480_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h501480[3:0], 52'd0 } != 56'd0 } ; - assign guard__h502880 = - { IF_sfdin11100_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h511100[3:0], 52'd0 } != 56'd0 } ; - assign guard__h503478 = x__h503578 != 57'd0 ; - assign guard__h511949 = - { IF_theResult___snd19885_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h519885[3:0], 52'd0 } != 56'd0 } ; - assign guard__h532421 = - { IF_theResult___snd40333_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h540333[3:0], 52'd0 } != 56'd0 } ; - assign guard__h541733 = - { IF_sfdin49953_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h549953[3:0], 52'd0 } != 56'd0 } ; - assign guard__h542331 = x__h542431 != 57'd0 ; - assign guard__h550802 = - { IF_theResult___snd58738_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h558738[3:0], 52'd0 } != 56'd0 } ; - assign guard__h571725 = - { IF_theResult___snd79637_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h579637[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581037 = - { IF_sfdin89257_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h589257[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581635 = x__h581735 != 57'd0 ; - assign guard__h590106 = - { IF_theResult___snd98042_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h598042[3:0], 52'd0 } != 56'd0 } ; - assign idx__h685370 = + assign fflags_csr__read__h609353 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h609364 = { 61'd0, csrf_frm_reg } ; + assign guard__h346097 = + { IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29[1], + { sfdin__h354192[32:0], 23'd0 } != 56'd0 } ; + assign guard__h354806 = + { IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31[1], + { _theResult___snd__h362805[32:0], 23'd0 } != 56'd0 } ; + assign guard__h363736 = + { IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39[1], + { sfdin__h371958[32:0], 23'd0 } != 56'd0 } ; + assign guard__h364334 = x__h364436 != 57'd0 ; + assign guard__h372572 = + { IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44[1], + { _theResult___snd__h380595[32:0], 23'd0 } != 56'd0 } ; + assign guard__h391796 = + { IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64[1], + { sfdin__h399889[32:0], 23'd0 } != 56'd0 } ; + assign guard__h400503 = + { IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66[1], + { _theResult___snd__h408502[32:0], 23'd0 } != 56'd0 } ; + assign guard__h409433 = + { IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74[1], + { sfdin__h417655[32:0], 23'd0 } != 56'd0 } ; + assign guard__h410031 = x__h410133 != 57'd0 ; + assign guard__h418269 = + { IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79[1], + { _theResult___snd__h426292[32:0], 23'd0 } != 56'd0 } ; + assign guard__h437491 = + { IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99[1], + { sfdin__h445584[32:0], 23'd0 } != 56'd0 } ; + assign guard__h446198 = + { IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101[1], + { _theResult___snd__h454197[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455128 = + { IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109[1], + { sfdin__h463350[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455726 = x__h455828 != 57'd0 ; + assign guard__h463964 = + { IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114[1], + { _theResult___snd__h471987[32:0], 23'd0 } != 56'd0 } ; + assign guard__h493569 = + { IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h501481[3:0], 52'd0 } != 56'd0 } ; + assign guard__h502881 = + { IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h511101[3:0], 52'd0 } != 56'd0 } ; + assign guard__h503479 = x__h503579 != 57'd0 ; + assign guard__h511950 = + { IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h519886[3:0], 52'd0 } != 56'd0 } ; + assign guard__h532422 = + { IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h540334[3:0], 52'd0 } != 56'd0 } ; + assign guard__h541734 = + { IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h549954[3:0], 52'd0 } != 56'd0 } ; + assign guard__h542332 = x__h542432 != 57'd0 ; + assign guard__h550803 = + { IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h558739[3:0], 52'd0 } != 56'd0 } ; + assign guard__h571726 = + { IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h579638[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581038 = + { IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h589258[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581636 = x__h581736 != 57'd0 ; + assign guard__h590107 = + { IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h598043[3:0], 52'd0 } != 56'd0 } ; + assign idx__h685371 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 || !coreFix_aluExe_0_rsAlu$canEnq || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770 ; - assign imm__h655329 = + assign imm__h655330 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h669625 = + assign k__h669626 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ; - assign mcause_csr__read__h611019 = - { r1__read__h614498, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h610764 = - { r1__read__h614485, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h610371 = - { r1__read__h614346, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h610466 = - { r1__read__h614363, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h610590 = { r1__read__h614387, 1'b0 } ; - assign mip_csr__read__h611252 = { r1__read__h614504, 1'b0 } ; + assign mcause_csr__read__h611020 = + { r1__read__h614499, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h610765 = + { r1__read__h614486, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h610372 = + { r1__read__h614347, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h610467 = + { r1__read__h614364, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h610591 = { r1__read__h614388, 1'b0 } ; + assign mip_csr__read__h611253 = { r1__read__h614505, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30686,302 +30686,302 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h76123 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h610223 = { r1__read__h614221, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h610672 = - { r1__read__h614480, csrf_mtvec_mode_low_reg } ; - assign n___1__h198530 = + assign msip__h76124 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h610224 = { r1__read__h614222, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h610673 = + { r1__read__h614481, csrf_mtvec_mode_low_reg } ; + assign n___1__h198531 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h197127[63:56], + x__h197128[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h197127[55:48], + x__h197128[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h197127[47:40], + x__h197128[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h197127[39:32], + x__h197128[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h197127[31:24], + x__h197128[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h197127[23:16], + x__h197128[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h197127[15:8], + x__h197128[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h197127[7:0] } ; - assign n__read__h611356 = + x__h197128[7:0] } ; + assign n__read__h611357 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h611547 = + assign n__read__h611548 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6760 = + assign n__read__h6761 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? - upd__h6874 : + upd__h6875 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h726694 = + assign n__read__h726565 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h296801 = + assign next_deqP___1__h296802 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h304797 = + assign next_deqP___1__h304798 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h311078 = + assign next_deqP___1__h311079 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h318932 = + assign next_deqP___1__h318933 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h328989 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h332214 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h722452 = + assign next_deqP___1__h328990 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h332215 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h722453 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign old_fflags__h732774 = + assign old_fflags__h732645 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; - assign out___1_sfd__h482205 = { f1_sfd__h482142, 29'd0 } ; - assign out___1_sfd__h521199 = { f2_sfd__h521136, 29'd0 } ; - assign out___1_sfd__h560503 = { f3_sfd__h560440, 29'd0 } ; - assign out_exp__h354716 = - sfdin__h354191[34] ? - _theResult___exp__h354713 : - _theResult___fst_exp__h354197 ; - assign out_exp__h363298 = - _theResult___snd__h362804[34] ? - _theResult___exp__h363295 : - _theResult___fst_exp__h362853 ; - assign out_exp__h372482 = - sfdin__h371957[34] ? - _theResult___exp__h372479 : - _theResult___fst_exp__h371963 ; - assign out_exp__h381118 = - _theResult___snd__h380594[34] ? - _theResult___exp__h381115 : - _theResult___fst_exp__h380648 ; - assign out_exp__h400413 = - sfdin__h399888[34] ? - _theResult___exp__h400410 : - _theResult___fst_exp__h399894 ; - assign out_exp__h408995 = - _theResult___snd__h408501[34] ? - _theResult___exp__h408992 : - _theResult___fst_exp__h408550 ; - assign out_exp__h418179 = - sfdin__h417654[34] ? - _theResult___exp__h418176 : - _theResult___fst_exp__h417660 ; - assign out_exp__h426815 = - _theResult___snd__h426291[34] ? - _theResult___exp__h426812 : - _theResult___fst_exp__h426345 ; - assign out_exp__h446108 = - sfdin__h445583[34] ? - _theResult___exp__h446105 : - _theResult___fst_exp__h445589 ; - assign out_exp__h454690 = - _theResult___snd__h454196[34] ? - _theResult___exp__h454687 : - _theResult___fst_exp__h454245 ; - assign out_exp__h463874 = - sfdin__h463349[34] ? - _theResult___exp__h463871 : - _theResult___fst_exp__h463355 ; - assign out_exp__h472510 = - _theResult___snd__h471986[34] ? - _theResult___exp__h472507 : - _theResult___fst_exp__h472040 ; - assign out_exp__h502187 = - _theResult___snd__h501480[5] ? - _theResult___exp__h502184 : - _theResult___fst_exp__h501529 ; - assign out_exp__h511838 = - sfdin__h511100[5] ? - _theResult___exp__h511835 : - _theResult___fst_exp__h511106 ; - assign out_exp__h520622 = - _theResult___snd__h519885[5] ? - _theResult___exp__h520619 : - _theResult___fst_exp__h519939 ; - assign out_exp__h541040 = - _theResult___snd__h540333[5] ? - _theResult___exp__h541037 : - _theResult___fst_exp__h540382 ; - assign out_exp__h550691 = - sfdin__h549953[5] ? - _theResult___exp__h550688 : - _theResult___fst_exp__h549959 ; - assign out_exp__h559475 = - _theResult___snd__h558738[5] ? - _theResult___exp__h559472 : - _theResult___fst_exp__h558792 ; - assign out_exp__h580344 = - _theResult___snd__h579637[5] ? - _theResult___exp__h580341 : - _theResult___fst_exp__h579686 ; - assign out_exp__h589995 = - sfdin__h589257[5] ? - _theResult___exp__h589992 : - _theResult___fst_exp__h589263 ; - assign out_exp__h598779 = - _theResult___snd__h598042[5] ? - _theResult___exp__h598776 : - _theResult___fst_exp__h598096 ; - assign out_f_exp__h381494 = - (_theResult___exp__h381217 == 8'd255 && - _theResult___sfd__h381218 != 23'd0 || + assign out___1_sfd__h482206 = { f1_sfd__h482143, 29'd0 } ; + assign out___1_sfd__h521200 = { f2_sfd__h521137, 29'd0 } ; + assign out___1_sfd__h560504 = { f3_sfd__h560441, 29'd0 } ; + assign out_exp__h354717 = + sfdin__h354192[34] ? + _theResult___exp__h354714 : + _theResult___fst_exp__h354198 ; + assign out_exp__h363299 = + _theResult___snd__h362805[34] ? + _theResult___exp__h363296 : + _theResult___fst_exp__h362854 ; + assign out_exp__h372483 = + sfdin__h371958[34] ? + _theResult___exp__h372480 : + _theResult___fst_exp__h371964 ; + assign out_exp__h381119 = + _theResult___snd__h380595[34] ? + _theResult___exp__h381116 : + _theResult___fst_exp__h380649 ; + assign out_exp__h400414 = + sfdin__h399889[34] ? + _theResult___exp__h400411 : + _theResult___fst_exp__h399895 ; + assign out_exp__h408996 = + _theResult___snd__h408502[34] ? + _theResult___exp__h408993 : + _theResult___fst_exp__h408551 ; + assign out_exp__h418180 = + sfdin__h417655[34] ? + _theResult___exp__h418177 : + _theResult___fst_exp__h417661 ; + assign out_exp__h426816 = + _theResult___snd__h426292[34] ? + _theResult___exp__h426813 : + _theResult___fst_exp__h426346 ; + assign out_exp__h446109 = + sfdin__h445584[34] ? + _theResult___exp__h446106 : + _theResult___fst_exp__h445590 ; + assign out_exp__h454691 = + _theResult___snd__h454197[34] ? + _theResult___exp__h454688 : + _theResult___fst_exp__h454246 ; + assign out_exp__h463875 = + sfdin__h463350[34] ? + _theResult___exp__h463872 : + _theResult___fst_exp__h463356 ; + assign out_exp__h472511 = + _theResult___snd__h471987[34] ? + _theResult___exp__h472508 : + _theResult___fst_exp__h472041 ; + assign out_exp__h502188 = + _theResult___snd__h501481[5] ? + _theResult___exp__h502185 : + _theResult___fst_exp__h501530 ; + assign out_exp__h511839 = + sfdin__h511101[5] ? + _theResult___exp__h511836 : + _theResult___fst_exp__h511107 ; + assign out_exp__h520623 = + _theResult___snd__h519886[5] ? + _theResult___exp__h520620 : + _theResult___fst_exp__h519940 ; + assign out_exp__h541041 = + _theResult___snd__h540334[5] ? + _theResult___exp__h541038 : + _theResult___fst_exp__h540383 ; + assign out_exp__h550692 = + sfdin__h549954[5] ? + _theResult___exp__h550689 : + _theResult___fst_exp__h549960 ; + assign out_exp__h559476 = + _theResult___snd__h558739[5] ? + _theResult___exp__h559473 : + _theResult___fst_exp__h558793 ; + assign out_exp__h580345 = + _theResult___snd__h579638[5] ? + _theResult___exp__h580342 : + _theResult___fst_exp__h579687 ; + assign out_exp__h589996 = + sfdin__h589258[5] ? + _theResult___exp__h589993 : + _theResult___fst_exp__h589264 ; + assign out_exp__h598780 = + _theResult___snd__h598043[5] ? + _theResult___exp__h598777 : + _theResult___fst_exp__h598097 ; + assign out_f_exp__h381495 = + (_theResult___exp__h381218 == 8'd255 && + _theResult___sfd__h381219 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381208 ; - assign out_f_exp__h427191 = - (_theResult___exp__h426914 == 8'd255 && - _theResult___sfd__h426915 != 23'd0 || + _theResult___fst_exp__h381209 ; + assign out_f_exp__h427192 = + (_theResult___exp__h426915 == 8'd255 && + _theResult___sfd__h426916 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426905 ; - assign out_f_exp__h472886 = - (_theResult___exp__h472609 == 8'd255 && - _theResult___sfd__h472610 != 23'd0 || + _theResult___fst_exp__h426906 ; + assign out_f_exp__h472887 = + (_theResult___exp__h472610 == 8'd255 && + _theResult___sfd__h472611 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472600 ; - assign out_f_sfd__h381495 = - (_theResult___exp__h381217 == 8'd255 && - _theResult___sfd__h381218 != 23'd0) ? + _theResult___fst_exp__h472601 ; + assign out_f_sfd__h381496 = + (_theResult___exp__h381218 == 8'd255 && + _theResult___sfd__h381219 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h381218 ; - assign out_f_sfd__h427192 = - (_theResult___exp__h426914 == 8'd255 && - _theResult___sfd__h426915 != 23'd0) ? + _theResult___sfd__h381219 ; + assign out_f_sfd__h427193 = + (_theResult___exp__h426915 == 8'd255 && + _theResult___sfd__h426916 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h426915 ; - assign out_f_sfd__h472887 = - (_theResult___exp__h472609 == 8'd255 && - _theResult___sfd__h472610 != 23'd0) ? + _theResult___sfd__h426916 ; + assign out_f_sfd__h472888 = + (_theResult___exp__h472610 == 8'd255 && + _theResult___sfd__h472611 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h472610 ; - assign out_sfd__h354717 = - sfdin__h354191[34] ? - _theResult___sfd__h354714 : - sfdin__h354191[56:34] ; - assign out_sfd__h363299 = - _theResult___snd__h362804[34] ? - _theResult___sfd__h363296 : - _theResult___snd__h362804[56:34] ; - assign out_sfd__h372483 = - sfdin__h371957[34] ? - _theResult___sfd__h372480 : - sfdin__h371957[56:34] ; - assign out_sfd__h381119 = - _theResult___snd__h380594[34] ? - _theResult___sfd__h381116 : - _theResult___snd__h380594[56:34] ; - assign out_sfd__h400414 = - sfdin__h399888[34] ? - _theResult___sfd__h400411 : - sfdin__h399888[56:34] ; - assign out_sfd__h408996 = - _theResult___snd__h408501[34] ? - _theResult___sfd__h408993 : - _theResult___snd__h408501[56:34] ; - assign out_sfd__h418180 = - sfdin__h417654[34] ? - _theResult___sfd__h418177 : - sfdin__h417654[56:34] ; - assign out_sfd__h426816 = - _theResult___snd__h426291[34] ? - _theResult___sfd__h426813 : - _theResult___snd__h426291[56:34] ; - assign out_sfd__h446109 = - sfdin__h445583[34] ? - _theResult___sfd__h446106 : - sfdin__h445583[56:34] ; - assign out_sfd__h454691 = - _theResult___snd__h454196[34] ? - _theResult___sfd__h454688 : - _theResult___snd__h454196[56:34] ; - assign out_sfd__h463875 = - sfdin__h463349[34] ? - _theResult___sfd__h463872 : - sfdin__h463349[56:34] ; - assign out_sfd__h472511 = - _theResult___snd__h471986[34] ? - _theResult___sfd__h472508 : - _theResult___snd__h471986[56:34] ; - assign out_sfd__h502188 = - _theResult___snd__h501480[5] ? - _theResult___sfd__h502185 : - _theResult___snd__h501480[56:5] ; - assign out_sfd__h511839 = - sfdin__h511100[5] ? - _theResult___sfd__h511836 : - sfdin__h511100[56:5] ; - assign out_sfd__h520623 = - _theResult___snd__h519885[5] ? - _theResult___sfd__h520620 : - _theResult___snd__h519885[56:5] ; - assign out_sfd__h541041 = - _theResult___snd__h540333[5] ? - _theResult___sfd__h541038 : - _theResult___snd__h540333[56:5] ; - assign out_sfd__h550692 = - sfdin__h549953[5] ? - _theResult___sfd__h550689 : - sfdin__h549953[56:5] ; - assign out_sfd__h559476 = - _theResult___snd__h558738[5] ? - _theResult___sfd__h559473 : - _theResult___snd__h558738[56:5] ; - assign out_sfd__h580345 = - _theResult___snd__h579637[5] ? - _theResult___sfd__h580342 : - _theResult___snd__h579637[56:5] ; - assign out_sfd__h589996 = - sfdin__h589257[5] ? - _theResult___sfd__h589993 : - sfdin__h589257[56:5] ; - assign out_sfd__h598780 = - _theResult___snd__h598042[5] ? - _theResult___sfd__h598777 : - _theResult___snd__h598042[56:5] ; - assign pc__h712387 = + _theResult___sfd__h472611 ; + assign out_sfd__h354718 = + sfdin__h354192[34] ? + _theResult___sfd__h354715 : + sfdin__h354192[56:34] ; + assign out_sfd__h363300 = + _theResult___snd__h362805[34] ? + _theResult___sfd__h363297 : + _theResult___snd__h362805[56:34] ; + assign out_sfd__h372484 = + sfdin__h371958[34] ? + _theResult___sfd__h372481 : + sfdin__h371958[56:34] ; + assign out_sfd__h381120 = + _theResult___snd__h380595[34] ? + _theResult___sfd__h381117 : + _theResult___snd__h380595[56:34] ; + assign out_sfd__h400415 = + sfdin__h399889[34] ? + _theResult___sfd__h400412 : + sfdin__h399889[56:34] ; + assign out_sfd__h408997 = + _theResult___snd__h408502[34] ? + _theResult___sfd__h408994 : + _theResult___snd__h408502[56:34] ; + assign out_sfd__h418181 = + sfdin__h417655[34] ? + _theResult___sfd__h418178 : + sfdin__h417655[56:34] ; + assign out_sfd__h426817 = + _theResult___snd__h426292[34] ? + _theResult___sfd__h426814 : + _theResult___snd__h426292[56:34] ; + assign out_sfd__h446110 = + sfdin__h445584[34] ? + _theResult___sfd__h446107 : + sfdin__h445584[56:34] ; + assign out_sfd__h454692 = + _theResult___snd__h454197[34] ? + _theResult___sfd__h454689 : + _theResult___snd__h454197[56:34] ; + assign out_sfd__h463876 = + sfdin__h463350[34] ? + _theResult___sfd__h463873 : + sfdin__h463350[56:34] ; + assign out_sfd__h472512 = + _theResult___snd__h471987[34] ? + _theResult___sfd__h472509 : + _theResult___snd__h471987[56:34] ; + assign out_sfd__h502189 = + _theResult___snd__h501481[5] ? + _theResult___sfd__h502186 : + _theResult___snd__h501481[56:5] ; + assign out_sfd__h511840 = + sfdin__h511101[5] ? + _theResult___sfd__h511837 : + sfdin__h511101[56:5] ; + assign out_sfd__h520624 = + _theResult___snd__h519886[5] ? + _theResult___sfd__h520621 : + _theResult___snd__h519886[56:5] ; + assign out_sfd__h541042 = + _theResult___snd__h540334[5] ? + _theResult___sfd__h541039 : + _theResult___snd__h540334[56:5] ; + assign out_sfd__h550693 = + sfdin__h549954[5] ? + _theResult___sfd__h550690 : + sfdin__h549954[56:5] ; + assign out_sfd__h559477 = + _theResult___snd__h558739[5] ? + _theResult___sfd__h559474 : + _theResult___snd__h558739[56:5] ; + assign out_sfd__h580346 = + _theResult___snd__h579638[5] ? + _theResult___sfd__h580343 : + _theResult___snd__h579638[56:5] ; + assign out_sfd__h589997 = + sfdin__h589258[5] ? + _theResult___sfd__h589994 : + sfdin__h589258[56:5] ; + assign out_sfd__h598781 = + _theResult___snd__h598043[5] ? + _theResult___sfd__h598778 : + _theResult___snd__h598043[56:5] ; + assign pc__h712388 = csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? - y_avValue_new_pc__h712179 : - y_avValue_new_pc__h712365 ; - assign pend_ints__h651116 = + y_avValue_new_pc__h712180 : + y_avValue_new_pc__h712366 ; + assign pend_ints__h651117 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h727999 = old_fflags__h732774 ; - assign po_fflags__h730652 = - old_fflags__h732774 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h734956 = csrf_prv_reg ; - assign prv__h735000 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h475882 = + assign po_fflags__h727870 = old_fflags__h732645 ; + assign po_fflags__h730523 = + old_fflags__h732645 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h734827 = csrf_prv_reg ; + assign prv__h734871 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h475883 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h651665 = + assign r1__read_BITS_13_TO_0___h651666 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -30989,116 +30989,116 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h655197 = csrf_fs_reg ; - assign r1__read_BITS_62_TO_14___h729677 = { r1__read__h614245, 2'd0 } ; - assign r1__read_BIT_20___h655893 = csrf_tw_reg ; - assign r1__read__h613050 = { r1__read__h613052, csrf_ie_vec_1 } ; - assign r1__read__h613052 = { r1__read__h613054, 2'b0 } ; - assign r1__read__h613054 = { r1__read__h613056, csrf_prev_ie_vec_0 } ; - assign r1__read__h613056 = { r1__read__h613058, csrf_prev_ie_vec_1 } ; - assign r1__read__h613058 = { r1__read__h613060, 2'b0 } ; - assign r1__read__h613060 = { r1__read__h613062, csrf_spp_reg } ; - assign r1__read__h613062 = { r1__read__h613064, 4'b0 } ; - assign r1__read__h613064 = { r1__read__h613066, csrf_fs_reg } ; - assign r1__read__h613066 = { r1__read__h613068, 2'd0 } ; - assign r1__read__h613068 = { r1__read__h613070, 1'b0 } ; - assign r1__read__h613070 = { r1__read__h613072, csrf_sum_reg } ; - assign r1__read__h613072 = { r1__read__h613074, csrf_mxr_reg } ; - assign r1__read__h613074 = { r1__read__h613076, 12'b0 } ; - assign r1__read__h613076 = { r1__read__h613078, 2'b10 } ; - assign r1__read__h613078 = { csrf_fs_reg == 2'b11, 29'b0 } ; - assign r1__read__h613454 = - { r1__read__h613456, csrf_software_int_en_vec_1 } ; - assign r1__read__h613456 = { r1__read__h613458, 2'b0 } ; - assign r1__read__h613458 = { r1__read__h613460, 1'b0 } ; - assign r1__read__h613460 = { r1__read__h613462, csrf_timer_int_en_vec_1 } ; - assign r1__read__h613462 = { r1__read__h613464, 2'b0 } ; - assign r1__read__h613464 = { r1__read__h613466, 1'b0 } ; - assign r1__read__h613466 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h613964 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h613969 = { r1__read__h613971, csrf_scounteren_tm_reg } ; - assign r1__read__h613971 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h613982 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h613988 = - { r1__read__h613990, csrf_software_int_pend_vec_1 } ; - assign r1__read__h613990 = { r1__read__h613992, 2'b0 } ; - assign r1__read__h613992 = { r1__read__h613994, 1'b0 } ; - assign r1__read__h613994 = - { r1__read__h613996, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h613996 = { r1__read__h613998, 2'b0 } ; - assign r1__read__h613998 = { r1__read__h614000, 1'b0 } ; - assign r1__read__h614000 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614198 = { vm_mode_reg__read__h614204, 16'd0 } ; - assign r1__read__h614221 = { r1__read__h614223, csrf_ie_vec_1 } ; - assign r1__read__h614223 = { r1__read__h614225, 1'b0 } ; - assign r1__read__h614225 = { r1__read__h614227, csrf_ie_vec_3 } ; - assign r1__read__h614227 = { r1__read__h614229, csrf_prev_ie_vec_0 } ; - assign r1__read__h614229 = { r1__read__h614231, csrf_prev_ie_vec_1 } ; - assign r1__read__h614231 = { r1__read__h614233, 1'b0 } ; - assign r1__read__h614233 = { r1__read__h614235, csrf_prev_ie_vec_3 } ; - assign r1__read__h614235 = { r1__read__h614237, csrf_spp_reg } ; - assign r1__read__h614237 = { r1__read__h614239, 2'b0 } ; - assign r1__read__h614239 = { r1__read__h614241, csrf_mpp_reg } ; - assign r1__read__h614241 = - { r1__read_BITS_62_TO_14___h729677, csrf_fs_reg } ; - assign r1__read__h614245 = { r1__read__h614247, csrf_mprv_reg } ; - assign r1__read__h614247 = { r1__read__h614249, csrf_sum_reg } ; - assign r1__read__h614249 = { r1__read__h614251, csrf_mxr_reg } ; - assign r1__read__h614251 = { r1__read__h614253, csrf_tvm_reg } ; - assign r1__read__h614253 = { r1__read__h614255, csrf_tw_reg } ; - assign r1__read__h614255 = { r1__read__h614257, csrf_tsr_reg } ; - assign r1__read__h614257 = { r1__read__h614259, 9'b0 } ; - assign r1__read__h614259 = { r1__read__h614261, 2'b10 } ; - assign r1__read__h614261 = { r1__read__h614263, 2'b10 } ; - assign r1__read__h614263 = { csrf_fs_reg == 2'b11, 27'b0 } ; - assign r1__read__h614346 = { r1__read__h614348, 1'b0 } ; - assign r1__read__h614348 = { r1__read__h614350, csrf_medeleg_13_11_reg } ; - assign r1__read__h614350 = { r1__read__h614352, 1'b0 } ; - assign r1__read__h614352 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h614363 = { r1__read__h614365, 1'b0 } ; - assign r1__read__h614365 = { r1__read__h614367, csrf_mideleg_5_3_reg } ; - assign r1__read__h614367 = { r1__read__h614369, 1'b0 } ; - assign r1__read__h614369 = { r1__read__h614371, csrf_mideleg_9_7_reg } ; - assign r1__read__h614371 = { r1__read__h614373, 1'b0 } ; - assign r1__read__h614373 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h614387 = - { r1__read__h614389, csrf_software_int_en_vec_1 } ; - assign r1__read__h614389 = { r1__read__h614391, 1'b0 } ; - assign r1__read__h614391 = - { r1__read__h614393, csrf_software_int_en_vec_3 } ; - assign r1__read__h614393 = { r1__read__h614395, 1'b0 } ; - assign r1__read__h614395 = { r1__read__h614397, csrf_timer_int_en_vec_1 } ; - assign r1__read__h614397 = { r1__read__h614399, 1'b0 } ; - assign r1__read__h614399 = { r1__read__h614401, csrf_timer_int_en_vec_3 } ; - assign r1__read__h614401 = { r1__read__h614403, 1'b0 } ; - assign r1__read__h614403 = - { r1__read__h614405, csrf_external_int_en_vec_1 } ; - assign r1__read__h614405 = { r1__read__h614407, 1'b0 } ; - assign r1__read__h614407 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h614480 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h614485 = { r1__read__h614487, csrf_mcounteren_tm_reg } ; - assign r1__read__h614487 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h614498 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h614504 = - { r1__read__h614506, csrf_software_int_pend_vec_1 } ; - assign r1__read__h614506 = { r1__read__h614508, 1'b0 } ; - assign r1__read__h614508 = - { r1__read__h614510, csrf_software_int_pend_vec_3 } ; - assign r1__read__h614510 = { r1__read__h614512, 1'b0 } ; - assign r1__read__h614512 = - { r1__read__h614514, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h614514 = { r1__read__h614516, 1'b0 } ; - assign r1__read__h614516 = - { r1__read__h614518, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h614518 = { r1__read__h614520, 1'b0 } ; - assign r1__read__h614520 = - { r1__read__h614522, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614522 = { r1__read__h614524, 1'b0 } ; - assign r1__read__h614524 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h614601 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h481762 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h481763 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h475908 = + assign r1__read_BITS_13_TO_12___h655198 = csrf_fs_reg ; + assign r1__read_BITS_62_TO_14___h729548 = { r1__read__h614246, 2'd0 } ; + assign r1__read_BIT_20___h655894 = csrf_tw_reg ; + assign r1__read__h613051 = { r1__read__h613053, csrf_ie_vec_1 } ; + assign r1__read__h613053 = { r1__read__h613055, 2'b0 } ; + assign r1__read__h613055 = { r1__read__h613057, csrf_prev_ie_vec_0 } ; + assign r1__read__h613057 = { r1__read__h613059, csrf_prev_ie_vec_1 } ; + assign r1__read__h613059 = { r1__read__h613061, 2'b0 } ; + assign r1__read__h613061 = { r1__read__h613063, csrf_spp_reg } ; + assign r1__read__h613063 = { r1__read__h613065, 4'b0 } ; + assign r1__read__h613065 = { r1__read__h613067, csrf_fs_reg } ; + assign r1__read__h613067 = { r1__read__h613069, 2'd0 } ; + assign r1__read__h613069 = { r1__read__h613071, 1'b0 } ; + assign r1__read__h613071 = { r1__read__h613073, csrf_sum_reg } ; + assign r1__read__h613073 = { r1__read__h613075, csrf_mxr_reg } ; + assign r1__read__h613075 = { r1__read__h613077, 12'b0 } ; + assign r1__read__h613077 = { r1__read__h613079, 2'b10 } ; + assign r1__read__h613079 = { csrf_fs_reg == 2'b11, 29'b0 } ; + assign r1__read__h613455 = + { r1__read__h613457, csrf_software_int_en_vec_1 } ; + assign r1__read__h613457 = { r1__read__h613459, 2'b0 } ; + assign r1__read__h613459 = { r1__read__h613461, 1'b0 } ; + assign r1__read__h613461 = { r1__read__h613463, csrf_timer_int_en_vec_1 } ; + assign r1__read__h613463 = { r1__read__h613465, 2'b0 } ; + assign r1__read__h613465 = { r1__read__h613467, 1'b0 } ; + assign r1__read__h613467 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h613965 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h613970 = { r1__read__h613972, csrf_scounteren_tm_reg } ; + assign r1__read__h613972 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h613983 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h613989 = + { r1__read__h613991, csrf_software_int_pend_vec_1 } ; + assign r1__read__h613991 = { r1__read__h613993, 2'b0 } ; + assign r1__read__h613993 = { r1__read__h613995, 1'b0 } ; + assign r1__read__h613995 = + { r1__read__h613997, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h613997 = { r1__read__h613999, 2'b0 } ; + assign r1__read__h613999 = { r1__read__h614001, 1'b0 } ; + assign r1__read__h614001 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614199 = { vm_mode_reg__read__h614205, 16'd0 } ; + assign r1__read__h614222 = { r1__read__h614224, csrf_ie_vec_1 } ; + assign r1__read__h614224 = { r1__read__h614226, 1'b0 } ; + assign r1__read__h614226 = { r1__read__h614228, csrf_ie_vec_3 } ; + assign r1__read__h614228 = { r1__read__h614230, csrf_prev_ie_vec_0 } ; + assign r1__read__h614230 = { r1__read__h614232, csrf_prev_ie_vec_1 } ; + assign r1__read__h614232 = { r1__read__h614234, 1'b0 } ; + assign r1__read__h614234 = { r1__read__h614236, csrf_prev_ie_vec_3 } ; + assign r1__read__h614236 = { r1__read__h614238, csrf_spp_reg } ; + assign r1__read__h614238 = { r1__read__h614240, 2'b0 } ; + assign r1__read__h614240 = { r1__read__h614242, csrf_mpp_reg } ; + assign r1__read__h614242 = + { r1__read_BITS_62_TO_14___h729548, csrf_fs_reg } ; + assign r1__read__h614246 = { r1__read__h614248, csrf_mprv_reg } ; + assign r1__read__h614248 = { r1__read__h614250, csrf_sum_reg } ; + assign r1__read__h614250 = { r1__read__h614252, csrf_mxr_reg } ; + assign r1__read__h614252 = { r1__read__h614254, csrf_tvm_reg } ; + assign r1__read__h614254 = { r1__read__h614256, csrf_tw_reg } ; + assign r1__read__h614256 = { r1__read__h614258, csrf_tsr_reg } ; + assign r1__read__h614258 = { r1__read__h614260, 9'b0 } ; + assign r1__read__h614260 = { r1__read__h614262, 2'b10 } ; + assign r1__read__h614262 = { r1__read__h614264, 2'b10 } ; + assign r1__read__h614264 = { csrf_fs_reg == 2'b11, 27'b0 } ; + assign r1__read__h614347 = { r1__read__h614349, 1'b0 } ; + assign r1__read__h614349 = { r1__read__h614351, csrf_medeleg_13_11_reg } ; + assign r1__read__h614351 = { r1__read__h614353, 1'b0 } ; + assign r1__read__h614353 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h614364 = { r1__read__h614366, 1'b0 } ; + assign r1__read__h614366 = { r1__read__h614368, csrf_mideleg_5_3_reg } ; + assign r1__read__h614368 = { r1__read__h614370, 1'b0 } ; + assign r1__read__h614370 = { r1__read__h614372, csrf_mideleg_9_7_reg } ; + assign r1__read__h614372 = { r1__read__h614374, 1'b0 } ; + assign r1__read__h614374 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h614388 = + { r1__read__h614390, csrf_software_int_en_vec_1 } ; + assign r1__read__h614390 = { r1__read__h614392, 1'b0 } ; + assign r1__read__h614392 = + { r1__read__h614394, csrf_software_int_en_vec_3 } ; + assign r1__read__h614394 = { r1__read__h614396, 1'b0 } ; + assign r1__read__h614396 = { r1__read__h614398, csrf_timer_int_en_vec_1 } ; + assign r1__read__h614398 = { r1__read__h614400, 1'b0 } ; + assign r1__read__h614400 = { r1__read__h614402, csrf_timer_int_en_vec_3 } ; + assign r1__read__h614402 = { r1__read__h614404, 1'b0 } ; + assign r1__read__h614404 = + { r1__read__h614406, csrf_external_int_en_vec_1 } ; + assign r1__read__h614406 = { r1__read__h614408, 1'b0 } ; + assign r1__read__h614408 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h614481 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h614486 = { r1__read__h614488, csrf_mcounteren_tm_reg } ; + assign r1__read__h614488 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h614499 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h614505 = + { r1__read__h614507, csrf_software_int_pend_vec_1 } ; + assign r1__read__h614507 = { r1__read__h614509, 1'b0 } ; + assign r1__read__h614509 = + { r1__read__h614511, csrf_software_int_pend_vec_3 } ; + assign r1__read__h614511 = { r1__read__h614513, 1'b0 } ; + assign r1__read__h614513 = + { r1__read__h614515, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h614515 = { r1__read__h614517, 1'b0 } ; + assign r1__read__h614517 = + { r1__read__h614519, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h614519 = { r1__read__h614521, 1'b0 } ; + assign r1__read__h614521 = + { r1__read__h614523, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614523 = { r1__read__h614525, 1'b0 } ; + assign r1__read__h614525 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h614602 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h481763 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h481764 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h475909 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = @@ -31319,12 +31319,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h685239 = + assign renaming_spec_bits__h685240 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h681634 : + y_avValue_fst__h681635 : specTagManager$currentSpecBits ; - assign res_data__h337870 = { 32'hFFFFFFFF, x__h337885 } ; - assign res_data__h337875 = + assign res_data__h337871 = { 32'hFFFFFFFF, x__h337886 } ; + assign res_data__h337876 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -31337,8 +31337,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h383572 = { 32'hFFFFFFFF, x__h383587 } ; - assign res_data__h383577 = + assign res_data__h383573 = { 32'hFFFFFFFF, x__h383588 } ; + assign res_data__h383578 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -31351,8 +31351,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h429267 = { 32'hFFFFFFFF, x__h429282 } ; - assign res_data__h429272 = + assign res_data__h429268 = { 32'hFFFFFFFF, x__h429283 } ; + assign res_data__h429273 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -31365,7 +31365,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h337871 = + assign res_fflags__h337872 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -31433,7 +31433,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 } ; - assign res_fflags__h383573 = + assign res_fflags__h383574 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -31501,7 +31501,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 } ; - assign res_fflags__h429268 = + assign res_fflags__h429269 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31569,43 +31569,43 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 } ; - assign resp_addr__h291972 = + assign resp_addr__h291973 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h364338 = + assign result__h364339 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[0] | - guard__h364333 } ; - assign result__h410035 = + guard__h364334 } ; + assign result__h410036 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[0] | - guard__h410030 } ; - assign result__h455730 = + guard__h410031 } ; + assign result__h455731 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[0] | - guard__h455725 } ; - assign result__h503483 = + guard__h455726 } ; + assign result__h503484 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[0] | - guard__h503478 } ; - assign result__h542336 = + guard__h503479 } ; + assign result__h542337 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[0] | - guard__h542331 } ; - assign result__h581640 = + guard__h542332 } ; + assign result__h581641 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[0] | - guard__h581635 } ; - assign result__h646695 = w__h646690 & y__h646724 ; - assign result__h646746 = ~x__h646745 ; + guard__h581636 } ; + assign result__h646696 = w__h646691 & y__h646725 ; + assign result__h646747 = ~x__h646746 ; assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15735 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h612207 = - { r1__read__h614601, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h612208 = + { r1__read__h614602, csrf_rg_tdata1_data } ; assign rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998 = rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && @@ -31623,14 +31623,14 @@ module mkCore(CLK, { 2'd1, rob$deqPort_0_deq_data[95:32] } : { 2'd2, (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h722429 : + data_warl_xformed__h722430 : rob$deqPort_0_deq_data[95:32] }), 5'h0A, rob$deqPort_0_deq_data[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h723013, + x_prv__h723014, 64'hAAAAAAAAAAAAAAAA, - x__h726188, + x__h726059, 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404 = { rob$deqPort_0_deq_data[166], @@ -31642,12 +31642,12 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h655328 = + assign rs1__h655329 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h610080 = { r1__read__h614198, csrf_ppn_reg } ; + assign satp_csr__read__h610081 = { r1__read__h614199, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 && @@ -31667,432 +31667,432 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 && IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629) ; - assign sbIdx__h157152 = + assign sbIdx__h157153 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h609877 = - { r1__read__h613982, csrf_scause_code_reg } ; - assign scounteren_csr__read__h609739 = - { r1__read__h613969, csrf_scounteren_cy_reg } ; - assign sfd__h338481 = { value__h346708, 3'd0 } ; - assign sfd__h354289 = + assign scause_csr__read__h609878 = + { r1__read__h613983, csrf_scause_code_reg } ; + assign scounteren_csr__read__h609740 = + { r1__read__h613970, csrf_scounteren_cy_reg } ; + assign sfd__h338482 = { value__h346709, 3'd0 } ; + assign sfd__h354290 = { 1'b0, - _theResult___fst_exp__h354197 != 8'd0, - sfdin__h354191[56:34] } + + _theResult___fst_exp__h354198 != 8'd0, + sfdin__h354192[56:34] } + 25'd1 ; - assign sfd__h362871 = + assign sfd__h362872 = { 1'b0, - _theResult___fst_exp__h362853 != 8'd0, - _theResult___snd__h362804[56:34] } + + _theResult___fst_exp__h362854 != 8'd0, + _theResult___snd__h362805[56:34] } + 25'd1 ; - assign sfd__h372055 = + assign sfd__h372056 = { 1'b0, - _theResult___fst_exp__h371963 != 8'd0, - sfdin__h371957[56:34] } + + _theResult___fst_exp__h371964 != 8'd0, + sfdin__h371958[56:34] } + 25'd1 ; - assign sfd__h380667 = + assign sfd__h380668 = { 1'b0, - _theResult___fst_exp__h380648 != 8'd0, - _theResult___snd__h380594[56:34] } + + _theResult___fst_exp__h380649 != 8'd0, + _theResult___snd__h380595[56:34] } + 25'd1 ; - assign sfd__h384183 = { value__h392405, 3'd0 } ; - assign sfd__h399986 = + assign sfd__h384184 = { value__h392406, 3'd0 } ; + assign sfd__h399987 = { 1'b0, - _theResult___fst_exp__h399894 != 8'd0, - sfdin__h399888[56:34] } + + _theResult___fst_exp__h399895 != 8'd0, + sfdin__h399889[56:34] } + 25'd1 ; - assign sfd__h408568 = + assign sfd__h408569 = { 1'b0, - _theResult___fst_exp__h408550 != 8'd0, - _theResult___snd__h408501[56:34] } + + _theResult___fst_exp__h408551 != 8'd0, + _theResult___snd__h408502[56:34] } + 25'd1 ; - assign sfd__h417752 = + assign sfd__h417753 = { 1'b0, - _theResult___fst_exp__h417660 != 8'd0, - sfdin__h417654[56:34] } + + _theResult___fst_exp__h417661 != 8'd0, + sfdin__h417655[56:34] } + 25'd1 ; - assign sfd__h426364 = + assign sfd__h426365 = { 1'b0, - _theResult___fst_exp__h426345 != 8'd0, - _theResult___snd__h426291[56:34] } + + _theResult___fst_exp__h426346 != 8'd0, + _theResult___snd__h426292[56:34] } + 25'd1 ; - assign sfd__h429878 = { value__h438100, 3'd0 } ; - assign sfd__h445681 = + assign sfd__h429879 = { value__h438101, 3'd0 } ; + assign sfd__h445682 = { 1'b0, - _theResult___fst_exp__h445589 != 8'd0, - sfdin__h445583[56:34] } + + _theResult___fst_exp__h445590 != 8'd0, + sfdin__h445584[56:34] } + 25'd1 ; - assign sfd__h454263 = + assign sfd__h454264 = { 1'b0, - _theResult___fst_exp__h454245 != 8'd0, - _theResult___snd__h454196[56:34] } + + _theResult___fst_exp__h454246 != 8'd0, + _theResult___snd__h454197[56:34] } + 25'd1 ; - assign sfd__h463447 = + assign sfd__h463448 = { 1'b0, - _theResult___fst_exp__h463355 != 8'd0, - sfdin__h463349[56:34] } + + _theResult___fst_exp__h463356 != 8'd0, + sfdin__h463350[56:34] } + 25'd1 ; - assign sfd__h472059 = + assign sfd__h472060 = { 1'b0, - _theResult___fst_exp__h472040 != 8'd0, - _theResult___snd__h471986[56:34] } + + _theResult___fst_exp__h472041 != 8'd0, + _theResult___snd__h471987[56:34] } + 25'd1 ; - assign sfd__h482503 = { value__h487086, 32'd0 } ; - assign sfd__h501547 = + assign sfd__h482504 = { value__h487087, 32'd0 } ; + assign sfd__h501548 = { 1'b0, - _theResult___fst_exp__h501529 != 11'd0, - _theResult___snd__h501480[56:5] } + + _theResult___fst_exp__h501530 != 11'd0, + _theResult___snd__h501481[56:5] } + 54'd1 ; - assign sfd__h511198 = + assign sfd__h511199 = { 1'b0, - _theResult___fst_exp__h511106 != 11'd0, - sfdin__h511100[56:5] } + + _theResult___fst_exp__h511107 != 11'd0, + sfdin__h511101[56:5] } + 54'd1 ; - assign sfd__h519958 = + assign sfd__h519959 = { 1'b0, - _theResult___fst_exp__h519939 != 11'd0, - _theResult___snd__h519885[56:5] } + + _theResult___fst_exp__h519940 != 11'd0, + _theResult___snd__h519886[56:5] } + 54'd1 ; - assign sfd__h521497 = { value__h525939, 32'd0 } ; - assign sfd__h540400 = + assign sfd__h521498 = { value__h525940, 32'd0 } ; + assign sfd__h540401 = { 1'b0, - _theResult___fst_exp__h540382 != 11'd0, - _theResult___snd__h540333[56:5] } + + _theResult___fst_exp__h540383 != 11'd0, + _theResult___snd__h540334[56:5] } + 54'd1 ; - assign sfd__h550051 = + assign sfd__h550052 = { 1'b0, - _theResult___fst_exp__h549959 != 11'd0, - sfdin__h549953[56:5] } + + _theResult___fst_exp__h549960 != 11'd0, + sfdin__h549954[56:5] } + 54'd1 ; - assign sfd__h558811 = + assign sfd__h558812 = { 1'b0, - _theResult___fst_exp__h558792 != 11'd0, - _theResult___snd__h558738[56:5] } + + _theResult___fst_exp__h558793 != 11'd0, + _theResult___snd__h558739[56:5] } + 54'd1 ; - assign sfd__h560801 = { value__h565243, 32'd0 } ; - assign sfd__h579704 = + assign sfd__h560802 = { value__h565244, 32'd0 } ; + assign sfd__h579705 = { 1'b0, - _theResult___fst_exp__h579686 != 11'd0, - _theResult___snd__h579637[56:5] } + + _theResult___fst_exp__h579687 != 11'd0, + _theResult___snd__h579638[56:5] } + 54'd1 ; - assign sfd__h589355 = + assign sfd__h589356 = { 1'b0, - _theResult___fst_exp__h589263 != 11'd0, - sfdin__h589257[56:5] } + + _theResult___fst_exp__h589264 != 11'd0, + sfdin__h589258[56:5] } + 54'd1 ; - assign sfd__h598115 = + assign sfd__h598116 = { 1'b0, - _theResult___fst_exp__h598096 != 11'd0, - _theResult___snd__h598042[56:5] } + + _theResult___fst_exp__h598097 != 11'd0, + _theResult___snd__h598043[56:5] } + 54'd1 ; - assign sfdin__h354191 = - _theResult____h346086[56] ? - _theResult___snd__h354208 : - _theResult___snd__h354219 ; - assign sfdin__h371957 = - _theResult____h363725[56] ? - _theResult___snd__h371974 : - _theResult___snd__h371985 ; - assign sfdin__h399888 = - _theResult____h391785[56] ? - _theResult___snd__h399905 : - _theResult___snd__h399916 ; - assign sfdin__h417654 = - _theResult____h409422[56] ? - _theResult___snd__h417671 : - _theResult___snd__h417682 ; - assign sfdin__h445583 = - _theResult____h437480[56] ? - _theResult___snd__h445600 : - _theResult___snd__h445611 ; - assign sfdin__h463349 = - _theResult____h455117[56] ? - _theResult___snd__h463366 : - _theResult___snd__h463377 ; - assign sfdin__h511100 = - _theResult____h502870[56] ? - _theResult___snd__h511117 : - _theResult___snd__h511128 ; - assign sfdin__h549953 = - _theResult____h541723[56] ? - _theResult___snd__h549970 : - _theResult___snd__h549981 ; - assign sfdin__h589257 = - _theResult____h581027[56] ? - _theResult___snd__h589274 : - _theResult___snd__h589285 ; - assign shiftData__h181568 = - coreFix_memExe_regToExeQ$first[75:12] << x__h181700 ; - assign sie_csr__read__h609643 = { r1__read__h613454, 1'b0 } ; - assign sip_csr__read__h610017 = { r1__read__h613988, 1'b0 } ; - assign spec_bits__h688398 = specTagManager$currentSpecBits | y__h688411 ; - assign sstatus_csr__read__h609573 = { r1__read__h613050, csrf_ie_vec_0 } ; - assign stvec_csr__read__h609686 = - { r1__read__h613964, csrf_stvec_mode_low_reg } ; - assign trap_val__h709444 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h710482 ; - assign tsr_val__h726308 = csrf_tsr_reg ; - assign tvm_val__h726310 = csrf_tvm_reg ; + assign sfdin__h354192 = + _theResult____h346087[56] ? + _theResult___snd__h354209 : + _theResult___snd__h354220 ; + assign sfdin__h371958 = + _theResult____h363726[56] ? + _theResult___snd__h371975 : + _theResult___snd__h371986 ; + assign sfdin__h399889 = + _theResult____h391786[56] ? + _theResult___snd__h399906 : + _theResult___snd__h399917 ; + assign sfdin__h417655 = + _theResult____h409423[56] ? + _theResult___snd__h417672 : + _theResult___snd__h417683 ; + assign sfdin__h445584 = + _theResult____h437481[56] ? + _theResult___snd__h445601 : + _theResult___snd__h445612 ; + assign sfdin__h463350 = + _theResult____h455118[56] ? + _theResult___snd__h463367 : + _theResult___snd__h463378 ; + assign sfdin__h511101 = + _theResult____h502871[56] ? + _theResult___snd__h511118 : + _theResult___snd__h511129 ; + assign sfdin__h549954 = + _theResult____h541724[56] ? + _theResult___snd__h549971 : + _theResult___snd__h549982 ; + assign sfdin__h589258 = + _theResult____h581028[56] ? + _theResult___snd__h589275 : + _theResult___snd__h589286 ; + assign shiftData__h181569 = + coreFix_memExe_regToExeQ$first[75:12] << x__h181701 ; + assign sie_csr__read__h609644 = { r1__read__h613455, 1'b0 } ; + assign sip_csr__read__h610018 = { r1__read__h613989, 1'b0 } ; + assign spec_bits__h688399 = specTagManager$currentSpecBits | y__h688412 ; + assign sstatus_csr__read__h609574 = { r1__read__h613051, csrf_ie_vec_0 } ; + assign stvec_csr__read__h609687 = + { r1__read__h613965, csrf_stvec_mode_low_reg } ; + assign trap_val__h709445 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h710483 ; + assign tsr_val__h726179 = csrf_tsr_reg ; + assign tvm_val__h726181 = csrf_tvm_reg ; assign upd__h3994 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h5311 = n__read__h6760 + 64'd1 ; - assign upd__h6874 = + assign upd__h5311 = n__read__h6761 + 64'd1 ; + assign upd__h6875 = MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h726805 = + assign upd__h726676 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h295942 = + assign v__h295943 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031) ? - v__h296173 : + v__h296174 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h296173 = + assign v__h296174 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h299287 = + assign v__h299288 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138) ? - v__h299805 : + v__h299806 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h299805 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h309801 = + assign v__h299806 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h309802 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309) ? - v__h310032 : + v__h310033 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h310032 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h313677 = + assign v__h310033 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h313678 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405) ? - v__h313908 : + v__h313909 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h313908 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h328278 = + assign v__h313909 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h328279 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634) ? - v__h328509 : + v__h328510 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h328509 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h331503 = + assign v__h328510 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h331504 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728) ? - v__h331734 : + v__h331735 : coreFix_memExe_forwardQ_enqP ; - assign v__h331734 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h603884 = + assign v__h331735 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h603885 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h603894 : + v__h603895 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h603894 = + assign v__h603895 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h604529 = v__h603884 - 2'd1 ; - assign v__h607935 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608841 ; - assign v__h632818 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633571 ; - assign value__h346708 = + assign v__h604530 = v__h603885 - 2'd1 ; + assign v__h607936 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608842 ; + assign v__h632819 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633572 ; + assign value__h346709 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h392405 = + assign value__h392406 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h438100 = + assign value__h438101 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h487086 = { 1'b0, f1_exp__h482141 != 8'd0, f1_sfd__h482142 } ; - assign value__h525939 = { 1'b0, f2_exp__h521135 != 8'd0, f2_sfd__h521136 } ; - assign value__h565243 = { 1'b0, f3_exp__h560439 != 8'd0, f3_sfd__h560440 } ; - assign vm_mode_reg__read__h614204 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h646690 = + assign value__h487087 = { 1'b0, f1_exp__h482142 != 8'd0, f1_sfd__h482143 } ; + assign value__h525940 = { 1'b0, f2_exp__h521136 != 8'd0, f2_sfd__h521137 } ; + assign value__h565244 = { 1'b0, f3_exp__h560440 != 8'd0, f3_sfd__h560441 } ; + assign vm_mode_reg__read__h614205 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h646691 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h646746 : + result__h646747 : 12'd4095 ; - assign x__h153726 = + assign x__h153727 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h153732 = + assign x__h153733 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h157273 = { 3'd0, sbIdx__h157152 } ; - assign x__h157279 = + assign x__h157274 = { 3'd0, sbIdx__h157153 } ; + assign x__h157280 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h160089 = + assign x__h160090 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h160093 = + assign x__h160094 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161941 = + assign x__h161942 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h181477 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180565 ; assign x__h181478 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181171 ; - assign x__h181700 = { x__h183903[2:0], 3'b0 } ; - assign x__h18386 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180566 ; + assign x__h181479 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181172 ; + assign x__h181701 = { x__h183904[2:0], 3'b0 } ; + assign x__h18387 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h183903 = + assign x__h183904 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ; - assign x__h193680 = + assign x__h193681 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h192917[63:32] : - curData__h192917[31:0] ; - assign x__h20924 = + curData__h192918[63:32] : + curData__h192918[31:0] ; + assign x__h20925 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h287280 = + assign x__h287281 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h287292 = + assign x__h287293 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h289146 = + assign x__h289147 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h302152 = + assign x__h302153 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h337885 = - { (_theResult___exp__h381217 != 8'd255 || - _theResult___sfd__h381218 == 23'd0) && + assign x__h337886 = + { (_theResult___exp__h381218 != 8'd255 || + _theResult___sfd__h381219 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140, - out_f_exp__h381494, - out_f_sfd__h381495 } ; - assign x__h364435 = - sfd__h338481 << (x__h364468[11] ? 12'hAAA : x__h364468) ; - assign x__h364468 = + out_f_exp__h381495, + out_f_sfd__h381496 } ; + assign x__h364436 = + sfd__h338482 << (x__h364469[11] ? 12'hAAA : x__h364469) ; + assign x__h364469 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ; - assign x__h383587 = - { (_theResult___exp__h426914 != 8'd255 || - _theResult___sfd__h426915 == 23'd0) && + assign x__h383588 = + { (_theResult___exp__h426915 != 8'd255 || + _theResult___sfd__h426916 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532, - out_f_exp__h427191, - out_f_sfd__h427192 } ; - assign x__h410132 = - sfd__h384183 << (x__h410165[11] ? 12'hAAA : x__h410165) ; - assign x__h410165 = + out_f_exp__h427192, + out_f_sfd__h427193 } ; + assign x__h410133 = + sfd__h384184 << (x__h410166[11] ? 12'hAAA : x__h410166) ; + assign x__h410166 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ; - assign x__h429282 = - { (_theResult___exp__h472609 != 8'd255 || - _theResult___sfd__h472610 == 23'd0) && + assign x__h429283 = + { (_theResult___exp__h472610 != 8'd255 || + _theResult___sfd__h472611 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924, - out_f_exp__h472886, - out_f_sfd__h472887 } ; - assign x__h455827 = - sfd__h429878 << (x__h455860[11] ? 12'hAAA : x__h455860) ; - assign x__h455860 = + out_f_exp__h472887, + out_f_sfd__h472888 } ; + assign x__h455828 = + sfd__h429879 << (x__h455861[11] ? 12'hAAA : x__h455861) ; + assign x__h455861 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ; - assign x__h46293 = + assign x__h46294 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h481671 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478807 ; assign x__h481672 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479415 ; + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478808 ; assign x__h481673 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480017 ; - assign x__h48829 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479416 ; + assign x__h481674 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480018 ; + assign x__h48830 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h503578 = sfd__h482503 << x__h503611 ; - assign x__h503611 = + assign x__h503579 = sfd__h482504 << x__h503612 ; + assign x__h503612 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; - assign x__h542431 = sfd__h521497 << x__h542464 ; - assign x__h542464 = + assign x__h542432 = sfd__h521498 << x__h542465 ; + assign x__h542465 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; - assign x__h581735 = sfd__h560801 << x__h581768 ; - assign x__h581768 = + assign x__h581736 = sfd__h560802 << x__h581769 ; + assign x__h581769 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; - assign x__h603385 = a__h602949[63] ^ b__h602950[63] ; - assign x__h613035 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h617232 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h609051 : - v__h607935 ; + assign x__h603386 = a__h602950[63] ^ b__h602951[63] ; + assign x__h613036 = { csrf_frm_reg, csrf_fflags_reg } ; assign x__h617233 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615057 ; - assign x__h639741 = - coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h633779 : - v__h632818 ; + coreFix_aluExe_1_dispToRegQ$first[131] ? + rVal1__h609052 : + v__h607936 ; + assign x__h617234 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615058 ; assign x__h639742 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637576 ; - assign x__h646694 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h646745 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h702377 = + coreFix_aluExe_0_dispToRegQ$first[131] ? + rVal1__h633780 : + v__h632819 ; + assign x__h639743 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637577 ; + assign x__h646695 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h646746 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h702378 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h712418 = { cause_code__h709443, 2'b0 } ; - assign x__h714645 = + assign x__h712419 = { cause_code__h709444, 2'b0 } ; + assign x__h714646 = { csrf_fs_reg == 2'b11, IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 } ; - assign x__h714837 = - { commitStage_commitTrap[36], 59'b0, cause_code__h709443 } ; - assign x__h722556 = { 1'b0, csrf_spp_reg } ; - assign x__h726188 = + assign x__h714838 = + { commitStage_commitTrap[36], 59'b0, cause_code__h709444 } ; + assign x__h722557 = { 1'b0, csrf_spp_reg } ; + assign x__h726059 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32104,8 +32104,8 @@ module mkCore(CLK, 2'd0, csrf_fs_reg, IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15288 } ; - assign x__h729657 = - { r1__read_BITS_62_TO_14___h729677, + assign x__h729528 = + { r1__read_BITS_62_TO_14___h729548, 2'b11, csrf_mpp_reg, 2'b0, @@ -32118,54 +32118,54 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h732802 = - { y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784[63:15], + assign x__h732673 = + { y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655[63:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784[12:0] } ; - assign x__h733551 = + y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655[12:0] } ; + assign x__h733422 = NOT_rob_deqPort_0_canDeq__5320_5321_OR_rob_deq_ETC___d15664 ? - y_avValue_snd_snd_snd_fst__h733361 : + y_avValue_snd_snd_snd_fst__h733232 : IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 ; - assign x__h76238 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h314075 = + assign x__h76239 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h314076 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h66087 = + assign x_data__h66088 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h676657 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h692711 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h655012 = csrf_frm_reg ; - assign x_prv__h712487 = + assign x_data_imm__h676658 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h692712 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h655013 = csrf_frm_reg ; + assign x_prv__h712488 = csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? 2'd1 : 2'd3 ; - assign x_prv__h723013 = + assign x_prv__h723014 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h722556 : + x__h722557 : csrf_mpp_reg ; - assign x_quotient__h475197 = + assign x_quotient__h475198 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h475882 : + q___1__h475883 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h609482 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h475198 = + assign x_reg_ifc__read__h609483 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h475199 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h475908 : + r___1__h475909 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h254804 = + assign y__h254805 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h646724 = ~x__h646694 ; - assign y__h651655 = + assign y__h646725 = ~x__h646695 ; + assign y__h651656 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -32174,66 +32174,66 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h688411 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h730489 = + assign y__h688412 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h730360 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h730512 : + y_avValue_snd_snd_snd_snd_snd_fst__h730383 : 64'd0 ; - assign y__h733310 = + assign y__h733181 = NOT_rob_deqPort_0_canDeq__5320_5321_OR_rob_deq_ETC___d15664 ? - y_avValue_snd_snd_snd_snd_snd_fst__h733371 : - y__h730489 ; - assign y_avValue__h180565 = + y_avValue_snd_snd_snd_snd_snd_fst__h733242 : + y__h730360 ; + assign y_avValue__h180566 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 ; - assign y_avValue__h181171 = + assign y_avValue__h181172 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 ; - assign y_avValue__h478807 = + assign y_avValue__h478808 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 ; - assign y_avValue__h479415 = + assign y_avValue__h479416 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 ; - assign y_avValue__h480017 = + assign y_avValue__h480018 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 ; - assign y_avValue__h608841 = + assign y_avValue__h608842 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 ; - assign y_avValue__h615057 = + assign y_avValue__h615058 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 ; - assign y_avValue__h633571 = + assign y_avValue__h633572 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 ; - assign y_avValue__h637576 = + assign y_avValue__h637577 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ; - assign y_avValue_fst__h681571 = + assign y_avValue_fst__h681572 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h688398 : + spec_bits__h688399 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681600 = + assign y_avValue_fst__h681601 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ? - y_avValue_fst__h681571 : + y_avValue_fst__h681572 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681634 = + assign y_avValue_fst__h681635 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429) ? - y_avValue_fst__h681600 : + y_avValue_fst__h681601 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h730027 = + assign y_avValue_fst__h729898 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32247,10 +32247,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h733192 = + assign y_avValue_fst__h733063 = IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h733224 = + assign y_avValue_fst__h733095 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32263,16 +32263,16 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 : - y_avValue_fst__h733192 ; - assign y_avValue_new_pc__h712179 = + y_avValue_fst__h733063 ; + assign y_avValue_new_pc__h712180 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h712403 + { 58'd0, x__h712418 } : - base__h712403 ; - assign y_avValue_new_pc__h712365 = + base__h712404 + { 58'd0, x__h712419 } : + base__h712404 ; + assign y_avValue_new_pc__h712366 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h712423 + { 58'd0, x__h712418 } : - base__h712423 ; - assign y_avValue_snd_snd_snd_fst__h730502 = + base__h712424 + { 58'd0, x__h712419 } : + base__h712424 ; + assign y_avValue_snd_snd_snd_fst__h730373 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32286,7 +32286,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h733361 = + assign y_avValue_snd_snd_snd_fst__h733232 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32299,11 +32299,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 : - y_avValue_snd_snd_snd_fst__h733397 ; - assign y_avValue_snd_snd_snd_fst__h733397 = + y_avValue_snd_snd_snd_fst__h733268 ; + assign y_avValue_snd_snd_snd_fst__h733268 = IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h730512 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h730383 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32317,7 +32317,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h733371 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h733242 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32329,10 +32329,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h730489 : - y_avValue_snd_snd_snd_snd_snd_fst__h733407 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h733407 = y__h730489 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784 = x__h729657 ; + y__h730360 : + y_avValue_snd_snd_snd_snd_snd_fst__h733278 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h733278 = y__h730360 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655 = x__h729528 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32533,28 +32533,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -32570,28 +32570,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -32601,10 +32601,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h290068 = + addr__h290069 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h290068 = + addr__h290069 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -32613,37 +32613,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h710482 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h710482 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h710482 = + 4'd0, 4'd3: trap_val__h710483 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h710483 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h710483 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -32657,360 +32657,360 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h291617 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h291618 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h291617 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h291618 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h609352 or - frm_csr__read__h609363 or - fcsr_csr__read__h609377 or - sstatus_csr__read__h609573 or - sie_csr__read__h609643 or - stvec_csr__read__h609686 or - scounteren_csr__read__h609739 or + fflags_csr__read__h609353 or + frm_csr__read__h609364 or + fcsr_csr__read__h609378 or + sstatus_csr__read__h609574 or + sie_csr__read__h609644 or + stvec_csr__read__h609687 or + scounteren_csr__read__h609740 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609877 or + scause_csr__read__h609878 or csrf_stval_csr or - sip_csr__read__h610017 or - satp_csr__read__h610080 or - mstatus_csr__read__h610223 or - medeleg_csr__read__h610371 or - mideleg_csr__read__h610466 or - mie_csr__read__h610590 or - mtvec_csr__read__h610672 or - mcounteren_csr__read__h610764 or + sip_csr__read__h610018 or + satp_csr__read__h610081 or + mstatus_csr__read__h610224 or + medeleg_csr__read__h610372 or + mideleg_csr__read__h610467 or + mie_csr__read__h610591 or + mtvec_csr__read__h610673 or + mcounteren_csr__read__h610765 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611019 or + mcause_csr__read__h611020 or csrf_mtval_csr or - mip_csr__read__h611252 or + mip_csr__read__h611253 or csrf_rg_tselect or - rg_tdata1__read__h612207 or + rg_tdata1__read__h612208 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609482 or - n__read__h611356 or n__read__h611547 or csrf_time_reg) + x_reg_ifc__read__h609483 or + n__read__h611357 or n__read__h611548 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h737401 = fflags_csr__read__h609352; - 12'd2: data_out__h737401 = frm_csr__read__h609363; - 12'd3: data_out__h737401 = fcsr_csr__read__h609377; - 12'd256: data_out__h737401 = sstatus_csr__read__h609573; - 12'd260: data_out__h737401 = sie_csr__read__h609643; - 12'd261: data_out__h737401 = stvec_csr__read__h609686; - 12'd262: data_out__h737401 = scounteren_csr__read__h609739; - 12'd320: data_out__h737401 = csrf_sscratch_csr; - 12'd321: data_out__h737401 = csrf_sepc_csr; - 12'd322: data_out__h737401 = scause_csr__read__h609877; - 12'd323: data_out__h737401 = csrf_stval_csr; - 12'd324: data_out__h737401 = sip_csr__read__h610017; - 12'd384: data_out__h737401 = satp_csr__read__h610080; - 12'd768: data_out__h737401 = mstatus_csr__read__h610223; - 12'd769: data_out__h737401 = 64'h800000000014112D; - 12'd770: data_out__h737401 = medeleg_csr__read__h610371; - 12'd771: data_out__h737401 = mideleg_csr__read__h610466; - 12'd772: data_out__h737401 = mie_csr__read__h610590; - 12'd773: data_out__h737401 = mtvec_csr__read__h610672; - 12'd774: data_out__h737401 = mcounteren_csr__read__h610764; - 12'd832: data_out__h737401 = csrf_mscratch_csr; - 12'd833: data_out__h737401 = csrf_mepc_csr; - 12'd834: data_out__h737401 = mcause_csr__read__h611019; - 12'd835: data_out__h737401 = csrf_mtval_csr; - 12'd836: data_out__h737401 = mip_csr__read__h611252; - 12'd1952: data_out__h737401 = csrf_rg_tselect; - 12'd1953: data_out__h737401 = rg_tdata1__read__h612207; - 12'd1954: data_out__h737401 = csrf_rg_tdata2; - 12'd1955: data_out__h737401 = csrf_rg_tdata3; - 12'd1968: data_out__h737401 = csrf_rg_dcsr; - 12'd1969: data_out__h737401 = csrf_rg_dpc; - 12'd1970: data_out__h737401 = csrf_rg_dscratch0; - 12'd1971: data_out__h737401 = csrf_rg_dscratch1; + 12'd1: data_out__h737272 = fflags_csr__read__h609353; + 12'd2: data_out__h737272 = frm_csr__read__h609364; + 12'd3: data_out__h737272 = fcsr_csr__read__h609378; + 12'd256: data_out__h737272 = sstatus_csr__read__h609574; + 12'd260: data_out__h737272 = sie_csr__read__h609644; + 12'd261: data_out__h737272 = stvec_csr__read__h609687; + 12'd262: data_out__h737272 = scounteren_csr__read__h609740; + 12'd320: data_out__h737272 = csrf_sscratch_csr; + 12'd321: data_out__h737272 = csrf_sepc_csr; + 12'd322: data_out__h737272 = scause_csr__read__h609878; + 12'd323: data_out__h737272 = csrf_stval_csr; + 12'd324: data_out__h737272 = sip_csr__read__h610018; + 12'd384: data_out__h737272 = satp_csr__read__h610081; + 12'd768: data_out__h737272 = mstatus_csr__read__h610224; + 12'd769: data_out__h737272 = 64'h800000000014112D; + 12'd770: data_out__h737272 = medeleg_csr__read__h610372; + 12'd771: data_out__h737272 = mideleg_csr__read__h610467; + 12'd772: data_out__h737272 = mie_csr__read__h610591; + 12'd773: data_out__h737272 = mtvec_csr__read__h610673; + 12'd774: data_out__h737272 = mcounteren_csr__read__h610765; + 12'd832: data_out__h737272 = csrf_mscratch_csr; + 12'd833: data_out__h737272 = csrf_mepc_csr; + 12'd834: data_out__h737272 = mcause_csr__read__h611020; + 12'd835: data_out__h737272 = csrf_mtval_csr; + 12'd836: data_out__h737272 = mip_csr__read__h611253; + 12'd1952: data_out__h737272 = csrf_rg_tselect; + 12'd1953: data_out__h737272 = rg_tdata1__read__h612208; + 12'd1954: data_out__h737272 = csrf_rg_tdata2; + 12'd1955: data_out__h737272 = csrf_rg_tdata3; + 12'd1968: data_out__h737272 = csrf_rg_dcsr; + 12'd1969: data_out__h737272 = csrf_rg_dpc; + 12'd1970: data_out__h737272 = csrf_rg_dscratch0; + 12'd1971: data_out__h737272 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h737401 = 64'd0; - 12'd2049: data_out__h737401 = x_reg_ifc__read__h609482; - 12'd2816, 12'd3072: data_out__h737401 = n__read__h611356; - 12'd2818, 12'd3074: data_out__h737401 = n__read__h611547; - 12'd3073: data_out__h737401 = csrf_time_reg; - default: data_out__h737401 = 64'b0; + data_out__h737272 = 64'd0; + 12'd2049: data_out__h737272 = x_reg_ifc__read__h609483; + 12'd2816, 12'd3072: data_out__h737272 = n__read__h611357; + 12'd2818, 12'd3074: data_out__h737272 = n__read__h611548; + 12'd3073: data_out__h737272 = csrf_time_reg; + default: data_out__h737272 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h609352 or - frm_csr__read__h609363 or - fcsr_csr__read__h609377 or - sstatus_csr__read__h609573 or - sie_csr__read__h609643 or - stvec_csr__read__h609686 or - scounteren_csr__read__h609739 or + fflags_csr__read__h609353 or + frm_csr__read__h609364 or + fcsr_csr__read__h609378 or + sstatus_csr__read__h609574 or + sie_csr__read__h609644 or + stvec_csr__read__h609687 or + scounteren_csr__read__h609740 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609877 or + scause_csr__read__h609878 or csrf_stval_csr or - sip_csr__read__h610017 or - satp_csr__read__h610080 or - mstatus_csr__read__h610223 or - medeleg_csr__read__h610371 or - mideleg_csr__read__h610466 or - mie_csr__read__h610590 or - mtvec_csr__read__h610672 or - mcounteren_csr__read__h610764 or + sip_csr__read__h610018 or + satp_csr__read__h610081 or + mstatus_csr__read__h610224 or + medeleg_csr__read__h610372 or + mideleg_csr__read__h610467 or + mie_csr__read__h610591 or + mtvec_csr__read__h610673 or + mcounteren_csr__read__h610765 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611019 or + mcause_csr__read__h611020 or csrf_mtval_csr or - mip_csr__read__h611252 or + mip_csr__read__h611253 or csrf_rg_tselect or - rg_tdata1__read__h612207 or + rg_tdata1__read__h612208 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609482 or - n__read__h611356 or n__read__h611547 or csrf_time_reg) + x_reg_ifc__read__h609483 or + n__read__h611357 or n__read__h611548 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h609051 = fflags_csr__read__h609352; - 12'd2: rVal1__h609051 = frm_csr__read__h609363; - 12'd3: rVal1__h609051 = fcsr_csr__read__h609377; - 12'd256: rVal1__h609051 = sstatus_csr__read__h609573; - 12'd260: rVal1__h609051 = sie_csr__read__h609643; - 12'd261: rVal1__h609051 = stvec_csr__read__h609686; - 12'd262: rVal1__h609051 = scounteren_csr__read__h609739; - 12'd320: rVal1__h609051 = csrf_sscratch_csr; - 12'd321: rVal1__h609051 = csrf_sepc_csr; - 12'd322: rVal1__h609051 = scause_csr__read__h609877; - 12'd323: rVal1__h609051 = csrf_stval_csr; - 12'd324: rVal1__h609051 = sip_csr__read__h610017; - 12'd384: rVal1__h609051 = satp_csr__read__h610080; - 12'd768: rVal1__h609051 = mstatus_csr__read__h610223; - 12'd769: rVal1__h609051 = 64'h800000000014112D; - 12'd770: rVal1__h609051 = medeleg_csr__read__h610371; - 12'd771: rVal1__h609051 = mideleg_csr__read__h610466; - 12'd772: rVal1__h609051 = mie_csr__read__h610590; - 12'd773: rVal1__h609051 = mtvec_csr__read__h610672; - 12'd774: rVal1__h609051 = mcounteren_csr__read__h610764; - 12'd832: rVal1__h609051 = csrf_mscratch_csr; - 12'd833: rVal1__h609051 = csrf_mepc_csr; - 12'd834: rVal1__h609051 = mcause_csr__read__h611019; - 12'd835: rVal1__h609051 = csrf_mtval_csr; - 12'd836: rVal1__h609051 = mip_csr__read__h611252; - 12'd1952: rVal1__h609051 = csrf_rg_tselect; - 12'd1953: rVal1__h609051 = rg_tdata1__read__h612207; - 12'd1954: rVal1__h609051 = csrf_rg_tdata2; - 12'd1955: rVal1__h609051 = csrf_rg_tdata3; - 12'd1968: rVal1__h609051 = csrf_rg_dcsr; - 12'd1969: rVal1__h609051 = csrf_rg_dpc; - 12'd1970: rVal1__h609051 = csrf_rg_dscratch0; - 12'd1971: rVal1__h609051 = csrf_rg_dscratch1; + 12'd1: rVal1__h609052 = fflags_csr__read__h609353; + 12'd2: rVal1__h609052 = frm_csr__read__h609364; + 12'd3: rVal1__h609052 = fcsr_csr__read__h609378; + 12'd256: rVal1__h609052 = sstatus_csr__read__h609574; + 12'd260: rVal1__h609052 = sie_csr__read__h609644; + 12'd261: rVal1__h609052 = stvec_csr__read__h609687; + 12'd262: rVal1__h609052 = scounteren_csr__read__h609740; + 12'd320: rVal1__h609052 = csrf_sscratch_csr; + 12'd321: rVal1__h609052 = csrf_sepc_csr; + 12'd322: rVal1__h609052 = scause_csr__read__h609878; + 12'd323: rVal1__h609052 = csrf_stval_csr; + 12'd324: rVal1__h609052 = sip_csr__read__h610018; + 12'd384: rVal1__h609052 = satp_csr__read__h610081; + 12'd768: rVal1__h609052 = mstatus_csr__read__h610224; + 12'd769: rVal1__h609052 = 64'h800000000014112D; + 12'd770: rVal1__h609052 = medeleg_csr__read__h610372; + 12'd771: rVal1__h609052 = mideleg_csr__read__h610467; + 12'd772: rVal1__h609052 = mie_csr__read__h610591; + 12'd773: rVal1__h609052 = mtvec_csr__read__h610673; + 12'd774: rVal1__h609052 = mcounteren_csr__read__h610765; + 12'd832: rVal1__h609052 = csrf_mscratch_csr; + 12'd833: rVal1__h609052 = csrf_mepc_csr; + 12'd834: rVal1__h609052 = mcause_csr__read__h611020; + 12'd835: rVal1__h609052 = csrf_mtval_csr; + 12'd836: rVal1__h609052 = mip_csr__read__h611253; + 12'd1952: rVal1__h609052 = csrf_rg_tselect; + 12'd1953: rVal1__h609052 = rg_tdata1__read__h612208; + 12'd1954: rVal1__h609052 = csrf_rg_tdata2; + 12'd1955: rVal1__h609052 = csrf_rg_tdata3; + 12'd1968: rVal1__h609052 = csrf_rg_dcsr; + 12'd1969: rVal1__h609052 = csrf_rg_dpc; + 12'd1970: rVal1__h609052 = csrf_rg_dscratch0; + 12'd1971: rVal1__h609052 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h609051 = 64'd0; - 12'd2049: rVal1__h609051 = x_reg_ifc__read__h609482; - 12'd2816, 12'd3072: rVal1__h609051 = n__read__h611356; - 12'd2818, 12'd3074: rVal1__h609051 = n__read__h611547; - 12'd3073: rVal1__h609051 = csrf_time_reg; - default: rVal1__h609051 = 64'b0; + rVal1__h609052 = 64'd0; + 12'd2049: rVal1__h609052 = x_reg_ifc__read__h609483; + 12'd2816, 12'd3072: rVal1__h609052 = n__read__h611357; + 12'd2818, 12'd3074: rVal1__h609052 = n__read__h611548; + 12'd3073: rVal1__h609052 = csrf_time_reg; + default: rVal1__h609052 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h609352 or - frm_csr__read__h609363 or - fcsr_csr__read__h609377 or - sstatus_csr__read__h609573 or - sie_csr__read__h609643 or - stvec_csr__read__h609686 or - scounteren_csr__read__h609739 or + fflags_csr__read__h609353 or + frm_csr__read__h609364 or + fcsr_csr__read__h609378 or + sstatus_csr__read__h609574 or + sie_csr__read__h609644 or + stvec_csr__read__h609687 or + scounteren_csr__read__h609740 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609877 or + scause_csr__read__h609878 or csrf_stval_csr or - sip_csr__read__h610017 or - satp_csr__read__h610080 or - mstatus_csr__read__h610223 or - medeleg_csr__read__h610371 or - mideleg_csr__read__h610466 or - mie_csr__read__h610590 or - mtvec_csr__read__h610672 or - mcounteren_csr__read__h610764 or + sip_csr__read__h610018 or + satp_csr__read__h610081 or + mstatus_csr__read__h610224 or + medeleg_csr__read__h610372 or + mideleg_csr__read__h610467 or + mie_csr__read__h610591 or + mtvec_csr__read__h610673 or + mcounteren_csr__read__h610765 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611019 or + mcause_csr__read__h611020 or csrf_mtval_csr or - mip_csr__read__h611252 or + mip_csr__read__h611253 or csrf_rg_tselect or - rg_tdata1__read__h612207 or + rg_tdata1__read__h612208 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609482 or - n__read__h611356 or n__read__h611547 or csrf_time_reg) + x_reg_ifc__read__h609483 or + n__read__h611357 or n__read__h611548 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h633779 = fflags_csr__read__h609352; - 12'd2: rVal1__h633779 = frm_csr__read__h609363; - 12'd3: rVal1__h633779 = fcsr_csr__read__h609377; - 12'd256: rVal1__h633779 = sstatus_csr__read__h609573; - 12'd260: rVal1__h633779 = sie_csr__read__h609643; - 12'd261: rVal1__h633779 = stvec_csr__read__h609686; - 12'd262: rVal1__h633779 = scounteren_csr__read__h609739; - 12'd320: rVal1__h633779 = csrf_sscratch_csr; - 12'd321: rVal1__h633779 = csrf_sepc_csr; - 12'd322: rVal1__h633779 = scause_csr__read__h609877; - 12'd323: rVal1__h633779 = csrf_stval_csr; - 12'd324: rVal1__h633779 = sip_csr__read__h610017; - 12'd384: rVal1__h633779 = satp_csr__read__h610080; - 12'd768: rVal1__h633779 = mstatus_csr__read__h610223; - 12'd769: rVal1__h633779 = 64'h800000000014112D; - 12'd770: rVal1__h633779 = medeleg_csr__read__h610371; - 12'd771: rVal1__h633779 = mideleg_csr__read__h610466; - 12'd772: rVal1__h633779 = mie_csr__read__h610590; - 12'd773: rVal1__h633779 = mtvec_csr__read__h610672; - 12'd774: rVal1__h633779 = mcounteren_csr__read__h610764; - 12'd832: rVal1__h633779 = csrf_mscratch_csr; - 12'd833: rVal1__h633779 = csrf_mepc_csr; - 12'd834: rVal1__h633779 = mcause_csr__read__h611019; - 12'd835: rVal1__h633779 = csrf_mtval_csr; - 12'd836: rVal1__h633779 = mip_csr__read__h611252; - 12'd1952: rVal1__h633779 = csrf_rg_tselect; - 12'd1953: rVal1__h633779 = rg_tdata1__read__h612207; - 12'd1954: rVal1__h633779 = csrf_rg_tdata2; - 12'd1955: rVal1__h633779 = csrf_rg_tdata3; - 12'd1968: rVal1__h633779 = csrf_rg_dcsr; - 12'd1969: rVal1__h633779 = csrf_rg_dpc; - 12'd1970: rVal1__h633779 = csrf_rg_dscratch0; - 12'd1971: rVal1__h633779 = csrf_rg_dscratch1; + 12'd1: rVal1__h633780 = fflags_csr__read__h609353; + 12'd2: rVal1__h633780 = frm_csr__read__h609364; + 12'd3: rVal1__h633780 = fcsr_csr__read__h609378; + 12'd256: rVal1__h633780 = sstatus_csr__read__h609574; + 12'd260: rVal1__h633780 = sie_csr__read__h609644; + 12'd261: rVal1__h633780 = stvec_csr__read__h609687; + 12'd262: rVal1__h633780 = scounteren_csr__read__h609740; + 12'd320: rVal1__h633780 = csrf_sscratch_csr; + 12'd321: rVal1__h633780 = csrf_sepc_csr; + 12'd322: rVal1__h633780 = scause_csr__read__h609878; + 12'd323: rVal1__h633780 = csrf_stval_csr; + 12'd324: rVal1__h633780 = sip_csr__read__h610018; + 12'd384: rVal1__h633780 = satp_csr__read__h610081; + 12'd768: rVal1__h633780 = mstatus_csr__read__h610224; + 12'd769: rVal1__h633780 = 64'h800000000014112D; + 12'd770: rVal1__h633780 = medeleg_csr__read__h610372; + 12'd771: rVal1__h633780 = mideleg_csr__read__h610467; + 12'd772: rVal1__h633780 = mie_csr__read__h610591; + 12'd773: rVal1__h633780 = mtvec_csr__read__h610673; + 12'd774: rVal1__h633780 = mcounteren_csr__read__h610765; + 12'd832: rVal1__h633780 = csrf_mscratch_csr; + 12'd833: rVal1__h633780 = csrf_mepc_csr; + 12'd834: rVal1__h633780 = mcause_csr__read__h611020; + 12'd835: rVal1__h633780 = csrf_mtval_csr; + 12'd836: rVal1__h633780 = mip_csr__read__h611253; + 12'd1952: rVal1__h633780 = csrf_rg_tselect; + 12'd1953: rVal1__h633780 = rg_tdata1__read__h612208; + 12'd1954: rVal1__h633780 = csrf_rg_tdata2; + 12'd1955: rVal1__h633780 = csrf_rg_tdata3; + 12'd1968: rVal1__h633780 = csrf_rg_dcsr; + 12'd1969: rVal1__h633780 = csrf_rg_dpc; + 12'd1970: rVal1__h633780 = csrf_rg_dscratch0; + 12'd1971: rVal1__h633780 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h633779 = 64'd0; - 12'd2049: rVal1__h633779 = x_reg_ifc__read__h609482; - 12'd2816, 12'd3072: rVal1__h633779 = n__read__h611356; - 12'd2818, 12'd3074: rVal1__h633779 = n__read__h611547; - 12'd3073: rVal1__h633779 = csrf_time_reg; - default: rVal1__h633779 = 64'b0; + rVal1__h633780 = 64'd0; + 12'd2049: rVal1__h633780 = x_reg_ifc__read__h609483; + 12'd2816, 12'd3072: rVal1__h633780 = n__read__h611357; + 12'd2818, 12'd3074: rVal1__h633780 = n__read__h611548; + 12'd3073: rVal1__h633780 = csrf_time_reg; + default: rVal1__h633780 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h346068 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h346069 = 8'd255; 3'd2: - _theResult___fst_exp__h346068 = + _theResult___fst_exp__h346069 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h346068 = + _theResult___fst_exp__h346069 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h346068 = 8'd254; - default: _theResult___fst_exp__h346068 = 8'd0; + 3'd4: _theResult___fst_exp__h346069 = 8'd254; + default: _theResult___fst_exp__h346069 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h346069 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h346070 = 23'd0; 3'd2: - _theResult___fst_sfd__h346069 = + _theResult___fst_sfd__h346070 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h346069 = + _theResult___fst_sfd__h346070 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h346069 = 23'd8388607; - default: _theResult___fst_sfd__h346069 = 23'd0; + 3'd4: _theResult___fst_sfd__h346070 = 23'd8388607; + default: _theResult___fst_sfd__h346070 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h391767 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h391768 = 8'd255; 3'd2: - _theResult___fst_exp__h391767 = + _theResult___fst_exp__h391768 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h391767 = + _theResult___fst_exp__h391768 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h391767 = 8'd254; - default: _theResult___fst_exp__h391767 = 8'd0; + 3'd4: _theResult___fst_exp__h391768 = 8'd254; + default: _theResult___fst_exp__h391768 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h391768 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h391769 = 23'd0; 3'd2: - _theResult___fst_sfd__h391768 = + _theResult___fst_sfd__h391769 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h391768 = + _theResult___fst_sfd__h391769 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h391768 = 23'd8388607; - default: _theResult___fst_sfd__h391768 = 23'd0; + 3'd4: _theResult___fst_sfd__h391769 = 23'd8388607; + default: _theResult___fst_sfd__h391769 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h437462 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h437463 = 8'd255; 3'd2: - _theResult___fst_exp__h437462 = + _theResult___fst_exp__h437463 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h437462 = + _theResult___fst_exp__h437463 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h437462 = 8'd254; - default: _theResult___fst_exp__h437462 = 8'd0; + 3'd4: _theResult___fst_exp__h437463 = 8'd254; + default: _theResult___fst_exp__h437463 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h437463 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h437464 = 23'd0; 3'd2: - _theResult___fst_sfd__h437463 = + _theResult___fst_sfd__h437464 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h437463 = + _theResult___fst_sfd__h437464 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h437463 = 23'd8388607; - default: _theResult___fst_sfd__h437463 = 23'd0; + 3'd4: _theResult___fst_sfd__h437464 = 23'd8388607; + default: _theResult___fst_sfd__h437464 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33161,16 +33161,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h709458 = commitStage_commitTrap[35:32]; - default: i__h709458 = 4'd15; + i__h709459 = commitStage_commitTrap[35:32]; + default: i__h709459 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h709618 = commitStage_commitTrap[35:32]; - default: i__h709618 = 4'd15; + i__h709619 = commitStage_commitTrap[35:32]; + default: i__h709619 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -33398,446 +33398,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h354805 or - _theResult___fst_exp__h362853 or - out_exp__h363298 or _theResult___exp__h363295) + always@(guard__h354806 or + _theResult___fst_exp__h362854 or + out_exp__h363299 or _theResult___exp__h363296) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 = - _theResult___fst_exp__h362853; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 = + _theResult___fst_exp__h362854; 2'b10: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 = - out_exp__h363298; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 = + out_exp__h363299; 2'b11: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 = - _theResult___exp__h363295; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 = + _theResult___exp__h363296; endcase end - always@(guard__h354805 or - _theResult___fst_exp__h362853 or _theResult___exp__h363295) + always@(guard__h354806 or + _theResult___fst_exp__h362854 or _theResult___exp__h363296) begin - case (guard__h354805) + case (guard__h354806) 2'b0: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33 = - _theResult___fst_exp__h362853; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 = + _theResult___fst_exp__h362854; 2'b01, 2'b10, 2'b11: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33 = - _theResult___exp__h363295; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 = + _theResult___exp__h363296; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 or - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33 or + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 or + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 or - _theResult___fst_exp__h362853) + _theResult___fst_exp__h362854) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h363373 = - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32; + _theResult___fst_exp__h363374 = + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32; 3'd1: - _theResult___fst_exp__h363373 = - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33; + _theResult___fst_exp__h363374 = + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33; 3'd2: - _theResult___fst_exp__h363373 = + _theResult___fst_exp__h363374 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532; 3'd3: - _theResult___fst_exp__h363373 = + _theResult___fst_exp__h363374 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534; - 3'd4: _theResult___fst_exp__h363373 = _theResult___fst_exp__h362853; - default: _theResult___fst_exp__h363373 = 8'd0; + 3'd4: _theResult___fst_exp__h363374 = _theResult___fst_exp__h362854; + default: _theResult___fst_exp__h363374 = 8'd0; endcase end - always@(guard__h346096 or - _theResult___fst_exp__h354197 or - out_exp__h354716 or _theResult___exp__h354713) + always@(guard__h346097 or + _theResult___fst_exp__h354198 or + out_exp__h354717 or _theResult___exp__h354714) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 = - _theResult___fst_exp__h354197; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 = + _theResult___fst_exp__h354198; 2'b10: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 = - out_exp__h354716; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 = + out_exp__h354717; 2'b11: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 = - _theResult___exp__h354713; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 = + _theResult___exp__h354714; endcase end - always@(guard__h346096 or - _theResult___fst_exp__h354197 or _theResult___exp__h354713) + always@(guard__h346097 or + _theResult___fst_exp__h354198 or _theResult___exp__h354714) begin - case (guard__h346096) + case (guard__h346097) 2'b0: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35 = - _theResult___fst_exp__h354197; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 = + _theResult___fst_exp__h354198; 2'b01, 2'b10, 2'b11: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35 = - _theResult___exp__h354713; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 = + _theResult___exp__h354714; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 or - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35 or + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 or + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 or - _theResult___fst_exp__h354197) + _theResult___fst_exp__h354198) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h354791 = - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34; + _theResult___fst_exp__h354792 = + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34; 3'd1: - _theResult___fst_exp__h354791 = - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35; + _theResult___fst_exp__h354792 = + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35; 3'd2: - _theResult___fst_exp__h354791 = + _theResult___fst_exp__h354792 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310; 3'd3: - _theResult___fst_exp__h354791 = + _theResult___fst_exp__h354792 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313; - 3'd4: _theResult___fst_exp__h354791 = _theResult___fst_exp__h354197; - default: _theResult___fst_exp__h354791 = 8'd0; + 3'd4: _theResult___fst_exp__h354792 = _theResult___fst_exp__h354198; + default: _theResult___fst_exp__h354792 = 8'd0; endcase end - always@(guard__h363735 or - _theResult___fst_exp__h371963 or - out_exp__h372482 or _theResult___exp__h372479) + always@(guard__h363736 or + _theResult___fst_exp__h371964 or + out_exp__h372483 or _theResult___exp__h372480) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 = - _theResult___fst_exp__h371963; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 = + _theResult___fst_exp__h371964; 2'b10: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 = - out_exp__h372482; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 = + out_exp__h372483; 2'b11: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 = - _theResult___exp__h372479; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 = + _theResult___exp__h372480; endcase end - always@(guard__h363735 or - _theResult___fst_exp__h371963 or _theResult___exp__h372479) + always@(guard__h363736 or + _theResult___fst_exp__h371964 or _theResult___exp__h372480) begin - case (guard__h363735) + case (guard__h363736) 2'b0: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41 = - _theResult___fst_exp__h371963; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 = + _theResult___fst_exp__h371964; 2'b01, 2'b10, 2'b11: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41 = - _theResult___exp__h372479; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 = + _theResult___exp__h372480; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 or - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41 or + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 or + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 or - _theResult___fst_exp__h371963) + _theResult___fst_exp__h371964) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h372557 = - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40; + _theResult___fst_exp__h372558 = + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40; 3'd1: - _theResult___fst_exp__h372557 = - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41; + _theResult___fst_exp__h372558 = + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41; 3'd2: - _theResult___fst_exp__h372557 = + _theResult___fst_exp__h372558 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857; 3'd3: - _theResult___fst_exp__h372557 = + _theResult___fst_exp__h372558 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859; - 3'd4: _theResult___fst_exp__h372557 = _theResult___fst_exp__h371963; - default: _theResult___fst_exp__h372557 = 8'd0; + 3'd4: _theResult___fst_exp__h372558 = _theResult___fst_exp__h371964; + default: _theResult___fst_exp__h372558 = 8'd0; endcase end - always@(guard__h372571 or - _theResult___fst_exp__h380648 or - out_exp__h381118 or _theResult___exp__h381115) + always@(guard__h372572 or + _theResult___fst_exp__h380649 or + out_exp__h381119 or _theResult___exp__h381116) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 = - _theResult___fst_exp__h380648; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 = + _theResult___fst_exp__h380649; 2'b10: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 = - out_exp__h381118; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 = + out_exp__h381119; 2'b11: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 = - _theResult___exp__h381115; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 = + _theResult___exp__h381116; endcase end - always@(guard__h372571 or - _theResult___fst_exp__h380648 or _theResult___exp__h381115) + always@(guard__h372572 or + _theResult___fst_exp__h380649 or _theResult___exp__h381116) begin - case (guard__h372571) + case (guard__h372572) 2'b0: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46 = - _theResult___fst_exp__h380648; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 = + _theResult___fst_exp__h380649; 2'b01, 2'b10, 2'b11: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46 = - _theResult___exp__h381115; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 = + _theResult___exp__h381116; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 or - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46 or + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 or + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 or - _theResult___fst_exp__h380648) + _theResult___fst_exp__h380649) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h381193 = - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45; + _theResult___fst_exp__h381194 = + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45; 3'd1: - _theResult___fst_exp__h381193 = - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46; + _theResult___fst_exp__h381194 = + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46; 3'd2: - _theResult___fst_exp__h381193 = + _theResult___fst_exp__h381194 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926; 3'd3: - _theResult___fst_exp__h381193 = + _theResult___fst_exp__h381194 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928; - 3'd4: _theResult___fst_exp__h381193 = _theResult___fst_exp__h380648; - default: _theResult___fst_exp__h381193 = 8'd0; + 3'd4: _theResult___fst_exp__h381194 = _theResult___fst_exp__h380649; + default: _theResult___fst_exp__h381194 = 8'd0; endcase end - always@(guard__h354805 or - _theResult___snd__h362804 or - out_sfd__h363299 or _theResult___sfd__h363296) + always@(guard__h354806 or + _theResult___snd__h362805 or + out_sfd__h363300 or _theResult___sfd__h363297) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 = - _theResult___snd__h362804[56:34]; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = + _theResult___snd__h362805[56:34]; 2'b10: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 = - out_sfd__h363299; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = + out_sfd__h363300; 2'b11: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 = - _theResult___sfd__h363296; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = + _theResult___sfd__h363297; endcase end - always@(guard__h354805 or - _theResult___snd__h362804 or _theResult___sfd__h363296) + always@(guard__h354806 or + _theResult___snd__h362805 or _theResult___sfd__h363297) begin - case (guard__h354805) + case (guard__h354806) 2'b0: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48 = - _theResult___snd__h362804[56:34]; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = + _theResult___snd__h362805[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48 = - _theResult___sfd__h363296; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = + _theResult___sfd__h363297; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 or - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or - _theResult___snd__h362804) + _theResult___snd__h362805) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h363374 = - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47; + _theResult___fst_sfd__h363375 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47; 3'd1: - _theResult___fst_sfd__h363374 = - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48; + _theResult___fst_sfd__h363375 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48; 3'd2: - _theResult___fst_sfd__h363374 = + _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; 3'd3: - _theResult___fst_sfd__h363374 = + _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978; - 3'd4: _theResult___fst_sfd__h363374 = _theResult___snd__h362804[56:34]; - default: _theResult___fst_sfd__h363374 = 23'd0; + 3'd4: _theResult___fst_sfd__h363375 = _theResult___snd__h362805[56:34]; + default: _theResult___fst_sfd__h363375 = 23'd0; endcase end - always@(guard__h346096 or - sfdin__h354191 or out_sfd__h354717 or _theResult___sfd__h354714) + always@(guard__h346097 or + sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 = - sfdin__h354191[56:34]; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354192[56:34]; 2'b10: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 = - out_sfd__h354717; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354718; 2'b11: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 = - _theResult___sfd__h354714; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354715; endcase end - always@(guard__h346096 or sfdin__h354191 or _theResult___sfd__h354714) + always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) begin - case (guard__h346096) + case (guard__h346097) 2'b0: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50 = - sfdin__h354191[56:34]; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354192[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h354714; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354715; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 or - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354191) + sfdin__h354192) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h354792 = - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49; + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49; 3'd1: - _theResult___fst_sfd__h354792 = - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50; 3'd2: - _theResult___fst_sfd__h354792 = + _theResult___fst_sfd__h354793 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; 3'd3: - _theResult___fst_sfd__h354792 = + _theResult___fst_sfd__h354793 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354792 = sfdin__h354191[56:34]; - default: _theResult___fst_sfd__h354792 = 23'd0; + 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; + default: _theResult___fst_sfd__h354793 = 23'd0; endcase end - always@(guard__h363735 or - sfdin__h371957 or out_sfd__h372483 or _theResult___sfd__h372480) + always@(guard__h363736 or + sfdin__h371958 or out_sfd__h372484 or _theResult___sfd__h372481) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 = - sfdin__h371957[56:34]; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 = + sfdin__h371958[56:34]; 2'b10: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 = - out_sfd__h372483; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 = + out_sfd__h372484; 2'b11: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h372480; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h372481; endcase end - always@(guard__h363735 or sfdin__h371957 or _theResult___sfd__h372480) + always@(guard__h363736 or sfdin__h371958 or _theResult___sfd__h372481) begin - case (guard__h363735) + case (guard__h363736) 2'b0: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52 = - sfdin__h371957[56:34]; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 = + sfdin__h371958[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h372480; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h372481; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 or - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52 or + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 or + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 or - sfdin__h371957) + sfdin__h371958) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h372558 = - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h372559 = + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51; 3'd1: - _theResult___fst_sfd__h372558 = - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h372559 = + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52; 3'd2: - _theResult___fst_sfd__h372558 = + _theResult___fst_sfd__h372559 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003; 3'd3: - _theResult___fst_sfd__h372558 = + _theResult___fst_sfd__h372559 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005; - 3'd4: _theResult___fst_sfd__h372558 = sfdin__h371957[56:34]; - default: _theResult___fst_sfd__h372558 = 23'd0; + 3'd4: _theResult___fst_sfd__h372559 = sfdin__h371958[56:34]; + default: _theResult___fst_sfd__h372559 = 23'd0; endcase end - always@(guard__h372571 or - _theResult___snd__h380594 or - out_sfd__h381119 or _theResult___sfd__h381116) + always@(guard__h372572 or + _theResult___snd__h380595 or + out_sfd__h381120 or _theResult___sfd__h381117) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 = - _theResult___snd__h380594[56:34]; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 = + _theResult___snd__h380595[56:34]; 2'b10: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 = - out_sfd__h381119; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 = + out_sfd__h381120; 2'b11: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 = - _theResult___sfd__h381116; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 = + _theResult___sfd__h381117; endcase end - always@(guard__h372571 or - _theResult___snd__h380594 or _theResult___sfd__h381116) + always@(guard__h372572 or + _theResult___snd__h380595 or _theResult___sfd__h381117) begin - case (guard__h372571) + case (guard__h372572) 2'b0: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54 = - _theResult___snd__h380594[56:34]; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 = + _theResult___snd__h380595[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54 = - _theResult___sfd__h381116; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 = + _theResult___sfd__h381117; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 or - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54 or + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 or + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___snd__h380594) + _theResult___snd__h380595) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h381194 = - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53; + _theResult___fst_sfd__h381195 = + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53; 3'd1: - _theResult___fst_sfd__h381194 = - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54; + _theResult___fst_sfd__h381195 = + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54; 3'd2: - _theResult___fst_sfd__h381194 = + _theResult___fst_sfd__h381195 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_sfd__h381194 = + _theResult___fst_sfd__h381195 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_sfd__h381194 = _theResult___snd__h380594[56:34]; - default: _theResult___fst_sfd__h381194 = 23'd0; + 3'd4: _theResult___fst_sfd__h381195 = _theResult___snd__h380595[56:34]; + default: _theResult___fst_sfd__h381195 = 23'd0; endcase end - always@(guard__h346096 or + always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = - guard__h346096 == 2'b11 && + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + guard__h346097 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or - guard__h346096) + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or + guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - (guard__h346096 == 2'b0) ? + (guard__h346097 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h346096 == 2'b01 || guard__h346096 == 2'b10 || - guard__h346096 == 2'b11) && + (guard__h346097 == 2'b01 || guard__h346097 == 2'b10 || + guard__h346097 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = @@ -33848,34 +33848,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h346096 or + always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - guard__h346096 != 2'b11 || + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or - guard__h346096) + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or + guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - (guard__h346096 == 2'b0) ? + (guard__h346097 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h346096 != 2'b01 && guard__h346096 != 2'b10 && - guard__h346096 != 2'b11 || + guard__h346097 != 2'b01 && guard__h346097 != 2'b10 && + guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = @@ -33886,34 +33886,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354805 or + always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01, 2'b10: - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = - guard__h354805 == 2'b11 && + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354806 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or - guard__h354805) + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354806) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354805 == 2'b0) ? + (guard__h354806 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354805 == 2'b01 || guard__h354805 == 2'b10 || - guard__h354805 == 2'b11) && + (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || + guard__h354806 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = @@ -33924,34 +33924,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354805 or + always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01, 2'b10: - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = - guard__h354805 != 2'b11 || + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + guard__h354806 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or - guard__h354805) + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or + guard__h354806) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - (guard__h354805 == 2'b0) ? + (guard__h354806 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h354805 != 2'b01 && guard__h354805 != 2'b10 && - guard__h354805 != 2'b11 || + guard__h354806 != 2'b01 && guard__h354806 != 2'b10 && + guard__h354806 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = @@ -33962,34 +33962,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363735 or + always@(guard__h363736 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01, 2'b10: - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = - guard__h363735 == 2'b11 && + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + guard__h363736 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or - guard__h363735) + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or + guard__h363736) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - (guard__h363735 == 2'b0) ? + (guard__h363736 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h363735 == 2'b01 || guard__h363735 == 2'b10 || - guard__h363735 == 2'b11) && + (guard__h363736 == 2'b01 || guard__h363736 == 2'b10 || + guard__h363736 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = @@ -34000,34 +34000,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363735 or + always@(guard__h363736 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01, 2'b10: - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = - guard__h363735 != 2'b11 || + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + guard__h363736 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or - guard__h363735) + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or + guard__h363736) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - (guard__h363735 == 2'b0) ? + (guard__h363736 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h363735 != 2'b01 && guard__h363735 != 2'b10 && - guard__h363735 != 2'b11 || + guard__h363736 != 2'b01 && guard__h363736 != 2'b10 && + guard__h363736 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = @@ -34038,34 +34038,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372571 or + always@(guard__h372572 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01, 2'b10: - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - guard__h372571 == 2'b11 && + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + guard__h372572 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or - guard__h372571) + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or + guard__h372572) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - (guard__h372571 == 2'b0) ? + (guard__h372572 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h372571 == 2'b01 || guard__h372571 == 2'b10 || - guard__h372571 == 2'b11) && + (guard__h372572 == 2'b01 || guard__h372572 == 2'b10 || + guard__h372572 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = @@ -34076,34 +34076,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372571 or + always@(guard__h372572 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01, 2'b10: - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = - guard__h372571 != 2'b11 || + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + guard__h372572 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or - guard__h372571) + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or + guard__h372572) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - (guard__h372571 == 2'b0) ? + (guard__h372572 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h372571 != 2'b01 && guard__h372571 != 2'b10 && - guard__h372571 != 2'b11 || + guard__h372572 != 2'b01 && guard__h372572 != 2'b10 && + guard__h372572 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = @@ -34140,446 +34140,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h400502 or - _theResult___fst_exp__h408550 or - out_exp__h408995 or _theResult___exp__h408992) + always@(guard__h400503 or + _theResult___fst_exp__h408551 or + out_exp__h408996 or _theResult___exp__h408993) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 = - _theResult___fst_exp__h408550; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 = + _theResult___fst_exp__h408551; 2'b10: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 = - out_exp__h408995; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 = + out_exp__h408996; 2'b11: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 = - _theResult___exp__h408992; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 = + _theResult___exp__h408993; endcase end - always@(guard__h400502 or - _theResult___fst_exp__h408550 or _theResult___exp__h408992) + always@(guard__h400503 or + _theResult___fst_exp__h408551 or _theResult___exp__h408993) begin - case (guard__h400502) + case (guard__h400503) 2'b0: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68 = - _theResult___fst_exp__h408550; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 = + _theResult___fst_exp__h408551; 2'b01, 2'b10, 2'b11: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68 = - _theResult___exp__h408992; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 = + _theResult___exp__h408993; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 or - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68 or + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 or + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 or - _theResult___fst_exp__h408550) + _theResult___fst_exp__h408551) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h409070 = - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67; + _theResult___fst_exp__h409071 = + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67; 3'd1: - _theResult___fst_exp__h409070 = - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68; + _theResult___fst_exp__h409071 = + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68; 3'd2: - _theResult___fst_exp__h409070 = + _theResult___fst_exp__h409071 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924; 3'd3: - _theResult___fst_exp__h409070 = + _theResult___fst_exp__h409071 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926; - 3'd4: _theResult___fst_exp__h409070 = _theResult___fst_exp__h408550; - default: _theResult___fst_exp__h409070 = 8'd0; + 3'd4: _theResult___fst_exp__h409071 = _theResult___fst_exp__h408551; + default: _theResult___fst_exp__h409071 = 8'd0; endcase end - always@(guard__h391795 or - _theResult___fst_exp__h399894 or - out_exp__h400413 or _theResult___exp__h400410) + always@(guard__h391796 or + _theResult___fst_exp__h399895 or + out_exp__h400414 or _theResult___exp__h400411) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 = - _theResult___fst_exp__h399894; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 = + _theResult___fst_exp__h399895; 2'b10: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 = - out_exp__h400413; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 = + out_exp__h400414; 2'b11: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 = - _theResult___exp__h400410; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 = + _theResult___exp__h400411; endcase end - always@(guard__h391795 or - _theResult___fst_exp__h399894 or _theResult___exp__h400410) + always@(guard__h391796 or + _theResult___fst_exp__h399895 or _theResult___exp__h400411) begin - case (guard__h391795) + case (guard__h391796) 2'b0: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70 = - _theResult___fst_exp__h399894; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 = + _theResult___fst_exp__h399895; 2'b01, 2'b10, 2'b11: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70 = - _theResult___exp__h400410; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 = + _theResult___exp__h400411; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 or - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70 or + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 or + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 or - _theResult___fst_exp__h399894) + _theResult___fst_exp__h399895) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h400488 = - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69; + _theResult___fst_exp__h400489 = + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69; 3'd1: - _theResult___fst_exp__h400488 = - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70; + _theResult___fst_exp__h400489 = + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70; 3'd2: - _theResult___fst_exp__h400488 = + _theResult___fst_exp__h400489 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702; 3'd3: - _theResult___fst_exp__h400488 = + _theResult___fst_exp__h400489 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705; - 3'd4: _theResult___fst_exp__h400488 = _theResult___fst_exp__h399894; - default: _theResult___fst_exp__h400488 = 8'd0; + 3'd4: _theResult___fst_exp__h400489 = _theResult___fst_exp__h399895; + default: _theResult___fst_exp__h400489 = 8'd0; endcase end - always@(guard__h409432 or - _theResult___fst_exp__h417660 or - out_exp__h418179 or _theResult___exp__h418176) + always@(guard__h409433 or + _theResult___fst_exp__h417661 or + out_exp__h418180 or _theResult___exp__h418177) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 = - _theResult___fst_exp__h417660; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 = + _theResult___fst_exp__h417661; 2'b10: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 = - out_exp__h418179; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 = + out_exp__h418180; 2'b11: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 = - _theResult___exp__h418176; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 = + _theResult___exp__h418177; endcase end - always@(guard__h409432 or - _theResult___fst_exp__h417660 or _theResult___exp__h418176) + always@(guard__h409433 or + _theResult___fst_exp__h417661 or _theResult___exp__h418177) begin - case (guard__h409432) + case (guard__h409433) 2'b0: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76 = - _theResult___fst_exp__h417660; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 = + _theResult___fst_exp__h417661; 2'b01, 2'b10, 2'b11: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76 = - _theResult___exp__h418176; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 = + _theResult___exp__h418177; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 or - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76 or + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 or + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 or - _theResult___fst_exp__h417660) + _theResult___fst_exp__h417661) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h418254 = - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75; + _theResult___fst_exp__h418255 = + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75; 3'd1: - _theResult___fst_exp__h418254 = - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76; + _theResult___fst_exp__h418255 = + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76; 3'd2: - _theResult___fst_exp__h418254 = + _theResult___fst_exp__h418255 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249; 3'd3: - _theResult___fst_exp__h418254 = + _theResult___fst_exp__h418255 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251; - 3'd4: _theResult___fst_exp__h418254 = _theResult___fst_exp__h417660; - default: _theResult___fst_exp__h418254 = 8'd0; + 3'd4: _theResult___fst_exp__h418255 = _theResult___fst_exp__h417661; + default: _theResult___fst_exp__h418255 = 8'd0; endcase end - always@(guard__h418268 or - _theResult___fst_exp__h426345 or - out_exp__h426815 or _theResult___exp__h426812) + always@(guard__h418269 or + _theResult___fst_exp__h426346 or + out_exp__h426816 or _theResult___exp__h426813) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 = - _theResult___fst_exp__h426345; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 = + _theResult___fst_exp__h426346; 2'b10: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 = - out_exp__h426815; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 = + out_exp__h426816; 2'b11: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 = - _theResult___exp__h426812; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 = + _theResult___exp__h426813; endcase end - always@(guard__h418268 or - _theResult___fst_exp__h426345 or _theResult___exp__h426812) + always@(guard__h418269 or + _theResult___fst_exp__h426346 or _theResult___exp__h426813) begin - case (guard__h418268) + case (guard__h418269) 2'b0: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81 = - _theResult___fst_exp__h426345; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 = + _theResult___fst_exp__h426346; 2'b01, 2'b10, 2'b11: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81 = - _theResult___exp__h426812; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 = + _theResult___exp__h426813; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 or - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81 or + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 or + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 or - _theResult___fst_exp__h426345) + _theResult___fst_exp__h426346) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h426890 = - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80; + _theResult___fst_exp__h426891 = + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80; 3'd1: - _theResult___fst_exp__h426890 = - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81; + _theResult___fst_exp__h426891 = + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81; 3'd2: - _theResult___fst_exp__h426890 = + _theResult___fst_exp__h426891 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318; 3'd3: - _theResult___fst_exp__h426890 = + _theResult___fst_exp__h426891 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320; - 3'd4: _theResult___fst_exp__h426890 = _theResult___fst_exp__h426345; - default: _theResult___fst_exp__h426890 = 8'd0; + 3'd4: _theResult___fst_exp__h426891 = _theResult___fst_exp__h426346; + default: _theResult___fst_exp__h426891 = 8'd0; endcase end - always@(guard__h400502 or - _theResult___snd__h408501 or - out_sfd__h408996 or _theResult___sfd__h408993) + always@(guard__h400503 or + _theResult___snd__h408502 or + out_sfd__h408997 or _theResult___sfd__h408994) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 = - _theResult___snd__h408501[56:34]; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = + _theResult___snd__h408502[56:34]; 2'b10: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 = - out_sfd__h408996; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = + out_sfd__h408997; 2'b11: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 = - _theResult___sfd__h408993; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = + _theResult___sfd__h408994; endcase end - always@(guard__h400502 or - _theResult___snd__h408501 or _theResult___sfd__h408993) + always@(guard__h400503 or + _theResult___snd__h408502 or _theResult___sfd__h408994) begin - case (guard__h400502) + case (guard__h400503) 2'b0: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83 = - _theResult___snd__h408501[56:34]; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = + _theResult___snd__h408502[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83 = - _theResult___sfd__h408993; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = + _theResult___sfd__h408994; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 or - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or - _theResult___snd__h408501) + _theResult___snd__h408502) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h409071 = - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82; + _theResult___fst_sfd__h409072 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82; 3'd1: - _theResult___fst_sfd__h409071 = - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83; + _theResult___fst_sfd__h409072 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83; 3'd2: - _theResult___fst_sfd__h409071 = + _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; 3'd3: - _theResult___fst_sfd__h409071 = + _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370; - 3'd4: _theResult___fst_sfd__h409071 = _theResult___snd__h408501[56:34]; - default: _theResult___fst_sfd__h409071 = 23'd0; + 3'd4: _theResult___fst_sfd__h409072 = _theResult___snd__h408502[56:34]; + default: _theResult___fst_sfd__h409072 = 23'd0; endcase end - always@(guard__h391795 or - sfdin__h399888 or out_sfd__h400414 or _theResult___sfd__h400411) + always@(guard__h391796 or + sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 = - sfdin__h399888[56:34]; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399889[56:34]; 2'b10: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 = - out_sfd__h400414; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400415; 2'b11: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 = - _theResult___sfd__h400411; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400412; endcase end - always@(guard__h391795 or sfdin__h399888 or _theResult___sfd__h400411) + always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) begin - case (guard__h391795) + case (guard__h391796) 2'b0: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85 = - sfdin__h399888[56:34]; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399889[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85 = - _theResult___sfd__h400411; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400412; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 or - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399888) + sfdin__h399889) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h400489 = - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84; + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84; 3'd1: - _theResult___fst_sfd__h400489 = - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85; + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85; 3'd2: - _theResult___fst_sfd__h400489 = + _theResult___fst_sfd__h400490 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; 3'd3: - _theResult___fst_sfd__h400489 = + _theResult___fst_sfd__h400490 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400489 = sfdin__h399888[56:34]; - default: _theResult___fst_sfd__h400489 = 23'd0; + 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; + default: _theResult___fst_sfd__h400490 = 23'd0; endcase end - always@(guard__h409432 or - sfdin__h417654 or out_sfd__h418180 or _theResult___sfd__h418177) + always@(guard__h409433 or + sfdin__h417655 or out_sfd__h418181 or _theResult___sfd__h418178) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 = - sfdin__h417654[56:34]; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 = + sfdin__h417655[56:34]; 2'b10: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 = - out_sfd__h418180; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 = + out_sfd__h418181; 2'b11: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h418177; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h418178; endcase end - always@(guard__h409432 or sfdin__h417654 or _theResult___sfd__h418177) + always@(guard__h409433 or sfdin__h417655 or _theResult___sfd__h418178) begin - case (guard__h409432) + case (guard__h409433) 2'b0: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87 = - sfdin__h417654[56:34]; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 = + sfdin__h417655[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h418177; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h418178; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 or - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87 or + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 or + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 or - sfdin__h417654) + sfdin__h417655) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h418255 = - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h418256 = + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86; 3'd1: - _theResult___fst_sfd__h418255 = - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h418256 = + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87; 3'd2: - _theResult___fst_sfd__h418255 = + _theResult___fst_sfd__h418256 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395; 3'd3: - _theResult___fst_sfd__h418255 = + _theResult___fst_sfd__h418256 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397; - 3'd4: _theResult___fst_sfd__h418255 = sfdin__h417654[56:34]; - default: _theResult___fst_sfd__h418255 = 23'd0; + 3'd4: _theResult___fst_sfd__h418256 = sfdin__h417655[56:34]; + default: _theResult___fst_sfd__h418256 = 23'd0; endcase end - always@(guard__h418268 or - _theResult___snd__h426291 or - out_sfd__h426816 or _theResult___sfd__h426813) + always@(guard__h418269 or + _theResult___snd__h426292 or + out_sfd__h426817 or _theResult___sfd__h426814) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 = - _theResult___snd__h426291[56:34]; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 = + _theResult___snd__h426292[56:34]; 2'b10: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 = - out_sfd__h426816; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 = + out_sfd__h426817; 2'b11: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 = - _theResult___sfd__h426813; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 = + _theResult___sfd__h426814; endcase end - always@(guard__h418268 or - _theResult___snd__h426291 or _theResult___sfd__h426813) + always@(guard__h418269 or + _theResult___snd__h426292 or _theResult___sfd__h426814) begin - case (guard__h418268) + case (guard__h418269) 2'b0: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89 = - _theResult___snd__h426291[56:34]; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 = + _theResult___snd__h426292[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89 = - _theResult___sfd__h426813; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 = + _theResult___sfd__h426814; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 or - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89 or + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 or + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___snd__h426291) + _theResult___snd__h426292) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h426891 = - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88; + _theResult___fst_sfd__h426892 = + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88; 3'd1: - _theResult___fst_sfd__h426891 = - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89; + _theResult___fst_sfd__h426892 = + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89; 3'd2: - _theResult___fst_sfd__h426891 = + _theResult___fst_sfd__h426892 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_sfd__h426891 = + _theResult___fst_sfd__h426892 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_sfd__h426891 = _theResult___snd__h426291[56:34]; - default: _theResult___fst_sfd__h426891 = 23'd0; + 3'd4: _theResult___fst_sfd__h426892 = _theResult___snd__h426292[56:34]; + default: _theResult___fst_sfd__h426892 = 23'd0; endcase end - always@(guard__h391795 or + always@(guard__h391796 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01, 2'b10: - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = - guard__h391795 == 2'b11 && + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + guard__h391796 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or - guard__h391795) + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or + guard__h391796) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - (guard__h391795 == 2'b0) ? + (guard__h391796 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h391795 == 2'b01 || guard__h391795 == 2'b10 || - guard__h391795 == 2'b11) && + (guard__h391796 == 2'b01 || guard__h391796 == 2'b10 || + guard__h391796 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = @@ -34590,34 +34590,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h391795 or + always@(guard__h391796 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01, 2'b10: - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = - guard__h391795 != 2'b11 || + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + guard__h391796 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or - guard__h391795) + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or + guard__h391796) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - (guard__h391795 == 2'b0) ? + (guard__h391796 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h391795 != 2'b01 && guard__h391795 != 2'b10 && - guard__h391795 != 2'b11 || + guard__h391796 != 2'b01 && guard__h391796 != 2'b10 && + guard__h391796 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = @@ -34628,34 +34628,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400502 or + always@(guard__h400503 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01, 2'b10: - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = - guard__h400502 == 2'b11 && + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + guard__h400503 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or - guard__h400502) + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or + guard__h400503) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - (guard__h400502 == 2'b0) ? + (guard__h400503 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h400502 == 2'b01 || guard__h400502 == 2'b10 || - guard__h400502 == 2'b11) && + (guard__h400503 == 2'b01 || guard__h400503 == 2'b10 || + guard__h400503 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = @@ -34666,34 +34666,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400502 or + always@(guard__h400503 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01, 2'b10: - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = - guard__h400502 != 2'b11 || + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + guard__h400503 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or - guard__h400502) + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or + guard__h400503) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - (guard__h400502 == 2'b0) ? + (guard__h400503 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h400502 != 2'b01 && guard__h400502 != 2'b10 && - guard__h400502 != 2'b11 || + guard__h400503 != 2'b01 && guard__h400503 != 2'b10 && + guard__h400503 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = @@ -34704,34 +34704,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409432 or + always@(guard__h409433 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01, 2'b10: - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = - guard__h409432 == 2'b11 && + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + guard__h409433 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or - guard__h409432) + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or + guard__h409433) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - (guard__h409432 == 2'b0) ? + (guard__h409433 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h409432 == 2'b01 || guard__h409432 == 2'b10 || - guard__h409432 == 2'b11) && + (guard__h409433 == 2'b01 || guard__h409433 == 2'b10 || + guard__h409433 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = @@ -34742,34 +34742,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409432 or + always@(guard__h409433 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01, 2'b10: - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = - guard__h409432 != 2'b11 || + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + guard__h409433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or - guard__h409432) + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or + guard__h409433) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - (guard__h409432 == 2'b0) ? + (guard__h409433 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h409432 != 2'b01 && guard__h409432 != 2'b10 && - guard__h409432 != 2'b11 || + guard__h409433 != 2'b01 && guard__h409433 != 2'b10 && + guard__h409433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = @@ -34780,34 +34780,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418268 or + always@(guard__h418269 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = - guard__h418268 == 2'b11 && + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + guard__h418269 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or - guard__h418268) + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or + guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - (guard__h418268 == 2'b0) ? + (guard__h418269 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h418268 == 2'b01 || guard__h418268 == 2'b10 || - guard__h418268 == 2'b11) && + (guard__h418269 == 2'b01 || guard__h418269 == 2'b10 || + guard__h418269 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = @@ -34818,34 +34818,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418268 or + always@(guard__h418269 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = - guard__h418268 != 2'b11 || + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418269 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or - guard__h418268) + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418268 == 2'b0) ? + (guard__h418269 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418268 != 2'b01 && guard__h418268 != 2'b10 && - guard__h418268 != 2'b11 || + guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && + guard__h418269 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = @@ -34882,446 +34882,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h446197 or - _theResult___fst_exp__h454245 or - out_exp__h454690 or _theResult___exp__h454687) + always@(guard__h446198 or + _theResult___fst_exp__h454246 or + out_exp__h454691 or _theResult___exp__h454688) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 = - _theResult___fst_exp__h454245; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 = + _theResult___fst_exp__h454246; 2'b10: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 = - out_exp__h454690; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 = + out_exp__h454691; 2'b11: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 = - _theResult___exp__h454687; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 = + _theResult___exp__h454688; endcase end - always@(guard__h446197 or - _theResult___fst_exp__h454245 or _theResult___exp__h454687) + always@(guard__h446198 or + _theResult___fst_exp__h454246 or _theResult___exp__h454688) begin - case (guard__h446197) + case (guard__h446198) 2'b0: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103 = - _theResult___fst_exp__h454245; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 = + _theResult___fst_exp__h454246; 2'b01, 2'b10, 2'b11: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103 = - _theResult___exp__h454687; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 = + _theResult___exp__h454688; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 or - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103 or + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 or + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 or - _theResult___fst_exp__h454245) + _theResult___fst_exp__h454246) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h454765 = - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102; + _theResult___fst_exp__h454766 = + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102; 3'd1: - _theResult___fst_exp__h454765 = - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103; + _theResult___fst_exp__h454766 = + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103; 3'd2: - _theResult___fst_exp__h454765 = + _theResult___fst_exp__h454766 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316; 3'd3: - _theResult___fst_exp__h454765 = + _theResult___fst_exp__h454766 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318; - 3'd4: _theResult___fst_exp__h454765 = _theResult___fst_exp__h454245; - default: _theResult___fst_exp__h454765 = 8'd0; + 3'd4: _theResult___fst_exp__h454766 = _theResult___fst_exp__h454246; + default: _theResult___fst_exp__h454766 = 8'd0; endcase end - always@(guard__h437490 or - _theResult___fst_exp__h445589 or - out_exp__h446108 or _theResult___exp__h446105) + always@(guard__h437491 or + _theResult___fst_exp__h445590 or + out_exp__h446109 or _theResult___exp__h446106) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 = - _theResult___fst_exp__h445589; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 = + _theResult___fst_exp__h445590; 2'b10: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 = - out_exp__h446108; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 = + out_exp__h446109; 2'b11: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 = - _theResult___exp__h446105; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 = + _theResult___exp__h446106; endcase end - always@(guard__h437490 or - _theResult___fst_exp__h445589 or _theResult___exp__h446105) + always@(guard__h437491 or + _theResult___fst_exp__h445590 or _theResult___exp__h446106) begin - case (guard__h437490) + case (guard__h437491) 2'b0: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105 = - _theResult___fst_exp__h445589; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 = + _theResult___fst_exp__h445590; 2'b01, 2'b10, 2'b11: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105 = - _theResult___exp__h446105; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 = + _theResult___exp__h446106; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 or - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105 or + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 or + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 or - _theResult___fst_exp__h445589) + _theResult___fst_exp__h445590) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h446183 = - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104; + _theResult___fst_exp__h446184 = + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104; 3'd1: - _theResult___fst_exp__h446183 = - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105; + _theResult___fst_exp__h446184 = + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105; 3'd2: - _theResult___fst_exp__h446183 = + _theResult___fst_exp__h446184 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094; 3'd3: - _theResult___fst_exp__h446183 = + _theResult___fst_exp__h446184 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097; - 3'd4: _theResult___fst_exp__h446183 = _theResult___fst_exp__h445589; - default: _theResult___fst_exp__h446183 = 8'd0; + 3'd4: _theResult___fst_exp__h446184 = _theResult___fst_exp__h445590; + default: _theResult___fst_exp__h446184 = 8'd0; endcase end - always@(guard__h455127 or - _theResult___fst_exp__h463355 or - out_exp__h463874 or _theResult___exp__h463871) + always@(guard__h455128 or + _theResult___fst_exp__h463356 or + out_exp__h463875 or _theResult___exp__h463872) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 = - _theResult___fst_exp__h463355; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 = + _theResult___fst_exp__h463356; 2'b10: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 = - out_exp__h463874; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 = + out_exp__h463875; 2'b11: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 = - _theResult___exp__h463871; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 = + _theResult___exp__h463872; endcase end - always@(guard__h455127 or - _theResult___fst_exp__h463355 or _theResult___exp__h463871) + always@(guard__h455128 or + _theResult___fst_exp__h463356 or _theResult___exp__h463872) begin - case (guard__h455127) + case (guard__h455128) 2'b0: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111 = - _theResult___fst_exp__h463355; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 = + _theResult___fst_exp__h463356; 2'b01, 2'b10, 2'b11: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111 = - _theResult___exp__h463871; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 = + _theResult___exp__h463872; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 or - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111 or + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 or + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 or - _theResult___fst_exp__h463355) + _theResult___fst_exp__h463356) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h463949 = - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110; + _theResult___fst_exp__h463950 = + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110; 3'd1: - _theResult___fst_exp__h463949 = - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111; + _theResult___fst_exp__h463950 = + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111; 3'd2: - _theResult___fst_exp__h463949 = + _theResult___fst_exp__h463950 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641; 3'd3: - _theResult___fst_exp__h463949 = + _theResult___fst_exp__h463950 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643; - 3'd4: _theResult___fst_exp__h463949 = _theResult___fst_exp__h463355; - default: _theResult___fst_exp__h463949 = 8'd0; + 3'd4: _theResult___fst_exp__h463950 = _theResult___fst_exp__h463356; + default: _theResult___fst_exp__h463950 = 8'd0; endcase end - always@(guard__h463963 or - _theResult___fst_exp__h472040 or - out_exp__h472510 or _theResult___exp__h472507) + always@(guard__h463964 or + _theResult___fst_exp__h472041 or + out_exp__h472511 or _theResult___exp__h472508) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 = - _theResult___fst_exp__h472040; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 = + _theResult___fst_exp__h472041; 2'b10: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 = - out_exp__h472510; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 = + out_exp__h472511; 2'b11: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 = - _theResult___exp__h472507; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 = + _theResult___exp__h472508; endcase end - always@(guard__h463963 or - _theResult___fst_exp__h472040 or _theResult___exp__h472507) + always@(guard__h463964 or + _theResult___fst_exp__h472041 or _theResult___exp__h472508) begin - case (guard__h463963) + case (guard__h463964) 2'b0: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116 = - _theResult___fst_exp__h472040; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 = + _theResult___fst_exp__h472041; 2'b01, 2'b10, 2'b11: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116 = - _theResult___exp__h472507; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 = + _theResult___exp__h472508; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 or - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116 or + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 or + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 or - _theResult___fst_exp__h472040) + _theResult___fst_exp__h472041) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h472585 = - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115; + _theResult___fst_exp__h472586 = + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115; 3'd1: - _theResult___fst_exp__h472585 = - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116; + _theResult___fst_exp__h472586 = + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116; 3'd2: - _theResult___fst_exp__h472585 = + _theResult___fst_exp__h472586 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710; 3'd3: - _theResult___fst_exp__h472585 = + _theResult___fst_exp__h472586 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712; - 3'd4: _theResult___fst_exp__h472585 = _theResult___fst_exp__h472040; - default: _theResult___fst_exp__h472585 = 8'd0; + 3'd4: _theResult___fst_exp__h472586 = _theResult___fst_exp__h472041; + default: _theResult___fst_exp__h472586 = 8'd0; endcase end - always@(guard__h446197 or - _theResult___snd__h454196 or - out_sfd__h454691 or _theResult___sfd__h454688) + always@(guard__h446198 or + _theResult___snd__h454197 or + out_sfd__h454692 or _theResult___sfd__h454689) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 = - _theResult___snd__h454196[56:34]; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 = + _theResult___snd__h454197[56:34]; 2'b10: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 = - out_sfd__h454691; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 = + out_sfd__h454692; 2'b11: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 = - _theResult___sfd__h454688; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 = + _theResult___sfd__h454689; endcase end - always@(guard__h446197 or - _theResult___snd__h454196 or _theResult___sfd__h454688) + always@(guard__h446198 or + _theResult___snd__h454197 or _theResult___sfd__h454689) begin - case (guard__h446197) + case (guard__h446198) 2'b0: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118 = - _theResult___snd__h454196[56:34]; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 = + _theResult___snd__h454197[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118 = - _theResult___sfd__h454688; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 = + _theResult___sfd__h454689; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 or - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118 or + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 or + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 or - _theResult___snd__h454196) + _theResult___snd__h454197) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h454766 = - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117; + _theResult___fst_sfd__h454767 = + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117; 3'd1: - _theResult___fst_sfd__h454766 = - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118; + _theResult___fst_sfd__h454767 = + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118; 3'd2: - _theResult___fst_sfd__h454766 = + _theResult___fst_sfd__h454767 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760; 3'd3: - _theResult___fst_sfd__h454766 = + _theResult___fst_sfd__h454767 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762; - 3'd4: _theResult___fst_sfd__h454766 = _theResult___snd__h454196[56:34]; - default: _theResult___fst_sfd__h454766 = 23'd0; + 3'd4: _theResult___fst_sfd__h454767 = _theResult___snd__h454197[56:34]; + default: _theResult___fst_sfd__h454767 = 23'd0; endcase end - always@(guard__h437490 or - sfdin__h445583 or out_sfd__h446109 or _theResult___sfd__h446106) + always@(guard__h437491 or + sfdin__h445584 or out_sfd__h446110 or _theResult___sfd__h446107) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 = - sfdin__h445583[56:34]; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 = + sfdin__h445584[56:34]; 2'b10: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 = - out_sfd__h446109; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 = + out_sfd__h446110; 2'b11: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 = - _theResult___sfd__h446106; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 = + _theResult___sfd__h446107; endcase end - always@(guard__h437490 or sfdin__h445583 or _theResult___sfd__h446106) + always@(guard__h437491 or sfdin__h445584 or _theResult___sfd__h446107) begin - case (guard__h437490) + case (guard__h437491) 2'b0: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120 = - sfdin__h445583[56:34]; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 = + sfdin__h445584[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h446106; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h446107; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 or - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120 or + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 or + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 or - sfdin__h445583) + sfdin__h445584) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h446184 = - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119; + _theResult___fst_sfd__h446185 = + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119; 3'd1: - _theResult___fst_sfd__h446184 = - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h446185 = + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120; 3'd2: - _theResult___fst_sfd__h446184 = + _theResult___fst_sfd__h446185 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741; 3'd3: - _theResult___fst_sfd__h446184 = + _theResult___fst_sfd__h446185 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743; - 3'd4: _theResult___fst_sfd__h446184 = sfdin__h445583[56:34]; - default: _theResult___fst_sfd__h446184 = 23'd0; + 3'd4: _theResult___fst_sfd__h446185 = sfdin__h445584[56:34]; + default: _theResult___fst_sfd__h446185 = 23'd0; endcase end - always@(guard__h455127 or - sfdin__h463349 or out_sfd__h463875 or _theResult___sfd__h463872) + always@(guard__h455128 or + sfdin__h463350 or out_sfd__h463876 or _theResult___sfd__h463873) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 = - sfdin__h463349[56:34]; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 = + sfdin__h463350[56:34]; 2'b10: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 = - out_sfd__h463875; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 = + out_sfd__h463876; 2'b11: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h463872; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h463873; endcase end - always@(guard__h455127 or sfdin__h463349 or _theResult___sfd__h463872) + always@(guard__h455128 or sfdin__h463350 or _theResult___sfd__h463873) begin - case (guard__h455127) + case (guard__h455128) 2'b0: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122 = - sfdin__h463349[56:34]; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 = + sfdin__h463350[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h463872; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h463873; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 or - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122 or + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 or + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 or - sfdin__h463349) + sfdin__h463350) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h463950 = - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h463951 = + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121; 3'd1: - _theResult___fst_sfd__h463950 = - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h463951 = + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122; 3'd2: - _theResult___fst_sfd__h463950 = + _theResult___fst_sfd__h463951 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787; 3'd3: - _theResult___fst_sfd__h463950 = + _theResult___fst_sfd__h463951 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789; - 3'd4: _theResult___fst_sfd__h463950 = sfdin__h463349[56:34]; - default: _theResult___fst_sfd__h463950 = 23'd0; + 3'd4: _theResult___fst_sfd__h463951 = sfdin__h463350[56:34]; + default: _theResult___fst_sfd__h463951 = 23'd0; endcase end - always@(guard__h463963 or - _theResult___snd__h471986 or - out_sfd__h472511 or _theResult___sfd__h472508) + always@(guard__h463964 or + _theResult___snd__h471987 or + out_sfd__h472512 or _theResult___sfd__h472509) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 = - _theResult___snd__h471986[56:34]; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 = + _theResult___snd__h471987[56:34]; 2'b10: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 = - out_sfd__h472511; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 = + out_sfd__h472512; 2'b11: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 = - _theResult___sfd__h472508; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 = + _theResult___sfd__h472509; endcase end - always@(guard__h463963 or - _theResult___snd__h471986 or _theResult___sfd__h472508) + always@(guard__h463964 or + _theResult___snd__h471987 or _theResult___sfd__h472509) begin - case (guard__h463963) + case (guard__h463964) 2'b0: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124 = - _theResult___snd__h471986[56:34]; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 = + _theResult___snd__h471987[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124 = - _theResult___sfd__h472508; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 = + _theResult___sfd__h472509; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 or - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124 or + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 or + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___snd__h471986) + _theResult___snd__h471987) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h472586 = - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123; + _theResult___fst_sfd__h472587 = + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123; 3'd1: - _theResult___fst_sfd__h472586 = - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124; + _theResult___fst_sfd__h472587 = + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124; 3'd2: - _theResult___fst_sfd__h472586 = + _theResult___fst_sfd__h472587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; 3'd3: - _theResult___fst_sfd__h472586 = + _theResult___fst_sfd__h472587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_sfd__h472586 = _theResult___snd__h471986[56:34]; - default: _theResult___fst_sfd__h472586 = 23'd0; + 3'd4: _theResult___fst_sfd__h472587 = _theResult___snd__h471987[56:34]; + default: _theResult___fst_sfd__h472587 = 23'd0; endcase end - always@(guard__h437490 or + always@(guard__h437491 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01, 2'b10: - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = - guard__h437490 == 2'b11 && + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = + guard__h437491 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or - guard__h437490) + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or + guard__h437491) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - (guard__h437490 == 2'b0) ? + (guard__h437491 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h437490 == 2'b01 || guard__h437490 == 2'b10 || - guard__h437490 == 2'b11) && + (guard__h437491 == 2'b01 || guard__h437491 == 2'b10 || + guard__h437491 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = @@ -35332,34 +35332,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h446197 or + always@(guard__h446198 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01, 2'b10: - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = - guard__h446197 == 2'b11 && + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h446198 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or - guard__h446197) + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h446198) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - (guard__h446197 == 2'b0) ? + (guard__h446198 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h446197 == 2'b01 || guard__h446197 == 2'b10 || - guard__h446197 == 2'b11) && + (guard__h446198 == 2'b01 || guard__h446198 == 2'b10 || + guard__h446198 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = @@ -35370,34 +35370,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h437490 or + always@(guard__h437491 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01, 2'b10: - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = - guard__h437490 != 2'b11 || + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h437491 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or - guard__h437490) + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h437491) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - (guard__h437490 == 2'b0) ? + (guard__h437491 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h437490 != 2'b01 && guard__h437490 != 2'b10 && - guard__h437490 != 2'b11 || + guard__h437491 != 2'b01 && guard__h437491 != 2'b10 && + guard__h437491 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = @@ -35408,34 +35408,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h446197 or + always@(guard__h446198 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01, 2'b10: - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = - guard__h446197 != 2'b11 || + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h446198 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or - guard__h446197) + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h446198) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - (guard__h446197 == 2'b0) ? + (guard__h446198 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h446197 != 2'b01 && guard__h446197 != 2'b10 && - guard__h446197 != 2'b11 || + guard__h446198 != 2'b01 && guard__h446198 != 2'b10 && + guard__h446198 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = @@ -35446,34 +35446,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455127 or + always@(guard__h455128 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01, 2'b10: - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = - guard__h455127 == 2'b11 && + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + guard__h455128 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or - guard__h455127) + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or + guard__h455128) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - (guard__h455127 == 2'b0) ? + (guard__h455128 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h455127 == 2'b01 || guard__h455127 == 2'b10 || - guard__h455127 == 2'b11) && + (guard__h455128 == 2'b01 || guard__h455128 == 2'b10 || + guard__h455128 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = @@ -35484,34 +35484,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455127 or + always@(guard__h455128 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01, 2'b10: - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - guard__h455127 != 2'b11 || + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + guard__h455128 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or - guard__h455127) + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or + guard__h455128) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - (guard__h455127 == 2'b0) ? + (guard__h455128 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h455127 != 2'b01 && guard__h455127 != 2'b10 && - guard__h455127 != 2'b11 || + guard__h455128 != 2'b01 && guard__h455128 != 2'b10 && + guard__h455128 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = @@ -35522,34 +35522,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463963 or + always@(guard__h463964 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01, 2'b10: - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = - guard__h463963 == 2'b11 && + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + guard__h463964 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or - guard__h463963) + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or + guard__h463964) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - (guard__h463963 == 2'b0) ? + (guard__h463964 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h463963 == 2'b01 || guard__h463963 == 2'b10 || - guard__h463963 == 2'b11) && + (guard__h463964 == 2'b01 || guard__h463964 == 2'b10 || + guard__h463964 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = @@ -35560,34 +35560,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463963 or + always@(guard__h463964 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01, 2'b10: - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = - guard__h463963 != 2'b11 || + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + guard__h463964 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or - guard__h463963) + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or + guard__h463964) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - (guard__h463963 == 2'b0) ? + (guard__h463964 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h463963 != 2'b01 && guard__h463963 != 2'b10 && - guard__h463963 != 2'b11 || + guard__h463964 != 2'b01 && guard__h463964 != 2'b10 && + guard__h463964 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = @@ -35644,28 +35644,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h493568 or - _theResult___fst_exp__h501529 or _theResult___exp__h502184) + always@(guard__h493569 or + _theResult___fst_exp__h501530 or _theResult___exp__h502185) begin - case (guard__h493568) + case (guard__h493569) 2'b0: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143 = - _theResult___fst_exp__h501529; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143 = + _theResult___fst_exp__h501530; 2'b01, 2'b10, 2'b11: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143 = - _theResult___exp__h502184; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143 = + _theResult___exp__h502185; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h501529 or + _theResult___fst_exp__h501530 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 or - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143) + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - _theResult___fst_exp__h501529; + _theResult___fst_exp__h501530; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015; @@ -35674,44 +35674,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = 11'd0; endcase end - always@(guard__h493568 or - _theResult___fst_exp__h501529 or - out_exp__h502187 or _theResult___exp__h502184) + always@(guard__h493569 or + _theResult___fst_exp__h501530 or + out_exp__h502188 or _theResult___exp__h502185) begin - case (guard__h493568) + case (guard__h493569) 2'b0, 2'b01: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 = - _theResult___fst_exp__h501529; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 = + _theResult___fst_exp__h501530; 2'b10: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 = - out_exp__h502187; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 = + out_exp__h502188; 2'b11: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 = - _theResult___exp__h502184; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 = + _theResult___exp__h502185; endcase end - always@(guard__h493568 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h493569 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h493568) + case (guard__h493569) 2'b0, 2'b01, 2'b10: - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h493568 == 2'b11 && + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h493569 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493568) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493569) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35721,12 +35721,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h493568 == 2'b0) ? + (guard__h493569 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h493568 == 2'b01 || guard__h493568 == 2'b10 || - guard__h493568 == 2'b11) && + (guard__h493569 == 2'b01 || guard__h493569 == 2'b10 || + guard__h493569 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35737,23 +35737,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h511949 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h511950 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h511949) + case (guard__h511950) 2'b0, 2'b01, 2'b10: - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h511949 == 2'b11 && + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h511950 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511949) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511950) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35763,12 +35763,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h511949 == 2'b0) ? + (guard__h511950 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h511949 == 2'b01 || guard__h511949 == 2'b10 || - guard__h511949 == 2'b11) && + (guard__h511950 == 2'b01 || guard__h511950 == 2'b10 || + guard__h511950 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35779,23 +35779,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h502880 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h502881 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h502880) + case (guard__h502881) 2'b0, 2'b01, 2'b10: - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h502880 == 2'b11 && + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h502881 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502880) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502881) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35805,12 +35805,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h502880 == 2'b0) ? + (guard__h502881 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h502880 == 2'b01 || guard__h502880 == 2'b10 || - guard__h502880 == 2'b11) && + (guard__h502881 == 2'b01 || guard__h502881 == 2'b10 || + guard__h502881 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35821,28 +35821,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h571725 or - _theResult___fst_exp__h579686 or _theResult___exp__h580341) + always@(guard__h571726 or + _theResult___fst_exp__h579687 or _theResult___exp__h580342) begin - case (guard__h571725) + case (guard__h571726) 2'b0: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160 = - _theResult___fst_exp__h579686; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160 = + _theResult___fst_exp__h579687; 2'b01, 2'b10, 2'b11: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160 = - _theResult___exp__h580341; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160 = + _theResult___exp__h580342; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h579686 or + _theResult___fst_exp__h579687 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 or - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160) + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - _theResult___fst_exp__h579686; + _theResult___fst_exp__h579687; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730; @@ -35851,42 +35851,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = 11'd0; endcase end - always@(guard__h571725 or - _theResult___fst_exp__h579686 or - out_exp__h580344 or _theResult___exp__h580341) + always@(guard__h571726 or + _theResult___fst_exp__h579687 or + out_exp__h580345 or _theResult___exp__h580342) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 = - _theResult___fst_exp__h579686; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 = + _theResult___fst_exp__h579687; 2'b10: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 = - out_exp__h580344; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 = + out_exp__h580345; 2'b11: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 = - _theResult___exp__h580341; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 = + _theResult___exp__h580342; endcase end - always@(guard__h571725 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h571725 == 2'b11 && + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571726 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571725) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35895,12 +35895,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h571725 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571725 == 2'b01 || guard__h571725 == 2'b10 || - guard__h571725 == 2'b11) && + (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || + guard__h571726 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35911,21 +35911,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581037 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h581037 == 2'b11 && + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581038 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581037) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35934,12 +35934,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h581037 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581037 == 2'b01 || guard__h581037 == 2'b10 || - guard__h581037 == 2'b11) && + (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || + guard__h581038 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35950,21 +35950,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590106 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590107 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01, 2'b10: - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h590106 == 2'b11 && + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h590107 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590106) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590107) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35973,12 +35973,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h590106 == 2'b0) ? + (guard__h590107 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h590106 == 2'b01 || guard__h590106 == 2'b10 || - guard__h590106 == 2'b11) && + (guard__h590107 == 2'b01 || guard__h590107 == 2'b10 || + guard__h590107 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35989,21 +35989,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581037 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h581037 != 2'b11 || + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h581038 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581037) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36012,12 +36012,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h581037 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h581037 != 2'b01 && guard__h581037 != 2'b10 && - guard__h581037 != 2'b11 || + guard__h581038 != 2'b01 && guard__h581038 != 2'b10 && + guard__h581038 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36028,21 +36028,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590106 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590107 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01, 2'b10: - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h590106 != 2'b11 || + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h590107 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590106) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590107) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36051,12 +36051,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h590106 == 2'b0) ? + (guard__h590107 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h590106 != 2'b01 && guard__h590106 != 2'b10 && - guard__h590106 != 2'b11 || + guard__h590107 != 2'b01 && guard__h590107 != 2'b10 && + guard__h590107 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36067,21 +36067,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571725 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h571725 != 2'b11 || + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h571726 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571725) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36090,12 +36090,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h571725 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h571725 != 2'b01 && guard__h571725 != 2'b10 && - guard__h571725 != 2'b11 || + guard__h571726 != 2'b01 && guard__h571726 != 2'b10 && + guard__h571726 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36106,28 +36106,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h532421 or - _theResult___fst_exp__h540382 or _theResult___exp__h541037) + always@(guard__h532422 or + _theResult___fst_exp__h540383 or _theResult___exp__h541038) begin - case (guard__h532421) + case (guard__h532422) 2'b0: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183 = - _theResult___fst_exp__h540382; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183 = + _theResult___fst_exp__h540383; 2'b01, 2'b10, 2'b11: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183 = - _theResult___exp__h541037; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183 = + _theResult___exp__h541038; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h540382 or + _theResult___fst_exp__h540383 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 or - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183) + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - _theResult___fst_exp__h540382; + _theResult___fst_exp__h540383; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500; @@ -36136,49 +36136,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = 11'd0; endcase end - always@(guard__h532421 or - _theResult___fst_exp__h540382 or - out_exp__h541040 or _theResult___exp__h541037) + always@(guard__h532422 or + _theResult___fst_exp__h540383 or + out_exp__h541041 or _theResult___exp__h541038) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 = - _theResult___fst_exp__h540382; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 = + _theResult___fst_exp__h540383; 2'b10: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 = - out_exp__h541040; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 = + out_exp__h541041; 2'b11: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 = - _theResult___exp__h541037; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 = + _theResult___exp__h541038; endcase end - always@(guard__h541733 or - _theResult___fst_exp__h549959 or _theResult___exp__h550688) + always@(guard__h541734 or + _theResult___fst_exp__h549960 or _theResult___exp__h550689) begin - case (guard__h541733) + case (guard__h541734) 2'b0: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185 = - _theResult___fst_exp__h549959; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185 = + _theResult___fst_exp__h549960; 2'b01, 2'b10, 2'b11: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185 = - _theResult___exp__h550688; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185 = + _theResult___exp__h550689; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h549959 or + _theResult___fst_exp__h549960 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 or - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185) + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - _theResult___fst_exp__h549959; + _theResult___fst_exp__h549960; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538; @@ -36187,49 +36187,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = 11'd0; endcase end - always@(guard__h541733 or - _theResult___fst_exp__h549959 or - out_exp__h550691 or _theResult___exp__h550688) + always@(guard__h541734 or + _theResult___fst_exp__h549960 or + out_exp__h550692 or _theResult___exp__h550689) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 = - _theResult___fst_exp__h549959; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 = + _theResult___fst_exp__h549960; 2'b10: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 = - out_exp__h550691; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 = + out_exp__h550692; 2'b11: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 = - _theResult___exp__h550688; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 = + _theResult___exp__h550689; endcase end - always@(guard__h550802 or - _theResult___fst_exp__h558792 or _theResult___exp__h559472) + always@(guard__h550803 or + _theResult___fst_exp__h558793 or _theResult___exp__h559473) begin - case (guard__h550802) + case (guard__h550803) 2'b0: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187 = - _theResult___fst_exp__h558792; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187 = + _theResult___fst_exp__h558793; 2'b01, 2'b10, 2'b11: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187 = - _theResult___exp__h559472; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187 = + _theResult___exp__h559473; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h558792 or + _theResult___fst_exp__h558793 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187) + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - _theResult___fst_exp__h558792; + _theResult___fst_exp__h558793; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569; @@ -36238,49 +36238,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = 11'd0; endcase end - always@(guard__h550802 or - _theResult___fst_exp__h558792 or - out_exp__h559475 or _theResult___exp__h559472) + always@(guard__h550803 or + _theResult___fst_exp__h558793 or + out_exp__h559476 or _theResult___exp__h559473) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 = - _theResult___fst_exp__h558792; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 = + _theResult___fst_exp__h558793; 2'b10: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 = - out_exp__h559475; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 = + out_exp__h559476; 2'b11: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 = - _theResult___exp__h559472; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 = + _theResult___exp__h559473; endcase end - always@(guard__h581037 or - _theResult___fst_exp__h589263 or _theResult___exp__h589992) + always@(guard__h581038 or + _theResult___fst_exp__h589264 or _theResult___exp__h589993) begin - case (guard__h581037) + case (guard__h581038) 2'b0: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189 = - _theResult___fst_exp__h589263; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189 = + _theResult___fst_exp__h589264; 2'b01, 2'b10, 2'b11: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189 = - _theResult___exp__h589992; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189 = + _theResult___exp__h589993; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h589263 or + _theResult___fst_exp__h589264 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189) + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - _theResult___fst_exp__h589263; + _theResult___fst_exp__h589264; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; @@ -36289,49 +36289,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = 11'd0; endcase end - always@(guard__h581037 or - _theResult___fst_exp__h589263 or - out_exp__h589995 or _theResult___exp__h589992) + always@(guard__h581038 or + _theResult___fst_exp__h589264 or + out_exp__h589996 or _theResult___exp__h589993) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 = - _theResult___fst_exp__h589263; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 = + _theResult___fst_exp__h589264; 2'b10: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 = - out_exp__h589995; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 = + out_exp__h589996; 2'b11: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 = - _theResult___exp__h589992; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 = + _theResult___exp__h589993; endcase end - always@(guard__h590106 or - _theResult___fst_exp__h598096 or _theResult___exp__h598776) + always@(guard__h590107 or + _theResult___fst_exp__h598097 or _theResult___exp__h598777) begin - case (guard__h590106) + case (guard__h590107) 2'b0: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191 = - _theResult___fst_exp__h598096; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = + _theResult___fst_exp__h598097; 2'b01, 2'b10, 2'b11: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191 = - _theResult___exp__h598776; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = + _theResult___exp__h598777; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h598096 or + _theResult___fst_exp__h598097 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191) + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - _theResult___fst_exp__h598096; + _theResult___fst_exp__h598097; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799; @@ -36340,44 +36340,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase end - always@(guard__h590106 or - _theResult___fst_exp__h598096 or - out_exp__h598779 or _theResult___exp__h598776) + always@(guard__h590107 or + _theResult___fst_exp__h598097 or + out_exp__h598780 or _theResult___exp__h598777) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 = - _theResult___fst_exp__h598096; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = + _theResult___fst_exp__h598097; 2'b10: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 = - out_exp__h598779; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = + out_exp__h598780; 2'b11: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 = - _theResult___exp__h598776; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = + _theResult___exp__h598777; endcase end - always@(guard__h532421 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01, 2'b10: - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h532421 == 2'b11 && + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h532422 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532421) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36387,12 +36387,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h532421 == 2'b0) ? + (guard__h532422 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532421 == 2'b01 || guard__h532421 == 2'b10 || - guard__h532421 == 2'b11) && + (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || + guard__h532422 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36403,23 +36403,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541733 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541734 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h541733 == 2'b11 && + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h541734 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541733) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541734) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36429,12 +36429,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h541733 == 2'b0) ? + (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h541733 == 2'b01 || guard__h541733 == 2'b10 || - guard__h541733 == 2'b11) && + (guard__h541734 == 2'b01 || guard__h541734 == 2'b10 || + guard__h541734 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36445,23 +36445,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550802 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h550802 == 2'b11 && + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h550803 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550802) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550803) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36471,12 +36471,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h550802 == 2'b0) ? + (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h550802 == 2'b01 || guard__h550802 == 2'b10 || - guard__h550802 == 2'b11) && + (guard__h550803 == 2'b01 || guard__h550803 == 2'b10 || + guard__h550803 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36487,23 +36487,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541733 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541734 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h541733 != 2'b11 || + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h541734 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541733) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541734) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36513,12 +36513,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h541733 == 2'b0) ? + (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h541733 != 2'b01 && guard__h541733 != 2'b10 && - guard__h541733 != 2'b11 || + guard__h541734 != 2'b01 && guard__h541734 != 2'b10 && + guard__h541734 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36529,23 +36529,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550802 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h550802 != 2'b11 || + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550802) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550803) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36555,12 +36555,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h550802 == 2'b0) ? + (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h550802 != 2'b01 && guard__h550802 != 2'b10 && - guard__h550802 != 2'b11 || + guard__h550803 != 2'b01 && guard__h550803 != 2'b10 && + guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36571,23 +36571,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532421 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01, 2'b10: - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h532421 != 2'b11 || + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532422 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532421) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36597,12 +36597,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h532421 == 2'b0) ? + (guard__h532422 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532421 != 2'b01 && guard__h532421 != 2'b10 && - guard__h532421 != 2'b11 || + guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && + guard__h532422 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36613,28 +36613,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532421 or - _theResult___snd__h540333 or _theResult___sfd__h541038) + always@(guard__h532422 or + _theResult___snd__h540334 or _theResult___sfd__h541039) begin - case (guard__h532421) + case (guard__h532422) 2'b0: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205 = - _theResult___snd__h540333[56:5]; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205 = + _theResult___snd__h540334[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205 = - _theResult___sfd__h541038; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205 = + _theResult___sfd__h541039; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h540333 or + _theResult___snd__h540334 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 or - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205) + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - _theResult___snd__h540333[56:5]; + _theResult___snd__h540334[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595; @@ -36643,48 +36643,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = 52'd0; endcase end - always@(guard__h532421 or - _theResult___snd__h540333 or - out_sfd__h541041 or _theResult___sfd__h541038) + always@(guard__h532422 or + _theResult___snd__h540334 or + out_sfd__h541042 or _theResult___sfd__h541039) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 = - _theResult___snd__h540333[56:5]; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 = + _theResult___snd__h540334[56:5]; 2'b10: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 = - out_sfd__h541041; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 = + out_sfd__h541042; 2'b11: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 = - _theResult___sfd__h541038; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 = + _theResult___sfd__h541039; endcase end - always@(guard__h541733 or sfdin__h549953 or _theResult___sfd__h550689) + always@(guard__h541734 or sfdin__h549954 or _theResult___sfd__h550690) begin - case (guard__h541733) + case (guard__h541734) 2'b0: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h549953[56:5]; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h549954[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h550689; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h550690; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h549953 or + sfdin__h549954 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207) + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - sfdin__h549953[56:5]; + sfdin__h549954[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621; @@ -36693,48 +36693,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase end - always@(guard__h541733 or - sfdin__h549953 or out_sfd__h550692 or _theResult___sfd__h550689) + always@(guard__h541734 or + sfdin__h549954 or out_sfd__h550693 or _theResult___sfd__h550690) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h549953[56:5]; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h549954[56:5]; 2'b10: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h550692; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h550693; 2'b11: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h550689; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h550690; endcase end - always@(guard__h550802 or - _theResult___snd__h558738 or _theResult___sfd__h559473) + always@(guard__h550803 or + _theResult___snd__h558739 or _theResult___sfd__h559474) begin - case (guard__h550802) + case (guard__h550803) 2'b0: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209 = - _theResult___snd__h558738[56:5]; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___snd__h558739[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209 = - _theResult___sfd__h559473; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___sfd__h559474; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558738 or + _theResult___snd__h558739 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209) + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558738[56:5]; + _theResult___snd__h558739[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; @@ -36743,49 +36743,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = 52'd0; endcase end - always@(guard__h550802 or - _theResult___snd__h558738 or - out_sfd__h559476 or _theResult___sfd__h559473) + always@(guard__h550803 or + _theResult___snd__h558739 or + out_sfd__h559477 or _theResult___sfd__h559474) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 = - _theResult___snd__h558738[56:5]; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___snd__h558739[56:5]; 2'b10: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 = - out_sfd__h559476; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + out_sfd__h559477; 2'b11: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 = - _theResult___sfd__h559473; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___sfd__h559474; endcase end - always@(guard__h502880 or - _theResult___fst_exp__h511106 or _theResult___exp__h511835) + always@(guard__h502881 or + _theResult___fst_exp__h511107 or _theResult___exp__h511836) begin - case (guard__h502880) + case (guard__h502881) 2'b0: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211 = - _theResult___fst_exp__h511106; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211 = + _theResult___fst_exp__h511107; 2'b01, 2'b10, 2'b11: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211 = - _theResult___exp__h511835; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211 = + _theResult___exp__h511836; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h511106 or + _theResult___fst_exp__h511107 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 or - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211) + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - _theResult___fst_exp__h511106; + _theResult___fst_exp__h511107; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058; @@ -36794,49 +36794,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = 11'd0; endcase end - always@(guard__h502880 or - _theResult___fst_exp__h511106 or - out_exp__h511838 or _theResult___exp__h511835) + always@(guard__h502881 or + _theResult___fst_exp__h511107 or + out_exp__h511839 or _theResult___exp__h511836) begin - case (guard__h502880) + case (guard__h502881) 2'b0, 2'b01: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 = - _theResult___fst_exp__h511106; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 = + _theResult___fst_exp__h511107; 2'b10: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 = - out_exp__h511838; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 = + out_exp__h511839; 2'b11: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 = - _theResult___exp__h511835; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 = + _theResult___exp__h511836; endcase end - always@(guard__h511949 or - _theResult___fst_exp__h519939 or _theResult___exp__h520619) + always@(guard__h511950 or + _theResult___fst_exp__h519940 or _theResult___exp__h520620) begin - case (guard__h511949) + case (guard__h511950) 2'b0: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213 = - _theResult___fst_exp__h519939; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213 = + _theResult___fst_exp__h519940; 2'b01, 2'b10, 2'b11: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213 = - _theResult___exp__h520619; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213 = + _theResult___exp__h520620; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h519939 or + _theResult___fst_exp__h519940 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 or - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213) + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - _theResult___fst_exp__h519939; + _theResult___fst_exp__h519940; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089; @@ -36845,49 +36845,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = 11'd0; endcase end - always@(guard__h511949 or - _theResult___fst_exp__h519939 or - out_exp__h520622 or _theResult___exp__h520619) + always@(guard__h511950 or + _theResult___fst_exp__h519940 or + out_exp__h520623 or _theResult___exp__h520620) begin - case (guard__h511949) + case (guard__h511950) 2'b0, 2'b01: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 = - _theResult___fst_exp__h519939; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 = + _theResult___fst_exp__h519940; 2'b10: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 = - out_exp__h520622; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 = + out_exp__h520623; 2'b11: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 = - _theResult___exp__h520619; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 = + _theResult___exp__h520620; endcase end - always@(guard__h493568 or - _theResult___snd__h501480 or _theResult___sfd__h502185) + always@(guard__h493569 or + _theResult___snd__h501481 or _theResult___sfd__h502186) begin - case (guard__h493568) + case (guard__h493569) 2'b0: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215 = - _theResult___snd__h501480[56:5]; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = + _theResult___snd__h501481[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215 = - _theResult___sfd__h502185; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = + _theResult___sfd__h502186; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h501480 or + _theResult___snd__h501481 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215) + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - _theResult___snd__h501480[56:5]; + _theResult___snd__h501481[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115; @@ -36896,48 +36896,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase end - always@(guard__h493568 or - _theResult___snd__h501480 or - out_sfd__h502188 or _theResult___sfd__h502185) + always@(guard__h493569 or + _theResult___snd__h501481 or + out_sfd__h502189 or _theResult___sfd__h502186) begin - case (guard__h493568) + case (guard__h493569) 2'b0, 2'b01: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 = - _theResult___snd__h501480[56:5]; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = + _theResult___snd__h501481[56:5]; 2'b10: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 = - out_sfd__h502188; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = + out_sfd__h502189; 2'b11: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 = - _theResult___sfd__h502185; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = + _theResult___sfd__h502186; endcase end - always@(guard__h502880 or sfdin__h511100 or _theResult___sfd__h511836) + always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) begin - case (guard__h502880) + case (guard__h502881) 2'b0: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h511100[56:5]; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h511101[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h511836; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h511837; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511100 or + sfdin__h511101 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217) + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511100[56:5]; + sfdin__h511101[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; @@ -36946,48 +36946,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = 52'd0; endcase end - always@(guard__h502880 or - sfdin__h511100 or out_sfd__h511839 or _theResult___sfd__h511836) + always@(guard__h502881 or + sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) begin - case (guard__h502880) + case (guard__h502881) 2'b0, 2'b01: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h511100[56:5]; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h511101[56:5]; 2'b10: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h511839; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h511840; 2'b11: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h511836; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h511837; endcase end - always@(guard__h511949 or - _theResult___snd__h519885 or _theResult___sfd__h520620) + always@(guard__h511950 or + _theResult___snd__h519886 or _theResult___sfd__h520621) begin - case (guard__h511949) + case (guard__h511950) 2'b0: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219 = - _theResult___snd__h519885[56:5]; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + _theResult___snd__h519886[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219 = - _theResult___sfd__h520620; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + _theResult___sfd__h520621; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h519885 or + _theResult___snd__h519886 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219) + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - _theResult___snd__h519885[56:5]; + _theResult___snd__h519886[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161; @@ -36996,49 +36996,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase end - always@(guard__h511949 or - _theResult___snd__h519885 or - out_sfd__h520623 or _theResult___sfd__h520620) + always@(guard__h511950 or + _theResult___snd__h519886 or + out_sfd__h520624 or _theResult___sfd__h520621) begin - case (guard__h511949) + case (guard__h511950) 2'b0, 2'b01: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 = - _theResult___snd__h519885[56:5]; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + _theResult___snd__h519886[56:5]; 2'b10: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 = - out_sfd__h520623; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + out_sfd__h520624; 2'b11: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 = - _theResult___sfd__h520620; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + _theResult___sfd__h520621; endcase end - always@(guard__h571725 or - _theResult___snd__h579637 or _theResult___sfd__h580342) + always@(guard__h571726 or + _theResult___snd__h579638 or _theResult___sfd__h580343) begin - case (guard__h571725) + case (guard__h571726) 2'b0: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221 = - _theResult___snd__h579637[56:5]; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221 = + _theResult___snd__h579638[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221 = - _theResult___sfd__h580342; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221 = + _theResult___sfd__h580343; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h579637 or + _theResult___snd__h579638 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 or - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221) + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - _theResult___snd__h579637[56:5]; + _theResult___snd__h579638[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825; @@ -37047,48 +37047,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = 52'd0; endcase end - always@(guard__h571725 or - _theResult___snd__h579637 or - out_sfd__h580345 or _theResult___sfd__h580342) + always@(guard__h571726 or + _theResult___snd__h579638 or + out_sfd__h580346 or _theResult___sfd__h580343) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 = - _theResult___snd__h579637[56:5]; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 = + _theResult___snd__h579638[56:5]; 2'b10: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 = - out_sfd__h580345; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 = + out_sfd__h580346; 2'b11: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 = - _theResult___sfd__h580342; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 = + _theResult___sfd__h580343; endcase end - always@(guard__h581037 or sfdin__h589257 or _theResult___sfd__h589993) + always@(guard__h581038 or sfdin__h589258 or _theResult___sfd__h589994) begin - case (guard__h581037) + case (guard__h581038) 2'b0: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h589257[56:5]; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h589258[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h589993; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h589994; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h589257 or + sfdin__h589258 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 or - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223) + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - sfdin__h589257[56:5]; + sfdin__h589258[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851; @@ -37097,24 +37097,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = 52'd0; endcase end - always@(guard__h581037 or - sfdin__h589257 or out_sfd__h589996 or _theResult___sfd__h589993) + always@(guard__h581038 or + sfdin__h589258 or out_sfd__h589997 or _theResult___sfd__h589994) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h589257[56:5]; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h589258[56:5]; 2'b10: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h589996; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h589997; 2'b11: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h589993; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h589994; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37149,28 +37149,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852; endcase end - always@(guard__h590106 or - _theResult___snd__h598042 or _theResult___sfd__h598777) + always@(guard__h590107 or + _theResult___snd__h598043 or _theResult___sfd__h598778) begin - case (guard__h590106) + case (guard__h590107) 2'b0: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225 = - _theResult___snd__h598042[56:5]; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225 = + _theResult___snd__h598043[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225 = - _theResult___sfd__h598777; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225 = + _theResult___sfd__h598778; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h598042 or + _theResult___snd__h598043 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 or - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225) + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - _theResult___snd__h598042[56:5]; + _theResult___snd__h598043[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870; @@ -37179,25 +37179,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = 52'd0; endcase end - always@(guard__h590106 or - _theResult___snd__h598042 or - out_sfd__h598780 or _theResult___sfd__h598777) + always@(guard__h590107 or + _theResult___snd__h598043 or + out_sfd__h598781 or _theResult___sfd__h598778) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 = - _theResult___snd__h598042[56:5]; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 = + _theResult___snd__h598043[56:5]; 2'b10: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 = - out_sfd__h598780; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 = + out_sfd__h598781; 2'b11: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 = - _theResult___sfd__h598777; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 = + _theResult___sfd__h598778; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37517,10 +37517,10 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h669625 or + always@(k__h669626 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669625) + case (k__h669626) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 = coreFix_aluExe_0_rsAlu$canEnq; @@ -37559,10 +37559,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(k__h669625 or + always@(k__h669626 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669625) + case (k__h669626) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -37708,14 +37708,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h685370 or + always@(idx__h685371 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685370) + case (idx__h685371) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 = fetchStage$pipelines_0_canDeq && @@ -37836,15 +37836,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738; endcase end - always@(k__h669625 or + always@(k__h669626 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h669625) + case (k__h669626) 1'd0: - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -37947,14 +37947,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(idx__h685370 or + always@(idx__h685371 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685370) + case (idx__h685371) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 = (!fetchStage$pipelines_0_canDeq || @@ -38280,16 +38280,16 @@ module mkCore(CLK, begin case (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983) 6'd0: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38302,30 +38302,31 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 54'd0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8], - 2'b0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4], - 2'b0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; + robdeqPort_0_deq_data_BITS_95_TO_32__q245[9], + 3'd0, + robdeqPort_0_deq_data_BITS_95_TO_32__q245[5], + 3'd0, + robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], + 1'd0 }; 6'd10, 6'd23: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38337,9 +38338,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h722429 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h722430 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38347,7 +38348,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38357,7 +38358,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd22, 6'd29: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 52'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'd0, @@ -38371,12 +38372,12 @@ module mkCore(CLK, 1'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h722429 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h722430 = 64'd0; 6'd37: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38385,7 +38386,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h722429 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h722430 = rob$deqPort_0_deq_data[95:32]; endcase end always@(rob$deqPort_0_deq_data) @@ -38446,9 +38447,9 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h723033 = + x__h723034 = IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191; - default: x__h723033 = rob$deqPort_0_deq_data[425:362]; + default: x__h723034 = rob$deqPort_0_deq_data[425:362]; endcase end always@(rob$deqPort_0_deq_data) @@ -41427,7 +41428,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h603884 == 2'd0) + v__h603885 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on diff --git a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v index a81d1dc..e8bcfa3 100644 --- a/src_SSITH_P3/Verilog_RTL_sim/mkCore.v +++ b/src_SSITH_P3/Verilog_RTL_sim/mkCore.v @@ -4560,36 +4560,36 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10059, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2972, - addr__h294422, - curData__h195854, - data_out__h747098, - data_warl_xformed__h731607, - rVal1__h615388, - rVal1__h640614, - trap_val__h719427, - x__h200593, - x__h732275; + addr__h294423, + curData__h195855, + data_out__h746969, + data_warl_xformed__h731608, + rVal1__h615389, + rVal1__h640615, + trap_val__h719428, + x__h200594, + x__h732276; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20, - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q217, - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q218, - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q219, - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q220, - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q205, - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q206, - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q207, - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q208, - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q209, - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q210, - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q221, - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q222, - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q223, - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q224, - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q225, - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q226, - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q215, - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q216, + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q217, + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q218, + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q219, + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q220, + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q205, + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q206, + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q207, + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q208, + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q209, + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q210, + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q221, + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q222, + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q223, + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q224, + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q225, + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q226, + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q215, + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759, @@ -4601,45 +4601,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408; - reg [22 : 0] CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q83, - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q84, - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q87, - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q88, - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q89, - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q90, - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q120, - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q121, - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q50, - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q51, - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q118, - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q119, - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q48, - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q49, - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q122, - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q123, - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q52, - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q53, - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q124, - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q125, - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q54, - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q55, - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q85, - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q86, - _theResult___fst_sfd__h350490, - _theResult___fst_sfd__h359213, - _theResult___fst_sfd__h367795, - _theResult___fst_sfd__h376979, - _theResult___fst_sfd__h385615, - _theResult___fst_sfd__h396189, - _theResult___fst_sfd__h404910, - _theResult___fst_sfd__h413492, - _theResult___fst_sfd__h422676, - _theResult___fst_sfd__h431312, - _theResult___fst_sfd__h441884, - _theResult___fst_sfd__h450605, - _theResult___fst_sfd__h459187, - _theResult___fst_sfd__h468371, - _theResult___fst_sfd__h477007; + reg [22 : 0] CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q83, + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q84, + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q87, + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q88, + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89, + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q90, + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120, + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121, + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50, + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q51, + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118, + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119, + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48, + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q49, + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122, + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q123, + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q52, + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q53, + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q124, + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q125, + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q54, + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q55, + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q85, + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q86, + _theResult___fst_sfd__h350491, + _theResult___fst_sfd__h359214, + _theResult___fst_sfd__h367796, + _theResult___fst_sfd__h376980, + _theResult___fst_sfd__h385616, + _theResult___fst_sfd__h396190, + _theResult___fst_sfd__h404911, + _theResult___fst_sfd__h413493, + _theResult___fst_sfd__h422677, + _theResult___fst_sfd__h431313, + _theResult___fst_sfd__h441885, + _theResult___fst_sfd__h450606, + _theResult___fst_sfd__h459188, + _theResult___fst_sfd__h468372, + _theResult___fst_sfd__h477008; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q286, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283, @@ -4668,24 +4668,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q211, - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q212, - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q213, - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q214, - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q183, - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q184, - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q185, - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q186, - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q187, - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q188, - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q160, - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q161, - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q189, - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q190, - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q191, - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q192, - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q143, - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q144, + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q211, + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q212, + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q213, + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q214, + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q183, + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q184, + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q185, + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q186, + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187, + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188, + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q160, + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q161, + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q189, + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q190, + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191, + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192, + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q143, + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688, @@ -4695,47 +4695,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918; - reg [7 : 0] CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q68, - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q69, - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q76, - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q77, - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q81, - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q82, - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q105, - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q106, - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q35, - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q36, - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q103, - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q104, - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q33, - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q34, - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q111, - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q112, - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q41, - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q42, - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q116, - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q117, - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q46, - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q47, - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q70, - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q71, + reg [7 : 0] CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q68, + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q69, + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q76, + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q77, + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q81, + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q82, + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q105, + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q106, + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q35, + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q36, + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q103, + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q104, + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q33, + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q34, + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q111, + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q112, + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q41, + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q42, + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q116, + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q117, + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q46, + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q47, + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q70, + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q71, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430, - _theResult___fst_exp__h350489, - _theResult___fst_exp__h359212, - _theResult___fst_exp__h367794, - _theResult___fst_exp__h376978, - _theResult___fst_exp__h385614, - _theResult___fst_exp__h396188, - _theResult___fst_exp__h404909, - _theResult___fst_exp__h413491, - _theResult___fst_exp__h422675, - _theResult___fst_exp__h431311, - _theResult___fst_exp__h441883, - _theResult___fst_exp__h450604, - _theResult___fst_exp__h459186, - _theResult___fst_exp__h468370, - _theResult___fst_exp__h477006; + _theResult___fst_exp__h350490, + _theResult___fst_exp__h359213, + _theResult___fst_exp__h367795, + _theResult___fst_exp__h376979, + _theResult___fst_exp__h385615, + _theResult___fst_exp__h396189, + _theResult___fst_exp__h404910, + _theResult___fst_exp__h413492, + _theResult___fst_exp__h422676, + _theResult___fst_exp__h431312, + _theResult___fst_exp__h441884, + _theResult___fst_exp__h450605, + _theResult___fst_exp__h459187, + _theResult___fst_exp__h468371, + _theResult___fst_exp__h477007; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q281, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q277, @@ -4758,8 +4758,8 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d14393, IF_fetchStage_pipelines_0_first__2992_BIT_68_3_ETC___d13365, IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14557, - i__h718403, - i__h718563; + i__h718404, + i__h718564; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q285, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282, @@ -4773,8 +4773,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10832, - x__h290201, - x__h295971; + x__h290202, + x__h295972; reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q300, @@ -4813,46 +4813,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard04923_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94, - CASE_guard04923_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93, - CASE_guard07809_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_guard13853_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, - CASE_guard13853_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95, - CASE_guard16878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard22689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98, - CASE_guard22689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, - CASE_guard37350_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard37350_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard41911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, - CASE_guard41911_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, - CASE_guard46662_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard46662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard50517_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, - CASE_guard50517_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, - CASE_guard50618_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, - CASE_guard50618_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, - CASE_guard55731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard55731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard59226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59, - CASE_guard59226_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58, - CASE_guard59548_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, - CASE_guard59548_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, - CASE_guard68156_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61, - CASE_guard68156_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, - CASE_guard76654_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard76654_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard76992_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, - CASE_guard76992_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, - CASE_guard85966_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard85966_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard95035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard95035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard96216_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, - CASE_guard96216_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, - CASE_guard98497_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_guard04924_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94, + CASE_guard04924_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93, + CASE_guard07810_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard13854_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96, + CASE_guard13854_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95, + CASE_guard16879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard22690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98, + CASE_guard22690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97, + CASE_guard37351_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard37351_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard46663_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard46663_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard50518_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57, + CASE_guard50518_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56, + CASE_guard50619_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129, + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128, + CASE_guard55732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard55732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard59227_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59, + CASE_guard59227_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58, + CASE_guard59549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131, + CASE_guard59549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130, + CASE_guard68157_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61, + CASE_guard68157_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60, + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133, + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132, + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard76655_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard76993_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63, + CASE_guard76993_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62, + CASE_guard85967_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard85967_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard95036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard96217_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92, + CASE_guard96217_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91, + CASE_guard98498_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_k77212_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6563, @@ -4941,7 +4941,7 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11197; wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2027; wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1734; - wire [127 : 0] b__h608064, b__h608140, b__h608241, b__h608253, x__h609065; + wire [127 : 0] b__h608065, b__h608141, b__h608242, b__h608254, x__h609066; wire [68 : 0] execFpuSimple___d11171; wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627, IF_rob_deqPort_0_deq_data__4646_BITS_97_TO_96__ETC___d14819; @@ -4977,175 +4977,175 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15505, - _theResult___fst__h608464, - _theResult___snd__h608465, - a___1__h608078, - a___1__h608469, - a__h607916, + _theResult___fst__h608465, + _theResult___snd__h608466, + a___1__h608079, + a___1__h608470, + a__h607917, amoExec___d882, - b___1__h608079, - b___1__h608530, - b__h607917, - base__h721348, - base__h721368, + b___1__h608080, + b___1__h608531, + b__h607918, + base__h721349, + base__h721369, commitStage_rg_serial_num_4635_PLUS_IF_rob_deq_ETC___d15776, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11260, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11261, - data___1__h479507, - data___1__h480401, - data__h478995, - data__h479889, - fallthrough_pc__h673432, - fallthrough_pc__h689940, - fcsr_csr__read__h615714, - fflags_csr__read__h615689, - frm_csr__read__h615700, - mcause_csr__read__h617356, - mcounteren_csr__read__h617101, - medeleg_csr__read__h616708, - mideleg_csr__read__h616803, - mie_csr__read__h616927, - mip_csr__read__h617589, - mstatus_csr__read__h616560, - mtvec_csr__read__h617009, - n___1__h201996, - n__h197392, - n__read__h617693, - n__read__h617884, - n__read__h6760, - n__read__h735936, - next_pc__h731630, - pc__h721332, - q___1__h480476, - rVal1__h486686, - rVal2__h486687, - r___1__h480503, - res_data__h342291, - res_data__h342296, - res_data__h387993, - res_data__h387998, - res_data__h433688, - res_data__h433693, - resp_addr__h296399, - rg_tdata1__read__h618544, + data___1__h479508, + data___1__h480402, + data__h478996, + data__h479890, + fallthrough_pc__h673433, + fallthrough_pc__h689941, + fcsr_csr__read__h615715, + fflags_csr__read__h615690, + frm_csr__read__h615701, + mcause_csr__read__h617357, + mcounteren_csr__read__h617102, + medeleg_csr__read__h616709, + mideleg_csr__read__h616804, + mie_csr__read__h616928, + mip_csr__read__h617590, + mstatus_csr__read__h616561, + mtvec_csr__read__h617010, + n___1__h201997, + n__h197393, + n__read__h617694, + n__read__h617885, + n__read__h6761, + n__read__h735807, + next_pc__h731631, + pc__h721333, + q___1__h480477, + rVal1__h486687, + rVal2__h486688, + r___1__h480504, + res_data__h342292, + res_data__h342297, + res_data__h387994, + res_data__h387999, + res_data__h433689, + res_data__h433694, + resp_addr__h296400, + rg_tdata1__read__h618545, rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496, robdeqPort_0_deq_data_BITS_95_TO_32__q245, - satp_csr__read__h616417, - scause_csr__read__h616214, - scounteren_csr__read__h616076, - shiftData__h184461, - sie_csr__read__h615980, - sip_csr__read__h616354, - sstatus_csr__read__h615910, - stvec_csr__read__h616023, - trap_val__h718389, + satp_csr__read__h616418, + scause_csr__read__h616215, + scounteren_csr__read__h616077, + shiftData__h184462, + sie_csr__read__h615981, + sip_csr__read__h616355, + sstatus_csr__read__h615911, + stvec_csr__read__h616024, + trap_val__h718390, upd__h3994, upd__h5311, - upd__h6874, - upd__h736047, - v__h614197, - v__h639578, - x__h155289, - x__h158836, - x__h161650, - x__h163498, - x__h18386, - x__h184368, + upd__h6875, + upd__h735918, + v__h614198, + v__h639579, + x__h155290, + x__h158837, + x__h161651, + x__h163499, + x__h18387, x__h184369, - x__h186793, - x__h20924, - x__h291646, - x__h293500, - x__h46293, - x__h486592, + x__h184370, + x__h186794, + x__h20925, + x__h291647, + x__h293501, + x__h46294, x__h486593, x__h486594, - x__h48829, - x__h608453, - x__h623643, + x__h486595, + x__h48830, + x__h608454, x__h623644, - x__h646650, + x__h623645, x__h646651, - x__h711187, - x__h723590, - x__h723782, - x__h735430, - x__h739233, - x__h742438, - x_addr__h318496, - x_quotient__h479691, - x_reg_ifc__read__h615819, - x_remainder__h479692, - y__h626401, - y__h649115, - y__h740125, - y__h743007, - y_avValue__h183534, - y_avValue__h184215, - y_avValue__h483731, - y_avValue__h484414, - y_avValue__h485091, - y_avValue__h615331, - y_avValue__h621621, - y_avValue__h640559, - y_avValue__h644638, - y_avValue_new_pc__h721124, - y_avValue_new_pc__h721310, - y_avValue_snd_snd_snd_snd_snd_fst__h740148, - y_avValue_snd_snd_snd_snd_snd_fst__h743068, - y_avValue_snd_snd_snd_snd_snd_fst__h743104, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h742420; + x__h646652, + x__h711188, + x__h723591, + x__h723783, + x__h735301, + x__h739104, + x__h742309, + x_addr__h318497, + x_quotient__h479692, + x_reg_ifc__read__h615820, + x_remainder__h479693, + y__h626402, + y__h649116, + y__h739996, + y__h742878, + y_avValue__h183535, + y_avValue__h184216, + y_avValue__h483732, + y_avValue__h484415, + y_avValue__h485092, + y_avValue__h615332, + y_avValue__h621622, + y_avValue__h640560, + y_avValue__h644639, + y_avValue_new_pc__h721125, + y_avValue_new_pc__h721311, + y_avValue_snd_snd_snd_snd_snd_fst__h740019, + y_avValue_snd_snd_snd_snd_snd_fst__h742939, + y_avValue_snd_snd_snd_snd_snd_fst__h742975, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h742291; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10767, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9997, IF_csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_c_ETC___d15232, - r1__read__h619387, - r1__read__h619791, - r1__read__h620301, - r1__read__h620306, - r1__read__h620325, - r1__read__h620558, - r1__read__h620724, - r1__read__h620817, - r1__read__h620822, - r1__read__h620841; - wire [61 : 0] r1__read__h619389, - r1__read__h619793, - r1__read__h620308, - r1__read__h620327, - r1__read__h620560, - r1__read__h620700, - r1__read__h620726, - r1__read__h620824, - r1__read__h620843; - wire [60 : 0] r1__read__h620562, - r1__read__h620702, - r1__read__h620728, - r1__read__h620845; - wire [59 : 0] r1__read__h619391, - r1__read__h619795, - r1__read__h620319, - r1__read__h620329, - r1__read__h620564, - r1__read__h620730, - r1__read__h620835, - r1__read__h620847; - wire [58 : 0] r1__read__h619393, - r1__read__h619797, - r1__read__h620331, - r1__read__h620566, - r1__read__h620732, - r1__read__h620849; + r1__read__h619388, + r1__read__h619792, + r1__read__h620302, + r1__read__h620307, + r1__read__h620326, + r1__read__h620559, + r1__read__h620725, + r1__read__h620818, + r1__read__h620823, + r1__read__h620842; + wire [61 : 0] r1__read__h619390, + r1__read__h619794, + r1__read__h620309, + r1__read__h620328, + r1__read__h620561, + r1__read__h620701, + r1__read__h620727, + r1__read__h620825, + r1__read__h620844; + wire [60 : 0] r1__read__h620563, + r1__read__h620703, + r1__read__h620729, + r1__read__h620846; + wire [59 : 0] r1__read__h619392, + r1__read__h619796, + r1__read__h620320, + r1__read__h620330, + r1__read__h620565, + r1__read__h620731, + r1__read__h620836, + r1__read__h620848; + wire [58 : 0] r1__read__h619394, + r1__read__h619798, + r1__read__h620332, + r1__read__h620567, + r1__read__h620733, + r1__read__h620850; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2582, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3112, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2791, - r1__read__h619395, - r1__read__h619799, - r1__read__h620333, - r1__read__h620568, - r1__read__h620704, - r1__read__h620734, - r1__read__h620851, - y__h258551; + r1__read__h619396, + r1__read__h619800, + r1__read__h620334, + r1__read__h620569, + r1__read__h620705, + r1__read__h620735, + r1__read__h620852, + y__h258552; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99, @@ -5173,187 +5173,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442, - _theResult____h350507, - _theResult____h368146, - _theResult____h396206, - _theResult____h413843, - _theResult____h441901, - _theResult____h459538, - _theResult____h507799, - _theResult____h546652, - _theResult____h585956, - _theResult___snd__h358629, - _theResult___snd__h358640, - _theResult___snd__h358642, - _theResult___snd__h358652, - _theResult___snd__h358658, - _theResult___snd__h358681, - _theResult___snd__h367225, - _theResult___snd__h367227, - _theResult___snd__h367234, - _theResult___snd__h367240, - _theResult___snd__h367263, - _theResult___snd__h376395, - _theResult___snd__h376406, - _theResult___snd__h376408, - _theResult___snd__h376418, - _theResult___snd__h376424, - _theResult___snd__h376447, - _theResult___snd__h385015, - _theResult___snd__h385029, - _theResult___snd__h385035, - _theResult___snd__h385053, - _theResult___snd__h404326, - _theResult___snd__h404337, - _theResult___snd__h404339, - _theResult___snd__h404349, - _theResult___snd__h404355, - _theResult___snd__h404378, - _theResult___snd__h412922, - _theResult___snd__h412924, - _theResult___snd__h412931, - _theResult___snd__h412937, - _theResult___snd__h412960, - _theResult___snd__h422092, - _theResult___snd__h422103, - _theResult___snd__h422105, - _theResult___snd__h422115, - _theResult___snd__h422121, - _theResult___snd__h422144, - _theResult___snd__h430712, - _theResult___snd__h430726, - _theResult___snd__h430732, - _theResult___snd__h430750, - _theResult___snd__h450021, - _theResult___snd__h450032, - _theResult___snd__h450034, - _theResult___snd__h450044, - _theResult___snd__h450050, - _theResult___snd__h450073, - _theResult___snd__h458617, - _theResult___snd__h458619, - _theResult___snd__h458626, - _theResult___snd__h458632, - _theResult___snd__h458655, - _theResult___snd__h467787, - _theResult___snd__h467798, - _theResult___snd__h467800, - _theResult___snd__h467810, - _theResult___snd__h467816, - _theResult___snd__h467839, - _theResult___snd__h476407, - _theResult___snd__h476421, - _theResult___snd__h476427, - _theResult___snd__h476445, - _theResult___snd__h506409, - _theResult___snd__h506411, - _theResult___snd__h506418, - _theResult___snd__h506424, - _theResult___snd__h506447, - _theResult___snd__h516046, - _theResult___snd__h516057, - _theResult___snd__h516059, - _theResult___snd__h516069, - _theResult___snd__h516075, - _theResult___snd__h516098, - _theResult___snd__h524814, - _theResult___snd__h524828, - _theResult___snd__h524834, - _theResult___snd__h524852, - _theResult___snd__h545262, - _theResult___snd__h545264, - _theResult___snd__h545271, - _theResult___snd__h545277, - _theResult___snd__h545300, - _theResult___snd__h554899, - _theResult___snd__h554910, - _theResult___snd__h554912, - _theResult___snd__h554922, - _theResult___snd__h554928, - _theResult___snd__h554951, - _theResult___snd__h563667, - _theResult___snd__h563681, - _theResult___snd__h563687, - _theResult___snd__h563705, - _theResult___snd__h584566, - _theResult___snd__h584568, - _theResult___snd__h584575, - _theResult___snd__h584581, - _theResult___snd__h584604, - _theResult___snd__h594203, - _theResult___snd__h594214, - _theResult___snd__h594216, - _theResult___snd__h594226, - _theResult___snd__h594232, - _theResult___snd__h594255, - _theResult___snd__h602971, - _theResult___snd__h602985, - _theResult___snd__h602991, - _theResult___snd__h603009, - r1__read__h620570, - r1__read__h620706, - r1__read__h620736, - r1__read__h620853, - result__h368759, - result__h414456, - result__h460151, - result__h508412, - result__h547265, - result__h586569, - sfd__h342902, - sfd__h388604, - sfd__h434299, - sfd__h487432, - sfd__h526426, - sfd__h565730, - sfdin__h358612, - sfdin__h376378, - sfdin__h404309, - sfdin__h422075, - sfdin__h450004, - sfdin__h467770, - sfdin__h516029, - sfdin__h554882, - sfdin__h594186, - x__h368856, - x__h414553, - x__h460248, - x__h508507, - x__h547360, - x__h586664; - wire [55 : 0] r1__read__h619397, - r1__read__h619801, - r1__read__h620335, - r1__read__h620572, - r1__read__h620738, - r1__read__h620855; - wire [54 : 0] r1__read__h619399, - r1__read__h619803, - r1__read__h620337, - r1__read__h620574, - r1__read__h620740, - r1__read__h620857; - wire [53 : 0] r1__read__h620683, - r1__read__h620708, - r1__read__h620742, - r1__read__h620859, - sfd__h506476, - sfd__h516127, - sfd__h524887, - sfd__h545329, - sfd__h554980, - sfd__h563740, - sfd__h584633, - sfd__h594284, - sfd__h603044, - value__h351129, - value__h396826, - value__h442521; - wire [52 : 0] r1__read__h620576, - r1__read__h620685, - r1__read__h620710, - r1__read__h620744, - r1__read__h620861; + _theResult____h350508, + _theResult____h368147, + _theResult____h396207, + _theResult____h413844, + _theResult____h441902, + _theResult____h459539, + _theResult____h507800, + _theResult____h546653, + _theResult____h585957, + _theResult___snd__h358630, + _theResult___snd__h358641, + _theResult___snd__h358643, + _theResult___snd__h358653, + _theResult___snd__h358659, + _theResult___snd__h358682, + _theResult___snd__h367226, + _theResult___snd__h367228, + _theResult___snd__h367235, + _theResult___snd__h367241, + _theResult___snd__h367264, + _theResult___snd__h376396, + _theResult___snd__h376407, + _theResult___snd__h376409, + _theResult___snd__h376419, + _theResult___snd__h376425, + _theResult___snd__h376448, + _theResult___snd__h385016, + _theResult___snd__h385030, + _theResult___snd__h385036, + _theResult___snd__h385054, + _theResult___snd__h404327, + _theResult___snd__h404338, + _theResult___snd__h404340, + _theResult___snd__h404350, + _theResult___snd__h404356, + _theResult___snd__h404379, + _theResult___snd__h412923, + _theResult___snd__h412925, + _theResult___snd__h412932, + _theResult___snd__h412938, + _theResult___snd__h412961, + _theResult___snd__h422093, + _theResult___snd__h422104, + _theResult___snd__h422106, + _theResult___snd__h422116, + _theResult___snd__h422122, + _theResult___snd__h422145, + _theResult___snd__h430713, + _theResult___snd__h430727, + _theResult___snd__h430733, + _theResult___snd__h430751, + _theResult___snd__h450022, + _theResult___snd__h450033, + _theResult___snd__h450035, + _theResult___snd__h450045, + _theResult___snd__h450051, + _theResult___snd__h450074, + _theResult___snd__h458618, + _theResult___snd__h458620, + _theResult___snd__h458627, + _theResult___snd__h458633, + _theResult___snd__h458656, + _theResult___snd__h467788, + _theResult___snd__h467799, + _theResult___snd__h467801, + _theResult___snd__h467811, + _theResult___snd__h467817, + _theResult___snd__h467840, + _theResult___snd__h476408, + _theResult___snd__h476422, + _theResult___snd__h476428, + _theResult___snd__h476446, + _theResult___snd__h506410, + _theResult___snd__h506412, + _theResult___snd__h506419, + _theResult___snd__h506425, + _theResult___snd__h506448, + _theResult___snd__h516047, + _theResult___snd__h516058, + _theResult___snd__h516060, + _theResult___snd__h516070, + _theResult___snd__h516076, + _theResult___snd__h516099, + _theResult___snd__h524815, + _theResult___snd__h524829, + _theResult___snd__h524835, + _theResult___snd__h524853, + _theResult___snd__h545263, + _theResult___snd__h545265, + _theResult___snd__h545272, + _theResult___snd__h545278, + _theResult___snd__h545301, + _theResult___snd__h554900, + _theResult___snd__h554911, + _theResult___snd__h554913, + _theResult___snd__h554923, + _theResult___snd__h554929, + _theResult___snd__h554952, + _theResult___snd__h563668, + _theResult___snd__h563682, + _theResult___snd__h563688, + _theResult___snd__h563706, + _theResult___snd__h584567, + _theResult___snd__h584569, + _theResult___snd__h584576, + _theResult___snd__h584582, + _theResult___snd__h584605, + _theResult___snd__h594204, + _theResult___snd__h594215, + _theResult___snd__h594217, + _theResult___snd__h594227, + _theResult___snd__h594233, + _theResult___snd__h594256, + _theResult___snd__h602972, + _theResult___snd__h602986, + _theResult___snd__h602992, + _theResult___snd__h603010, + r1__read__h620571, + r1__read__h620707, + r1__read__h620737, + r1__read__h620854, + result__h368760, + result__h414457, + result__h460152, + result__h508413, + result__h547266, + result__h586570, + sfd__h342903, + sfd__h388605, + sfd__h434300, + sfd__h487433, + sfd__h526427, + sfd__h565731, + sfdin__h358613, + sfdin__h376379, + sfdin__h404310, + sfdin__h422076, + sfdin__h450005, + sfdin__h467771, + sfdin__h516030, + sfdin__h554883, + sfdin__h594187, + x__h368857, + x__h414554, + x__h460249, + x__h508508, + x__h547361, + x__h586665; + wire [55 : 0] r1__read__h619398, + r1__read__h619802, + r1__read__h620336, + r1__read__h620573, + r1__read__h620739, + r1__read__h620856; + wire [54 : 0] r1__read__h619400, + r1__read__h619804, + r1__read__h620338, + r1__read__h620575, + r1__read__h620741, + r1__read__h620858; + wire [53 : 0] r1__read__h620684, + r1__read__h620709, + r1__read__h620743, + r1__read__h620860, + sfd__h506477, + sfd__h516128, + sfd__h524888, + sfd__h545330, + sfd__h554981, + sfd__h563741, + sfd__h584634, + sfd__h594285, + sfd__h603045, + value__h351130, + value__h396827, + value__h442522; + wire [52 : 0] r1__read__h620577, + r1__read__h620686, + r1__read__h620711, + r1__read__h620745, + r1__read__h620862; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255, @@ -5375,111 +5375,111 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10766, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9287, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9996, - _theResult___fst_sfd__h491386, - _theResult___fst_sfd__h507214, - _theResult___fst_sfd__h507217, - _theResult___fst_sfd__h516865, - _theResult___fst_sfd__h516868, - _theResult___fst_sfd__h525649, - _theResult___fst_sfd__h525652, - _theResult___fst_sfd__h525661, - _theResult___fst_sfd__h525667, - _theResult___fst_sfd__h530239, - _theResult___fst_sfd__h546067, - _theResult___fst_sfd__h546070, - _theResult___fst_sfd__h555718, - _theResult___fst_sfd__h555721, - _theResult___fst_sfd__h564502, - _theResult___fst_sfd__h564505, - _theResult___fst_sfd__h564514, - _theResult___fst_sfd__h564520, - _theResult___fst_sfd__h569543, - _theResult___fst_sfd__h585371, - _theResult___fst_sfd__h585374, - _theResult___fst_sfd__h595022, - _theResult___fst_sfd__h595025, - _theResult___fst_sfd__h603806, - _theResult___fst_sfd__h603809, - _theResult___fst_sfd__h603818, - _theResult___fst_sfd__h603824, - _theResult___sfd__h507114, - _theResult___sfd__h516765, - _theResult___sfd__h525549, - _theResult___sfd__h545967, - _theResult___sfd__h555618, - _theResult___sfd__h564402, - _theResult___sfd__h585271, - _theResult___sfd__h594922, - _theResult___sfd__h603706, - _theResult___snd_fst_sfd__h487386, - _theResult___snd_fst_sfd__h507220, - _theResult___snd_fst_sfd__h525655, - _theResult___snd_fst_sfd__h526380, - _theResult___snd_fst_sfd__h546073, - _theResult___snd_fst_sfd__h564508, - _theResult___snd_fst_sfd__h565684, - _theResult___snd_fst_sfd__h585377, - _theResult___snd_fst_sfd__h603812, - out___1_sfd__h487134, - out___1_sfd__h526128, - out___1_sfd__h565432, - out_sfd__h507117, - out_sfd__h516768, - out_sfd__h525552, - out_sfd__h545970, - out_sfd__h555621, - out_sfd__h564405, - out_sfd__h585274, - out_sfd__h594925, - out_sfd__h603709; - wire [50 : 0] r1__read__h619401, r1__read__h620578; - wire [49 : 0] r1__read__h620687; - wire [48 : 0] r1__read_BITS_62_TO_14___h739253, - r1__read__h619403, - r1__read__h620689; - wire [46 : 0] r1__read__h619405, r1__read__h620582; - wire [45 : 0] r1__read__h619407, r1__read__h620584; - wire [44 : 0] r1__read__h619409, r1__read__h620586; - wire [43 : 0] r1__read__h619411, r1__read__h620588; - wire [42 : 0] r1__read__h620590; - wire [41 : 0] r1__read__h620592; - wire [40 : 0] r1__read__h620594; + _theResult___fst_sfd__h491387, + _theResult___fst_sfd__h507215, + _theResult___fst_sfd__h507218, + _theResult___fst_sfd__h516866, + _theResult___fst_sfd__h516869, + _theResult___fst_sfd__h525650, + _theResult___fst_sfd__h525653, + _theResult___fst_sfd__h525662, + _theResult___fst_sfd__h525668, + _theResult___fst_sfd__h530240, + _theResult___fst_sfd__h546068, + _theResult___fst_sfd__h546071, + _theResult___fst_sfd__h555719, + _theResult___fst_sfd__h555722, + _theResult___fst_sfd__h564503, + _theResult___fst_sfd__h564506, + _theResult___fst_sfd__h564515, + _theResult___fst_sfd__h564521, + _theResult___fst_sfd__h569544, + _theResult___fst_sfd__h585372, + _theResult___fst_sfd__h585375, + _theResult___fst_sfd__h595023, + _theResult___fst_sfd__h595026, + _theResult___fst_sfd__h603807, + _theResult___fst_sfd__h603810, + _theResult___fst_sfd__h603819, + _theResult___fst_sfd__h603825, + _theResult___sfd__h507115, + _theResult___sfd__h516766, + _theResult___sfd__h525550, + _theResult___sfd__h545968, + _theResult___sfd__h555619, + _theResult___sfd__h564403, + _theResult___sfd__h585272, + _theResult___sfd__h594923, + _theResult___sfd__h603707, + _theResult___snd_fst_sfd__h487387, + _theResult___snd_fst_sfd__h507221, + _theResult___snd_fst_sfd__h525656, + _theResult___snd_fst_sfd__h526381, + _theResult___snd_fst_sfd__h546074, + _theResult___snd_fst_sfd__h564509, + _theResult___snd_fst_sfd__h565685, + _theResult___snd_fst_sfd__h585378, + _theResult___snd_fst_sfd__h603813, + out___1_sfd__h487135, + out___1_sfd__h526129, + out___1_sfd__h565433, + out_sfd__h507118, + out_sfd__h516769, + out_sfd__h525553, + out_sfd__h545971, + out_sfd__h555622, + out_sfd__h564406, + out_sfd__h585275, + out_sfd__h594926, + out_sfd__h603710; + wire [50 : 0] r1__read__h619402, r1__read__h620579; + wire [49 : 0] r1__read__h620688; + wire [48 : 0] r1__read_BITS_62_TO_14___h739124, + r1__read__h619404, + r1__read__h620690; + wire [46 : 0] r1__read__h619406, r1__read__h620583; + wire [45 : 0] r1__read__h619408, r1__read__h620585; + wire [44 : 0] r1__read__h619410, r1__read__h620587; + wire [43 : 0] r1__read__h619412, r1__read__h620589; + wire [42 : 0] r1__read__h620591; + wire [41 : 0] r1__read__h620593; + wire [40 : 0] r1__read__h620595; wire [37 : 0] IF_fetchStage_pipelines_0_first__2992_BIT_160__ETC___d14396, IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14560; wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data78995_BITS_31_TO_0__q11, - data79889_BITS_31_TO_0__q14, - imm__h662587, - r1__read__h619413, - r1__read__h620596, - x__h196617, - x__h342306, - x__h388008, - x__h433703, - x__h76238, - x_data__h66087, - x_data_imm__h684505, - x_data_imm__h701171; - wire [29 : 0] r1__read__h619415, r1__read__h620598; - wire [27 : 0] r1__read__h620600; + data78996_BITS_31_TO_0__q11, + data79890_BITS_31_TO_0__q14, + imm__h662588, + r1__read__h619414, + r1__read__h620597, + x__h196618, + x__h342307, + x__h388009, + x__h433704, + x__h76239, + x_data__h66088, + x_data_imm__h684506, + x_data_imm__h701172; + wire [29 : 0] r1__read__h619416, r1__read__h620599; + wire [27 : 0] r1__read__h620601; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d14442, - sfd__h358710, - sfd__h367292, - sfd__h376476, - sfd__h385088, - sfd__h404407, - sfd__h412989, - sfd__h422173, - sfd__h430785, - sfd__h450102, - sfd__h458684, - sfd__h467868, - sfd__h476480, - value__h492015, - value__h530868, - value__h570172; + sfd__h358711, + sfd__h367293, + sfd__h376477, + sfd__h385089, + sfd__h404408, + sfd__h412990, + sfd__h422174, + sfd__h430786, + sfd__h450103, + sfd__h458685, + sfd__h467869, + sfd__h476481, + value__h492016, + value__h530869, + value__h570173; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449, @@ -5504,74 +5504,74 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908, - _theResult___fst_sfd__h359216, - _theResult___fst_sfd__h367798, - _theResult___fst_sfd__h376982, - _theResult___fst_sfd__h385618, - _theResult___fst_sfd__h385627, - _theResult___fst_sfd__h385633, - _theResult___fst_sfd__h404913, - _theResult___fst_sfd__h413495, - _theResult___fst_sfd__h422679, - _theResult___fst_sfd__h431315, - _theResult___fst_sfd__h431324, - _theResult___fst_sfd__h431330, - _theResult___fst_sfd__h450608, - _theResult___fst_sfd__h459190, - _theResult___fst_sfd__h468374, - _theResult___fst_sfd__h477010, - _theResult___fst_sfd__h477019, - _theResult___fst_sfd__h477025, - _theResult___sfd__h359135, - _theResult___sfd__h367717, - _theResult___sfd__h376901, - _theResult___sfd__h385537, - _theResult___sfd__h385639, - _theResult___sfd__h404832, - _theResult___sfd__h413414, - _theResult___sfd__h422598, - _theResult___sfd__h431234, - _theResult___sfd__h431336, - _theResult___sfd__h450527, - _theResult___sfd__h459109, - _theResult___sfd__h468293, - _theResult___sfd__h476929, - _theResult___sfd__h477031, - _theResult___snd_fst_sfd__h342852, - _theResult___snd_fst_sfd__h367801, - _theResult___snd_fst_sfd__h385621, - _theResult___snd_fst_sfd__h388554, - _theResult___snd_fst_sfd__h413498, - _theResult___snd_fst_sfd__h431318, - _theResult___snd_fst_sfd__h434249, - _theResult___snd_fst_sfd__h459193, - _theResult___snd_fst_sfd__h477013, - f1_sfd__h487071, - f2_sfd__h526065, - f3_sfd__h565369, - out_f_sfd__h385916, - out_f_sfd__h431613, - out_f_sfd__h477308, - out_sfd__h359138, - out_sfd__h367720, - out_sfd__h376904, - out_sfd__h385540, - out_sfd__h404835, - out_sfd__h413417, - out_sfd__h422601, - out_sfd__h431237, - out_sfd__h450530, - out_sfd__h459112, - out_sfd__h468296, - out_sfd__h476932; - wire [19 : 0] r1__read__h620535; + _theResult___fst_sfd__h359217, + _theResult___fst_sfd__h367799, + _theResult___fst_sfd__h376983, + _theResult___fst_sfd__h385619, + _theResult___fst_sfd__h385628, + _theResult___fst_sfd__h385634, + _theResult___fst_sfd__h404914, + _theResult___fst_sfd__h413496, + _theResult___fst_sfd__h422680, + _theResult___fst_sfd__h431316, + _theResult___fst_sfd__h431325, + _theResult___fst_sfd__h431331, + _theResult___fst_sfd__h450609, + _theResult___fst_sfd__h459191, + _theResult___fst_sfd__h468375, + _theResult___fst_sfd__h477011, + _theResult___fst_sfd__h477020, + _theResult___fst_sfd__h477026, + _theResult___sfd__h359136, + _theResult___sfd__h367718, + _theResult___sfd__h376902, + _theResult___sfd__h385538, + _theResult___sfd__h385640, + _theResult___sfd__h404833, + _theResult___sfd__h413415, + _theResult___sfd__h422599, + _theResult___sfd__h431235, + _theResult___sfd__h431337, + _theResult___sfd__h450528, + _theResult___sfd__h459110, + _theResult___sfd__h468294, + _theResult___sfd__h476930, + _theResult___sfd__h477032, + _theResult___snd_fst_sfd__h342853, + _theResult___snd_fst_sfd__h367802, + _theResult___snd_fst_sfd__h385622, + _theResult___snd_fst_sfd__h388555, + _theResult___snd_fst_sfd__h413499, + _theResult___snd_fst_sfd__h431319, + _theResult___snd_fst_sfd__h434250, + _theResult___snd_fst_sfd__h459194, + _theResult___snd_fst_sfd__h477014, + f1_sfd__h487072, + f2_sfd__h526066, + f3_sfd__h565370, + out_f_sfd__h385917, + out_f_sfd__h431614, + out_f_sfd__h477309, + out_sfd__h359139, + out_sfd__h367721, + out_sfd__h376905, + out_sfd__h385541, + out_sfd__h404836, + out_sfd__h413418, + out_sfd__h422602, + out_sfd__h431238, + out_sfd__h450531, + out_sfd__h459113, + out_sfd__h468297, + out_sfd__h476933; + wire [19 : 0] r1__read__h620536; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059, - _theResult____h658376, - enabled_ints___1__h658901, - enabled_ints__h658947, - pend_ints__h658374, - y__h658913; - wire [13 : 0] r1__read_BITS_13_TO_0___h658923; + _theResult____h658377, + enabled_ints___1__h658902, + enabled_ints__h658948, + pend_ints__h658375, + y__h658914; + wire [13 : 0] r1__read_BITS_13_TO_0___h658924; wire [12 : 0] IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15602, fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13921, rob_deqPort_0_deq_data__4646_BIT_181_4721_CONC_ETC___d14812; @@ -5604,25 +5604,25 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438, - csr_addr__h662585, - renaming_spec_bits__h693437, - result__h653953, - result__h654004, - spec_bits__h696596, - w__h653948, - x__h368889, - x__h414586, - x__h460281, - x__h508540, - x__h547393, - x__h586697, - x__h653952, - x__h654003, - y__h653982, - y__h696609, - y_avValue_fst__h689769, - y_avValue_fst__h689798, - y_avValue_fst__h689832; + csr_addr__h662586, + renaming_spec_bits__h693438, + result__h653954, + result__h654005, + spec_bits__h696597, + w__h653949, + x__h368890, + x__h414587, + x__h460282, + x__h508541, + x__h547394, + x__h586698, + x__h653953, + x__h654004, + y__h653983, + y__h696610, + y_avValue_fst__h689770, + y_avValue_fst__h689799, + y_avValue_fst__h689833; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171, @@ -5644,102 +5644,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h507113, - _theResult___exp__h516764, - _theResult___exp__h525548, - _theResult___exp__h545966, - _theResult___exp__h555617, - _theResult___exp__h564401, - _theResult___exp__h585270, - _theResult___exp__h594921, - _theResult___exp__h603705, - _theResult___fst_exp__h491385, - _theResult___fst_exp__h506449, - _theResult___fst_exp__h506455, - _theResult___fst_exp__h506458, - _theResult___fst_exp__h507213, - _theResult___fst_exp__h507216, - _theResult___fst_exp__h516035, - _theResult___fst_exp__h516100, - _theResult___fst_exp__h516106, - _theResult___fst_exp__h516109, - _theResult___fst_exp__h516864, - _theResult___fst_exp__h516867, - _theResult___fst_exp__h524820, - _theResult___fst_exp__h524859, - _theResult___fst_exp__h524865, - _theResult___fst_exp__h524868, - _theResult___fst_exp__h525648, - _theResult___fst_exp__h525651, - _theResult___fst_exp__h525660, - _theResult___fst_exp__h525663, - _theResult___fst_exp__h530238, - _theResult___fst_exp__h545302, - _theResult___fst_exp__h545308, - _theResult___fst_exp__h545311, - _theResult___fst_exp__h546066, - _theResult___fst_exp__h546069, - _theResult___fst_exp__h554888, - _theResult___fst_exp__h554953, - _theResult___fst_exp__h554959, - _theResult___fst_exp__h554962, - _theResult___fst_exp__h555717, - _theResult___fst_exp__h555720, - _theResult___fst_exp__h563673, - _theResult___fst_exp__h563712, - _theResult___fst_exp__h563718, - _theResult___fst_exp__h563721, - _theResult___fst_exp__h564501, - _theResult___fst_exp__h564504, - _theResult___fst_exp__h564513, - _theResult___fst_exp__h564516, - _theResult___fst_exp__h569542, - _theResult___fst_exp__h584606, - _theResult___fst_exp__h584612, - _theResult___fst_exp__h584615, - _theResult___fst_exp__h585370, - _theResult___fst_exp__h585373, - _theResult___fst_exp__h594192, - _theResult___fst_exp__h594257, - _theResult___fst_exp__h594263, - _theResult___fst_exp__h594266, - _theResult___fst_exp__h595021, - _theResult___fst_exp__h595024, - _theResult___fst_exp__h602977, - _theResult___fst_exp__h603016, - _theResult___fst_exp__h603022, - _theResult___fst_exp__h603025, - _theResult___fst_exp__h603805, - _theResult___fst_exp__h603808, - _theResult___fst_exp__h603817, - _theResult___fst_exp__h603820, - _theResult___snd_fst_exp__h507219, - _theResult___snd_fst_exp__h525654, - _theResult___snd_fst_exp__h546072, - _theResult___snd_fst_exp__h564507, - _theResult___snd_fst_exp__h585376, - _theResult___snd_fst_exp__h603811, + _theResult___exp__h507114, + _theResult___exp__h516765, + _theResult___exp__h525549, + _theResult___exp__h545967, + _theResult___exp__h555618, + _theResult___exp__h564402, + _theResult___exp__h585271, + _theResult___exp__h594922, + _theResult___exp__h603706, + _theResult___fst_exp__h491386, + _theResult___fst_exp__h506450, + _theResult___fst_exp__h506456, + _theResult___fst_exp__h506459, + _theResult___fst_exp__h507214, + _theResult___fst_exp__h507217, + _theResult___fst_exp__h516036, + _theResult___fst_exp__h516101, + _theResult___fst_exp__h516107, + _theResult___fst_exp__h516110, + _theResult___fst_exp__h516865, + _theResult___fst_exp__h516868, + _theResult___fst_exp__h524821, + _theResult___fst_exp__h524860, + _theResult___fst_exp__h524866, + _theResult___fst_exp__h524869, + _theResult___fst_exp__h525649, + _theResult___fst_exp__h525652, + _theResult___fst_exp__h525661, + _theResult___fst_exp__h525664, + _theResult___fst_exp__h530239, + _theResult___fst_exp__h545303, + _theResult___fst_exp__h545309, + _theResult___fst_exp__h545312, + _theResult___fst_exp__h546067, + _theResult___fst_exp__h546070, + _theResult___fst_exp__h554889, + _theResult___fst_exp__h554954, + _theResult___fst_exp__h554960, + _theResult___fst_exp__h554963, + _theResult___fst_exp__h555718, + _theResult___fst_exp__h555721, + _theResult___fst_exp__h563674, + _theResult___fst_exp__h563713, + _theResult___fst_exp__h563719, + _theResult___fst_exp__h563722, + _theResult___fst_exp__h564502, + _theResult___fst_exp__h564505, + _theResult___fst_exp__h564514, + _theResult___fst_exp__h564517, + _theResult___fst_exp__h569543, + _theResult___fst_exp__h584607, + _theResult___fst_exp__h584613, + _theResult___fst_exp__h584616, + _theResult___fst_exp__h585371, + _theResult___fst_exp__h585374, + _theResult___fst_exp__h594193, + _theResult___fst_exp__h594258, + _theResult___fst_exp__h594264, + _theResult___fst_exp__h594267, + _theResult___fst_exp__h595022, + _theResult___fst_exp__h595025, + _theResult___fst_exp__h602978, + _theResult___fst_exp__h603017, + _theResult___fst_exp__h603023, + _theResult___fst_exp__h603026, + _theResult___fst_exp__h603806, + _theResult___fst_exp__h603809, + _theResult___fst_exp__h603818, + _theResult___fst_exp__h603821, + _theResult___snd_fst_exp__h507220, + _theResult___snd_fst_exp__h525655, + _theResult___snd_fst_exp__h546073, + _theResult___snd_fst_exp__h564508, + _theResult___snd_fst_exp__h585377, + _theResult___snd_fst_exp__h603812, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q72, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q37, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q107, - din_inc___2_exp__h525708, - din_inc___2_exp__h525743, - din_inc___2_exp__h525769, - din_inc___2_exp__h564561, - din_inc___2_exp__h564596, - din_inc___2_exp__h564622, - din_inc___2_exp__h603865, - din_inc___2_exp__h603900, - din_inc___2_exp__h603926, - out_exp__h507116, - out_exp__h516767, - out_exp__h525551, - out_exp__h545969, - out_exp__h555620, - out_exp__h564404, - out_exp__h585273, - out_exp__h594924, - out_exp__h603708; + din_inc___2_exp__h525709, + din_inc___2_exp__h525744, + din_inc___2_exp__h525770, + din_inc___2_exp__h564562, + din_inc___2_exp__h564597, + din_inc___2_exp__h564623, + din_inc___2_exp__h603866, + din_inc___2_exp__h603901, + din_inc___2_exp__h603927, + out_exp__h507117, + out_exp__h516768, + out_exp__h525552, + out_exp__h545970, + out_exp__h555621, + out_exp__h564405, + out_exp__h585274, + out_exp__h594925, + out_exp__h603709; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4972, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756; @@ -5770,124 +5770,124 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q78, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q43, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q113, - _theResult___exp__h359134, - _theResult___exp__h367716, - _theResult___exp__h376900, - _theResult___exp__h385536, - _theResult___exp__h385638, - _theResult___exp__h404831, - _theResult___exp__h413413, - _theResult___exp__h422597, - _theResult___exp__h431233, - _theResult___exp__h431335, - _theResult___exp__h450526, - _theResult___exp__h459108, - _theResult___exp__h468292, - _theResult___exp__h476928, - _theResult___exp__h477030, - _theResult___fst_exp__h358618, - _theResult___fst_exp__h358683, - _theResult___fst_exp__h358689, - _theResult___fst_exp__h358692, - _theResult___fst_exp__h359215, - _theResult___fst_exp__h367265, - _theResult___fst_exp__h367271, - _theResult___fst_exp__h367274, - _theResult___fst_exp__h367797, - _theResult___fst_exp__h376384, - _theResult___fst_exp__h376449, - _theResult___fst_exp__h376455, - _theResult___fst_exp__h376458, - _theResult___fst_exp__h376981, - _theResult___fst_exp__h385021, - _theResult___fst_exp__h385060, - _theResult___fst_exp__h385066, - _theResult___fst_exp__h385069, - _theResult___fst_exp__h385617, - _theResult___fst_exp__h385626, - _theResult___fst_exp__h385629, - _theResult___fst_exp__h404315, - _theResult___fst_exp__h404380, - _theResult___fst_exp__h404386, - _theResult___fst_exp__h404389, - _theResult___fst_exp__h404912, - _theResult___fst_exp__h412962, - _theResult___fst_exp__h412968, - _theResult___fst_exp__h412971, - _theResult___fst_exp__h413494, - _theResult___fst_exp__h422081, - _theResult___fst_exp__h422146, - _theResult___fst_exp__h422152, - _theResult___fst_exp__h422155, - _theResult___fst_exp__h422678, - _theResult___fst_exp__h430718, - _theResult___fst_exp__h430757, - _theResult___fst_exp__h430763, - _theResult___fst_exp__h430766, - _theResult___fst_exp__h431314, - _theResult___fst_exp__h431323, - _theResult___fst_exp__h431326, - _theResult___fst_exp__h450010, - _theResult___fst_exp__h450075, - _theResult___fst_exp__h450081, - _theResult___fst_exp__h450084, - _theResult___fst_exp__h450607, - _theResult___fst_exp__h458657, - _theResult___fst_exp__h458663, - _theResult___fst_exp__h458666, - _theResult___fst_exp__h459189, - _theResult___fst_exp__h467776, - _theResult___fst_exp__h467841, - _theResult___fst_exp__h467847, - _theResult___fst_exp__h467850, - _theResult___fst_exp__h468373, - _theResult___fst_exp__h476413, - _theResult___fst_exp__h476452, - _theResult___fst_exp__h476458, - _theResult___fst_exp__h476461, - _theResult___fst_exp__h477009, - _theResult___fst_exp__h477018, - _theResult___fst_exp__h477021, - _theResult___snd_fst_exp__h367800, - _theResult___snd_fst_exp__h385620, - _theResult___snd_fst_exp__h413497, - _theResult___snd_fst_exp__h431317, - _theResult___snd_fst_exp__h459192, - _theResult___snd_fst_exp__h477012, - din_inc___2_exp__h385651, - din_inc___2_exp__h385675, - din_inc___2_exp__h385705, - din_inc___2_exp__h385729, - din_inc___2_exp__h431348, - din_inc___2_exp__h431372, - din_inc___2_exp__h431402, - din_inc___2_exp__h431426, - din_inc___2_exp__h477043, - din_inc___2_exp__h477067, - din_inc___2_exp__h477097, - din_inc___2_exp__h477121, - f1_exp87070_MINUS_127__q136, - f1_exp__h487070, - f2_exp26064_MINUS_127__q176, - f2_exp__h526064, - f3_exp65368_MINUS_127__q153, - f3_exp__h565368, - out_exp__h359137, - out_exp__h367719, - out_exp__h376903, - out_exp__h385539, - out_exp__h404834, - out_exp__h413416, - out_exp__h422600, - out_exp__h431236, - out_exp__h450529, - out_exp__h459111, - out_exp__h468295, - out_exp__h476931, - out_f_exp__h385915, - out_f_exp__h431612, - out_f_exp__h477307, - x__h619372; + _theResult___exp__h359135, + _theResult___exp__h367717, + _theResult___exp__h376901, + _theResult___exp__h385537, + _theResult___exp__h385639, + _theResult___exp__h404832, + _theResult___exp__h413414, + _theResult___exp__h422598, + _theResult___exp__h431234, + _theResult___exp__h431336, + _theResult___exp__h450527, + _theResult___exp__h459109, + _theResult___exp__h468293, + _theResult___exp__h476929, + _theResult___exp__h477031, + _theResult___fst_exp__h358619, + _theResult___fst_exp__h358684, + _theResult___fst_exp__h358690, + _theResult___fst_exp__h358693, + _theResult___fst_exp__h359216, + _theResult___fst_exp__h367266, + _theResult___fst_exp__h367272, + _theResult___fst_exp__h367275, + _theResult___fst_exp__h367798, + _theResult___fst_exp__h376385, + _theResult___fst_exp__h376450, + _theResult___fst_exp__h376456, + _theResult___fst_exp__h376459, + _theResult___fst_exp__h376982, + _theResult___fst_exp__h385022, + _theResult___fst_exp__h385061, + _theResult___fst_exp__h385067, + _theResult___fst_exp__h385070, + _theResult___fst_exp__h385618, + _theResult___fst_exp__h385627, + _theResult___fst_exp__h385630, + _theResult___fst_exp__h404316, + _theResult___fst_exp__h404381, + _theResult___fst_exp__h404387, + _theResult___fst_exp__h404390, + _theResult___fst_exp__h404913, + _theResult___fst_exp__h412963, + _theResult___fst_exp__h412969, + _theResult___fst_exp__h412972, + _theResult___fst_exp__h413495, + _theResult___fst_exp__h422082, + _theResult___fst_exp__h422147, + _theResult___fst_exp__h422153, + _theResult___fst_exp__h422156, + _theResult___fst_exp__h422679, + _theResult___fst_exp__h430719, + _theResult___fst_exp__h430758, + _theResult___fst_exp__h430764, + _theResult___fst_exp__h430767, + _theResult___fst_exp__h431315, + _theResult___fst_exp__h431324, + _theResult___fst_exp__h431327, + _theResult___fst_exp__h450011, + _theResult___fst_exp__h450076, + _theResult___fst_exp__h450082, + _theResult___fst_exp__h450085, + _theResult___fst_exp__h450608, + _theResult___fst_exp__h458658, + _theResult___fst_exp__h458664, + _theResult___fst_exp__h458667, + _theResult___fst_exp__h459190, + _theResult___fst_exp__h467777, + _theResult___fst_exp__h467842, + _theResult___fst_exp__h467848, + _theResult___fst_exp__h467851, + _theResult___fst_exp__h468374, + _theResult___fst_exp__h476414, + _theResult___fst_exp__h476453, + _theResult___fst_exp__h476459, + _theResult___fst_exp__h476462, + _theResult___fst_exp__h477010, + _theResult___fst_exp__h477019, + _theResult___fst_exp__h477022, + _theResult___snd_fst_exp__h367801, + _theResult___snd_fst_exp__h385621, + _theResult___snd_fst_exp__h413498, + _theResult___snd_fst_exp__h431318, + _theResult___snd_fst_exp__h459193, + _theResult___snd_fst_exp__h477013, + din_inc___2_exp__h385652, + din_inc___2_exp__h385676, + din_inc___2_exp__h385706, + din_inc___2_exp__h385730, + din_inc___2_exp__h431349, + din_inc___2_exp__h431373, + din_inc___2_exp__h431403, + din_inc___2_exp__h431427, + din_inc___2_exp__h477044, + din_inc___2_exp__h477068, + din_inc___2_exp__h477098, + din_inc___2_exp__h477122, + f1_exp87071_MINUS_127__q136, + f1_exp__h487071, + f2_exp26065_MINUS_127__q176, + f2_exp__h526065, + f3_exp65369_MINUS_127__q153, + f3_exp__h565369, + out_exp__h359138, + out_exp__h367720, + out_exp__h376904, + out_exp__h385540, + out_exp__h404835, + out_exp__h413417, + out_exp__h422601, + out_exp__h431237, + out_exp__h450530, + out_exp__h459112, + out_exp__h468296, + out_exp__h476932, + out_f_exp__h385916, + out_f_exp__h431613, + out_f_exp__h477308, + x__h619373; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131, @@ -5908,8 +5908,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2176, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426, - x__h184590, - x__h721363; + x__h184591, + x__h721364; wire [4 : 0] IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14613, IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d15994, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5269, @@ -5929,25 +5929,25 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8065, checkForException___d13243, checkForException___d13943, - fflags__h737590, - fflags__h740303, - fflags__h742984, - old_fflags__h742410, - po_fflags__h737575, - po_fflags__h740288, - r1__read__h620938, - res_fflags__h342292, - res_fflags__h387994, - res_fflags__h433689, + fflags__h737461, + fflags__h740174, + fflags__h742855, + old_fflags__h742281, + po_fflags__h737446, + po_fflags__h740159, + r1__read__h620939, + res_fflags__h342293, + res_fflags__h387995, + res_fflags__h433690, rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, - rs1__h662586, - x__h155283, - x__h158830, - x__h161646, - x__h291634, - y_avValue_fst__h739663, - y_avValue_fst__h742889, - y_avValue_fst__h742921; + rs1__h662587, + x__h155284, + x__h158831, + x__h161647, + x__h291635, + y_avValue_fst__h739534, + y_avValue_fst__h742760, + y_avValue_fst__h742792; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1879, IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1881, IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1883, @@ -5974,77 +5974,77 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2933, IF_coreFix_memExe_dTlb_procResp__742_BITS_177__ETC___d1824, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, - cause_code__h718388, - vm_mode_reg__read__h620541; + cause_code__h718389, + vm_mode_reg__read__h620542; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2571, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2890, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, - _theResult_____2__h300943, - dcsr_cause__h717907, - next_deqP___1__h301222, - v__h300363, - v__h300594, - x__h306573, - x_decodeInfo_frm__h662270; + _theResult_____2__h300944, + dcsr_cause__h717908, + next_deqP___1__h301223, + v__h300364, + v__h300595, + x__h306574, + x_decodeInfo_frm__h662271; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d16013, - IF_sfdin04309_BIT_33_THEN_2_ELSE_0__q65, - IF_sfdin16029_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin22075_BIT_33_THEN_2_ELSE_0__q75, - IF_sfdin50004_BIT_33_THEN_2_ELSE_0__q100, - IF_sfdin54882_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin58612_BIT_33_THEN_2_ELSE_0__q30, - IF_sfdin67770_BIT_33_THEN_2_ELSE_0__q110, - IF_sfdin76378_BIT_33_THEN_2_ELSE_0__q40, - IF_sfdin94186_BIT_4_THEN_2_ELSE_0__q156, - IF_theResult___snd02971_BIT_4_THEN_2_ELSE_0__q159, - IF_theResult___snd06409_BIT_4_THEN_2_ELSE_0__q135, - IF_theResult___snd12922_BIT_33_THEN_2_ELSE_0__q67, - IF_theResult___snd24814_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd30712_BIT_33_THEN_2_ELSE_0__q80, - IF_theResult___snd45262_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd58617_BIT_33_THEN_2_ELSE_0__q102, - IF_theResult___snd63667_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd67225_BIT_33_THEN_2_ELSE_0__q32, - IF_theResult___snd76407_BIT_33_THEN_2_ELSE_0__q115, - IF_theResult___snd84566_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd85015_BIT_33_THEN_2_ELSE_0__q45, - guard__h350517, - guard__h359226, - guard__h368156, - guard__h376992, - guard__h396216, - guard__h404923, - guard__h413853, - guard__h422689, - guard__h441911, - guard__h450618, - guard__h459548, - guard__h468384, - guard__h498497, - guard__h507809, - guard__h516878, - guard__h537350, - guard__h546662, - guard__h555731, - guard__h576654, - guard__h585966, - guard__h595035, - prv__h744653, - prv__h744697, - r1__read_BITS_13_TO_12___h662455, - sbIdx__h158709, - v__h609135, - v__h609145, - v__h610176, - x__h731805, - x__h743248, - x_prv__h721432, - x_prv__h732255, - y_avValue_snd_snd_snd_fst__h740138, - y_avValue_snd_snd_snd_fst__h743058, - y_avValue_snd_snd_snd_fst__h743094; + IF_sfdin04310_BIT_33_THEN_2_ELSE_0__q65, + IF_sfdin16030_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin22076_BIT_33_THEN_2_ELSE_0__q75, + IF_sfdin50005_BIT_33_THEN_2_ELSE_0__q100, + IF_sfdin54883_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin58613_BIT_33_THEN_2_ELSE_0__q30, + IF_sfdin67771_BIT_33_THEN_2_ELSE_0__q110, + IF_sfdin76379_BIT_33_THEN_2_ELSE_0__q40, + IF_sfdin94187_BIT_4_THEN_2_ELSE_0__q156, + IF_theResult___snd02972_BIT_4_THEN_2_ELSE_0__q159, + IF_theResult___snd06410_BIT_4_THEN_2_ELSE_0__q135, + IF_theResult___snd12923_BIT_33_THEN_2_ELSE_0__q67, + IF_theResult___snd24815_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd30713_BIT_33_THEN_2_ELSE_0__q80, + IF_theResult___snd45263_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd58618_BIT_33_THEN_2_ELSE_0__q102, + IF_theResult___snd63668_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd67226_BIT_33_THEN_2_ELSE_0__q32, + IF_theResult___snd76408_BIT_33_THEN_2_ELSE_0__q115, + IF_theResult___snd84567_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd85016_BIT_33_THEN_2_ELSE_0__q45, + guard__h350518, + guard__h359227, + guard__h368157, + guard__h376993, + guard__h396217, + guard__h404924, + guard__h413854, + guard__h422690, + guard__h441912, + guard__h450619, + guard__h459549, + guard__h468385, + guard__h498498, + guard__h507810, + guard__h516879, + guard__h537351, + guard__h546663, + guard__h555732, + guard__h576655, + guard__h585967, + guard__h595036, + prv__h744524, + prv__h744568, + r1__read_BITS_13_TO_12___h662456, + sbIdx__h158710, + v__h609136, + v__h609146, + v__h610177, + x__h731806, + x__h743119, + x_prv__h721433, + x_prv__h732256, + y_avValue_snd_snd_snd_fst__h740009, + y_avValue_snd_snd_snd_fst__h742929, + y_avValue_snd_snd_snd_fst__h742965; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5169, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5219, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6561, @@ -6492,11 +6492,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h308939, - _theResult_____2__h314933, - _theResult_____2__h322787, - _theResult_____2__h333131, - _theResult_____2__h336356, + _theResult_____2__h308940, + _theResult_____2__h314934, + _theResult_____2__h322788, + _theResult_____2__h333132, + _theResult_____2__h336357, commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966, coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413, coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12454, @@ -6648,14 +6648,14 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2992_BIT_68_3021_ETC___d14080, fetchStage_pipelines_1_first__3001_BITS_194_TO_ETC___d14218, fetchStage_pipelines_1_first__3001_BITS_199_TO_ETC___d14230, - guard__h368754, - guard__h414451, - guard__h460146, - guard__h508407, - guard__h547260, - guard__h586564, - idx__h693568, - k__h677211, + guard__h368755, + guard__h414452, + guard__h460147, + guard__h508408, + guard__h547261, + guard__h586565, + idx__h693569, + k__h677212, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6668,13 +6668,13 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14339, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h76123, - next_deqP___1__h309218, - next_deqP___1__h315499, - next_deqP___1__h323353, - next_deqP___1__h333410, - next_deqP___1__h336635, - r1__read_BIT_20___h663151, + msip__h76124, + next_deqP___1__h309219, + next_deqP___1__h315500, + next_deqP___1__h323354, + next_deqP___1__h333411, + next_deqP___1__h336636, + r1__read_BIT_20___h663152, regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544, regRenamingTable_RDY_rename_0_getRename__3535__ETC___d14186, regRenamingTable_RDY_rename_1_getRename__4249__ETC___d14267, @@ -6705,19 +6705,19 @@ module mkCore(CLK, renameStage_rg_m_halt_req_3019_BIT_4_3020_OR_f_ETC___d14165, rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16059, rob_RDY_deqPort_0_deq__4643_AND_rob_RDY_deqPor_ETC___d15310, - tsr_val__h735550, - tvm_val__h735552, - v__h303708, - v__h304226, - v__h314222, - v__h314453, - v__h318098, - v__h318329, - v__h332699, - v__h332930, - v__h335924, - v__h336155, - x__h608479; + tsr_val__h735421, + tvm_val__h735423, + v__h303709, + v__h304227, + v__h314223, + v__h314454, + v__h318099, + v__h318330, + v__h332700, + v__h332931, + v__h335925, + v__h336156, + x__h608480; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -12143,13 +12143,13 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h711187, + x__h711188, rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h743007 ; + commitStage_rg_serial_num + y__h742878 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, @@ -12163,7 +12163,7 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h677211 == 1'd0 && + (k__h677212 == 1'd0 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, @@ -12184,7 +12184,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693437, + renaming_spec_bits__h693438, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -12275,7 +12275,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2791, @@ -12289,10 +12289,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h290201 } ; + x__h290202 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h291646, + x__h291647, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12300,7 +12300,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h294422, + addr__h294423, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3042 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12313,12 +12313,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h155283, x__h155289, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h155284, x__h155290, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h158830, x__h158836, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h158831, x__h158837, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h161646, - x__h161650, + { x__h161647, + x__h161651, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224, @@ -12329,7 +12329,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255, - x__h163498, + x__h163499, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271, @@ -12342,7 +12342,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h296399, + resp_addr__h296400, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -12350,8 +12350,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h744697, - prv__h744697 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h744568, + prv__h744568 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12428,7 +12428,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h200593 } ; + x__h200594 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12463,8 +12463,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h195854 : - { {32{x__h196617[31]}}, x__h196617 } } ; + curData__h195855 : + { {32{x__h196618[31]}}, x__h196618 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12497,7 +12497,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h742984 ; + csrf_fflags_reg | fflags__h742855 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == 6'd1) ? @@ -12540,9 +12540,9 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h735936 + 64'd1 ; + n__read__h735807 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h735936 + { 62'd0, x__h743248 } ; + n__read__h735807 + { 62'd0, x__h743119 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295 == @@ -12568,12 +12568,12 @@ module mkCore(CLK, 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h731805 : + x__h731806 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h717907, + dcsr_cause__h717908, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12589,7 +12589,7 @@ module mkCore(CLK, 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h747098 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h746969 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12598,12 +12598,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h731630 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h731631 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h731630; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h731631; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12638,24 +12638,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h342296 : - res_data__h342291 ; + res_data__h342297 : + res_data__h342292 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h387998 : - res_data__h387993 ; + res_data__h387999 : + res_data__h387994 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h433693 : - res_data__h433688 ; + res_data__h433694 : + res_data__h433689 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h479507 : - data__h478995 ; + data___1__h479508 : + data__h478996 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h480401 : - data__h479889 ; + data___1__h480402 : + data__h479890 ; assign MUX_rf$write_3_wr_2__VAL_4 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -12724,15 +12724,15 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h342292 ; + res_fflags__h342293 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h387994 ; + res_fflags__h387995 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h433689 ; + res_fflags__h433690 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, @@ -12748,19 +12748,19 @@ module mkCore(CLK, rob_deqPort_0_deq_data__4646_BIT_166_4662_CONC_ETC___d14711, rob$deqPort_0_deq_data[161:98], IF_rob_deqPort_0_deq_data__4646_BITS_97_TO_96__ETC___d14819, - fflags__h737590, + fflags__h737461, rob$deqPort_0_deq_data[26], - x__h739233, + x__h739104, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, 13'd4932, - mip_csr__read__h617589, + mip_csr__read__h617590, 721'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_5 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, - x__h732275, + x__h732276, rob$deqPort_0_deq_data[361:182], rob_deqPort_0_deq_data__4646_BIT_181_4721_CONC_ETC___d14812, rob$deqPort_0_deq_data[167], @@ -13072,7 +13072,7 @@ module mkCore(CLK, CAN_FIRE_RL_commitStage_rl_send_tv_reset ; // register commitStage_rg_old_mip_csr_val - assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h617589 ; + assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h617590 ; assign commitStage_rg_old_mip_csr_val$EN = CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; @@ -13139,8 +13139,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h610176 : - v__h609135 ; + v__h610177 : + v__h609136 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 @@ -13286,7 +13286,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h300943 ; + _theResult_____2__h300944 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -13308,7 +13308,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h300363 ; + v__h300364 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -13354,7 +13354,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3227 && - _theResult_____2__h308939 ; + _theResult_____2__h308940 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -13372,7 +13372,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3227 && - v__h303708 ; + v__h303709 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13472,7 +13472,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3398 && - _theResult_____2__h314933 ; + _theResult_____2__h314934 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13490,7 +13490,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3398 && - v__h314222 ; + v__h314223 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13511,7 +13511,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h318496, + { x_addr__h318497, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13541,7 +13541,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3494 && - _theResult_____2__h322787 ; + _theResult_____2__h322788 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13559,7 +13559,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3494 && - v__h318098 ; + v__h318099 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13636,7 +13636,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3817 && - _theResult_____2__h336356 ; + _theResult_____2__h336357 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13654,7 +13654,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3817 && - v__h335924 ; + v__h335925 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13697,7 +13697,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3723 && - _theResult_____2__h333131 ; + _theResult_____2__h333132 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13715,7 +13715,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3723 && - v__h332699 ; + v__h332700 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -14074,13 +14074,13 @@ module mkCore(CLK, always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h718388 or + cause_code__h718389 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h718388; + csrf_mcause_code_reg$D_IN = cause_code__h718389; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14343,12 +14343,12 @@ module mkCore(CLK, always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h718389 or + trap_val__h718390 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h718389; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h718390; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14475,13 +14475,13 @@ module mkCore(CLK, always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h721432 or + x_prv__h721433 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h721432; + csrf_prv_reg$D_IN = x_prv__h721433; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; @@ -14638,13 +14638,13 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h718388 or + cause_code__h718389 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h718388; + csrf_scause_code_reg$D_IN = cause_code__h718389; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14868,12 +14868,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h718389 or + trap_val__h718390 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h718389; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h718390; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -15071,7 +15071,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46293, + { x__h46294, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15083,7 +15083,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48829 } ; + x__h48830 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -15176,7 +15176,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18386, + { x__h18387, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15188,7 +15188,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20924 } ; + x__h20925 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -15272,7 +15272,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h66087 } ; + x_data__h66088 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -15515,8 +15515,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q287, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h646650, x__h646651, + x__h646652, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -15806,8 +15806,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q293, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h623643, x__h623644, + x__h623645, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -15849,7 +15849,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h677211 == 1'd1 && + (k__h677212 == 1'd1 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13118, @@ -15870,7 +15870,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693437, + renaming_spec_bits__h693438, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16348,12 +16348,12 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN = - { x__h608453, - b__h607917 == 64'd0, - a__h607916, + { x__h608454, + b__h607918 == 64'd0, + a__h607917, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h608479, - a__h607916[63], + x__h608480, + a__h607917[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && @@ -16368,8 +16368,8 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h608465 : - b__h607917 ; + _theResult___snd__h608466 : + b__h607918 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -16382,7 +16382,7 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN = - { x__h609065, + { x__h609066, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ = CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ; @@ -16463,9 +16463,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q299, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h486592, x__h486593, x__h486594, + x__h486595, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12933 ; @@ -16517,7 +16517,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13829, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693437, + renaming_spec_bits__h693438, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16675,8 +16675,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h291634, - x__h291646, + { x__h291635, + x__h291647, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2890, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2894, @@ -16687,13 +16687,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2920, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2925, - x__h293500, + x__h293501, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2933, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2945 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h290201 ; + x__h290202 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -17487,7 +17487,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3653_AND__ETC___d14414) ? specTagManager$currentSpecBits : - renaming_spec_bits__h693437 ; + renaming_spec_bits__h693438 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3653_AND__ETC___d14422) ? @@ -17507,7 +17507,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3653_AND__ETC___d14422) ? specTagManager$currentSpecBits : - renaming_spec_bits__h693437 ; + renaming_spec_bits__h693438 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17587,7 +17587,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h184461 ; + shiftData__h184462 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17687,8 +17687,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h184368, x__h184369, + x__h184370, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12933 ; @@ -17952,7 +17952,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BIT_160__ETC___d14560, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h693437, + renaming_spec_bits__h693438, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -18400,7 +18400,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h721332 or + pc__h721333 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18414,7 +18414,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h721332; + fetchStage$redirect_pc = pc__h721333; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18834,7 +18834,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h693437 ; + renaming_spec_bits__h693438 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -19106,7 +19106,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_191_ETC___d14554, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d14613, 7'd32, - renaming_spec_bits__h693437 } ; + renaming_spec_bits__h693438 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -19765,9 +19765,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q302, rob$deqPort_1_deq_data[95:32], - fflags__h740303, + fflags__h740174, rob$deqPort_1_deq_data[26], - x__h742438, + x__h742309, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19789,15 +19789,15 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h195854), + .amoExec_current_data(curData__h195855), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h197392)); + .amoExec(n__h197393)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h76123 }), - .amoExec_in_data({ 32'd0, x__h76238 }), + msip__h76124 }), + .amoExec_in_data({ 32'd0, x__h76239 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d882)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], @@ -19829,7 +19829,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208 }, fetchStage$pipelines_0_first[160], - x_data_imm__h684505 } }), + x_data_imm__h684506 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19838,13 +19838,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h662270, - r1__read_BITS_13_TO_12___h662455 != + .checkForException_csrState({ x_decodeInfo_frm__h662271, + r1__read_BITS_13_TO_12___h662456 != 2'd0, - { prv__h744653, - tvm_val__h735552, - { r1__read_BIT_20___h663151, - tsr_val__h735550, + { prv__h744524, + tvm_val__h735423, + { r1__read_BIT_20___h663152, + tsr_val__h735421, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19859,7 +19859,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__3001_BITS_194_ETC___d13829, { fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13921, fetchStage$pipelines_1_first[160], - x_data_imm__h701171 } }), + x_data_imm__h701172 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19868,13 +19868,13 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h662270, - r1__read_BITS_13_TO_12___h662455 != + .checkForException_csrState({ x_decodeInfo_frm__h662271, + r1__read_BITS_13_TO_12___h662456 != 2'd0, - { prv__h744653, - tvm_val__h735552, - { r1__read_BIT_20___h663151, - tsr_val__h735550, + { prv__h744524, + tvm_val__h735423, + { r1__read_BIT_20___h663152, + tsr_val__h735421, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19888,1196 +19888,1196 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h486686), - .execFpuSimple_rVal2(rVal2__h486687), + .execFpuSimple_rVal1(rVal1__h486687), + .execFpuSimple_rVal2(rVal2__h486688), .execFpuSimple(execFpuSimple___d11171)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4349 ? - _theResult___snd__h358681 : - _theResult____h350507 ; + _theResult___snd__h358682 : + _theResult____h350508 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5741 ? - _theResult___snd__h404378 : - _theResult____h396206 ; + _theResult___snd__h404379 : + _theResult____h396207 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7133 ? - _theResult___snd__h450073 : - _theResult____h441901 ; + _theResult___snd__h450074 : + _theResult____h441902 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9012 ? - _theResult___snd__h516098 : - _theResult____h507799 ; + _theResult___snd__h516099 : + _theResult____h507800 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9727 ? - _theResult___snd__h594255 : - _theResult____h585956 ; + _theResult___snd__h594256 : + _theResult____h585957 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10497 ? - _theResult___snd__h554951 : - _theResult____h546652 ; + _theResult___snd__h554952 : + _theResult____h546653 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7684 ? - _theResult___snd__h467839 : - _theResult____h459538 ; + _theResult___snd__h467840 : + _theResult____h459539 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4900 ? - _theResult___snd__h376447 : - _theResult____h368146 ; + _theResult___snd__h376448 : + _theResult____h368147 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6292 ? - _theResult___snd__h422144 : - _theResult____h413843 ; + _theResult___snd__h422145 : + _theResult____h413844 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8700 ? - _theResult___snd__h506447 : + _theResult___snd__h506448 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9062 ? - _theResult___snd__h506447 : - _theResult___snd__h524852 ; + _theResult___snd__h506448 : + _theResult___snd__h524853 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9430 ? - _theResult___snd__h584604 : + _theResult___snd__h584605 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9777 ? - _theResult___snd__h584604 : - _theResult___snd__h603009 ; + _theResult___snd__h584605 : + _theResult___snd__h603010 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10200 ? - _theResult___snd__h545300 : + _theResult___snd__h545301 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10547 ? - _theResult___snd__h545300 : - _theResult___snd__h563705 ; + _theResult___snd__h545301 : + _theResult___snd__h563706 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7364 ? - _theResult___snd__h458655 : + _theResult___snd__h458656 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7757 ? - _theResult___snd__h458655 : - _theResult___snd__h476445 ; + _theResult___snd__h458656 : + _theResult___snd__h476446 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4580 ? - _theResult___snd__h367263 : + _theResult___snd__h367264 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4973 ? - _theResult___snd__h367263 : - _theResult___snd__h385053 ; + _theResult___snd__h367264 : + _theResult___snd__h385054 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5972 ? - _theResult___snd__h412960 : + _theResult___snd__h412961 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6365 ? - _theResult___snd__h412960 : - _theResult___snd__h430750 ; + _theResult___snd__h412961 : + _theResult___snd__h430751 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5169 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - ((_theResult___fst_exp__h358618 == 8'd255) ? + ((_theResult___fst_exp__h358619 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154) : - ((_theResult___fst_exp__h367274 == 8'd255) ? + ((_theResult___fst_exp__h367275 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5219 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - ((_theResult___fst_exp__h358618 == 8'd255) ? + ((_theResult___fst_exp__h358619 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210) : - ((_theResult___fst_exp__h367274 == 8'd255) ? + ((_theResult___fst_exp__h367275 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6561 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - ((_theResult___fst_exp__h404315 == 8'd255) ? + ((_theResult___fst_exp__h404316 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546) : - ((_theResult___fst_exp__h412971 == 8'd255) ? + ((_theResult___fst_exp__h412972 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6611 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - ((_theResult___fst_exp__h404315 == 8'd255) ? + ((_theResult___fst_exp__h404316 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602) : - ((_theResult___fst_exp__h412971 == 8'd255) ? + ((_theResult___fst_exp__h412972 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7953 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - ((_theResult___fst_exp__h450010 == 8'd255) ? + ((_theResult___fst_exp__h450011 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938) : - ((_theResult___fst_exp__h458666 == 8'd255) ? + ((_theResult___fst_exp__h458667 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d8003 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - ((_theResult___fst_exp__h450010 == 8'd255) ? + ((_theResult___fst_exp__h450011 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994) : - ((_theResult___fst_exp__h458666 == 8'd255) ? + ((_theResult___fst_exp__h458667 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347 = - (_theResult____h350507[56] ? + (_theResult____h350508[56] ? 6'd0 : - (_theResult____h350507[55] ? + (_theResult____h350508[55] ? 6'd1 : - (_theResult____h350507[54] ? + (_theResult____h350508[54] ? 6'd2 : - (_theResult____h350507[53] ? + (_theResult____h350508[53] ? 6'd3 : - (_theResult____h350507[52] ? + (_theResult____h350508[52] ? 6'd4 : - (_theResult____h350507[51] ? + (_theResult____h350508[51] ? 6'd5 : - (_theResult____h350507[50] ? + (_theResult____h350508[50] ? 6'd6 : - (_theResult____h350507[49] ? + (_theResult____h350508[49] ? 6'd7 : - (_theResult____h350507[48] ? + (_theResult____h350508[48] ? 6'd8 : - (_theResult____h350507[47] ? + (_theResult____h350508[47] ? 6'd9 : - (_theResult____h350507[46] ? + (_theResult____h350508[46] ? 6'd10 : - (_theResult____h350507[45] ? + (_theResult____h350508[45] ? 6'd11 : - (_theResult____h350507[44] ? + (_theResult____h350508[44] ? 6'd12 : - (_theResult____h350507[43] ? + (_theResult____h350508[43] ? 6'd13 : - (_theResult____h350507[42] ? + (_theResult____h350508[42] ? 6'd14 : - (_theResult____h350507[41] ? + (_theResult____h350508[41] ? 6'd15 : - (_theResult____h350507[40] ? + (_theResult____h350508[40] ? 6'd16 : - (_theResult____h350507[39] ? + (_theResult____h350508[39] ? 6'd17 : - (_theResult____h350507[38] ? + (_theResult____h350508[38] ? 6'd18 : - (_theResult____h350507[37] ? + (_theResult____h350508[37] ? 6'd19 : - (_theResult____h350507[36] ? + (_theResult____h350508[36] ? 6'd20 : - (_theResult____h350507[35] ? + (_theResult____h350508[35] ? 6'd21 : - (_theResult____h350507[34] ? + (_theResult____h350508[34] ? 6'd22 : - (_theResult____h350507[33] ? + (_theResult____h350508[33] ? 6'd23 : - (_theResult____h350507[32] ? + (_theResult____h350508[32] ? 6'd24 : - (_theResult____h350507[31] ? + (_theResult____h350508[31] ? 6'd25 : - (_theResult____h350507[30] ? + (_theResult____h350508[30] ? 6'd26 : - (_theResult____h350507[29] ? + (_theResult____h350508[29] ? 6'd27 : - (_theResult____h350507[28] ? + (_theResult____h350508[28] ? 6'd28 : - (_theResult____h350507[27] ? + (_theResult____h350508[27] ? 6'd29 : - (_theResult____h350507[26] ? + (_theResult____h350508[26] ? 6'd30 : - (_theResult____h350507[25] ? + (_theResult____h350508[25] ? 6'd31 : - (_theResult____h350507[24] ? + (_theResult____h350508[24] ? 6'd32 : - (_theResult____h350507[23] ? + (_theResult____h350508[23] ? 6'd33 : - (_theResult____h350507[22] ? + (_theResult____h350508[22] ? 6'd34 : - (_theResult____h350507[21] ? + (_theResult____h350508[21] ? 6'd35 : - (_theResult____h350507[20] ? + (_theResult____h350508[20] ? 6'd36 : - (_theResult____h350507[19] ? + (_theResult____h350508[19] ? 6'd37 : - (_theResult____h350507[18] ? + (_theResult____h350508[18] ? 6'd38 : - (_theResult____h350507[17] ? + (_theResult____h350508[17] ? 6'd39 : - (_theResult____h350507[16] ? + (_theResult____h350508[16] ? 6'd40 : - (_theResult____h350507[15] ? + (_theResult____h350508[15] ? 6'd41 : - (_theResult____h350507[14] ? + (_theResult____h350508[14] ? 6'd42 : - (_theResult____h350507[13] ? + (_theResult____h350508[13] ? 6'd43 : - (_theResult____h350507[12] ? + (_theResult____h350508[12] ? 6'd44 : - (_theResult____h350507[11] ? + (_theResult____h350508[11] ? 6'd45 : - (_theResult____h350507[10] ? + (_theResult____h350508[10] ? 6'd46 : - (_theResult____h350507[9] ? + (_theResult____h350508[9] ? 6'd47 : - (_theResult____h350507[8] ? + (_theResult____h350508[8] ? 6'd48 : - (_theResult____h350507[7] ? + (_theResult____h350508[7] ? 6'd49 : - (_theResult____h350507[6] ? + (_theResult____h350508[6] ? 6'd50 : - (_theResult____h350507[5] ? + (_theResult____h350508[5] ? 6'd51 : - (_theResult____h350507[4] ? + (_theResult____h350508[4] ? 6'd52 : - (_theResult____h350507[3] ? + (_theResult____h350508[3] ? 6'd53 : - (_theResult____h350507[2] ? + (_theResult____h350508[2] ? 6'd54 : - (_theResult____h350507[1] ? + (_theResult____h350508[1] ? 6'd55 : - (_theResult____h350507[0] ? + (_theResult____h350508[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 = - (_theResult____h396206[56] ? + (_theResult____h396207[56] ? 6'd0 : - (_theResult____h396206[55] ? + (_theResult____h396207[55] ? 6'd1 : - (_theResult____h396206[54] ? + (_theResult____h396207[54] ? 6'd2 : - (_theResult____h396206[53] ? + (_theResult____h396207[53] ? 6'd3 : - (_theResult____h396206[52] ? + (_theResult____h396207[52] ? 6'd4 : - (_theResult____h396206[51] ? + (_theResult____h396207[51] ? 6'd5 : - (_theResult____h396206[50] ? + (_theResult____h396207[50] ? 6'd6 : - (_theResult____h396206[49] ? + (_theResult____h396207[49] ? 6'd7 : - (_theResult____h396206[48] ? + (_theResult____h396207[48] ? 6'd8 : - (_theResult____h396206[47] ? + (_theResult____h396207[47] ? 6'd9 : - (_theResult____h396206[46] ? + (_theResult____h396207[46] ? 6'd10 : - (_theResult____h396206[45] ? + (_theResult____h396207[45] ? 6'd11 : - (_theResult____h396206[44] ? + (_theResult____h396207[44] ? 6'd12 : - (_theResult____h396206[43] ? + (_theResult____h396207[43] ? 6'd13 : - (_theResult____h396206[42] ? + (_theResult____h396207[42] ? 6'd14 : - (_theResult____h396206[41] ? + (_theResult____h396207[41] ? 6'd15 : - (_theResult____h396206[40] ? + (_theResult____h396207[40] ? 6'd16 : - (_theResult____h396206[39] ? + (_theResult____h396207[39] ? 6'd17 : - (_theResult____h396206[38] ? + (_theResult____h396207[38] ? 6'd18 : - (_theResult____h396206[37] ? + (_theResult____h396207[37] ? 6'd19 : - (_theResult____h396206[36] ? + (_theResult____h396207[36] ? 6'd20 : - (_theResult____h396206[35] ? + (_theResult____h396207[35] ? 6'd21 : - (_theResult____h396206[34] ? + (_theResult____h396207[34] ? 6'd22 : - (_theResult____h396206[33] ? + (_theResult____h396207[33] ? 6'd23 : - (_theResult____h396206[32] ? + (_theResult____h396207[32] ? 6'd24 : - (_theResult____h396206[31] ? + (_theResult____h396207[31] ? 6'd25 : - (_theResult____h396206[30] ? + (_theResult____h396207[30] ? 6'd26 : - (_theResult____h396206[29] ? + (_theResult____h396207[29] ? 6'd27 : - (_theResult____h396206[28] ? + (_theResult____h396207[28] ? 6'd28 : - (_theResult____h396206[27] ? + (_theResult____h396207[27] ? 6'd29 : - (_theResult____h396206[26] ? + (_theResult____h396207[26] ? 6'd30 : - (_theResult____h396206[25] ? + (_theResult____h396207[25] ? 6'd31 : - (_theResult____h396206[24] ? + (_theResult____h396207[24] ? 6'd32 : - (_theResult____h396206[23] ? + (_theResult____h396207[23] ? 6'd33 : - (_theResult____h396206[22] ? + (_theResult____h396207[22] ? 6'd34 : - (_theResult____h396206[21] ? + (_theResult____h396207[21] ? 6'd35 : - (_theResult____h396206[20] ? + (_theResult____h396207[20] ? 6'd36 : - (_theResult____h396206[19] ? + (_theResult____h396207[19] ? 6'd37 : - (_theResult____h396206[18] ? + (_theResult____h396207[18] ? 6'd38 : - (_theResult____h396206[17] ? + (_theResult____h396207[17] ? 6'd39 : - (_theResult____h396206[16] ? + (_theResult____h396207[16] ? 6'd40 : - (_theResult____h396206[15] ? + (_theResult____h396207[15] ? 6'd41 : - (_theResult____h396206[14] ? + (_theResult____h396207[14] ? 6'd42 : - (_theResult____h396206[13] ? + (_theResult____h396207[13] ? 6'd43 : - (_theResult____h396206[12] ? + (_theResult____h396207[12] ? 6'd44 : - (_theResult____h396206[11] ? + (_theResult____h396207[11] ? 6'd45 : - (_theResult____h396206[10] ? + (_theResult____h396207[10] ? 6'd46 : - (_theResult____h396206[9] ? + (_theResult____h396207[9] ? 6'd47 : - (_theResult____h396206[8] ? + (_theResult____h396207[8] ? 6'd48 : - (_theResult____h396206[7] ? + (_theResult____h396207[7] ? 6'd49 : - (_theResult____h396206[6] ? + (_theResult____h396207[6] ? 6'd50 : - (_theResult____h396206[5] ? + (_theResult____h396207[5] ? 6'd51 : - (_theResult____h396206[4] ? + (_theResult____h396207[4] ? 6'd52 : - (_theResult____h396206[3] ? + (_theResult____h396207[3] ? 6'd53 : - (_theResult____h396206[2] ? + (_theResult____h396207[2] ? 6'd54 : - (_theResult____h396206[1] ? + (_theResult____h396207[1] ? 6'd55 : - (_theResult____h396206[0] ? + (_theResult____h396207[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 = - (_theResult____h441901[56] ? + (_theResult____h441902[56] ? 6'd0 : - (_theResult____h441901[55] ? + (_theResult____h441902[55] ? 6'd1 : - (_theResult____h441901[54] ? + (_theResult____h441902[54] ? 6'd2 : - (_theResult____h441901[53] ? + (_theResult____h441902[53] ? 6'd3 : - (_theResult____h441901[52] ? + (_theResult____h441902[52] ? 6'd4 : - (_theResult____h441901[51] ? + (_theResult____h441902[51] ? 6'd5 : - (_theResult____h441901[50] ? + (_theResult____h441902[50] ? 6'd6 : - (_theResult____h441901[49] ? + (_theResult____h441902[49] ? 6'd7 : - (_theResult____h441901[48] ? + (_theResult____h441902[48] ? 6'd8 : - (_theResult____h441901[47] ? + (_theResult____h441902[47] ? 6'd9 : - (_theResult____h441901[46] ? + (_theResult____h441902[46] ? 6'd10 : - (_theResult____h441901[45] ? + (_theResult____h441902[45] ? 6'd11 : - (_theResult____h441901[44] ? + (_theResult____h441902[44] ? 6'd12 : - (_theResult____h441901[43] ? + (_theResult____h441902[43] ? 6'd13 : - (_theResult____h441901[42] ? + (_theResult____h441902[42] ? 6'd14 : - (_theResult____h441901[41] ? + (_theResult____h441902[41] ? 6'd15 : - (_theResult____h441901[40] ? + (_theResult____h441902[40] ? 6'd16 : - (_theResult____h441901[39] ? + (_theResult____h441902[39] ? 6'd17 : - (_theResult____h441901[38] ? + (_theResult____h441902[38] ? 6'd18 : - (_theResult____h441901[37] ? + (_theResult____h441902[37] ? 6'd19 : - (_theResult____h441901[36] ? + (_theResult____h441902[36] ? 6'd20 : - (_theResult____h441901[35] ? + (_theResult____h441902[35] ? 6'd21 : - (_theResult____h441901[34] ? + (_theResult____h441902[34] ? 6'd22 : - (_theResult____h441901[33] ? + (_theResult____h441902[33] ? 6'd23 : - (_theResult____h441901[32] ? + (_theResult____h441902[32] ? 6'd24 : - (_theResult____h441901[31] ? + (_theResult____h441902[31] ? 6'd25 : - (_theResult____h441901[30] ? + (_theResult____h441902[30] ? 6'd26 : - (_theResult____h441901[29] ? + (_theResult____h441902[29] ? 6'd27 : - (_theResult____h441901[28] ? + (_theResult____h441902[28] ? 6'd28 : - (_theResult____h441901[27] ? + (_theResult____h441902[27] ? 6'd29 : - (_theResult____h441901[26] ? + (_theResult____h441902[26] ? 6'd30 : - (_theResult____h441901[25] ? + (_theResult____h441902[25] ? 6'd31 : - (_theResult____h441901[24] ? + (_theResult____h441902[24] ? 6'd32 : - (_theResult____h441901[23] ? + (_theResult____h441902[23] ? 6'd33 : - (_theResult____h441901[22] ? + (_theResult____h441902[22] ? 6'd34 : - (_theResult____h441901[21] ? + (_theResult____h441902[21] ? 6'd35 : - (_theResult____h441901[20] ? + (_theResult____h441902[20] ? 6'd36 : - (_theResult____h441901[19] ? + (_theResult____h441902[19] ? 6'd37 : - (_theResult____h441901[18] ? + (_theResult____h441902[18] ? 6'd38 : - (_theResult____h441901[17] ? + (_theResult____h441902[17] ? 6'd39 : - (_theResult____h441901[16] ? + (_theResult____h441902[16] ? 6'd40 : - (_theResult____h441901[15] ? + (_theResult____h441902[15] ? 6'd41 : - (_theResult____h441901[14] ? + (_theResult____h441902[14] ? 6'd42 : - (_theResult____h441901[13] ? + (_theResult____h441902[13] ? 6'd43 : - (_theResult____h441901[12] ? + (_theResult____h441902[12] ? 6'd44 : - (_theResult____h441901[11] ? + (_theResult____h441902[11] ? 6'd45 : - (_theResult____h441901[10] ? + (_theResult____h441902[10] ? 6'd46 : - (_theResult____h441901[9] ? + (_theResult____h441902[9] ? 6'd47 : - (_theResult____h441901[8] ? + (_theResult____h441902[8] ? 6'd48 : - (_theResult____h441901[7] ? + (_theResult____h441902[7] ? 6'd49 : - (_theResult____h441901[6] ? + (_theResult____h441902[6] ? 6'd50 : - (_theResult____h441901[5] ? + (_theResult____h441902[5] ? 6'd51 : - (_theResult____h441901[4] ? + (_theResult____h441902[4] ? 6'd52 : - (_theResult____h441901[3] ? + (_theResult____h441902[3] ? 6'd53 : - (_theResult____h441901[2] ? + (_theResult____h441902[2] ? 6'd54 : - (_theResult____h441901[1] ? + (_theResult____h441902[1] ? 6'd55 : - (_theResult____h441901[0] ? + (_theResult____h441902[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 = - (_theResult____h546652[56] ? + (_theResult____h546653[56] ? 6'd0 : - (_theResult____h546652[55] ? + (_theResult____h546653[55] ? 6'd1 : - (_theResult____h546652[54] ? + (_theResult____h546653[54] ? 6'd2 : - (_theResult____h546652[53] ? + (_theResult____h546653[53] ? 6'd3 : - (_theResult____h546652[52] ? + (_theResult____h546653[52] ? 6'd4 : - (_theResult____h546652[51] ? + (_theResult____h546653[51] ? 6'd5 : - (_theResult____h546652[50] ? + (_theResult____h546653[50] ? 6'd6 : - (_theResult____h546652[49] ? + (_theResult____h546653[49] ? 6'd7 : - (_theResult____h546652[48] ? + (_theResult____h546653[48] ? 6'd8 : - (_theResult____h546652[47] ? + (_theResult____h546653[47] ? 6'd9 : - (_theResult____h546652[46] ? + (_theResult____h546653[46] ? 6'd10 : - (_theResult____h546652[45] ? + (_theResult____h546653[45] ? 6'd11 : - (_theResult____h546652[44] ? + (_theResult____h546653[44] ? 6'd12 : - (_theResult____h546652[43] ? + (_theResult____h546653[43] ? 6'd13 : - (_theResult____h546652[42] ? + (_theResult____h546653[42] ? 6'd14 : - (_theResult____h546652[41] ? + (_theResult____h546653[41] ? 6'd15 : - (_theResult____h546652[40] ? + (_theResult____h546653[40] ? 6'd16 : - (_theResult____h546652[39] ? + (_theResult____h546653[39] ? 6'd17 : - (_theResult____h546652[38] ? + (_theResult____h546653[38] ? 6'd18 : - (_theResult____h546652[37] ? + (_theResult____h546653[37] ? 6'd19 : - (_theResult____h546652[36] ? + (_theResult____h546653[36] ? 6'd20 : - (_theResult____h546652[35] ? + (_theResult____h546653[35] ? 6'd21 : - (_theResult____h546652[34] ? + (_theResult____h546653[34] ? 6'd22 : - (_theResult____h546652[33] ? + (_theResult____h546653[33] ? 6'd23 : - (_theResult____h546652[32] ? + (_theResult____h546653[32] ? 6'd24 : - (_theResult____h546652[31] ? + (_theResult____h546653[31] ? 6'd25 : - (_theResult____h546652[30] ? + (_theResult____h546653[30] ? 6'd26 : - (_theResult____h546652[29] ? + (_theResult____h546653[29] ? 6'd27 : - (_theResult____h546652[28] ? + (_theResult____h546653[28] ? 6'd28 : - (_theResult____h546652[27] ? + (_theResult____h546653[27] ? 6'd29 : - (_theResult____h546652[26] ? + (_theResult____h546653[26] ? 6'd30 : - (_theResult____h546652[25] ? + (_theResult____h546653[25] ? 6'd31 : - (_theResult____h546652[24] ? + (_theResult____h546653[24] ? 6'd32 : - (_theResult____h546652[23] ? + (_theResult____h546653[23] ? 6'd33 : - (_theResult____h546652[22] ? + (_theResult____h546653[22] ? 6'd34 : - (_theResult____h546652[21] ? + (_theResult____h546653[21] ? 6'd35 : - (_theResult____h546652[20] ? + (_theResult____h546653[20] ? 6'd36 : - (_theResult____h546652[19] ? + (_theResult____h546653[19] ? 6'd37 : - (_theResult____h546652[18] ? + (_theResult____h546653[18] ? 6'd38 : - (_theResult____h546652[17] ? + (_theResult____h546653[17] ? 6'd39 : - (_theResult____h546652[16] ? + (_theResult____h546653[16] ? 6'd40 : - (_theResult____h546652[15] ? + (_theResult____h546653[15] ? 6'd41 : - (_theResult____h546652[14] ? + (_theResult____h546653[14] ? 6'd42 : - (_theResult____h546652[13] ? + (_theResult____h546653[13] ? 6'd43 : - (_theResult____h546652[12] ? + (_theResult____h546653[12] ? 6'd44 : - (_theResult____h546652[11] ? + (_theResult____h546653[11] ? 6'd45 : - (_theResult____h546652[10] ? + (_theResult____h546653[10] ? 6'd46 : - (_theResult____h546652[9] ? + (_theResult____h546653[9] ? 6'd47 : - (_theResult____h546652[8] ? + (_theResult____h546653[8] ? 6'd48 : - (_theResult____h546652[7] ? + (_theResult____h546653[7] ? 6'd49 : - (_theResult____h546652[6] ? + (_theResult____h546653[6] ? 6'd50 : - (_theResult____h546652[5] ? + (_theResult____h546653[5] ? 6'd51 : - (_theResult____h546652[4] ? + (_theResult____h546653[4] ? 6'd52 : - (_theResult____h546652[3] ? + (_theResult____h546653[3] ? 6'd53 : - (_theResult____h546652[2] ? + (_theResult____h546653[2] ? 6'd54 : - (_theResult____h546652[1] ? + (_theResult____h546653[1] ? 6'd55 : - (_theResult____h546652[0] ? + (_theResult____h546653[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 = - (_theResult____h507799[56] ? + (_theResult____h507800[56] ? 6'd0 : - (_theResult____h507799[55] ? + (_theResult____h507800[55] ? 6'd1 : - (_theResult____h507799[54] ? + (_theResult____h507800[54] ? 6'd2 : - (_theResult____h507799[53] ? + (_theResult____h507800[53] ? 6'd3 : - (_theResult____h507799[52] ? + (_theResult____h507800[52] ? 6'd4 : - (_theResult____h507799[51] ? + (_theResult____h507800[51] ? 6'd5 : - (_theResult____h507799[50] ? + (_theResult____h507800[50] ? 6'd6 : - (_theResult____h507799[49] ? + (_theResult____h507800[49] ? 6'd7 : - (_theResult____h507799[48] ? + (_theResult____h507800[48] ? 6'd8 : - (_theResult____h507799[47] ? + (_theResult____h507800[47] ? 6'd9 : - (_theResult____h507799[46] ? + (_theResult____h507800[46] ? 6'd10 : - (_theResult____h507799[45] ? + (_theResult____h507800[45] ? 6'd11 : - (_theResult____h507799[44] ? + (_theResult____h507800[44] ? 6'd12 : - (_theResult____h507799[43] ? + (_theResult____h507800[43] ? 6'd13 : - (_theResult____h507799[42] ? + (_theResult____h507800[42] ? 6'd14 : - (_theResult____h507799[41] ? + (_theResult____h507800[41] ? 6'd15 : - (_theResult____h507799[40] ? + (_theResult____h507800[40] ? 6'd16 : - (_theResult____h507799[39] ? + (_theResult____h507800[39] ? 6'd17 : - (_theResult____h507799[38] ? + (_theResult____h507800[38] ? 6'd18 : - (_theResult____h507799[37] ? + (_theResult____h507800[37] ? 6'd19 : - (_theResult____h507799[36] ? + (_theResult____h507800[36] ? 6'd20 : - (_theResult____h507799[35] ? + (_theResult____h507800[35] ? 6'd21 : - (_theResult____h507799[34] ? + (_theResult____h507800[34] ? 6'd22 : - (_theResult____h507799[33] ? + (_theResult____h507800[33] ? 6'd23 : - (_theResult____h507799[32] ? + (_theResult____h507800[32] ? 6'd24 : - (_theResult____h507799[31] ? + (_theResult____h507800[31] ? 6'd25 : - (_theResult____h507799[30] ? + (_theResult____h507800[30] ? 6'd26 : - (_theResult____h507799[29] ? + (_theResult____h507800[29] ? 6'd27 : - (_theResult____h507799[28] ? + (_theResult____h507800[28] ? 6'd28 : - (_theResult____h507799[27] ? + (_theResult____h507800[27] ? 6'd29 : - (_theResult____h507799[26] ? + (_theResult____h507800[26] ? 6'd30 : - (_theResult____h507799[25] ? + (_theResult____h507800[25] ? 6'd31 : - (_theResult____h507799[24] ? + (_theResult____h507800[24] ? 6'd32 : - (_theResult____h507799[23] ? + (_theResult____h507800[23] ? 6'd33 : - (_theResult____h507799[22] ? + (_theResult____h507800[22] ? 6'd34 : - (_theResult____h507799[21] ? + (_theResult____h507800[21] ? 6'd35 : - (_theResult____h507799[20] ? + (_theResult____h507800[20] ? 6'd36 : - (_theResult____h507799[19] ? + (_theResult____h507800[19] ? 6'd37 : - (_theResult____h507799[18] ? + (_theResult____h507800[18] ? 6'd38 : - (_theResult____h507799[17] ? + (_theResult____h507800[17] ? 6'd39 : - (_theResult____h507799[16] ? + (_theResult____h507800[16] ? 6'd40 : - (_theResult____h507799[15] ? + (_theResult____h507800[15] ? 6'd41 : - (_theResult____h507799[14] ? + (_theResult____h507800[14] ? 6'd42 : - (_theResult____h507799[13] ? + (_theResult____h507800[13] ? 6'd43 : - (_theResult____h507799[12] ? + (_theResult____h507800[12] ? 6'd44 : - (_theResult____h507799[11] ? + (_theResult____h507800[11] ? 6'd45 : - (_theResult____h507799[10] ? + (_theResult____h507800[10] ? 6'd46 : - (_theResult____h507799[9] ? + (_theResult____h507800[9] ? 6'd47 : - (_theResult____h507799[8] ? + (_theResult____h507800[8] ? 6'd48 : - (_theResult____h507799[7] ? + (_theResult____h507800[7] ? 6'd49 : - (_theResult____h507799[6] ? + (_theResult____h507800[6] ? 6'd50 : - (_theResult____h507799[5] ? + (_theResult____h507800[5] ? 6'd51 : - (_theResult____h507799[4] ? + (_theResult____h507800[4] ? 6'd52 : - (_theResult____h507799[3] ? + (_theResult____h507800[3] ? 6'd53 : - (_theResult____h507799[2] ? + (_theResult____h507800[2] ? 6'd54 : - (_theResult____h507799[1] ? + (_theResult____h507800[1] ? 6'd55 : - (_theResult____h507799[0] ? + (_theResult____h507800[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9725 = - (_theResult____h585956[56] ? + (_theResult____h585957[56] ? 6'd0 : - (_theResult____h585956[55] ? + (_theResult____h585957[55] ? 6'd1 : - (_theResult____h585956[54] ? + (_theResult____h585957[54] ? 6'd2 : - (_theResult____h585956[53] ? + (_theResult____h585957[53] ? 6'd3 : - (_theResult____h585956[52] ? + (_theResult____h585957[52] ? 6'd4 : - (_theResult____h585956[51] ? + (_theResult____h585957[51] ? 6'd5 : - (_theResult____h585956[50] ? + (_theResult____h585957[50] ? 6'd6 : - (_theResult____h585956[49] ? + (_theResult____h585957[49] ? 6'd7 : - (_theResult____h585956[48] ? + (_theResult____h585957[48] ? 6'd8 : - (_theResult____h585956[47] ? + (_theResult____h585957[47] ? 6'd9 : - (_theResult____h585956[46] ? + (_theResult____h585957[46] ? 6'd10 : - (_theResult____h585956[45] ? + (_theResult____h585957[45] ? 6'd11 : - (_theResult____h585956[44] ? + (_theResult____h585957[44] ? 6'd12 : - (_theResult____h585956[43] ? + (_theResult____h585957[43] ? 6'd13 : - (_theResult____h585956[42] ? + (_theResult____h585957[42] ? 6'd14 : - (_theResult____h585956[41] ? + (_theResult____h585957[41] ? 6'd15 : - (_theResult____h585956[40] ? + (_theResult____h585957[40] ? 6'd16 : - (_theResult____h585956[39] ? + (_theResult____h585957[39] ? 6'd17 : - (_theResult____h585956[38] ? + (_theResult____h585957[38] ? 6'd18 : - (_theResult____h585956[37] ? + (_theResult____h585957[37] ? 6'd19 : - (_theResult____h585956[36] ? + (_theResult____h585957[36] ? 6'd20 : - (_theResult____h585956[35] ? + (_theResult____h585957[35] ? 6'd21 : - (_theResult____h585956[34] ? + (_theResult____h585957[34] ? 6'd22 : - (_theResult____h585956[33] ? + (_theResult____h585957[33] ? 6'd23 : - (_theResult____h585956[32] ? + (_theResult____h585957[32] ? 6'd24 : - (_theResult____h585956[31] ? + (_theResult____h585957[31] ? 6'd25 : - (_theResult____h585956[30] ? + (_theResult____h585957[30] ? 6'd26 : - (_theResult____h585956[29] ? + (_theResult____h585957[29] ? 6'd27 : - (_theResult____h585956[28] ? + (_theResult____h585957[28] ? 6'd28 : - (_theResult____h585956[27] ? + (_theResult____h585957[27] ? 6'd29 : - (_theResult____h585956[26] ? + (_theResult____h585957[26] ? 6'd30 : - (_theResult____h585956[25] ? + (_theResult____h585957[25] ? 6'd31 : - (_theResult____h585956[24] ? + (_theResult____h585957[24] ? 6'd32 : - (_theResult____h585956[23] ? + (_theResult____h585957[23] ? 6'd33 : - (_theResult____h585956[22] ? + (_theResult____h585957[22] ? 6'd34 : - (_theResult____h585956[21] ? + (_theResult____h585957[21] ? 6'd35 : - (_theResult____h585956[20] ? + (_theResult____h585957[20] ? 6'd36 : - (_theResult____h585956[19] ? + (_theResult____h585957[19] ? 6'd37 : - (_theResult____h585956[18] ? + (_theResult____h585957[18] ? 6'd38 : - (_theResult____h585956[17] ? + (_theResult____h585957[17] ? 6'd39 : - (_theResult____h585956[16] ? + (_theResult____h585957[16] ? 6'd40 : - (_theResult____h585956[15] ? + (_theResult____h585957[15] ? 6'd41 : - (_theResult____h585956[14] ? + (_theResult____h585957[14] ? 6'd42 : - (_theResult____h585956[13] ? + (_theResult____h585957[13] ? 6'd43 : - (_theResult____h585956[12] ? + (_theResult____h585957[12] ? 6'd44 : - (_theResult____h585956[11] ? + (_theResult____h585957[11] ? 6'd45 : - (_theResult____h585956[10] ? + (_theResult____h585957[10] ? 6'd46 : - (_theResult____h585956[9] ? + (_theResult____h585957[9] ? 6'd47 : - (_theResult____h585956[8] ? + (_theResult____h585957[8] ? 6'd48 : - (_theResult____h585956[7] ? + (_theResult____h585957[7] ? 6'd49 : - (_theResult____h585956[6] ? + (_theResult____h585957[6] ? 6'd50 : - (_theResult____h585956[5] ? + (_theResult____h585957[5] ? 6'd51 : - (_theResult____h585956[4] ? + (_theResult____h585957[4] ? 6'd52 : - (_theResult____h585956[3] ? + (_theResult____h585957[3] ? 6'd53 : - (_theResult____h585956[2] ? + (_theResult____h585957[2] ? 6'd54 : - (_theResult____h585956[1] ? + (_theResult____h585957[1] ? 6'd55 : - (_theResult____h585956[0] ? + (_theResult____h585957[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4898 = - (_theResult____h368146[56] ? + (_theResult____h368147[56] ? 6'd0 : - (_theResult____h368146[55] ? + (_theResult____h368147[55] ? 6'd1 : - (_theResult____h368146[54] ? + (_theResult____h368147[54] ? 6'd2 : - (_theResult____h368146[53] ? + (_theResult____h368147[53] ? 6'd3 : - (_theResult____h368146[52] ? + (_theResult____h368147[52] ? 6'd4 : - (_theResult____h368146[51] ? + (_theResult____h368147[51] ? 6'd5 : - (_theResult____h368146[50] ? + (_theResult____h368147[50] ? 6'd6 : - (_theResult____h368146[49] ? + (_theResult____h368147[49] ? 6'd7 : - (_theResult____h368146[48] ? + (_theResult____h368147[48] ? 6'd8 : - (_theResult____h368146[47] ? + (_theResult____h368147[47] ? 6'd9 : - (_theResult____h368146[46] ? + (_theResult____h368147[46] ? 6'd10 : - (_theResult____h368146[45] ? + (_theResult____h368147[45] ? 6'd11 : - (_theResult____h368146[44] ? + (_theResult____h368147[44] ? 6'd12 : - (_theResult____h368146[43] ? + (_theResult____h368147[43] ? 6'd13 : - (_theResult____h368146[42] ? + (_theResult____h368147[42] ? 6'd14 : - (_theResult____h368146[41] ? + (_theResult____h368147[41] ? 6'd15 : - (_theResult____h368146[40] ? + (_theResult____h368147[40] ? 6'd16 : - (_theResult____h368146[39] ? + (_theResult____h368147[39] ? 6'd17 : - (_theResult____h368146[38] ? + (_theResult____h368147[38] ? 6'd18 : - (_theResult____h368146[37] ? + (_theResult____h368147[37] ? 6'd19 : - (_theResult____h368146[36] ? + (_theResult____h368147[36] ? 6'd20 : - (_theResult____h368146[35] ? + (_theResult____h368147[35] ? 6'd21 : - (_theResult____h368146[34] ? + (_theResult____h368147[34] ? 6'd22 : - (_theResult____h368146[33] ? + (_theResult____h368147[33] ? 6'd23 : - (_theResult____h368146[32] ? + (_theResult____h368147[32] ? 6'd24 : - (_theResult____h368146[31] ? + (_theResult____h368147[31] ? 6'd25 : - (_theResult____h368146[30] ? + (_theResult____h368147[30] ? 6'd26 : - (_theResult____h368146[29] ? + (_theResult____h368147[29] ? 6'd27 : - (_theResult____h368146[28] ? + (_theResult____h368147[28] ? 6'd28 : - (_theResult____h368146[27] ? + (_theResult____h368147[27] ? 6'd29 : - (_theResult____h368146[26] ? + (_theResult____h368147[26] ? 6'd30 : - (_theResult____h368146[25] ? + (_theResult____h368147[25] ? 6'd31 : - (_theResult____h368146[24] ? + (_theResult____h368147[24] ? 6'd32 : - (_theResult____h368146[23] ? + (_theResult____h368147[23] ? 6'd33 : - (_theResult____h368146[22] ? + (_theResult____h368147[22] ? 6'd34 : - (_theResult____h368146[21] ? + (_theResult____h368147[21] ? 6'd35 : - (_theResult____h368146[20] ? + (_theResult____h368147[20] ? 6'd36 : - (_theResult____h368146[19] ? + (_theResult____h368147[19] ? 6'd37 : - (_theResult____h368146[18] ? + (_theResult____h368147[18] ? 6'd38 : - (_theResult____h368146[17] ? + (_theResult____h368147[17] ? 6'd39 : - (_theResult____h368146[16] ? + (_theResult____h368147[16] ? 6'd40 : - (_theResult____h368146[15] ? + (_theResult____h368147[15] ? 6'd41 : - (_theResult____h368146[14] ? + (_theResult____h368147[14] ? 6'd42 : - (_theResult____h368146[13] ? + (_theResult____h368147[13] ? 6'd43 : - (_theResult____h368146[12] ? + (_theResult____h368147[12] ? 6'd44 : - (_theResult____h368146[11] ? + (_theResult____h368147[11] ? 6'd45 : - (_theResult____h368146[10] ? + (_theResult____h368147[10] ? 6'd46 : - (_theResult____h368146[9] ? + (_theResult____h368147[9] ? 6'd47 : - (_theResult____h368146[8] ? + (_theResult____h368147[8] ? 6'd48 : - (_theResult____h368146[7] ? + (_theResult____h368147[7] ? 6'd49 : - (_theResult____h368146[6] ? + (_theResult____h368147[6] ? 6'd50 : - (_theResult____h368146[5] ? + (_theResult____h368147[5] ? 6'd51 : - (_theResult____h368146[4] ? + (_theResult____h368147[4] ? 6'd52 : - (_theResult____h368146[3] ? + (_theResult____h368147[3] ? 6'd53 : - (_theResult____h368146[2] ? + (_theResult____h368147[2] ? 6'd54 : - (_theResult____h368146[1] ? + (_theResult____h368147[1] ? 6'd55 : - (_theResult____h368146[0] ? + (_theResult____h368147[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 = - (_theResult____h413843[56] ? + (_theResult____h413844[56] ? 6'd0 : - (_theResult____h413843[55] ? + (_theResult____h413844[55] ? 6'd1 : - (_theResult____h413843[54] ? + (_theResult____h413844[54] ? 6'd2 : - (_theResult____h413843[53] ? + (_theResult____h413844[53] ? 6'd3 : - (_theResult____h413843[52] ? + (_theResult____h413844[52] ? 6'd4 : - (_theResult____h413843[51] ? + (_theResult____h413844[51] ? 6'd5 : - (_theResult____h413843[50] ? + (_theResult____h413844[50] ? 6'd6 : - (_theResult____h413843[49] ? + (_theResult____h413844[49] ? 6'd7 : - (_theResult____h413843[48] ? + (_theResult____h413844[48] ? 6'd8 : - (_theResult____h413843[47] ? + (_theResult____h413844[47] ? 6'd9 : - (_theResult____h413843[46] ? + (_theResult____h413844[46] ? 6'd10 : - (_theResult____h413843[45] ? + (_theResult____h413844[45] ? 6'd11 : - (_theResult____h413843[44] ? + (_theResult____h413844[44] ? 6'd12 : - (_theResult____h413843[43] ? + (_theResult____h413844[43] ? 6'd13 : - (_theResult____h413843[42] ? + (_theResult____h413844[42] ? 6'd14 : - (_theResult____h413843[41] ? + (_theResult____h413844[41] ? 6'd15 : - (_theResult____h413843[40] ? + (_theResult____h413844[40] ? 6'd16 : - (_theResult____h413843[39] ? + (_theResult____h413844[39] ? 6'd17 : - (_theResult____h413843[38] ? + (_theResult____h413844[38] ? 6'd18 : - (_theResult____h413843[37] ? + (_theResult____h413844[37] ? 6'd19 : - (_theResult____h413843[36] ? + (_theResult____h413844[36] ? 6'd20 : - (_theResult____h413843[35] ? + (_theResult____h413844[35] ? 6'd21 : - (_theResult____h413843[34] ? + (_theResult____h413844[34] ? 6'd22 : - (_theResult____h413843[33] ? + (_theResult____h413844[33] ? 6'd23 : - (_theResult____h413843[32] ? + (_theResult____h413844[32] ? 6'd24 : - (_theResult____h413843[31] ? + (_theResult____h413844[31] ? 6'd25 : - (_theResult____h413843[30] ? + (_theResult____h413844[30] ? 6'd26 : - (_theResult____h413843[29] ? + (_theResult____h413844[29] ? 6'd27 : - (_theResult____h413843[28] ? + (_theResult____h413844[28] ? 6'd28 : - (_theResult____h413843[27] ? + (_theResult____h413844[27] ? 6'd29 : - (_theResult____h413843[26] ? + (_theResult____h413844[26] ? 6'd30 : - (_theResult____h413843[25] ? + (_theResult____h413844[25] ? 6'd31 : - (_theResult____h413843[24] ? + (_theResult____h413844[24] ? 6'd32 : - (_theResult____h413843[23] ? + (_theResult____h413844[23] ? 6'd33 : - (_theResult____h413843[22] ? + (_theResult____h413844[22] ? 6'd34 : - (_theResult____h413843[21] ? + (_theResult____h413844[21] ? 6'd35 : - (_theResult____h413843[20] ? + (_theResult____h413844[20] ? 6'd36 : - (_theResult____h413843[19] ? + (_theResult____h413844[19] ? 6'd37 : - (_theResult____h413843[18] ? + (_theResult____h413844[18] ? 6'd38 : - (_theResult____h413843[17] ? + (_theResult____h413844[17] ? 6'd39 : - (_theResult____h413843[16] ? + (_theResult____h413844[16] ? 6'd40 : - (_theResult____h413843[15] ? + (_theResult____h413844[15] ? 6'd41 : - (_theResult____h413843[14] ? + (_theResult____h413844[14] ? 6'd42 : - (_theResult____h413843[13] ? + (_theResult____h413844[13] ? 6'd43 : - (_theResult____h413843[12] ? + (_theResult____h413844[12] ? 6'd44 : - (_theResult____h413843[11] ? + (_theResult____h413844[11] ? 6'd45 : - (_theResult____h413843[10] ? + (_theResult____h413844[10] ? 6'd46 : - (_theResult____h413843[9] ? + (_theResult____h413844[9] ? 6'd47 : - (_theResult____h413843[8] ? + (_theResult____h413844[8] ? 6'd48 : - (_theResult____h413843[7] ? + (_theResult____h413844[7] ? 6'd49 : - (_theResult____h413843[6] ? + (_theResult____h413844[6] ? 6'd50 : - (_theResult____h413843[5] ? + (_theResult____h413844[5] ? 6'd51 : - (_theResult____h413843[4] ? + (_theResult____h413844[4] ? 6'd52 : - (_theResult____h413843[3] ? + (_theResult____h413844[3] ? 6'd53 : - (_theResult____h413843[2] ? + (_theResult____h413844[2] ? 6'd54 : - (_theResult____h413843[1] ? + (_theResult____h413844[1] ? 6'd55 : - (_theResult____h413843[0] ? + (_theResult____h413844[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 = - (_theResult____h459538[56] ? + (_theResult____h459539[56] ? 6'd0 : - (_theResult____h459538[55] ? + (_theResult____h459539[55] ? 6'd1 : - (_theResult____h459538[54] ? + (_theResult____h459539[54] ? 6'd2 : - (_theResult____h459538[53] ? + (_theResult____h459539[53] ? 6'd3 : - (_theResult____h459538[52] ? + (_theResult____h459539[52] ? 6'd4 : - (_theResult____h459538[51] ? + (_theResult____h459539[51] ? 6'd5 : - (_theResult____h459538[50] ? + (_theResult____h459539[50] ? 6'd6 : - (_theResult____h459538[49] ? + (_theResult____h459539[49] ? 6'd7 : - (_theResult____h459538[48] ? + (_theResult____h459539[48] ? 6'd8 : - (_theResult____h459538[47] ? + (_theResult____h459539[47] ? 6'd9 : - (_theResult____h459538[46] ? + (_theResult____h459539[46] ? 6'd10 : - (_theResult____h459538[45] ? + (_theResult____h459539[45] ? 6'd11 : - (_theResult____h459538[44] ? + (_theResult____h459539[44] ? 6'd12 : - (_theResult____h459538[43] ? + (_theResult____h459539[43] ? 6'd13 : - (_theResult____h459538[42] ? + (_theResult____h459539[42] ? 6'd14 : - (_theResult____h459538[41] ? + (_theResult____h459539[41] ? 6'd15 : - (_theResult____h459538[40] ? + (_theResult____h459539[40] ? 6'd16 : - (_theResult____h459538[39] ? + (_theResult____h459539[39] ? 6'd17 : - (_theResult____h459538[38] ? + (_theResult____h459539[38] ? 6'd18 : - (_theResult____h459538[37] ? + (_theResult____h459539[37] ? 6'd19 : - (_theResult____h459538[36] ? + (_theResult____h459539[36] ? 6'd20 : - (_theResult____h459538[35] ? + (_theResult____h459539[35] ? 6'd21 : - (_theResult____h459538[34] ? + (_theResult____h459539[34] ? 6'd22 : - (_theResult____h459538[33] ? + (_theResult____h459539[33] ? 6'd23 : - (_theResult____h459538[32] ? + (_theResult____h459539[32] ? 6'd24 : - (_theResult____h459538[31] ? + (_theResult____h459539[31] ? 6'd25 : - (_theResult____h459538[30] ? + (_theResult____h459539[30] ? 6'd26 : - (_theResult____h459538[29] ? + (_theResult____h459539[29] ? 6'd27 : - (_theResult____h459538[28] ? + (_theResult____h459539[28] ? 6'd28 : - (_theResult____h459538[27] ? + (_theResult____h459539[27] ? 6'd29 : - (_theResult____h459538[26] ? + (_theResult____h459539[26] ? 6'd30 : - (_theResult____h459538[25] ? + (_theResult____h459539[25] ? 6'd31 : - (_theResult____h459538[24] ? + (_theResult____h459539[24] ? 6'd32 : - (_theResult____h459538[23] ? + (_theResult____h459539[23] ? 6'd33 : - (_theResult____h459538[22] ? + (_theResult____h459539[22] ? 6'd34 : - (_theResult____h459538[21] ? + (_theResult____h459539[21] ? 6'd35 : - (_theResult____h459538[20] ? + (_theResult____h459539[20] ? 6'd36 : - (_theResult____h459538[19] ? + (_theResult____h459539[19] ? 6'd37 : - (_theResult____h459538[18] ? + (_theResult____h459539[18] ? 6'd38 : - (_theResult____h459538[17] ? + (_theResult____h459539[17] ? 6'd39 : - (_theResult____h459538[16] ? + (_theResult____h459539[16] ? 6'd40 : - (_theResult____h459538[15] ? + (_theResult____h459539[15] ? 6'd41 : - (_theResult____h459538[14] ? + (_theResult____h459539[14] ? 6'd42 : - (_theResult____h459538[13] ? + (_theResult____h459539[13] ? 6'd43 : - (_theResult____h459538[12] ? + (_theResult____h459539[12] ? 6'd44 : - (_theResult____h459538[11] ? + (_theResult____h459539[11] ? 6'd45 : - (_theResult____h459538[10] ? + (_theResult____h459539[10] ? 6'd46 : - (_theResult____h459538[9] ? + (_theResult____h459539[9] ? 6'd47 : - (_theResult____h459538[8] ? + (_theResult____h459539[8] ? 6'd48 : - (_theResult____h459538[7] ? + (_theResult____h459539[7] ? 6'd49 : - (_theResult____h459538[6] ? + (_theResult____h459539[6] ? 6'd50 : - (_theResult____h459538[5] ? + (_theResult____h459539[5] ? 6'd51 : - (_theResult____h459538[4] ? + (_theResult____h459539[4] ? 6'd52 : - (_theResult____h459538[3] ? + (_theResult____h459539[3] ? 6'd53 : - (_theResult____h459538[2] ? + (_theResult____h459539[2] ? 6'd54 : - (_theResult____h459538[1] ? + (_theResult____h459539[1] ? 6'd55 : - (_theResult____h459538[0] ? + (_theResult____h459539[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10037 = - (_theResult___fst_exp__h594192 == 11'd2047) ? + (_theResult___fst_exp__h594193 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21085,10 +21085,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85966_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard85967_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10539 = - (_theResult___fst_exp__h554888 == 11'd2047) ? + (_theResult___fst_exp__h554889 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21096,10 +21096,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_guard46663_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10806 = - (_theResult___fst_exp__h554888 == 11'd2047) ? + (_theResult___fst_exp__h554889 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21107,10 +21107,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46662_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard46663_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9054 = - (_theResult___fst_exp__h516035 == 11'd2047) ? + (_theResult___fst_exp__h516036 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21118,10 +21118,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07809_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_guard07810_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9769 = - (_theResult___fst_exp__h594192 == 11'd2047) ? + (_theResult___fst_exp__h594193 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21129,538 +21129,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85966_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard85967_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410 = - (guard__h350517 == 2'b0 || + (guard__h350518 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h358618 : - _theResult___exp__h359134 ; + _theResult___fst_exp__h358619 : + _theResult___exp__h359135 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4413 = - (guard__h350517 == 2'b0) ? - _theResult___fst_exp__h358618 : + (guard__h350518 == 2'b0) ? + _theResult___fst_exp__h358619 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h359134 : - _theResult___fst_exp__h358618) ; + _theResult___exp__h359135 : + _theResult___fst_exp__h358619) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057 = - (guard__h350517 == 2'b0 || + (guard__h350518 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h358612[56:34] : - _theResult___sfd__h359135 ; + sfdin__h358613[56:34] : + _theResult___sfd__h359136 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059 = - (guard__h350517 == 2'b0) ? - sfdin__h358612[56:34] : + (guard__h350518 == 2'b0) ? + sfdin__h358613[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h359135 : - sfdin__h358612[56:34]) ; + _theResult___sfd__h359136 : + sfdin__h358613[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802 = - (guard__h396216 == 2'b0 || + (guard__h396217 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h404315 : - _theResult___exp__h404831 ; + _theResult___fst_exp__h404316 : + _theResult___exp__h404832 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5805 = - (guard__h396216 == 2'b0) ? - _theResult___fst_exp__h404315 : + (guard__h396217 == 2'b0) ? + _theResult___fst_exp__h404316 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h404831 : - _theResult___fst_exp__h404315) ; + _theResult___exp__h404832 : + _theResult___fst_exp__h404316) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449 = - (guard__h396216 == 2'b0 || + (guard__h396217 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h404309[56:34] : - _theResult___sfd__h404832 ; + sfdin__h404310[56:34] : + _theResult___sfd__h404833 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6451 = - (guard__h396216 == 2'b0) ? - sfdin__h404309[56:34] : + (guard__h396217 == 2'b0) ? + sfdin__h404310[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h404832 : - sfdin__h404309[56:34]) ; + _theResult___sfd__h404833 : + sfdin__h404310[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194 = - (guard__h441911 == 2'b0 || + (guard__h441912 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h450010 : - _theResult___exp__h450526 ; + _theResult___fst_exp__h450011 : + _theResult___exp__h450527 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7197 = - (guard__h441911 == 2'b0) ? - _theResult___fst_exp__h450010 : + (guard__h441912 == 2'b0) ? + _theResult___fst_exp__h450011 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h450526 : - _theResult___fst_exp__h450010) ; + _theResult___exp__h450527 : + _theResult___fst_exp__h450011) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841 = - (guard__h441911 == 2'b0 || + (guard__h441912 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h450004[56:34] : - _theResult___sfd__h450527 ; + sfdin__h450005[56:34] : + _theResult___sfd__h450528 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843 = - (guard__h441911 == 2'b0) ? - sfdin__h450004[56:34] : + (guard__h441912 == 2'b0) ? + sfdin__h450005[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h450527 : - sfdin__h450004[56:34]) ; + _theResult___sfd__h450528 : + sfdin__h450005[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651 = - (guard__h546662 == 2'b0 || + (guard__h546663 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h554888 : - _theResult___exp__h555617 ; + _theResult___fst_exp__h554889 : + _theResult___exp__h555618 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653 = - (guard__h546662 == 2'b0) ? - _theResult___fst_exp__h554888 : + (guard__h546663 == 2'b0) ? + _theResult___fst_exp__h554889 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h555617 : - _theResult___fst_exp__h554888) ; + _theResult___exp__h555618 : + _theResult___fst_exp__h554889) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734 = - (guard__h546662 == 2'b0 || + (guard__h546663 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h554882[56:5] : - _theResult___sfd__h555618 ; + sfdin__h554883[56:5] : + _theResult___sfd__h555619 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736 = - (guard__h546662 == 2'b0) ? - sfdin__h554882[56:5] : + (guard__h546663 == 2'b0) ? + sfdin__h554883[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h555618 : - sfdin__h554882[56:5]) ; + _theResult___sfd__h555619 : + sfdin__h554883[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171 = - (guard__h507809 == 2'b0 || + (guard__h507810 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h516035 : - _theResult___exp__h516764 ; + _theResult___fst_exp__h516036 : + _theResult___exp__h516765 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9173 = - (guard__h507809 == 2'b0) ? - _theResult___fst_exp__h516035 : + (guard__h507810 == 2'b0) ? + _theResult___fst_exp__h516036 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h516764 : - _theResult___fst_exp__h516035) ; + _theResult___exp__h516765 : + _theResult___fst_exp__h516036) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255 = - (guard__h507809 == 2'b0 || + (guard__h507810 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h516029[56:5] : - _theResult___sfd__h516765 ; + sfdin__h516030[56:5] : + _theResult___sfd__h516766 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9257 = - (guard__h507809 == 2'b0) ? - sfdin__h516029[56:5] : + (guard__h507810 == 2'b0) ? + sfdin__h516030[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h516765 : - sfdin__h516029[56:5]) ; + _theResult___sfd__h516766 : + sfdin__h516030[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 = - (guard__h585966 == 2'b0 || + (guard__h585967 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h594192 : - _theResult___exp__h594921 ; + _theResult___fst_exp__h594193 : + _theResult___exp__h594922 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 = - (guard__h585966 == 2'b0) ? - _theResult___fst_exp__h594192 : + (guard__h585967 == 2'b0) ? + _theResult___fst_exp__h594193 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h594921 : - _theResult___fst_exp__h594192) ; + _theResult___exp__h594922 : + _theResult___fst_exp__h594193) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9964 = - (guard__h585966 == 2'b0 || + (guard__h585967 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h594186[56:5] : - _theResult___sfd__h594922 ; + sfdin__h594187[56:5] : + _theResult___sfd__h594923 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9966 = - (guard__h585966 == 2'b0) ? - sfdin__h594186[56:5] : + (guard__h585967 == 2'b0) ? + sfdin__h594187[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h594922 : - sfdin__h594186[56:5]) ; + _theResult___sfd__h594923 : + sfdin__h594187[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4957 = - (guard__h368156 == 2'b0 || + (guard__h368157 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h376384 : - _theResult___exp__h376900 ; + _theResult___fst_exp__h376385 : + _theResult___exp__h376901 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4959 = - (guard__h368156 == 2'b0) ? - _theResult___fst_exp__h376384 : + (guard__h368157 == 2'b0) ? + _theResult___fst_exp__h376385 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h376900 : - _theResult___fst_exp__h376384) ; + _theResult___exp__h376901 : + _theResult___fst_exp__h376385) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5103 = - (guard__h368156 == 2'b0 || + (guard__h368157 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h376378[56:34] : - _theResult___sfd__h376901 ; + sfdin__h376379[56:34] : + _theResult___sfd__h376902 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5105 = - (guard__h368156 == 2'b0) ? - sfdin__h376378[56:34] : + (guard__h368157 == 2'b0) ? + sfdin__h376379[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h376901 : - sfdin__h376378[56:34]) ; + _theResult___sfd__h376902 : + sfdin__h376379[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6349 = - (guard__h413853 == 2'b0 || + (guard__h413854 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h422081 : - _theResult___exp__h422597 ; + _theResult___fst_exp__h422082 : + _theResult___exp__h422598 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6351 = - (guard__h413853 == 2'b0) ? - _theResult___fst_exp__h422081 : + (guard__h413854 == 2'b0) ? + _theResult___fst_exp__h422082 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h422597 : - _theResult___fst_exp__h422081) ; + _theResult___exp__h422598 : + _theResult___fst_exp__h422082) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6495 = - (guard__h413853 == 2'b0 || + (guard__h413854 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h422075[56:34] : - _theResult___sfd__h422598 ; + sfdin__h422076[56:34] : + _theResult___sfd__h422599 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6497 = - (guard__h413853 == 2'b0) ? - sfdin__h422075[56:34] : + (guard__h413854 == 2'b0) ? + sfdin__h422076[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h422598 : - sfdin__h422075[56:34]) ; + _theResult___sfd__h422599 : + sfdin__h422076[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7741 = - (guard__h459548 == 2'b0 || + (guard__h459549 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h467776 : - _theResult___exp__h468292 ; + _theResult___fst_exp__h467777 : + _theResult___exp__h468293 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7743 = - (guard__h459548 == 2'b0) ? - _theResult___fst_exp__h467776 : + (guard__h459549 == 2'b0) ? + _theResult___fst_exp__h467777 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h468292 : - _theResult___fst_exp__h467776) ; + _theResult___exp__h468293 : + _theResult___fst_exp__h467777) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7887 = - (guard__h459548 == 2'b0 || + (guard__h459549 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h467770[56:34] : - _theResult___sfd__h468293 ; + sfdin__h467771[56:34] : + _theResult___sfd__h468294 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7889 = - (guard__h459548 == 2'b0) ? - sfdin__h467770[56:34] : + (guard__h459549 == 2'b0) ? + sfdin__h467771[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h468293 : - sfdin__h467770[56:34]) ; + _theResult___sfd__h468294 : + sfdin__h467771[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10613 = - (guard__h537350 == 2'b0 || + (guard__h537351 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h545311 : - _theResult___exp__h545966 ; + _theResult___fst_exp__h545312 : + _theResult___exp__h545967 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10615 = - (guard__h537350 == 2'b0) ? - _theResult___fst_exp__h545311 : + (guard__h537351 == 2'b0) ? + _theResult___fst_exp__h545312 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h545966 : - _theResult___fst_exp__h545311) ; + _theResult___exp__h545967 : + _theResult___fst_exp__h545312) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682 = - (guard__h555731 == 2'b0 || + (guard__h555732 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h563721 : - _theResult___exp__h564401 ; + _theResult___fst_exp__h563722 : + _theResult___exp__h564402 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684 = - (guard__h555731 == 2'b0) ? - _theResult___fst_exp__h563721 : + (guard__h555732 == 2'b0) ? + _theResult___fst_exp__h563722 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h564401 : - _theResult___fst_exp__h563721) ; + _theResult___exp__h564402 : + _theResult___fst_exp__h563722) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708 = - (guard__h537350 == 2'b0 || + (guard__h537351 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h545262[56:5] : - _theResult___sfd__h545967 ; + _theResult___snd__h545263[56:5] : + _theResult___sfd__h545968 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10710 = - (guard__h537350 == 2'b0) ? - _theResult___snd__h545262[56:5] : + (guard__h537351 == 2'b0) ? + _theResult___snd__h545263[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h545967 : - _theResult___snd__h545262[56:5]) ; + _theResult___sfd__h545968 : + _theResult___snd__h545263[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10753 = - (guard__h555731 == 2'b0 || + (guard__h555732 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h563667[56:5] : - _theResult___sfd__h564402 ; + _theResult___snd__h563668[56:5] : + _theResult___sfd__h564403 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10755 = - (guard__h555731 == 2'b0) ? - _theResult___snd__h563667[56:5] : + (guard__h555732 == 2'b0) ? + _theResult___snd__h563668[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h564402 : - _theResult___snd__h563667[56:5]) ; + _theResult___sfd__h564403 : + _theResult___snd__h563668[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9128 = - (guard__h498497 == 2'b0 || + (guard__h498498 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h506458 : - _theResult___exp__h507113 ; + _theResult___fst_exp__h506459 : + _theResult___exp__h507114 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9130 = - (guard__h498497 == 2'b0) ? - _theResult___fst_exp__h506458 : + (guard__h498498 == 2'b0) ? + _theResult___fst_exp__h506459 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h507113 : - _theResult___fst_exp__h506458) ; + _theResult___exp__h507114 : + _theResult___fst_exp__h506459) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9202 = - (guard__h516878 == 2'b0 || + (guard__h516879 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h524868 : - _theResult___exp__h525548 ; + _theResult___fst_exp__h524869 : + _theResult___exp__h525549 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9204 = - (guard__h516878 == 2'b0) ? - _theResult___fst_exp__h524868 : + (guard__h516879 == 2'b0) ? + _theResult___fst_exp__h524869 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h525548 : - _theResult___fst_exp__h524868) ; + _theResult___exp__h525549 : + _theResult___fst_exp__h524869) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9228 = - (guard__h498497 == 2'b0 || + (guard__h498498 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h506409[56:5] : - _theResult___sfd__h507114 ; + _theResult___snd__h506410[56:5] : + _theResult___sfd__h507115 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9230 = - (guard__h498497 == 2'b0) ? - _theResult___snd__h506409[56:5] : + (guard__h498498 == 2'b0) ? + _theResult___snd__h506410[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h507114 : - _theResult___snd__h506409[56:5]) ; + _theResult___sfd__h507115 : + _theResult___snd__h506410[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9274 = - (guard__h516878 == 2'b0 || + (guard__h516879 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h524814[56:5] : - _theResult___sfd__h525549 ; + _theResult___snd__h524815[56:5] : + _theResult___sfd__h525550 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9276 = - (guard__h516878 == 2'b0) ? - _theResult___snd__h524814[56:5] : + (guard__h516879 == 2'b0) ? + _theResult___snd__h524815[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h525549 : - _theResult___snd__h524814[56:5]) ; + _theResult___sfd__h525550 : + _theResult___snd__h524815[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9843 = - (guard__h576654 == 2'b0 || + (guard__h576655 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h584615 : - _theResult___exp__h585270 ; + _theResult___fst_exp__h584616 : + _theResult___exp__h585271 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9845 = - (guard__h576654 == 2'b0) ? - _theResult___fst_exp__h584615 : + (guard__h576655 == 2'b0) ? + _theResult___fst_exp__h584616 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h585270 : - _theResult___fst_exp__h584615) ; + _theResult___exp__h585271 : + _theResult___fst_exp__h584616) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912 = - (guard__h595035 == 2'b0 || + (guard__h595036 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h603025 : - _theResult___exp__h603705 ; + _theResult___fst_exp__h603026 : + _theResult___exp__h603706 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914 = - (guard__h595035 == 2'b0) ? - _theResult___fst_exp__h603025 : + (guard__h595036 == 2'b0) ? + _theResult___fst_exp__h603026 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h603705 : - _theResult___fst_exp__h603025) ; + _theResult___exp__h603706 : + _theResult___fst_exp__h603026) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9938 = - (guard__h576654 == 2'b0 || + (guard__h576655 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h584566[56:5] : - _theResult___sfd__h585271 ; + _theResult___snd__h584567[56:5] : + _theResult___sfd__h585272 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9940 = - (guard__h576654 == 2'b0) ? - _theResult___snd__h584566[56:5] : + (guard__h576655 == 2'b0) ? + _theResult___snd__h584567[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h585271 : - _theResult___snd__h584566[56:5]) ; + _theResult___sfd__h585272 : + _theResult___snd__h584567[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9983 = - (guard__h595035 == 2'b0 || + (guard__h595036 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h602971[56:5] : - _theResult___sfd__h603706 ; + _theResult___snd__h602972[56:5] : + _theResult___sfd__h603707 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9985 = - (guard__h595035 == 2'b0) ? - _theResult___snd__h602971[56:5] : + (guard__h595036 == 2'b0) ? + _theResult___snd__h602972[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h603706 : - _theResult___snd__h602971[56:5]) ; + _theResult___sfd__h603707 : + _theResult___snd__h602972[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4632 = - (guard__h359226 == 2'b0 || + (guard__h359227 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h367274 : - _theResult___exp__h367716 ; + _theResult___fst_exp__h367275 : + _theResult___exp__h367717 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4634 = - (guard__h359226 == 2'b0) ? - _theResult___fst_exp__h367274 : + (guard__h359227 == 2'b0) ? + _theResult___fst_exp__h367275 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h367716 : - _theResult___fst_exp__h367274) ; + _theResult___exp__h367717 : + _theResult___fst_exp__h367275) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5026 = - (guard__h376992 == 2'b0 || + (guard__h376993 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h385069 : - _theResult___exp__h385536 ; + _theResult___fst_exp__h385070 : + _theResult___exp__h385537 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5028 = - (guard__h376992 == 2'b0) ? - _theResult___fst_exp__h385069 : + (guard__h376993 == 2'b0) ? + _theResult___fst_exp__h385070 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h385536 : - _theResult___fst_exp__h385069) ; + _theResult___exp__h385537 : + _theResult___fst_exp__h385070) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5076 = - (guard__h359226 == 2'b0 || + (guard__h359227 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h367225[56:34] : - _theResult___sfd__h367717 ; + _theResult___snd__h367226[56:34] : + _theResult___sfd__h367718 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5078 = - (guard__h359226 == 2'b0) ? - _theResult___snd__h367225[56:34] : + (guard__h359227 == 2'b0) ? + _theResult___snd__h367226[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h367717 : - _theResult___snd__h367225[56:34]) ; + _theResult___sfd__h367718 : + _theResult___snd__h367226[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122 = - (guard__h376992 == 2'b0 || + (guard__h376993 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h385015[56:34] : - _theResult___sfd__h385537 ; + _theResult___snd__h385016[56:34] : + _theResult___sfd__h385538 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124 = - (guard__h376992 == 2'b0) ? - _theResult___snd__h385015[56:34] : + (guard__h376993 == 2'b0) ? + _theResult___snd__h385016[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h385537 : - _theResult___snd__h385015[56:34]) ; + _theResult___sfd__h385538 : + _theResult___snd__h385016[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6024 = - (guard__h404923 == 2'b0 || + (guard__h404924 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h412971 : - _theResult___exp__h413413 ; + _theResult___fst_exp__h412972 : + _theResult___exp__h413414 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6026 = - (guard__h404923 == 2'b0) ? - _theResult___fst_exp__h412971 : + (guard__h404924 == 2'b0) ? + _theResult___fst_exp__h412972 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h413413 : - _theResult___fst_exp__h412971) ; + _theResult___exp__h413414 : + _theResult___fst_exp__h412972) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6418 = - (guard__h422689 == 2'b0 || + (guard__h422690 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h430766 : - _theResult___exp__h431233 ; + _theResult___fst_exp__h430767 : + _theResult___exp__h431234 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6420 = - (guard__h422689 == 2'b0) ? - _theResult___fst_exp__h430766 : + (guard__h422690 == 2'b0) ? + _theResult___fst_exp__h430767 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h431233 : - _theResult___fst_exp__h430766) ; + _theResult___exp__h431234 : + _theResult___fst_exp__h430767) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6468 = - (guard__h404923 == 2'b0 || + (guard__h404924 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h412922[56:34] : - _theResult___sfd__h413414 ; + _theResult___snd__h412923[56:34] : + _theResult___sfd__h413415 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6470 = - (guard__h404923 == 2'b0) ? - _theResult___snd__h412922[56:34] : + (guard__h404924 == 2'b0) ? + _theResult___snd__h412923[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h413414 : - _theResult___snd__h412922[56:34]) ; + _theResult___sfd__h413415 : + _theResult___snd__h412923[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514 = - (guard__h422689 == 2'b0 || + (guard__h422690 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h430712[56:34] : - _theResult___sfd__h431234 ; + _theResult___snd__h430713[56:34] : + _theResult___sfd__h431235 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516 = - (guard__h422689 == 2'b0) ? - _theResult___snd__h430712[56:34] : + (guard__h422690 == 2'b0) ? + _theResult___snd__h430713[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h431234 : - _theResult___snd__h430712[56:34]) ; + _theResult___sfd__h431235 : + _theResult___snd__h430713[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7416 = - (guard__h450618 == 2'b0 || + (guard__h450619 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h458666 : - _theResult___exp__h459108 ; + _theResult___fst_exp__h458667 : + _theResult___exp__h459109 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7418 = - (guard__h450618 == 2'b0) ? - _theResult___fst_exp__h458666 : + (guard__h450619 == 2'b0) ? + _theResult___fst_exp__h458667 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h459108 : - _theResult___fst_exp__h458666) ; + _theResult___exp__h459109 : + _theResult___fst_exp__h458667) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7810 = - (guard__h468384 == 2'b0 || + (guard__h468385 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h476461 : - _theResult___exp__h476928 ; + _theResult___fst_exp__h476462 : + _theResult___exp__h476929 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7812 = - (guard__h468384 == 2'b0) ? - _theResult___fst_exp__h476461 : + (guard__h468385 == 2'b0) ? + _theResult___fst_exp__h476462 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h476928 : - _theResult___fst_exp__h476461) ; + _theResult___exp__h476929 : + _theResult___fst_exp__h476462) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 = - (guard__h450618 == 2'b0 || + (guard__h450619 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h458617[56:34] : - _theResult___sfd__h459109 ; + _theResult___snd__h458618[56:34] : + _theResult___sfd__h459110 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 = - (guard__h450618 == 2'b0) ? - _theResult___snd__h458617[56:34] : + (guard__h450619 == 2'b0) ? + _theResult___snd__h458618[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h459109 : - _theResult___snd__h458617[56:34]) ; + _theResult___sfd__h459110 : + _theResult___snd__h458618[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906 = - (guard__h468384 == 2'b0 || + (guard__h468385 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h476407[56:34] : - _theResult___sfd__h476929 ; + _theResult___snd__h476408[56:34] : + _theResult___sfd__h476930 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908 = - (guard__h468384 == 2'b0) ? - _theResult___snd__h476407[56:34] : + (guard__h468385 == 2'b0) ? + _theResult___snd__h476408[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h476929 : - _theResult___snd__h476407[56:34]) ; + _theResult___sfd__h476930 : + _theResult___snd__h476408[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10022 = - (_theResult___fst_exp__h584615 == 11'd2047) ? + (_theResult___fst_exp__h584616 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21668,10 +21668,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76654_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10049 = - (_theResult___fst_exp__h603025 == 11'd2047) ? + (_theResult___fst_exp__h603026 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21679,10 +21679,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10585 = - (_theResult___fst_exp__h563721 == 11'd2047) ? + (_theResult___fst_exp__h563722 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21690,10 +21690,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_guard55732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10791 = - (_theResult___fst_exp__h545311 == 11'd2047) ? + (_theResult___fst_exp__h545312 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21701,10 +21701,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37350_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard37351_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10818 = - (_theResult___fst_exp__h563721 == 11'd2047) ? + (_theResult___fst_exp__h563722 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21712,10 +21712,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard55732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9100 = - (_theResult___fst_exp__h524868 == 11'd2047) ? + (_theResult___fst_exp__h524869 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21723,10 +21723,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_guard16879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9815 = - (_theResult___fst_exp__h603025 == 11'd2047) ? + (_theResult___fst_exp__h603026 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21734,14 +21734,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_guard95036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059 = - (_theResult____h658376 == 16'd0 && + (_theResult____h658377 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h658947 : - _theResult____h658376 ; + enabled_ints__h658948 : + _theResult____h658377 ; assign IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13287 = IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] || IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[1] || @@ -21803,7 +21803,7 @@ module mkCore(CLK, checkForException___d13943[4] || csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d14036 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10052 = - (f3_exp__h565368 == 8'd0) ? + (f3_exp__h565369 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21813,85 +21813,85 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10024) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10051 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10053 = - (f3_exp__h565368 == 8'd255 && f3_sfd__h565369 != 23'd0 || - (f3_exp__h565368 == 8'd255 || f3_exp__h565368 == 8'd0) && - f3_sfd__h565369 == 23'd0) ? + (f3_exp__h565369 == 8'd255 && f3_sfd__h565370 != 23'd0 || + (f3_exp__h565369 == 8'd255 || f3_exp__h565369 == 8'd0) && + f3_sfd__h565370 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10052 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 = - ((f2_exp__h526064 == 8'd0) ? - (f2_sfd__h526065[22] ? + ((f2_exp__h526065 == 8'd0) ? + (f2_sfd__h526066[22] ? 6'd2 : - (f2_sfd__h526065[21] ? + (f2_sfd__h526066[21] ? 6'd3 : - (f2_sfd__h526065[20] ? + (f2_sfd__h526066[20] ? 6'd4 : - (f2_sfd__h526065[19] ? + (f2_sfd__h526066[19] ? 6'd5 : - (f2_sfd__h526065[18] ? + (f2_sfd__h526066[18] ? 6'd6 : - (f2_sfd__h526065[17] ? + (f2_sfd__h526066[17] ? 6'd7 : - (f2_sfd__h526065[16] ? + (f2_sfd__h526066[16] ? 6'd8 : - (f2_sfd__h526065[15] ? + (f2_sfd__h526066[15] ? 6'd9 : - (f2_sfd__h526065[14] ? + (f2_sfd__h526066[14] ? 6'd10 : - (f2_sfd__h526065[13] ? + (f2_sfd__h526066[13] ? 6'd11 : - (f2_sfd__h526065[12] ? + (f2_sfd__h526066[12] ? 6'd12 : - (f2_sfd__h526065[11] ? + (f2_sfd__h526066[11] ? 6'd13 : - (f2_sfd__h526065[10] ? + (f2_sfd__h526066[10] ? 6'd14 : - (f2_sfd__h526065[9] ? + (f2_sfd__h526066[9] ? 6'd15 : - (f2_sfd__h526065[8] ? + (f2_sfd__h526066[8] ? 6'd16 : - (f2_sfd__h526065[7] ? + (f2_sfd__h526066[7] ? 6'd17 : - (f2_sfd__h526065[6] ? + (f2_sfd__h526066[6] ? 6'd18 : - (f2_sfd__h526065[5] ? + (f2_sfd__h526066[5] ? 6'd19 : - (f2_sfd__h526065[4] ? + (f2_sfd__h526066[4] ? 6'd20 : - (f2_sfd__h526065[3] ? + (f2_sfd__h526066[3] ? 6'd21 : - (f2_sfd__h526065[2] ? + (f2_sfd__h526066[2] ? 6'd22 : - (f2_sfd__h526065[1] ? + (f2_sfd__h526066[1] ? 6'd23 : - (f2_sfd__h526065[0] ? + (f2_sfd__h526066[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10589 = - (f2_exp__h526064 == 8'd255 && f2_sfd__h526065 != 23'd0 || - (f2_exp__h526064 == 8'd255 || f2_exp__h526064 == 8'd0) && - f2_sfd__h526065 == 23'd0) ? + (f2_exp__h526065 == 8'd255 && f2_sfd__h526066 != 23'd0 || + (f2_exp__h526065 == 8'd255 || f2_exp__h526065 == 8'd0) && + f2_sfd__h526066 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h526064 == 8'd0) ? + ((f2_exp__h526065 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10244 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10587) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10766 = - (f2_exp__h526064 == 8'd255 && f2_sfd__h526065 != 23'd0) ? - _theResult___snd_fst_sfd__h526380 : - _theResult___fst_sfd__h564520 ; + (f2_exp__h526065 == 8'd255 && f2_sfd__h526066 != 23'd0) ? + _theResult___snd_fst_sfd__h526381 : + _theResult___fst_sfd__h564521 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10767 = - { (f2_exp__h526064 == 8'd255) ? + { (f2_exp__h526065 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h564516, + _theResult___fst_exp__h564517, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10766 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10821 = - (f2_exp__h526064 == 8'd0) ? + (f2_exp__h526065 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21901,15 +21901,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10793) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10820 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10822 = - (f2_exp__h526064 == 8'd255 && f2_sfd__h526065 != 23'd0 || - (f2_exp__h526064 == 8'd255 || f2_exp__h526064 == 8'd0) && - f2_sfd__h526065 == 23'd0) ? + (f2_exp__h526065 == 8'd255 && f2_sfd__h526066 != 23'd0 || + (f2_exp__h526065 == 8'd255 || f2_exp__h526065 == 8'd0) && + f2_sfd__h526066 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10821 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10877 = - (f1_exp__h487070 == 8'd0) ? + (f1_exp__h487071 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[4] : @@ -21917,7 +21917,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10918 = - (f2_exp__h526064 == 8'd0) ? + (f2_exp__h526065 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[4] : @@ -21925,7 +21925,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10962 = - (f3_exp__h565368 == 8'd0) ? + (f3_exp__h565369 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[4] : @@ -21933,7 +21933,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10977 = - (f1_exp__h487070 == 8'd0) ? + (f1_exp__h487071 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[3] : @@ -21941,7 +21941,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 = - (f2_exp__h526064 == 8'd0) ? + (f2_exp__h526065 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[3] : @@ -21949,7 +21949,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10998 = - (f3_exp__h565368 == 8'd0) ? + (f3_exp__h565369 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[3] : @@ -21957,208 +21957,208 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11017 = - (f1_exp__h487070 == 8'd0) ? + (f1_exp__h487071 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11015 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11031 = - (f2_exp__h526064 == 8'd0) ? + (f2_exp__h526065 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11029 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11046 = - (f3_exp__h565368 == 8'd0) ? + (f3_exp__h565369 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11044 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11063 = - (f1_exp__h487070 == 8'd0) ? + (f1_exp__h487071 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11061 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11075 = - (f2_exp__h526064 == 8'd0) ? + (f2_exp__h526065 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11073 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11088 = - (f3_exp__h565368 == 8'd0) ? + (f3_exp__h565369 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11086 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11105 = - (f1_exp__h487070 == 8'd0) ? + (f1_exp__h487071 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11103 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11117 = - (f2_exp__h526064 == 8'd0) ? + (f2_exp__h526065 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11115 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11130 = - (f3_exp__h565368 == 8'd0) ? + (f3_exp__h565369 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11128 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 = - ((f1_exp__h487070 == 8'd0) ? - (f1_sfd__h487071[22] ? + ((f1_exp__h487071 == 8'd0) ? + (f1_sfd__h487072[22] ? 6'd2 : - (f1_sfd__h487071[21] ? + (f1_sfd__h487072[21] ? 6'd3 : - (f1_sfd__h487071[20] ? + (f1_sfd__h487072[20] ? 6'd4 : - (f1_sfd__h487071[19] ? + (f1_sfd__h487072[19] ? 6'd5 : - (f1_sfd__h487071[18] ? + (f1_sfd__h487072[18] ? 6'd6 : - (f1_sfd__h487071[17] ? + (f1_sfd__h487072[17] ? 6'd7 : - (f1_sfd__h487071[16] ? + (f1_sfd__h487072[16] ? 6'd8 : - (f1_sfd__h487071[15] ? + (f1_sfd__h487072[15] ? 6'd9 : - (f1_sfd__h487071[14] ? + (f1_sfd__h487072[14] ? 6'd10 : - (f1_sfd__h487071[13] ? + (f1_sfd__h487072[13] ? 6'd11 : - (f1_sfd__h487071[12] ? + (f1_sfd__h487072[12] ? 6'd12 : - (f1_sfd__h487071[11] ? + (f1_sfd__h487072[11] ? 6'd13 : - (f1_sfd__h487071[10] ? + (f1_sfd__h487072[10] ? 6'd14 : - (f1_sfd__h487071[9] ? + (f1_sfd__h487072[9] ? 6'd15 : - (f1_sfd__h487071[8] ? + (f1_sfd__h487072[8] ? 6'd16 : - (f1_sfd__h487071[7] ? + (f1_sfd__h487072[7] ? 6'd17 : - (f1_sfd__h487071[6] ? + (f1_sfd__h487072[6] ? 6'd18 : - (f1_sfd__h487071[5] ? + (f1_sfd__h487072[5] ? 6'd19 : - (f1_sfd__h487071[4] ? + (f1_sfd__h487072[4] ? 6'd20 : - (f1_sfd__h487071[3] ? + (f1_sfd__h487072[3] ? 6'd21 : - (f1_sfd__h487071[2] ? + (f1_sfd__h487072[2] ? 6'd22 : - (f1_sfd__h487071[1] ? + (f1_sfd__h487072[1] ? 6'd23 : - (f1_sfd__h487071[0] ? + (f1_sfd__h487072[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9104 = - (f1_exp__h487070 == 8'd255 && f1_sfd__h487071 != 23'd0 || - (f1_exp__h487070 == 8'd255 || f1_exp__h487070 == 8'd0) && - f1_sfd__h487071 == 23'd0) ? + (f1_exp__h487071 == 8'd255 && f1_sfd__h487072 != 23'd0 || + (f1_exp__h487071 == 8'd255 || f1_exp__h487071 == 8'd0) && + f1_sfd__h487072 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h487070 == 8'd0) ? + ((f1_exp__h487071 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8759 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9102) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9287 = - (f1_exp__h487070 == 8'd255 && f1_sfd__h487071 != 23'd0) ? - _theResult___snd_fst_sfd__h487386 : - _theResult___fst_sfd__h525667 ; + (f1_exp__h487071 == 8'd255 && f1_sfd__h487072 != 23'd0) ? + _theResult___snd_fst_sfd__h487387 : + _theResult___fst_sfd__h525668 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9288 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9104, - (f1_exp__h487070 == 8'd255) ? + (f1_exp__h487071 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h525663, + _theResult___fst_exp__h525664, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9287 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 = - ((f3_exp__h565368 == 8'd0) ? - (f3_sfd__h565369[22] ? + ((f3_exp__h565369 == 8'd0) ? + (f3_sfd__h565370[22] ? 6'd2 : - (f3_sfd__h565369[21] ? + (f3_sfd__h565370[21] ? 6'd3 : - (f3_sfd__h565369[20] ? + (f3_sfd__h565370[20] ? 6'd4 : - (f3_sfd__h565369[19] ? + (f3_sfd__h565370[19] ? 6'd5 : - (f3_sfd__h565369[18] ? + (f3_sfd__h565370[18] ? 6'd6 : - (f3_sfd__h565369[17] ? + (f3_sfd__h565370[17] ? 6'd7 : - (f3_sfd__h565369[16] ? + (f3_sfd__h565370[16] ? 6'd8 : - (f3_sfd__h565369[15] ? + (f3_sfd__h565370[15] ? 6'd9 : - (f3_sfd__h565369[14] ? + (f3_sfd__h565370[14] ? 6'd10 : - (f3_sfd__h565369[13] ? + (f3_sfd__h565370[13] ? 6'd11 : - (f3_sfd__h565369[12] ? + (f3_sfd__h565370[12] ? 6'd12 : - (f3_sfd__h565369[11] ? + (f3_sfd__h565370[11] ? 6'd13 : - (f3_sfd__h565369[10] ? + (f3_sfd__h565370[10] ? 6'd14 : - (f3_sfd__h565369[9] ? + (f3_sfd__h565370[9] ? 6'd15 : - (f3_sfd__h565369[8] ? + (f3_sfd__h565370[8] ? 6'd16 : - (f3_sfd__h565369[7] ? + (f3_sfd__h565370[7] ? 6'd17 : - (f3_sfd__h565369[6] ? + (f3_sfd__h565370[6] ? 6'd18 : - (f3_sfd__h565369[5] ? + (f3_sfd__h565370[5] ? 6'd19 : - (f3_sfd__h565369[4] ? + (f3_sfd__h565370[4] ? 6'd20 : - (f3_sfd__h565369[3] ? + (f3_sfd__h565370[3] ? 6'd21 : - (f3_sfd__h565369[2] ? + (f3_sfd__h565370[2] ? 6'd22 : - (f3_sfd__h565369[1] ? + (f3_sfd__h565370[1] ? 6'd23 : - (f3_sfd__h565369[0] ? + (f3_sfd__h565370[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9819 = - (f3_exp__h565368 == 8'd255 && f3_sfd__h565369 != 23'd0 || - (f3_exp__h565368 == 8'd255 || f3_exp__h565368 == 8'd0) && - f3_sfd__h565369 == 23'd0) ? + (f3_exp__h565369 == 8'd255 && f3_sfd__h565370 != 23'd0 || + (f3_exp__h565369 == 8'd255 || f3_exp__h565369 == 8'd0) && + f3_sfd__h565370 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h565368 == 8'd0) ? + ((f3_exp__h565369 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9474 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9817) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9996 = - (f3_exp__h565368 == 8'd255 && f3_sfd__h565369 != 23'd0) ? - _theResult___snd_fst_sfd__h565684 : - _theResult___fst_sfd__h603824 ; + (f3_exp__h565369 == 8'd255 && f3_sfd__h565370 != 23'd0) ? + _theResult___snd_fst_sfd__h565685 : + _theResult___fst_sfd__h603825 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9997 = - { (f3_exp__h565368 == 8'd255) ? + { (f3_exp__h565369 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h603820, + _theResult___fst_exp__h603821, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9996 } ; assign IF_IF_coreFix_memExe_dTlb_procResp__742_BIT_18_ETC___d1879 = IF_coreFix_memExe_dTlb_procResp__742_BIT_182_7_ETC___d1868 ? @@ -22364,7 +22364,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10244 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 || - _theResult___fst_exp__h545311 == 11'd2047) ? + _theResult___fst_exp__h545312 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22372,12 +22372,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37350_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_guard37351_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8759 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 || - _theResult___fst_exp__h506458 == 11'd2047) ? + _theResult___fst_exp__h506459 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -22385,12 +22385,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98497_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_guard98498_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9474 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 || - _theResult___fst_exp__h584615 == 11'd2047) ? + _theResult___fst_exp__h584616 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22398,7 +22398,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76654_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_guard76655_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3__ETC___d13478 = IF_IF_NOT_csrf_prv_reg_read__3022_EQ_3_3023_30_ETC___d13059[0] ? @@ -22919,48 +22919,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11015 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[2] : - _theResult___fst_exp__h525651 == 11'd2047 && - _theResult___fst_sfd__h525652 == 52'd0 ; + _theResult___fst_exp__h525652 == 11'd2047 && + _theResult___fst_sfd__h525653 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11029 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[2] : - _theResult___fst_exp__h564504 == 11'd2047 && - _theResult___fst_sfd__h564505 == 52'd0 ; + _theResult___fst_exp__h564505 == 11'd2047 && + _theResult___fst_sfd__h564506 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11044 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[2] : - _theResult___fst_exp__h603808 == 11'd2047 && - _theResult___fst_sfd__h603809 == 52'd0 ; + _theResult___fst_exp__h603809 == 11'd2047 && + _theResult___fst_sfd__h603810 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11061 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[1] : - _theResult___fst_exp__h524868 == 11'd0 && - guard__h516878 != 2'b0 ; + _theResult___fst_exp__h524869 == 11'd0 && + guard__h516879 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11073 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[1] : - _theResult___fst_exp__h563721 == 11'd0 && - guard__h555731 != 2'b0 ; + _theResult___fst_exp__h563722 == 11'd0 && + guard__h555732 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11086 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[1] : - _theResult___fst_exp__h603025 == 11'd0 && - guard__h595035 != 2'b0 ; + _theResult___fst_exp__h603026 == 11'd0 && + guard__h595036 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11103 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873[0] : - _theResult___fst_exp__h524868 != 11'd2047 && - guard__h516878 != 2'b0 ; + _theResult___fst_exp__h524869 != 11'd2047 && + guard__h516879 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11115 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914[0] : - _theResult___fst_exp__h563721 != 11'd2047 && - guard__h555731 != 2'b0 ; + _theResult___fst_exp__h563722 != 11'd2047 && + guard__h555732 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11128 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958[0] : - _theResult___fst_exp__h603025 != 11'd2047 && - guard__h595035 != 2'b0 ; + _theResult___fst_exp__h603026 != 11'd2047 && + guard__h595036 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9061 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -23000,35 +23000,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5199 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - ((_theResult___fst_exp__h376384 == 8'd255) ? + ((_theResult___fst_exp__h376385 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184) : - ((_theResult___fst_exp__h385069 == 8'd255) ? + ((_theResult___fst_exp__h385070 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - ((_theResult___fst_exp__h376384 == 8'd255) ? + ((_theResult___fst_exp__h376385 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227) : - ((_theResult___fst_exp__h385069 == 8'd255) ? + ((_theResult___fst_exp__h385070 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5327 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298[2] : - _theResult___fst_exp__h385617 == 8'd255 && - _theResult___fst_sfd__h385618 == 23'd0 ; + _theResult___fst_exp__h385618 == 8'd255 && + _theResult___fst_sfd__h385619 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5340 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298[1] : - _theResult___fst_exp__h385069 == 8'd0 && - guard__h376992 != 2'b0 ; + _theResult___fst_exp__h385070 == 8'd0 && + guard__h376993 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5353 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298[0] : - _theResult___fst_exp__h385069 != 8'd255 && - guard__h376992 != 2'b0 ; + _theResult___fst_exp__h385070 != 8'd255 && + guard__h376993 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] == 8'd0) ? @@ -23038,35 +23038,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6591 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - ((_theResult___fst_exp__h422081 == 8'd255) ? + ((_theResult___fst_exp__h422082 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576) : - ((_theResult___fst_exp__h430766 == 8'd255) ? + ((_theResult___fst_exp__h430767 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - ((_theResult___fst_exp__h422081 == 8'd255) ? + ((_theResult___fst_exp__h422082 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619) : - ((_theResult___fst_exp__h430766 == 8'd255) ? + ((_theResult___fst_exp__h430767 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6719 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690[2] : - _theResult___fst_exp__h431314 == 8'd255 && - _theResult___fst_sfd__h431315 == 23'd0 ; + _theResult___fst_exp__h431315 == 8'd255 && + _theResult___fst_sfd__h431316 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6732 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690[1] : - _theResult___fst_exp__h430766 == 8'd0 && - guard__h422689 != 2'b0 ; + _theResult___fst_exp__h430767 == 8'd0 && + guard__h422690 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6745 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690[0] : - _theResult___fst_exp__h430766 != 8'd255 && - guard__h422689 != 2'b0 ; + _theResult___fst_exp__h430767 != 8'd255 && + guard__h422690 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] == 8'd0) ? @@ -23076,35 +23076,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7983 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - ((_theResult___fst_exp__h467776 == 8'd255) ? + ((_theResult___fst_exp__h467777 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968) : - ((_theResult___fst_exp__h476461 == 8'd255) ? + ((_theResult___fst_exp__h476462 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - ((_theResult___fst_exp__h467776 == 8'd255) ? + ((_theResult___fst_exp__h467777 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011) : - ((_theResult___fst_exp__h476461 == 8'd255) ? + ((_theResult___fst_exp__h476462 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8111 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082[2] : - _theResult___fst_exp__h477009 == 8'd255 && - _theResult___fst_sfd__h477010 == 23'd0 ; + _theResult___fst_exp__h477010 == 8'd255 && + _theResult___fst_sfd__h477011 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8124 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082[1] : - _theResult___fst_exp__h476461 == 8'd0 && - guard__h468384 != 2'b0 ; + _theResult___fst_exp__h476462 == 8'd0 && + guard__h468385 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8137 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082[0] : - _theResult___fst_exp__h476461 != 8'd255 && - guard__h468384 != 2'b0 ; + _theResult___fst_exp__h476462 != 8'd255 && + guard__h468385 != 2'b0 ; assign IF_checkForException_3243_BIT_4_3244_THEN_IF_c_ETC___d13394 = checkForException___d13243[4] ? CASE_checkForException_3243_BITS_3_TO_0_0_chec_ETC__q234 : @@ -23115,10 +23115,10 @@ module mkCore(CLK, 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h721432, - pc__h721332, - x__h723590, - x__h723782, + x_prv__h721433, + pc__h721333, + x__h723591, + x__h723783, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2388_ETC___d12421 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -23773,8 +23773,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9997 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12933 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h653953 : - w__h653948 ; + result__h653954 : + w__h653949 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2116 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23796,39 +23796,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2230, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2240 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2235, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h201996 : + n___1__h201997 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2553 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23881,7 +23881,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2599 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h200593 : + x__h200594 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2182 ? 64'd0 : 64'd1) ; @@ -23893,7 +23893,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3158 = - _theResult_____2__h300943 == v__h300363 ; + _theResult_____2__h300944 == v__h300364 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3238 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23902,7 +23902,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3260 = - _theResult_____2__h308939 == v__h303708 ; + _theResult_____2__h308940 == v__h303709 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3280 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23931,7 +23931,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h306573 } ; + x__h306574 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3104 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -24029,35 +24029,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2027 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2027, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2037 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2032, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h197392 : + n__h197393 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -24085,7 +24085,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3432 = - _theResult_____2__h314933 == v__h314222 ; + _theResult_____2__h314934 == v__h314223 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3505 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24094,7 +24094,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3528 = - _theResult_____2__h322787 == v__h318098 ; + _theResult_____2__h322788 == v__h318099 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3547 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24246,7 +24246,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3850 = - _theResult_____2__h336356 == v__h335924 ; + _theResult_____2__h336357 == v__h335925 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3843 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -24295,7 +24295,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) : IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3756 = - _theResult_____2__h333131 == v__h332699 ; + _theResult_____2__h333132 == v__h332700 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3749 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -24327,7 +24327,7 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h736047 : + upd__h735918 : csrf_minstret_ehr_data_rl ; assign IF_csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_c_ETC___d15232 = csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 ? @@ -24454,10 +24454,10 @@ module mkCore(CLK, mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d15994 = - rob$deqPort_0_canDeq ? y_avValue_fst__h739663 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_fst__h739534 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d16013 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h740138 : + y_avValue_snd_snd_snd_fst__h740009 : 2'd0 ; assign IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15505 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? @@ -24490,48 +24490,48 @@ module mkCore(CLK, rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__5648_BIT_25_564_ETC___d16004 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin04309_BIT_33_THEN_2_ELSE_0__q65 = - sfdin__h404309[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin16029_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h516029[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin22075_BIT_33_THEN_2_ELSE_0__q75 = - sfdin__h422075[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin50004_BIT_33_THEN_2_ELSE_0__q100 = - sfdin__h450004[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin54882_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h554882[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin58612_BIT_33_THEN_2_ELSE_0__q30 = - sfdin__h358612[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin67770_BIT_33_THEN_2_ELSE_0__q110 = - sfdin__h467770[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin76378_BIT_33_THEN_2_ELSE_0__q40 = - sfdin__h376378[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin94186_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h594186[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd02971_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h602971[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd06409_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h506409[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd12922_BIT_33_THEN_2_ELSE_0__q67 = - _theResult___snd__h412922[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd24814_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h524814[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd30712_BIT_33_THEN_2_ELSE_0__q80 = - _theResult___snd__h430712[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd45262_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h545262[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58617_BIT_33_THEN_2_ELSE_0__q102 = - _theResult___snd__h458617[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd63667_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h563667[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd67225_BIT_33_THEN_2_ELSE_0__q32 = - _theResult___snd__h367225[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd76407_BIT_33_THEN_2_ELSE_0__q115 = - _theResult___snd__h476407[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd84566_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h584566[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd85015_BIT_33_THEN_2_ELSE_0__q45 = - _theResult___snd__h385015[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin04310_BIT_33_THEN_2_ELSE_0__q65 = + sfdin__h404310[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin16030_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h516030[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin22076_BIT_33_THEN_2_ELSE_0__q75 = + sfdin__h422076[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin50005_BIT_33_THEN_2_ELSE_0__q100 = + sfdin__h450005[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin54883_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h554883[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin58613_BIT_33_THEN_2_ELSE_0__q30 = + sfdin__h358613[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin67771_BIT_33_THEN_2_ELSE_0__q110 = + sfdin__h467771[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin76379_BIT_33_THEN_2_ELSE_0__q40 = + sfdin__h376379[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin94187_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h594187[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd02972_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h602972[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd06410_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h506410[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd12923_BIT_33_THEN_2_ELSE_0__q67 = + _theResult___snd__h412923[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd24815_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h524815[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd30713_BIT_33_THEN_2_ELSE_0__q80 = + _theResult___snd__h430713[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd45263_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h545263[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58618_BIT_33_THEN_2_ELSE_0__q102 = + _theResult___snd__h458618[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd63668_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h563668[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd67226_BIT_33_THEN_2_ELSE_0__q32 = + _theResult___snd__h367226[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd76408_BIT_33_THEN_2_ELSE_0__q115 = + _theResult___snd__h476408[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd84567_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h584567[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd85016_BIT_33_THEN_2_ELSE_0__q45 = + _theResult___snd__h385016[33] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5321 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? @@ -24623,131 +24623,131 @@ module mkCore(CLK, !checkForException___d13943[4] && NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13968 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__5640_5641_OR__ETC___d16010 = - (fflags__h742984 & csrf_fflags_reg) != fflags__h742984 || + (fflags__h742855 & csrf_fflags_reg) != fflags__h742855 || csrf_fs_reg != 2'b11 && (IF_rob_deqPort_1_canDeq__5645_THEN_IF_NOT_rob__ETC___d16005 || - fflags__h742984 != 5'd0) ; + fflags__h742855 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171 = - !f2_sfd__h526065[21] && !f2_sfd__h526065[20] && - !f2_sfd__h526065[19] && - !f2_sfd__h526065[18] && - !f2_sfd__h526065[17] && - !f2_sfd__h526065[16] && - !f2_sfd__h526065[15] && - !f2_sfd__h526065[14] && - !f2_sfd__h526065[13] && - !f2_sfd__h526065[12] && - !f2_sfd__h526065[11] && - !f2_sfd__h526065[10] && - !f2_sfd__h526065[9] && - !f2_sfd__h526065[8] && - !f2_sfd__h526065[7] && - !f2_sfd__h526065[6] && - !f2_sfd__h526065[5] && - !f2_sfd__h526065[4] && - !f2_sfd__h526065[3] && - !f2_sfd__h526065[2] && - !f2_sfd__h526065[1] && - !f2_sfd__h526065[0] ; + !f2_sfd__h526066[21] && !f2_sfd__h526066[20] && + !f2_sfd__h526066[19] && + !f2_sfd__h526066[18] && + !f2_sfd__h526066[17] && + !f2_sfd__h526066[16] && + !f2_sfd__h526066[15] && + !f2_sfd__h526066[14] && + !f2_sfd__h526066[13] && + !f2_sfd__h526066[12] && + !f2_sfd__h526066[11] && + !f2_sfd__h526066[10] && + !f2_sfd__h526066[9] && + !f2_sfd__h526066[8] && + !f2_sfd__h526066[7] && + !f2_sfd__h526066[6] && + !f2_sfd__h526066[5] && + !f2_sfd__h526066[4] && + !f2_sfd__h526066[3] && + !f2_sfd__h526066[2] && + !f2_sfd__h526066[1] && + !f2_sfd__h526066[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10880 = - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 == 23'd0) && - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 != 23'd0) && - (f1_exp__h487070 != 8'd0 || f1_sfd__h487071 != 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 == 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 != 23'd0) && + (f1_exp__h487071 != 8'd0 || f1_sfd__h487072 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10877 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10922 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10880 | - ((f2_exp__h526064 != 8'd255 || f2_sfd__h526065 == 23'd0) && - (f2_exp__h526064 != 8'd255 || f2_sfd__h526065 != 23'd0) && - (f2_exp__h526064 != 8'd0 || f2_sfd__h526065 != 23'd0) && + ((f2_exp__h526065 != 8'd255 || f2_sfd__h526066 == 23'd0) && + (f2_exp__h526065 != 8'd255 || f2_sfd__h526066 != 23'd0) && + (f2_exp__h526065 != 8'd0 || f2_sfd__h526066 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10918) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10980 = - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 == 23'd0) && - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 != 23'd0) && - (f1_exp__h487070 != 8'd0 || f1_sfd__h487071 != 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 == 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 != 23'd0) && + (f1_exp__h487071 != 8'd0 || f1_sfd__h487072 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10977 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10991 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10980 | - ((f2_exp__h526064 != 8'd255 || f2_sfd__h526065 == 23'd0) && - (f2_exp__h526064 != 8'd255 || f2_sfd__h526065 != 23'd0) && - (f2_exp__h526064 != 8'd0 || f2_sfd__h526065 != 23'd0) && + ((f2_exp__h526065 != 8'd255 || f2_sfd__h526066 == 23'd0) && + (f2_exp__h526065 != 8'd255 || f2_sfd__h526066 != 23'd0) && + (f2_exp__h526065 != 8'd0 || f2_sfd__h526066 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11020 = - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 == 23'd0) && - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 != 23'd0) && - (f1_exp__h487070 != 8'd0 || f1_sfd__h487071 != 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 == 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 != 23'd0) && + (f1_exp__h487071 != 8'd0 || f1_sfd__h487072 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11017 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11035 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11020 | - ((f2_exp__h526064 != 8'd255 || f2_sfd__h526065 == 23'd0) && - (f2_exp__h526064 != 8'd255 || f2_sfd__h526065 != 23'd0) && - (f2_exp__h526064 != 8'd0 || f2_sfd__h526065 != 23'd0) && + ((f2_exp__h526065 != 8'd255 || f2_sfd__h526066 == 23'd0) && + (f2_exp__h526065 != 8'd255 || f2_sfd__h526066 != 23'd0) && + (f2_exp__h526065 != 8'd0 || f2_sfd__h526066 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11031) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11066 = - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 == 23'd0) && - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 != 23'd0) && - (f1_exp__h487070 != 8'd0 || f1_sfd__h487071 != 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 == 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 != 23'd0) && + (f1_exp__h487071 != 8'd0 || f1_sfd__h487072 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11063 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11079 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11066 | - ((f2_exp__h526064 != 8'd255 || f2_sfd__h526065 == 23'd0) && - (f2_exp__h526064 != 8'd255 || f2_sfd__h526065 != 23'd0) && - (f2_exp__h526064 != 8'd0 || f2_sfd__h526065 != 23'd0) && + ((f2_exp__h526065 != 8'd255 || f2_sfd__h526066 == 23'd0) && + (f2_exp__h526065 != 8'd255 || f2_sfd__h526066 != 23'd0) && + (f2_exp__h526065 != 8'd0 || f2_sfd__h526066 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11075) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11108 = - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 == 23'd0) && - (f1_exp__h487070 != 8'd255 || f1_sfd__h487071 != 23'd0) && - (f1_exp__h487070 != 8'd0 || f1_sfd__h487071 != 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 == 23'd0) && + (f1_exp__h487071 != 8'd255 || f1_sfd__h487072 != 23'd0) && + (f1_exp__h487071 != 8'd0 || f1_sfd__h487072 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11105 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11121 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11108 | - ((f2_exp__h526064 != 8'd255 || f2_sfd__h526065 == 23'd0) && - (f2_exp__h526064 != 8'd255 || f2_sfd__h526065 != 23'd0) && - (f2_exp__h526064 != 8'd0 || f2_sfd__h526065 != 23'd0) && + ((f2_exp__h526065 != 8'd255 || f2_sfd__h526066 == 23'd0) && + (f2_exp__h526065 != 8'd255 || f2_sfd__h526066 != 23'd0) && + (f2_exp__h526065 != 8'd0 || f2_sfd__h526066 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11117) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671 = - !f1_sfd__h487071[21] && !f1_sfd__h487071[20] && - !f1_sfd__h487071[19] && - !f1_sfd__h487071[18] && - !f1_sfd__h487071[17] && - !f1_sfd__h487071[16] && - !f1_sfd__h487071[15] && - !f1_sfd__h487071[14] && - !f1_sfd__h487071[13] && - !f1_sfd__h487071[12] && - !f1_sfd__h487071[11] && - !f1_sfd__h487071[10] && - !f1_sfd__h487071[9] && - !f1_sfd__h487071[8] && - !f1_sfd__h487071[7] && - !f1_sfd__h487071[6] && - !f1_sfd__h487071[5] && - !f1_sfd__h487071[4] && - !f1_sfd__h487071[3] && - !f1_sfd__h487071[2] && - !f1_sfd__h487071[1] && - !f1_sfd__h487071[0] ; + !f1_sfd__h487072[21] && !f1_sfd__h487072[20] && + !f1_sfd__h487072[19] && + !f1_sfd__h487072[18] && + !f1_sfd__h487072[17] && + !f1_sfd__h487072[16] && + !f1_sfd__h487072[15] && + !f1_sfd__h487072[14] && + !f1_sfd__h487072[13] && + !f1_sfd__h487072[12] && + !f1_sfd__h487072[11] && + !f1_sfd__h487072[10] && + !f1_sfd__h487072[9] && + !f1_sfd__h487072[8] && + !f1_sfd__h487072[7] && + !f1_sfd__h487072[6] && + !f1_sfd__h487072[5] && + !f1_sfd__h487072[4] && + !f1_sfd__h487072[3] && + !f1_sfd__h487072[2] && + !f1_sfd__h487072[1] && + !f1_sfd__h487072[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401 = - !f3_sfd__h565369[21] && !f3_sfd__h565369[20] && - !f3_sfd__h565369[19] && - !f3_sfd__h565369[18] && - !f3_sfd__h565369[17] && - !f3_sfd__h565369[16] && - !f3_sfd__h565369[15] && - !f3_sfd__h565369[14] && - !f3_sfd__h565369[13] && - !f3_sfd__h565369[12] && - !f3_sfd__h565369[11] && - !f3_sfd__h565369[10] && - !f3_sfd__h565369[9] && - !f3_sfd__h565369[8] && - !f3_sfd__h565369[7] && - !f3_sfd__h565369[6] && - !f3_sfd__h565369[5] && - !f3_sfd__h565369[4] && - !f3_sfd__h565369[3] && - !f3_sfd__h565369[2] && - !f3_sfd__h565369[1] && - !f3_sfd__h565369[0] ; + !f3_sfd__h565370[21] && !f3_sfd__h565370[20] && + !f3_sfd__h565370[19] && + !f3_sfd__h565370[18] && + !f3_sfd__h565370[17] && + !f3_sfd__h565370[16] && + !f3_sfd__h565370[15] && + !f3_sfd__h565370[14] && + !f3_sfd__h565370[13] && + !f3_sfd__h565370[12] && + !f3_sfd__h565370[11] && + !f3_sfd__h565370[10] && + !f3_sfd__h565370[9] && + !f3_sfd__h565370[8] && + !f3_sfd__h565370[7] && + !f3_sfd__h565370[6] && + !f3_sfd__h565370[5] && + !f3_sfd__h565370[4] && + !f3_sfd__h565370[3] && + !f3_sfd__h565370[2] && + !f3_sfd__h565370[1] && + !f3_sfd__h565370[0] ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13729 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13727 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -25357,7 +25357,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13566 && !csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 && - csr_addr__h662585 != 12'h8FF) ; + csr_addr__h662586 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1746_EQ_0_3232_3233_OR_N_ETC___d13666 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -25496,9 +25496,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13566 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h662586 == 5'd0 && - imm__h662587 == 32'd0 || - csr_addr__h662585[11:10] != 2'b11 ; + rs1__h662587 == 5'd0 && + imm__h662588 == 32'd0 || + csr_addr__h662586[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13711 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && @@ -25545,7 +25545,7 @@ module mkCore(CLK, specTagManager$currentSpecBits } ; assign NOT_fetchStage_pipelines_0_first__2992_BITS_32_ETC___d14366 = fetchStage$pipelines_0_first[323:260] != - fallthrough_pc__h673432 ; + fallthrough_pc__h673433 ; assign NOT_fetchStage_pipelines_0_first__2992_BIT_68__ETC___d13722 = !fetchStage$pipelines_0_first[68] && !checkForException___d13243[4] && @@ -25585,7 +25585,7 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3775_AND__ETC___d14480 ; assign NOT_fetchStage_pipelines_1_first__3001_BITS_32_ETC___d14535 = fetchStage$pipelines_1_first[323:260] != - fallthrough_pc__h689940 ; + fallthrough_pc__h689941 ; assign NOT_fetchStage_pipelines_1_first__3001_BIT_68__ETC___d14478 = !fetchStage$pipelines_1_first[68] && !checkForException___d13943[4] && @@ -25831,7 +25831,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3035, - x__h295971 } ; + x__h295972 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16426 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271, @@ -25850,8 +25850,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10246 = - { {4{f2_exp26064_MINUS_127__q176[7]}}, - f2_exp26064_MINUS_127__q176 } ; + { {4{f2_exp26065_MINUS_127__q176[7]}}, + f2_exp26065_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10246 ^ 12'h800) <= @@ -25861,12 +25861,12 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11191 = - b__h608064 * b__h608140 ; + b__h608065 * b__h608141 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11204 = - b__h608064 * b__h608253 ; + b__h608065 * b__h608254 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8761 = - { {4{f1_exp87070_MINUS_127__q136[7]}}, - f1_exp87070_MINUS_127__q136 } ; + { {4{f1_exp87071_MINUS_127__q136[7]}}, + f1_exp87071_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8761 ^ 12'h800) <= @@ -25876,8 +25876,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9476 = - { {4{f3_exp65368_MINUS_127__q153[7]}}, - f3_exp65368_MINUS_127__q153 } ; + { {4{f3_exp65369_MINUS_127__q153[7]}}, + f3_exp65369_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9476 ^ 12'h800) <= @@ -25962,15 +25962,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5269 = { 3'd0, - _theResult___fst_exp__h358618 == 8'd0 && - (sfdin__h358612[56:34] == 23'd0 || guard__h350517 != 2'b0), + _theResult___fst_exp__h358619 == 8'd0 && + (sfdin__h358613[56:34] == 23'd0 || guard__h350518 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h359215 == 8'd255 && - _theResult___fst_sfd__h359216 == 23'd0, + _theResult___fst_exp__h359216 == 8'd255 && + _theResult___fst_sfd__h359217 == 23'd0, 1'd0, - _theResult___fst_exp__h358618 != 8'd255 && - guard__h350517 != 2'b0 } ; + _theResult___fst_exp__h358619 != 8'd255 && + guard__h350518 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5741 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 } ^ @@ -25978,15 +25978,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6661 = { 3'd0, - _theResult___fst_exp__h404315 == 8'd0 && - (sfdin__h404309[56:34] == 23'd0 || guard__h396216 != 2'b0), + _theResult___fst_exp__h404316 == 8'd0 && + (sfdin__h404310[56:34] == 23'd0 || guard__h396217 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h404912 == 8'd255 && - _theResult___fst_sfd__h404913 == 23'd0, + _theResult___fst_exp__h404913 == 8'd255 && + _theResult___fst_sfd__h404914 == 23'd0, 1'd0, - _theResult___fst_exp__h404315 != 8'd255 && - guard__h396216 != 2'b0 } ; + _theResult___fst_exp__h404316 != 8'd255 && + guard__h396217 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7133 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 } ^ @@ -25994,15 +25994,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8053 = { 3'd0, - _theResult___fst_exp__h450010 == 8'd0 && - (sfdin__h450004[56:34] == 23'd0 || guard__h441911 != 2'b0), + _theResult___fst_exp__h450011 == 8'd0 && + (sfdin__h450005[56:34] == 23'd0 || guard__h441912 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h450607 == 8'd255 && - _theResult___fst_sfd__h450608 == 23'd0, + _theResult___fst_exp__h450608 == 8'd255 && + _theResult___fst_sfd__h450609 == 23'd0, 1'd0, - _theResult___fst_exp__h450010 != 8'd255 && - guard__h441911 != 2'b0 } ; + _theResult___fst_exp__h450011 != 8'd255 && + guard__h441912 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10497 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 } ^ @@ -26010,37 +26010,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10873 = { 3'd0, - _theResult___fst_exp__h516035 == 11'd0 && - (sfdin__h516029[56:5] == 52'd0 || guard__h507809 != 2'b0), + _theResult___fst_exp__h516036 == 11'd0 && + (sfdin__h516030[56:5] == 52'd0 || guard__h507810 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h516867 == 11'd2047 && - _theResult___fst_sfd__h516868 == 52'd0, + _theResult___fst_exp__h516868 == 11'd2047 && + _theResult___fst_sfd__h516869 == 52'd0, 1'd0, - _theResult___fst_exp__h516035 != 11'd2047 && - guard__h507809 != 2'b0 } ; + _theResult___fst_exp__h516036 != 11'd2047 && + guard__h507810 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10914 = { 3'd0, - _theResult___fst_exp__h554888 == 11'd0 && - (sfdin__h554882[56:5] == 52'd0 || guard__h546662 != 2'b0), + _theResult___fst_exp__h554889 == 11'd0 && + (sfdin__h554883[56:5] == 52'd0 || guard__h546663 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h555720 == 11'd2047 && - _theResult___fst_sfd__h555721 == 52'd0, + _theResult___fst_exp__h555721 == 11'd2047 && + _theResult___fst_sfd__h555722 == 52'd0, 1'd0, - _theResult___fst_exp__h554888 != 11'd2047 && - guard__h546662 != 2'b0 } ; + _theResult___fst_exp__h554889 != 11'd2047 && + guard__h546663 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10958 = { 3'd0, - _theResult___fst_exp__h594192 == 11'd0 && - (sfdin__h594186[56:5] == 52'd0 || guard__h585966 != 2'b0), + _theResult___fst_exp__h594193 == 11'd0 && + (sfdin__h594187[56:5] == 52'd0 || guard__h585967 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h595024 == 11'd2047 && - _theResult___fst_sfd__h595025 == 52'd0, + _theResult___fst_exp__h595025 == 11'd2047 && + _theResult___fst_sfd__h595026 == 52'd0, 1'd0, - _theResult___fst_exp__h594192 != 11'd2047 && - guard__h585966 != 2'b0 } ; + _theResult___fst_exp__h594193 != 11'd2047 && + guard__h585967 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9012 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 } ^ @@ -26058,15 +26058,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5298 = { 3'd0, - _theResult___fst_exp__h376384 == 8'd0 && - (sfdin__h376378[56:34] == 23'd0 || guard__h368156 != 2'b0), + _theResult___fst_exp__h376385 == 8'd0 && + (sfdin__h376379[56:34] == 23'd0 || guard__h368157 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h376981 == 8'd255 && - _theResult___fst_sfd__h376982 == 23'd0, + _theResult___fst_exp__h376982 == 8'd255 && + _theResult___fst_sfd__h376983 == 23'd0, 1'd0, - _theResult___fst_exp__h376384 != 8'd255 && - guard__h368156 != 2'b0 } ; + _theResult___fst_exp__h376385 != 8'd255 && + guard__h368157 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6292 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 } ^ @@ -26074,15 +26074,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6690 = { 3'd0, - _theResult___fst_exp__h422081 == 8'd0 && - (sfdin__h422075[56:34] == 23'd0 || guard__h413853 != 2'b0), + _theResult___fst_exp__h422082 == 8'd0 && + (sfdin__h422076[56:34] == 23'd0 || guard__h413854 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h422678 == 8'd255 && - _theResult___fst_sfd__h422679 == 23'd0, + _theResult___fst_exp__h422679 == 8'd255 && + _theResult___fst_sfd__h422680 == 23'd0, 1'd0, - _theResult___fst_exp__h422081 != 8'd255 && - guard__h413853 != 2'b0 } ; + _theResult___fst_exp__h422082 != 8'd255 && + guard__h413854 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7684 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 } ^ @@ -26090,15 +26090,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8082 = { 3'd0, - _theResult___fst_exp__h467776 == 8'd0 && - (sfdin__h467770[56:34] == 23'd0 || guard__h459548 != 2'b0), + _theResult___fst_exp__h467777 == 8'd0 && + (sfdin__h467771[56:34] == 23'd0 || guard__h459549 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h468373 == 8'd255 && - _theResult___fst_sfd__h468374 == 23'd0, + _theResult___fst_exp__h468374 == 8'd255 && + _theResult___fst_sfd__h468375 == 23'd0, 1'd0, - _theResult___fst_exp__h467776 != 8'd255 && - guard__h459548 != 2'b0 } ; + _theResult___fst_exp__h467777 != 8'd255 && + guard__h459549 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10200 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 } ^ @@ -26112,37 +26112,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10856 = { 3'd0, - _theResult___fst_exp__h506458 == 11'd0 && - guard__h498497 != 2'b0, + _theResult___fst_exp__h506459 == 11'd0 && + guard__h498498 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h507216 == 11'd2047 && - _theResult___fst_sfd__h507217 == 52'd0, + _theResult___fst_exp__h507217 == 11'd2047 && + _theResult___fst_sfd__h507218 == 52'd0, 1'd0, - _theResult___fst_exp__h506458 != 11'd2047 && - guard__h498497 != 2'b0 } ; + _theResult___fst_exp__h506459 != 11'd2047 && + guard__h498498 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10897 = { 3'd0, - _theResult___fst_exp__h545311 == 11'd0 && - guard__h537350 != 2'b0, + _theResult___fst_exp__h545312 == 11'd0 && + guard__h537351 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h546069 == 11'd2047 && - _theResult___fst_sfd__h546070 == 52'd0, + _theResult___fst_exp__h546070 == 11'd2047 && + _theResult___fst_sfd__h546071 == 52'd0, 1'd0, - _theResult___fst_exp__h545311 != 11'd2047 && - guard__h537350 != 2'b0 } ; + _theResult___fst_exp__h545312 != 11'd2047 && + guard__h537351 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10941 = { 3'd0, - _theResult___fst_exp__h584615 == 11'd0 && - guard__h576654 != 2'b0, + _theResult___fst_exp__h584616 == 11'd0 && + guard__h576655 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h585373 == 11'd2047 && - _theResult___fst_sfd__h585374 == 52'd0, + _theResult___fst_exp__h585374 == 11'd2047 && + _theResult___fst_sfd__h585375 == 52'd0, 1'd0, - _theResult___fst_exp__h584615 != 11'd2047 && - guard__h576654 != 2'b0 } ; + _theResult___fst_exp__h584616 != 11'd2047 && + guard__h576655 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8700 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 } ^ @@ -26178,15 +26178,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5281 = { 3'd0, - _theResult___fst_exp__h367274 == 8'd0 && - guard__h359226 != 2'b0, + _theResult___fst_exp__h367275 == 8'd0 && + guard__h359227 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h367797 == 8'd255 && - _theResult___fst_sfd__h367798 == 23'd0, + _theResult___fst_exp__h367798 == 8'd255 && + _theResult___fst_sfd__h367799 == 23'd0, 1'd0, - _theResult___fst_exp__h367274 != 8'd255 && - guard__h359226 != 2'b0 } ; + _theResult___fst_exp__h367275 != 8'd255 && + guard__h359227 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5972 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 } ^ @@ -26200,15 +26200,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6673 = { 3'd0, - _theResult___fst_exp__h412971 == 8'd0 && - guard__h404923 != 2'b0, + _theResult___fst_exp__h412972 == 8'd0 && + guard__h404924 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h413494 == 8'd255 && - _theResult___fst_sfd__h413495 == 23'd0, + _theResult___fst_exp__h413495 == 8'd255 && + _theResult___fst_sfd__h413496 == 23'd0, 1'd0, - _theResult___fst_exp__h412971 != 8'd255 && - guard__h404923 != 2'b0 } ; + _theResult___fst_exp__h412972 != 8'd255 && + guard__h404924 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7364 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 } ^ @@ -26222,17 +26222,17 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8065 = { 3'd0, - _theResult___fst_exp__h458666 == 8'd0 && - guard__h450618 != 2'b0, + _theResult___fst_exp__h458667 == 8'd0 && + guard__h450619 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h459189 == 8'd255 && - _theResult___fst_sfd__h459190 == 23'd0, + _theResult___fst_exp__h459190 == 8'd255 && + _theResult___fst_sfd__h459191 == 23'd0, 1'd0, - _theResult___fst_exp__h458666 != 8'd255 && - guard__h450618 != 2'b0 } ; + _theResult___fst_exp__h458667 != 8'd255 && + guard__h450619 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11197 = - b__h608241 * b__h608253 ; + b__h608242 * b__h608254 ; assign _0_CONCAT_csrf_external_int_en_vec_3_read__1864_ETC___d13033 = { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, @@ -26246,7 +26246,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2992_BI_ETC___d14173 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + CASE_k77212_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__3001_BI_ETC___d14074 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -26260,35 +26260,35 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2990_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10253 = - sfd__h526426 >> + sfd__h526427 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10249 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8768 = - sfd__h487432 >> + sfd__h487433 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8764 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9483 = - sfd__h565730 >> + sfd__h565731 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9479 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658 = - sfd__h342902 >> + sfd__h342903 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050 = - sfd__h388604 >> + sfd__h388605 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442 = - sfd__h434299 >> + sfd__h434300 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438) ; assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14631 = - mip_csr__read__h617589 == commitStage_rg_old_mip_csr_val ; + mip_csr__read__h617590 == commitStage_rg_old_mip_csr_val ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15028 = - medeleg_csr__read__h616708[i__h718403] ; + medeleg_csr__read__h616709[i__h718404] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1853_1854_ETC___d15010 = - mideleg_csr__read__h616803[i__h718563] ; + mideleg_csr__read__h616804[i__h718564] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4111 = 12'd3074 - { 6'd0, @@ -26694,51 +26694,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10124 = 12'd3970 - { 7'd0, - f2_sfd__h526065[22] ? + f2_sfd__h526066[22] ? 5'd0 : - (f2_sfd__h526065[21] ? + (f2_sfd__h526066[21] ? 5'd1 : - (f2_sfd__h526065[20] ? + (f2_sfd__h526066[20] ? 5'd2 : - (f2_sfd__h526065[19] ? + (f2_sfd__h526066[19] ? 5'd3 : - (f2_sfd__h526065[18] ? + (f2_sfd__h526066[18] ? 5'd4 : - (f2_sfd__h526065[17] ? + (f2_sfd__h526066[17] ? 5'd5 : - (f2_sfd__h526065[16] ? + (f2_sfd__h526066[16] ? 5'd6 : - (f2_sfd__h526065[15] ? + (f2_sfd__h526066[15] ? 5'd7 : - (f2_sfd__h526065[14] ? + (f2_sfd__h526066[14] ? 5'd8 : - (f2_sfd__h526065[13] ? + (f2_sfd__h526066[13] ? 5'd9 : - (f2_sfd__h526065[12] ? + (f2_sfd__h526066[12] ? 5'd10 : - (f2_sfd__h526065[11] ? + (f2_sfd__h526066[11] ? 5'd11 : - (f2_sfd__h526065[10] ? + (f2_sfd__h526066[10] ? 5'd12 : - (f2_sfd__h526065[9] ? + (f2_sfd__h526066[9] ? 5'd13 : - (f2_sfd__h526065[8] ? + (f2_sfd__h526066[8] ? 5'd14 : - (f2_sfd__h526065[7] ? + (f2_sfd__h526066[7] ? 5'd15 : - (f2_sfd__h526065[6] ? + (f2_sfd__h526066[6] ? 5'd16 : - (f2_sfd__h526065[5] ? + (f2_sfd__h526066[5] ? 5'd17 : - (f2_sfd__h526065[4] ? + (f2_sfd__h526066[4] ? 5'd18 : - (f2_sfd__h526065[3] ? + (f2_sfd__h526066[3] ? 5'd19 : - (f2_sfd__h526065[2] ? + (f2_sfd__h526066[2] ? 5'd20 : - (f2_sfd__h526065[1] ? + (f2_sfd__h526066[1] ? 5'd21 : - (f2_sfd__h526065[0] ? + (f2_sfd__h526066[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 = @@ -26752,51 +26752,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8624 = 12'd3970 - { 7'd0, - f1_sfd__h487071[22] ? + f1_sfd__h487072[22] ? 5'd0 : - (f1_sfd__h487071[21] ? + (f1_sfd__h487072[21] ? 5'd1 : - (f1_sfd__h487071[20] ? + (f1_sfd__h487072[20] ? 5'd2 : - (f1_sfd__h487071[19] ? + (f1_sfd__h487072[19] ? 5'd3 : - (f1_sfd__h487071[18] ? + (f1_sfd__h487072[18] ? 5'd4 : - (f1_sfd__h487071[17] ? + (f1_sfd__h487072[17] ? 5'd5 : - (f1_sfd__h487071[16] ? + (f1_sfd__h487072[16] ? 5'd6 : - (f1_sfd__h487071[15] ? + (f1_sfd__h487072[15] ? 5'd7 : - (f1_sfd__h487071[14] ? + (f1_sfd__h487072[14] ? 5'd8 : - (f1_sfd__h487071[13] ? + (f1_sfd__h487072[13] ? 5'd9 : - (f1_sfd__h487071[12] ? + (f1_sfd__h487072[12] ? 5'd10 : - (f1_sfd__h487071[11] ? + (f1_sfd__h487072[11] ? 5'd11 : - (f1_sfd__h487071[10] ? + (f1_sfd__h487072[10] ? 5'd12 : - (f1_sfd__h487071[9] ? + (f1_sfd__h487072[9] ? 5'd13 : - (f1_sfd__h487071[8] ? + (f1_sfd__h487072[8] ? 5'd14 : - (f1_sfd__h487071[7] ? + (f1_sfd__h487072[7] ? 5'd15 : - (f1_sfd__h487071[6] ? + (f1_sfd__h487072[6] ? 5'd16 : - (f1_sfd__h487071[5] ? + (f1_sfd__h487072[5] ? 5'd17 : - (f1_sfd__h487071[4] ? + (f1_sfd__h487072[4] ? 5'd18 : - (f1_sfd__h487071[3] ? + (f1_sfd__h487072[3] ? 5'd19 : - (f1_sfd__h487071[2] ? + (f1_sfd__h487072[2] ? 5'd20 : - (f1_sfd__h487071[1] ? + (f1_sfd__h487072[1] ? 5'd21 : - (f1_sfd__h487071[0] ? + (f1_sfd__h487072[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 = @@ -26810,51 +26810,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9354 = 12'd3970 - { 7'd0, - f3_sfd__h565369[22] ? + f3_sfd__h565370[22] ? 5'd0 : - (f3_sfd__h565369[21] ? + (f3_sfd__h565370[21] ? 5'd1 : - (f3_sfd__h565369[20] ? + (f3_sfd__h565370[20] ? 5'd2 : - (f3_sfd__h565369[19] ? + (f3_sfd__h565370[19] ? 5'd3 : - (f3_sfd__h565369[18] ? + (f3_sfd__h565370[18] ? 5'd4 : - (f3_sfd__h565369[17] ? + (f3_sfd__h565370[17] ? 5'd5 : - (f3_sfd__h565369[16] ? + (f3_sfd__h565370[16] ? 5'd6 : - (f3_sfd__h565369[15] ? + (f3_sfd__h565370[15] ? 5'd7 : - (f3_sfd__h565369[14] ? + (f3_sfd__h565370[14] ? 5'd8 : - (f3_sfd__h565369[13] ? + (f3_sfd__h565370[13] ? 5'd9 : - (f3_sfd__h565369[12] ? + (f3_sfd__h565370[12] ? 5'd10 : - (f3_sfd__h565369[11] ? + (f3_sfd__h565370[11] ? 5'd11 : - (f3_sfd__h565369[10] ? + (f3_sfd__h565370[10] ? 5'd12 : - (f3_sfd__h565369[9] ? + (f3_sfd__h565370[9] ? 5'd13 : - (f3_sfd__h565369[8] ? + (f3_sfd__h565370[8] ? 5'd14 : - (f3_sfd__h565369[7] ? + (f3_sfd__h565370[7] ? 5'd15 : - (f3_sfd__h565369[6] ? + (f3_sfd__h565370[6] ? 5'd16 : - (f3_sfd__h565369[5] ? + (f3_sfd__h565370[5] ? 5'd17 : - (f3_sfd__h565369[4] ? + (f3_sfd__h565370[4] ? 5'd18 : - (f3_sfd__h565369[3] ? + (f3_sfd__h565370[3] ? 5'd19 : - (f3_sfd__h565369[2] ? + (f3_sfd__h565370[2] ? 5'd20 : - (f3_sfd__h565369[1] ? + (f3_sfd__h565370[1] ? 5'd21 : - (f3_sfd__h565369[0] ? + (f3_sfd__h565370[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 = @@ -26883,14 +26883,14 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14548 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h677211 == 1'd1 && + k__h677212 == 1'd1 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345 || (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14452 || NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14465) == 1'd1 && NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14484 ; assign _dfoo18 = - k__h677211 == 1'd0 && + k__h677212 == 1'd0 && fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14345 || (fetchStage_pipelines_0_canDeq__2990_AND_NOT_fe_ETC___d14452 || NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14465) == @@ -27007,1421 +27007,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h300943 = + assign _theResult_____2__h300944 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3146) ? - next_deqP___1__h301222 : + next_deqP___1__h301223 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h308939 = + assign _theResult_____2__h308940 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3253) ? - next_deqP___1__h309218 : + next_deqP___1__h309219 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h314933 = + assign _theResult_____2__h314934 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3424) ? - next_deqP___1__h315499 : + next_deqP___1__h315500 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h322787 = + assign _theResult_____2__h322788 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3520) ? - next_deqP___1__h323353 : + next_deqP___1__h323354 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h333131 = + assign _theResult_____2__h333132 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3749) ? - next_deqP___1__h333410 : + next_deqP___1__h333411 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h336356 = + assign _theResult_____2__h336357 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3843) ? - next_deqP___1__h336635 : + next_deqP___1__h336636 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h350507 = - (value__h351129 == 54'd0) ? sfd__h342902 : 57'd1 ; - assign _theResult____h368146 = + assign _theResult____h350508 = + (value__h351130 == 54'd0) ? sfd__h342903 : 57'd1 ; + assign _theResult____h368147 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654 ^ 12'h800) < 12'd2105) ? - result__h368759 : - _theResult____h350507 ; - assign _theResult____h396206 = - (value__h396826 == 54'd0) ? sfd__h388604 : 57'd1 ; - assign _theResult____h413843 = + result__h368760 : + _theResult____h350508 ; + assign _theResult____h396207 = + (value__h396827 == 54'd0) ? sfd__h388605 : 57'd1 ; + assign _theResult____h413844 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046 ^ 12'h800) < 12'd2105) ? - result__h414456 : - _theResult____h396206 ; - assign _theResult____h441901 = - (value__h442521 == 54'd0) ? sfd__h434299 : 57'd1 ; - assign _theResult____h459538 = + result__h414457 : + _theResult____h396207 ; + assign _theResult____h441902 = + (value__h442522 == 54'd0) ? sfd__h434300 : 57'd1 ; + assign _theResult____h459539 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438 ^ 12'h800) < 12'd2105) ? - result__h460151 : - _theResult____h441901 ; - assign _theResult____h507799 = + result__h460152 : + _theResult____h441902 ; + assign _theResult____h507800 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8764 ^ 12'h800) < 12'd2105) ? - result__h508412 : - ((value__h492015 == 25'd0) ? sfd__h487432 : 57'd1) ; - assign _theResult____h546652 = + result__h508413 : + ((value__h492016 == 25'd0) ? sfd__h487433 : 57'd1) ; + assign _theResult____h546653 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10249 ^ 12'h800) < 12'd2105) ? - result__h547265 : - ((value__h530868 == 25'd0) ? sfd__h526426 : 57'd1) ; - assign _theResult____h585956 = + result__h547266 : + ((value__h530869 == 25'd0) ? sfd__h526427 : 57'd1) ; + assign _theResult____h585957 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9479 ^ 12'h800) < 12'd2105) ? - result__h586569 : - ((value__h570172 == 25'd0) ? sfd__h565730 : 57'd1) ; - assign _theResult____h658376 = + result__h586570 : + ((value__h570173 == 25'd0) ? sfd__h565731 : 57'd1) ; + assign _theResult____h658377 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h658901 : + enabled_ints___1__h658902 : 16'd0 ; - assign _theResult___exp__h359134 = - sfd__h358710[24] ? - ((_theResult___fst_exp__h358618 == 8'd254) ? + assign _theResult___exp__h359135 = + sfd__h358711[24] ? + ((_theResult___fst_exp__h358619 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385651) : - ((_theResult___fst_exp__h358618 == 8'd0 && - sfd__h358710[24:23] == 2'b01) ? + din_inc___2_exp__h385652) : + ((_theResult___fst_exp__h358619 == 8'd0 && + sfd__h358711[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h358618) ; - assign _theResult___exp__h367716 = - sfd__h367292[24] ? - ((_theResult___fst_exp__h367274 == 8'd254) ? + _theResult___fst_exp__h358619) ; + assign _theResult___exp__h367717 = + sfd__h367293[24] ? + ((_theResult___fst_exp__h367275 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385675) : - ((_theResult___fst_exp__h367274 == 8'd0 && - sfd__h367292[24:23] == 2'b01) ? + din_inc___2_exp__h385676) : + ((_theResult___fst_exp__h367275 == 8'd0 && + sfd__h367293[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h367274) ; - assign _theResult___exp__h376900 = - sfd__h376476[24] ? - ((_theResult___fst_exp__h376384 == 8'd254) ? + _theResult___fst_exp__h367275) ; + assign _theResult___exp__h376901 = + sfd__h376477[24] ? + ((_theResult___fst_exp__h376385 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385705) : - ((_theResult___fst_exp__h376384 == 8'd0 && - sfd__h376476[24:23] == 2'b01) ? + din_inc___2_exp__h385706) : + ((_theResult___fst_exp__h376385 == 8'd0 && + sfd__h376477[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h376384) ; - assign _theResult___exp__h385536 = - sfd__h385088[24] ? - ((_theResult___fst_exp__h385069 == 8'd254) ? + _theResult___fst_exp__h376385) ; + assign _theResult___exp__h385537 = + sfd__h385089[24] ? + ((_theResult___fst_exp__h385070 == 8'd254) ? 8'd255 : - din_inc___2_exp__h385729) : - ((_theResult___fst_exp__h385069 == 8'd0 && - sfd__h385088[24:23] == 2'b01) ? + din_inc___2_exp__h385730) : + ((_theResult___fst_exp__h385070 == 8'd0 && + sfd__h385089[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h385069) ; - assign _theResult___exp__h385638 = + _theResult___fst_exp__h385070) ; + assign _theResult___exp__h385639 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385629 ; - assign _theResult___exp__h404831 = - sfd__h404407[24] ? - ((_theResult___fst_exp__h404315 == 8'd254) ? + _theResult___fst_exp__h385630 ; + assign _theResult___exp__h404832 = + sfd__h404408[24] ? + ((_theResult___fst_exp__h404316 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431348) : - ((_theResult___fst_exp__h404315 == 8'd0 && - sfd__h404407[24:23] == 2'b01) ? + din_inc___2_exp__h431349) : + ((_theResult___fst_exp__h404316 == 8'd0 && + sfd__h404408[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h404315) ; - assign _theResult___exp__h413413 = - sfd__h412989[24] ? - ((_theResult___fst_exp__h412971 == 8'd254) ? + _theResult___fst_exp__h404316) ; + assign _theResult___exp__h413414 = + sfd__h412990[24] ? + ((_theResult___fst_exp__h412972 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431372) : - ((_theResult___fst_exp__h412971 == 8'd0 && - sfd__h412989[24:23] == 2'b01) ? + din_inc___2_exp__h431373) : + ((_theResult___fst_exp__h412972 == 8'd0 && + sfd__h412990[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h412971) ; - assign _theResult___exp__h422597 = - sfd__h422173[24] ? - ((_theResult___fst_exp__h422081 == 8'd254) ? + _theResult___fst_exp__h412972) ; + assign _theResult___exp__h422598 = + sfd__h422174[24] ? + ((_theResult___fst_exp__h422082 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431402) : - ((_theResult___fst_exp__h422081 == 8'd0 && - sfd__h422173[24:23] == 2'b01) ? + din_inc___2_exp__h431403) : + ((_theResult___fst_exp__h422082 == 8'd0 && + sfd__h422174[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h422081) ; - assign _theResult___exp__h431233 = - sfd__h430785[24] ? - ((_theResult___fst_exp__h430766 == 8'd254) ? + _theResult___fst_exp__h422082) ; + assign _theResult___exp__h431234 = + sfd__h430786[24] ? + ((_theResult___fst_exp__h430767 == 8'd254) ? 8'd255 : - din_inc___2_exp__h431426) : - ((_theResult___fst_exp__h430766 == 8'd0 && - sfd__h430785[24:23] == 2'b01) ? + din_inc___2_exp__h431427) : + ((_theResult___fst_exp__h430767 == 8'd0 && + sfd__h430786[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h430766) ; - assign _theResult___exp__h431335 = + _theResult___fst_exp__h430767) ; + assign _theResult___exp__h431336 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431326 ; - assign _theResult___exp__h450526 = - sfd__h450102[24] ? - ((_theResult___fst_exp__h450010 == 8'd254) ? + _theResult___fst_exp__h431327 ; + assign _theResult___exp__h450527 = + sfd__h450103[24] ? + ((_theResult___fst_exp__h450011 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477043) : - ((_theResult___fst_exp__h450010 == 8'd0 && - sfd__h450102[24:23] == 2'b01) ? + din_inc___2_exp__h477044) : + ((_theResult___fst_exp__h450011 == 8'd0 && + sfd__h450103[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h450010) ; - assign _theResult___exp__h459108 = - sfd__h458684[24] ? - ((_theResult___fst_exp__h458666 == 8'd254) ? + _theResult___fst_exp__h450011) ; + assign _theResult___exp__h459109 = + sfd__h458685[24] ? + ((_theResult___fst_exp__h458667 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477067) : - ((_theResult___fst_exp__h458666 == 8'd0 && - sfd__h458684[24:23] == 2'b01) ? + din_inc___2_exp__h477068) : + ((_theResult___fst_exp__h458667 == 8'd0 && + sfd__h458685[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h458666) ; - assign _theResult___exp__h468292 = - sfd__h467868[24] ? - ((_theResult___fst_exp__h467776 == 8'd254) ? + _theResult___fst_exp__h458667) ; + assign _theResult___exp__h468293 = + sfd__h467869[24] ? + ((_theResult___fst_exp__h467777 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477097) : - ((_theResult___fst_exp__h467776 == 8'd0 && - sfd__h467868[24:23] == 2'b01) ? + din_inc___2_exp__h477098) : + ((_theResult___fst_exp__h467777 == 8'd0 && + sfd__h467869[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h467776) ; - assign _theResult___exp__h476928 = - sfd__h476480[24] ? - ((_theResult___fst_exp__h476461 == 8'd254) ? + _theResult___fst_exp__h467777) ; + assign _theResult___exp__h476929 = + sfd__h476481[24] ? + ((_theResult___fst_exp__h476462 == 8'd254) ? 8'd255 : - din_inc___2_exp__h477121) : - ((_theResult___fst_exp__h476461 == 8'd0 && - sfd__h476480[24:23] == 2'b01) ? + din_inc___2_exp__h477122) : + ((_theResult___fst_exp__h476462 == 8'd0 && + sfd__h476481[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h476461) ; - assign _theResult___exp__h477030 = + _theResult___fst_exp__h476462) ; + assign _theResult___exp__h477031 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477021 ; - assign _theResult___exp__h507113 = - sfd__h506476[53] ? - ((_theResult___fst_exp__h506458 == 11'd2046) ? + _theResult___fst_exp__h477022 ; + assign _theResult___exp__h507114 = + sfd__h506477[53] ? + ((_theResult___fst_exp__h506459 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525708) : - ((_theResult___fst_exp__h506458 == 11'd0 && - sfd__h506476[53:52] == 2'b01) ? + din_inc___2_exp__h525709) : + ((_theResult___fst_exp__h506459 == 11'd0 && + sfd__h506477[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h506458) ; - assign _theResult___exp__h516764 = - sfd__h516127[53] ? - ((_theResult___fst_exp__h516035 == 11'd2046) ? + _theResult___fst_exp__h506459) ; + assign _theResult___exp__h516765 = + sfd__h516128[53] ? + ((_theResult___fst_exp__h516036 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525743) : - ((_theResult___fst_exp__h516035 == 11'd0 && - sfd__h516127[53:52] == 2'b01) ? + din_inc___2_exp__h525744) : + ((_theResult___fst_exp__h516036 == 11'd0 && + sfd__h516128[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h516035) ; - assign _theResult___exp__h525548 = - sfd__h524887[53] ? - ((_theResult___fst_exp__h524868 == 11'd2046) ? + _theResult___fst_exp__h516036) ; + assign _theResult___exp__h525549 = + sfd__h524888[53] ? + ((_theResult___fst_exp__h524869 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h525769) : - ((_theResult___fst_exp__h524868 == 11'd0 && - sfd__h524887[53:52] == 2'b01) ? + din_inc___2_exp__h525770) : + ((_theResult___fst_exp__h524869 == 11'd0 && + sfd__h524888[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h524868) ; - assign _theResult___exp__h545966 = - sfd__h545329[53] ? - ((_theResult___fst_exp__h545311 == 11'd2046) ? + _theResult___fst_exp__h524869) ; + assign _theResult___exp__h545967 = + sfd__h545330[53] ? + ((_theResult___fst_exp__h545312 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564561) : - ((_theResult___fst_exp__h545311 == 11'd0 && - sfd__h545329[53:52] == 2'b01) ? + din_inc___2_exp__h564562) : + ((_theResult___fst_exp__h545312 == 11'd0 && + sfd__h545330[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h545311) ; - assign _theResult___exp__h555617 = - sfd__h554980[53] ? - ((_theResult___fst_exp__h554888 == 11'd2046) ? + _theResult___fst_exp__h545312) ; + assign _theResult___exp__h555618 = + sfd__h554981[53] ? + ((_theResult___fst_exp__h554889 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564596) : - ((_theResult___fst_exp__h554888 == 11'd0 && - sfd__h554980[53:52] == 2'b01) ? + din_inc___2_exp__h564597) : + ((_theResult___fst_exp__h554889 == 11'd0 && + sfd__h554981[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h554888) ; - assign _theResult___exp__h564401 = - sfd__h563740[53] ? - ((_theResult___fst_exp__h563721 == 11'd2046) ? + _theResult___fst_exp__h554889) ; + assign _theResult___exp__h564402 = + sfd__h563741[53] ? + ((_theResult___fst_exp__h563722 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h564622) : - ((_theResult___fst_exp__h563721 == 11'd0 && - sfd__h563740[53:52] == 2'b01) ? + din_inc___2_exp__h564623) : + ((_theResult___fst_exp__h563722 == 11'd0 && + sfd__h563741[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h563721) ; - assign _theResult___exp__h585270 = - sfd__h584633[53] ? - ((_theResult___fst_exp__h584615 == 11'd2046) ? + _theResult___fst_exp__h563722) ; + assign _theResult___exp__h585271 = + sfd__h584634[53] ? + ((_theResult___fst_exp__h584616 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603865) : - ((_theResult___fst_exp__h584615 == 11'd0 && - sfd__h584633[53:52] == 2'b01) ? + din_inc___2_exp__h603866) : + ((_theResult___fst_exp__h584616 == 11'd0 && + sfd__h584634[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h584615) ; - assign _theResult___exp__h594921 = - sfd__h594284[53] ? - ((_theResult___fst_exp__h594192 == 11'd2046) ? + _theResult___fst_exp__h584616) ; + assign _theResult___exp__h594922 = + sfd__h594285[53] ? + ((_theResult___fst_exp__h594193 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603900) : - ((_theResult___fst_exp__h594192 == 11'd0 && - sfd__h594284[53:52] == 2'b01) ? + din_inc___2_exp__h603901) : + ((_theResult___fst_exp__h594193 == 11'd0 && + sfd__h594285[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h594192) ; - assign _theResult___exp__h603705 = - sfd__h603044[53] ? - ((_theResult___fst_exp__h603025 == 11'd2046) ? + _theResult___fst_exp__h594193) ; + assign _theResult___exp__h603706 = + sfd__h603045[53] ? + ((_theResult___fst_exp__h603026 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h603926) : - ((_theResult___fst_exp__h603025 == 11'd0 && - sfd__h603044[53:52] == 2'b01) ? + din_inc___2_exp__h603927) : + ((_theResult___fst_exp__h603026 == 11'd0 && + sfd__h603045[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h603025) ; - assign _theResult___fst__h608464 = - a__h607916[63] ? a___1__h608469 : a__h607916 ; - assign _theResult___fst_exp__h358618 = - _theResult____h350507[56] ? + _theResult___fst_exp__h603026) ; + assign _theResult___fst__h608465 = + a__h607917[63] ? a___1__h608470 : a__h607917 ; + assign _theResult___fst_exp__h358619 = + _theResult____h350508[56] ? 8'd2 : - _theResult___fst_exp__h358692 ; - assign _theResult___fst_exp__h358683 = + _theResult___fst_exp__h358693 ; + assign _theResult___fst_exp__h358684 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347 } ; - assign _theResult___fst_exp__h358689 = - (!_theResult____h350507[56] && !_theResult____h350507[55] && - !_theResult____h350507[54] && - !_theResult____h350507[53] && - !_theResult____h350507[52] && - !_theResult____h350507[51] && - !_theResult____h350507[50] && - !_theResult____h350507[49] && - !_theResult____h350507[48] && - !_theResult____h350507[47] && - !_theResult____h350507[46] && - !_theResult____h350507[45] && - !_theResult____h350507[44] && - !_theResult____h350507[43] && - !_theResult____h350507[42] && - !_theResult____h350507[41] && - !_theResult____h350507[40] && - !_theResult____h350507[39] && - !_theResult____h350507[38] && - !_theResult____h350507[37] && - !_theResult____h350507[36] && - !_theResult____h350507[35] && - !_theResult____h350507[34] && - !_theResult____h350507[33] && - !_theResult____h350507[32] && - !_theResult____h350507[31] && - !_theResult____h350507[30] && - !_theResult____h350507[29] && - !_theResult____h350507[28] && - !_theResult____h350507[27] && - !_theResult____h350507[26] && - !_theResult____h350507[25] && - !_theResult____h350507[24] && - !_theResult____h350507[23] && - !_theResult____h350507[22] && - !_theResult____h350507[21] && - !_theResult____h350507[20] && - !_theResult____h350507[19] && - !_theResult____h350507[18] && - !_theResult____h350507[17] && - !_theResult____h350507[16] && - !_theResult____h350507[15] && - !_theResult____h350507[14] && - !_theResult____h350507[13] && - !_theResult____h350507[12] && - !_theResult____h350507[11] && - !_theResult____h350507[10] && - !_theResult____h350507[9] && - !_theResult____h350507[8] && - !_theResult____h350507[7] && - !_theResult____h350507[6] && - !_theResult____h350507[5] && - !_theResult____h350507[4] && - !_theResult____h350507[3] && - !_theResult____h350507[2] && - !_theResult____h350507[1] && - !_theResult____h350507[0] || + assign _theResult___fst_exp__h358690 = + (!_theResult____h350508[56] && !_theResult____h350508[55] && + !_theResult____h350508[54] && + !_theResult____h350508[53] && + !_theResult____h350508[52] && + !_theResult____h350508[51] && + !_theResult____h350508[50] && + !_theResult____h350508[49] && + !_theResult____h350508[48] && + !_theResult____h350508[47] && + !_theResult____h350508[46] && + !_theResult____h350508[45] && + !_theResult____h350508[44] && + !_theResult____h350508[43] && + !_theResult____h350508[42] && + !_theResult____h350508[41] && + !_theResult____h350508[40] && + !_theResult____h350508[39] && + !_theResult____h350508[38] && + !_theResult____h350508[37] && + !_theResult____h350508[36] && + !_theResult____h350508[35] && + !_theResult____h350508[34] && + !_theResult____h350508[33] && + !_theResult____h350508[32] && + !_theResult____h350508[31] && + !_theResult____h350508[30] && + !_theResult____h350508[29] && + !_theResult____h350508[28] && + !_theResult____h350508[27] && + !_theResult____h350508[26] && + !_theResult____h350508[25] && + !_theResult____h350508[24] && + !_theResult____h350508[23] && + !_theResult____h350508[22] && + !_theResult____h350508[21] && + !_theResult____h350508[20] && + !_theResult____h350508[19] && + !_theResult____h350508[18] && + !_theResult____h350508[17] && + !_theResult____h350508[16] && + !_theResult____h350508[15] && + !_theResult____h350508[14] && + !_theResult____h350508[13] && + !_theResult____h350508[12] && + !_theResult____h350508[11] && + !_theResult____h350508[10] && + !_theResult____h350508[9] && + !_theResult____h350508[8] && + !_theResult____h350508[7] && + !_theResult____h350508[6] && + !_theResult____h350508[5] && + !_theResult____h350508[4] && + !_theResult____h350508[3] && + !_theResult____h350508[2] && + !_theResult____h350508[1] && + !_theResult____h350508[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4349) ? 8'd0 : - _theResult___fst_exp__h358683 ; - assign _theResult___fst_exp__h358692 = - (!_theResult____h350507[56] && _theResult____h350507[55]) ? + _theResult___fst_exp__h358684 ; + assign _theResult___fst_exp__h358693 = + (!_theResult____h350508[56] && _theResult____h350508[55]) ? 8'd1 : - _theResult___fst_exp__h358689 ; - assign _theResult___fst_exp__h359215 = - (_theResult___fst_exp__h358618 == 8'd255) ? - _theResult___fst_exp__h358618 : - _theResult___fst_exp__h359212 ; - assign _theResult___fst_exp__h367265 = + _theResult___fst_exp__h358690 ; + assign _theResult___fst_exp__h359216 = + (_theResult___fst_exp__h358619 == 8'd255) ? + _theResult___fst_exp__h358619 : + _theResult___fst_exp__h359213 ; + assign _theResult___fst_exp__h367266 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578 } ; - assign _theResult___fst_exp__h367271 = + assign _theResult___fst_exp__h367272 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4580) ? 8'd0 : - _theResult___fst_exp__h367265 ; - assign _theResult___fst_exp__h367274 = + _theResult___fst_exp__h367266 ; + assign _theResult___fst_exp__h367275 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h367271 : + _theResult___fst_exp__h367272 : 8'd129 ; - assign _theResult___fst_exp__h367797 = - (_theResult___fst_exp__h367274 == 8'd255) ? - _theResult___fst_exp__h367274 : - _theResult___fst_exp__h367794 ; - assign _theResult___fst_exp__h376384 = - _theResult____h368146[56] ? + assign _theResult___fst_exp__h367798 = + (_theResult___fst_exp__h367275 == 8'd255) ? + _theResult___fst_exp__h367275 : + _theResult___fst_exp__h367795 ; + assign _theResult___fst_exp__h376385 = + _theResult____h368147[56] ? 8'd2 : - _theResult___fst_exp__h376458 ; - assign _theResult___fst_exp__h376449 = + _theResult___fst_exp__h376459 ; + assign _theResult___fst_exp__h376450 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4898 } ; - assign _theResult___fst_exp__h376455 = - (!_theResult____h368146[56] && !_theResult____h368146[55] && - !_theResult____h368146[54] && - !_theResult____h368146[53] && - !_theResult____h368146[52] && - !_theResult____h368146[51] && - !_theResult____h368146[50] && - !_theResult____h368146[49] && - !_theResult____h368146[48] && - !_theResult____h368146[47] && - !_theResult____h368146[46] && - !_theResult____h368146[45] && - !_theResult____h368146[44] && - !_theResult____h368146[43] && - !_theResult____h368146[42] && - !_theResult____h368146[41] && - !_theResult____h368146[40] && - !_theResult____h368146[39] && - !_theResult____h368146[38] && - !_theResult____h368146[37] && - !_theResult____h368146[36] && - !_theResult____h368146[35] && - !_theResult____h368146[34] && - !_theResult____h368146[33] && - !_theResult____h368146[32] && - !_theResult____h368146[31] && - !_theResult____h368146[30] && - !_theResult____h368146[29] && - !_theResult____h368146[28] && - !_theResult____h368146[27] && - !_theResult____h368146[26] && - !_theResult____h368146[25] && - !_theResult____h368146[24] && - !_theResult____h368146[23] && - !_theResult____h368146[22] && - !_theResult____h368146[21] && - !_theResult____h368146[20] && - !_theResult____h368146[19] && - !_theResult____h368146[18] && - !_theResult____h368146[17] && - !_theResult____h368146[16] && - !_theResult____h368146[15] && - !_theResult____h368146[14] && - !_theResult____h368146[13] && - !_theResult____h368146[12] && - !_theResult____h368146[11] && - !_theResult____h368146[10] && - !_theResult____h368146[9] && - !_theResult____h368146[8] && - !_theResult____h368146[7] && - !_theResult____h368146[6] && - !_theResult____h368146[5] && - !_theResult____h368146[4] && - !_theResult____h368146[3] && - !_theResult____h368146[2] && - !_theResult____h368146[1] && - !_theResult____h368146[0] || + assign _theResult___fst_exp__h376456 = + (!_theResult____h368147[56] && !_theResult____h368147[55] && + !_theResult____h368147[54] && + !_theResult____h368147[53] && + !_theResult____h368147[52] && + !_theResult____h368147[51] && + !_theResult____h368147[50] && + !_theResult____h368147[49] && + !_theResult____h368147[48] && + !_theResult____h368147[47] && + !_theResult____h368147[46] && + !_theResult____h368147[45] && + !_theResult____h368147[44] && + !_theResult____h368147[43] && + !_theResult____h368147[42] && + !_theResult____h368147[41] && + !_theResult____h368147[40] && + !_theResult____h368147[39] && + !_theResult____h368147[38] && + !_theResult____h368147[37] && + !_theResult____h368147[36] && + !_theResult____h368147[35] && + !_theResult____h368147[34] && + !_theResult____h368147[33] && + !_theResult____h368147[32] && + !_theResult____h368147[31] && + !_theResult____h368147[30] && + !_theResult____h368147[29] && + !_theResult____h368147[28] && + !_theResult____h368147[27] && + !_theResult____h368147[26] && + !_theResult____h368147[25] && + !_theResult____h368147[24] && + !_theResult____h368147[23] && + !_theResult____h368147[22] && + !_theResult____h368147[21] && + !_theResult____h368147[20] && + !_theResult____h368147[19] && + !_theResult____h368147[18] && + !_theResult____h368147[17] && + !_theResult____h368147[16] && + !_theResult____h368147[15] && + !_theResult____h368147[14] && + !_theResult____h368147[13] && + !_theResult____h368147[12] && + !_theResult____h368147[11] && + !_theResult____h368147[10] && + !_theResult____h368147[9] && + !_theResult____h368147[8] && + !_theResult____h368147[7] && + !_theResult____h368147[6] && + !_theResult____h368147[5] && + !_theResult____h368147[4] && + !_theResult____h368147[3] && + !_theResult____h368147[2] && + !_theResult____h368147[1] && + !_theResult____h368147[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4900) ? 8'd0 : - _theResult___fst_exp__h376449 ; - assign _theResult___fst_exp__h376458 = - (!_theResult____h368146[56] && _theResult____h368146[55]) ? + _theResult___fst_exp__h376450 ; + assign _theResult___fst_exp__h376459 = + (!_theResult____h368147[56] && _theResult____h368147[55]) ? 8'd1 : - _theResult___fst_exp__h376455 ; - assign _theResult___fst_exp__h376981 = - (_theResult___fst_exp__h376384 == 8'd255) ? - _theResult___fst_exp__h376384 : - _theResult___fst_exp__h376978 ; - assign _theResult___fst_exp__h385021 = + _theResult___fst_exp__h376456 ; + assign _theResult___fst_exp__h376982 = + (_theResult___fst_exp__h376385 == 8'd255) ? + _theResult___fst_exp__h376385 : + _theResult___fst_exp__h376979 ; + assign _theResult___fst_exp__h385022 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] ; - assign _theResult___fst_exp__h385060 = + assign _theResult___fst_exp__h385061 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q38[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578 } ; - assign _theResult___fst_exp__h385066 = + assign _theResult___fst_exp__h385067 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4973) ? 8'd0 : - _theResult___fst_exp__h385060 ; - assign _theResult___fst_exp__h385069 = + _theResult___fst_exp__h385061 ; + assign _theResult___fst_exp__h385070 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h385066 : - _theResult___fst_exp__h385021 ; - assign _theResult___fst_exp__h385617 = - (_theResult___fst_exp__h385069 == 8'd255) ? - _theResult___fst_exp__h385069 : - _theResult___fst_exp__h385614 ; - assign _theResult___fst_exp__h385626 = + _theResult___fst_exp__h385067 : + _theResult___fst_exp__h385022 ; + assign _theResult___fst_exp__h385618 = + (_theResult___fst_exp__h385070 == 8'd255) ? + _theResult___fst_exp__h385070 : + _theResult___fst_exp__h385615 ; + assign _theResult___fst_exp__h385627 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112 ? - _theResult___snd_fst_exp__h367800 : - _theResult___fst_exp__h350489) : + _theResult___snd_fst_exp__h367801 : + _theResult___fst_exp__h350490) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4652 ? - _theResult___snd_fst_exp__h385620 : - _theResult___fst_exp__h350489) ; - assign _theResult___fst_exp__h385629 = + _theResult___snd_fst_exp__h385621 : + _theResult___fst_exp__h350490) ; + assign _theResult___fst_exp__h385630 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h385626 ; - assign _theResult___fst_exp__h404315 = - _theResult____h396206[56] ? + _theResult___fst_exp__h385627 ; + assign _theResult___fst_exp__h404316 = + _theResult____h396207[56] ? 8'd2 : - _theResult___fst_exp__h404389 ; - assign _theResult___fst_exp__h404380 = + _theResult___fst_exp__h404390 ; + assign _theResult___fst_exp__h404381 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 } ; - assign _theResult___fst_exp__h404386 = - (!_theResult____h396206[56] && !_theResult____h396206[55] && - !_theResult____h396206[54] && - !_theResult____h396206[53] && - !_theResult____h396206[52] && - !_theResult____h396206[51] && - !_theResult____h396206[50] && - !_theResult____h396206[49] && - !_theResult____h396206[48] && - !_theResult____h396206[47] && - !_theResult____h396206[46] && - !_theResult____h396206[45] && - !_theResult____h396206[44] && - !_theResult____h396206[43] && - !_theResult____h396206[42] && - !_theResult____h396206[41] && - !_theResult____h396206[40] && - !_theResult____h396206[39] && - !_theResult____h396206[38] && - !_theResult____h396206[37] && - !_theResult____h396206[36] && - !_theResult____h396206[35] && - !_theResult____h396206[34] && - !_theResult____h396206[33] && - !_theResult____h396206[32] && - !_theResult____h396206[31] && - !_theResult____h396206[30] && - !_theResult____h396206[29] && - !_theResult____h396206[28] && - !_theResult____h396206[27] && - !_theResult____h396206[26] && - !_theResult____h396206[25] && - !_theResult____h396206[24] && - !_theResult____h396206[23] && - !_theResult____h396206[22] && - !_theResult____h396206[21] && - !_theResult____h396206[20] && - !_theResult____h396206[19] && - !_theResult____h396206[18] && - !_theResult____h396206[17] && - !_theResult____h396206[16] && - !_theResult____h396206[15] && - !_theResult____h396206[14] && - !_theResult____h396206[13] && - !_theResult____h396206[12] && - !_theResult____h396206[11] && - !_theResult____h396206[10] && - !_theResult____h396206[9] && - !_theResult____h396206[8] && - !_theResult____h396206[7] && - !_theResult____h396206[6] && - !_theResult____h396206[5] && - !_theResult____h396206[4] && - !_theResult____h396206[3] && - !_theResult____h396206[2] && - !_theResult____h396206[1] && - !_theResult____h396206[0] || + assign _theResult___fst_exp__h404387 = + (!_theResult____h396207[56] && !_theResult____h396207[55] && + !_theResult____h396207[54] && + !_theResult____h396207[53] && + !_theResult____h396207[52] && + !_theResult____h396207[51] && + !_theResult____h396207[50] && + !_theResult____h396207[49] && + !_theResult____h396207[48] && + !_theResult____h396207[47] && + !_theResult____h396207[46] && + !_theResult____h396207[45] && + !_theResult____h396207[44] && + !_theResult____h396207[43] && + !_theResult____h396207[42] && + !_theResult____h396207[41] && + !_theResult____h396207[40] && + !_theResult____h396207[39] && + !_theResult____h396207[38] && + !_theResult____h396207[37] && + !_theResult____h396207[36] && + !_theResult____h396207[35] && + !_theResult____h396207[34] && + !_theResult____h396207[33] && + !_theResult____h396207[32] && + !_theResult____h396207[31] && + !_theResult____h396207[30] && + !_theResult____h396207[29] && + !_theResult____h396207[28] && + !_theResult____h396207[27] && + !_theResult____h396207[26] && + !_theResult____h396207[25] && + !_theResult____h396207[24] && + !_theResult____h396207[23] && + !_theResult____h396207[22] && + !_theResult____h396207[21] && + !_theResult____h396207[20] && + !_theResult____h396207[19] && + !_theResult____h396207[18] && + !_theResult____h396207[17] && + !_theResult____h396207[16] && + !_theResult____h396207[15] && + !_theResult____h396207[14] && + !_theResult____h396207[13] && + !_theResult____h396207[12] && + !_theResult____h396207[11] && + !_theResult____h396207[10] && + !_theResult____h396207[9] && + !_theResult____h396207[8] && + !_theResult____h396207[7] && + !_theResult____h396207[6] && + !_theResult____h396207[5] && + !_theResult____h396207[4] && + !_theResult____h396207[3] && + !_theResult____h396207[2] && + !_theResult____h396207[1] && + !_theResult____h396207[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5741) ? 8'd0 : - _theResult___fst_exp__h404380 ; - assign _theResult___fst_exp__h404389 = - (!_theResult____h396206[56] && _theResult____h396206[55]) ? + _theResult___fst_exp__h404381 ; + assign _theResult___fst_exp__h404390 = + (!_theResult____h396207[56] && _theResult____h396207[55]) ? 8'd1 : - _theResult___fst_exp__h404386 ; - assign _theResult___fst_exp__h404912 = - (_theResult___fst_exp__h404315 == 8'd255) ? - _theResult___fst_exp__h404315 : - _theResult___fst_exp__h404909 ; - assign _theResult___fst_exp__h412962 = + _theResult___fst_exp__h404387 ; + assign _theResult___fst_exp__h404913 = + (_theResult___fst_exp__h404316 == 8'd255) ? + _theResult___fst_exp__h404316 : + _theResult___fst_exp__h404910 ; + assign _theResult___fst_exp__h412963 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 } ; - assign _theResult___fst_exp__h412968 = + assign _theResult___fst_exp__h412969 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5972) ? 8'd0 : - _theResult___fst_exp__h412962 ; - assign _theResult___fst_exp__h412971 = + _theResult___fst_exp__h412963 ; + assign _theResult___fst_exp__h412972 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h412968 : + _theResult___fst_exp__h412969 : 8'd129 ; - assign _theResult___fst_exp__h413494 = - (_theResult___fst_exp__h412971 == 8'd255) ? - _theResult___fst_exp__h412971 : - _theResult___fst_exp__h413491 ; - assign _theResult___fst_exp__h422081 = - _theResult____h413843[56] ? + assign _theResult___fst_exp__h413495 = + (_theResult___fst_exp__h412972 == 8'd255) ? + _theResult___fst_exp__h412972 : + _theResult___fst_exp__h413492 ; + assign _theResult___fst_exp__h422082 = + _theResult____h413844[56] ? 8'd2 : - _theResult___fst_exp__h422155 ; - assign _theResult___fst_exp__h422146 = + _theResult___fst_exp__h422156 ; + assign _theResult___fst_exp__h422147 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 } ; - assign _theResult___fst_exp__h422152 = - (!_theResult____h413843[56] && !_theResult____h413843[55] && - !_theResult____h413843[54] && - !_theResult____h413843[53] && - !_theResult____h413843[52] && - !_theResult____h413843[51] && - !_theResult____h413843[50] && - !_theResult____h413843[49] && - !_theResult____h413843[48] && - !_theResult____h413843[47] && - !_theResult____h413843[46] && - !_theResult____h413843[45] && - !_theResult____h413843[44] && - !_theResult____h413843[43] && - !_theResult____h413843[42] && - !_theResult____h413843[41] && - !_theResult____h413843[40] && - !_theResult____h413843[39] && - !_theResult____h413843[38] && - !_theResult____h413843[37] && - !_theResult____h413843[36] && - !_theResult____h413843[35] && - !_theResult____h413843[34] && - !_theResult____h413843[33] && - !_theResult____h413843[32] && - !_theResult____h413843[31] && - !_theResult____h413843[30] && - !_theResult____h413843[29] && - !_theResult____h413843[28] && - !_theResult____h413843[27] && - !_theResult____h413843[26] && - !_theResult____h413843[25] && - !_theResult____h413843[24] && - !_theResult____h413843[23] && - !_theResult____h413843[22] && - !_theResult____h413843[21] && - !_theResult____h413843[20] && - !_theResult____h413843[19] && - !_theResult____h413843[18] && - !_theResult____h413843[17] && - !_theResult____h413843[16] && - !_theResult____h413843[15] && - !_theResult____h413843[14] && - !_theResult____h413843[13] && - !_theResult____h413843[12] && - !_theResult____h413843[11] && - !_theResult____h413843[10] && - !_theResult____h413843[9] && - !_theResult____h413843[8] && - !_theResult____h413843[7] && - !_theResult____h413843[6] && - !_theResult____h413843[5] && - !_theResult____h413843[4] && - !_theResult____h413843[3] && - !_theResult____h413843[2] && - !_theResult____h413843[1] && - !_theResult____h413843[0] || + assign _theResult___fst_exp__h422153 = + (!_theResult____h413844[56] && !_theResult____h413844[55] && + !_theResult____h413844[54] && + !_theResult____h413844[53] && + !_theResult____h413844[52] && + !_theResult____h413844[51] && + !_theResult____h413844[50] && + !_theResult____h413844[49] && + !_theResult____h413844[48] && + !_theResult____h413844[47] && + !_theResult____h413844[46] && + !_theResult____h413844[45] && + !_theResult____h413844[44] && + !_theResult____h413844[43] && + !_theResult____h413844[42] && + !_theResult____h413844[41] && + !_theResult____h413844[40] && + !_theResult____h413844[39] && + !_theResult____h413844[38] && + !_theResult____h413844[37] && + !_theResult____h413844[36] && + !_theResult____h413844[35] && + !_theResult____h413844[34] && + !_theResult____h413844[33] && + !_theResult____h413844[32] && + !_theResult____h413844[31] && + !_theResult____h413844[30] && + !_theResult____h413844[29] && + !_theResult____h413844[28] && + !_theResult____h413844[27] && + !_theResult____h413844[26] && + !_theResult____h413844[25] && + !_theResult____h413844[24] && + !_theResult____h413844[23] && + !_theResult____h413844[22] && + !_theResult____h413844[21] && + !_theResult____h413844[20] && + !_theResult____h413844[19] && + !_theResult____h413844[18] && + !_theResult____h413844[17] && + !_theResult____h413844[16] && + !_theResult____h413844[15] && + !_theResult____h413844[14] && + !_theResult____h413844[13] && + !_theResult____h413844[12] && + !_theResult____h413844[11] && + !_theResult____h413844[10] && + !_theResult____h413844[9] && + !_theResult____h413844[8] && + !_theResult____h413844[7] && + !_theResult____h413844[6] && + !_theResult____h413844[5] && + !_theResult____h413844[4] && + !_theResult____h413844[3] && + !_theResult____h413844[2] && + !_theResult____h413844[1] && + !_theResult____h413844[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6292) ? 8'd0 : - _theResult___fst_exp__h422146 ; - assign _theResult___fst_exp__h422155 = - (!_theResult____h413843[56] && _theResult____h413843[55]) ? + _theResult___fst_exp__h422147 ; + assign _theResult___fst_exp__h422156 = + (!_theResult____h413844[56] && _theResult____h413844[55]) ? 8'd1 : - _theResult___fst_exp__h422152 ; - assign _theResult___fst_exp__h422678 = - (_theResult___fst_exp__h422081 == 8'd255) ? - _theResult___fst_exp__h422081 : - _theResult___fst_exp__h422675 ; - assign _theResult___fst_exp__h430718 = + _theResult___fst_exp__h422153 ; + assign _theResult___fst_exp__h422679 = + (_theResult___fst_exp__h422082 == 8'd255) ? + _theResult___fst_exp__h422082 : + _theResult___fst_exp__h422676 ; + assign _theResult___fst_exp__h430719 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] ; - assign _theResult___fst_exp__h430757 = + assign _theResult___fst_exp__h430758 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q73[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 } ; - assign _theResult___fst_exp__h430763 = + assign _theResult___fst_exp__h430764 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6365) ? 8'd0 : - _theResult___fst_exp__h430757 ; - assign _theResult___fst_exp__h430766 = + _theResult___fst_exp__h430758 ; + assign _theResult___fst_exp__h430767 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h430763 : - _theResult___fst_exp__h430718 ; - assign _theResult___fst_exp__h431314 = - (_theResult___fst_exp__h430766 == 8'd255) ? - _theResult___fst_exp__h430766 : - _theResult___fst_exp__h431311 ; - assign _theResult___fst_exp__h431323 = + _theResult___fst_exp__h430764 : + _theResult___fst_exp__h430719 ; + assign _theResult___fst_exp__h431315 = + (_theResult___fst_exp__h430767 == 8'd255) ? + _theResult___fst_exp__h430767 : + _theResult___fst_exp__h431312 ; + assign _theResult___fst_exp__h431324 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5504 ? - _theResult___snd_fst_exp__h413497 : - _theResult___fst_exp__h396188) : + _theResult___snd_fst_exp__h413498 : + _theResult___fst_exp__h396189) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6044 ? - _theResult___snd_fst_exp__h431317 : - _theResult___fst_exp__h396188) ; - assign _theResult___fst_exp__h431326 = + _theResult___snd_fst_exp__h431318 : + _theResult___fst_exp__h396189) ; + assign _theResult___fst_exp__h431327 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h431323 ; - assign _theResult___fst_exp__h450010 = - _theResult____h441901[56] ? + _theResult___fst_exp__h431324 ; + assign _theResult___fst_exp__h450011 = + _theResult____h441902[56] ? 8'd2 : - _theResult___fst_exp__h450084 ; - assign _theResult___fst_exp__h450075 = + _theResult___fst_exp__h450085 ; + assign _theResult___fst_exp__h450076 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 } ; - assign _theResult___fst_exp__h450081 = - (!_theResult____h441901[56] && !_theResult____h441901[55] && - !_theResult____h441901[54] && - !_theResult____h441901[53] && - !_theResult____h441901[52] && - !_theResult____h441901[51] && - !_theResult____h441901[50] && - !_theResult____h441901[49] && - !_theResult____h441901[48] && - !_theResult____h441901[47] && - !_theResult____h441901[46] && - !_theResult____h441901[45] && - !_theResult____h441901[44] && - !_theResult____h441901[43] && - !_theResult____h441901[42] && - !_theResult____h441901[41] && - !_theResult____h441901[40] && - !_theResult____h441901[39] && - !_theResult____h441901[38] && - !_theResult____h441901[37] && - !_theResult____h441901[36] && - !_theResult____h441901[35] && - !_theResult____h441901[34] && - !_theResult____h441901[33] && - !_theResult____h441901[32] && - !_theResult____h441901[31] && - !_theResult____h441901[30] && - !_theResult____h441901[29] && - !_theResult____h441901[28] && - !_theResult____h441901[27] && - !_theResult____h441901[26] && - !_theResult____h441901[25] && - !_theResult____h441901[24] && - !_theResult____h441901[23] && - !_theResult____h441901[22] && - !_theResult____h441901[21] && - !_theResult____h441901[20] && - !_theResult____h441901[19] && - !_theResult____h441901[18] && - !_theResult____h441901[17] && - !_theResult____h441901[16] && - !_theResult____h441901[15] && - !_theResult____h441901[14] && - !_theResult____h441901[13] && - !_theResult____h441901[12] && - !_theResult____h441901[11] && - !_theResult____h441901[10] && - !_theResult____h441901[9] && - !_theResult____h441901[8] && - !_theResult____h441901[7] && - !_theResult____h441901[6] && - !_theResult____h441901[5] && - !_theResult____h441901[4] && - !_theResult____h441901[3] && - !_theResult____h441901[2] && - !_theResult____h441901[1] && - !_theResult____h441901[0] || + assign _theResult___fst_exp__h450082 = + (!_theResult____h441902[56] && !_theResult____h441902[55] && + !_theResult____h441902[54] && + !_theResult____h441902[53] && + !_theResult____h441902[52] && + !_theResult____h441902[51] && + !_theResult____h441902[50] && + !_theResult____h441902[49] && + !_theResult____h441902[48] && + !_theResult____h441902[47] && + !_theResult____h441902[46] && + !_theResult____h441902[45] && + !_theResult____h441902[44] && + !_theResult____h441902[43] && + !_theResult____h441902[42] && + !_theResult____h441902[41] && + !_theResult____h441902[40] && + !_theResult____h441902[39] && + !_theResult____h441902[38] && + !_theResult____h441902[37] && + !_theResult____h441902[36] && + !_theResult____h441902[35] && + !_theResult____h441902[34] && + !_theResult____h441902[33] && + !_theResult____h441902[32] && + !_theResult____h441902[31] && + !_theResult____h441902[30] && + !_theResult____h441902[29] && + !_theResult____h441902[28] && + !_theResult____h441902[27] && + !_theResult____h441902[26] && + !_theResult____h441902[25] && + !_theResult____h441902[24] && + !_theResult____h441902[23] && + !_theResult____h441902[22] && + !_theResult____h441902[21] && + !_theResult____h441902[20] && + !_theResult____h441902[19] && + !_theResult____h441902[18] && + !_theResult____h441902[17] && + !_theResult____h441902[16] && + !_theResult____h441902[15] && + !_theResult____h441902[14] && + !_theResult____h441902[13] && + !_theResult____h441902[12] && + !_theResult____h441902[11] && + !_theResult____h441902[10] && + !_theResult____h441902[9] && + !_theResult____h441902[8] && + !_theResult____h441902[7] && + !_theResult____h441902[6] && + !_theResult____h441902[5] && + !_theResult____h441902[4] && + !_theResult____h441902[3] && + !_theResult____h441902[2] && + !_theResult____h441902[1] && + !_theResult____h441902[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7133) ? 8'd0 : - _theResult___fst_exp__h450075 ; - assign _theResult___fst_exp__h450084 = - (!_theResult____h441901[56] && _theResult____h441901[55]) ? + _theResult___fst_exp__h450076 ; + assign _theResult___fst_exp__h450085 = + (!_theResult____h441902[56] && _theResult____h441902[55]) ? 8'd1 : - _theResult___fst_exp__h450081 ; - assign _theResult___fst_exp__h450607 = - (_theResult___fst_exp__h450010 == 8'd255) ? - _theResult___fst_exp__h450010 : - _theResult___fst_exp__h450604 ; - assign _theResult___fst_exp__h458657 = + _theResult___fst_exp__h450082 ; + assign _theResult___fst_exp__h450608 = + (_theResult___fst_exp__h450011 == 8'd255) ? + _theResult___fst_exp__h450011 : + _theResult___fst_exp__h450605 ; + assign _theResult___fst_exp__h458658 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 } ; - assign _theResult___fst_exp__h458663 = + assign _theResult___fst_exp__h458664 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7364) ? 8'd0 : - _theResult___fst_exp__h458657 ; - assign _theResult___fst_exp__h458666 = + _theResult___fst_exp__h458658 ; + assign _theResult___fst_exp__h458667 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h458663 : + _theResult___fst_exp__h458664 : 8'd129 ; - assign _theResult___fst_exp__h459189 = - (_theResult___fst_exp__h458666 == 8'd255) ? - _theResult___fst_exp__h458666 : - _theResult___fst_exp__h459186 ; - assign _theResult___fst_exp__h467776 = - _theResult____h459538[56] ? + assign _theResult___fst_exp__h459190 = + (_theResult___fst_exp__h458667 == 8'd255) ? + _theResult___fst_exp__h458667 : + _theResult___fst_exp__h459187 ; + assign _theResult___fst_exp__h467777 = + _theResult____h459539[56] ? 8'd2 : - _theResult___fst_exp__h467850 ; - assign _theResult___fst_exp__h467841 = + _theResult___fst_exp__h467851 ; + assign _theResult___fst_exp__h467842 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 } ; - assign _theResult___fst_exp__h467847 = - (!_theResult____h459538[56] && !_theResult____h459538[55] && - !_theResult____h459538[54] && - !_theResult____h459538[53] && - !_theResult____h459538[52] && - !_theResult____h459538[51] && - !_theResult____h459538[50] && - !_theResult____h459538[49] && - !_theResult____h459538[48] && - !_theResult____h459538[47] && - !_theResult____h459538[46] && - !_theResult____h459538[45] && - !_theResult____h459538[44] && - !_theResult____h459538[43] && - !_theResult____h459538[42] && - !_theResult____h459538[41] && - !_theResult____h459538[40] && - !_theResult____h459538[39] && - !_theResult____h459538[38] && - !_theResult____h459538[37] && - !_theResult____h459538[36] && - !_theResult____h459538[35] && - !_theResult____h459538[34] && - !_theResult____h459538[33] && - !_theResult____h459538[32] && - !_theResult____h459538[31] && - !_theResult____h459538[30] && - !_theResult____h459538[29] && - !_theResult____h459538[28] && - !_theResult____h459538[27] && - !_theResult____h459538[26] && - !_theResult____h459538[25] && - !_theResult____h459538[24] && - !_theResult____h459538[23] && - !_theResult____h459538[22] && - !_theResult____h459538[21] && - !_theResult____h459538[20] && - !_theResult____h459538[19] && - !_theResult____h459538[18] && - !_theResult____h459538[17] && - !_theResult____h459538[16] && - !_theResult____h459538[15] && - !_theResult____h459538[14] && - !_theResult____h459538[13] && - !_theResult____h459538[12] && - !_theResult____h459538[11] && - !_theResult____h459538[10] && - !_theResult____h459538[9] && - !_theResult____h459538[8] && - !_theResult____h459538[7] && - !_theResult____h459538[6] && - !_theResult____h459538[5] && - !_theResult____h459538[4] && - !_theResult____h459538[3] && - !_theResult____h459538[2] && - !_theResult____h459538[1] && - !_theResult____h459538[0] || + assign _theResult___fst_exp__h467848 = + (!_theResult____h459539[56] && !_theResult____h459539[55] && + !_theResult____h459539[54] && + !_theResult____h459539[53] && + !_theResult____h459539[52] && + !_theResult____h459539[51] && + !_theResult____h459539[50] && + !_theResult____h459539[49] && + !_theResult____h459539[48] && + !_theResult____h459539[47] && + !_theResult____h459539[46] && + !_theResult____h459539[45] && + !_theResult____h459539[44] && + !_theResult____h459539[43] && + !_theResult____h459539[42] && + !_theResult____h459539[41] && + !_theResult____h459539[40] && + !_theResult____h459539[39] && + !_theResult____h459539[38] && + !_theResult____h459539[37] && + !_theResult____h459539[36] && + !_theResult____h459539[35] && + !_theResult____h459539[34] && + !_theResult____h459539[33] && + !_theResult____h459539[32] && + !_theResult____h459539[31] && + !_theResult____h459539[30] && + !_theResult____h459539[29] && + !_theResult____h459539[28] && + !_theResult____h459539[27] && + !_theResult____h459539[26] && + !_theResult____h459539[25] && + !_theResult____h459539[24] && + !_theResult____h459539[23] && + !_theResult____h459539[22] && + !_theResult____h459539[21] && + !_theResult____h459539[20] && + !_theResult____h459539[19] && + !_theResult____h459539[18] && + !_theResult____h459539[17] && + !_theResult____h459539[16] && + !_theResult____h459539[15] && + !_theResult____h459539[14] && + !_theResult____h459539[13] && + !_theResult____h459539[12] && + !_theResult____h459539[11] && + !_theResult____h459539[10] && + !_theResult____h459539[9] && + !_theResult____h459539[8] && + !_theResult____h459539[7] && + !_theResult____h459539[6] && + !_theResult____h459539[5] && + !_theResult____h459539[4] && + !_theResult____h459539[3] && + !_theResult____h459539[2] && + !_theResult____h459539[1] && + !_theResult____h459539[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7684) ? 8'd0 : - _theResult___fst_exp__h467841 ; - assign _theResult___fst_exp__h467850 = - (!_theResult____h459538[56] && _theResult____h459538[55]) ? + _theResult___fst_exp__h467842 ; + assign _theResult___fst_exp__h467851 = + (!_theResult____h459539[56] && _theResult____h459539[55]) ? 8'd1 : - _theResult___fst_exp__h467847 ; - assign _theResult___fst_exp__h468373 = - (_theResult___fst_exp__h467776 == 8'd255) ? - _theResult___fst_exp__h467776 : - _theResult___fst_exp__h468370 ; - assign _theResult___fst_exp__h476413 = + _theResult___fst_exp__h467848 ; + assign _theResult___fst_exp__h468374 = + (_theResult___fst_exp__h467777 == 8'd255) ? + _theResult___fst_exp__h467777 : + _theResult___fst_exp__h468371 ; + assign _theResult___fst_exp__h476414 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] ; - assign _theResult___fst_exp__h476452 = + assign _theResult___fst_exp__h476453 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q108[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 } ; - assign _theResult___fst_exp__h476458 = + assign _theResult___fst_exp__h476459 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7757) ? 8'd0 : - _theResult___fst_exp__h476452 ; - assign _theResult___fst_exp__h476461 = + _theResult___fst_exp__h476453 ; + assign _theResult___fst_exp__h476462 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h476458 : - _theResult___fst_exp__h476413 ; - assign _theResult___fst_exp__h477009 = - (_theResult___fst_exp__h476461 == 8'd255) ? - _theResult___fst_exp__h476461 : - _theResult___fst_exp__h477006 ; - assign _theResult___fst_exp__h477018 = + _theResult___fst_exp__h476459 : + _theResult___fst_exp__h476414 ; + assign _theResult___fst_exp__h477010 = + (_theResult___fst_exp__h476462 == 8'd255) ? + _theResult___fst_exp__h476462 : + _theResult___fst_exp__h477007 ; + assign _theResult___fst_exp__h477019 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6896 ? - _theResult___snd_fst_exp__h459192 : - _theResult___fst_exp__h441883) : + _theResult___snd_fst_exp__h459193 : + _theResult___fst_exp__h441884) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7436 ? - _theResult___snd_fst_exp__h477012 : - _theResult___fst_exp__h441883) ; - assign _theResult___fst_exp__h477021 = + _theResult___snd_fst_exp__h477013 : + _theResult___fst_exp__h441884) ; + assign _theResult___fst_exp__h477022 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h477018 ; - assign _theResult___fst_exp__h491385 = + _theResult___fst_exp__h477019 ; + assign _theResult___fst_exp__h491386 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_exp__h506449 = + assign _theResult___fst_exp__h506450 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 } ; - assign _theResult___fst_exp__h506455 = - (f1_exp__h487070 == 8'd0 && !f1_sfd__h487071[22] && + assign _theResult___fst_exp__h506456 = + (f1_exp__h487071 == 8'd0 && !f1_sfd__h487072[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8700) ? 11'd0 : - _theResult___fst_exp__h506449 ; - assign _theResult___fst_exp__h506458 = - (f1_exp__h487070 == 8'd0) ? - _theResult___fst_exp__h506455 : + _theResult___fst_exp__h506450 ; + assign _theResult___fst_exp__h506459 = + (f1_exp__h487071 == 8'd0) ? + _theResult___fst_exp__h506456 : 11'd897 ; - assign _theResult___fst_exp__h507213 = + assign _theResult___fst_exp__h507214 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q144 : + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q144 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 ; - assign _theResult___fst_exp__h507216 = - (_theResult___fst_exp__h506458 == 11'd2047) ? - _theResult___fst_exp__h506458 : - _theResult___fst_exp__h507213 ; - assign _theResult___fst_exp__h516035 = - _theResult____h507799[56] ? + assign _theResult___fst_exp__h507217 = + (_theResult___fst_exp__h506459 == 11'd2047) ? + _theResult___fst_exp__h506459 : + _theResult___fst_exp__h507214 ; + assign _theResult___fst_exp__h516036 = + _theResult____h507800[56] ? 11'd2 : - _theResult___fst_exp__h516109 ; - assign _theResult___fst_exp__h516100 = + _theResult___fst_exp__h516110 ; + assign _theResult___fst_exp__h516101 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 } ; - assign _theResult___fst_exp__h516106 = - (!_theResult____h507799[56] && !_theResult____h507799[55] && - !_theResult____h507799[54] && - !_theResult____h507799[53] && - !_theResult____h507799[52] && - !_theResult____h507799[51] && - !_theResult____h507799[50] && - !_theResult____h507799[49] && - !_theResult____h507799[48] && - !_theResult____h507799[47] && - !_theResult____h507799[46] && - !_theResult____h507799[45] && - !_theResult____h507799[44] && - !_theResult____h507799[43] && - !_theResult____h507799[42] && - !_theResult____h507799[41] && - !_theResult____h507799[40] && - !_theResult____h507799[39] && - !_theResult____h507799[38] && - !_theResult____h507799[37] && - !_theResult____h507799[36] && - !_theResult____h507799[35] && - !_theResult____h507799[34] && - !_theResult____h507799[33] && - !_theResult____h507799[32] && - !_theResult____h507799[31] && - !_theResult____h507799[30] && - !_theResult____h507799[29] && - !_theResult____h507799[28] && - !_theResult____h507799[27] && - !_theResult____h507799[26] && - !_theResult____h507799[25] && - !_theResult____h507799[24] && - !_theResult____h507799[23] && - !_theResult____h507799[22] && - !_theResult____h507799[21] && - !_theResult____h507799[20] && - !_theResult____h507799[19] && - !_theResult____h507799[18] && - !_theResult____h507799[17] && - !_theResult____h507799[16] && - !_theResult____h507799[15] && - !_theResult____h507799[14] && - !_theResult____h507799[13] && - !_theResult____h507799[12] && - !_theResult____h507799[11] && - !_theResult____h507799[10] && - !_theResult____h507799[9] && - !_theResult____h507799[8] && - !_theResult____h507799[7] && - !_theResult____h507799[6] && - !_theResult____h507799[5] && - !_theResult____h507799[4] && - !_theResult____h507799[3] && - !_theResult____h507799[2] && - !_theResult____h507799[1] && - !_theResult____h507799[0] || + assign _theResult___fst_exp__h516107 = + (!_theResult____h507800[56] && !_theResult____h507800[55] && + !_theResult____h507800[54] && + !_theResult____h507800[53] && + !_theResult____h507800[52] && + !_theResult____h507800[51] && + !_theResult____h507800[50] && + !_theResult____h507800[49] && + !_theResult____h507800[48] && + !_theResult____h507800[47] && + !_theResult____h507800[46] && + !_theResult____h507800[45] && + !_theResult____h507800[44] && + !_theResult____h507800[43] && + !_theResult____h507800[42] && + !_theResult____h507800[41] && + !_theResult____h507800[40] && + !_theResult____h507800[39] && + !_theResult____h507800[38] && + !_theResult____h507800[37] && + !_theResult____h507800[36] && + !_theResult____h507800[35] && + !_theResult____h507800[34] && + !_theResult____h507800[33] && + !_theResult____h507800[32] && + !_theResult____h507800[31] && + !_theResult____h507800[30] && + !_theResult____h507800[29] && + !_theResult____h507800[28] && + !_theResult____h507800[27] && + !_theResult____h507800[26] && + !_theResult____h507800[25] && + !_theResult____h507800[24] && + !_theResult____h507800[23] && + !_theResult____h507800[22] && + !_theResult____h507800[21] && + !_theResult____h507800[20] && + !_theResult____h507800[19] && + !_theResult____h507800[18] && + !_theResult____h507800[17] && + !_theResult____h507800[16] && + !_theResult____h507800[15] && + !_theResult____h507800[14] && + !_theResult____h507800[13] && + !_theResult____h507800[12] && + !_theResult____h507800[11] && + !_theResult____h507800[10] && + !_theResult____h507800[9] && + !_theResult____h507800[8] && + !_theResult____h507800[7] && + !_theResult____h507800[6] && + !_theResult____h507800[5] && + !_theResult____h507800[4] && + !_theResult____h507800[3] && + !_theResult____h507800[2] && + !_theResult____h507800[1] && + !_theResult____h507800[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9012) ? 11'd0 : - _theResult___fst_exp__h516100 ; - assign _theResult___fst_exp__h516109 = - (!_theResult____h507799[56] && _theResult____h507799[55]) ? + _theResult___fst_exp__h516101 ; + assign _theResult___fst_exp__h516110 = + (!_theResult____h507800[56] && _theResult____h507800[55]) ? 11'd1 : - _theResult___fst_exp__h516106 ; - assign _theResult___fst_exp__h516864 = + _theResult___fst_exp__h516107 ; + assign _theResult___fst_exp__h516865 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q212 : + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 ; - assign _theResult___fst_exp__h516867 = - (_theResult___fst_exp__h516035 == 11'd2047) ? - _theResult___fst_exp__h516035 : - _theResult___fst_exp__h516864 ; - assign _theResult___fst_exp__h524820 = + assign _theResult___fst_exp__h516868 = + (_theResult___fst_exp__h516036 == 11'd2047) ? + _theResult___fst_exp__h516036 : + _theResult___fst_exp__h516865 ; + assign _theResult___fst_exp__h524821 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h524859 = + assign _theResult___fst_exp__h524860 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 } ; - assign _theResult___fst_exp__h524865 = - (f1_exp__h487070 == 8'd0 && !f1_sfd__h487071[22] && + assign _theResult___fst_exp__h524866 = + (f1_exp__h487071 == 8'd0 && !f1_sfd__h487072[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9062) ? 11'd0 : - _theResult___fst_exp__h524859 ; - assign _theResult___fst_exp__h524868 = - (f1_exp__h487070 == 8'd0) ? - _theResult___fst_exp__h524865 : - _theResult___fst_exp__h524820 ; - assign _theResult___fst_exp__h525648 = + _theResult___fst_exp__h524860 ; + assign _theResult___fst_exp__h524869 = + (f1_exp__h487071 == 8'd0) ? + _theResult___fst_exp__h524866 : + _theResult___fst_exp__h524821 ; + assign _theResult___fst_exp__h525649 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q214 : + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 ; - assign _theResult___fst_exp__h525651 = - (_theResult___fst_exp__h524868 == 11'd2047) ? - _theResult___fst_exp__h524868 : - _theResult___fst_exp__h525648 ; - assign _theResult___fst_exp__h525660 = - (f1_exp__h487070 == 8'd0) ? + assign _theResult___fst_exp__h525652 = + (_theResult___fst_exp__h524869 == 11'd2047) ? + _theResult___fst_exp__h524869 : + _theResult___fst_exp__h525649 ; + assign _theResult___fst_exp__h525661 = + (f1_exp__h487071 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 ? - _theResult___snd_fst_exp__h507219 : - _theResult___fst_exp__h491385) : + _theResult___snd_fst_exp__h507220 : + _theResult___fst_exp__h491386) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 ? - _theResult___snd_fst_exp__h525654 : - _theResult___fst_exp__h491385) ; - assign _theResult___fst_exp__h525663 = - (f1_exp__h487070 == 8'd0 && f1_sfd__h487071 == 23'd0) ? + _theResult___snd_fst_exp__h525655 : + _theResult___fst_exp__h491386) ; + assign _theResult___fst_exp__h525664 = + (f1_exp__h487071 == 8'd0 && f1_sfd__h487072 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h525660 ; - assign _theResult___fst_exp__h530238 = + _theResult___fst_exp__h525661 ; + assign _theResult___fst_exp__h530239 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_exp__h545302 = + assign _theResult___fst_exp__h545303 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 } ; - assign _theResult___fst_exp__h545308 = - (f2_exp__h526064 == 8'd0 && !f2_sfd__h526065[22] && + assign _theResult___fst_exp__h545309 = + (f2_exp__h526065 == 8'd0 && !f2_sfd__h526066[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10200) ? 11'd0 : - _theResult___fst_exp__h545302 ; - assign _theResult___fst_exp__h545311 = - (f2_exp__h526064 == 8'd0) ? - _theResult___fst_exp__h545308 : + _theResult___fst_exp__h545303 ; + assign _theResult___fst_exp__h545312 = + (f2_exp__h526065 == 8'd0) ? + _theResult___fst_exp__h545309 : 11'd897 ; - assign _theResult___fst_exp__h546066 = + assign _theResult___fst_exp__h546067 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q184 : + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 ; - assign _theResult___fst_exp__h546069 = - (_theResult___fst_exp__h545311 == 11'd2047) ? - _theResult___fst_exp__h545311 : - _theResult___fst_exp__h546066 ; - assign _theResult___fst_exp__h554888 = - _theResult____h546652[56] ? + assign _theResult___fst_exp__h546070 = + (_theResult___fst_exp__h545312 == 11'd2047) ? + _theResult___fst_exp__h545312 : + _theResult___fst_exp__h546067 ; + assign _theResult___fst_exp__h554889 = + _theResult____h546653[56] ? 11'd2 : - _theResult___fst_exp__h554962 ; - assign _theResult___fst_exp__h554953 = + _theResult___fst_exp__h554963 ; + assign _theResult___fst_exp__h554954 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 } ; - assign _theResult___fst_exp__h554959 = - (!_theResult____h546652[56] && !_theResult____h546652[55] && - !_theResult____h546652[54] && - !_theResult____h546652[53] && - !_theResult____h546652[52] && - !_theResult____h546652[51] && - !_theResult____h546652[50] && - !_theResult____h546652[49] && - !_theResult____h546652[48] && - !_theResult____h546652[47] && - !_theResult____h546652[46] && - !_theResult____h546652[45] && - !_theResult____h546652[44] && - !_theResult____h546652[43] && - !_theResult____h546652[42] && - !_theResult____h546652[41] && - !_theResult____h546652[40] && - !_theResult____h546652[39] && - !_theResult____h546652[38] && - !_theResult____h546652[37] && - !_theResult____h546652[36] && - !_theResult____h546652[35] && - !_theResult____h546652[34] && - !_theResult____h546652[33] && - !_theResult____h546652[32] && - !_theResult____h546652[31] && - !_theResult____h546652[30] && - !_theResult____h546652[29] && - !_theResult____h546652[28] && - !_theResult____h546652[27] && - !_theResult____h546652[26] && - !_theResult____h546652[25] && - !_theResult____h546652[24] && - !_theResult____h546652[23] && - !_theResult____h546652[22] && - !_theResult____h546652[21] && - !_theResult____h546652[20] && - !_theResult____h546652[19] && - !_theResult____h546652[18] && - !_theResult____h546652[17] && - !_theResult____h546652[16] && - !_theResult____h546652[15] && - !_theResult____h546652[14] && - !_theResult____h546652[13] && - !_theResult____h546652[12] && - !_theResult____h546652[11] && - !_theResult____h546652[10] && - !_theResult____h546652[9] && - !_theResult____h546652[8] && - !_theResult____h546652[7] && - !_theResult____h546652[6] && - !_theResult____h546652[5] && - !_theResult____h546652[4] && - !_theResult____h546652[3] && - !_theResult____h546652[2] && - !_theResult____h546652[1] && - !_theResult____h546652[0] || + assign _theResult___fst_exp__h554960 = + (!_theResult____h546653[56] && !_theResult____h546653[55] && + !_theResult____h546653[54] && + !_theResult____h546653[53] && + !_theResult____h546653[52] && + !_theResult____h546653[51] && + !_theResult____h546653[50] && + !_theResult____h546653[49] && + !_theResult____h546653[48] && + !_theResult____h546653[47] && + !_theResult____h546653[46] && + !_theResult____h546653[45] && + !_theResult____h546653[44] && + !_theResult____h546653[43] && + !_theResult____h546653[42] && + !_theResult____h546653[41] && + !_theResult____h546653[40] && + !_theResult____h546653[39] && + !_theResult____h546653[38] && + !_theResult____h546653[37] && + !_theResult____h546653[36] && + !_theResult____h546653[35] && + !_theResult____h546653[34] && + !_theResult____h546653[33] && + !_theResult____h546653[32] && + !_theResult____h546653[31] && + !_theResult____h546653[30] && + !_theResult____h546653[29] && + !_theResult____h546653[28] && + !_theResult____h546653[27] && + !_theResult____h546653[26] && + !_theResult____h546653[25] && + !_theResult____h546653[24] && + !_theResult____h546653[23] && + !_theResult____h546653[22] && + !_theResult____h546653[21] && + !_theResult____h546653[20] && + !_theResult____h546653[19] && + !_theResult____h546653[18] && + !_theResult____h546653[17] && + !_theResult____h546653[16] && + !_theResult____h546653[15] && + !_theResult____h546653[14] && + !_theResult____h546653[13] && + !_theResult____h546653[12] && + !_theResult____h546653[11] && + !_theResult____h546653[10] && + !_theResult____h546653[9] && + !_theResult____h546653[8] && + !_theResult____h546653[7] && + !_theResult____h546653[6] && + !_theResult____h546653[5] && + !_theResult____h546653[4] && + !_theResult____h546653[3] && + !_theResult____h546653[2] && + !_theResult____h546653[1] && + !_theResult____h546653[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10497) ? 11'd0 : - _theResult___fst_exp__h554953 ; - assign _theResult___fst_exp__h554962 = - (!_theResult____h546652[56] && _theResult____h546652[55]) ? + _theResult___fst_exp__h554954 ; + assign _theResult___fst_exp__h554963 = + (!_theResult____h546653[56] && _theResult____h546653[55]) ? 11'd1 : - _theResult___fst_exp__h554959 ; - assign _theResult___fst_exp__h555717 = + _theResult___fst_exp__h554960 ; + assign _theResult___fst_exp__h555718 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q186 : + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q186 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 ; - assign _theResult___fst_exp__h555720 = - (_theResult___fst_exp__h554888 == 11'd2047) ? - _theResult___fst_exp__h554888 : - _theResult___fst_exp__h555717 ; - assign _theResult___fst_exp__h563673 = + assign _theResult___fst_exp__h555721 = + (_theResult___fst_exp__h554889 == 11'd2047) ? + _theResult___fst_exp__h554889 : + _theResult___fst_exp__h555718 ; + assign _theResult___fst_exp__h563674 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h563712 = + assign _theResult___fst_exp__h563713 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 } ; - assign _theResult___fst_exp__h563718 = - (f2_exp__h526064 == 8'd0 && !f2_sfd__h526065[22] && + assign _theResult___fst_exp__h563719 = + (f2_exp__h526065 == 8'd0 && !f2_sfd__h526066[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10547) ? 11'd0 : - _theResult___fst_exp__h563712 ; - assign _theResult___fst_exp__h563721 = - (f2_exp__h526064 == 8'd0) ? - _theResult___fst_exp__h563718 : - _theResult___fst_exp__h563673 ; - assign _theResult___fst_exp__h564501 = + _theResult___fst_exp__h563713 ; + assign _theResult___fst_exp__h563722 = + (f2_exp__h526065 == 8'd0) ? + _theResult___fst_exp__h563719 : + _theResult___fst_exp__h563674 ; + assign _theResult___fst_exp__h564502 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q188 : + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 ; - assign _theResult___fst_exp__h564504 = - (_theResult___fst_exp__h563721 == 11'd2047) ? - _theResult___fst_exp__h563721 : - _theResult___fst_exp__h564501 ; - assign _theResult___fst_exp__h564513 = - (f2_exp__h526064 == 8'd0) ? + assign _theResult___fst_exp__h564505 = + (_theResult___fst_exp__h563722 == 11'd2047) ? + _theResult___fst_exp__h563722 : + _theResult___fst_exp__h564502 ; + assign _theResult___fst_exp__h564514 = + (f2_exp__h526065 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 ? - _theResult___snd_fst_exp__h546072 : - _theResult___fst_exp__h530238) : + _theResult___snd_fst_exp__h546073 : + _theResult___fst_exp__h530239) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 ? - _theResult___snd_fst_exp__h564507 : - _theResult___fst_exp__h530238) ; - assign _theResult___fst_exp__h564516 = - (f2_exp__h526064 == 8'd0 && f2_sfd__h526065 == 23'd0) ? + _theResult___snd_fst_exp__h564508 : + _theResult___fst_exp__h530239) ; + assign _theResult___fst_exp__h564517 = + (f2_exp__h526065 == 8'd0 && f2_sfd__h526066 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h564513 ; - assign _theResult___fst_exp__h569542 = + _theResult___fst_exp__h564514 ; + assign _theResult___fst_exp__h569543 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_exp__h584606 = + assign _theResult___fst_exp__h584607 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 } ; - assign _theResult___fst_exp__h584612 = - (f3_exp__h565368 == 8'd0 && !f3_sfd__h565369[22] && + assign _theResult___fst_exp__h584613 = + (f3_exp__h565369 == 8'd0 && !f3_sfd__h565370[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9430) ? 11'd0 : - _theResult___fst_exp__h584606 ; - assign _theResult___fst_exp__h584615 = - (f3_exp__h565368 == 8'd0) ? - _theResult___fst_exp__h584612 : + _theResult___fst_exp__h584607 ; + assign _theResult___fst_exp__h584616 = + (f3_exp__h565369 == 8'd0) ? + _theResult___fst_exp__h584613 : 11'd897 ; - assign _theResult___fst_exp__h585370 = + assign _theResult___fst_exp__h585371 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q161 : + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 ; - assign _theResult___fst_exp__h585373 = - (_theResult___fst_exp__h584615 == 11'd2047) ? - _theResult___fst_exp__h584615 : - _theResult___fst_exp__h585370 ; - assign _theResult___fst_exp__h594192 = - _theResult____h585956[56] ? + assign _theResult___fst_exp__h585374 = + (_theResult___fst_exp__h584616 == 11'd2047) ? + _theResult___fst_exp__h584616 : + _theResult___fst_exp__h585371 ; + assign _theResult___fst_exp__h594193 = + _theResult____h585957[56] ? 11'd2 : - _theResult___fst_exp__h594266 ; - assign _theResult___fst_exp__h594257 = + _theResult___fst_exp__h594267 ; + assign _theResult___fst_exp__h594258 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9725 } ; - assign _theResult___fst_exp__h594263 = - (!_theResult____h585956[56] && !_theResult____h585956[55] && - !_theResult____h585956[54] && - !_theResult____h585956[53] && - !_theResult____h585956[52] && - !_theResult____h585956[51] && - !_theResult____h585956[50] && - !_theResult____h585956[49] && - !_theResult____h585956[48] && - !_theResult____h585956[47] && - !_theResult____h585956[46] && - !_theResult____h585956[45] && - !_theResult____h585956[44] && - !_theResult____h585956[43] && - !_theResult____h585956[42] && - !_theResult____h585956[41] && - !_theResult____h585956[40] && - !_theResult____h585956[39] && - !_theResult____h585956[38] && - !_theResult____h585956[37] && - !_theResult____h585956[36] && - !_theResult____h585956[35] && - !_theResult____h585956[34] && - !_theResult____h585956[33] && - !_theResult____h585956[32] && - !_theResult____h585956[31] && - !_theResult____h585956[30] && - !_theResult____h585956[29] && - !_theResult____h585956[28] && - !_theResult____h585956[27] && - !_theResult____h585956[26] && - !_theResult____h585956[25] && - !_theResult____h585956[24] && - !_theResult____h585956[23] && - !_theResult____h585956[22] && - !_theResult____h585956[21] && - !_theResult____h585956[20] && - !_theResult____h585956[19] && - !_theResult____h585956[18] && - !_theResult____h585956[17] && - !_theResult____h585956[16] && - !_theResult____h585956[15] && - !_theResult____h585956[14] && - !_theResult____h585956[13] && - !_theResult____h585956[12] && - !_theResult____h585956[11] && - !_theResult____h585956[10] && - !_theResult____h585956[9] && - !_theResult____h585956[8] && - !_theResult____h585956[7] && - !_theResult____h585956[6] && - !_theResult____h585956[5] && - !_theResult____h585956[4] && - !_theResult____h585956[3] && - !_theResult____h585956[2] && - !_theResult____h585956[1] && - !_theResult____h585956[0] || + assign _theResult___fst_exp__h594264 = + (!_theResult____h585957[56] && !_theResult____h585957[55] && + !_theResult____h585957[54] && + !_theResult____h585957[53] && + !_theResult____h585957[52] && + !_theResult____h585957[51] && + !_theResult____h585957[50] && + !_theResult____h585957[49] && + !_theResult____h585957[48] && + !_theResult____h585957[47] && + !_theResult____h585957[46] && + !_theResult____h585957[45] && + !_theResult____h585957[44] && + !_theResult____h585957[43] && + !_theResult____h585957[42] && + !_theResult____h585957[41] && + !_theResult____h585957[40] && + !_theResult____h585957[39] && + !_theResult____h585957[38] && + !_theResult____h585957[37] && + !_theResult____h585957[36] && + !_theResult____h585957[35] && + !_theResult____h585957[34] && + !_theResult____h585957[33] && + !_theResult____h585957[32] && + !_theResult____h585957[31] && + !_theResult____h585957[30] && + !_theResult____h585957[29] && + !_theResult____h585957[28] && + !_theResult____h585957[27] && + !_theResult____h585957[26] && + !_theResult____h585957[25] && + !_theResult____h585957[24] && + !_theResult____h585957[23] && + !_theResult____h585957[22] && + !_theResult____h585957[21] && + !_theResult____h585957[20] && + !_theResult____h585957[19] && + !_theResult____h585957[18] && + !_theResult____h585957[17] && + !_theResult____h585957[16] && + !_theResult____h585957[15] && + !_theResult____h585957[14] && + !_theResult____h585957[13] && + !_theResult____h585957[12] && + !_theResult____h585957[11] && + !_theResult____h585957[10] && + !_theResult____h585957[9] && + !_theResult____h585957[8] && + !_theResult____h585957[7] && + !_theResult____h585957[6] && + !_theResult____h585957[5] && + !_theResult____h585957[4] && + !_theResult____h585957[3] && + !_theResult____h585957[2] && + !_theResult____h585957[1] && + !_theResult____h585957[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9727) ? 11'd0 : - _theResult___fst_exp__h594257 ; - assign _theResult___fst_exp__h594266 = - (!_theResult____h585956[56] && _theResult____h585956[55]) ? + _theResult___fst_exp__h594258 ; + assign _theResult___fst_exp__h594267 = + (!_theResult____h585957[56] && _theResult____h585957[55]) ? 11'd1 : - _theResult___fst_exp__h594263 ; - assign _theResult___fst_exp__h595021 = + _theResult___fst_exp__h594264 ; + assign _theResult___fst_exp__h595022 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q190 : + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 ; - assign _theResult___fst_exp__h595024 = - (_theResult___fst_exp__h594192 == 11'd2047) ? - _theResult___fst_exp__h594192 : - _theResult___fst_exp__h595021 ; - assign _theResult___fst_exp__h602977 = + assign _theResult___fst_exp__h595025 = + (_theResult___fst_exp__h594193 == 11'd2047) ? + _theResult___fst_exp__h594193 : + _theResult___fst_exp__h595022 ; + assign _theResult___fst_exp__h602978 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h603016 = + assign _theResult___fst_exp__h603017 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 } ; - assign _theResult___fst_exp__h603022 = - (f3_exp__h565368 == 8'd0 && !f3_sfd__h565369[22] && + assign _theResult___fst_exp__h603023 = + (f3_exp__h565369 == 8'd0 && !f3_sfd__h565370[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9777) ? 11'd0 : - _theResult___fst_exp__h603016 ; - assign _theResult___fst_exp__h603025 = - (f3_exp__h565368 == 8'd0) ? - _theResult___fst_exp__h603022 : - _theResult___fst_exp__h602977 ; - assign _theResult___fst_exp__h603805 = + _theResult___fst_exp__h603017 ; + assign _theResult___fst_exp__h603026 = + (f3_exp__h565369 == 8'd0) ? + _theResult___fst_exp__h603023 : + _theResult___fst_exp__h602978 ; + assign _theResult___fst_exp__h603806 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q192 : + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 ; - assign _theResult___fst_exp__h603808 = - (_theResult___fst_exp__h603025 == 11'd2047) ? - _theResult___fst_exp__h603025 : - _theResult___fst_exp__h603805 ; - assign _theResult___fst_exp__h603817 = - (f3_exp__h565368 == 8'd0) ? + assign _theResult___fst_exp__h603809 = + (_theResult___fst_exp__h603026 == 11'd2047) ? + _theResult___fst_exp__h603026 : + _theResult___fst_exp__h603806 ; + assign _theResult___fst_exp__h603818 = + (f3_exp__h565369 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 ? - _theResult___snd_fst_exp__h585376 : - _theResult___fst_exp__h569542) : + _theResult___snd_fst_exp__h585377 : + _theResult___fst_exp__h569543) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 ? - _theResult___snd_fst_exp__h603811 : - _theResult___fst_exp__h569542) ; - assign _theResult___fst_exp__h603820 = - (f3_exp__h565368 == 8'd0 && f3_sfd__h565369 == 23'd0) ? + _theResult___snd_fst_exp__h603812 : + _theResult___fst_exp__h569543) ; + assign _theResult___fst_exp__h603821 = + (f3_exp__h565369 == 8'd0 && f3_sfd__h565370 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h603817 ; - assign _theResult___fst_sfd__h359216 = - (_theResult___fst_exp__h358618 == 8'd255) ? - sfdin__h358612[56:34] : - _theResult___fst_sfd__h359213 ; - assign _theResult___fst_sfd__h367798 = - (_theResult___fst_exp__h367274 == 8'd255) ? - _theResult___snd__h367225[56:34] : - _theResult___fst_sfd__h367795 ; - assign _theResult___fst_sfd__h376982 = - (_theResult___fst_exp__h376384 == 8'd255) ? - sfdin__h376378[56:34] : - _theResult___fst_sfd__h376979 ; - assign _theResult___fst_sfd__h385618 = - (_theResult___fst_exp__h385069 == 8'd255) ? - _theResult___snd__h385015[56:34] : - _theResult___fst_sfd__h385615 ; - assign _theResult___fst_sfd__h385627 = + _theResult___fst_exp__h603818 ; + assign _theResult___fst_sfd__h359217 = + (_theResult___fst_exp__h358619 == 8'd255) ? + sfdin__h358613[56:34] : + _theResult___fst_sfd__h359214 ; + assign _theResult___fst_sfd__h367799 = + (_theResult___fst_exp__h367275 == 8'd255) ? + _theResult___snd__h367226[56:34] : + _theResult___fst_sfd__h367796 ; + assign _theResult___fst_sfd__h376983 = + (_theResult___fst_exp__h376385 == 8'd255) ? + sfdin__h376379[56:34] : + _theResult___fst_sfd__h376980 ; + assign _theResult___fst_sfd__h385619 = + (_theResult___fst_exp__h385070 == 8'd255) ? + _theResult___snd__h385016[56:34] : + _theResult___fst_sfd__h385616 ; + assign _theResult___fst_sfd__h385628 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4112 ? - _theResult___snd_fst_sfd__h367801 : - _theResult___fst_sfd__h350490) : + _theResult___snd_fst_sfd__h367802 : + _theResult___fst_sfd__h350491) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4652 ? - _theResult___snd_fst_sfd__h385621 : - _theResult___fst_sfd__h350490) ; - assign _theResult___fst_sfd__h385633 = + _theResult___snd_fst_sfd__h385622 : + _theResult___fst_sfd__h350491) ; + assign _theResult___fst_sfd__h385634 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -28429,33 +28429,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h385627 ; - assign _theResult___fst_sfd__h404913 = - (_theResult___fst_exp__h404315 == 8'd255) ? - sfdin__h404309[56:34] : - _theResult___fst_sfd__h404910 ; - assign _theResult___fst_sfd__h413495 = - (_theResult___fst_exp__h412971 == 8'd255) ? - _theResult___snd__h412922[56:34] : - _theResult___fst_sfd__h413492 ; - assign _theResult___fst_sfd__h422679 = - (_theResult___fst_exp__h422081 == 8'd255) ? - sfdin__h422075[56:34] : - _theResult___fst_sfd__h422676 ; - assign _theResult___fst_sfd__h431315 = - (_theResult___fst_exp__h430766 == 8'd255) ? - _theResult___snd__h430712[56:34] : - _theResult___fst_sfd__h431312 ; - assign _theResult___fst_sfd__h431324 = + _theResult___fst_sfd__h385628 ; + assign _theResult___fst_sfd__h404914 = + (_theResult___fst_exp__h404316 == 8'd255) ? + sfdin__h404310[56:34] : + _theResult___fst_sfd__h404911 ; + assign _theResult___fst_sfd__h413496 = + (_theResult___fst_exp__h412972 == 8'd255) ? + _theResult___snd__h412923[56:34] : + _theResult___fst_sfd__h413493 ; + assign _theResult___fst_sfd__h422680 = + (_theResult___fst_exp__h422082 == 8'd255) ? + sfdin__h422076[56:34] : + _theResult___fst_sfd__h422677 ; + assign _theResult___fst_sfd__h431316 = + (_theResult___fst_exp__h430767 == 8'd255) ? + _theResult___snd__h430713[56:34] : + _theResult___fst_sfd__h431313 ; + assign _theResult___fst_sfd__h431325 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5504 ? - _theResult___snd_fst_sfd__h413498 : - _theResult___fst_sfd__h396189) : + _theResult___snd_fst_sfd__h413499 : + _theResult___fst_sfd__h396190) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6044 ? - _theResult___snd_fst_sfd__h431318 : - _theResult___fst_sfd__h396189) ; - assign _theResult___fst_sfd__h431330 = + _theResult___snd_fst_sfd__h431319 : + _theResult___fst_sfd__h396190) ; + assign _theResult___fst_sfd__h431331 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -28463,33 +28463,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h431324 ; - assign _theResult___fst_sfd__h450608 = - (_theResult___fst_exp__h450010 == 8'd255) ? - sfdin__h450004[56:34] : - _theResult___fst_sfd__h450605 ; - assign _theResult___fst_sfd__h459190 = - (_theResult___fst_exp__h458666 == 8'd255) ? - _theResult___snd__h458617[56:34] : - _theResult___fst_sfd__h459187 ; - assign _theResult___fst_sfd__h468374 = - (_theResult___fst_exp__h467776 == 8'd255) ? - sfdin__h467770[56:34] : - _theResult___fst_sfd__h468371 ; - assign _theResult___fst_sfd__h477010 = - (_theResult___fst_exp__h476461 == 8'd255) ? - _theResult___snd__h476407[56:34] : - _theResult___fst_sfd__h477007 ; - assign _theResult___fst_sfd__h477019 = + _theResult___fst_sfd__h431325 ; + assign _theResult___fst_sfd__h450609 = + (_theResult___fst_exp__h450011 == 8'd255) ? + sfdin__h450005[56:34] : + _theResult___fst_sfd__h450606 ; + assign _theResult___fst_sfd__h459191 = + (_theResult___fst_exp__h458667 == 8'd255) ? + _theResult___snd__h458618[56:34] : + _theResult___fst_sfd__h459188 ; + assign _theResult___fst_sfd__h468375 = + (_theResult___fst_exp__h467777 == 8'd255) ? + sfdin__h467771[56:34] : + _theResult___fst_sfd__h468372 ; + assign _theResult___fst_sfd__h477011 = + (_theResult___fst_exp__h476462 == 8'd255) ? + _theResult___snd__h476408[56:34] : + _theResult___fst_sfd__h477008 ; + assign _theResult___fst_sfd__h477020 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6896 ? - _theResult___snd_fst_sfd__h459193 : - _theResult___fst_sfd__h441884) : + _theResult___snd_fst_sfd__h459194 : + _theResult___fst_sfd__h441885) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7436 ? - _theResult___snd_fst_sfd__h477013 : - _theResult___fst_sfd__h441884) ; - assign _theResult___fst_sfd__h477025 = + _theResult___snd_fst_sfd__h477014 : + _theResult___fst_sfd__h441885) ; + assign _theResult___fst_sfd__h477026 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -28497,1312 +28497,1312 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h477019 ; - assign _theResult___fst_sfd__h491386 = + _theResult___fst_sfd__h477020 ; + assign _theResult___fst_sfd__h491387 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_sfd__h507214 = + assign _theResult___fst_sfd__h507215 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q216 : + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 ; - assign _theResult___fst_sfd__h507217 = - (_theResult___fst_exp__h506458 == 11'd2047) ? - _theResult___snd__h506409[56:5] : - _theResult___fst_sfd__h507214 ; - assign _theResult___fst_sfd__h516865 = + assign _theResult___fst_sfd__h507218 = + (_theResult___fst_exp__h506459 == 11'd2047) ? + _theResult___snd__h506410[56:5] : + _theResult___fst_sfd__h507215 ; + assign _theResult___fst_sfd__h516866 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 ; - assign _theResult___fst_sfd__h516868 = - (_theResult___fst_exp__h516035 == 11'd2047) ? - sfdin__h516029[56:5] : - _theResult___fst_sfd__h516865 ; - assign _theResult___fst_sfd__h525649 = + assign _theResult___fst_sfd__h516869 = + (_theResult___fst_exp__h516036 == 11'd2047) ? + sfdin__h516030[56:5] : + _theResult___fst_sfd__h516866 ; + assign _theResult___fst_sfd__h525650 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q220 : + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 ; - assign _theResult___fst_sfd__h525652 = - (_theResult___fst_exp__h524868 == 11'd2047) ? - _theResult___snd__h524814[56:5] : - _theResult___fst_sfd__h525649 ; - assign _theResult___fst_sfd__h525661 = - (f1_exp__h487070 == 8'd0) ? + assign _theResult___fst_sfd__h525653 = + (_theResult___fst_exp__h524869 == 11'd2047) ? + _theResult___snd__h524815[56:5] : + _theResult___fst_sfd__h525650 ; + assign _theResult___fst_sfd__h525662 = + (f1_exp__h487071 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8625 ? - _theResult___snd_fst_sfd__h507220 : - _theResult___fst_sfd__h491386) : + _theResult___snd_fst_sfd__h507221 : + _theResult___fst_sfd__h491387) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8762 ? - _theResult___snd_fst_sfd__h525655 : - _theResult___fst_sfd__h491386) ; - assign _theResult___fst_sfd__h525667 = - ((f1_exp__h487070 == 8'd255 || f1_exp__h487070 == 8'd0) && - f1_sfd__h487071 == 23'd0) ? + _theResult___snd_fst_sfd__h525656 : + _theResult___fst_sfd__h491387) ; + assign _theResult___fst_sfd__h525668 = + ((f1_exp__h487071 == 8'd255 || f1_exp__h487071 == 8'd0) && + f1_sfd__h487072 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h525661 ; - assign _theResult___fst_sfd__h530239 = + _theResult___fst_sfd__h525662 ; + assign _theResult___fst_sfd__h530240 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_sfd__h546067 = + assign _theResult___fst_sfd__h546068 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q206 : + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 ; - assign _theResult___fst_sfd__h546070 = - (_theResult___fst_exp__h545311 == 11'd2047) ? - _theResult___snd__h545262[56:5] : - _theResult___fst_sfd__h546067 ; - assign _theResult___fst_sfd__h555718 = + assign _theResult___fst_sfd__h546071 = + (_theResult___fst_exp__h545312 == 11'd2047) ? + _theResult___snd__h545263[56:5] : + _theResult___fst_sfd__h546068 ; + assign _theResult___fst_sfd__h555719 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 ; - assign _theResult___fst_sfd__h555721 = - (_theResult___fst_exp__h554888 == 11'd2047) ? - sfdin__h554882[56:5] : - _theResult___fst_sfd__h555718 ; - assign _theResult___fst_sfd__h564502 = + assign _theResult___fst_sfd__h555722 = + (_theResult___fst_exp__h554889 == 11'd2047) ? + sfdin__h554883[56:5] : + _theResult___fst_sfd__h555719 ; + assign _theResult___fst_sfd__h564503 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q210 : + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 ; - assign _theResult___fst_sfd__h564505 = - (_theResult___fst_exp__h563721 == 11'd2047) ? - _theResult___snd__h563667[56:5] : - _theResult___fst_sfd__h564502 ; - assign _theResult___fst_sfd__h564514 = - (f2_exp__h526064 == 8'd0) ? + assign _theResult___fst_sfd__h564506 = + (_theResult___fst_exp__h563722 == 11'd2047) ? + _theResult___snd__h563668[56:5] : + _theResult___fst_sfd__h564503 ; + assign _theResult___fst_sfd__h564515 = + (f2_exp__h526065 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10125 ? - _theResult___snd_fst_sfd__h546073 : - _theResult___fst_sfd__h530239) : + _theResult___snd_fst_sfd__h546074 : + _theResult___fst_sfd__h530240) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10247 ? - _theResult___snd_fst_sfd__h564508 : - _theResult___fst_sfd__h530239) ; - assign _theResult___fst_sfd__h564520 = - ((f2_exp__h526064 == 8'd255 || f2_exp__h526064 == 8'd0) && - f2_sfd__h526065 == 23'd0) ? + _theResult___snd_fst_sfd__h564509 : + _theResult___fst_sfd__h530240) ; + assign _theResult___fst_sfd__h564521 = + ((f2_exp__h526065 == 8'd255 || f2_exp__h526065 == 8'd0) && + f2_sfd__h526066 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h564514 ; - assign _theResult___fst_sfd__h569543 = + _theResult___fst_sfd__h564515 ; + assign _theResult___fst_sfd__h569544 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q20 ; - assign _theResult___fst_sfd__h585371 = + assign _theResult___fst_sfd__h585372 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q222 : + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 ; - assign _theResult___fst_sfd__h585374 = - (_theResult___fst_exp__h584615 == 11'd2047) ? - _theResult___snd__h584566[56:5] : - _theResult___fst_sfd__h585371 ; - assign _theResult___fst_sfd__h595022 = + assign _theResult___fst_sfd__h585375 = + (_theResult___fst_exp__h584616 == 11'd2047) ? + _theResult___snd__h584567[56:5] : + _theResult___fst_sfd__h585372 ; + assign _theResult___fst_sfd__h595023 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 ; - assign _theResult___fst_sfd__h595025 = - (_theResult___fst_exp__h594192 == 11'd2047) ? - sfdin__h594186[56:5] : - _theResult___fst_sfd__h595022 ; - assign _theResult___fst_sfd__h603806 = + assign _theResult___fst_sfd__h595026 = + (_theResult___fst_exp__h594193 == 11'd2047) ? + sfdin__h594187[56:5] : + _theResult___fst_sfd__h595023 ; + assign _theResult___fst_sfd__h603807 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q226 : + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 ; - assign _theResult___fst_sfd__h603809 = - (_theResult___fst_exp__h603025 == 11'd2047) ? - _theResult___snd__h602971[56:5] : - _theResult___fst_sfd__h603806 ; - assign _theResult___fst_sfd__h603818 = - (f3_exp__h565368 == 8'd0) ? + assign _theResult___fst_sfd__h603810 = + (_theResult___fst_exp__h603026 == 11'd2047) ? + _theResult___snd__h602972[56:5] : + _theResult___fst_sfd__h603807 ; + assign _theResult___fst_sfd__h603819 = + (f3_exp__h565369 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9355 ? - _theResult___snd_fst_sfd__h585377 : - _theResult___fst_sfd__h569543) : + _theResult___snd_fst_sfd__h585378 : + _theResult___fst_sfd__h569544) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9477 ? - _theResult___snd_fst_sfd__h603812 : - _theResult___fst_sfd__h569543) ; - assign _theResult___fst_sfd__h603824 = - ((f3_exp__h565368 == 8'd255 || f3_exp__h565368 == 8'd0) && - f3_sfd__h565369 == 23'd0) ? + _theResult___snd_fst_sfd__h603813 : + _theResult___fst_sfd__h569544) ; + assign _theResult___fst_sfd__h603825 = + ((f3_exp__h565369 == 8'd255 || f3_exp__h565369 == 8'd0) && + f3_sfd__h565370 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h603818 ; - assign _theResult___sfd__h359135 = - sfd__h358710[24] ? - ((_theResult___fst_exp__h358618 == 8'd254) ? + _theResult___fst_sfd__h603819 ; + assign _theResult___sfd__h359136 = + sfd__h358711[24] ? + ((_theResult___fst_exp__h358619 == 8'd254) ? 23'd0 : - sfd__h358710[23:1]) : - sfd__h358710[22:0] ; - assign _theResult___sfd__h367717 = - sfd__h367292[24] ? - ((_theResult___fst_exp__h367274 == 8'd254) ? + sfd__h358711[23:1]) : + sfd__h358711[22:0] ; + assign _theResult___sfd__h367718 = + sfd__h367293[24] ? + ((_theResult___fst_exp__h367275 == 8'd254) ? 23'd0 : - sfd__h367292[23:1]) : - sfd__h367292[22:0] ; - assign _theResult___sfd__h376901 = - sfd__h376476[24] ? - ((_theResult___fst_exp__h376384 == 8'd254) ? + sfd__h367293[23:1]) : + sfd__h367293[22:0] ; + assign _theResult___sfd__h376902 = + sfd__h376477[24] ? + ((_theResult___fst_exp__h376385 == 8'd254) ? 23'd0 : - sfd__h376476[23:1]) : - sfd__h376476[22:0] ; - assign _theResult___sfd__h385537 = - sfd__h385088[24] ? - ((_theResult___fst_exp__h385069 == 8'd254) ? + sfd__h376477[23:1]) : + sfd__h376477[22:0] ; + assign _theResult___sfd__h385538 = + sfd__h385089[24] ? + ((_theResult___fst_exp__h385070 == 8'd254) ? 23'd0 : - sfd__h385088[23:1]) : - sfd__h385088[22:0] ; - assign _theResult___sfd__h385639 = + sfd__h385089[23:1]) : + sfd__h385089[22:0] ; + assign _theResult___sfd__h385640 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h342852 : - _theResult___fst_sfd__h385633 ; - assign _theResult___sfd__h404832 = - sfd__h404407[24] ? - ((_theResult___fst_exp__h404315 == 8'd254) ? + _theResult___snd_fst_sfd__h342853 : + _theResult___fst_sfd__h385634 ; + assign _theResult___sfd__h404833 = + sfd__h404408[24] ? + ((_theResult___fst_exp__h404316 == 8'd254) ? 23'd0 : - sfd__h404407[23:1]) : - sfd__h404407[22:0] ; - assign _theResult___sfd__h413414 = - sfd__h412989[24] ? - ((_theResult___fst_exp__h412971 == 8'd254) ? + sfd__h404408[23:1]) : + sfd__h404408[22:0] ; + assign _theResult___sfd__h413415 = + sfd__h412990[24] ? + ((_theResult___fst_exp__h412972 == 8'd254) ? 23'd0 : - sfd__h412989[23:1]) : - sfd__h412989[22:0] ; - assign _theResult___sfd__h422598 = - sfd__h422173[24] ? - ((_theResult___fst_exp__h422081 == 8'd254) ? + sfd__h412990[23:1]) : + sfd__h412990[22:0] ; + assign _theResult___sfd__h422599 = + sfd__h422174[24] ? + ((_theResult___fst_exp__h422082 == 8'd254) ? 23'd0 : - sfd__h422173[23:1]) : - sfd__h422173[22:0] ; - assign _theResult___sfd__h431234 = - sfd__h430785[24] ? - ((_theResult___fst_exp__h430766 == 8'd254) ? + sfd__h422174[23:1]) : + sfd__h422174[22:0] ; + assign _theResult___sfd__h431235 = + sfd__h430786[24] ? + ((_theResult___fst_exp__h430767 == 8'd254) ? 23'd0 : - sfd__h430785[23:1]) : - sfd__h430785[22:0] ; - assign _theResult___sfd__h431336 = + sfd__h430786[23:1]) : + sfd__h430786[22:0] ; + assign _theResult___sfd__h431337 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h388554 : - _theResult___fst_sfd__h431330 ; - assign _theResult___sfd__h450527 = - sfd__h450102[24] ? - ((_theResult___fst_exp__h450010 == 8'd254) ? + _theResult___snd_fst_sfd__h388555 : + _theResult___fst_sfd__h431331 ; + assign _theResult___sfd__h450528 = + sfd__h450103[24] ? + ((_theResult___fst_exp__h450011 == 8'd254) ? 23'd0 : - sfd__h450102[23:1]) : - sfd__h450102[22:0] ; - assign _theResult___sfd__h459109 = - sfd__h458684[24] ? - ((_theResult___fst_exp__h458666 == 8'd254) ? + sfd__h450103[23:1]) : + sfd__h450103[22:0] ; + assign _theResult___sfd__h459110 = + sfd__h458685[24] ? + ((_theResult___fst_exp__h458667 == 8'd254) ? 23'd0 : - sfd__h458684[23:1]) : - sfd__h458684[22:0] ; - assign _theResult___sfd__h468293 = - sfd__h467868[24] ? - ((_theResult___fst_exp__h467776 == 8'd254) ? + sfd__h458685[23:1]) : + sfd__h458685[22:0] ; + assign _theResult___sfd__h468294 = + sfd__h467869[24] ? + ((_theResult___fst_exp__h467777 == 8'd254) ? 23'd0 : - sfd__h467868[23:1]) : - sfd__h467868[22:0] ; - assign _theResult___sfd__h476929 = - sfd__h476480[24] ? - ((_theResult___fst_exp__h476461 == 8'd254) ? + sfd__h467869[23:1]) : + sfd__h467869[22:0] ; + assign _theResult___sfd__h476930 = + sfd__h476481[24] ? + ((_theResult___fst_exp__h476462 == 8'd254) ? 23'd0 : - sfd__h476480[23:1]) : - sfd__h476480[22:0] ; - assign _theResult___sfd__h477031 = + sfd__h476481[23:1]) : + sfd__h476481[22:0] ; + assign _theResult___sfd__h477032 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h434249 : - _theResult___fst_sfd__h477025 ; - assign _theResult___sfd__h507114 = - sfd__h506476[53] ? - ((_theResult___fst_exp__h506458 == 11'd2046) ? + _theResult___snd_fst_sfd__h434250 : + _theResult___fst_sfd__h477026 ; + assign _theResult___sfd__h507115 = + sfd__h506477[53] ? + ((_theResult___fst_exp__h506459 == 11'd2046) ? 52'd0 : - sfd__h506476[52:1]) : - sfd__h506476[51:0] ; - assign _theResult___sfd__h516765 = - sfd__h516127[53] ? - ((_theResult___fst_exp__h516035 == 11'd2046) ? + sfd__h506477[52:1]) : + sfd__h506477[51:0] ; + assign _theResult___sfd__h516766 = + sfd__h516128[53] ? + ((_theResult___fst_exp__h516036 == 11'd2046) ? 52'd0 : - sfd__h516127[52:1]) : - sfd__h516127[51:0] ; - assign _theResult___sfd__h525549 = - sfd__h524887[53] ? - ((_theResult___fst_exp__h524868 == 11'd2046) ? + sfd__h516128[52:1]) : + sfd__h516128[51:0] ; + assign _theResult___sfd__h525550 = + sfd__h524888[53] ? + ((_theResult___fst_exp__h524869 == 11'd2046) ? 52'd0 : - sfd__h524887[52:1]) : - sfd__h524887[51:0] ; - assign _theResult___sfd__h545967 = - sfd__h545329[53] ? - ((_theResult___fst_exp__h545311 == 11'd2046) ? + sfd__h524888[52:1]) : + sfd__h524888[51:0] ; + assign _theResult___sfd__h545968 = + sfd__h545330[53] ? + ((_theResult___fst_exp__h545312 == 11'd2046) ? 52'd0 : - sfd__h545329[52:1]) : - sfd__h545329[51:0] ; - assign _theResult___sfd__h555618 = - sfd__h554980[53] ? - ((_theResult___fst_exp__h554888 == 11'd2046) ? + sfd__h545330[52:1]) : + sfd__h545330[51:0] ; + assign _theResult___sfd__h555619 = + sfd__h554981[53] ? + ((_theResult___fst_exp__h554889 == 11'd2046) ? 52'd0 : - sfd__h554980[52:1]) : - sfd__h554980[51:0] ; - assign _theResult___sfd__h564402 = - sfd__h563740[53] ? - ((_theResult___fst_exp__h563721 == 11'd2046) ? + sfd__h554981[52:1]) : + sfd__h554981[51:0] ; + assign _theResult___sfd__h564403 = + sfd__h563741[53] ? + ((_theResult___fst_exp__h563722 == 11'd2046) ? 52'd0 : - sfd__h563740[52:1]) : - sfd__h563740[51:0] ; - assign _theResult___sfd__h585271 = - sfd__h584633[53] ? - ((_theResult___fst_exp__h584615 == 11'd2046) ? + sfd__h563741[52:1]) : + sfd__h563741[51:0] ; + assign _theResult___sfd__h585272 = + sfd__h584634[53] ? + ((_theResult___fst_exp__h584616 == 11'd2046) ? 52'd0 : - sfd__h584633[52:1]) : - sfd__h584633[51:0] ; - assign _theResult___sfd__h594922 = - sfd__h594284[53] ? - ((_theResult___fst_exp__h594192 == 11'd2046) ? + sfd__h584634[52:1]) : + sfd__h584634[51:0] ; + assign _theResult___sfd__h594923 = + sfd__h594285[53] ? + ((_theResult___fst_exp__h594193 == 11'd2046) ? 52'd0 : - sfd__h594284[52:1]) : - sfd__h594284[51:0] ; - assign _theResult___sfd__h603706 = - sfd__h603044[53] ? - ((_theResult___fst_exp__h603025 == 11'd2046) ? + sfd__h594285[52:1]) : + sfd__h594285[51:0] ; + assign _theResult___sfd__h603707 = + sfd__h603045[53] ? + ((_theResult___fst_exp__h603026 == 11'd2046) ? 52'd0 : - sfd__h603044[52:1]) : - sfd__h603044[51:0] ; - assign _theResult___snd__h358629 = { _theResult____h350507[55:0], 1'd0 } ; - assign _theResult___snd__h358640 = - (!_theResult____h350507[56] && _theResult____h350507[55]) ? - _theResult___snd__h358642 : - _theResult___snd__h358652 ; - assign _theResult___snd__h358642 = { _theResult____h350507[54:0], 2'd0 } ; - assign _theResult___snd__h358652 = - (!_theResult____h350507[56] && !_theResult____h350507[55] && - !_theResult____h350507[54] && - !_theResult____h350507[53] && - !_theResult____h350507[52] && - !_theResult____h350507[51] && - !_theResult____h350507[50] && - !_theResult____h350507[49] && - !_theResult____h350507[48] && - !_theResult____h350507[47] && - !_theResult____h350507[46] && - !_theResult____h350507[45] && - !_theResult____h350507[44] && - !_theResult____h350507[43] && - !_theResult____h350507[42] && - !_theResult____h350507[41] && - !_theResult____h350507[40] && - !_theResult____h350507[39] && - !_theResult____h350507[38] && - !_theResult____h350507[37] && - !_theResult____h350507[36] && - !_theResult____h350507[35] && - !_theResult____h350507[34] && - !_theResult____h350507[33] && - !_theResult____h350507[32] && - !_theResult____h350507[31] && - !_theResult____h350507[30] && - !_theResult____h350507[29] && - !_theResult____h350507[28] && - !_theResult____h350507[27] && - !_theResult____h350507[26] && - !_theResult____h350507[25] && - !_theResult____h350507[24] && - !_theResult____h350507[23] && - !_theResult____h350507[22] && - !_theResult____h350507[21] && - !_theResult____h350507[20] && - !_theResult____h350507[19] && - !_theResult____h350507[18] && - !_theResult____h350507[17] && - !_theResult____h350507[16] && - !_theResult____h350507[15] && - !_theResult____h350507[14] && - !_theResult____h350507[13] && - !_theResult____h350507[12] && - !_theResult____h350507[11] && - !_theResult____h350507[10] && - !_theResult____h350507[9] && - !_theResult____h350507[8] && - !_theResult____h350507[7] && - !_theResult____h350507[6] && - !_theResult____h350507[5] && - !_theResult____h350507[4] && - !_theResult____h350507[3] && - !_theResult____h350507[2] && - !_theResult____h350507[1] && - !_theResult____h350507[0]) ? - _theResult____h350507 : - _theResult___snd__h358658 ; - assign _theResult___snd__h358658 = + sfd__h603045[52:1]) : + sfd__h603045[51:0] ; + assign _theResult___snd__h358630 = { _theResult____h350508[55:0], 1'd0 } ; + assign _theResult___snd__h358641 = + (!_theResult____h350508[56] && _theResult____h350508[55]) ? + _theResult___snd__h358643 : + _theResult___snd__h358653 ; + assign _theResult___snd__h358643 = { _theResult____h350508[54:0], 2'd0 } ; + assign _theResult___snd__h358653 = + (!_theResult____h350508[56] && !_theResult____h350508[55] && + !_theResult____h350508[54] && + !_theResult____h350508[53] && + !_theResult____h350508[52] && + !_theResult____h350508[51] && + !_theResult____h350508[50] && + !_theResult____h350508[49] && + !_theResult____h350508[48] && + !_theResult____h350508[47] && + !_theResult____h350508[46] && + !_theResult____h350508[45] && + !_theResult____h350508[44] && + !_theResult____h350508[43] && + !_theResult____h350508[42] && + !_theResult____h350508[41] && + !_theResult____h350508[40] && + !_theResult____h350508[39] && + !_theResult____h350508[38] && + !_theResult____h350508[37] && + !_theResult____h350508[36] && + !_theResult____h350508[35] && + !_theResult____h350508[34] && + !_theResult____h350508[33] && + !_theResult____h350508[32] && + !_theResult____h350508[31] && + !_theResult____h350508[30] && + !_theResult____h350508[29] && + !_theResult____h350508[28] && + !_theResult____h350508[27] && + !_theResult____h350508[26] && + !_theResult____h350508[25] && + !_theResult____h350508[24] && + !_theResult____h350508[23] && + !_theResult____h350508[22] && + !_theResult____h350508[21] && + !_theResult____h350508[20] && + !_theResult____h350508[19] && + !_theResult____h350508[18] && + !_theResult____h350508[17] && + !_theResult____h350508[16] && + !_theResult____h350508[15] && + !_theResult____h350508[14] && + !_theResult____h350508[13] && + !_theResult____h350508[12] && + !_theResult____h350508[11] && + !_theResult____h350508[10] && + !_theResult____h350508[9] && + !_theResult____h350508[8] && + !_theResult____h350508[7] && + !_theResult____h350508[6] && + !_theResult____h350508[5] && + !_theResult____h350508[4] && + !_theResult____h350508[3] && + !_theResult____h350508[2] && + !_theResult____h350508[1] && + !_theResult____h350508[0]) ? + _theResult____h350508 : + _theResult___snd__h358659 ; + assign _theResult___snd__h358659 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q29[54:0], 2'd0 } ; - assign _theResult___snd__h358681 = - _theResult____h350507 << + assign _theResult___snd__h358682 = + _theResult____h350508 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4347 ; - assign _theResult___snd__h367225 = + assign _theResult___snd__h367226 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h367234 : - _theResult___snd__h367227 ; - assign _theResult___snd__h367227 = + _theResult___snd__h367235 : + _theResult___snd__h367228 ; + assign _theResult___snd__h367228 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h367234 = + assign _theResult___snd__h367235 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523) ? - sfd__h342902 : - _theResult___snd__h367240 ; - assign _theResult___snd__h367240 = + sfd__h342903 : + _theResult___snd__h367241 ; + assign _theResult___snd__h367241 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q31[54:0], 2'd0 } ; - assign _theResult___snd__h367263 = - sfd__h342902 << + assign _theResult___snd__h367264 = + sfd__h342903 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4578 ; - assign _theResult___snd__h376395 = { _theResult____h368146[55:0], 1'd0 } ; - assign _theResult___snd__h376406 = - (!_theResult____h368146[56] && _theResult____h368146[55]) ? - _theResult___snd__h376408 : - _theResult___snd__h376418 ; - assign _theResult___snd__h376408 = { _theResult____h368146[54:0], 2'd0 } ; - assign _theResult___snd__h376418 = - (!_theResult____h368146[56] && !_theResult____h368146[55] && - !_theResult____h368146[54] && - !_theResult____h368146[53] && - !_theResult____h368146[52] && - !_theResult____h368146[51] && - !_theResult____h368146[50] && - !_theResult____h368146[49] && - !_theResult____h368146[48] && - !_theResult____h368146[47] && - !_theResult____h368146[46] && - !_theResult____h368146[45] && - !_theResult____h368146[44] && - !_theResult____h368146[43] && - !_theResult____h368146[42] && - !_theResult____h368146[41] && - !_theResult____h368146[40] && - !_theResult____h368146[39] && - !_theResult____h368146[38] && - !_theResult____h368146[37] && - !_theResult____h368146[36] && - !_theResult____h368146[35] && - !_theResult____h368146[34] && - !_theResult____h368146[33] && - !_theResult____h368146[32] && - !_theResult____h368146[31] && - !_theResult____h368146[30] && - !_theResult____h368146[29] && - !_theResult____h368146[28] && - !_theResult____h368146[27] && - !_theResult____h368146[26] && - !_theResult____h368146[25] && - !_theResult____h368146[24] && - !_theResult____h368146[23] && - !_theResult____h368146[22] && - !_theResult____h368146[21] && - !_theResult____h368146[20] && - !_theResult____h368146[19] && - !_theResult____h368146[18] && - !_theResult____h368146[17] && - !_theResult____h368146[16] && - !_theResult____h368146[15] && - !_theResult____h368146[14] && - !_theResult____h368146[13] && - !_theResult____h368146[12] && - !_theResult____h368146[11] && - !_theResult____h368146[10] && - !_theResult____h368146[9] && - !_theResult____h368146[8] && - !_theResult____h368146[7] && - !_theResult____h368146[6] && - !_theResult____h368146[5] && - !_theResult____h368146[4] && - !_theResult____h368146[3] && - !_theResult____h368146[2] && - !_theResult____h368146[1] && - !_theResult____h368146[0]) ? - _theResult____h368146 : - _theResult___snd__h376424 ; - assign _theResult___snd__h376424 = + assign _theResult___snd__h376396 = { _theResult____h368147[55:0], 1'd0 } ; + assign _theResult___snd__h376407 = + (!_theResult____h368147[56] && _theResult____h368147[55]) ? + _theResult___snd__h376409 : + _theResult___snd__h376419 ; + assign _theResult___snd__h376409 = { _theResult____h368147[54:0], 2'd0 } ; + assign _theResult___snd__h376419 = + (!_theResult____h368147[56] && !_theResult____h368147[55] && + !_theResult____h368147[54] && + !_theResult____h368147[53] && + !_theResult____h368147[52] && + !_theResult____h368147[51] && + !_theResult____h368147[50] && + !_theResult____h368147[49] && + !_theResult____h368147[48] && + !_theResult____h368147[47] && + !_theResult____h368147[46] && + !_theResult____h368147[45] && + !_theResult____h368147[44] && + !_theResult____h368147[43] && + !_theResult____h368147[42] && + !_theResult____h368147[41] && + !_theResult____h368147[40] && + !_theResult____h368147[39] && + !_theResult____h368147[38] && + !_theResult____h368147[37] && + !_theResult____h368147[36] && + !_theResult____h368147[35] && + !_theResult____h368147[34] && + !_theResult____h368147[33] && + !_theResult____h368147[32] && + !_theResult____h368147[31] && + !_theResult____h368147[30] && + !_theResult____h368147[29] && + !_theResult____h368147[28] && + !_theResult____h368147[27] && + !_theResult____h368147[26] && + !_theResult____h368147[25] && + !_theResult____h368147[24] && + !_theResult____h368147[23] && + !_theResult____h368147[22] && + !_theResult____h368147[21] && + !_theResult____h368147[20] && + !_theResult____h368147[19] && + !_theResult____h368147[18] && + !_theResult____h368147[17] && + !_theResult____h368147[16] && + !_theResult____h368147[15] && + !_theResult____h368147[14] && + !_theResult____h368147[13] && + !_theResult____h368147[12] && + !_theResult____h368147[11] && + !_theResult____h368147[10] && + !_theResult____h368147[9] && + !_theResult____h368147[8] && + !_theResult____h368147[7] && + !_theResult____h368147[6] && + !_theResult____h368147[5] && + !_theResult____h368147[4] && + !_theResult____h368147[3] && + !_theResult____h368147[2] && + !_theResult____h368147[1] && + !_theResult____h368147[0]) ? + _theResult____h368147 : + _theResult___snd__h376425 ; + assign _theResult___snd__h376425 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q39[54:0], 2'd0 } ; - assign _theResult___snd__h376447 = - _theResult____h368146 << + assign _theResult___snd__h376448 = + _theResult____h368147 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4898 ; - assign _theResult___snd__h385015 = + assign _theResult___snd__h385016 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h385029 : - _theResult___snd__h367227 ; - assign _theResult___snd__h385029 = + _theResult___snd__h385030 : + _theResult___snd__h367228 ; + assign _theResult___snd__h385030 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4523) ? - sfd__h342902 : - _theResult___snd__h385035 ; - assign _theResult___snd__h385035 = + sfd__h342903 : + _theResult___snd__h385036 ; + assign _theResult___snd__h385036 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q44[54:0], 2'd0 } ; - assign _theResult___snd__h385053 = - sfd__h342902 << + assign _theResult___snd__h385054 = + sfd__h342903 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4972[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4972) ; - assign _theResult___snd__h404326 = { _theResult____h396206[55:0], 1'd0 } ; - assign _theResult___snd__h404337 = - (!_theResult____h396206[56] && _theResult____h396206[55]) ? - _theResult___snd__h404339 : - _theResult___snd__h404349 ; - assign _theResult___snd__h404339 = { _theResult____h396206[54:0], 2'd0 } ; - assign _theResult___snd__h404349 = - (!_theResult____h396206[56] && !_theResult____h396206[55] && - !_theResult____h396206[54] && - !_theResult____h396206[53] && - !_theResult____h396206[52] && - !_theResult____h396206[51] && - !_theResult____h396206[50] && - !_theResult____h396206[49] && - !_theResult____h396206[48] && - !_theResult____h396206[47] && - !_theResult____h396206[46] && - !_theResult____h396206[45] && - !_theResult____h396206[44] && - !_theResult____h396206[43] && - !_theResult____h396206[42] && - !_theResult____h396206[41] && - !_theResult____h396206[40] && - !_theResult____h396206[39] && - !_theResult____h396206[38] && - !_theResult____h396206[37] && - !_theResult____h396206[36] && - !_theResult____h396206[35] && - !_theResult____h396206[34] && - !_theResult____h396206[33] && - !_theResult____h396206[32] && - !_theResult____h396206[31] && - !_theResult____h396206[30] && - !_theResult____h396206[29] && - !_theResult____h396206[28] && - !_theResult____h396206[27] && - !_theResult____h396206[26] && - !_theResult____h396206[25] && - !_theResult____h396206[24] && - !_theResult____h396206[23] && - !_theResult____h396206[22] && - !_theResult____h396206[21] && - !_theResult____h396206[20] && - !_theResult____h396206[19] && - !_theResult____h396206[18] && - !_theResult____h396206[17] && - !_theResult____h396206[16] && - !_theResult____h396206[15] && - !_theResult____h396206[14] && - !_theResult____h396206[13] && - !_theResult____h396206[12] && - !_theResult____h396206[11] && - !_theResult____h396206[10] && - !_theResult____h396206[9] && - !_theResult____h396206[8] && - !_theResult____h396206[7] && - !_theResult____h396206[6] && - !_theResult____h396206[5] && - !_theResult____h396206[4] && - !_theResult____h396206[3] && - !_theResult____h396206[2] && - !_theResult____h396206[1] && - !_theResult____h396206[0]) ? - _theResult____h396206 : - _theResult___snd__h404355 ; - assign _theResult___snd__h404355 = + assign _theResult___snd__h404327 = { _theResult____h396207[55:0], 1'd0 } ; + assign _theResult___snd__h404338 = + (!_theResult____h396207[56] && _theResult____h396207[55]) ? + _theResult___snd__h404340 : + _theResult___snd__h404350 ; + assign _theResult___snd__h404340 = { _theResult____h396207[54:0], 2'd0 } ; + assign _theResult___snd__h404350 = + (!_theResult____h396207[56] && !_theResult____h396207[55] && + !_theResult____h396207[54] && + !_theResult____h396207[53] && + !_theResult____h396207[52] && + !_theResult____h396207[51] && + !_theResult____h396207[50] && + !_theResult____h396207[49] && + !_theResult____h396207[48] && + !_theResult____h396207[47] && + !_theResult____h396207[46] && + !_theResult____h396207[45] && + !_theResult____h396207[44] && + !_theResult____h396207[43] && + !_theResult____h396207[42] && + !_theResult____h396207[41] && + !_theResult____h396207[40] && + !_theResult____h396207[39] && + !_theResult____h396207[38] && + !_theResult____h396207[37] && + !_theResult____h396207[36] && + !_theResult____h396207[35] && + !_theResult____h396207[34] && + !_theResult____h396207[33] && + !_theResult____h396207[32] && + !_theResult____h396207[31] && + !_theResult____h396207[30] && + !_theResult____h396207[29] && + !_theResult____h396207[28] && + !_theResult____h396207[27] && + !_theResult____h396207[26] && + !_theResult____h396207[25] && + !_theResult____h396207[24] && + !_theResult____h396207[23] && + !_theResult____h396207[22] && + !_theResult____h396207[21] && + !_theResult____h396207[20] && + !_theResult____h396207[19] && + !_theResult____h396207[18] && + !_theResult____h396207[17] && + !_theResult____h396207[16] && + !_theResult____h396207[15] && + !_theResult____h396207[14] && + !_theResult____h396207[13] && + !_theResult____h396207[12] && + !_theResult____h396207[11] && + !_theResult____h396207[10] && + !_theResult____h396207[9] && + !_theResult____h396207[8] && + !_theResult____h396207[7] && + !_theResult____h396207[6] && + !_theResult____h396207[5] && + !_theResult____h396207[4] && + !_theResult____h396207[3] && + !_theResult____h396207[2] && + !_theResult____h396207[1] && + !_theResult____h396207[0]) ? + _theResult____h396207 : + _theResult___snd__h404356 ; + assign _theResult___snd__h404356 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q64[54:0], 2'd0 } ; - assign _theResult___snd__h404378 = - _theResult____h396206 << + assign _theResult___snd__h404379 = + _theResult____h396207 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5739 ; - assign _theResult___snd__h412922 = + assign _theResult___snd__h412923 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h412931 : - _theResult___snd__h412924 ; - assign _theResult___snd__h412924 = + _theResult___snd__h412932 : + _theResult___snd__h412925 ; + assign _theResult___snd__h412925 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h412931 = + assign _theResult___snd__h412932 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915) ? - sfd__h388604 : - _theResult___snd__h412937 ; - assign _theResult___snd__h412937 = + sfd__h388605 : + _theResult___snd__h412938 ; + assign _theResult___snd__h412938 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q66[54:0], 2'd0 } ; - assign _theResult___snd__h412960 = - sfd__h388604 << + assign _theResult___snd__h412961 = + sfd__h388605 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5970 ; - assign _theResult___snd__h422092 = { _theResult____h413843[55:0], 1'd0 } ; - assign _theResult___snd__h422103 = - (!_theResult____h413843[56] && _theResult____h413843[55]) ? - _theResult___snd__h422105 : - _theResult___snd__h422115 ; - assign _theResult___snd__h422105 = { _theResult____h413843[54:0], 2'd0 } ; - assign _theResult___snd__h422115 = - (!_theResult____h413843[56] && !_theResult____h413843[55] && - !_theResult____h413843[54] && - !_theResult____h413843[53] && - !_theResult____h413843[52] && - !_theResult____h413843[51] && - !_theResult____h413843[50] && - !_theResult____h413843[49] && - !_theResult____h413843[48] && - !_theResult____h413843[47] && - !_theResult____h413843[46] && - !_theResult____h413843[45] && - !_theResult____h413843[44] && - !_theResult____h413843[43] && - !_theResult____h413843[42] && - !_theResult____h413843[41] && - !_theResult____h413843[40] && - !_theResult____h413843[39] && - !_theResult____h413843[38] && - !_theResult____h413843[37] && - !_theResult____h413843[36] && - !_theResult____h413843[35] && - !_theResult____h413843[34] && - !_theResult____h413843[33] && - !_theResult____h413843[32] && - !_theResult____h413843[31] && - !_theResult____h413843[30] && - !_theResult____h413843[29] && - !_theResult____h413843[28] && - !_theResult____h413843[27] && - !_theResult____h413843[26] && - !_theResult____h413843[25] && - !_theResult____h413843[24] && - !_theResult____h413843[23] && - !_theResult____h413843[22] && - !_theResult____h413843[21] && - !_theResult____h413843[20] && - !_theResult____h413843[19] && - !_theResult____h413843[18] && - !_theResult____h413843[17] && - !_theResult____h413843[16] && - !_theResult____h413843[15] && - !_theResult____h413843[14] && - !_theResult____h413843[13] && - !_theResult____h413843[12] && - !_theResult____h413843[11] && - !_theResult____h413843[10] && - !_theResult____h413843[9] && - !_theResult____h413843[8] && - !_theResult____h413843[7] && - !_theResult____h413843[6] && - !_theResult____h413843[5] && - !_theResult____h413843[4] && - !_theResult____h413843[3] && - !_theResult____h413843[2] && - !_theResult____h413843[1] && - !_theResult____h413843[0]) ? - _theResult____h413843 : - _theResult___snd__h422121 ; - assign _theResult___snd__h422121 = + assign _theResult___snd__h422093 = { _theResult____h413844[55:0], 1'd0 } ; + assign _theResult___snd__h422104 = + (!_theResult____h413844[56] && _theResult____h413844[55]) ? + _theResult___snd__h422106 : + _theResult___snd__h422116 ; + assign _theResult___snd__h422106 = { _theResult____h413844[54:0], 2'd0 } ; + assign _theResult___snd__h422116 = + (!_theResult____h413844[56] && !_theResult____h413844[55] && + !_theResult____h413844[54] && + !_theResult____h413844[53] && + !_theResult____h413844[52] && + !_theResult____h413844[51] && + !_theResult____h413844[50] && + !_theResult____h413844[49] && + !_theResult____h413844[48] && + !_theResult____h413844[47] && + !_theResult____h413844[46] && + !_theResult____h413844[45] && + !_theResult____h413844[44] && + !_theResult____h413844[43] && + !_theResult____h413844[42] && + !_theResult____h413844[41] && + !_theResult____h413844[40] && + !_theResult____h413844[39] && + !_theResult____h413844[38] && + !_theResult____h413844[37] && + !_theResult____h413844[36] && + !_theResult____h413844[35] && + !_theResult____h413844[34] && + !_theResult____h413844[33] && + !_theResult____h413844[32] && + !_theResult____h413844[31] && + !_theResult____h413844[30] && + !_theResult____h413844[29] && + !_theResult____h413844[28] && + !_theResult____h413844[27] && + !_theResult____h413844[26] && + !_theResult____h413844[25] && + !_theResult____h413844[24] && + !_theResult____h413844[23] && + !_theResult____h413844[22] && + !_theResult____h413844[21] && + !_theResult____h413844[20] && + !_theResult____h413844[19] && + !_theResult____h413844[18] && + !_theResult____h413844[17] && + !_theResult____h413844[16] && + !_theResult____h413844[15] && + !_theResult____h413844[14] && + !_theResult____h413844[13] && + !_theResult____h413844[12] && + !_theResult____h413844[11] && + !_theResult____h413844[10] && + !_theResult____h413844[9] && + !_theResult____h413844[8] && + !_theResult____h413844[7] && + !_theResult____h413844[6] && + !_theResult____h413844[5] && + !_theResult____h413844[4] && + !_theResult____h413844[3] && + !_theResult____h413844[2] && + !_theResult____h413844[1] && + !_theResult____h413844[0]) ? + _theResult____h413844 : + _theResult___snd__h422122 ; + assign _theResult___snd__h422122 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q74[54:0], 2'd0 } ; - assign _theResult___snd__h422144 = - _theResult____h413843 << + assign _theResult___snd__h422145 = + _theResult____h413844 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6290 ; - assign _theResult___snd__h430712 = + assign _theResult___snd__h430713 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h430726 : - _theResult___snd__h412924 ; - assign _theResult___snd__h430726 = + _theResult___snd__h430727 : + _theResult___snd__h412925 ; + assign _theResult___snd__h430727 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5915) ? - sfd__h388604 : - _theResult___snd__h430732 ; - assign _theResult___snd__h430732 = + sfd__h388605 : + _theResult___snd__h430733 ; + assign _theResult___snd__h430733 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q79[54:0], 2'd0 } ; - assign _theResult___snd__h430750 = - sfd__h388604 << + assign _theResult___snd__h430751 = + sfd__h388605 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6364) ; - assign _theResult___snd__h450021 = { _theResult____h441901[55:0], 1'd0 } ; - assign _theResult___snd__h450032 = - (!_theResult____h441901[56] && _theResult____h441901[55]) ? - _theResult___snd__h450034 : - _theResult___snd__h450044 ; - assign _theResult___snd__h450034 = { _theResult____h441901[54:0], 2'd0 } ; - assign _theResult___snd__h450044 = - (!_theResult____h441901[56] && !_theResult____h441901[55] && - !_theResult____h441901[54] && - !_theResult____h441901[53] && - !_theResult____h441901[52] && - !_theResult____h441901[51] && - !_theResult____h441901[50] && - !_theResult____h441901[49] && - !_theResult____h441901[48] && - !_theResult____h441901[47] && - !_theResult____h441901[46] && - !_theResult____h441901[45] && - !_theResult____h441901[44] && - !_theResult____h441901[43] && - !_theResult____h441901[42] && - !_theResult____h441901[41] && - !_theResult____h441901[40] && - !_theResult____h441901[39] && - !_theResult____h441901[38] && - !_theResult____h441901[37] && - !_theResult____h441901[36] && - !_theResult____h441901[35] && - !_theResult____h441901[34] && - !_theResult____h441901[33] && - !_theResult____h441901[32] && - !_theResult____h441901[31] && - !_theResult____h441901[30] && - !_theResult____h441901[29] && - !_theResult____h441901[28] && - !_theResult____h441901[27] && - !_theResult____h441901[26] && - !_theResult____h441901[25] && - !_theResult____h441901[24] && - !_theResult____h441901[23] && - !_theResult____h441901[22] && - !_theResult____h441901[21] && - !_theResult____h441901[20] && - !_theResult____h441901[19] && - !_theResult____h441901[18] && - !_theResult____h441901[17] && - !_theResult____h441901[16] && - !_theResult____h441901[15] && - !_theResult____h441901[14] && - !_theResult____h441901[13] && - !_theResult____h441901[12] && - !_theResult____h441901[11] && - !_theResult____h441901[10] && - !_theResult____h441901[9] && - !_theResult____h441901[8] && - !_theResult____h441901[7] && - !_theResult____h441901[6] && - !_theResult____h441901[5] && - !_theResult____h441901[4] && - !_theResult____h441901[3] && - !_theResult____h441901[2] && - !_theResult____h441901[1] && - !_theResult____h441901[0]) ? - _theResult____h441901 : - _theResult___snd__h450050 ; - assign _theResult___snd__h450050 = + assign _theResult___snd__h450022 = { _theResult____h441902[55:0], 1'd0 } ; + assign _theResult___snd__h450033 = + (!_theResult____h441902[56] && _theResult____h441902[55]) ? + _theResult___snd__h450035 : + _theResult___snd__h450045 ; + assign _theResult___snd__h450035 = { _theResult____h441902[54:0], 2'd0 } ; + assign _theResult___snd__h450045 = + (!_theResult____h441902[56] && !_theResult____h441902[55] && + !_theResult____h441902[54] && + !_theResult____h441902[53] && + !_theResult____h441902[52] && + !_theResult____h441902[51] && + !_theResult____h441902[50] && + !_theResult____h441902[49] && + !_theResult____h441902[48] && + !_theResult____h441902[47] && + !_theResult____h441902[46] && + !_theResult____h441902[45] && + !_theResult____h441902[44] && + !_theResult____h441902[43] && + !_theResult____h441902[42] && + !_theResult____h441902[41] && + !_theResult____h441902[40] && + !_theResult____h441902[39] && + !_theResult____h441902[38] && + !_theResult____h441902[37] && + !_theResult____h441902[36] && + !_theResult____h441902[35] && + !_theResult____h441902[34] && + !_theResult____h441902[33] && + !_theResult____h441902[32] && + !_theResult____h441902[31] && + !_theResult____h441902[30] && + !_theResult____h441902[29] && + !_theResult____h441902[28] && + !_theResult____h441902[27] && + !_theResult____h441902[26] && + !_theResult____h441902[25] && + !_theResult____h441902[24] && + !_theResult____h441902[23] && + !_theResult____h441902[22] && + !_theResult____h441902[21] && + !_theResult____h441902[20] && + !_theResult____h441902[19] && + !_theResult____h441902[18] && + !_theResult____h441902[17] && + !_theResult____h441902[16] && + !_theResult____h441902[15] && + !_theResult____h441902[14] && + !_theResult____h441902[13] && + !_theResult____h441902[12] && + !_theResult____h441902[11] && + !_theResult____h441902[10] && + !_theResult____h441902[9] && + !_theResult____h441902[8] && + !_theResult____h441902[7] && + !_theResult____h441902[6] && + !_theResult____h441902[5] && + !_theResult____h441902[4] && + !_theResult____h441902[3] && + !_theResult____h441902[2] && + !_theResult____h441902[1] && + !_theResult____h441902[0]) ? + _theResult____h441902 : + _theResult___snd__h450051 ; + assign _theResult___snd__h450051 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q99[54:0], 2'd0 } ; - assign _theResult___snd__h450073 = - _theResult____h441901 << + assign _theResult___snd__h450074 = + _theResult____h441902 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7131 ; - assign _theResult___snd__h458617 = + assign _theResult___snd__h458618 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h458626 : - _theResult___snd__h458619 ; - assign _theResult___snd__h458619 = + _theResult___snd__h458627 : + _theResult___snd__h458620 ; + assign _theResult___snd__h458620 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h458626 = + assign _theResult___snd__h458627 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307) ? - sfd__h434299 : - _theResult___snd__h458632 ; - assign _theResult___snd__h458632 = + sfd__h434300 : + _theResult___snd__h458633 ; + assign _theResult___snd__h458633 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q101[54:0], 2'd0 } ; - assign _theResult___snd__h458655 = - sfd__h434299 << + assign _theResult___snd__h458656 = + sfd__h434300 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7362 ; - assign _theResult___snd__h467787 = { _theResult____h459538[55:0], 1'd0 } ; - assign _theResult___snd__h467798 = - (!_theResult____h459538[56] && _theResult____h459538[55]) ? - _theResult___snd__h467800 : - _theResult___snd__h467810 ; - assign _theResult___snd__h467800 = { _theResult____h459538[54:0], 2'd0 } ; - assign _theResult___snd__h467810 = - (!_theResult____h459538[56] && !_theResult____h459538[55] && - !_theResult____h459538[54] && - !_theResult____h459538[53] && - !_theResult____h459538[52] && - !_theResult____h459538[51] && - !_theResult____h459538[50] && - !_theResult____h459538[49] && - !_theResult____h459538[48] && - !_theResult____h459538[47] && - !_theResult____h459538[46] && - !_theResult____h459538[45] && - !_theResult____h459538[44] && - !_theResult____h459538[43] && - !_theResult____h459538[42] && - !_theResult____h459538[41] && - !_theResult____h459538[40] && - !_theResult____h459538[39] && - !_theResult____h459538[38] && - !_theResult____h459538[37] && - !_theResult____h459538[36] && - !_theResult____h459538[35] && - !_theResult____h459538[34] && - !_theResult____h459538[33] && - !_theResult____h459538[32] && - !_theResult____h459538[31] && - !_theResult____h459538[30] && - !_theResult____h459538[29] && - !_theResult____h459538[28] && - !_theResult____h459538[27] && - !_theResult____h459538[26] && - !_theResult____h459538[25] && - !_theResult____h459538[24] && - !_theResult____h459538[23] && - !_theResult____h459538[22] && - !_theResult____h459538[21] && - !_theResult____h459538[20] && - !_theResult____h459538[19] && - !_theResult____h459538[18] && - !_theResult____h459538[17] && - !_theResult____h459538[16] && - !_theResult____h459538[15] && - !_theResult____h459538[14] && - !_theResult____h459538[13] && - !_theResult____h459538[12] && - !_theResult____h459538[11] && - !_theResult____h459538[10] && - !_theResult____h459538[9] && - !_theResult____h459538[8] && - !_theResult____h459538[7] && - !_theResult____h459538[6] && - !_theResult____h459538[5] && - !_theResult____h459538[4] && - !_theResult____h459538[3] && - !_theResult____h459538[2] && - !_theResult____h459538[1] && - !_theResult____h459538[0]) ? - _theResult____h459538 : - _theResult___snd__h467816 ; - assign _theResult___snd__h467816 = + assign _theResult___snd__h467788 = { _theResult____h459539[55:0], 1'd0 } ; + assign _theResult___snd__h467799 = + (!_theResult____h459539[56] && _theResult____h459539[55]) ? + _theResult___snd__h467801 : + _theResult___snd__h467811 ; + assign _theResult___snd__h467801 = { _theResult____h459539[54:0], 2'd0 } ; + assign _theResult___snd__h467811 = + (!_theResult____h459539[56] && !_theResult____h459539[55] && + !_theResult____h459539[54] && + !_theResult____h459539[53] && + !_theResult____h459539[52] && + !_theResult____h459539[51] && + !_theResult____h459539[50] && + !_theResult____h459539[49] && + !_theResult____h459539[48] && + !_theResult____h459539[47] && + !_theResult____h459539[46] && + !_theResult____h459539[45] && + !_theResult____h459539[44] && + !_theResult____h459539[43] && + !_theResult____h459539[42] && + !_theResult____h459539[41] && + !_theResult____h459539[40] && + !_theResult____h459539[39] && + !_theResult____h459539[38] && + !_theResult____h459539[37] && + !_theResult____h459539[36] && + !_theResult____h459539[35] && + !_theResult____h459539[34] && + !_theResult____h459539[33] && + !_theResult____h459539[32] && + !_theResult____h459539[31] && + !_theResult____h459539[30] && + !_theResult____h459539[29] && + !_theResult____h459539[28] && + !_theResult____h459539[27] && + !_theResult____h459539[26] && + !_theResult____h459539[25] && + !_theResult____h459539[24] && + !_theResult____h459539[23] && + !_theResult____h459539[22] && + !_theResult____h459539[21] && + !_theResult____h459539[20] && + !_theResult____h459539[19] && + !_theResult____h459539[18] && + !_theResult____h459539[17] && + !_theResult____h459539[16] && + !_theResult____h459539[15] && + !_theResult____h459539[14] && + !_theResult____h459539[13] && + !_theResult____h459539[12] && + !_theResult____h459539[11] && + !_theResult____h459539[10] && + !_theResult____h459539[9] && + !_theResult____h459539[8] && + !_theResult____h459539[7] && + !_theResult____h459539[6] && + !_theResult____h459539[5] && + !_theResult____h459539[4] && + !_theResult____h459539[3] && + !_theResult____h459539[2] && + !_theResult____h459539[1] && + !_theResult____h459539[0]) ? + _theResult____h459539 : + _theResult___snd__h467817 ; + assign _theResult___snd__h467817 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q109[54:0], 2'd0 } ; - assign _theResult___snd__h467839 = - _theResult____h459538 << + assign _theResult___snd__h467840 = + _theResult____h459539 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7682 ; - assign _theResult___snd__h476407 = + assign _theResult___snd__h476408 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h476421 : - _theResult___snd__h458619 ; - assign _theResult___snd__h476421 = + _theResult___snd__h476422 : + _theResult___snd__h458620 ; + assign _theResult___snd__h476422 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7307) ? - sfd__h434299 : - _theResult___snd__h476427 ; - assign _theResult___snd__h476427 = + sfd__h434300 : + _theResult___snd__h476428 ; + assign _theResult___snd__h476428 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q114[54:0], 2'd0 } ; - assign _theResult___snd__h476445 = - sfd__h434299 << + assign _theResult___snd__h476446 = + sfd__h434300 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7756) ; - assign _theResult___snd__h506409 = - (f1_exp__h487070 == 8'd0) ? - _theResult___snd__h506418 : - _theResult___snd__h506411 ; - assign _theResult___snd__h506411 = { f1_sfd__h487071, 34'd0 } ; - assign _theResult___snd__h506418 = - (f1_exp__h487070 == 8'd0 && !f1_sfd__h487071[22] && + assign _theResult___snd__h506410 = + (f1_exp__h487071 == 8'd0) ? + _theResult___snd__h506419 : + _theResult___snd__h506412 ; + assign _theResult___snd__h506412 = { f1_sfd__h487072, 34'd0 } ; + assign _theResult___snd__h506419 = + (f1_exp__h487071 == 8'd0 && !f1_sfd__h487072[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671) ? - sfd__h487432 : - _theResult___snd__h506424 ; - assign _theResult___snd__h506424 = + sfd__h487433 : + _theResult___snd__h506425 ; + assign _theResult___snd__h506425 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h506447 = - sfd__h487432 << + assign _theResult___snd__h506448 = + sfd__h487433 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8698 ; - assign _theResult___snd__h516046 = { _theResult____h507799[55:0], 1'd0 } ; - assign _theResult___snd__h516057 = - (!_theResult____h507799[56] && _theResult____h507799[55]) ? - _theResult___snd__h516059 : - _theResult___snd__h516069 ; - assign _theResult___snd__h516059 = { _theResult____h507799[54:0], 2'd0 } ; - assign _theResult___snd__h516069 = - (!_theResult____h507799[56] && !_theResult____h507799[55] && - !_theResult____h507799[54] && - !_theResult____h507799[53] && - !_theResult____h507799[52] && - !_theResult____h507799[51] && - !_theResult____h507799[50] && - !_theResult____h507799[49] && - !_theResult____h507799[48] && - !_theResult____h507799[47] && - !_theResult____h507799[46] && - !_theResult____h507799[45] && - !_theResult____h507799[44] && - !_theResult____h507799[43] && - !_theResult____h507799[42] && - !_theResult____h507799[41] && - !_theResult____h507799[40] && - !_theResult____h507799[39] && - !_theResult____h507799[38] && - !_theResult____h507799[37] && - !_theResult____h507799[36] && - !_theResult____h507799[35] && - !_theResult____h507799[34] && - !_theResult____h507799[33] && - !_theResult____h507799[32] && - !_theResult____h507799[31] && - !_theResult____h507799[30] && - !_theResult____h507799[29] && - !_theResult____h507799[28] && - !_theResult____h507799[27] && - !_theResult____h507799[26] && - !_theResult____h507799[25] && - !_theResult____h507799[24] && - !_theResult____h507799[23] && - !_theResult____h507799[22] && - !_theResult____h507799[21] && - !_theResult____h507799[20] && - !_theResult____h507799[19] && - !_theResult____h507799[18] && - !_theResult____h507799[17] && - !_theResult____h507799[16] && - !_theResult____h507799[15] && - !_theResult____h507799[14] && - !_theResult____h507799[13] && - !_theResult____h507799[12] && - !_theResult____h507799[11] && - !_theResult____h507799[10] && - !_theResult____h507799[9] && - !_theResult____h507799[8] && - !_theResult____h507799[7] && - !_theResult____h507799[6] && - !_theResult____h507799[5] && - !_theResult____h507799[4] && - !_theResult____h507799[3] && - !_theResult____h507799[2] && - !_theResult____h507799[1] && - !_theResult____h507799[0]) ? - _theResult____h507799 : - _theResult___snd__h516075 ; - assign _theResult___snd__h516075 = + assign _theResult___snd__h516047 = { _theResult____h507800[55:0], 1'd0 } ; + assign _theResult___snd__h516058 = + (!_theResult____h507800[56] && _theResult____h507800[55]) ? + _theResult___snd__h516060 : + _theResult___snd__h516070 ; + assign _theResult___snd__h516060 = { _theResult____h507800[54:0], 2'd0 } ; + assign _theResult___snd__h516070 = + (!_theResult____h507800[56] && !_theResult____h507800[55] && + !_theResult____h507800[54] && + !_theResult____h507800[53] && + !_theResult____h507800[52] && + !_theResult____h507800[51] && + !_theResult____h507800[50] && + !_theResult____h507800[49] && + !_theResult____h507800[48] && + !_theResult____h507800[47] && + !_theResult____h507800[46] && + !_theResult____h507800[45] && + !_theResult____h507800[44] && + !_theResult____h507800[43] && + !_theResult____h507800[42] && + !_theResult____h507800[41] && + !_theResult____h507800[40] && + !_theResult____h507800[39] && + !_theResult____h507800[38] && + !_theResult____h507800[37] && + !_theResult____h507800[36] && + !_theResult____h507800[35] && + !_theResult____h507800[34] && + !_theResult____h507800[33] && + !_theResult____h507800[32] && + !_theResult____h507800[31] && + !_theResult____h507800[30] && + !_theResult____h507800[29] && + !_theResult____h507800[28] && + !_theResult____h507800[27] && + !_theResult____h507800[26] && + !_theResult____h507800[25] && + !_theResult____h507800[24] && + !_theResult____h507800[23] && + !_theResult____h507800[22] && + !_theResult____h507800[21] && + !_theResult____h507800[20] && + !_theResult____h507800[19] && + !_theResult____h507800[18] && + !_theResult____h507800[17] && + !_theResult____h507800[16] && + !_theResult____h507800[15] && + !_theResult____h507800[14] && + !_theResult____h507800[13] && + !_theResult____h507800[12] && + !_theResult____h507800[11] && + !_theResult____h507800[10] && + !_theResult____h507800[9] && + !_theResult____h507800[8] && + !_theResult____h507800[7] && + !_theResult____h507800[6] && + !_theResult____h507800[5] && + !_theResult____h507800[4] && + !_theResult____h507800[3] && + !_theResult____h507800[2] && + !_theResult____h507800[1] && + !_theResult____h507800[0]) ? + _theResult____h507800 : + _theResult___snd__h516076 ; + assign _theResult___snd__h516076 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h516098 = - _theResult____h507799 << + assign _theResult___snd__h516099 = + _theResult____h507800 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9010 ; - assign _theResult___snd__h524814 = - (f1_exp__h487070 == 8'd0) ? - _theResult___snd__h524828 : - _theResult___snd__h506411 ; - assign _theResult___snd__h524828 = - (f1_exp__h487070 == 8'd0 && !f1_sfd__h487071[22] && + assign _theResult___snd__h524815 = + (f1_exp__h487071 == 8'd0) ? + _theResult___snd__h524829 : + _theResult___snd__h506412 ; + assign _theResult___snd__h524829 = + (f1_exp__h487071 == 8'd0 && !f1_sfd__h487072[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8671) ? - sfd__h487432 : - _theResult___snd__h524834 ; - assign _theResult___snd__h524834 = + sfd__h487433 : + _theResult___snd__h524835 ; + assign _theResult___snd__h524835 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h524852 = - sfd__h487432 << + assign _theResult___snd__h524853 = + sfd__h487433 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9061 ; - assign _theResult___snd__h545262 = - (f2_exp__h526064 == 8'd0) ? - _theResult___snd__h545271 : - _theResult___snd__h545264 ; - assign _theResult___snd__h545264 = { f2_sfd__h526065, 34'd0 } ; - assign _theResult___snd__h545271 = - (f2_exp__h526064 == 8'd0 && !f2_sfd__h526065[22] && + assign _theResult___snd__h545263 = + (f2_exp__h526065 == 8'd0) ? + _theResult___snd__h545272 : + _theResult___snd__h545265 ; + assign _theResult___snd__h545265 = { f2_sfd__h526066, 34'd0 } ; + assign _theResult___snd__h545272 = + (f2_exp__h526065 == 8'd0 && !f2_sfd__h526066[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171) ? - sfd__h526426 : - _theResult___snd__h545277 ; - assign _theResult___snd__h545277 = + sfd__h526427 : + _theResult___snd__h545278 ; + assign _theResult___snd__h545278 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h545300 = - sfd__h526426 << + assign _theResult___snd__h545301 = + sfd__h526427 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10198 ; - assign _theResult___snd__h554899 = { _theResult____h546652[55:0], 1'd0 } ; - assign _theResult___snd__h554910 = - (!_theResult____h546652[56] && _theResult____h546652[55]) ? - _theResult___snd__h554912 : - _theResult___snd__h554922 ; - assign _theResult___snd__h554912 = { _theResult____h546652[54:0], 2'd0 } ; - assign _theResult___snd__h554922 = - (!_theResult____h546652[56] && !_theResult____h546652[55] && - !_theResult____h546652[54] && - !_theResult____h546652[53] && - !_theResult____h546652[52] && - !_theResult____h546652[51] && - !_theResult____h546652[50] && - !_theResult____h546652[49] && - !_theResult____h546652[48] && - !_theResult____h546652[47] && - !_theResult____h546652[46] && - !_theResult____h546652[45] && - !_theResult____h546652[44] && - !_theResult____h546652[43] && - !_theResult____h546652[42] && - !_theResult____h546652[41] && - !_theResult____h546652[40] && - !_theResult____h546652[39] && - !_theResult____h546652[38] && - !_theResult____h546652[37] && - !_theResult____h546652[36] && - !_theResult____h546652[35] && - !_theResult____h546652[34] && - !_theResult____h546652[33] && - !_theResult____h546652[32] && - !_theResult____h546652[31] && - !_theResult____h546652[30] && - !_theResult____h546652[29] && - !_theResult____h546652[28] && - !_theResult____h546652[27] && - !_theResult____h546652[26] && - !_theResult____h546652[25] && - !_theResult____h546652[24] && - !_theResult____h546652[23] && - !_theResult____h546652[22] && - !_theResult____h546652[21] && - !_theResult____h546652[20] && - !_theResult____h546652[19] && - !_theResult____h546652[18] && - !_theResult____h546652[17] && - !_theResult____h546652[16] && - !_theResult____h546652[15] && - !_theResult____h546652[14] && - !_theResult____h546652[13] && - !_theResult____h546652[12] && - !_theResult____h546652[11] && - !_theResult____h546652[10] && - !_theResult____h546652[9] && - !_theResult____h546652[8] && - !_theResult____h546652[7] && - !_theResult____h546652[6] && - !_theResult____h546652[5] && - !_theResult____h546652[4] && - !_theResult____h546652[3] && - !_theResult____h546652[2] && - !_theResult____h546652[1] && - !_theResult____h546652[0]) ? - _theResult____h546652 : - _theResult___snd__h554928 ; - assign _theResult___snd__h554928 = + assign _theResult___snd__h554900 = { _theResult____h546653[55:0], 1'd0 } ; + assign _theResult___snd__h554911 = + (!_theResult____h546653[56] && _theResult____h546653[55]) ? + _theResult___snd__h554913 : + _theResult___snd__h554923 ; + assign _theResult___snd__h554913 = { _theResult____h546653[54:0], 2'd0 } ; + assign _theResult___snd__h554923 = + (!_theResult____h546653[56] && !_theResult____h546653[55] && + !_theResult____h546653[54] && + !_theResult____h546653[53] && + !_theResult____h546653[52] && + !_theResult____h546653[51] && + !_theResult____h546653[50] && + !_theResult____h546653[49] && + !_theResult____h546653[48] && + !_theResult____h546653[47] && + !_theResult____h546653[46] && + !_theResult____h546653[45] && + !_theResult____h546653[44] && + !_theResult____h546653[43] && + !_theResult____h546653[42] && + !_theResult____h546653[41] && + !_theResult____h546653[40] && + !_theResult____h546653[39] && + !_theResult____h546653[38] && + !_theResult____h546653[37] && + !_theResult____h546653[36] && + !_theResult____h546653[35] && + !_theResult____h546653[34] && + !_theResult____h546653[33] && + !_theResult____h546653[32] && + !_theResult____h546653[31] && + !_theResult____h546653[30] && + !_theResult____h546653[29] && + !_theResult____h546653[28] && + !_theResult____h546653[27] && + !_theResult____h546653[26] && + !_theResult____h546653[25] && + !_theResult____h546653[24] && + !_theResult____h546653[23] && + !_theResult____h546653[22] && + !_theResult____h546653[21] && + !_theResult____h546653[20] && + !_theResult____h546653[19] && + !_theResult____h546653[18] && + !_theResult____h546653[17] && + !_theResult____h546653[16] && + !_theResult____h546653[15] && + !_theResult____h546653[14] && + !_theResult____h546653[13] && + !_theResult____h546653[12] && + !_theResult____h546653[11] && + !_theResult____h546653[10] && + !_theResult____h546653[9] && + !_theResult____h546653[8] && + !_theResult____h546653[7] && + !_theResult____h546653[6] && + !_theResult____h546653[5] && + !_theResult____h546653[4] && + !_theResult____h546653[3] && + !_theResult____h546653[2] && + !_theResult____h546653[1] && + !_theResult____h546653[0]) ? + _theResult____h546653 : + _theResult___snd__h554929 ; + assign _theResult___snd__h554929 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h554951 = - _theResult____h546652 << + assign _theResult___snd__h554952 = + _theResult____h546653 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10495 ; - assign _theResult___snd__h563667 = - (f2_exp__h526064 == 8'd0) ? - _theResult___snd__h563681 : - _theResult___snd__h545264 ; - assign _theResult___snd__h563681 = - (f2_exp__h526064 == 8'd0 && !f2_sfd__h526065[22] && + assign _theResult___snd__h563668 = + (f2_exp__h526065 == 8'd0) ? + _theResult___snd__h563682 : + _theResult___snd__h545265 ; + assign _theResult___snd__h563682 = + (f2_exp__h526065 == 8'd0 && !f2_sfd__h526066[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10171) ? - sfd__h526426 : - _theResult___snd__h563687 ; - assign _theResult___snd__h563687 = + sfd__h526427 : + _theResult___snd__h563688 ; + assign _theResult___snd__h563688 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h563705 = - sfd__h526426 << + assign _theResult___snd__h563706 = + sfd__h526427 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10546 ; - assign _theResult___snd__h584566 = - (f3_exp__h565368 == 8'd0) ? - _theResult___snd__h584575 : - _theResult___snd__h584568 ; - assign _theResult___snd__h584568 = { f3_sfd__h565369, 34'd0 } ; - assign _theResult___snd__h584575 = - (f3_exp__h565368 == 8'd0 && !f3_sfd__h565369[22] && + assign _theResult___snd__h584567 = + (f3_exp__h565369 == 8'd0) ? + _theResult___snd__h584576 : + _theResult___snd__h584569 ; + assign _theResult___snd__h584569 = { f3_sfd__h565370, 34'd0 } ; + assign _theResult___snd__h584576 = + (f3_exp__h565369 == 8'd0 && !f3_sfd__h565370[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401) ? - sfd__h565730 : - _theResult___snd__h584581 ; - assign _theResult___snd__h584581 = + sfd__h565731 : + _theResult___snd__h584582 ; + assign _theResult___snd__h584582 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h584604 = - sfd__h565730 << + assign _theResult___snd__h584605 = + sfd__h565731 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9428 ; - assign _theResult___snd__h594203 = { _theResult____h585956[55:0], 1'd0 } ; - assign _theResult___snd__h594214 = - (!_theResult____h585956[56] && _theResult____h585956[55]) ? - _theResult___snd__h594216 : - _theResult___snd__h594226 ; - assign _theResult___snd__h594216 = { _theResult____h585956[54:0], 2'd0 } ; - assign _theResult___snd__h594226 = - (!_theResult____h585956[56] && !_theResult____h585956[55] && - !_theResult____h585956[54] && - !_theResult____h585956[53] && - !_theResult____h585956[52] && - !_theResult____h585956[51] && - !_theResult____h585956[50] && - !_theResult____h585956[49] && - !_theResult____h585956[48] && - !_theResult____h585956[47] && - !_theResult____h585956[46] && - !_theResult____h585956[45] && - !_theResult____h585956[44] && - !_theResult____h585956[43] && - !_theResult____h585956[42] && - !_theResult____h585956[41] && - !_theResult____h585956[40] && - !_theResult____h585956[39] && - !_theResult____h585956[38] && - !_theResult____h585956[37] && - !_theResult____h585956[36] && - !_theResult____h585956[35] && - !_theResult____h585956[34] && - !_theResult____h585956[33] && - !_theResult____h585956[32] && - !_theResult____h585956[31] && - !_theResult____h585956[30] && - !_theResult____h585956[29] && - !_theResult____h585956[28] && - !_theResult____h585956[27] && - !_theResult____h585956[26] && - !_theResult____h585956[25] && - !_theResult____h585956[24] && - !_theResult____h585956[23] && - !_theResult____h585956[22] && - !_theResult____h585956[21] && - !_theResult____h585956[20] && - !_theResult____h585956[19] && - !_theResult____h585956[18] && - !_theResult____h585956[17] && - !_theResult____h585956[16] && - !_theResult____h585956[15] && - !_theResult____h585956[14] && - !_theResult____h585956[13] && - !_theResult____h585956[12] && - !_theResult____h585956[11] && - !_theResult____h585956[10] && - !_theResult____h585956[9] && - !_theResult____h585956[8] && - !_theResult____h585956[7] && - !_theResult____h585956[6] && - !_theResult____h585956[5] && - !_theResult____h585956[4] && - !_theResult____h585956[3] && - !_theResult____h585956[2] && - !_theResult____h585956[1] && - !_theResult____h585956[0]) ? - _theResult____h585956 : - _theResult___snd__h594232 ; - assign _theResult___snd__h594232 = + assign _theResult___snd__h594204 = { _theResult____h585957[55:0], 1'd0 } ; + assign _theResult___snd__h594215 = + (!_theResult____h585957[56] && _theResult____h585957[55]) ? + _theResult___snd__h594217 : + _theResult___snd__h594227 ; + assign _theResult___snd__h594217 = { _theResult____h585957[54:0], 2'd0 } ; + assign _theResult___snd__h594227 = + (!_theResult____h585957[56] && !_theResult____h585957[55] && + !_theResult____h585957[54] && + !_theResult____h585957[53] && + !_theResult____h585957[52] && + !_theResult____h585957[51] && + !_theResult____h585957[50] && + !_theResult____h585957[49] && + !_theResult____h585957[48] && + !_theResult____h585957[47] && + !_theResult____h585957[46] && + !_theResult____h585957[45] && + !_theResult____h585957[44] && + !_theResult____h585957[43] && + !_theResult____h585957[42] && + !_theResult____h585957[41] && + !_theResult____h585957[40] && + !_theResult____h585957[39] && + !_theResult____h585957[38] && + !_theResult____h585957[37] && + !_theResult____h585957[36] && + !_theResult____h585957[35] && + !_theResult____h585957[34] && + !_theResult____h585957[33] && + !_theResult____h585957[32] && + !_theResult____h585957[31] && + !_theResult____h585957[30] && + !_theResult____h585957[29] && + !_theResult____h585957[28] && + !_theResult____h585957[27] && + !_theResult____h585957[26] && + !_theResult____h585957[25] && + !_theResult____h585957[24] && + !_theResult____h585957[23] && + !_theResult____h585957[22] && + !_theResult____h585957[21] && + !_theResult____h585957[20] && + !_theResult____h585957[19] && + !_theResult____h585957[18] && + !_theResult____h585957[17] && + !_theResult____h585957[16] && + !_theResult____h585957[15] && + !_theResult____h585957[14] && + !_theResult____h585957[13] && + !_theResult____h585957[12] && + !_theResult____h585957[11] && + !_theResult____h585957[10] && + !_theResult____h585957[9] && + !_theResult____h585957[8] && + !_theResult____h585957[7] && + !_theResult____h585957[6] && + !_theResult____h585957[5] && + !_theResult____h585957[4] && + !_theResult____h585957[3] && + !_theResult____h585957[2] && + !_theResult____h585957[1] && + !_theResult____h585957[0]) ? + _theResult____h585957 : + _theResult___snd__h594233 ; + assign _theResult___snd__h594233 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h594255 = - _theResult____h585956 << + assign _theResult___snd__h594256 = + _theResult____h585957 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9725 ; - assign _theResult___snd__h602971 = - (f3_exp__h565368 == 8'd0) ? - _theResult___snd__h602985 : - _theResult___snd__h584568 ; - assign _theResult___snd__h602985 = - (f3_exp__h565368 == 8'd0 && !f3_sfd__h565369[22] && + assign _theResult___snd__h602972 = + (f3_exp__h565369 == 8'd0) ? + _theResult___snd__h602986 : + _theResult___snd__h584569 ; + assign _theResult___snd__h602986 = + (f3_exp__h565369 == 8'd0 && !f3_sfd__h565370[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9401) ? - sfd__h565730 : - _theResult___snd__h602991 ; - assign _theResult___snd__h602991 = + sfd__h565731 : + _theResult___snd__h602992 ; + assign _theResult___snd__h602992 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h603009 = - sfd__h565730 << + assign _theResult___snd__h603010 = + sfd__h565731 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9776 ; - assign _theResult___snd__h608465 = - b__h607917[63] ? b___1__h608530 : b__h607917 ; - assign _theResult___snd_fst_exp__h367800 = + assign _theResult___snd__h608466 = + b__h607918[63] ? b___1__h608531 : b__h607918 ; + assign _theResult___snd_fst_exp__h367801 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - _theResult___fst_exp__h359215 : - _theResult___fst_exp__h367797 ; - assign _theResult___snd_fst_exp__h385620 = + _theResult___fst_exp__h359216 : + _theResult___fst_exp__h367798 ; + assign _theResult___snd_fst_exp__h385621 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - _theResult___fst_exp__h376981 : - _theResult___fst_exp__h385617 ; - assign _theResult___snd_fst_exp__h413497 = + _theResult___fst_exp__h376982 : + _theResult___fst_exp__h385618 ; + assign _theResult___snd_fst_exp__h413498 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - _theResult___fst_exp__h404912 : - _theResult___fst_exp__h413494 ; - assign _theResult___snd_fst_exp__h431317 = + _theResult___fst_exp__h404913 : + _theResult___fst_exp__h413495 ; + assign _theResult___snd_fst_exp__h431318 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - _theResult___fst_exp__h422678 : - _theResult___fst_exp__h431314 ; - assign _theResult___snd_fst_exp__h459192 = + _theResult___fst_exp__h422679 : + _theResult___fst_exp__h431315 ; + assign _theResult___snd_fst_exp__h459193 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - _theResult___fst_exp__h450607 : - _theResult___fst_exp__h459189 ; - assign _theResult___snd_fst_exp__h477012 = + _theResult___fst_exp__h450608 : + _theResult___fst_exp__h459190 ; + assign _theResult___snd_fst_exp__h477013 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - _theResult___fst_exp__h468373 : - _theResult___fst_exp__h477009 ; - assign _theResult___snd_fst_exp__h507219 = + _theResult___fst_exp__h468374 : + _theResult___fst_exp__h477010 ; + assign _theResult___snd_fst_exp__h507220 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 ? 11'd0 : - _theResult___fst_exp__h507216 ; - assign _theResult___snd_fst_exp__h525654 = + _theResult___fst_exp__h507217 ; + assign _theResult___snd_fst_exp__h525655 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? - _theResult___fst_exp__h516867 : - _theResult___fst_exp__h525651 ; - assign _theResult___snd_fst_exp__h546072 = + _theResult___fst_exp__h516868 : + _theResult___fst_exp__h525652 ; + assign _theResult___snd_fst_exp__h546073 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 ? 11'd0 : - _theResult___fst_exp__h546069 ; - assign _theResult___snd_fst_exp__h564507 = + _theResult___fst_exp__h546070 ; + assign _theResult___snd_fst_exp__h564508 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? - _theResult___fst_exp__h555720 : - _theResult___fst_exp__h564504 ; - assign _theResult___snd_fst_exp__h585376 = + _theResult___fst_exp__h555721 : + _theResult___fst_exp__h564505 ; + assign _theResult___snd_fst_exp__h585377 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 ? 11'd0 : - _theResult___fst_exp__h585373 ; - assign _theResult___snd_fst_exp__h603811 = + _theResult___fst_exp__h585374 ; + assign _theResult___snd_fst_exp__h603812 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? - _theResult___fst_exp__h595024 : - _theResult___fst_exp__h603808 ; - assign _theResult___snd_fst_sfd__h342852 = + _theResult___fst_exp__h595025 : + _theResult___fst_exp__h603809 ; + assign _theResult___snd_fst_sfd__h342853 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h367801 = + assign _theResult___snd_fst_sfd__h367802 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4113 ? - _theResult___fst_sfd__h359216 : - _theResult___fst_sfd__h367798 ; - assign _theResult___snd_fst_sfd__h385621 = + _theResult___fst_sfd__h359217 : + _theResult___fst_sfd__h367799 ; + assign _theResult___snd_fst_sfd__h385622 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4653 ? - _theResult___fst_sfd__h376982 : - _theResult___fst_sfd__h385618 ; - assign _theResult___snd_fst_sfd__h388554 = + _theResult___fst_sfd__h376983 : + _theResult___fst_sfd__h385619 ; + assign _theResult___snd_fst_sfd__h388555 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h413498 = + assign _theResult___snd_fst_sfd__h413499 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5505 ? - _theResult___fst_sfd__h404913 : - _theResult___fst_sfd__h413495 ; - assign _theResult___snd_fst_sfd__h431318 = + _theResult___fst_sfd__h404914 : + _theResult___fst_sfd__h413496 ; + assign _theResult___snd_fst_sfd__h431319 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6045 ? - _theResult___fst_sfd__h422679 : - _theResult___fst_sfd__h431315 ; - assign _theResult___snd_fst_sfd__h434249 = + _theResult___fst_sfd__h422680 : + _theResult___fst_sfd__h431316 ; + assign _theResult___snd_fst_sfd__h434250 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h459193 = + assign _theResult___snd_fst_sfd__h459194 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6897 ? - _theResult___fst_sfd__h450608 : - _theResult___fst_sfd__h459190 ; - assign _theResult___snd_fst_sfd__h477013 = + _theResult___fst_sfd__h450609 : + _theResult___fst_sfd__h459191 ; + assign _theResult___snd_fst_sfd__h477014 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7437 ? - _theResult___fst_sfd__h468374 : - _theResult___fst_sfd__h477010 ; - assign _theResult___snd_fst_sfd__h487386 = - (f1_sfd__h487071 == 23'd0) ? + _theResult___fst_sfd__h468375 : + _theResult___fst_sfd__h477011 ; + assign _theResult___snd_fst_sfd__h487387 = + (f1_sfd__h487072 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h487134 ; - assign _theResult___snd_fst_sfd__h507220 = + out___1_sfd__h487135 ; + assign _theResult___snd_fst_sfd__h507221 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8627 ? 52'd0 : - _theResult___fst_sfd__h507217 ; - assign _theResult___snd_fst_sfd__h525655 = + _theResult___fst_sfd__h507218 ; + assign _theResult___snd_fst_sfd__h525656 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8763 ? - _theResult___fst_sfd__h516868 : - _theResult___fst_sfd__h525652 ; - assign _theResult___snd_fst_sfd__h526380 = - (f2_sfd__h526065 == 23'd0) ? + _theResult___fst_sfd__h516869 : + _theResult___fst_sfd__h525653 ; + assign _theResult___snd_fst_sfd__h526381 = + (f2_sfd__h526066 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h526128 ; - assign _theResult___snd_fst_sfd__h546073 = + out___1_sfd__h526129 ; + assign _theResult___snd_fst_sfd__h546074 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10127 ? 52'd0 : - _theResult___fst_sfd__h546070 ; - assign _theResult___snd_fst_sfd__h564508 = + _theResult___fst_sfd__h546071 ; + assign _theResult___snd_fst_sfd__h564509 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10248 ? - _theResult___fst_sfd__h555721 : - _theResult___fst_sfd__h564505 ; - assign _theResult___snd_fst_sfd__h565684 = - (f3_sfd__h565369 == 23'd0) ? + _theResult___fst_sfd__h555722 : + _theResult___fst_sfd__h564506 ; + assign _theResult___snd_fst_sfd__h565685 = + (f3_sfd__h565370 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h565432 ; - assign _theResult___snd_fst_sfd__h585377 = + out___1_sfd__h565433 ; + assign _theResult___snd_fst_sfd__h585378 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9357 ? 52'd0 : - _theResult___fst_sfd__h585374 ; - assign _theResult___snd_fst_sfd__h603812 = + _theResult___fst_sfd__h585375 ; + assign _theResult___snd_fst_sfd__h603813 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9478 ? - _theResult___fst_sfd__h595025 : - _theResult___fst_sfd__h603809 ; - assign a___1__h608078 = + _theResult___fst_sfd__h595026 : + _theResult___fst_sfd__h603810 ; + assign a___1__h608079 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q12 } ; - assign a___1__h608469 = 64'd0 - a__h607916 ; - assign a__h607916 = + assign a___1__h608470 = 64'd0 - a__h607917 ; + assign a__h607917 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h608078 : + a___1__h608079 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h608079 = + assign b___1__h608080 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h608530 = 64'd0 - b__h607917 ; - assign b__h607917 = + assign b___1__h608531 = 64'd0 - b__h607918 ; + assign b__h607918 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h608079 : + b___1__h608080 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign b__h608064 = { {64{a__h607916[63]}}, a__h607916 } ; - assign b__h608140 = { {64{b__h607917[63]}}, b__h607917 } ; - assign b__h608241 = { 64'd0, a__h607916 } ; - assign b__h608253 = { 64'd0, b__h607917 } ; - assign base__h721348 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h721368 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h718388 = - commitStage_commitTrap[36] ? i__h718563 : i__h718403 ; + assign b__h608065 = { {64{a__h607917[63]}}, a__h607917 } ; + assign b__h608141 = { {64{b__h607918[63]}}, b__h607918 } ; + assign b__h608242 = { 64'd0, a__h607917 } ; + assign b__h608254 = { 64'd0, b__h607918 } ; + assign base__h721349 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h721369 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h718389 = + commitStage_commitTrap[36] ? i__h718564 : i__h718404 ; assign commitStage_commitTrap_4654_BIT_36_4901_AND_co_ETC___d14966 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && @@ -29822,10 +29822,10 @@ module mkCore(CLK, commitStage_f_rob_data$D_OUT[166] ? CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, - trap_val__h718389, + trap_val__h718390, IF_commitStage_f_rob_data_first__5067_BITS_97__ETC___d15238 } ; assign commitStage_rg_serial_num_4635_PLUS_IF_rob_deq_ETC___d15776 = - commitStage_rg_serial_num + y__h740125 ; + commitStage_rg_serial_num + y__h739996 ; assign coreFix_aluExe_0_bypassWire_0_wget__2411_BITS__ETC___d12413 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -30012,9 +30012,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10922 | - ((f3_exp__h565368 != 8'd255 || f3_sfd__h565369 == 23'd0) && - (f3_exp__h565368 != 8'd255 || f3_sfd__h565369 != 23'd0) && - (f3_exp__h565368 != 8'd0 || f3_sfd__h565369 != 23'd0) && + ((f3_exp__h565369 != 8'd255 || f3_sfd__h565370 == 23'd0) && + (f3_exp__h565369 != 8'd255 || f3_sfd__h565370 != 23'd0) && + (f3_exp__h565369 != 8'd0 || f3_sfd__h565370 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10962) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11003 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -30022,9 +30022,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10991 | - ((f3_exp__h565368 != 8'd255 || f3_sfd__h565369 == 23'd0) && - (f3_exp__h565368 != 8'd255 || f3_sfd__h565369 != 23'd0) && - (f3_exp__h565368 != 8'd0 || f3_sfd__h565369 != 23'd0) && + ((f3_exp__h565369 != 8'd255 || f3_sfd__h565370 == 23'd0) && + (f3_exp__h565369 != 8'd255 || f3_sfd__h565370 != 23'd0) && + (f3_exp__h565369 != 8'd0 || f3_sfd__h565370 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10998) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11051 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -30032,9 +30032,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11035 | - ((f3_exp__h565368 != 8'd255 || f3_sfd__h565369 == 23'd0) && - (f3_exp__h565368 != 8'd255 || f3_sfd__h565369 != 23'd0) && - (f3_exp__h565368 != 8'd0 || f3_sfd__h565369 != 23'd0) && + ((f3_exp__h565369 != 8'd255 || f3_sfd__h565370 == 23'd0) && + (f3_exp__h565369 != 8'd255 || f3_sfd__h565370 != 23'd0) && + (f3_exp__h565369 != 8'd0 || f3_sfd__h565370 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11046) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11093 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -30042,9 +30042,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11079 | - ((f3_exp__h565368 != 8'd255 || f3_sfd__h565369 == 23'd0) && - (f3_exp__h565368 != 8'd255 || f3_sfd__h565369 != 23'd0) && - (f3_exp__h565368 != 8'd0 || f3_sfd__h565369 != 23'd0) && + ((f3_exp__h565369 != 8'd255 || f3_sfd__h565370 == 23'd0) && + (f3_exp__h565369 != 8'd255 || f3_sfd__h565370 != 23'd0) && + (f3_exp__h565369 != 8'd0 || f3_sfd__h565370 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11088) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d11135 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -30052,9 +30052,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11121 | - ((f3_exp__h565368 != 8'd255 || f3_sfd__h565369 == 23'd0) && - (f3_exp__h565368 != 8'd255 || f3_sfd__h565369 != 23'd0) && - (f3_exp__h565368 != 8'd0 || f3_sfd__h565369 != 23'd0) && + ((f3_exp__h565369 != 8'd255 || f3_sfd__h565370 == 23'd0) && + (f3_exp__h565369 != 8'd255 || f3_sfd__h565370 != 23'd0) && + (f3_exp__h565369 != 8'd0 || f3_sfd__h565370 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11130) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q13 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -30100,7 +30100,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h258551 ; + y__h258552 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3167 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3131 || @@ -30356,15 +30356,15 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_deqReq_rl) && coreFix_memExe_forwardQ_full ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1734 = - { coreFix_memExe_lsq$getOrigBE << x__h186793[2:0], - x__h186793, + { coreFix_memExe_lsq$getOrigBE << x__h186794[2:0], + x__h186794, coreFix_memExe_regToExeQ$first[75:12], coreFix_memExe_lsq$getOrigBE, coreFix_memExe_lsq$getOrigBE[7] ? - x__h186793[2:0] != 3'd0 : + x__h186794[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - x__h186793[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && x__h186793[0]) } ; + x__h186794[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && x__h186794[0]) } ; assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3765 = coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3734 || @@ -30452,7 +30452,7 @@ module mkCore(CLK, v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign csr_addr__h662585 = + assign csr_addr__h662586 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2992_BITS_172_ETC___d13208 : 12'hCFF ; @@ -30468,7 +30468,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13273 || csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 || - csr_addr__h662585 == 12'h8FF) ; + csr_addr__h662586 == 12'h8FF) ; assign csrf_fs_reg_read__1746_EQ_0_3232_AND_fetchStag_ETC___d13747 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -30500,30 +30500,30 @@ module mkCore(CLK, _0b0_CONCAT_csrf_medeleg_15_reg_read__1845_1846_ETC___d15028) ; assign csrf_prv_reg_read__3022_ULE_1___d15008 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__3022_ULT_IF_fetchStage_pipe_ETC___d13275 = - csrf_prv_reg < csr_addr__h662585[9:8] ; + csrf_prv_reg < csr_addr__h662586[9:8] ; assign csrf_rg_dcsr_read__1920_BIT_2_3297_OR_NOT_fetc_ETC___d13743 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2989_AND__ETC___d13681 ; - assign data78995_BITS_31_TO_0__q11 = data__h478995[31:0] ; - assign data79889_BITS_31_TO_0__q14 = data__h479889[31:0] ; - assign data___1__h479507 = - { {32{data78995_BITS_31_TO_0__q11[31]}}, - data78995_BITS_31_TO_0__q11 } ; - assign data___1__h480401 = - { {32{data79889_BITS_31_TO_0__q14[31]}}, - data79889_BITS_31_TO_0__q14 } ; - assign data__h478995 = + assign data78996_BITS_31_TO_0__q11 = data__h478996[31:0] ; + assign data79890_BITS_31_TO_0__q14 = data__h479890[31:0] ; + assign data___1__h479508 = + { {32{data78996_BITS_31_TO_0__q11[31]}}, + data78996_BITS_31_TO_0__q11 } ; + assign data___1__h480402 = + { {32{data79890_BITS_31_TO_0__q14[31]}}, + data79890_BITS_31_TO_0__q14 } ; + assign data__h478996 = (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] == 2'd0) ? coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ; - assign data__h479889 = + assign data__h479890 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h479691 : - x_remainder__h479692 ; - assign dcsr_cause__h717907 = + x_quotient__h479692 : + x_remainder__h479693 ; + assign dcsr_cause__h717908 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30540,31 +30540,31 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h385651 = _theResult___fst_exp__h358618 + 8'd1 ; - assign din_inc___2_exp__h385675 = _theResult___fst_exp__h367274 + 8'd1 ; - assign din_inc___2_exp__h385705 = _theResult___fst_exp__h376384 + 8'd1 ; - assign din_inc___2_exp__h385729 = _theResult___fst_exp__h385069 + 8'd1 ; - assign din_inc___2_exp__h431348 = _theResult___fst_exp__h404315 + 8'd1 ; - assign din_inc___2_exp__h431372 = _theResult___fst_exp__h412971 + 8'd1 ; - assign din_inc___2_exp__h431402 = _theResult___fst_exp__h422081 + 8'd1 ; - assign din_inc___2_exp__h431426 = _theResult___fst_exp__h430766 + 8'd1 ; - assign din_inc___2_exp__h477043 = _theResult___fst_exp__h450010 + 8'd1 ; - assign din_inc___2_exp__h477067 = _theResult___fst_exp__h458666 + 8'd1 ; - assign din_inc___2_exp__h477097 = _theResult___fst_exp__h467776 + 8'd1 ; - assign din_inc___2_exp__h477121 = _theResult___fst_exp__h476461 + 8'd1 ; - assign din_inc___2_exp__h525708 = _theResult___fst_exp__h506458 + 11'd1 ; - assign din_inc___2_exp__h525743 = _theResult___fst_exp__h516035 + 11'd1 ; - assign din_inc___2_exp__h525769 = _theResult___fst_exp__h524868 + 11'd1 ; - assign din_inc___2_exp__h564561 = _theResult___fst_exp__h545311 + 11'd1 ; - assign din_inc___2_exp__h564596 = _theResult___fst_exp__h554888 + 11'd1 ; - assign din_inc___2_exp__h564622 = _theResult___fst_exp__h563721 + 11'd1 ; - assign din_inc___2_exp__h603865 = _theResult___fst_exp__h584615 + 11'd1 ; - assign din_inc___2_exp__h603900 = _theResult___fst_exp__h594192 + 11'd1 ; - assign din_inc___2_exp__h603926 = _theResult___fst_exp__h603025 + 11'd1 ; - assign enabled_ints___1__h658901 = pend_ints__h658374 & y__h658913 ; - assign enabled_ints__h658947 = - pend_ints__h658374 & - { r1__read_BITS_13_TO_0___h658923, csrf_mideleg_1_0_reg } ; + assign din_inc___2_exp__h385652 = _theResult___fst_exp__h358619 + 8'd1 ; + assign din_inc___2_exp__h385676 = _theResult___fst_exp__h367275 + 8'd1 ; + assign din_inc___2_exp__h385706 = _theResult___fst_exp__h376385 + 8'd1 ; + assign din_inc___2_exp__h385730 = _theResult___fst_exp__h385070 + 8'd1 ; + assign din_inc___2_exp__h431349 = _theResult___fst_exp__h404316 + 8'd1 ; + assign din_inc___2_exp__h431373 = _theResult___fst_exp__h412972 + 8'd1 ; + assign din_inc___2_exp__h431403 = _theResult___fst_exp__h422082 + 8'd1 ; + assign din_inc___2_exp__h431427 = _theResult___fst_exp__h430767 + 8'd1 ; + assign din_inc___2_exp__h477044 = _theResult___fst_exp__h450011 + 8'd1 ; + assign din_inc___2_exp__h477068 = _theResult___fst_exp__h458667 + 8'd1 ; + assign din_inc___2_exp__h477098 = _theResult___fst_exp__h467777 + 8'd1 ; + assign din_inc___2_exp__h477122 = _theResult___fst_exp__h476462 + 8'd1 ; + assign din_inc___2_exp__h525709 = _theResult___fst_exp__h506459 + 11'd1 ; + assign din_inc___2_exp__h525744 = _theResult___fst_exp__h516036 + 11'd1 ; + assign din_inc___2_exp__h525770 = _theResult___fst_exp__h524869 + 11'd1 ; + assign din_inc___2_exp__h564562 = _theResult___fst_exp__h545312 + 11'd1 ; + assign din_inc___2_exp__h564597 = _theResult___fst_exp__h554889 + 11'd1 ; + assign din_inc___2_exp__h564623 = _theResult___fst_exp__h563722 + 11'd1 ; + assign din_inc___2_exp__h603866 = _theResult___fst_exp__h584616 + 11'd1 ; + assign din_inc___2_exp__h603901 = _theResult___fst_exp__h594193 + 11'd1 ; + assign din_inc___2_exp__h603927 = _theResult___fst_exp__h603026 + 11'd1 ; + assign enabled_ints___1__h658902 = pend_ints__h658375 & y__h658914 ; + assign enabled_ints__h658948 = + pend_ints__h658375 & + { r1__read_BITS_13_TO_0___h658924, csrf_mideleg_1_0_reg } ; assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13979 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || @@ -30586,34 +30586,34 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3653_AND__ETC___d13724 && IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d14135) ; - assign f1_exp87070_MINUS_127__q136 = f1_exp__h487070 - 8'd127 ; - assign f1_exp__h487070 = + assign f1_exp87071_MINUS_127__q136 = f1_exp__h487071 - 8'd127 ; + assign f1_exp__h487071 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h487071 = + assign f1_sfd__h487072 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp26064_MINUS_127__q176 = f2_exp__h526064 - 8'd127 ; - assign f2_exp__h526064 = + assign f2_exp26065_MINUS_127__q176 = f2_exp__h526065 - 8'd127 ; + assign f2_exp__h526065 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h526065 = + assign f2_sfd__h526066 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp65368_MINUS_127__q153 = f3_exp__h565368 - 8'd127 ; - assign f3_exp__h565368 = + assign f3_exp65369_MINUS_127__q153 = f3_exp__h565369 - 8'd127 ; + assign f3_exp__h565369 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h565369 = + assign f3_sfd__h565370 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; @@ -30623,15 +30623,15 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fallthrough_pc__h673432 = + assign fallthrough_pc__h673433 = (fetchStage$pipelines_0_first[97:96] == 2'b11) ? fetchStage$pipelines_0_first[387:324] + 64'd4 : fetchStage$pipelines_0_first[387:324] + 64'd2 ; - assign fallthrough_pc__h689940 = + assign fallthrough_pc__h689941 = (fetchStage$pipelines_1_first[97:96] == 2'b11) ? fetchStage$pipelines_1_first[387:324] + 64'd4 : fetchStage$pipelines_1_first[387:324] + 64'd2 ; - assign fcsr_csr__read__h615714 = { 56'd0, x__h619372 } ; + assign fcsr_csr__read__h615715 = { 56'd0, x__h619373 } ; assign fetchStage_RDY_pipelines_1_deq__3004_AND_NOT_f_ETC___d14323 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || @@ -30712,9 +30712,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13273 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h662586 != 5'd0 || - imm__h662587 != 32'd0) && - csr_addr__h662585[11:10] == 2'b11 ; + rs1__h662587 != 5'd0 || + imm__h662588 != 32'd0) && + csr_addr__h662586[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d13990 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -30821,7 +30821,7 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__3001_BIT_173_383_ETC___d13921 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h737590 = + assign fflags__h737461 = ({ rob$deqPort_0_deq_data[361:356], 1'd0, rob$deqPort_0_deq_data[354:350], @@ -30831,8 +30831,8 @@ module mkCore(CLK, rob$deqPort_0_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h737575 ; - assign fflags__h740303 = + po_fflags__h737446 ; + assign fflags__h740174 = ({ rob$deqPort_1_deq_data[361:356], 1'd0, rob$deqPort_1_deq_data[354:350], @@ -30842,105 +30842,105 @@ module mkCore(CLK, rob$deqPort_1_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h740288 ; - assign fflags__h742984 = + po_fflags__h740159 ; + assign fflags__h742855 = NOT_rob_deqPort_0_canDeq__5640_5641_OR_rob_deq_ETC___d15988 ? - y_avValue_fst__h742921 : + y_avValue_fst__h742792 : IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d15994 ; - assign fflags_csr__read__h615689 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h615700 = { 61'd0, csrf_frm_reg } ; - assign guard__h350517 = - { IF_sfdin58612_BIT_33_THEN_2_ELSE_0__q30[1], - { sfdin__h358612[32:0], 23'd0 } != 56'd0 } ; - assign guard__h359226 = - { IF_theResult___snd67225_BIT_33_THEN_2_ELSE_0__q32[1], - { _theResult___snd__h367225[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368156 = - { IF_sfdin76378_BIT_33_THEN_2_ELSE_0__q40[1], - { sfdin__h376378[32:0], 23'd0 } != 56'd0 } ; - assign guard__h368754 = x__h368856 != 57'd0 ; - assign guard__h376992 = - { IF_theResult___snd85015_BIT_33_THEN_2_ELSE_0__q45[1], - { _theResult___snd__h385015[32:0], 23'd0 } != 56'd0 } ; - assign guard__h396216 = - { IF_sfdin04309_BIT_33_THEN_2_ELSE_0__q65[1], - { sfdin__h404309[32:0], 23'd0 } != 56'd0 } ; - assign guard__h404923 = - { IF_theResult___snd12922_BIT_33_THEN_2_ELSE_0__q67[1], - { _theResult___snd__h412922[32:0], 23'd0 } != 56'd0 } ; - assign guard__h413853 = - { IF_sfdin22075_BIT_33_THEN_2_ELSE_0__q75[1], - { sfdin__h422075[32:0], 23'd0 } != 56'd0 } ; - assign guard__h414451 = x__h414553 != 57'd0 ; - assign guard__h422689 = - { IF_theResult___snd30712_BIT_33_THEN_2_ELSE_0__q80[1], - { _theResult___snd__h430712[32:0], 23'd0 } != 56'd0 } ; - assign guard__h441911 = - { IF_sfdin50004_BIT_33_THEN_2_ELSE_0__q100[1], - { sfdin__h450004[32:0], 23'd0 } != 56'd0 } ; - assign guard__h450618 = - { IF_theResult___snd58617_BIT_33_THEN_2_ELSE_0__q102[1], - { _theResult___snd__h458617[32:0], 23'd0 } != 56'd0 } ; - assign guard__h459548 = - { IF_sfdin67770_BIT_33_THEN_2_ELSE_0__q110[1], - { sfdin__h467770[32:0], 23'd0 } != 56'd0 } ; - assign guard__h460146 = x__h460248 != 57'd0 ; - assign guard__h468384 = - { IF_theResult___snd76407_BIT_33_THEN_2_ELSE_0__q115[1], - { _theResult___snd__h476407[32:0], 23'd0 } != 56'd0 } ; - assign guard__h498497 = - { IF_theResult___snd06409_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h506409[3:0], 52'd0 } != 56'd0 } ; - assign guard__h507809 = - { IF_sfdin16029_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h516029[3:0], 52'd0 } != 56'd0 } ; - assign guard__h508407 = x__h508507 != 57'd0 ; - assign guard__h516878 = - { IF_theResult___snd24814_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h524814[3:0], 52'd0 } != 56'd0 } ; - assign guard__h537350 = - { IF_theResult___snd45262_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h545262[3:0], 52'd0 } != 56'd0 } ; - assign guard__h546662 = - { IF_sfdin54882_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h554882[3:0], 52'd0 } != 56'd0 } ; - assign guard__h547260 = x__h547360 != 57'd0 ; - assign guard__h555731 = - { IF_theResult___snd63667_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h563667[3:0], 52'd0 } != 56'd0 } ; - assign guard__h576654 = - { IF_theResult___snd84566_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h584566[3:0], 52'd0 } != 56'd0 } ; - assign guard__h585966 = - { IF_sfdin94186_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h594186[3:0], 52'd0 } != 56'd0 } ; - assign guard__h586564 = x__h586664 != 57'd0 ; - assign guard__h595035 = - { IF_theResult___snd02971_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h602971[3:0], 52'd0 } != 56'd0 } ; - assign idx__h693568 = + assign fflags_csr__read__h615690 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h615701 = { 61'd0, csrf_frm_reg } ; + assign guard__h350518 = + { IF_sfdin58613_BIT_33_THEN_2_ELSE_0__q30[1], + { sfdin__h358613[32:0], 23'd0 } != 56'd0 } ; + assign guard__h359227 = + { IF_theResult___snd67226_BIT_33_THEN_2_ELSE_0__q32[1], + { _theResult___snd__h367226[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368157 = + { IF_sfdin76379_BIT_33_THEN_2_ELSE_0__q40[1], + { sfdin__h376379[32:0], 23'd0 } != 56'd0 } ; + assign guard__h368755 = x__h368857 != 57'd0 ; + assign guard__h376993 = + { IF_theResult___snd85016_BIT_33_THEN_2_ELSE_0__q45[1], + { _theResult___snd__h385016[32:0], 23'd0 } != 56'd0 } ; + assign guard__h396217 = + { IF_sfdin04310_BIT_33_THEN_2_ELSE_0__q65[1], + { sfdin__h404310[32:0], 23'd0 } != 56'd0 } ; + assign guard__h404924 = + { IF_theResult___snd12923_BIT_33_THEN_2_ELSE_0__q67[1], + { _theResult___snd__h412923[32:0], 23'd0 } != 56'd0 } ; + assign guard__h413854 = + { IF_sfdin22076_BIT_33_THEN_2_ELSE_0__q75[1], + { sfdin__h422076[32:0], 23'd0 } != 56'd0 } ; + assign guard__h414452 = x__h414554 != 57'd0 ; + assign guard__h422690 = + { IF_theResult___snd30713_BIT_33_THEN_2_ELSE_0__q80[1], + { _theResult___snd__h430713[32:0], 23'd0 } != 56'd0 } ; + assign guard__h441912 = + { IF_sfdin50005_BIT_33_THEN_2_ELSE_0__q100[1], + { sfdin__h450005[32:0], 23'd0 } != 56'd0 } ; + assign guard__h450619 = + { IF_theResult___snd58618_BIT_33_THEN_2_ELSE_0__q102[1], + { _theResult___snd__h458618[32:0], 23'd0 } != 56'd0 } ; + assign guard__h459549 = + { IF_sfdin67771_BIT_33_THEN_2_ELSE_0__q110[1], + { sfdin__h467771[32:0], 23'd0 } != 56'd0 } ; + assign guard__h460147 = x__h460249 != 57'd0 ; + assign guard__h468385 = + { IF_theResult___snd76408_BIT_33_THEN_2_ELSE_0__q115[1], + { _theResult___snd__h476408[32:0], 23'd0 } != 56'd0 } ; + assign guard__h498498 = + { IF_theResult___snd06410_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h506410[3:0], 52'd0 } != 56'd0 } ; + assign guard__h507810 = + { IF_sfdin16030_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h516030[3:0], 52'd0 } != 56'd0 } ; + assign guard__h508408 = x__h508508 != 57'd0 ; + assign guard__h516879 = + { IF_theResult___snd24815_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h524815[3:0], 52'd0 } != 56'd0 } ; + assign guard__h537351 = + { IF_theResult___snd45263_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h545263[3:0], 52'd0 } != 56'd0 } ; + assign guard__h546663 = + { IF_sfdin54883_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h554883[3:0], 52'd0 } != 56'd0 } ; + assign guard__h547261 = x__h547361 != 57'd0 ; + assign guard__h555732 = + { IF_theResult___snd63668_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h563668[3:0], 52'd0 } != 56'd0 } ; + assign guard__h576655 = + { IF_theResult___snd84567_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h584567[3:0], 52'd0 } != 56'd0 } ; + assign guard__h585967 = + { IF_sfdin94187_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h594187[3:0], 52'd0 } != 56'd0 } ; + assign guard__h586565 = x__h586665 != 57'd0 ; + assign guard__h595036 = + { IF_theResult___snd02972_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h602972[3:0], 52'd0 } != 56'd0 } ; + assign idx__h693569 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13991 || !coreFix_aluExe_0_rsAlu$canEnq || NOT_fetchStage_pipelines_0_canDeq__2990_2991_O_ETC___d14015 ; - assign imm__h662587 = + assign imm__h662588 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h677211 = + assign k__h677212 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3688__ETC___d13690 ; - assign mcause_csr__read__h617356 = - { r1__read__h620835, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h617101 = - { r1__read__h620822, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h616708 = - { r1__read__h620683, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h616803 = - { r1__read__h620700, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h616927 = { r1__read__h620724, 1'b0 } ; - assign mip_csr__read__h617589 = { r1__read__h620841, 1'b0 } ; + assign mcause_csr__read__h617357 = + { r1__read__h620836, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h617102 = + { r1__read__h620823, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h616709 = + { r1__read__h620684, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h616804 = + { r1__read__h620701, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h616928 = { r1__read__h620725, 1'b0 } ; + assign mip_csr__read__h617590 = { r1__read__h620842, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -31024,302 +31024,302 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h76123 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h616560 = { r1__read__h620558, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h617009 = - { r1__read__h620817, csrf_mtvec_mode_low_reg } ; - assign n___1__h201996 = + assign msip__h76124 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h616561 = { r1__read__h620559, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h617010 = + { r1__read__h620818, csrf_mtvec_mode_low_reg } ; + assign n___1__h201997 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h200593[63:56], + x__h200594[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h200593[55:48], + x__h200594[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h200593[47:40], + x__h200594[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h200593[39:32], + x__h200594[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h200593[31:24], + x__h200594[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h200593[23:16], + x__h200594[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h200593[15:8], + x__h200594[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h200593[7:0] } ; - assign n__read__h617693 = + x__h200594[7:0] } ; + assign n__read__h617694 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h617884 = + assign n__read__h617885 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6760 = + assign n__read__h6761 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? - upd__h6874 : + upd__h6875 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h735936 = + assign n__read__h735807 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h301222 = + assign next_deqP___1__h301223 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h309218 = + assign next_deqP___1__h309219 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h315499 = + assign next_deqP___1__h315500 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h323353 = + assign next_deqP___1__h323354 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h333410 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h336635 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h731630 = + assign next_deqP___1__h333411 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h336636 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h731631 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496 ; - assign old_fflags__h742410 = + assign old_fflags__h742281 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; - assign out___1_sfd__h487134 = { f1_sfd__h487071, 29'd0 } ; - assign out___1_sfd__h526128 = { f2_sfd__h526065, 29'd0 } ; - assign out___1_sfd__h565432 = { f3_sfd__h565369, 29'd0 } ; - assign out_exp__h359137 = - sfdin__h358612[34] ? - _theResult___exp__h359134 : - _theResult___fst_exp__h358618 ; - assign out_exp__h367719 = - _theResult___snd__h367225[34] ? - _theResult___exp__h367716 : - _theResult___fst_exp__h367274 ; - assign out_exp__h376903 = - sfdin__h376378[34] ? - _theResult___exp__h376900 : - _theResult___fst_exp__h376384 ; - assign out_exp__h385539 = - _theResult___snd__h385015[34] ? - _theResult___exp__h385536 : - _theResult___fst_exp__h385069 ; - assign out_exp__h404834 = - sfdin__h404309[34] ? - _theResult___exp__h404831 : - _theResult___fst_exp__h404315 ; - assign out_exp__h413416 = - _theResult___snd__h412922[34] ? - _theResult___exp__h413413 : - _theResult___fst_exp__h412971 ; - assign out_exp__h422600 = - sfdin__h422075[34] ? - _theResult___exp__h422597 : - _theResult___fst_exp__h422081 ; - assign out_exp__h431236 = - _theResult___snd__h430712[34] ? - _theResult___exp__h431233 : - _theResult___fst_exp__h430766 ; - assign out_exp__h450529 = - sfdin__h450004[34] ? - _theResult___exp__h450526 : - _theResult___fst_exp__h450010 ; - assign out_exp__h459111 = - _theResult___snd__h458617[34] ? - _theResult___exp__h459108 : - _theResult___fst_exp__h458666 ; - assign out_exp__h468295 = - sfdin__h467770[34] ? - _theResult___exp__h468292 : - _theResult___fst_exp__h467776 ; - assign out_exp__h476931 = - _theResult___snd__h476407[34] ? - _theResult___exp__h476928 : - _theResult___fst_exp__h476461 ; - assign out_exp__h507116 = - _theResult___snd__h506409[5] ? - _theResult___exp__h507113 : - _theResult___fst_exp__h506458 ; - assign out_exp__h516767 = - sfdin__h516029[5] ? - _theResult___exp__h516764 : - _theResult___fst_exp__h516035 ; - assign out_exp__h525551 = - _theResult___snd__h524814[5] ? - _theResult___exp__h525548 : - _theResult___fst_exp__h524868 ; - assign out_exp__h545969 = - _theResult___snd__h545262[5] ? - _theResult___exp__h545966 : - _theResult___fst_exp__h545311 ; - assign out_exp__h555620 = - sfdin__h554882[5] ? - _theResult___exp__h555617 : - _theResult___fst_exp__h554888 ; - assign out_exp__h564404 = - _theResult___snd__h563667[5] ? - _theResult___exp__h564401 : - _theResult___fst_exp__h563721 ; - assign out_exp__h585273 = - _theResult___snd__h584566[5] ? - _theResult___exp__h585270 : - _theResult___fst_exp__h584615 ; - assign out_exp__h594924 = - sfdin__h594186[5] ? - _theResult___exp__h594921 : - _theResult___fst_exp__h594192 ; - assign out_exp__h603708 = - _theResult___snd__h602971[5] ? - _theResult___exp__h603705 : - _theResult___fst_exp__h603025 ; - assign out_f_exp__h385915 = - (_theResult___exp__h385638 == 8'd255 && - _theResult___sfd__h385639 != 23'd0 || + assign out___1_sfd__h487135 = { f1_sfd__h487072, 29'd0 } ; + assign out___1_sfd__h526129 = { f2_sfd__h526066, 29'd0 } ; + assign out___1_sfd__h565433 = { f3_sfd__h565370, 29'd0 } ; + assign out_exp__h359138 = + sfdin__h358613[34] ? + _theResult___exp__h359135 : + _theResult___fst_exp__h358619 ; + assign out_exp__h367720 = + _theResult___snd__h367226[34] ? + _theResult___exp__h367717 : + _theResult___fst_exp__h367275 ; + assign out_exp__h376904 = + sfdin__h376379[34] ? + _theResult___exp__h376901 : + _theResult___fst_exp__h376385 ; + assign out_exp__h385540 = + _theResult___snd__h385016[34] ? + _theResult___exp__h385537 : + _theResult___fst_exp__h385070 ; + assign out_exp__h404835 = + sfdin__h404310[34] ? + _theResult___exp__h404832 : + _theResult___fst_exp__h404316 ; + assign out_exp__h413417 = + _theResult___snd__h412923[34] ? + _theResult___exp__h413414 : + _theResult___fst_exp__h412972 ; + assign out_exp__h422601 = + sfdin__h422076[34] ? + _theResult___exp__h422598 : + _theResult___fst_exp__h422082 ; + assign out_exp__h431237 = + _theResult___snd__h430713[34] ? + _theResult___exp__h431234 : + _theResult___fst_exp__h430767 ; + assign out_exp__h450530 = + sfdin__h450005[34] ? + _theResult___exp__h450527 : + _theResult___fst_exp__h450011 ; + assign out_exp__h459112 = + _theResult___snd__h458618[34] ? + _theResult___exp__h459109 : + _theResult___fst_exp__h458667 ; + assign out_exp__h468296 = + sfdin__h467771[34] ? + _theResult___exp__h468293 : + _theResult___fst_exp__h467777 ; + assign out_exp__h476932 = + _theResult___snd__h476408[34] ? + _theResult___exp__h476929 : + _theResult___fst_exp__h476462 ; + assign out_exp__h507117 = + _theResult___snd__h506410[5] ? + _theResult___exp__h507114 : + _theResult___fst_exp__h506459 ; + assign out_exp__h516768 = + sfdin__h516030[5] ? + _theResult___exp__h516765 : + _theResult___fst_exp__h516036 ; + assign out_exp__h525552 = + _theResult___snd__h524815[5] ? + _theResult___exp__h525549 : + _theResult___fst_exp__h524869 ; + assign out_exp__h545970 = + _theResult___snd__h545263[5] ? + _theResult___exp__h545967 : + _theResult___fst_exp__h545312 ; + assign out_exp__h555621 = + sfdin__h554883[5] ? + _theResult___exp__h555618 : + _theResult___fst_exp__h554889 ; + assign out_exp__h564405 = + _theResult___snd__h563668[5] ? + _theResult___exp__h564402 : + _theResult___fst_exp__h563722 ; + assign out_exp__h585274 = + _theResult___snd__h584567[5] ? + _theResult___exp__h585271 : + _theResult___fst_exp__h584616 ; + assign out_exp__h594925 = + sfdin__h594187[5] ? + _theResult___exp__h594922 : + _theResult___fst_exp__h594193 ; + assign out_exp__h603709 = + _theResult___snd__h602972[5] ? + _theResult___exp__h603706 : + _theResult___fst_exp__h603026 ; + assign out_f_exp__h385916 = + (_theResult___exp__h385639 == 8'd255 && + _theResult___sfd__h385640 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h385629 ; - assign out_f_exp__h431612 = - (_theResult___exp__h431335 == 8'd255 && - _theResult___sfd__h431336 != 23'd0 || + _theResult___fst_exp__h385630 ; + assign out_f_exp__h431613 = + (_theResult___exp__h431336 == 8'd255 && + _theResult___sfd__h431337 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h431326 ; - assign out_f_exp__h477307 = - (_theResult___exp__h477030 == 8'd255 && - _theResult___sfd__h477031 != 23'd0 || + _theResult___fst_exp__h431327 ; + assign out_f_exp__h477308 = + (_theResult___exp__h477031 == 8'd255 && + _theResult___sfd__h477032 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h477021 ; - assign out_f_sfd__h385916 = - (_theResult___exp__h385638 == 8'd255 && - _theResult___sfd__h385639 != 23'd0) ? + _theResult___fst_exp__h477022 ; + assign out_f_sfd__h385917 = + (_theResult___exp__h385639 == 8'd255 && + _theResult___sfd__h385640 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h385639 ; - assign out_f_sfd__h431613 = - (_theResult___exp__h431335 == 8'd255 && - _theResult___sfd__h431336 != 23'd0) ? + _theResult___sfd__h385640 ; + assign out_f_sfd__h431614 = + (_theResult___exp__h431336 == 8'd255 && + _theResult___sfd__h431337 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h431336 ; - assign out_f_sfd__h477308 = - (_theResult___exp__h477030 == 8'd255 && - _theResult___sfd__h477031 != 23'd0) ? + _theResult___sfd__h431337 ; + assign out_f_sfd__h477309 = + (_theResult___exp__h477031 == 8'd255 && + _theResult___sfd__h477032 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h477031 ; - assign out_sfd__h359138 = - sfdin__h358612[34] ? - _theResult___sfd__h359135 : - sfdin__h358612[56:34] ; - assign out_sfd__h367720 = - _theResult___snd__h367225[34] ? - _theResult___sfd__h367717 : - _theResult___snd__h367225[56:34] ; - assign out_sfd__h376904 = - sfdin__h376378[34] ? - _theResult___sfd__h376901 : - sfdin__h376378[56:34] ; - assign out_sfd__h385540 = - _theResult___snd__h385015[34] ? - _theResult___sfd__h385537 : - _theResult___snd__h385015[56:34] ; - assign out_sfd__h404835 = - sfdin__h404309[34] ? - _theResult___sfd__h404832 : - sfdin__h404309[56:34] ; - assign out_sfd__h413417 = - _theResult___snd__h412922[34] ? - _theResult___sfd__h413414 : - _theResult___snd__h412922[56:34] ; - assign out_sfd__h422601 = - sfdin__h422075[34] ? - _theResult___sfd__h422598 : - sfdin__h422075[56:34] ; - assign out_sfd__h431237 = - _theResult___snd__h430712[34] ? - _theResult___sfd__h431234 : - _theResult___snd__h430712[56:34] ; - assign out_sfd__h450530 = - sfdin__h450004[34] ? - _theResult___sfd__h450527 : - sfdin__h450004[56:34] ; - assign out_sfd__h459112 = - _theResult___snd__h458617[34] ? - _theResult___sfd__h459109 : - _theResult___snd__h458617[56:34] ; - assign out_sfd__h468296 = - sfdin__h467770[34] ? - _theResult___sfd__h468293 : - sfdin__h467770[56:34] ; - assign out_sfd__h476932 = - _theResult___snd__h476407[34] ? - _theResult___sfd__h476929 : - _theResult___snd__h476407[56:34] ; - assign out_sfd__h507117 = - _theResult___snd__h506409[5] ? - _theResult___sfd__h507114 : - _theResult___snd__h506409[56:5] ; - assign out_sfd__h516768 = - sfdin__h516029[5] ? - _theResult___sfd__h516765 : - sfdin__h516029[56:5] ; - assign out_sfd__h525552 = - _theResult___snd__h524814[5] ? - _theResult___sfd__h525549 : - _theResult___snd__h524814[56:5] ; - assign out_sfd__h545970 = - _theResult___snd__h545262[5] ? - _theResult___sfd__h545967 : - _theResult___snd__h545262[56:5] ; - assign out_sfd__h555621 = - sfdin__h554882[5] ? - _theResult___sfd__h555618 : - sfdin__h554882[56:5] ; - assign out_sfd__h564405 = - _theResult___snd__h563667[5] ? - _theResult___sfd__h564402 : - _theResult___snd__h563667[56:5] ; - assign out_sfd__h585274 = - _theResult___snd__h584566[5] ? - _theResult___sfd__h585271 : - _theResult___snd__h584566[56:5] ; - assign out_sfd__h594925 = - sfdin__h594186[5] ? - _theResult___sfd__h594922 : - sfdin__h594186[56:5] ; - assign out_sfd__h603709 = - _theResult___snd__h602971[5] ? - _theResult___sfd__h603706 : - _theResult___snd__h602971[56:5] ; - assign pc__h721332 = + _theResult___sfd__h477032 ; + assign out_sfd__h359139 = + sfdin__h358613[34] ? + _theResult___sfd__h359136 : + sfdin__h358613[56:34] ; + assign out_sfd__h367721 = + _theResult___snd__h367226[34] ? + _theResult___sfd__h367718 : + _theResult___snd__h367226[56:34] ; + assign out_sfd__h376905 = + sfdin__h376379[34] ? + _theResult___sfd__h376902 : + sfdin__h376379[56:34] ; + assign out_sfd__h385541 = + _theResult___snd__h385016[34] ? + _theResult___sfd__h385538 : + _theResult___snd__h385016[56:34] ; + assign out_sfd__h404836 = + sfdin__h404310[34] ? + _theResult___sfd__h404833 : + sfdin__h404310[56:34] ; + assign out_sfd__h413418 = + _theResult___snd__h412923[34] ? + _theResult___sfd__h413415 : + _theResult___snd__h412923[56:34] ; + assign out_sfd__h422602 = + sfdin__h422076[34] ? + _theResult___sfd__h422599 : + sfdin__h422076[56:34] ; + assign out_sfd__h431238 = + _theResult___snd__h430713[34] ? + _theResult___sfd__h431235 : + _theResult___snd__h430713[56:34] ; + assign out_sfd__h450531 = + sfdin__h450005[34] ? + _theResult___sfd__h450528 : + sfdin__h450005[56:34] ; + assign out_sfd__h459113 = + _theResult___snd__h458618[34] ? + _theResult___sfd__h459110 : + _theResult___snd__h458618[56:34] ; + assign out_sfd__h468297 = + sfdin__h467771[34] ? + _theResult___sfd__h468294 : + sfdin__h467771[56:34] ; + assign out_sfd__h476933 = + _theResult___snd__h476408[34] ? + _theResult___sfd__h476930 : + _theResult___snd__h476408[56:34] ; + assign out_sfd__h507118 = + _theResult___snd__h506410[5] ? + _theResult___sfd__h507115 : + _theResult___snd__h506410[56:5] ; + assign out_sfd__h516769 = + sfdin__h516030[5] ? + _theResult___sfd__h516766 : + sfdin__h516030[56:5] ; + assign out_sfd__h525553 = + _theResult___snd__h524815[5] ? + _theResult___sfd__h525550 : + _theResult___snd__h524815[56:5] ; + assign out_sfd__h545971 = + _theResult___snd__h545263[5] ? + _theResult___sfd__h545968 : + _theResult___snd__h545263[56:5] ; + assign out_sfd__h555622 = + sfdin__h554883[5] ? + _theResult___sfd__h555619 : + sfdin__h554883[56:5] ; + assign out_sfd__h564406 = + _theResult___snd__h563668[5] ? + _theResult___sfd__h564403 : + _theResult___snd__h563668[56:5] ; + assign out_sfd__h585275 = + _theResult___snd__h584567[5] ? + _theResult___sfd__h585272 : + _theResult___snd__h584567[56:5] ; + assign out_sfd__h594926 = + sfdin__h594187[5] ? + _theResult___sfd__h594923 : + sfdin__h594187[56:5] ; + assign out_sfd__h603710 = + _theResult___snd__h602972[5] ? + _theResult___sfd__h603707 : + _theResult___snd__h602972[56:5] ; + assign pc__h721333 = csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 ? - y_avValue_new_pc__h721124 : - y_avValue_new_pc__h721310 ; - assign pend_ints__h658374 = + y_avValue_new_pc__h721125 : + y_avValue_new_pc__h721311 ; + assign pend_ints__h658375 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1864_ETC___d13033, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h737575 = old_fflags__h742410 ; - assign po_fflags__h740288 = - old_fflags__h742410 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h744653 = csrf_prv_reg ; - assign prv__h744697 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h480476 = + assign po_fflags__h737446 = old_fflags__h742281 ; + assign po_fflags__h740159 = + old_fflags__h742281 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h744524 = csrf_prv_reg ; + assign prv__h744568 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h480477 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ; - assign r1__read_BITS_13_TO_0___h658923 = + assign r1__read_BITS_13_TO_0___h658924 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -31327,116 +31327,116 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h662455 = csrf_fs_reg ; - assign r1__read_BITS_62_TO_14___h739253 = { r1__read__h620582, 2'd0 } ; - assign r1__read_BIT_20___h663151 = csrf_tw_reg ; - assign r1__read__h619387 = { r1__read__h619389, csrf_ie_vec_1 } ; - assign r1__read__h619389 = { r1__read__h619391, 2'b0 } ; - assign r1__read__h619391 = { r1__read__h619393, csrf_prev_ie_vec_0 } ; - assign r1__read__h619393 = { r1__read__h619395, csrf_prev_ie_vec_1 } ; - assign r1__read__h619395 = { r1__read__h619397, 2'b0 } ; - assign r1__read__h619397 = { r1__read__h619399, csrf_spp_reg } ; - assign r1__read__h619399 = { r1__read__h619401, 4'b0 } ; - assign r1__read__h619401 = { r1__read__h619403, csrf_fs_reg } ; - assign r1__read__h619403 = { r1__read__h619405, 2'd0 } ; - assign r1__read__h619405 = { r1__read__h619407, 1'b0 } ; - assign r1__read__h619407 = { r1__read__h619409, csrf_sum_reg } ; - assign r1__read__h619409 = { r1__read__h619411, csrf_mxr_reg } ; - assign r1__read__h619411 = { r1__read__h619413, 12'b0 } ; - assign r1__read__h619413 = { r1__read__h619415, 2'b10 } ; - assign r1__read__h619415 = { csrf_fs_reg == 2'b11, 29'b0 } ; - assign r1__read__h619791 = - { r1__read__h619793, csrf_software_int_en_vec_1 } ; - assign r1__read__h619793 = { r1__read__h619795, 2'b0 } ; - assign r1__read__h619795 = { r1__read__h619797, 1'b0 } ; - assign r1__read__h619797 = { r1__read__h619799, csrf_timer_int_en_vec_1 } ; - assign r1__read__h619799 = { r1__read__h619801, 2'b0 } ; - assign r1__read__h619801 = { r1__read__h619803, 1'b0 } ; - assign r1__read__h619803 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h620301 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620306 = { r1__read__h620308, csrf_scounteren_tm_reg } ; - assign r1__read__h620308 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h620319 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h620325 = - { r1__read__h620327, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620327 = { r1__read__h620329, 2'b0 } ; - assign r1__read__h620329 = { r1__read__h620331, 1'b0 } ; - assign r1__read__h620331 = - { r1__read__h620333, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620333 = { r1__read__h620335, 2'b0 } ; - assign r1__read__h620335 = { r1__read__h620337, 1'b0 } ; - assign r1__read__h620337 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620535 = { vm_mode_reg__read__h620541, 16'd0 } ; - assign r1__read__h620558 = { r1__read__h620560, csrf_ie_vec_1 } ; - assign r1__read__h620560 = { r1__read__h620562, 1'b0 } ; - assign r1__read__h620562 = { r1__read__h620564, csrf_ie_vec_3 } ; - assign r1__read__h620564 = { r1__read__h620566, csrf_prev_ie_vec_0 } ; - assign r1__read__h620566 = { r1__read__h620568, csrf_prev_ie_vec_1 } ; - assign r1__read__h620568 = { r1__read__h620570, 1'b0 } ; - assign r1__read__h620570 = { r1__read__h620572, csrf_prev_ie_vec_3 } ; - assign r1__read__h620572 = { r1__read__h620574, csrf_spp_reg } ; - assign r1__read__h620574 = { r1__read__h620576, 2'b0 } ; - assign r1__read__h620576 = { r1__read__h620578, csrf_mpp_reg } ; - assign r1__read__h620578 = - { r1__read_BITS_62_TO_14___h739253, csrf_fs_reg } ; - assign r1__read__h620582 = { r1__read__h620584, csrf_mprv_reg } ; - assign r1__read__h620584 = { r1__read__h620586, csrf_sum_reg } ; - assign r1__read__h620586 = { r1__read__h620588, csrf_mxr_reg } ; - assign r1__read__h620588 = { r1__read__h620590, csrf_tvm_reg } ; - assign r1__read__h620590 = { r1__read__h620592, csrf_tw_reg } ; - assign r1__read__h620592 = { r1__read__h620594, csrf_tsr_reg } ; - assign r1__read__h620594 = { r1__read__h620596, 9'b0 } ; - assign r1__read__h620596 = { r1__read__h620598, 2'b10 } ; - assign r1__read__h620598 = { r1__read__h620600, 2'b10 } ; - assign r1__read__h620600 = { csrf_fs_reg == 2'b11, 27'b0 } ; - assign r1__read__h620683 = { r1__read__h620685, 1'b0 } ; - assign r1__read__h620685 = { r1__read__h620687, csrf_medeleg_13_11_reg } ; - assign r1__read__h620687 = { r1__read__h620689, 1'b0 } ; - assign r1__read__h620689 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h620700 = { r1__read__h620702, 1'b0 } ; - assign r1__read__h620702 = { r1__read__h620704, csrf_mideleg_5_3_reg } ; - assign r1__read__h620704 = { r1__read__h620706, 1'b0 } ; - assign r1__read__h620706 = { r1__read__h620708, csrf_mideleg_9_7_reg } ; - assign r1__read__h620708 = { r1__read__h620710, 1'b0 } ; - assign r1__read__h620710 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h620724 = - { r1__read__h620726, csrf_software_int_en_vec_1 } ; - assign r1__read__h620726 = { r1__read__h620728, 1'b0 } ; - assign r1__read__h620728 = - { r1__read__h620730, csrf_software_int_en_vec_3 } ; - assign r1__read__h620730 = { r1__read__h620732, 1'b0 } ; - assign r1__read__h620732 = { r1__read__h620734, csrf_timer_int_en_vec_1 } ; - assign r1__read__h620734 = { r1__read__h620736, 1'b0 } ; - assign r1__read__h620736 = { r1__read__h620738, csrf_timer_int_en_vec_3 } ; - assign r1__read__h620738 = { r1__read__h620740, 1'b0 } ; - assign r1__read__h620740 = - { r1__read__h620742, csrf_external_int_en_vec_1 } ; - assign r1__read__h620742 = { r1__read__h620744, 1'b0 } ; - assign r1__read__h620744 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h620817 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h620822 = { r1__read__h620824, csrf_mcounteren_tm_reg } ; - assign r1__read__h620824 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h620835 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h620841 = - { r1__read__h620843, csrf_software_int_pend_vec_1 } ; - assign r1__read__h620843 = { r1__read__h620845, 1'b0 } ; - assign r1__read__h620845 = - { r1__read__h620847, csrf_software_int_pend_vec_3 } ; - assign r1__read__h620847 = { r1__read__h620849, 1'b0 } ; - assign r1__read__h620849 = - { r1__read__h620851, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h620851 = { r1__read__h620853, 1'b0 } ; - assign r1__read__h620853 = - { r1__read__h620855, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h620855 = { r1__read__h620857, 1'b0 } ; - assign r1__read__h620857 = - { r1__read__h620859, csrf_external_int_pend_vec_1 } ; - assign r1__read__h620859 = { r1__read__h620861, 1'b0 } ; - assign r1__read__h620861 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h620938 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h486686 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h486687 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h480503 = + assign r1__read_BITS_13_TO_12___h662456 = csrf_fs_reg ; + assign r1__read_BITS_62_TO_14___h739124 = { r1__read__h620583, 2'd0 } ; + assign r1__read_BIT_20___h663152 = csrf_tw_reg ; + assign r1__read__h619388 = { r1__read__h619390, csrf_ie_vec_1 } ; + assign r1__read__h619390 = { r1__read__h619392, 2'b0 } ; + assign r1__read__h619392 = { r1__read__h619394, csrf_prev_ie_vec_0 } ; + assign r1__read__h619394 = { r1__read__h619396, csrf_prev_ie_vec_1 } ; + assign r1__read__h619396 = { r1__read__h619398, 2'b0 } ; + assign r1__read__h619398 = { r1__read__h619400, csrf_spp_reg } ; + assign r1__read__h619400 = { r1__read__h619402, 4'b0 } ; + assign r1__read__h619402 = { r1__read__h619404, csrf_fs_reg } ; + assign r1__read__h619404 = { r1__read__h619406, 2'd0 } ; + assign r1__read__h619406 = { r1__read__h619408, 1'b0 } ; + assign r1__read__h619408 = { r1__read__h619410, csrf_sum_reg } ; + assign r1__read__h619410 = { r1__read__h619412, csrf_mxr_reg } ; + assign r1__read__h619412 = { r1__read__h619414, 12'b0 } ; + assign r1__read__h619414 = { r1__read__h619416, 2'b10 } ; + assign r1__read__h619416 = { csrf_fs_reg == 2'b11, 29'b0 } ; + assign r1__read__h619792 = + { r1__read__h619794, csrf_software_int_en_vec_1 } ; + assign r1__read__h619794 = { r1__read__h619796, 2'b0 } ; + assign r1__read__h619796 = { r1__read__h619798, 1'b0 } ; + assign r1__read__h619798 = { r1__read__h619800, csrf_timer_int_en_vec_1 } ; + assign r1__read__h619800 = { r1__read__h619802, 2'b0 } ; + assign r1__read__h619802 = { r1__read__h619804, 1'b0 } ; + assign r1__read__h619804 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h620302 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620307 = { r1__read__h620309, csrf_scounteren_tm_reg } ; + assign r1__read__h620309 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h620320 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h620326 = + { r1__read__h620328, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620328 = { r1__read__h620330, 2'b0 } ; + assign r1__read__h620330 = { r1__read__h620332, 1'b0 } ; + assign r1__read__h620332 = + { r1__read__h620334, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620334 = { r1__read__h620336, 2'b0 } ; + assign r1__read__h620336 = { r1__read__h620338, 1'b0 } ; + assign r1__read__h620338 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620536 = { vm_mode_reg__read__h620542, 16'd0 } ; + assign r1__read__h620559 = { r1__read__h620561, csrf_ie_vec_1 } ; + assign r1__read__h620561 = { r1__read__h620563, 1'b0 } ; + assign r1__read__h620563 = { r1__read__h620565, csrf_ie_vec_3 } ; + assign r1__read__h620565 = { r1__read__h620567, csrf_prev_ie_vec_0 } ; + assign r1__read__h620567 = { r1__read__h620569, csrf_prev_ie_vec_1 } ; + assign r1__read__h620569 = { r1__read__h620571, 1'b0 } ; + assign r1__read__h620571 = { r1__read__h620573, csrf_prev_ie_vec_3 } ; + assign r1__read__h620573 = { r1__read__h620575, csrf_spp_reg } ; + assign r1__read__h620575 = { r1__read__h620577, 2'b0 } ; + assign r1__read__h620577 = { r1__read__h620579, csrf_mpp_reg } ; + assign r1__read__h620579 = + { r1__read_BITS_62_TO_14___h739124, csrf_fs_reg } ; + assign r1__read__h620583 = { r1__read__h620585, csrf_mprv_reg } ; + assign r1__read__h620585 = { r1__read__h620587, csrf_sum_reg } ; + assign r1__read__h620587 = { r1__read__h620589, csrf_mxr_reg } ; + assign r1__read__h620589 = { r1__read__h620591, csrf_tvm_reg } ; + assign r1__read__h620591 = { r1__read__h620593, csrf_tw_reg } ; + assign r1__read__h620593 = { r1__read__h620595, csrf_tsr_reg } ; + assign r1__read__h620595 = { r1__read__h620597, 9'b0 } ; + assign r1__read__h620597 = { r1__read__h620599, 2'b10 } ; + assign r1__read__h620599 = { r1__read__h620601, 2'b10 } ; + assign r1__read__h620601 = { csrf_fs_reg == 2'b11, 27'b0 } ; + assign r1__read__h620684 = { r1__read__h620686, 1'b0 } ; + assign r1__read__h620686 = { r1__read__h620688, csrf_medeleg_13_11_reg } ; + assign r1__read__h620688 = { r1__read__h620690, 1'b0 } ; + assign r1__read__h620690 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h620701 = { r1__read__h620703, 1'b0 } ; + assign r1__read__h620703 = { r1__read__h620705, csrf_mideleg_5_3_reg } ; + assign r1__read__h620705 = { r1__read__h620707, 1'b0 } ; + assign r1__read__h620707 = { r1__read__h620709, csrf_mideleg_9_7_reg } ; + assign r1__read__h620709 = { r1__read__h620711, 1'b0 } ; + assign r1__read__h620711 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h620725 = + { r1__read__h620727, csrf_software_int_en_vec_1 } ; + assign r1__read__h620727 = { r1__read__h620729, 1'b0 } ; + assign r1__read__h620729 = + { r1__read__h620731, csrf_software_int_en_vec_3 } ; + assign r1__read__h620731 = { r1__read__h620733, 1'b0 } ; + assign r1__read__h620733 = { r1__read__h620735, csrf_timer_int_en_vec_1 } ; + assign r1__read__h620735 = { r1__read__h620737, 1'b0 } ; + assign r1__read__h620737 = { r1__read__h620739, csrf_timer_int_en_vec_3 } ; + assign r1__read__h620739 = { r1__read__h620741, 1'b0 } ; + assign r1__read__h620741 = + { r1__read__h620743, csrf_external_int_en_vec_1 } ; + assign r1__read__h620743 = { r1__read__h620745, 1'b0 } ; + assign r1__read__h620745 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h620818 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h620823 = { r1__read__h620825, csrf_mcounteren_tm_reg } ; + assign r1__read__h620825 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h620836 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h620842 = + { r1__read__h620844, csrf_software_int_pend_vec_1 } ; + assign r1__read__h620844 = { r1__read__h620846, 1'b0 } ; + assign r1__read__h620846 = + { r1__read__h620848, csrf_software_int_pend_vec_3 } ; + assign r1__read__h620848 = { r1__read__h620850, 1'b0 } ; + assign r1__read__h620850 = + { r1__read__h620852, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h620852 = { r1__read__h620854, 1'b0 } ; + assign r1__read__h620854 = + { r1__read__h620856, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h620856 = { r1__read__h620858, 1'b0 } ; + assign r1__read__h620858 = + { r1__read__h620860, csrf_external_int_pend_vec_1 } ; + assign r1__read__h620860 = { r1__read__h620862, 1'b0 } ; + assign r1__read__h620862 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h620939 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h486687 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h486688 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h480504 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ; assign regRenamingTable_RDY_rename_0_getRename__3535__ETC___d13544 = @@ -31688,12 +31688,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[68] || checkForException___d13243[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h693437 = + assign renaming_spec_bits__h693438 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h689832 : + y_avValue_fst__h689833 : specTagManager$currentSpecBits ; - assign res_data__h342291 = { 32'hFFFFFFFF, x__h342306 } ; - assign res_data__h342296 = + assign res_data__h342292 = { 32'hFFFFFFFF, x__h342307 } ; + assign res_data__h342297 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -31706,8 +31706,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h387993 = { 32'hFFFFFFFF, x__h388008 } ; - assign res_data__h387998 = + assign res_data__h387994 = { 32'hFFFFFFFF, x__h388009 } ; + assign res_data__h387999 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -31720,8 +31720,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h433688 = { 32'hFFFFFFFF, x__h433703 } ; - assign res_data__h433693 = + assign res_data__h433689 = { 32'hFFFFFFFF, x__h433704 } ; + assign res_data__h433694 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -31734,7 +31734,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h342292 = + assign res_fflags__h342293 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -31802,7 +31802,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5355 } ; - assign res_fflags__h387994 = + assign res_fflags__h387995 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -31870,7 +31870,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6747 } ; - assign res_fflags__h433689 = + assign res_fflags__h433690 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31938,43 +31938,43 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8139 } ; - assign resp_addr__h296399 = + assign resp_addr__h296400 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h368759 = + assign result__h368760 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4658[0] | - guard__h368754 } ; - assign result__h414456 = + guard__h368755 } ; + assign result__h414457 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6050[0] | - guard__h414451 } ; - assign result__h460151 = + guard__h414452 } ; + assign result__h460152 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7442[0] | - guard__h460146 } ; - assign result__h508412 = + guard__h460147 } ; + assign result__h508413 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8768[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8768[0] | - guard__h508407 } ; - assign result__h547265 = + guard__h508408 } ; + assign result__h547266 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10253[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10253[0] | - guard__h547260 } ; - assign result__h586569 = + guard__h547261 } ; + assign result__h586570 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9483[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9483[0] | - guard__h586564 } ; - assign result__h653953 = w__h653948 & y__h653982 ; - assign result__h654004 = ~x__h654003 ; + guard__h586565 } ; + assign result__h653954 = w__h653949 & y__h653983 ; + assign result__h654005 = ~x__h654004 ; assign rg_core_run_state_read__3293_EQ_2_3294_AND_NOT_ETC___d16059 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h618544 = - { r1__read__h620938, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h618545 = + { r1__read__h620939, csrf_rg_tdata1_data } ; assign rob_RDY_deqPort_0_deq__4643_AND_rob_RDY_deqPor_ETC___d15310 = rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && @@ -31992,14 +31992,14 @@ module mkCore(CLK, { 2'd1, rob$deqPort_0_deq_data[95:32] } : { 2'd2, (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h731607 : + data_warl_xformed__h731608 : rob$deqPort_0_deq_data[95:32] }), 5'h0A, rob$deqPort_0_deq_data[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h732255, + x_prv__h732256, 64'hAAAAAAAAAAAAAAAA, - x__h735430, + x__h735301, 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496 = rob$deqPort_0_deq_data[425:362] + 64'd4 ; @@ -32013,449 +32013,449 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h662586 = + assign rs1__h662587 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h616417 = { r1__read__h620535, csrf_ppn_reg } ; - assign sbIdx__h158709 = + assign satp_csr__read__h616418 = { r1__read__h620536, csrf_ppn_reg } ; + assign sbIdx__h158710 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h616214 = - { r1__read__h620319, csrf_scause_code_reg } ; - assign scounteren_csr__read__h616076 = - { r1__read__h620306, csrf_scounteren_cy_reg } ; - assign sfd__h342902 = { value__h351129, 3'd0 } ; - assign sfd__h358710 = + assign scause_csr__read__h616215 = + { r1__read__h620320, csrf_scause_code_reg } ; + assign scounteren_csr__read__h616077 = + { r1__read__h620307, csrf_scounteren_cy_reg } ; + assign sfd__h342903 = { value__h351130, 3'd0 } ; + assign sfd__h358711 = { 1'b0, - _theResult___fst_exp__h358618 != 8'd0, - sfdin__h358612[56:34] } + + _theResult___fst_exp__h358619 != 8'd0, + sfdin__h358613[56:34] } + 25'd1 ; - assign sfd__h367292 = + assign sfd__h367293 = { 1'b0, - _theResult___fst_exp__h367274 != 8'd0, - _theResult___snd__h367225[56:34] } + + _theResult___fst_exp__h367275 != 8'd0, + _theResult___snd__h367226[56:34] } + 25'd1 ; - assign sfd__h376476 = + assign sfd__h376477 = { 1'b0, - _theResult___fst_exp__h376384 != 8'd0, - sfdin__h376378[56:34] } + + _theResult___fst_exp__h376385 != 8'd0, + sfdin__h376379[56:34] } + 25'd1 ; - assign sfd__h385088 = + assign sfd__h385089 = { 1'b0, - _theResult___fst_exp__h385069 != 8'd0, - _theResult___snd__h385015[56:34] } + + _theResult___fst_exp__h385070 != 8'd0, + _theResult___snd__h385016[56:34] } + 25'd1 ; - assign sfd__h388604 = { value__h396826, 3'd0 } ; - assign sfd__h404407 = + assign sfd__h388605 = { value__h396827, 3'd0 } ; + assign sfd__h404408 = { 1'b0, - _theResult___fst_exp__h404315 != 8'd0, - sfdin__h404309[56:34] } + + _theResult___fst_exp__h404316 != 8'd0, + sfdin__h404310[56:34] } + 25'd1 ; - assign sfd__h412989 = + assign sfd__h412990 = { 1'b0, - _theResult___fst_exp__h412971 != 8'd0, - _theResult___snd__h412922[56:34] } + + _theResult___fst_exp__h412972 != 8'd0, + _theResult___snd__h412923[56:34] } + 25'd1 ; - assign sfd__h422173 = + assign sfd__h422174 = { 1'b0, - _theResult___fst_exp__h422081 != 8'd0, - sfdin__h422075[56:34] } + + _theResult___fst_exp__h422082 != 8'd0, + sfdin__h422076[56:34] } + 25'd1 ; - assign sfd__h430785 = + assign sfd__h430786 = { 1'b0, - _theResult___fst_exp__h430766 != 8'd0, - _theResult___snd__h430712[56:34] } + + _theResult___fst_exp__h430767 != 8'd0, + _theResult___snd__h430713[56:34] } + 25'd1 ; - assign sfd__h434299 = { value__h442521, 3'd0 } ; - assign sfd__h450102 = + assign sfd__h434300 = { value__h442522, 3'd0 } ; + assign sfd__h450103 = { 1'b0, - _theResult___fst_exp__h450010 != 8'd0, - sfdin__h450004[56:34] } + + _theResult___fst_exp__h450011 != 8'd0, + sfdin__h450005[56:34] } + 25'd1 ; - assign sfd__h458684 = + assign sfd__h458685 = { 1'b0, - _theResult___fst_exp__h458666 != 8'd0, - _theResult___snd__h458617[56:34] } + + _theResult___fst_exp__h458667 != 8'd0, + _theResult___snd__h458618[56:34] } + 25'd1 ; - assign sfd__h467868 = + assign sfd__h467869 = { 1'b0, - _theResult___fst_exp__h467776 != 8'd0, - sfdin__h467770[56:34] } + + _theResult___fst_exp__h467777 != 8'd0, + sfdin__h467771[56:34] } + 25'd1 ; - assign sfd__h476480 = + assign sfd__h476481 = { 1'b0, - _theResult___fst_exp__h476461 != 8'd0, - _theResult___snd__h476407[56:34] } + + _theResult___fst_exp__h476462 != 8'd0, + _theResult___snd__h476408[56:34] } + 25'd1 ; - assign sfd__h487432 = { value__h492015, 32'd0 } ; - assign sfd__h506476 = + assign sfd__h487433 = { value__h492016, 32'd0 } ; + assign sfd__h506477 = { 1'b0, - _theResult___fst_exp__h506458 != 11'd0, - _theResult___snd__h506409[56:5] } + + _theResult___fst_exp__h506459 != 11'd0, + _theResult___snd__h506410[56:5] } + 54'd1 ; - assign sfd__h516127 = + assign sfd__h516128 = { 1'b0, - _theResult___fst_exp__h516035 != 11'd0, - sfdin__h516029[56:5] } + + _theResult___fst_exp__h516036 != 11'd0, + sfdin__h516030[56:5] } + 54'd1 ; - assign sfd__h524887 = + assign sfd__h524888 = { 1'b0, - _theResult___fst_exp__h524868 != 11'd0, - _theResult___snd__h524814[56:5] } + + _theResult___fst_exp__h524869 != 11'd0, + _theResult___snd__h524815[56:5] } + 54'd1 ; - assign sfd__h526426 = { value__h530868, 32'd0 } ; - assign sfd__h545329 = + assign sfd__h526427 = { value__h530869, 32'd0 } ; + assign sfd__h545330 = { 1'b0, - _theResult___fst_exp__h545311 != 11'd0, - _theResult___snd__h545262[56:5] } + + _theResult___fst_exp__h545312 != 11'd0, + _theResult___snd__h545263[56:5] } + 54'd1 ; - assign sfd__h554980 = + assign sfd__h554981 = { 1'b0, - _theResult___fst_exp__h554888 != 11'd0, - sfdin__h554882[56:5] } + + _theResult___fst_exp__h554889 != 11'd0, + sfdin__h554883[56:5] } + 54'd1 ; - assign sfd__h563740 = + assign sfd__h563741 = { 1'b0, - _theResult___fst_exp__h563721 != 11'd0, - _theResult___snd__h563667[56:5] } + + _theResult___fst_exp__h563722 != 11'd0, + _theResult___snd__h563668[56:5] } + 54'd1 ; - assign sfd__h565730 = { value__h570172, 32'd0 } ; - assign sfd__h584633 = + assign sfd__h565731 = { value__h570173, 32'd0 } ; + assign sfd__h584634 = { 1'b0, - _theResult___fst_exp__h584615 != 11'd0, - _theResult___snd__h584566[56:5] } + + _theResult___fst_exp__h584616 != 11'd0, + _theResult___snd__h584567[56:5] } + 54'd1 ; - assign sfd__h594284 = + assign sfd__h594285 = { 1'b0, - _theResult___fst_exp__h594192 != 11'd0, - sfdin__h594186[56:5] } + + _theResult___fst_exp__h594193 != 11'd0, + sfdin__h594187[56:5] } + 54'd1 ; - assign sfd__h603044 = + assign sfd__h603045 = { 1'b0, - _theResult___fst_exp__h603025 != 11'd0, - _theResult___snd__h602971[56:5] } + + _theResult___fst_exp__h603026 != 11'd0, + _theResult___snd__h602972[56:5] } + 54'd1 ; - assign sfdin__h358612 = - _theResult____h350507[56] ? - _theResult___snd__h358629 : - _theResult___snd__h358640 ; - assign sfdin__h376378 = - _theResult____h368146[56] ? - _theResult___snd__h376395 : - _theResult___snd__h376406 ; - assign sfdin__h404309 = - _theResult____h396206[56] ? - _theResult___snd__h404326 : - _theResult___snd__h404337 ; - assign sfdin__h422075 = - _theResult____h413843[56] ? - _theResult___snd__h422092 : - _theResult___snd__h422103 ; - assign sfdin__h450004 = - _theResult____h441901[56] ? - _theResult___snd__h450021 : - _theResult___snd__h450032 ; - assign sfdin__h467770 = - _theResult____h459538[56] ? - _theResult___snd__h467787 : - _theResult___snd__h467798 ; - assign sfdin__h516029 = - _theResult____h507799[56] ? - _theResult___snd__h516046 : - _theResult___snd__h516057 ; - assign sfdin__h554882 = - _theResult____h546652[56] ? - _theResult___snd__h554899 : - _theResult___snd__h554910 ; - assign sfdin__h594186 = - _theResult____h585956[56] ? - _theResult___snd__h594203 : - _theResult___snd__h594214 ; - assign shiftData__h184461 = - coreFix_memExe_regToExeQ$first[75:12] << x__h184590 ; - assign sie_csr__read__h615980 = { r1__read__h619791, 1'b0 } ; - assign sip_csr__read__h616354 = { r1__read__h620325, 1'b0 } ; - assign spec_bits__h696596 = specTagManager$currentSpecBits | y__h696609 ; - assign sstatus_csr__read__h615910 = { r1__read__h619387, csrf_ie_vec_0 } ; - assign stvec_csr__read__h616023 = - { r1__read__h620301, csrf_stvec_mode_low_reg } ; - assign trap_val__h718389 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h719427 ; - assign tsr_val__h735550 = csrf_tsr_reg ; - assign tvm_val__h735552 = csrf_tvm_reg ; + assign sfdin__h358613 = + _theResult____h350508[56] ? + _theResult___snd__h358630 : + _theResult___snd__h358641 ; + assign sfdin__h376379 = + _theResult____h368147[56] ? + _theResult___snd__h376396 : + _theResult___snd__h376407 ; + assign sfdin__h404310 = + _theResult____h396207[56] ? + _theResult___snd__h404327 : + _theResult___snd__h404338 ; + assign sfdin__h422076 = + _theResult____h413844[56] ? + _theResult___snd__h422093 : + _theResult___snd__h422104 ; + assign sfdin__h450005 = + _theResult____h441902[56] ? + _theResult___snd__h450022 : + _theResult___snd__h450033 ; + assign sfdin__h467771 = + _theResult____h459539[56] ? + _theResult___snd__h467788 : + _theResult___snd__h467799 ; + assign sfdin__h516030 = + _theResult____h507800[56] ? + _theResult___snd__h516047 : + _theResult___snd__h516058 ; + assign sfdin__h554883 = + _theResult____h546653[56] ? + _theResult___snd__h554900 : + _theResult___snd__h554911 ; + assign sfdin__h594187 = + _theResult____h585957[56] ? + _theResult___snd__h594204 : + _theResult___snd__h594215 ; + assign shiftData__h184462 = + coreFix_memExe_regToExeQ$first[75:12] << x__h184591 ; + assign sie_csr__read__h615981 = { r1__read__h619792, 1'b0 } ; + assign sip_csr__read__h616355 = { r1__read__h620326, 1'b0 } ; + assign spec_bits__h696597 = specTagManager$currentSpecBits | y__h696610 ; + assign sstatus_csr__read__h615911 = { r1__read__h619388, csrf_ie_vec_0 } ; + assign stvec_csr__read__h616024 = + { r1__read__h620302, csrf_stvec_mode_low_reg } ; + assign trap_val__h718390 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h719428 ; + assign tsr_val__h735421 = csrf_tsr_reg ; + assign tvm_val__h735423 = csrf_tvm_reg ; assign upd__h3994 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h5311 = n__read__h6760 + 64'd1 ; - assign upd__h6874 = + assign upd__h5311 = n__read__h6761 + 64'd1 ; + assign upd__h6875 = MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h736047 = + assign upd__h735918 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h300363 = + assign v__h300364 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3131) ? - v__h300594 : + v__h300595 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h300594 = + assign v__h300595 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h303708 = + assign v__h303709 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3238) ? - v__h304226 : + v__h304227 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h304226 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h314222 = + assign v__h304227 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h314223 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3409) ? - v__h314453 : + v__h314454 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h314453 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h318098 = + assign v__h314454 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h318099 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3505) ? - v__h318329 : + v__h318330 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h318329 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h332699 = + assign v__h318330 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h332700 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3734) ? - v__h332930 : + v__h332931 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h332930 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h335924 = + assign v__h332931 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h335925 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3828) ? - v__h336155 : + v__h336156 : coreFix_memExe_forwardQ_enqP ; - assign v__h336155 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h609135 = + assign v__h336156 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h609136 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h609145 : + v__h609146 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h609145 = + assign v__h609146 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h610176 = v__h609135 - 2'd1 ; - assign v__h614197 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615331 ; - assign v__h639578 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640559 ; - assign value__h351129 = + assign v__h610177 = v__h609136 - 2'd1 ; + assign v__h614198 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615332 ; + assign v__h639579 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640560 ; + assign value__h351130 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h396826 = + assign value__h396827 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h442521 = + assign value__h442522 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h492015 = { 1'b0, f1_exp__h487070 != 8'd0, f1_sfd__h487071 } ; - assign value__h530868 = { 1'b0, f2_exp__h526064 != 8'd0, f2_sfd__h526065 } ; - assign value__h570172 = { 1'b0, f3_exp__h565368 != 8'd0, f3_sfd__h565369 } ; - assign vm_mode_reg__read__h620541 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h653948 = + assign value__h492016 = { 1'b0, f1_exp__h487071 != 8'd0, f1_sfd__h487072 } ; + assign value__h530869 = { 1'b0, f2_exp__h526065 != 8'd0, f2_sfd__h526066 } ; + assign value__h570173 = { 1'b0, f3_exp__h565369 != 8'd0, f3_sfd__h565370 } ; + assign vm_mode_reg__read__h620542 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h653949 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h654004 : + result__h654005 : 12'd4095 ; - assign x__h155283 = + assign x__h155284 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h155289 = + assign x__h155290 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h158830 = { 3'd0, sbIdx__h158709 } ; - assign x__h158836 = + assign x__h158831 = { 3'd0, sbIdx__h158710 } ; + assign x__h158837 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h161646 = + assign x__h161647 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h161650 = + assign x__h161651 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h163498 = + assign x__h163499 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h18386 = + assign x__h18387 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h184368 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183534 ; assign x__h184369 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184215 ; - assign x__h184590 = { x__h186793[2:0], 3'b0 } ; - assign x__h186793 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183535 ; + assign x__h184370 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184216 ; + assign x__h184591 = { x__h186794[2:0], 3'b0 } ; + assign x__h186794 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ; - assign x__h196617 = + assign x__h196618 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h195854[63:32] : - curData__h195854[31:0] ; - assign x__h20924 = + curData__h195855[63:32] : + curData__h195855[31:0] ; + assign x__h20925 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h291634 = + assign x__h291635 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h291646 = + assign x__h291647 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h293500 = + assign x__h293501 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h306573 = + assign x__h306574 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h342306 = - { (_theResult___exp__h385638 != 8'd255 || - _theResult___sfd__h385639 == 23'd0) && + assign x__h342307 = + { (_theResult___exp__h385639 != 8'd255 || + _theResult___sfd__h385640 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5240, - out_f_exp__h385915, - out_f_sfd__h385916 } ; - assign x__h368856 = - sfd__h342902 << (x__h368889[11] ? 12'hAAA : x__h368889) ; - assign x__h368889 = + out_f_exp__h385916, + out_f_sfd__h385917 } ; + assign x__h368857 = + sfd__h342903 << (x__h368890[11] ? 12'hAAA : x__h368890) ; + assign x__h368890 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4654 ; - assign x__h388008 = - { (_theResult___exp__h431335 != 8'd255 || - _theResult___sfd__h431336 == 23'd0) && + assign x__h388009 = + { (_theResult___exp__h431336 != 8'd255 || + _theResult___sfd__h431337 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6632, - out_f_exp__h431612, - out_f_sfd__h431613 } ; - assign x__h414553 = - sfd__h388604 << (x__h414586[11] ? 12'hAAA : x__h414586) ; - assign x__h414586 = + out_f_exp__h431613, + out_f_sfd__h431614 } ; + assign x__h414554 = + sfd__h388605 << (x__h414587[11] ? 12'hAAA : x__h414587) ; + assign x__h414587 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6046 ; - assign x__h433703 = - { (_theResult___exp__h477030 != 8'd255 || - _theResult___sfd__h477031 == 23'd0) && + assign x__h433704 = + { (_theResult___exp__h477031 != 8'd255 || + _theResult___sfd__h477032 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8024, - out_f_exp__h477307, - out_f_sfd__h477308 } ; - assign x__h460248 = - sfd__h434299 << (x__h460281[11] ? 12'hAAA : x__h460281) ; - assign x__h460281 = + out_f_exp__h477308, + out_f_sfd__h477309 } ; + assign x__h460249 = + sfd__h434300 << (x__h460282[11] ? 12'hAAA : x__h460282) ; + assign x__h460282 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7438 ; - assign x__h46293 = + assign x__h46294 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h486592 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h483731 ; assign x__h486593 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484414 ; + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h483732 ; assign x__h486594 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485091 ; - assign x__h48829 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484415 ; + assign x__h486595 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485092 ; + assign x__h48830 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h508507 = sfd__h487432 << x__h508540 ; - assign x__h508540 = + assign x__h508508 = sfd__h487433 << x__h508541 ; + assign x__h508541 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8764 ; - assign x__h547360 = sfd__h526426 << x__h547393 ; - assign x__h547393 = + assign x__h547361 = sfd__h526427 << x__h547394 ; + assign x__h547394 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10249 ; - assign x__h586664 = sfd__h565730 << x__h586697 ; - assign x__h586697 = + assign x__h586665 = sfd__h565731 << x__h586698 ; + assign x__h586698 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9479 ; - assign x__h608453 = + assign x__h608454 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h608464 : - a__h607916 ; - assign x__h608479 = a__h607916[63] ^ b__h607917[63] ; - assign x__h609065 = + _theResult___fst__h608465 : + a__h607917 ; + assign x__h608480 = a__h607917[63] ^ b__h607918[63] ; + assign x__h609066 = (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT == 64'd0) ? { 64'hFFFFFFFFFFFFFFFF, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } : { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11260, coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11261 } ; - assign x__h619372 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h623643 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h615388 : - v__h614197 ; + assign x__h619373 = { csrf_frm_reg, csrf_fflags_reg } ; assign x__h623644 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621621 ; - assign x__h646650 = - coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h640614 : - v__h639578 ; + coreFix_aluExe_1_dispToRegQ$first[131] ? + rVal1__h615389 : + v__h614198 ; + assign x__h623645 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621622 ; assign x__h646651 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644638 ; - assign x__h653952 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h654003 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h711187 = + coreFix_aluExe_0_dispToRegQ$first[131] ? + rVal1__h640615 : + v__h639579 ; + assign x__h646652 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644639 ; + assign x__h653953 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h654004 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h711188 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h721363 = { cause_code__h718388, 2'b0 } ; - assign x__h723590 = + assign x__h721364 = { cause_code__h718389, 2'b0 } ; + assign x__h723591 = { csrf_fs_reg == 2'b11, IF_csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_c_ETC___d15232 } ; - assign x__h723782 = - { commitStage_commitTrap[36], 59'b0, cause_code__h718388 } ; - assign x__h731805 = { 1'b0, csrf_spp_reg } ; - assign x__h735430 = + assign x__h723783 = + { commitStage_commitTrap[36], 59'b0, cause_code__h718389 } ; + assign x__h731806 = { 1'b0, csrf_spp_reg } ; + assign x__h735301 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32467,8 +32467,8 @@ module mkCore(CLK, 2'd0, csrf_fs_reg, IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15602 } ; - assign x__h739233 = - { r1__read_BITS_62_TO_14___h739253, + assign x__h739104 = + { r1__read_BITS_62_TO_14___h739124, 2'b11, csrf_mpp_reg, 2'b0, @@ -32481,56 +32481,56 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h742438 = - { y_avValue_snd_snd_snd_snd_snd_snd_snd__h742420[63:15], + assign x__h742309 = + { y_avValue_snd_snd_snd_snd_snd_snd_snd__h742291[63:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h742420[12:0] } ; - assign x__h743248 = + y_avValue_snd_snd_snd_snd_snd_snd_snd__h742291[12:0] } ; + assign x__h743119 = NOT_rob_deqPort_0_canDeq__5640_5641_OR_rob_deq_ETC___d15988 ? - y_avValue_snd_snd_snd_fst__h743058 : + y_avValue_snd_snd_snd_fst__h742929 : IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d16013 ; - assign x__h76238 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h318496 = + assign x__h76239 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h318497 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h66087 = + assign x_data__h66088 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h684505 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h701171 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h662270 = csrf_frm_reg ; - assign x_prv__h721432 = + assign x_data_imm__h684506 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h701172 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h662271 = csrf_frm_reg ; + assign x_prv__h721433 = csrf_prv_reg_read__3022_ULE_1_5008_AND_IF_comm_ETC___d15030 ? 2'd1 : 2'd3 ; - assign x_prv__h732255 = + assign x_prv__h732256 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h731805 : + x__h731806 : csrf_mpp_reg ; - assign x_quotient__h479691 = + assign x_quotient__h479692 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ? - q___1__h480476 : + q___1__h480477 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ; - assign x_reg_ifc__read__h615819 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h479692 = + assign x_reg_ifc__read__h615820 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h479693 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ? - r___1__h480503 : + r___1__h480504 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ; - assign y__h258551 = + assign y__h258552 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h626401 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; - assign y__h649115 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; - assign y__h653982 = ~x__h653952 ; - assign y__h658913 = + assign y__h626402 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ; + assign y__h649116 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ; + assign y__h653983 = ~x__h653953 ; + assign y__h658914 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -32539,66 +32539,66 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h696609 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h740125 = + assign y__h696610 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h739996 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h740148 : + y_avValue_snd_snd_snd_snd_snd_fst__h740019 : 64'd0 ; - assign y__h743007 = + assign y__h742878 = NOT_rob_deqPort_0_canDeq__5640_5641_OR_rob_deq_ETC___d15988 ? - y_avValue_snd_snd_snd_snd_snd_fst__h743068 : - y__h740125 ; - assign y_avValue__h183534 = + y_avValue_snd_snd_snd_snd_snd_fst__h742939 : + y__h739996 ; + assign y_avValue__h183535 = NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1612 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1680 ; - assign y_avValue__h184215 = + assign y_avValue__h184216 = NOT_coreFix_memExe_bypassWire_0_whas__585_591__ETC___d1641 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__585_5_ETC___d1688 ; - assign y_avValue__h483731 = + assign y_avValue__h483732 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8331 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8458 ; - assign y_avValue__h484414 = + assign y_avValue__h484415 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8360 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8466 ; - assign y_avValue__h485091 = + assign y_avValue__h485092 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8386 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8474 ; - assign y_avValue__h615331 = + assign y_avValue__h615332 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1522_1_ETC___d11549 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__152_ETC___d11971 ; - assign y_avValue__h621621 = + assign y_avValue__h621622 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1522_1_ETC___d11579 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__152_ETC___d11980 ; - assign y_avValue__h640559 = + assign y_avValue__h640560 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12437 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__241_ETC___d12673 ; - assign y_avValue__h644638 = + assign y_avValue__h644639 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2410_2_ETC___d12467 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__241_ETC___d12682 ; - assign y_avValue_fst__h689769 = + assign y_avValue_fst__h689770 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h696596 : + spec_bits__h696597 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h689798 = + assign y_avValue_fst__h689799 = IF_fetchStage_pipelines_0_first__2992_BITS_194_ETC___d13734 ? - y_avValue_fst__h689769 : + y_avValue_fst__h689770 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h689832 = + assign y_avValue_fst__h689833 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3653_AND__ETC___d13675) ? - y_avValue_fst__h689798 : + y_avValue_fst__h689799 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h739663 = + assign y_avValue_fst__h739534 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32612,10 +32612,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h742889 = + assign y_avValue_fst__h742760 = IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d15994 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h742921 = + assign y_avValue_fst__h742792 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32628,16 +32628,16 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d15994 : - y_avValue_fst__h742889 ; - assign y_avValue_new_pc__h721124 = + y_avValue_fst__h742760 ; + assign y_avValue_new_pc__h721125 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h721348 + { 58'd0, x__h721363 } : - base__h721348 ; - assign y_avValue_new_pc__h721310 = + base__h721349 + { 58'd0, x__h721364 } : + base__h721349 ; + assign y_avValue_new_pc__h721311 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h721368 + { 58'd0, x__h721363 } : - base__h721368 ; - assign y_avValue_snd_snd_snd_fst__h740138 = + base__h721369 + { 58'd0, x__h721364 } : + base__h721369 ; + assign y_avValue_snd_snd_snd_fst__h740009 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32651,7 +32651,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h743058 = + assign y_avValue_snd_snd_snd_fst__h742929 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32664,11 +32664,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d16013 : - y_avValue_snd_snd_snd_fst__h743094 ; - assign y_avValue_snd_snd_snd_fst__h743094 = + y_avValue_snd_snd_snd_fst__h742965 ; + assign y_avValue_snd_snd_snd_fst__h742965 = IF_rob_deqPort_0_canDeq__5640_THEN_IF_NOT_rob__ETC___d16013 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h740148 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h740019 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32682,7 +32682,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h743068 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h742939 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32694,10 +32694,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h740125 : - y_avValue_snd_snd_snd_snd_snd_fst__h743104 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h743104 = y__h740125 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h742420 = x__h739233 ; + y__h739996 : + y_avValue_snd_snd_snd_snd_snd_fst__h742975 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h742975 = y__h739996 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h742291 = x__h739104 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32898,28 +32898,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h200593 = + x__h200594 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -32935,28 +32935,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h290201 = + x__h290202 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -32966,10 +32966,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h294422 = + addr__h294423 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h294422 = + addr__h294423 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -32978,37 +32978,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h195854 = + curData__h195855 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h719427 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h719427 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h719427 = + 4'd0, 4'd3: trap_val__h719428 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h719428 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h719428 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -33022,360 +33022,360 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h295971 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h295972 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h295971 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h295972 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h615689 or - frm_csr__read__h615700 or - fcsr_csr__read__h615714 or - sstatus_csr__read__h615910 or - sie_csr__read__h615980 or - stvec_csr__read__h616023 or - scounteren_csr__read__h616076 or + fflags_csr__read__h615690 or + frm_csr__read__h615701 or + fcsr_csr__read__h615715 or + sstatus_csr__read__h615911 or + sie_csr__read__h615981 or + stvec_csr__read__h616024 or + scounteren_csr__read__h616077 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616214 or + scause_csr__read__h616215 or csrf_stval_csr or - sip_csr__read__h616354 or - satp_csr__read__h616417 or - mstatus_csr__read__h616560 or - medeleg_csr__read__h616708 or - mideleg_csr__read__h616803 or - mie_csr__read__h616927 or - mtvec_csr__read__h617009 or - mcounteren_csr__read__h617101 or + sip_csr__read__h616355 or + satp_csr__read__h616418 or + mstatus_csr__read__h616561 or + medeleg_csr__read__h616709 or + mideleg_csr__read__h616804 or + mie_csr__read__h616928 or + mtvec_csr__read__h617010 or + mcounteren_csr__read__h617102 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617356 or + mcause_csr__read__h617357 or csrf_mtval_csr or - mip_csr__read__h617589 or + mip_csr__read__h617590 or csrf_rg_tselect or - rg_tdata1__read__h618544 or + rg_tdata1__read__h618545 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h615819 or - n__read__h617693 or n__read__h617884 or csrf_time_reg) + x_reg_ifc__read__h615820 or + n__read__h617694 or n__read__h617885 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h747098 = fflags_csr__read__h615689; - 12'd2: data_out__h747098 = frm_csr__read__h615700; - 12'd3: data_out__h747098 = fcsr_csr__read__h615714; - 12'd256: data_out__h747098 = sstatus_csr__read__h615910; - 12'd260: data_out__h747098 = sie_csr__read__h615980; - 12'd261: data_out__h747098 = stvec_csr__read__h616023; - 12'd262: data_out__h747098 = scounteren_csr__read__h616076; - 12'd320: data_out__h747098 = csrf_sscratch_csr; - 12'd321: data_out__h747098 = csrf_sepc_csr; - 12'd322: data_out__h747098 = scause_csr__read__h616214; - 12'd323: data_out__h747098 = csrf_stval_csr; - 12'd324: data_out__h747098 = sip_csr__read__h616354; - 12'd384: data_out__h747098 = satp_csr__read__h616417; - 12'd768: data_out__h747098 = mstatus_csr__read__h616560; - 12'd769: data_out__h747098 = 64'h800000000014112D; - 12'd770: data_out__h747098 = medeleg_csr__read__h616708; - 12'd771: data_out__h747098 = mideleg_csr__read__h616803; - 12'd772: data_out__h747098 = mie_csr__read__h616927; - 12'd773: data_out__h747098 = mtvec_csr__read__h617009; - 12'd774: data_out__h747098 = mcounteren_csr__read__h617101; - 12'd832: data_out__h747098 = csrf_mscratch_csr; - 12'd833: data_out__h747098 = csrf_mepc_csr; - 12'd834: data_out__h747098 = mcause_csr__read__h617356; - 12'd835: data_out__h747098 = csrf_mtval_csr; - 12'd836: data_out__h747098 = mip_csr__read__h617589; - 12'd1952: data_out__h747098 = csrf_rg_tselect; - 12'd1953: data_out__h747098 = rg_tdata1__read__h618544; - 12'd1954: data_out__h747098 = csrf_rg_tdata2; - 12'd1955: data_out__h747098 = csrf_rg_tdata3; - 12'd1968: data_out__h747098 = csrf_rg_dcsr; - 12'd1969: data_out__h747098 = csrf_rg_dpc; - 12'd1970: data_out__h747098 = csrf_rg_dscratch0; - 12'd1971: data_out__h747098 = csrf_rg_dscratch1; + 12'd1: data_out__h746969 = fflags_csr__read__h615690; + 12'd2: data_out__h746969 = frm_csr__read__h615701; + 12'd3: data_out__h746969 = fcsr_csr__read__h615715; + 12'd256: data_out__h746969 = sstatus_csr__read__h615911; + 12'd260: data_out__h746969 = sie_csr__read__h615981; + 12'd261: data_out__h746969 = stvec_csr__read__h616024; + 12'd262: data_out__h746969 = scounteren_csr__read__h616077; + 12'd320: data_out__h746969 = csrf_sscratch_csr; + 12'd321: data_out__h746969 = csrf_sepc_csr; + 12'd322: data_out__h746969 = scause_csr__read__h616215; + 12'd323: data_out__h746969 = csrf_stval_csr; + 12'd324: data_out__h746969 = sip_csr__read__h616355; + 12'd384: data_out__h746969 = satp_csr__read__h616418; + 12'd768: data_out__h746969 = mstatus_csr__read__h616561; + 12'd769: data_out__h746969 = 64'h800000000014112D; + 12'd770: data_out__h746969 = medeleg_csr__read__h616709; + 12'd771: data_out__h746969 = mideleg_csr__read__h616804; + 12'd772: data_out__h746969 = mie_csr__read__h616928; + 12'd773: data_out__h746969 = mtvec_csr__read__h617010; + 12'd774: data_out__h746969 = mcounteren_csr__read__h617102; + 12'd832: data_out__h746969 = csrf_mscratch_csr; + 12'd833: data_out__h746969 = csrf_mepc_csr; + 12'd834: data_out__h746969 = mcause_csr__read__h617357; + 12'd835: data_out__h746969 = csrf_mtval_csr; + 12'd836: data_out__h746969 = mip_csr__read__h617590; + 12'd1952: data_out__h746969 = csrf_rg_tselect; + 12'd1953: data_out__h746969 = rg_tdata1__read__h618545; + 12'd1954: data_out__h746969 = csrf_rg_tdata2; + 12'd1955: data_out__h746969 = csrf_rg_tdata3; + 12'd1968: data_out__h746969 = csrf_rg_dcsr; + 12'd1969: data_out__h746969 = csrf_rg_dpc; + 12'd1970: data_out__h746969 = csrf_rg_dscratch0; + 12'd1971: data_out__h746969 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h747098 = 64'd0; - 12'd2049: data_out__h747098 = x_reg_ifc__read__h615819; - 12'd2816, 12'd3072: data_out__h747098 = n__read__h617693; - 12'd2818, 12'd3074: data_out__h747098 = n__read__h617884; - 12'd3073: data_out__h747098 = csrf_time_reg; - default: data_out__h747098 = 64'b0; + data_out__h746969 = 64'd0; + 12'd2049: data_out__h746969 = x_reg_ifc__read__h615820; + 12'd2816, 12'd3072: data_out__h746969 = n__read__h617694; + 12'd2818, 12'd3074: data_out__h746969 = n__read__h617885; + 12'd3073: data_out__h746969 = csrf_time_reg; + default: data_out__h746969 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h615689 or - frm_csr__read__h615700 or - fcsr_csr__read__h615714 or - sstatus_csr__read__h615910 or - sie_csr__read__h615980 or - stvec_csr__read__h616023 or - scounteren_csr__read__h616076 or + fflags_csr__read__h615690 or + frm_csr__read__h615701 or + fcsr_csr__read__h615715 or + sstatus_csr__read__h615911 or + sie_csr__read__h615981 or + stvec_csr__read__h616024 or + scounteren_csr__read__h616077 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616214 or + scause_csr__read__h616215 or csrf_stval_csr or - sip_csr__read__h616354 or - satp_csr__read__h616417 or - mstatus_csr__read__h616560 or - medeleg_csr__read__h616708 or - mideleg_csr__read__h616803 or - mie_csr__read__h616927 or - mtvec_csr__read__h617009 or - mcounteren_csr__read__h617101 or + sip_csr__read__h616355 or + satp_csr__read__h616418 or + mstatus_csr__read__h616561 or + medeleg_csr__read__h616709 or + mideleg_csr__read__h616804 or + mie_csr__read__h616928 or + mtvec_csr__read__h617010 or + mcounteren_csr__read__h617102 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617356 or + mcause_csr__read__h617357 or csrf_mtval_csr or - mip_csr__read__h617589 or + mip_csr__read__h617590 or csrf_rg_tselect or - rg_tdata1__read__h618544 or + rg_tdata1__read__h618545 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h615819 or - n__read__h617693 or n__read__h617884 or csrf_time_reg) + x_reg_ifc__read__h615820 or + n__read__h617694 or n__read__h617885 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h615388 = fflags_csr__read__h615689; - 12'd2: rVal1__h615388 = frm_csr__read__h615700; - 12'd3: rVal1__h615388 = fcsr_csr__read__h615714; - 12'd256: rVal1__h615388 = sstatus_csr__read__h615910; - 12'd260: rVal1__h615388 = sie_csr__read__h615980; - 12'd261: rVal1__h615388 = stvec_csr__read__h616023; - 12'd262: rVal1__h615388 = scounteren_csr__read__h616076; - 12'd320: rVal1__h615388 = csrf_sscratch_csr; - 12'd321: rVal1__h615388 = csrf_sepc_csr; - 12'd322: rVal1__h615388 = scause_csr__read__h616214; - 12'd323: rVal1__h615388 = csrf_stval_csr; - 12'd324: rVal1__h615388 = sip_csr__read__h616354; - 12'd384: rVal1__h615388 = satp_csr__read__h616417; - 12'd768: rVal1__h615388 = mstatus_csr__read__h616560; - 12'd769: rVal1__h615388 = 64'h800000000014112D; - 12'd770: rVal1__h615388 = medeleg_csr__read__h616708; - 12'd771: rVal1__h615388 = mideleg_csr__read__h616803; - 12'd772: rVal1__h615388 = mie_csr__read__h616927; - 12'd773: rVal1__h615388 = mtvec_csr__read__h617009; - 12'd774: rVal1__h615388 = mcounteren_csr__read__h617101; - 12'd832: rVal1__h615388 = csrf_mscratch_csr; - 12'd833: rVal1__h615388 = csrf_mepc_csr; - 12'd834: rVal1__h615388 = mcause_csr__read__h617356; - 12'd835: rVal1__h615388 = csrf_mtval_csr; - 12'd836: rVal1__h615388 = mip_csr__read__h617589; - 12'd1952: rVal1__h615388 = csrf_rg_tselect; - 12'd1953: rVal1__h615388 = rg_tdata1__read__h618544; - 12'd1954: rVal1__h615388 = csrf_rg_tdata2; - 12'd1955: rVal1__h615388 = csrf_rg_tdata3; - 12'd1968: rVal1__h615388 = csrf_rg_dcsr; - 12'd1969: rVal1__h615388 = csrf_rg_dpc; - 12'd1970: rVal1__h615388 = csrf_rg_dscratch0; - 12'd1971: rVal1__h615388 = csrf_rg_dscratch1; + 12'd1: rVal1__h615389 = fflags_csr__read__h615690; + 12'd2: rVal1__h615389 = frm_csr__read__h615701; + 12'd3: rVal1__h615389 = fcsr_csr__read__h615715; + 12'd256: rVal1__h615389 = sstatus_csr__read__h615911; + 12'd260: rVal1__h615389 = sie_csr__read__h615981; + 12'd261: rVal1__h615389 = stvec_csr__read__h616024; + 12'd262: rVal1__h615389 = scounteren_csr__read__h616077; + 12'd320: rVal1__h615389 = csrf_sscratch_csr; + 12'd321: rVal1__h615389 = csrf_sepc_csr; + 12'd322: rVal1__h615389 = scause_csr__read__h616215; + 12'd323: rVal1__h615389 = csrf_stval_csr; + 12'd324: rVal1__h615389 = sip_csr__read__h616355; + 12'd384: rVal1__h615389 = satp_csr__read__h616418; + 12'd768: rVal1__h615389 = mstatus_csr__read__h616561; + 12'd769: rVal1__h615389 = 64'h800000000014112D; + 12'd770: rVal1__h615389 = medeleg_csr__read__h616709; + 12'd771: rVal1__h615389 = mideleg_csr__read__h616804; + 12'd772: rVal1__h615389 = mie_csr__read__h616928; + 12'd773: rVal1__h615389 = mtvec_csr__read__h617010; + 12'd774: rVal1__h615389 = mcounteren_csr__read__h617102; + 12'd832: rVal1__h615389 = csrf_mscratch_csr; + 12'd833: rVal1__h615389 = csrf_mepc_csr; + 12'd834: rVal1__h615389 = mcause_csr__read__h617357; + 12'd835: rVal1__h615389 = csrf_mtval_csr; + 12'd836: rVal1__h615389 = mip_csr__read__h617590; + 12'd1952: rVal1__h615389 = csrf_rg_tselect; + 12'd1953: rVal1__h615389 = rg_tdata1__read__h618545; + 12'd1954: rVal1__h615389 = csrf_rg_tdata2; + 12'd1955: rVal1__h615389 = csrf_rg_tdata3; + 12'd1968: rVal1__h615389 = csrf_rg_dcsr; + 12'd1969: rVal1__h615389 = csrf_rg_dpc; + 12'd1970: rVal1__h615389 = csrf_rg_dscratch0; + 12'd1971: rVal1__h615389 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h615388 = 64'd0; - 12'd2049: rVal1__h615388 = x_reg_ifc__read__h615819; - 12'd2816, 12'd3072: rVal1__h615388 = n__read__h617693; - 12'd2818, 12'd3074: rVal1__h615388 = n__read__h617884; - 12'd3073: rVal1__h615388 = csrf_time_reg; - default: rVal1__h615388 = 64'b0; + rVal1__h615389 = 64'd0; + 12'd2049: rVal1__h615389 = x_reg_ifc__read__h615820; + 12'd2816, 12'd3072: rVal1__h615389 = n__read__h617694; + 12'd2818, 12'd3074: rVal1__h615389 = n__read__h617885; + 12'd3073: rVal1__h615389 = csrf_time_reg; + default: rVal1__h615389 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h615689 or - frm_csr__read__h615700 or - fcsr_csr__read__h615714 or - sstatus_csr__read__h615910 or - sie_csr__read__h615980 or - stvec_csr__read__h616023 or - scounteren_csr__read__h616076 or + fflags_csr__read__h615690 or + frm_csr__read__h615701 or + fcsr_csr__read__h615715 or + sstatus_csr__read__h615911 or + sie_csr__read__h615981 or + stvec_csr__read__h616024 or + scounteren_csr__read__h616077 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h616214 or + scause_csr__read__h616215 or csrf_stval_csr or - sip_csr__read__h616354 or - satp_csr__read__h616417 or - mstatus_csr__read__h616560 or - medeleg_csr__read__h616708 or - mideleg_csr__read__h616803 or - mie_csr__read__h616927 or - mtvec_csr__read__h617009 or - mcounteren_csr__read__h617101 or + sip_csr__read__h616355 or + satp_csr__read__h616418 or + mstatus_csr__read__h616561 or + medeleg_csr__read__h616709 or + mideleg_csr__read__h616804 or + mie_csr__read__h616928 or + mtvec_csr__read__h617010 or + mcounteren_csr__read__h617102 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h617356 or + mcause_csr__read__h617357 or csrf_mtval_csr or - mip_csr__read__h617589 or + mip_csr__read__h617590 or csrf_rg_tselect or - rg_tdata1__read__h618544 or + rg_tdata1__read__h618545 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h615819 or - n__read__h617693 or n__read__h617884 or csrf_time_reg) + x_reg_ifc__read__h615820 or + n__read__h617694 or n__read__h617885 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h640614 = fflags_csr__read__h615689; - 12'd2: rVal1__h640614 = frm_csr__read__h615700; - 12'd3: rVal1__h640614 = fcsr_csr__read__h615714; - 12'd256: rVal1__h640614 = sstatus_csr__read__h615910; - 12'd260: rVal1__h640614 = sie_csr__read__h615980; - 12'd261: rVal1__h640614 = stvec_csr__read__h616023; - 12'd262: rVal1__h640614 = scounteren_csr__read__h616076; - 12'd320: rVal1__h640614 = csrf_sscratch_csr; - 12'd321: rVal1__h640614 = csrf_sepc_csr; - 12'd322: rVal1__h640614 = scause_csr__read__h616214; - 12'd323: rVal1__h640614 = csrf_stval_csr; - 12'd324: rVal1__h640614 = sip_csr__read__h616354; - 12'd384: rVal1__h640614 = satp_csr__read__h616417; - 12'd768: rVal1__h640614 = mstatus_csr__read__h616560; - 12'd769: rVal1__h640614 = 64'h800000000014112D; - 12'd770: rVal1__h640614 = medeleg_csr__read__h616708; - 12'd771: rVal1__h640614 = mideleg_csr__read__h616803; - 12'd772: rVal1__h640614 = mie_csr__read__h616927; - 12'd773: rVal1__h640614 = mtvec_csr__read__h617009; - 12'd774: rVal1__h640614 = mcounteren_csr__read__h617101; - 12'd832: rVal1__h640614 = csrf_mscratch_csr; - 12'd833: rVal1__h640614 = csrf_mepc_csr; - 12'd834: rVal1__h640614 = mcause_csr__read__h617356; - 12'd835: rVal1__h640614 = csrf_mtval_csr; - 12'd836: rVal1__h640614 = mip_csr__read__h617589; - 12'd1952: rVal1__h640614 = csrf_rg_tselect; - 12'd1953: rVal1__h640614 = rg_tdata1__read__h618544; - 12'd1954: rVal1__h640614 = csrf_rg_tdata2; - 12'd1955: rVal1__h640614 = csrf_rg_tdata3; - 12'd1968: rVal1__h640614 = csrf_rg_dcsr; - 12'd1969: rVal1__h640614 = csrf_rg_dpc; - 12'd1970: rVal1__h640614 = csrf_rg_dscratch0; - 12'd1971: rVal1__h640614 = csrf_rg_dscratch1; + 12'd1: rVal1__h640615 = fflags_csr__read__h615690; + 12'd2: rVal1__h640615 = frm_csr__read__h615701; + 12'd3: rVal1__h640615 = fcsr_csr__read__h615715; + 12'd256: rVal1__h640615 = sstatus_csr__read__h615911; + 12'd260: rVal1__h640615 = sie_csr__read__h615981; + 12'd261: rVal1__h640615 = stvec_csr__read__h616024; + 12'd262: rVal1__h640615 = scounteren_csr__read__h616077; + 12'd320: rVal1__h640615 = csrf_sscratch_csr; + 12'd321: rVal1__h640615 = csrf_sepc_csr; + 12'd322: rVal1__h640615 = scause_csr__read__h616215; + 12'd323: rVal1__h640615 = csrf_stval_csr; + 12'd324: rVal1__h640615 = sip_csr__read__h616355; + 12'd384: rVal1__h640615 = satp_csr__read__h616418; + 12'd768: rVal1__h640615 = mstatus_csr__read__h616561; + 12'd769: rVal1__h640615 = 64'h800000000014112D; + 12'd770: rVal1__h640615 = medeleg_csr__read__h616709; + 12'd771: rVal1__h640615 = mideleg_csr__read__h616804; + 12'd772: rVal1__h640615 = mie_csr__read__h616928; + 12'd773: rVal1__h640615 = mtvec_csr__read__h617010; + 12'd774: rVal1__h640615 = mcounteren_csr__read__h617102; + 12'd832: rVal1__h640615 = csrf_mscratch_csr; + 12'd833: rVal1__h640615 = csrf_mepc_csr; + 12'd834: rVal1__h640615 = mcause_csr__read__h617357; + 12'd835: rVal1__h640615 = csrf_mtval_csr; + 12'd836: rVal1__h640615 = mip_csr__read__h617590; + 12'd1952: rVal1__h640615 = csrf_rg_tselect; + 12'd1953: rVal1__h640615 = rg_tdata1__read__h618545; + 12'd1954: rVal1__h640615 = csrf_rg_tdata2; + 12'd1955: rVal1__h640615 = csrf_rg_tdata3; + 12'd1968: rVal1__h640615 = csrf_rg_dcsr; + 12'd1969: rVal1__h640615 = csrf_rg_dpc; + 12'd1970: rVal1__h640615 = csrf_rg_dscratch0; + 12'd1971: rVal1__h640615 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h640614 = 64'd0; - 12'd2049: rVal1__h640614 = x_reg_ifc__read__h615819; - 12'd2816, 12'd3072: rVal1__h640614 = n__read__h617693; - 12'd2818, 12'd3074: rVal1__h640614 = n__read__h617884; - 12'd3073: rVal1__h640614 = csrf_time_reg; - default: rVal1__h640614 = 64'b0; + rVal1__h640615 = 64'd0; + 12'd2049: rVal1__h640615 = x_reg_ifc__read__h615820; + 12'd2816, 12'd3072: rVal1__h640615 = n__read__h617694; + 12'd2818, 12'd3074: rVal1__h640615 = n__read__h617885; + 12'd3073: rVal1__h640615 = csrf_time_reg; + default: rVal1__h640615 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h350489 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h350490 = 8'd255; 3'd2: - _theResult___fst_exp__h350489 = + _theResult___fst_exp__h350490 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h350489 = + _theResult___fst_exp__h350490 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h350489 = 8'd254; - default: _theResult___fst_exp__h350489 = 8'd0; + 3'd4: _theResult___fst_exp__h350490 = 8'd254; + default: _theResult___fst_exp__h350490 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h350490 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h350491 = 23'd0; 3'd2: - _theResult___fst_sfd__h350490 = + _theResult___fst_sfd__h350491 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h350490 = + _theResult___fst_sfd__h350491 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h350490 = 23'd8388607; - default: _theResult___fst_sfd__h350490 = 23'd0; + 3'd4: _theResult___fst_sfd__h350491 = 23'd8388607; + default: _theResult___fst_sfd__h350491 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h396188 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h396189 = 8'd255; 3'd2: - _theResult___fst_exp__h396188 = + _theResult___fst_exp__h396189 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h396188 = + _theResult___fst_exp__h396189 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h396188 = 8'd254; - default: _theResult___fst_exp__h396188 = 8'd0; + 3'd4: _theResult___fst_exp__h396189 = 8'd254; + default: _theResult___fst_exp__h396189 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h396189 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h396190 = 23'd0; 3'd2: - _theResult___fst_sfd__h396189 = + _theResult___fst_sfd__h396190 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h396189 = + _theResult___fst_sfd__h396190 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h396189 = 23'd8388607; - default: _theResult___fst_sfd__h396189 = 23'd0; + 3'd4: _theResult___fst_sfd__h396190 = 23'd8388607; + default: _theResult___fst_sfd__h396190 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h441883 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h441884 = 8'd255; 3'd2: - _theResult___fst_exp__h441883 = + _theResult___fst_exp__h441884 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h441883 = + _theResult___fst_exp__h441884 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h441883 = 8'd254; - default: _theResult___fst_exp__h441883 = 8'd0; + 3'd4: _theResult___fst_exp__h441884 = 8'd254; + default: _theResult___fst_exp__h441884 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h441884 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h441885 = 23'd0; 3'd2: - _theResult___fst_sfd__h441884 = + _theResult___fst_sfd__h441885 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h441884 = + _theResult___fst_sfd__h441885 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h441884 = 23'd8388607; - default: _theResult___fst_sfd__h441884 = 23'd0; + 3'd4: _theResult___fst_sfd__h441885 = 23'd8388607; + default: _theResult___fst_sfd__h441885 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33526,16 +33526,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h718403 = commitStage_commitTrap[35:32]; - default: i__h718403 = 4'd15; + i__h718404 = commitStage_commitTrap[35:32]; + default: i__h718404 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h718563 = commitStage_commitTrap[35:32]; - default: i__h718563 = 4'd15; + i__h718564 = commitStage_commitTrap[35:32]; + default: i__h718564 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -33763,446 +33763,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h359226 or - _theResult___fst_exp__h367274 or - out_exp__h367719 or _theResult___exp__h367716) + always@(guard__h359227 or + _theResult___fst_exp__h367275 or + out_exp__h367720 or _theResult___exp__h367717) begin - case (guard__h359226) + case (guard__h359227) 2'b0, 2'b01: - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q33 = - _theResult___fst_exp__h367274; + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q33 = + _theResult___fst_exp__h367275; 2'b10: - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q33 = - out_exp__h367719; + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q33 = + out_exp__h367720; 2'b11: - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q33 = - _theResult___exp__h367716; + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q33 = + _theResult___exp__h367717; endcase end - always@(guard__h359226 or - _theResult___fst_exp__h367274 or _theResult___exp__h367716) + always@(guard__h359227 or + _theResult___fst_exp__h367275 or _theResult___exp__h367717) begin - case (guard__h359226) + case (guard__h359227) 2'b0: - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q34 = - _theResult___fst_exp__h367274; + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q34 = + _theResult___fst_exp__h367275; 2'b01, 2'b10, 2'b11: - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q34 = - _theResult___exp__h367716; + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q34 = + _theResult___exp__h367717; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q33 or - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q34 or + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q33 or + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q34 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4632 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4634 or - _theResult___fst_exp__h367274) + _theResult___fst_exp__h367275) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h367794 = - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q33; + _theResult___fst_exp__h367795 = + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q33; 3'd1: - _theResult___fst_exp__h367794 = - CASE_guard59226_0b0_theResult___fst_exp67274_0_ETC__q34; + _theResult___fst_exp__h367795 = + CASE_guard59227_0b0_theResult___fst_exp67275_0_ETC__q34; 3'd2: - _theResult___fst_exp__h367794 = + _theResult___fst_exp__h367795 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4632; 3'd3: - _theResult___fst_exp__h367794 = + _theResult___fst_exp__h367795 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4634; - 3'd4: _theResult___fst_exp__h367794 = _theResult___fst_exp__h367274; - default: _theResult___fst_exp__h367794 = 8'd0; + 3'd4: _theResult___fst_exp__h367795 = _theResult___fst_exp__h367275; + default: _theResult___fst_exp__h367795 = 8'd0; endcase end - always@(guard__h350517 or - _theResult___fst_exp__h358618 or - out_exp__h359137 or _theResult___exp__h359134) + always@(guard__h350518 or + _theResult___fst_exp__h358619 or + out_exp__h359138 or _theResult___exp__h359135) begin - case (guard__h350517) + case (guard__h350518) 2'b0, 2'b01: - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q35 = - _theResult___fst_exp__h358618; + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q35 = + _theResult___fst_exp__h358619; 2'b10: - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q35 = - out_exp__h359137; + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q35 = + out_exp__h359138; 2'b11: - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q35 = - _theResult___exp__h359134; + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q35 = + _theResult___exp__h359135; endcase end - always@(guard__h350517 or - _theResult___fst_exp__h358618 or _theResult___exp__h359134) + always@(guard__h350518 or + _theResult___fst_exp__h358619 or _theResult___exp__h359135) begin - case (guard__h350517) + case (guard__h350518) 2'b0: - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q36 = - _theResult___fst_exp__h358618; + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q36 = + _theResult___fst_exp__h358619; 2'b01, 2'b10, 2'b11: - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q36 = - _theResult___exp__h359134; + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q36 = + _theResult___exp__h359135; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q35 or - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q36 or + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q35 or + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q36 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4413 or - _theResult___fst_exp__h358618) + _theResult___fst_exp__h358619) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h359212 = - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q35; + _theResult___fst_exp__h359213 = + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q35; 3'd1: - _theResult___fst_exp__h359212 = - CASE_guard50517_0b0_theResult___fst_exp58618_0_ETC__q36; + _theResult___fst_exp__h359213 = + CASE_guard50518_0b0_theResult___fst_exp58619_0_ETC__q36; 3'd2: - _theResult___fst_exp__h359212 = + _theResult___fst_exp__h359213 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4410; 3'd3: - _theResult___fst_exp__h359212 = + _theResult___fst_exp__h359213 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4413; - 3'd4: _theResult___fst_exp__h359212 = _theResult___fst_exp__h358618; - default: _theResult___fst_exp__h359212 = 8'd0; + 3'd4: _theResult___fst_exp__h359213 = _theResult___fst_exp__h358619; + default: _theResult___fst_exp__h359213 = 8'd0; endcase end - always@(guard__h368156 or - _theResult___fst_exp__h376384 or - out_exp__h376903 or _theResult___exp__h376900) + always@(guard__h368157 or + _theResult___fst_exp__h376385 or + out_exp__h376904 or _theResult___exp__h376901) begin - case (guard__h368156) + case (guard__h368157) 2'b0, 2'b01: - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q41 = - _theResult___fst_exp__h376384; + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q41 = + _theResult___fst_exp__h376385; 2'b10: - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q41 = - out_exp__h376903; + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q41 = + out_exp__h376904; 2'b11: - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q41 = - _theResult___exp__h376900; + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q41 = + _theResult___exp__h376901; endcase end - always@(guard__h368156 or - _theResult___fst_exp__h376384 or _theResult___exp__h376900) + always@(guard__h368157 or + _theResult___fst_exp__h376385 or _theResult___exp__h376901) begin - case (guard__h368156) + case (guard__h368157) 2'b0: - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q42 = - _theResult___fst_exp__h376384; + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q42 = + _theResult___fst_exp__h376385; 2'b01, 2'b10, 2'b11: - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q42 = - _theResult___exp__h376900; + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q42 = + _theResult___exp__h376901; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q41 or - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q42 or + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q41 or + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q42 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4957 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4959 or - _theResult___fst_exp__h376384) + _theResult___fst_exp__h376385) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h376978 = - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q41; + _theResult___fst_exp__h376979 = + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q41; 3'd1: - _theResult___fst_exp__h376978 = - CASE_guard68156_0b0_theResult___fst_exp76384_0_ETC__q42; + _theResult___fst_exp__h376979 = + CASE_guard68157_0b0_theResult___fst_exp76385_0_ETC__q42; 3'd2: - _theResult___fst_exp__h376978 = + _theResult___fst_exp__h376979 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4957; 3'd3: - _theResult___fst_exp__h376978 = + _theResult___fst_exp__h376979 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4959; - 3'd4: _theResult___fst_exp__h376978 = _theResult___fst_exp__h376384; - default: _theResult___fst_exp__h376978 = 8'd0; + 3'd4: _theResult___fst_exp__h376979 = _theResult___fst_exp__h376385; + default: _theResult___fst_exp__h376979 = 8'd0; endcase end - always@(guard__h376992 or - _theResult___fst_exp__h385069 or - out_exp__h385539 or _theResult___exp__h385536) + always@(guard__h376993 or + _theResult___fst_exp__h385070 or + out_exp__h385540 or _theResult___exp__h385537) begin - case (guard__h376992) + case (guard__h376993) 2'b0, 2'b01: - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q46 = - _theResult___fst_exp__h385069; + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q46 = + _theResult___fst_exp__h385070; 2'b10: - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q46 = - out_exp__h385539; + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q46 = + out_exp__h385540; 2'b11: - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q46 = - _theResult___exp__h385536; + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q46 = + _theResult___exp__h385537; endcase end - always@(guard__h376992 or - _theResult___fst_exp__h385069 or _theResult___exp__h385536) + always@(guard__h376993 or + _theResult___fst_exp__h385070 or _theResult___exp__h385537) begin - case (guard__h376992) + case (guard__h376993) 2'b0: - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q47 = - _theResult___fst_exp__h385069; + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q47 = + _theResult___fst_exp__h385070; 2'b01, 2'b10, 2'b11: - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q47 = - _theResult___exp__h385536; + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q47 = + _theResult___exp__h385537; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q46 or - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q47 or + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q46 or + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q47 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5026 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5028 or - _theResult___fst_exp__h385069) + _theResult___fst_exp__h385070) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h385614 = - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q46; + _theResult___fst_exp__h385615 = + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q46; 3'd1: - _theResult___fst_exp__h385614 = - CASE_guard76992_0b0_theResult___fst_exp85069_0_ETC__q47; + _theResult___fst_exp__h385615 = + CASE_guard76993_0b0_theResult___fst_exp85070_0_ETC__q47; 3'd2: - _theResult___fst_exp__h385614 = + _theResult___fst_exp__h385615 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5026; 3'd3: - _theResult___fst_exp__h385614 = + _theResult___fst_exp__h385615 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5028; - 3'd4: _theResult___fst_exp__h385614 = _theResult___fst_exp__h385069; - default: _theResult___fst_exp__h385614 = 8'd0; + 3'd4: _theResult___fst_exp__h385615 = _theResult___fst_exp__h385070; + default: _theResult___fst_exp__h385615 = 8'd0; endcase end - always@(guard__h359226 or - _theResult___snd__h367225 or - out_sfd__h367720 or _theResult___sfd__h367717) + always@(guard__h359227 or + _theResult___snd__h367226 or + out_sfd__h367721 or _theResult___sfd__h367718) begin - case (guard__h359226) + case (guard__h359227) 2'b0, 2'b01: - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q48 = - _theResult___snd__h367225[56:34]; + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48 = + _theResult___snd__h367226[56:34]; 2'b10: - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q48 = - out_sfd__h367720; + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48 = + out_sfd__h367721; 2'b11: - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q48 = - _theResult___sfd__h367717; + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48 = + _theResult___sfd__h367718; endcase end - always@(guard__h359226 or - _theResult___snd__h367225 or _theResult___sfd__h367717) + always@(guard__h359227 or + _theResult___snd__h367226 or _theResult___sfd__h367718) begin - case (guard__h359226) + case (guard__h359227) 2'b0: - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q49 = - _theResult___snd__h367225[56:34]; + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q49 = + _theResult___snd__h367226[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q49 = - _theResult___sfd__h367717; + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q49 = + _theResult___sfd__h367718; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q48 or - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q49 or + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48 or + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q49 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5076 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5078 or - _theResult___snd__h367225) + _theResult___snd__h367226) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h367795 = - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q48; + _theResult___fst_sfd__h367796 = + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q48; 3'd1: - _theResult___fst_sfd__h367795 = - CASE_guard59226_0b0_theResult___snd67225_BITS__ETC__q49; + _theResult___fst_sfd__h367796 = + CASE_guard59227_0b0_theResult___snd67226_BITS__ETC__q49; 3'd2: - _theResult___fst_sfd__h367795 = + _theResult___fst_sfd__h367796 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5076; 3'd3: - _theResult___fst_sfd__h367795 = + _theResult___fst_sfd__h367796 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5078; - 3'd4: _theResult___fst_sfd__h367795 = _theResult___snd__h367225[56:34]; - default: _theResult___fst_sfd__h367795 = 23'd0; + 3'd4: _theResult___fst_sfd__h367796 = _theResult___snd__h367226[56:34]; + default: _theResult___fst_sfd__h367796 = 23'd0; endcase end - always@(guard__h350517 or - sfdin__h358612 or out_sfd__h359138 or _theResult___sfd__h359135) + always@(guard__h350518 or + sfdin__h358613 or out_sfd__h359139 or _theResult___sfd__h359136) begin - case (guard__h350517) + case (guard__h350518) 2'b0, 2'b01: - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q50 = - sfdin__h358612[56:34]; + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50 = + sfdin__h358613[56:34]; 2'b10: - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q50 = - out_sfd__h359138; + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50 = + out_sfd__h359139; 2'b11: - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h359135; + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h359136; endcase end - always@(guard__h350517 or sfdin__h358612 or _theResult___sfd__h359135) + always@(guard__h350518 or sfdin__h358613 or _theResult___sfd__h359136) begin - case (guard__h350517) + case (guard__h350518) 2'b0: - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q51 = - sfdin__h358612[56:34]; + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q51 = + sfdin__h358613[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h359135; + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h359136; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q50 or - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q51 or + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50 or + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q51 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059 or - sfdin__h358612) + sfdin__h358613) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h359213 = - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h359214 = + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q50; 3'd1: - _theResult___fst_sfd__h359213 = - CASE_guard50517_0b0_sfdin58612_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h359214 = + CASE_guard50518_0b0_sfdin58613_BITS_56_TO_34_0_ETC__q51; 3'd2: - _theResult___fst_sfd__h359213 = + _theResult___fst_sfd__h359214 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5057; 3'd3: - _theResult___fst_sfd__h359213 = + _theResult___fst_sfd__h359214 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5059; - 3'd4: _theResult___fst_sfd__h359213 = sfdin__h358612[56:34]; - default: _theResult___fst_sfd__h359213 = 23'd0; + 3'd4: _theResult___fst_sfd__h359214 = sfdin__h358613[56:34]; + default: _theResult___fst_sfd__h359214 = 23'd0; endcase end - always@(guard__h368156 or - sfdin__h376378 or out_sfd__h376904 or _theResult___sfd__h376901) + always@(guard__h368157 or + sfdin__h376379 or out_sfd__h376905 or _theResult___sfd__h376902) begin - case (guard__h368156) + case (guard__h368157) 2'b0, 2'b01: - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q52 = - sfdin__h376378[56:34]; + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q52 = + sfdin__h376379[56:34]; 2'b10: - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q52 = - out_sfd__h376904; + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q52 = + out_sfd__h376905; 2'b11: - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h376901; + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h376902; endcase end - always@(guard__h368156 or sfdin__h376378 or _theResult___sfd__h376901) + always@(guard__h368157 or sfdin__h376379 or _theResult___sfd__h376902) begin - case (guard__h368156) + case (guard__h368157) 2'b0: - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q53 = - sfdin__h376378[56:34]; + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q53 = + sfdin__h376379[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q53 = - _theResult___sfd__h376901; + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q53 = + _theResult___sfd__h376902; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q52 or - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q53 or + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q52 or + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q53 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5103 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5105 or - sfdin__h376378) + sfdin__h376379) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h376979 = - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h376980 = + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q52; 3'd1: - _theResult___fst_sfd__h376979 = - CASE_guard68156_0b0_sfdin76378_BITS_56_TO_34_0_ETC__q53; + _theResult___fst_sfd__h376980 = + CASE_guard68157_0b0_sfdin76379_BITS_56_TO_34_0_ETC__q53; 3'd2: - _theResult___fst_sfd__h376979 = + _theResult___fst_sfd__h376980 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5103; 3'd3: - _theResult___fst_sfd__h376979 = + _theResult___fst_sfd__h376980 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5105; - 3'd4: _theResult___fst_sfd__h376979 = sfdin__h376378[56:34]; - default: _theResult___fst_sfd__h376979 = 23'd0; + 3'd4: _theResult___fst_sfd__h376980 = sfdin__h376379[56:34]; + default: _theResult___fst_sfd__h376980 = 23'd0; endcase end - always@(guard__h376992 or - _theResult___snd__h385015 or - out_sfd__h385540 or _theResult___sfd__h385537) + always@(guard__h376993 or + _theResult___snd__h385016 or + out_sfd__h385541 or _theResult___sfd__h385538) begin - case (guard__h376992) + case (guard__h376993) 2'b0, 2'b01: - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q54 = - _theResult___snd__h385015[56:34]; + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q54 = + _theResult___snd__h385016[56:34]; 2'b10: - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q54 = - out_sfd__h385540; + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q54 = + out_sfd__h385541; 2'b11: - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q54 = - _theResult___sfd__h385537; + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q54 = + _theResult___sfd__h385538; endcase end - always@(guard__h376992 or - _theResult___snd__h385015 or _theResult___sfd__h385537) + always@(guard__h376993 or + _theResult___snd__h385016 or _theResult___sfd__h385538) begin - case (guard__h376992) + case (guard__h376993) 2'b0: - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q55 = - _theResult___snd__h385015[56:34]; + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q55 = + _theResult___snd__h385016[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q55 = - _theResult___sfd__h385537; + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q55 = + _theResult___sfd__h385538; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q54 or - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q55 or + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q54 or + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q55 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124 or - _theResult___snd__h385015) + _theResult___snd__h385016) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h385615 = - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q54; + _theResult___fst_sfd__h385616 = + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q54; 3'd1: - _theResult___fst_sfd__h385615 = - CASE_guard76992_0b0_theResult___snd85015_BITS__ETC__q55; + _theResult___fst_sfd__h385616 = + CASE_guard76993_0b0_theResult___snd85016_BITS__ETC__q55; 3'd2: - _theResult___fst_sfd__h385615 = + _theResult___fst_sfd__h385616 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5122; 3'd3: - _theResult___fst_sfd__h385615 = + _theResult___fst_sfd__h385616 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5124; - 3'd4: _theResult___fst_sfd__h385615 = _theResult___snd__h385015[56:34]; - default: _theResult___fst_sfd__h385615 = 23'd0; + 3'd4: _theResult___fst_sfd__h385616 = _theResult___snd__h385016[56:34]; + default: _theResult___fst_sfd__h385616 = 23'd0; endcase end - always@(guard__h350517 or + always@(guard__h350518 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350517) + case (guard__h350518) 2'b0, 2'b01, 2'b10: - CASE_guard50517_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = + CASE_guard50518_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50517_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = - guard__h350517 == 2'b11 && + CASE_guard50518_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 = + guard__h350518 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50517_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or - guard__h350517) + CASE_guard50518_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56 or + guard__h350518) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = - CASE_guard50517_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; + CASE_guard50518_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = - (guard__h350517 == 2'b0) ? + (guard__h350518 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h350517 == 2'b01 || guard__h350517 == 2'b10 || - guard__h350517 == 2'b11) && + (guard__h350518 == 2'b01 || guard__h350518 == 2'b10 || + guard__h350518 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5210 = @@ -34213,34 +34213,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h350517 or + always@(guard__h350518 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h350517) + case (guard__h350518) 2'b0, 2'b01, 2'b10: - CASE_guard50517_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + CASE_guard50518_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard50517_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = - guard__h350517 != 2'b11 || + CASE_guard50518_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 = + guard__h350518 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard50517_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or - guard__h350517) + CASE_guard50518_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57 or + guard__h350518) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - CASE_guard50517_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; + CASE_guard50518_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = - (guard__h350517 == 2'b0) ? + (guard__h350518 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h350517 != 2'b01 && guard__h350517 != 2'b10 && - guard__h350517 != 2'b11 || + guard__h350518 != 2'b01 && guard__h350518 != 2'b10 && + guard__h350518 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5154 = @@ -34251,34 +34251,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359226 or + always@(guard__h359227 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359226) + case (guard__h359227) 2'b0, 2'b01, 2'b10: - CASE_guard59226_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = + CASE_guard59227_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59226_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = - guard__h359226 == 2'b11 && + CASE_guard59227_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 = + guard__h359227 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59226_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 or - guard__h359226) + CASE_guard59227_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58 or + guard__h359227) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 = - CASE_guard59226_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58; + CASE_guard59227_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 = - (guard__h359226 == 2'b0) ? + (guard__h359227 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h359226 == 2'b01 || guard__h359226 == 2'b10 || - guard__h359226 == 2'b11) && + (guard__h359227 == 2'b01 || guard__h359227 == 2'b10 || + guard__h359227 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5217 = @@ -34289,34 +34289,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h359226 or + always@(guard__h359227 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h359226) + case (guard__h359227) 2'b0, 2'b01, 2'b10: - CASE_guard59226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = + CASE_guard59227_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard59226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = - guard__h359226 != 2'b11 || + CASE_guard59227_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 = + guard__h359227 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard59226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 or - guard__h359226) + CASE_guard59227_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59 or + guard__h359227) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 = - CASE_guard59226_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59; + CASE_guard59227_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 = - (guard__h359226 == 2'b0) ? + (guard__h359227 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h359226 != 2'b01 && guard__h359226 != 2'b10 && - guard__h359226 != 2'b11 || + guard__h359227 != 2'b01 && guard__h359227 != 2'b10 && + guard__h359227 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 = @@ -34327,34 +34327,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368156 or + always@(guard__h368157 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368156) + case (guard__h368157) 2'b0, 2'b01, 2'b10: - CASE_guard68156_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = + CASE_guard68157_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68156_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = - guard__h368156 == 2'b11 && + CASE_guard68157_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 = + guard__h368157 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68156_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 or - guard__h368156) + CASE_guard68157_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60 or + guard__h368157) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227 = - CASE_guard68156_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60; + CASE_guard68157_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227 = - (guard__h368156 == 2'b0) ? + (guard__h368157 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h368156 == 2'b01 || guard__h368156 == 2'b10 || - guard__h368156 == 2'b11) && + (guard__h368157 == 2'b01 || guard__h368157 == 2'b10 || + guard__h368157 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5227 = @@ -34365,34 +34365,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h368156 or + always@(guard__h368157 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h368156) + case (guard__h368157) 2'b0, 2'b01, 2'b10: - CASE_guard68156_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = + CASE_guard68157_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard68156_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = - guard__h368156 != 2'b11 || + CASE_guard68157_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 = + guard__h368157 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard68156_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 or - guard__h368156) + CASE_guard68157_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61 or + guard__h368157) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = - CASE_guard68156_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61; + CASE_guard68157_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = - (guard__h368156 == 2'b0) ? + (guard__h368157 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h368156 != 2'b01 && guard__h368156 != 2'b10 && - guard__h368156 != 2'b11 || + guard__h368157 != 2'b01 && guard__h368157 != 2'b10 && + guard__h368157 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5184 = @@ -34403,34 +34403,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376992 or + always@(guard__h376993 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h376992) + case (guard__h376993) 2'b0, 2'b01, 2'b10: - CASE_guard76992_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = + CASE_guard76993_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76992_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = - guard__h376992 == 2'b11 && + CASE_guard76993_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 = + guard__h376993 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76992_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 or - guard__h376992) + CASE_guard76993_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62 or + guard__h376993) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - CASE_guard76992_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62; + CASE_guard76993_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = - (guard__h376992 == 2'b0) ? + (guard__h376993 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h376992 == 2'b01 || guard__h376992 == 2'b10 || - guard__h376992 == 2'b11) && + (guard__h376993 == 2'b01 || guard__h376993 == 2'b10 || + guard__h376993 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5234 = @@ -34441,34 +34441,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h376992 or + always@(guard__h376993 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h376992) + case (guard__h376993) 2'b0, 2'b01, 2'b10: - CASE_guard76992_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = + CASE_guard76993_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard76992_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = - guard__h376992 != 2'b11 || + CASE_guard76993_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 = + guard__h376993 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard76992_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 or - guard__h376992) + CASE_guard76993_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63 or + guard__h376993) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197 = - CASE_guard76992_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63; + CASE_guard76993_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q63; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197 = - (guard__h376992 == 2'b0) ? + (guard__h376993 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h376992 != 2'b01 && guard__h376992 != 2'b10 && - guard__h376992 != 2'b11 || + guard__h376993 != 2'b01 && guard__h376993 != 2'b10 && + guard__h376993 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5197 = @@ -34505,446 +34505,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h404923 or - _theResult___fst_exp__h412971 or - out_exp__h413416 or _theResult___exp__h413413) + always@(guard__h404924 or + _theResult___fst_exp__h412972 or + out_exp__h413417 or _theResult___exp__h413414) begin - case (guard__h404923) + case (guard__h404924) 2'b0, 2'b01: - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q68 = - _theResult___fst_exp__h412971; + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q68 = + _theResult___fst_exp__h412972; 2'b10: - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q68 = - out_exp__h413416; + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q68 = + out_exp__h413417; 2'b11: - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q68 = - _theResult___exp__h413413; + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q68 = + _theResult___exp__h413414; endcase end - always@(guard__h404923 or - _theResult___fst_exp__h412971 or _theResult___exp__h413413) + always@(guard__h404924 or + _theResult___fst_exp__h412972 or _theResult___exp__h413414) begin - case (guard__h404923) + case (guard__h404924) 2'b0: - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q69 = - _theResult___fst_exp__h412971; + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q69 = + _theResult___fst_exp__h412972; 2'b01, 2'b10, 2'b11: - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q69 = - _theResult___exp__h413413; + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q69 = + _theResult___exp__h413414; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q68 or - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q69 or + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q68 or + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q69 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6024 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6026 or - _theResult___fst_exp__h412971) + _theResult___fst_exp__h412972) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h413491 = - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q68; + _theResult___fst_exp__h413492 = + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q68; 3'd1: - _theResult___fst_exp__h413491 = - CASE_guard04923_0b0_theResult___fst_exp12971_0_ETC__q69; + _theResult___fst_exp__h413492 = + CASE_guard04924_0b0_theResult___fst_exp12972_0_ETC__q69; 3'd2: - _theResult___fst_exp__h413491 = + _theResult___fst_exp__h413492 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6024; 3'd3: - _theResult___fst_exp__h413491 = + _theResult___fst_exp__h413492 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6026; - 3'd4: _theResult___fst_exp__h413491 = _theResult___fst_exp__h412971; - default: _theResult___fst_exp__h413491 = 8'd0; + 3'd4: _theResult___fst_exp__h413492 = _theResult___fst_exp__h412972; + default: _theResult___fst_exp__h413492 = 8'd0; endcase end - always@(guard__h396216 or - _theResult___fst_exp__h404315 or - out_exp__h404834 or _theResult___exp__h404831) + always@(guard__h396217 or + _theResult___fst_exp__h404316 or + out_exp__h404835 or _theResult___exp__h404832) begin - case (guard__h396216) + case (guard__h396217) 2'b0, 2'b01: - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q70 = - _theResult___fst_exp__h404315; + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q70 = + _theResult___fst_exp__h404316; 2'b10: - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q70 = - out_exp__h404834; + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q70 = + out_exp__h404835; 2'b11: - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q70 = - _theResult___exp__h404831; + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q70 = + _theResult___exp__h404832; endcase end - always@(guard__h396216 or - _theResult___fst_exp__h404315 or _theResult___exp__h404831) + always@(guard__h396217 or + _theResult___fst_exp__h404316 or _theResult___exp__h404832) begin - case (guard__h396216) + case (guard__h396217) 2'b0: - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q71 = - _theResult___fst_exp__h404315; + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q71 = + _theResult___fst_exp__h404316; 2'b01, 2'b10, 2'b11: - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q71 = - _theResult___exp__h404831; + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q71 = + _theResult___exp__h404832; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q70 or - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q71 or + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q70 or + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q71 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5805 or - _theResult___fst_exp__h404315) + _theResult___fst_exp__h404316) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h404909 = - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q70; + _theResult___fst_exp__h404910 = + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q70; 3'd1: - _theResult___fst_exp__h404909 = - CASE_guard96216_0b0_theResult___fst_exp04315_0_ETC__q71; + _theResult___fst_exp__h404910 = + CASE_guard96217_0b0_theResult___fst_exp04316_0_ETC__q71; 3'd2: - _theResult___fst_exp__h404909 = + _theResult___fst_exp__h404910 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5802; 3'd3: - _theResult___fst_exp__h404909 = + _theResult___fst_exp__h404910 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5805; - 3'd4: _theResult___fst_exp__h404909 = _theResult___fst_exp__h404315; - default: _theResult___fst_exp__h404909 = 8'd0; + 3'd4: _theResult___fst_exp__h404910 = _theResult___fst_exp__h404316; + default: _theResult___fst_exp__h404910 = 8'd0; endcase end - always@(guard__h413853 or - _theResult___fst_exp__h422081 or - out_exp__h422600 or _theResult___exp__h422597) + always@(guard__h413854 or + _theResult___fst_exp__h422082 or + out_exp__h422601 or _theResult___exp__h422598) begin - case (guard__h413853) + case (guard__h413854) 2'b0, 2'b01: - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q76 = - _theResult___fst_exp__h422081; + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q76 = + _theResult___fst_exp__h422082; 2'b10: - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q76 = - out_exp__h422600; + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q76 = + out_exp__h422601; 2'b11: - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q76 = - _theResult___exp__h422597; + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q76 = + _theResult___exp__h422598; endcase end - always@(guard__h413853 or - _theResult___fst_exp__h422081 or _theResult___exp__h422597) + always@(guard__h413854 or + _theResult___fst_exp__h422082 or _theResult___exp__h422598) begin - case (guard__h413853) + case (guard__h413854) 2'b0: - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q77 = - _theResult___fst_exp__h422081; + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q77 = + _theResult___fst_exp__h422082; 2'b01, 2'b10, 2'b11: - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q77 = - _theResult___exp__h422597; + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q77 = + _theResult___exp__h422598; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q76 or - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q77 or + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q76 or + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q77 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6349 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6351 or - _theResult___fst_exp__h422081) + _theResult___fst_exp__h422082) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h422675 = - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q76; + _theResult___fst_exp__h422676 = + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q76; 3'd1: - _theResult___fst_exp__h422675 = - CASE_guard13853_0b0_theResult___fst_exp22081_0_ETC__q77; + _theResult___fst_exp__h422676 = + CASE_guard13854_0b0_theResult___fst_exp22082_0_ETC__q77; 3'd2: - _theResult___fst_exp__h422675 = + _theResult___fst_exp__h422676 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6349; 3'd3: - _theResult___fst_exp__h422675 = + _theResult___fst_exp__h422676 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6351; - 3'd4: _theResult___fst_exp__h422675 = _theResult___fst_exp__h422081; - default: _theResult___fst_exp__h422675 = 8'd0; + 3'd4: _theResult___fst_exp__h422676 = _theResult___fst_exp__h422082; + default: _theResult___fst_exp__h422676 = 8'd0; endcase end - always@(guard__h422689 or - _theResult___fst_exp__h430766 or - out_exp__h431236 or _theResult___exp__h431233) + always@(guard__h422690 or + _theResult___fst_exp__h430767 or + out_exp__h431237 or _theResult___exp__h431234) begin - case (guard__h422689) + case (guard__h422690) 2'b0, 2'b01: - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q81 = - _theResult___fst_exp__h430766; + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q81 = + _theResult___fst_exp__h430767; 2'b10: - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q81 = - out_exp__h431236; + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q81 = + out_exp__h431237; 2'b11: - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q81 = - _theResult___exp__h431233; + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q81 = + _theResult___exp__h431234; endcase end - always@(guard__h422689 or - _theResult___fst_exp__h430766 or _theResult___exp__h431233) + always@(guard__h422690 or + _theResult___fst_exp__h430767 or _theResult___exp__h431234) begin - case (guard__h422689) + case (guard__h422690) 2'b0: - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q82 = - _theResult___fst_exp__h430766; + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q82 = + _theResult___fst_exp__h430767; 2'b01, 2'b10, 2'b11: - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q82 = - _theResult___exp__h431233; + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q82 = + _theResult___exp__h431234; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q81 or - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q82 or + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q81 or + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q82 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6418 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6420 or - _theResult___fst_exp__h430766) + _theResult___fst_exp__h430767) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h431311 = - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q81; + _theResult___fst_exp__h431312 = + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q81; 3'd1: - _theResult___fst_exp__h431311 = - CASE_guard22689_0b0_theResult___fst_exp30766_0_ETC__q82; + _theResult___fst_exp__h431312 = + CASE_guard22690_0b0_theResult___fst_exp30767_0_ETC__q82; 3'd2: - _theResult___fst_exp__h431311 = + _theResult___fst_exp__h431312 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6418; 3'd3: - _theResult___fst_exp__h431311 = + _theResult___fst_exp__h431312 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6420; - 3'd4: _theResult___fst_exp__h431311 = _theResult___fst_exp__h430766; - default: _theResult___fst_exp__h431311 = 8'd0; + 3'd4: _theResult___fst_exp__h431312 = _theResult___fst_exp__h430767; + default: _theResult___fst_exp__h431312 = 8'd0; endcase end - always@(guard__h404923 or - _theResult___snd__h412922 or - out_sfd__h413417 or _theResult___sfd__h413414) + always@(guard__h404924 or + _theResult___snd__h412923 or + out_sfd__h413418 or _theResult___sfd__h413415) begin - case (guard__h404923) + case (guard__h404924) 2'b0, 2'b01: - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q83 = - _theResult___snd__h412922[56:34]; + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q83 = + _theResult___snd__h412923[56:34]; 2'b10: - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q83 = - out_sfd__h413417; + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q83 = + out_sfd__h413418; 2'b11: - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q83 = - _theResult___sfd__h413414; + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q83 = + _theResult___sfd__h413415; endcase end - always@(guard__h404923 or - _theResult___snd__h412922 or _theResult___sfd__h413414) + always@(guard__h404924 or + _theResult___snd__h412923 or _theResult___sfd__h413415) begin - case (guard__h404923) + case (guard__h404924) 2'b0: - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q84 = - _theResult___snd__h412922[56:34]; + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q84 = + _theResult___snd__h412923[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q84 = - _theResult___sfd__h413414; + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q84 = + _theResult___sfd__h413415; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q83 or - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q84 or + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q83 or + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q84 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6468 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6470 or - _theResult___snd__h412922) + _theResult___snd__h412923) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h413492 = - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q83; + _theResult___fst_sfd__h413493 = + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q83; 3'd1: - _theResult___fst_sfd__h413492 = - CASE_guard04923_0b0_theResult___snd12922_BITS__ETC__q84; + _theResult___fst_sfd__h413493 = + CASE_guard04924_0b0_theResult___snd12923_BITS__ETC__q84; 3'd2: - _theResult___fst_sfd__h413492 = + _theResult___fst_sfd__h413493 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6468; 3'd3: - _theResult___fst_sfd__h413492 = + _theResult___fst_sfd__h413493 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6470; - 3'd4: _theResult___fst_sfd__h413492 = _theResult___snd__h412922[56:34]; - default: _theResult___fst_sfd__h413492 = 23'd0; + 3'd4: _theResult___fst_sfd__h413493 = _theResult___snd__h412923[56:34]; + default: _theResult___fst_sfd__h413493 = 23'd0; endcase end - always@(guard__h396216 or - sfdin__h404309 or out_sfd__h404835 or _theResult___sfd__h404832) + always@(guard__h396217 or + sfdin__h404310 or out_sfd__h404836 or _theResult___sfd__h404833) begin - case (guard__h396216) + case (guard__h396217) 2'b0, 2'b01: - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q85 = - sfdin__h404309[56:34]; + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q85 = + sfdin__h404310[56:34]; 2'b10: - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q85 = - out_sfd__h404835; + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q85 = + out_sfd__h404836; 2'b11: - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q85 = - _theResult___sfd__h404832; + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h404833; endcase end - always@(guard__h396216 or sfdin__h404309 or _theResult___sfd__h404832) + always@(guard__h396217 or sfdin__h404310 or _theResult___sfd__h404833) begin - case (guard__h396216) + case (guard__h396217) 2'b0: - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q86 = - sfdin__h404309[56:34]; + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q86 = + sfdin__h404310[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h404832; + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h404833; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q85 or - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q86 or + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q85 or + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q86 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6451 or - sfdin__h404309) + sfdin__h404310) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h404910 = - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q85; + _theResult___fst_sfd__h404911 = + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q85; 3'd1: - _theResult___fst_sfd__h404910 = - CASE_guard96216_0b0_sfdin04309_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h404911 = + CASE_guard96217_0b0_sfdin04310_BITS_56_TO_34_0_ETC__q86; 3'd2: - _theResult___fst_sfd__h404910 = + _theResult___fst_sfd__h404911 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6449; 3'd3: - _theResult___fst_sfd__h404910 = + _theResult___fst_sfd__h404911 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6451; - 3'd4: _theResult___fst_sfd__h404910 = sfdin__h404309[56:34]; - default: _theResult___fst_sfd__h404910 = 23'd0; + 3'd4: _theResult___fst_sfd__h404911 = sfdin__h404310[56:34]; + default: _theResult___fst_sfd__h404911 = 23'd0; endcase end - always@(guard__h413853 or - sfdin__h422075 or out_sfd__h422601 or _theResult___sfd__h422598) + always@(guard__h413854 or + sfdin__h422076 or out_sfd__h422602 or _theResult___sfd__h422599) begin - case (guard__h413853) + case (guard__h413854) 2'b0, 2'b01: - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q87 = - sfdin__h422075[56:34]; + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q87 = + sfdin__h422076[56:34]; 2'b10: - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q87 = - out_sfd__h422601; + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q87 = + out_sfd__h422602; 2'b11: - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h422598; + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h422599; endcase end - always@(guard__h413853 or sfdin__h422075 or _theResult___sfd__h422598) + always@(guard__h413854 or sfdin__h422076 or _theResult___sfd__h422599) begin - case (guard__h413853) + case (guard__h413854) 2'b0: - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q88 = - sfdin__h422075[56:34]; + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q88 = + sfdin__h422076[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q88 = - _theResult___sfd__h422598; + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q88 = + _theResult___sfd__h422599; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q87 or - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q88 or + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q87 or + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q88 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6495 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6497 or - sfdin__h422075) + sfdin__h422076) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h422676 = - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h422677 = + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q87; 3'd1: - _theResult___fst_sfd__h422676 = - CASE_guard13853_0b0_sfdin22075_BITS_56_TO_34_0_ETC__q88; + _theResult___fst_sfd__h422677 = + CASE_guard13854_0b0_sfdin22076_BITS_56_TO_34_0_ETC__q88; 3'd2: - _theResult___fst_sfd__h422676 = + _theResult___fst_sfd__h422677 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6495; 3'd3: - _theResult___fst_sfd__h422676 = + _theResult___fst_sfd__h422677 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6497; - 3'd4: _theResult___fst_sfd__h422676 = sfdin__h422075[56:34]; - default: _theResult___fst_sfd__h422676 = 23'd0; + 3'd4: _theResult___fst_sfd__h422677 = sfdin__h422076[56:34]; + default: _theResult___fst_sfd__h422677 = 23'd0; endcase end - always@(guard__h422689 or - _theResult___snd__h430712 or - out_sfd__h431237 or _theResult___sfd__h431234) + always@(guard__h422690 or + _theResult___snd__h430713 or + out_sfd__h431238 or _theResult___sfd__h431235) begin - case (guard__h422689) + case (guard__h422690) 2'b0, 2'b01: - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q89 = - _theResult___snd__h430712[56:34]; + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89 = + _theResult___snd__h430713[56:34]; 2'b10: - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q89 = - out_sfd__h431237; + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89 = + out_sfd__h431238; 2'b11: - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q89 = - _theResult___sfd__h431234; + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89 = + _theResult___sfd__h431235; endcase end - always@(guard__h422689 or - _theResult___snd__h430712 or _theResult___sfd__h431234) + always@(guard__h422690 or + _theResult___snd__h430713 or _theResult___sfd__h431235) begin - case (guard__h422689) + case (guard__h422690) 2'b0: - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q90 = - _theResult___snd__h430712[56:34]; + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q90 = + _theResult___snd__h430713[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q90 = - _theResult___sfd__h431234; + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q90 = + _theResult___sfd__h431235; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q89 or - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q90 or + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89 or + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q90 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516 or - _theResult___snd__h430712) + _theResult___snd__h430713) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h431312 = - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q89; + _theResult___fst_sfd__h431313 = + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q89; 3'd1: - _theResult___fst_sfd__h431312 = - CASE_guard22689_0b0_theResult___snd30712_BITS__ETC__q90; + _theResult___fst_sfd__h431313 = + CASE_guard22690_0b0_theResult___snd30713_BITS__ETC__q90; 3'd2: - _theResult___fst_sfd__h431312 = + _theResult___fst_sfd__h431313 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6514; 3'd3: - _theResult___fst_sfd__h431312 = + _theResult___fst_sfd__h431313 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6516; - 3'd4: _theResult___fst_sfd__h431312 = _theResult___snd__h430712[56:34]; - default: _theResult___fst_sfd__h431312 = 23'd0; + 3'd4: _theResult___fst_sfd__h431313 = _theResult___snd__h430713[56:34]; + default: _theResult___fst_sfd__h431313 = 23'd0; endcase end - always@(guard__h396216 or + always@(guard__h396217 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396216) + case (guard__h396217) 2'b0, 2'b01, 2'b10: - CASE_guard96216_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = + CASE_guard96217_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96216_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = - guard__h396216 == 2'b11 && + CASE_guard96217_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 = + guard__h396217 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96216_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or - guard__h396216) + CASE_guard96217_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91 or + guard__h396217) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = - CASE_guard96216_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91; + CASE_guard96217_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = - (guard__h396216 == 2'b0) ? + (guard__h396217 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h396216 == 2'b01 || guard__h396216 == 2'b10 || - guard__h396216 == 2'b11) && + (guard__h396217 == 2'b01 || guard__h396217 == 2'b10 || + guard__h396217 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6602 = @@ -34955,34 +34955,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h396216 or + always@(guard__h396217 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h396216) + case (guard__h396217) 2'b0, 2'b01, 2'b10: - CASE_guard96216_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + CASE_guard96217_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard96216_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = - guard__h396216 != 2'b11 || + CASE_guard96217_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 = + guard__h396217 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard96216_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or - guard__h396216) + CASE_guard96217_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92 or + guard__h396217) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - CASE_guard96216_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; + CASE_guard96217_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q92; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = - (guard__h396216 == 2'b0) ? + (guard__h396217 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h396216 != 2'b01 && guard__h396216 != 2'b10 && - guard__h396216 != 2'b11 || + guard__h396217 != 2'b01 && guard__h396217 != 2'b10 && + guard__h396217 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6546 = @@ -34993,34 +34993,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h404923 or + always@(guard__h404924 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h404923) + case (guard__h404924) 2'b0, 2'b01, 2'b10: - CASE_guard04923_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = + CASE_guard04924_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard04923_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = - guard__h404923 == 2'b11 && + CASE_guard04924_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 = + guard__h404924 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard04923_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 or - guard__h404923) + CASE_guard04924_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93 or + guard__h404924) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 = - CASE_guard04923_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93; + CASE_guard04924_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 = - (guard__h404923 == 2'b0) ? + (guard__h404924 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h404923 == 2'b01 || guard__h404923 == 2'b10 || - guard__h404923 == 2'b11) && + (guard__h404924 == 2'b01 || guard__h404924 == 2'b10 || + guard__h404924 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6609 = @@ -35031,34 +35031,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h404923 or + always@(guard__h404924 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h404923) + case (guard__h404924) 2'b0, 2'b01, 2'b10: - CASE_guard04923_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = + CASE_guard04924_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard04923_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = - guard__h404923 != 2'b11 || + CASE_guard04924_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 = + guard__h404924 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard04923_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 or - guard__h404923) + CASE_guard04924_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94 or + guard__h404924) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 = - CASE_guard04923_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94; + CASE_guard04924_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 = - (guard__h404923 == 2'b0) ? + (guard__h404924 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h404923 != 2'b01 && guard__h404923 != 2'b10 && - guard__h404923 != 2'b11 || + guard__h404924 != 2'b01 && guard__h404924 != 2'b10 && + guard__h404924 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 = @@ -35069,34 +35069,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h413853 or + always@(guard__h413854 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h413853) + case (guard__h413854) 2'b0, 2'b01, 2'b10: - CASE_guard13853_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = + CASE_guard13854_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard13853_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = - guard__h413853 == 2'b11 && + CASE_guard13854_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 = + guard__h413854 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard13853_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 or - guard__h413853) + CASE_guard13854_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95 or + guard__h413854) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619 = - CASE_guard13853_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95; + CASE_guard13854_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619 = - (guard__h413853 == 2'b0) ? + (guard__h413854 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h413853 == 2'b01 || guard__h413853 == 2'b10 || - guard__h413853 == 2'b11) && + (guard__h413854 == 2'b01 || guard__h413854 == 2'b10 || + guard__h413854 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6619 = @@ -35107,34 +35107,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h413853 or + always@(guard__h413854 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h413853) + case (guard__h413854) 2'b0, 2'b01, 2'b10: - CASE_guard13853_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = + CASE_guard13854_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard13853_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = - guard__h413853 != 2'b11 || + CASE_guard13854_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 = + guard__h413854 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard13853_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or - guard__h413853) + CASE_guard13854_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96 or + guard__h413854) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576 = - CASE_guard13853_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; + CASE_guard13854_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576 = - (guard__h413853 == 2'b0) ? + (guard__h413854 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h413853 != 2'b01 && guard__h413853 != 2'b10 && - guard__h413853 != 2'b11 || + guard__h413854 != 2'b01 && guard__h413854 != 2'b10 && + guard__h413854 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6576 = @@ -35145,34 +35145,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422689 or + always@(guard__h422690 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422689) + case (guard__h422690) 2'b0, 2'b01, 2'b10: - CASE_guard22689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + CASE_guard22690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = - guard__h422689 == 2'b11 && + CASE_guard22690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 = + guard__h422690 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or - guard__h422689) + CASE_guard22690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97 or + guard__h422690) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626 = - CASE_guard22689_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; + CASE_guard22690_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626 = - (guard__h422689 == 2'b0) ? + (guard__h422690 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h422689 == 2'b01 || guard__h422689 == 2'b10 || - guard__h422689 == 2'b11) && + (guard__h422690 == 2'b01 || guard__h422690 == 2'b10 || + guard__h422690 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6626 = @@ -35183,34 +35183,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h422689 or + always@(guard__h422690 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h422689) + case (guard__h422690) 2'b0, 2'b01, 2'b10: - CASE_guard22689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = + CASE_guard22690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard22689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = - guard__h422689 != 2'b11 || + CASE_guard22690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 = + guard__h422690 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard22689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 or - guard__h422689) + CASE_guard22690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98 or + guard__h422690) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589 = - CASE_guard22689_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98; + CASE_guard22690_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q98; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589 = - (guard__h422689 == 2'b0) ? + (guard__h422690 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h422689 != 2'b01 && guard__h422689 != 2'b10 && - guard__h422689 != 2'b11 || + guard__h422690 != 2'b01 && guard__h422690 != 2'b10 && + guard__h422690 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6589 = @@ -35247,446 +35247,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h450618 or - _theResult___fst_exp__h458666 or - out_exp__h459111 or _theResult___exp__h459108) + always@(guard__h450619 or + _theResult___fst_exp__h458667 or + out_exp__h459112 or _theResult___exp__h459109) begin - case (guard__h450618) + case (guard__h450619) 2'b0, 2'b01: - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q103 = - _theResult___fst_exp__h458666; + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q103 = + _theResult___fst_exp__h458667; 2'b10: - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q103 = - out_exp__h459111; + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q103 = + out_exp__h459112; 2'b11: - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q103 = - _theResult___exp__h459108; + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q103 = + _theResult___exp__h459109; endcase end - always@(guard__h450618 or - _theResult___fst_exp__h458666 or _theResult___exp__h459108) + always@(guard__h450619 or + _theResult___fst_exp__h458667 or _theResult___exp__h459109) begin - case (guard__h450618) + case (guard__h450619) 2'b0: - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q104 = - _theResult___fst_exp__h458666; + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q104 = + _theResult___fst_exp__h458667; 2'b01, 2'b10, 2'b11: - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q104 = - _theResult___exp__h459108; + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q104 = + _theResult___exp__h459109; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q103 or - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q104 or + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q103 or + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q104 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7416 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7418 or - _theResult___fst_exp__h458666) + _theResult___fst_exp__h458667) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h459186 = - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q103; + _theResult___fst_exp__h459187 = + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q103; 3'd1: - _theResult___fst_exp__h459186 = - CASE_guard50618_0b0_theResult___fst_exp58666_0_ETC__q104; + _theResult___fst_exp__h459187 = + CASE_guard50619_0b0_theResult___fst_exp58667_0_ETC__q104; 3'd2: - _theResult___fst_exp__h459186 = + _theResult___fst_exp__h459187 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7416; 3'd3: - _theResult___fst_exp__h459186 = + _theResult___fst_exp__h459187 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7418; - 3'd4: _theResult___fst_exp__h459186 = _theResult___fst_exp__h458666; - default: _theResult___fst_exp__h459186 = 8'd0; + 3'd4: _theResult___fst_exp__h459187 = _theResult___fst_exp__h458667; + default: _theResult___fst_exp__h459187 = 8'd0; endcase end - always@(guard__h441911 or - _theResult___fst_exp__h450010 or - out_exp__h450529 or _theResult___exp__h450526) + always@(guard__h441912 or + _theResult___fst_exp__h450011 or + out_exp__h450530 or _theResult___exp__h450527) begin - case (guard__h441911) + case (guard__h441912) 2'b0, 2'b01: - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q105 = - _theResult___fst_exp__h450010; + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q105 = + _theResult___fst_exp__h450011; 2'b10: - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q105 = - out_exp__h450529; + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q105 = + out_exp__h450530; 2'b11: - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q105 = - _theResult___exp__h450526; + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q105 = + _theResult___exp__h450527; endcase end - always@(guard__h441911 or - _theResult___fst_exp__h450010 or _theResult___exp__h450526) + always@(guard__h441912 or + _theResult___fst_exp__h450011 or _theResult___exp__h450527) begin - case (guard__h441911) + case (guard__h441912) 2'b0: - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q106 = - _theResult___fst_exp__h450010; + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q106 = + _theResult___fst_exp__h450011; 2'b01, 2'b10, 2'b11: - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q106 = - _theResult___exp__h450526; + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q106 = + _theResult___exp__h450527; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q105 or - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q106 or + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q105 or + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q106 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7197 or - _theResult___fst_exp__h450010) + _theResult___fst_exp__h450011) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h450604 = - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q105; + _theResult___fst_exp__h450605 = + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q105; 3'd1: - _theResult___fst_exp__h450604 = - CASE_guard41911_0b0_theResult___fst_exp50010_0_ETC__q106; + _theResult___fst_exp__h450605 = + CASE_guard41912_0b0_theResult___fst_exp50011_0_ETC__q106; 3'd2: - _theResult___fst_exp__h450604 = + _theResult___fst_exp__h450605 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7194; 3'd3: - _theResult___fst_exp__h450604 = + _theResult___fst_exp__h450605 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7197; - 3'd4: _theResult___fst_exp__h450604 = _theResult___fst_exp__h450010; - default: _theResult___fst_exp__h450604 = 8'd0; + 3'd4: _theResult___fst_exp__h450605 = _theResult___fst_exp__h450011; + default: _theResult___fst_exp__h450605 = 8'd0; endcase end - always@(guard__h459548 or - _theResult___fst_exp__h467776 or - out_exp__h468295 or _theResult___exp__h468292) + always@(guard__h459549 or + _theResult___fst_exp__h467777 or + out_exp__h468296 or _theResult___exp__h468293) begin - case (guard__h459548) + case (guard__h459549) 2'b0, 2'b01: - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q111 = - _theResult___fst_exp__h467776; + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q111 = + _theResult___fst_exp__h467777; 2'b10: - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q111 = - out_exp__h468295; + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q111 = + out_exp__h468296; 2'b11: - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q111 = - _theResult___exp__h468292; + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q111 = + _theResult___exp__h468293; endcase end - always@(guard__h459548 or - _theResult___fst_exp__h467776 or _theResult___exp__h468292) + always@(guard__h459549 or + _theResult___fst_exp__h467777 or _theResult___exp__h468293) begin - case (guard__h459548) + case (guard__h459549) 2'b0: - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q112 = - _theResult___fst_exp__h467776; + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q112 = + _theResult___fst_exp__h467777; 2'b01, 2'b10, 2'b11: - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q112 = - _theResult___exp__h468292; + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q112 = + _theResult___exp__h468293; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q111 or - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q112 or + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q111 or + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q112 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7741 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7743 or - _theResult___fst_exp__h467776) + _theResult___fst_exp__h467777) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h468370 = - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q111; + _theResult___fst_exp__h468371 = + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q111; 3'd1: - _theResult___fst_exp__h468370 = - CASE_guard59548_0b0_theResult___fst_exp67776_0_ETC__q112; + _theResult___fst_exp__h468371 = + CASE_guard59549_0b0_theResult___fst_exp67777_0_ETC__q112; 3'd2: - _theResult___fst_exp__h468370 = + _theResult___fst_exp__h468371 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7741; 3'd3: - _theResult___fst_exp__h468370 = + _theResult___fst_exp__h468371 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7743; - 3'd4: _theResult___fst_exp__h468370 = _theResult___fst_exp__h467776; - default: _theResult___fst_exp__h468370 = 8'd0; + 3'd4: _theResult___fst_exp__h468371 = _theResult___fst_exp__h467777; + default: _theResult___fst_exp__h468371 = 8'd0; endcase end - always@(guard__h468384 or - _theResult___fst_exp__h476461 or - out_exp__h476931 or _theResult___exp__h476928) + always@(guard__h468385 or + _theResult___fst_exp__h476462 or + out_exp__h476932 or _theResult___exp__h476929) begin - case (guard__h468384) + case (guard__h468385) 2'b0, 2'b01: - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q116 = - _theResult___fst_exp__h476461; + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q116 = + _theResult___fst_exp__h476462; 2'b10: - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q116 = - out_exp__h476931; + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q116 = + out_exp__h476932; 2'b11: - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q116 = - _theResult___exp__h476928; + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q116 = + _theResult___exp__h476929; endcase end - always@(guard__h468384 or - _theResult___fst_exp__h476461 or _theResult___exp__h476928) + always@(guard__h468385 or + _theResult___fst_exp__h476462 or _theResult___exp__h476929) begin - case (guard__h468384) + case (guard__h468385) 2'b0: - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q117 = - _theResult___fst_exp__h476461; + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q117 = + _theResult___fst_exp__h476462; 2'b01, 2'b10, 2'b11: - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q117 = - _theResult___exp__h476928; + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q117 = + _theResult___exp__h476929; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q116 or - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q117 or + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q116 or + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q117 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7810 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7812 or - _theResult___fst_exp__h476461) + _theResult___fst_exp__h476462) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h477006 = - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q116; + _theResult___fst_exp__h477007 = + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q116; 3'd1: - _theResult___fst_exp__h477006 = - CASE_guard68384_0b0_theResult___fst_exp76461_0_ETC__q117; + _theResult___fst_exp__h477007 = + CASE_guard68385_0b0_theResult___fst_exp76462_0_ETC__q117; 3'd2: - _theResult___fst_exp__h477006 = + _theResult___fst_exp__h477007 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7810; 3'd3: - _theResult___fst_exp__h477006 = + _theResult___fst_exp__h477007 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7812; - 3'd4: _theResult___fst_exp__h477006 = _theResult___fst_exp__h476461; - default: _theResult___fst_exp__h477006 = 8'd0; + 3'd4: _theResult___fst_exp__h477007 = _theResult___fst_exp__h476462; + default: _theResult___fst_exp__h477007 = 8'd0; endcase end - always@(guard__h450618 or - _theResult___snd__h458617 or - out_sfd__h459112 or _theResult___sfd__h459109) + always@(guard__h450619 or + _theResult___snd__h458618 or + out_sfd__h459113 or _theResult___sfd__h459110) begin - case (guard__h450618) + case (guard__h450619) 2'b0, 2'b01: - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q118 = - _theResult___snd__h458617[56:34]; + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = + _theResult___snd__h458618[56:34]; 2'b10: - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q118 = - out_sfd__h459112; + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = + out_sfd__h459113; 2'b11: - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q118 = - _theResult___sfd__h459109; + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 = + _theResult___sfd__h459110; endcase end - always@(guard__h450618 or - _theResult___snd__h458617 or _theResult___sfd__h459109) + always@(guard__h450619 or + _theResult___snd__h458618 or _theResult___sfd__h459110) begin - case (guard__h450618) + case (guard__h450619) 2'b0: - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q119 = - _theResult___snd__h458617[56:34]; + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 = + _theResult___snd__h458618[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q119 = - _theResult___sfd__h459109; + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 = + _theResult___sfd__h459110; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q118 or - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q119 or + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118 or + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862 or - _theResult___snd__h458617) + _theResult___snd__h458618) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h459187 = - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q118; + _theResult___fst_sfd__h459188 = + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q118; 3'd1: - _theResult___fst_sfd__h459187 = - CASE_guard50618_0b0_theResult___snd58617_BITS__ETC__q119; + _theResult___fst_sfd__h459188 = + CASE_guard50619_0b0_theResult___snd58618_BITS__ETC__q119; 3'd2: - _theResult___fst_sfd__h459187 = + _theResult___fst_sfd__h459188 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7860; 3'd3: - _theResult___fst_sfd__h459187 = + _theResult___fst_sfd__h459188 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7862; - 3'd4: _theResult___fst_sfd__h459187 = _theResult___snd__h458617[56:34]; - default: _theResult___fst_sfd__h459187 = 23'd0; + 3'd4: _theResult___fst_sfd__h459188 = _theResult___snd__h458618[56:34]; + default: _theResult___fst_sfd__h459188 = 23'd0; endcase end - always@(guard__h441911 or - sfdin__h450004 or out_sfd__h450530 or _theResult___sfd__h450527) + always@(guard__h441912 or + sfdin__h450005 or out_sfd__h450531 or _theResult___sfd__h450528) begin - case (guard__h441911) + case (guard__h441912) 2'b0, 2'b01: - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q120 = - sfdin__h450004[56:34]; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + sfdin__h450005[56:34]; 2'b10: - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q120 = - out_sfd__h450530; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + out_sfd__h450531; 2'b11: - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h450527; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h450528; endcase end - always@(guard__h441911 or sfdin__h450004 or _theResult___sfd__h450527) + always@(guard__h441912 or sfdin__h450005 or _theResult___sfd__h450528) begin - case (guard__h441911) + case (guard__h441912) 2'b0: - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q121 = - sfdin__h450004[56:34]; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 = + sfdin__h450005[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h450527; + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h450528; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q120 or - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q121 or + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120 or + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843 or - sfdin__h450004) + sfdin__h450005) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h450605 = - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h450606 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q120; 3'd1: - _theResult___fst_sfd__h450605 = - CASE_guard41911_0b0_sfdin50004_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h450606 = + CASE_guard41912_0b0_sfdin50005_BITS_56_TO_34_0_ETC__q121; 3'd2: - _theResult___fst_sfd__h450605 = + _theResult___fst_sfd__h450606 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7841; 3'd3: - _theResult___fst_sfd__h450605 = + _theResult___fst_sfd__h450606 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7843; - 3'd4: _theResult___fst_sfd__h450605 = sfdin__h450004[56:34]; - default: _theResult___fst_sfd__h450605 = 23'd0; + 3'd4: _theResult___fst_sfd__h450606 = sfdin__h450005[56:34]; + default: _theResult___fst_sfd__h450606 = 23'd0; endcase end - always@(guard__h459548 or - sfdin__h467770 or out_sfd__h468296 or _theResult___sfd__h468293) + always@(guard__h459549 or + sfdin__h467771 or out_sfd__h468297 or _theResult___sfd__h468294) begin - case (guard__h459548) + case (guard__h459549) 2'b0, 2'b01: - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q122 = - sfdin__h467770[56:34]; + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122 = + sfdin__h467771[56:34]; 2'b10: - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q122 = - out_sfd__h468296; + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122 = + out_sfd__h468297; 2'b11: - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h468293; + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h468294; endcase end - always@(guard__h459548 or sfdin__h467770 or _theResult___sfd__h468293) + always@(guard__h459549 or sfdin__h467771 or _theResult___sfd__h468294) begin - case (guard__h459548) + case (guard__h459549) 2'b0: - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q123 = - sfdin__h467770[56:34]; + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q123 = + sfdin__h467771[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q123 = - _theResult___sfd__h468293; + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q123 = + _theResult___sfd__h468294; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q122 or - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q123 or + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122 or + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q123 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7887 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7889 or - sfdin__h467770) + sfdin__h467771) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h468371 = - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h468372 = + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q122; 3'd1: - _theResult___fst_sfd__h468371 = - CASE_guard59548_0b0_sfdin67770_BITS_56_TO_34_0_ETC__q123; + _theResult___fst_sfd__h468372 = + CASE_guard59549_0b0_sfdin67771_BITS_56_TO_34_0_ETC__q123; 3'd2: - _theResult___fst_sfd__h468371 = + _theResult___fst_sfd__h468372 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7887; 3'd3: - _theResult___fst_sfd__h468371 = + _theResult___fst_sfd__h468372 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7889; - 3'd4: _theResult___fst_sfd__h468371 = sfdin__h467770[56:34]; - default: _theResult___fst_sfd__h468371 = 23'd0; + 3'd4: _theResult___fst_sfd__h468372 = sfdin__h467771[56:34]; + default: _theResult___fst_sfd__h468372 = 23'd0; endcase end - always@(guard__h468384 or - _theResult___snd__h476407 or - out_sfd__h476932 or _theResult___sfd__h476929) + always@(guard__h468385 or + _theResult___snd__h476408 or + out_sfd__h476933 or _theResult___sfd__h476930) begin - case (guard__h468384) + case (guard__h468385) 2'b0, 2'b01: - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q124 = - _theResult___snd__h476407[56:34]; + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q124 = + _theResult___snd__h476408[56:34]; 2'b10: - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q124 = - out_sfd__h476932; + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q124 = + out_sfd__h476933; 2'b11: - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q124 = - _theResult___sfd__h476929; + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q124 = + _theResult___sfd__h476930; endcase end - always@(guard__h468384 or - _theResult___snd__h476407 or _theResult___sfd__h476929) + always@(guard__h468385 or + _theResult___snd__h476408 or _theResult___sfd__h476930) begin - case (guard__h468384) + case (guard__h468385) 2'b0: - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q125 = - _theResult___snd__h476407[56:34]; + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q125 = + _theResult___snd__h476408[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q125 = - _theResult___sfd__h476929; + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q125 = + _theResult___sfd__h476930; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q124 or - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q125 or + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q124 or + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q125 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908 or - _theResult___snd__h476407) + _theResult___snd__h476408) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h477007 = - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q124; + _theResult___fst_sfd__h477008 = + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q124; 3'd1: - _theResult___fst_sfd__h477007 = - CASE_guard68384_0b0_theResult___snd76407_BITS__ETC__q125; + _theResult___fst_sfd__h477008 = + CASE_guard68385_0b0_theResult___snd76408_BITS__ETC__q125; 3'd2: - _theResult___fst_sfd__h477007 = + _theResult___fst_sfd__h477008 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7906; 3'd3: - _theResult___fst_sfd__h477007 = + _theResult___fst_sfd__h477008 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7908; - 3'd4: _theResult___fst_sfd__h477007 = _theResult___snd__h476407[56:34]; - default: _theResult___fst_sfd__h477007 = 23'd0; + 3'd4: _theResult___fst_sfd__h477008 = _theResult___snd__h476408[56:34]; + default: _theResult___fst_sfd__h477008 = 23'd0; endcase end - always@(guard__h441911 or + always@(guard__h441912 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h441911) + case (guard__h441912) 2'b0, 2'b01, 2'b10: - CASE_guard41911_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard41911_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = - guard__h441911 == 2'b11 && + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h441912 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41911_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or - guard__h441911) + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h441912) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = - CASE_guard41911_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; + CASE_guard41912_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = - (guard__h441911 == 2'b0) ? + (guard__h441912 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h441911 == 2'b01 || guard__h441911 == 2'b10 || - guard__h441911 == 2'b11) && + (guard__h441912 == 2'b01 || guard__h441912 == 2'b10 || + guard__h441912 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7994 = @@ -35697,34 +35697,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h441911 or + always@(guard__h441912 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h441911) + case (guard__h441912) 2'b0, 2'b01, 2'b10: - CASE_guard41911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard41911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = - guard__h441911 != 2'b11 || + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h441912 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard41911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or - guard__h441911) + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h441912) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - CASE_guard41911_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + CASE_guard41912_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = - (guard__h441911 == 2'b0) ? + (guard__h441912 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h441911 != 2'b01 && guard__h441911 != 2'b10 && - guard__h441911 != 2'b11 || + guard__h441912 != 2'b01 && guard__h441912 != 2'b10 && + guard__h441912 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7938 = @@ -35735,34 +35735,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h450618 or + always@(guard__h450619 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h450618) + case (guard__h450619) 2'b0, 2'b01, 2'b10: - CASE_guard50618_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50618_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = - guard__h450618 == 2'b11 && + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 = + guard__h450619 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50618_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or - guard__h450618) + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128 or + guard__h450619) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = - CASE_guard50618_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128; + CASE_guard50619_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = - (guard__h450618 == 2'b0) ? + (guard__h450619 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h450618 == 2'b01 || guard__h450618 == 2'b10 || - guard__h450618 == 2'b11) && + (guard__h450619 == 2'b01 || guard__h450619 == 2'b10 || + guard__h450619 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8001 = @@ -35773,34 +35773,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h450618 or + always@(guard__h450619 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h450618) + case (guard__h450619) 2'b0, 2'b01, 2'b10: - CASE_guard50618_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = + CASE_guard50619_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard50618_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = - guard__h450618 != 2'b11 || + CASE_guard50619_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 = + guard__h450619 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard50618_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 or - guard__h450618) + CASE_guard50619_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129 or + guard__h450619) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 = - CASE_guard50618_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129; + CASE_guard50619_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 = - (guard__h450618 == 2'b0) ? + (guard__h450619 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h450618 != 2'b01 && guard__h450618 != 2'b10 && - guard__h450618 != 2'b11 || + guard__h450619 != 2'b01 && guard__h450619 != 2'b10 && + guard__h450619 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 = @@ -35811,34 +35811,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459548 or + always@(guard__h459549 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459548) + case (guard__h459549) 2'b0, 2'b01, 2'b10: - CASE_guard59548_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = + CASE_guard59549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59548_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = - guard__h459548 == 2'b11 && + CASE_guard59549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 = + guard__h459549 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59548_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or - guard__h459548) + CASE_guard59549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or + guard__h459549) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011 = - CASE_guard59548_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130; + CASE_guard59549_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011 = - (guard__h459548 == 2'b0) ? + (guard__h459549 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h459548 == 2'b01 || guard__h459548 == 2'b10 || - guard__h459548 == 2'b11) && + (guard__h459549 == 2'b01 || guard__h459549 == 2'b10 || + guard__h459549 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8011 = @@ -35849,34 +35849,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h459548 or + always@(guard__h459549 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h459548) + case (guard__h459549) 2'b0, 2'b01, 2'b10: - CASE_guard59548_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = + CASE_guard59549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard59548_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = - guard__h459548 != 2'b11 || + CASE_guard59549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 = + guard__h459549 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard59548_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or - guard__h459548) + CASE_guard59549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or + guard__h459549) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968 = - CASE_guard59548_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131; + CASE_guard59549_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968 = - (guard__h459548 == 2'b0) ? + (guard__h459549 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h459548 != 2'b01 && guard__h459548 != 2'b10 && - guard__h459548 != 2'b11 || + guard__h459549 != 2'b01 && guard__h459549 != 2'b10 && + guard__h459549 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7968 = @@ -35887,34 +35887,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468384 or + always@(guard__h468385 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468384) + case (guard__h468385) 2'b0, 2'b01, 2'b10: - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = - guard__h468384 == 2'b11 && + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 = + guard__h468385 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 or - guard__h468384) + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132 or + guard__h468385) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018 = - CASE_guard68384_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132; + CASE_guard68385_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018 = - (guard__h468384 == 2'b0) ? + (guard__h468385 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h468384 == 2'b01 || guard__h468384 == 2'b10 || - guard__h468384 == 2'b11) && + (guard__h468385 == 2'b01 || guard__h468385 == 2'b10 || + guard__h468385 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8018 = @@ -35925,34 +35925,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h468384 or + always@(guard__h468385 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h468384) + case (guard__h468385) 2'b0, 2'b01, 2'b10: - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = - guard__h468384 != 2'b11 || + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 = + guard__h468385 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 or - guard__h468384) + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133 or + guard__h468385) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981 = - CASE_guard68384_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133; + CASE_guard68385_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q133; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981 = - (guard__h468384 == 2'b0) ? + (guard__h468385 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h468384 != 2'b01 && guard__h468384 != 2'b10 && - guard__h468384 != 2'b11 || + guard__h468385 != 2'b01 && guard__h468385 != 2'b10 && + guard__h468385 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7981 = @@ -36009,28 +36009,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h498497 or - _theResult___fst_exp__h506458 or _theResult___exp__h507113) + always@(guard__h498498 or + _theResult___fst_exp__h506459 or _theResult___exp__h507114) begin - case (guard__h498497) + case (guard__h498498) 2'b0: - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q143 = - _theResult___fst_exp__h506458; + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q143 = + _theResult___fst_exp__h506459; 2'b01, 2'b10, 2'b11: - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q143 = - _theResult___exp__h507113; + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q143 = + _theResult___exp__h507114; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h506458 or + _theResult___fst_exp__h506459 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9130 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9128 or - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q143) + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = - _theResult___fst_exp__h506458; + _theResult___fst_exp__h506459; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9130; @@ -36039,44 +36039,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9128; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q143; + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9134 = 11'd0; endcase end - always@(guard__h498497 or - _theResult___fst_exp__h506458 or - out_exp__h507116 or _theResult___exp__h507113) + always@(guard__h498498 or + _theResult___fst_exp__h506459 or + out_exp__h507117 or _theResult___exp__h507114) begin - case (guard__h498497) + case (guard__h498498) 2'b0, 2'b01: - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q144 = - _theResult___fst_exp__h506458; + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q144 = + _theResult___fst_exp__h506459; 2'b10: - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q144 = - out_exp__h507116; + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q144 = + out_exp__h507117; 2'b11: - CASE_guard98497_0b0_theResult___fst_exp06458_0_ETC__q144 = - _theResult___exp__h507113; + CASE_guard98498_0b0_theResult___fst_exp06459_0_ETC__q144 = + _theResult___exp__h507114; endcase end - always@(guard__h498497 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h498498 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h498497) + case (guard__h498498) 2'b0, 2'b01, 2'b10: - CASE_guard98497_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard98498_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard98497_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h498497 == 2'b11 && + CASE_guard98498_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h498498 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498497) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498498) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36086,12 +36086,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h498497 == 2'b0) ? + (guard__h498498 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h498497 == 2'b01 || guard__h498497 == 2'b10 || - guard__h498497 == 2'b11) && + (guard__h498498 == 2'b01 || guard__h498498 == 2'b10 || + guard__h498498 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -36102,23 +36102,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h507809 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h507810 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h507809) + case (guard__h507810) 2'b0, 2'b01, 2'b10: - CASE_guard07809_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard07810_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard07809_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h507809 == 2'b11 && + CASE_guard07810_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h507810 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507809) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h507810) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36128,12 +36128,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h507809 == 2'b0) ? + (guard__h507810 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h507809 == 2'b01 || guard__h507809 == 2'b10 || - guard__h507809 == 2'b11) && + (guard__h507810 == 2'b01 || guard__h507810 == 2'b10 || + guard__h507810 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -36144,23 +36144,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h516878 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h516879 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h516878) + case (guard__h516879) 2'b0, 2'b01, 2'b10: - CASE_guard16878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard16879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard16878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h516878 == 2'b11 && + CASE_guard16879_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h516879 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h516878) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h516879) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36170,12 +36170,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h516878 == 2'b0) ? + (guard__h516879 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h516878 == 2'b01 || guard__h516878 == 2'b10 || - guard__h516878 == 2'b11) && + (guard__h516879 == 2'b01 || guard__h516879 == 2'b10 || + guard__h516879 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -36186,28 +36186,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h576654 or - _theResult___fst_exp__h584615 or _theResult___exp__h585270) + always@(guard__h576655 or + _theResult___fst_exp__h584616 or _theResult___exp__h585271) begin - case (guard__h576654) + case (guard__h576655) 2'b0: - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q160 = - _theResult___fst_exp__h584615; + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q160 = + _theResult___fst_exp__h584616; 2'b01, 2'b10, 2'b11: - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q160 = - _theResult___exp__h585270; + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q160 = + _theResult___exp__h585271; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h584615 or + _theResult___fst_exp__h584616 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9845 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9843 or - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q160) + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = - _theResult___fst_exp__h584615; + _theResult___fst_exp__h584616; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9845; @@ -36216,42 +36216,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9843; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q160; + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9849 = 11'd0; endcase end - always@(guard__h576654 or - _theResult___fst_exp__h584615 or - out_exp__h585273 or _theResult___exp__h585270) + always@(guard__h576655 or + _theResult___fst_exp__h584616 or + out_exp__h585274 or _theResult___exp__h585271) begin - case (guard__h576654) + case (guard__h576655) 2'b0, 2'b01: - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q161 = - _theResult___fst_exp__h584615; + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q161 = + _theResult___fst_exp__h584616; 2'b10: - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q161 = - out_exp__h585273; + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q161 = + out_exp__h585274; 2'b11: - CASE_guard76654_0b0_theResult___fst_exp84615_0_ETC__q161 = - _theResult___exp__h585270; + CASE_guard76655_0b0_theResult___fst_exp84616_0_ETC__q161 = + _theResult___exp__h585271; endcase end - always@(guard__h576654 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576655 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576654) + case (guard__h576655) 2'b0, 2'b01, 2'b10: - CASE_guard76654_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard76655_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76654_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h576654 == 2'b11 && + CASE_guard76655_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h576655 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576654) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576655) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36260,12 +36260,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h576654 == 2'b0) ? + (guard__h576655 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h576654 == 2'b01 || guard__h576654 == 2'b10 || - guard__h576654 == 2'b11) && + (guard__h576655 == 2'b01 || guard__h576655 == 2'b10 || + guard__h576655 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36276,21 +36276,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595035 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595035) + case (guard__h595036) 2'b0, 2'b01, 2'b10: - CASE_guard95035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard95036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h595035 == 2'b11 && + CASE_guard95036_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h595036 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595035) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36299,12 +36299,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h595035 == 2'b0) ? + (guard__h595036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h595035 == 2'b01 || guard__h595035 == 2'b10 || - guard__h595035 == 2'b11) && + (guard__h595036 == 2'b01 || guard__h595036 == 2'b10 || + guard__h595036 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36315,21 +36315,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h585966 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h585967 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h585966) + case (guard__h585967) 2'b0, 2'b01, 2'b10: - CASE_guard85966_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard85967_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard85966_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h585966 == 2'b11 && + CASE_guard85967_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h585967 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585966) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585967) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36338,12 +36338,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h585966 == 2'b0) ? + (guard__h585967 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h585966 == 2'b01 || guard__h585966 == 2'b10 || - guard__h585966 == 2'b11) && + (guard__h585967 == 2'b01 || guard__h585967 == 2'b10 || + guard__h585967 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36354,21 +36354,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h585966 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h585967 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h585966) + case (guard__h585967) 2'b0, 2'b01, 2'b10: - CASE_guard85966_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard85967_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard85966_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h585966 != 2'b11 || + CASE_guard85967_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h585967 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585966) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h585967) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36377,12 +36377,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h585966 == 2'b0) ? + (guard__h585967 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h585966 != 2'b01 && guard__h585966 != 2'b10 && - guard__h585966 != 2'b11 || + guard__h585967 != 2'b01 && guard__h585967 != 2'b10 && + guard__h585967 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36393,21 +36393,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h595035 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h595036 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h595035) + case (guard__h595036) 2'b0, 2'b01, 2'b10: - CASE_guard95035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard95035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h595035 != 2'b11 || + CASE_guard95036_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h595036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595035) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595036) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36416,12 +36416,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h595035 == 2'b0) ? + (guard__h595036 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h595035 != 2'b01 && guard__h595035 != 2'b10 && - guard__h595035 != 2'b11 || + guard__h595036 != 2'b01 && guard__h595036 != 2'b10 && + guard__h595036 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36432,21 +36432,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h576654 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h576655 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h576654) + case (guard__h576655) 2'b0, 2'b01, 2'b10: - CASE_guard76654_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard76654_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h576654 != 2'b11 || + CASE_guard76655_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h576655 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576654) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h576655) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36455,12 +36455,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h576654 == 2'b0) ? + (guard__h576655 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h576654 != 2'b01 && guard__h576654 != 2'b10 && - guard__h576654 != 2'b11 || + guard__h576655 != 2'b01 && guard__h576655 != 2'b10 && + guard__h576655 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36471,28 +36471,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h537350 or - _theResult___fst_exp__h545311 or _theResult___exp__h545966) + always@(guard__h537351 or + _theResult___fst_exp__h545312 or _theResult___exp__h545967) begin - case (guard__h537350) + case (guard__h537351) 2'b0: - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q183 = - _theResult___fst_exp__h545311; + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q183 = + _theResult___fst_exp__h545312; 2'b01, 2'b10, 2'b11: - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q183 = - _theResult___exp__h545966; + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q183 = + _theResult___exp__h545967; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h545311 or + _theResult___fst_exp__h545312 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10615 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10613 or - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q183) + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = - _theResult___fst_exp__h545311; + _theResult___fst_exp__h545312; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10615; @@ -36501,49 +36501,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10613; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q183; + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10619 = 11'd0; endcase end - always@(guard__h537350 or - _theResult___fst_exp__h545311 or - out_exp__h545969 or _theResult___exp__h545966) + always@(guard__h537351 or + _theResult___fst_exp__h545312 or + out_exp__h545970 or _theResult___exp__h545967) begin - case (guard__h537350) + case (guard__h537351) 2'b0, 2'b01: - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q184 = - _theResult___fst_exp__h545311; + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q184 = + _theResult___fst_exp__h545312; 2'b10: - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q184 = - out_exp__h545969; + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q184 = + out_exp__h545970; 2'b11: - CASE_guard37350_0b0_theResult___fst_exp45311_0_ETC__q184 = - _theResult___exp__h545966; + CASE_guard37351_0b0_theResult___fst_exp45312_0_ETC__q184 = + _theResult___exp__h545967; endcase end - always@(guard__h546662 or - _theResult___fst_exp__h554888 or _theResult___exp__h555617) + always@(guard__h546663 or + _theResult___fst_exp__h554889 or _theResult___exp__h555618) begin - case (guard__h546662) + case (guard__h546663) 2'b0: - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q185 = - _theResult___fst_exp__h554888; + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q185 = + _theResult___fst_exp__h554889; 2'b01, 2'b10, 2'b11: - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q185 = - _theResult___exp__h555617; + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q185 = + _theResult___exp__h555618; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h554888 or + _theResult___fst_exp__h554889 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651 or - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q185) + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = - _theResult___fst_exp__h554888; + _theResult___fst_exp__h554889; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10653; @@ -36552,49 +36552,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10651; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q185; + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10657 = 11'd0; endcase end - always@(guard__h546662 or - _theResult___fst_exp__h554888 or - out_exp__h555620 or _theResult___exp__h555617) + always@(guard__h546663 or + _theResult___fst_exp__h554889 or + out_exp__h555621 or _theResult___exp__h555618) begin - case (guard__h546662) + case (guard__h546663) 2'b0, 2'b01: - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q186 = - _theResult___fst_exp__h554888; + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q186 = + _theResult___fst_exp__h554889; 2'b10: - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q186 = - out_exp__h555620; + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q186 = + out_exp__h555621; 2'b11: - CASE_guard46662_0b0_theResult___fst_exp54888_0_ETC__q186 = - _theResult___exp__h555617; + CASE_guard46663_0b0_theResult___fst_exp54889_0_ETC__q186 = + _theResult___exp__h555618; endcase end - always@(guard__h555731 or - _theResult___fst_exp__h563721 or _theResult___exp__h564401) + always@(guard__h555732 or + _theResult___fst_exp__h563722 or _theResult___exp__h564402) begin - case (guard__h555731) + case (guard__h555732) 2'b0: - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q187 = - _theResult___fst_exp__h563721; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187 = + _theResult___fst_exp__h563722; 2'b01, 2'b10, 2'b11: - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q187 = - _theResult___exp__h564401; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187 = + _theResult___exp__h564402; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h563721 or + _theResult___fst_exp__h563722 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682 or - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q187) + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = - _theResult___fst_exp__h563721; + _theResult___fst_exp__h563722; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10684; @@ -36603,49 +36603,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10682; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q187; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10688 = 11'd0; endcase end - always@(guard__h555731 or - _theResult___fst_exp__h563721 or - out_exp__h564404 or _theResult___exp__h564401) + always@(guard__h555732 or + _theResult___fst_exp__h563722 or + out_exp__h564405 or _theResult___exp__h564402) begin - case (guard__h555731) + case (guard__h555732) 2'b0, 2'b01: - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q188 = - _theResult___fst_exp__h563721; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = + _theResult___fst_exp__h563722; 2'b10: - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q188 = - out_exp__h564404; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = + out_exp__h564405; 2'b11: - CASE_guard55731_0b0_theResult___fst_exp63721_0_ETC__q188 = - _theResult___exp__h564401; + CASE_guard55732_0b0_theResult___fst_exp63722_0_ETC__q188 = + _theResult___exp__h564402; endcase end - always@(guard__h585966 or - _theResult___fst_exp__h594192 or _theResult___exp__h594921) + always@(guard__h585967 or + _theResult___fst_exp__h594193 or _theResult___exp__h594922) begin - case (guard__h585966) + case (guard__h585967) 2'b0: - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q189 = - _theResult___fst_exp__h594192; + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q189 = + _theResult___fst_exp__h594193; 2'b01, 2'b10, 2'b11: - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q189 = - _theResult___exp__h594921; + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q189 = + _theResult___exp__h594922; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h594192 or + _theResult___fst_exp__h594193 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881 or - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q189) + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - _theResult___fst_exp__h594192; + _theResult___fst_exp__h594193; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9883; @@ -36654,49 +36654,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9881; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q189; + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9887 = 11'd0; endcase end - always@(guard__h585966 or - _theResult___fst_exp__h594192 or - out_exp__h594924 or _theResult___exp__h594921) + always@(guard__h585967 or + _theResult___fst_exp__h594193 or + out_exp__h594925 or _theResult___exp__h594922) begin - case (guard__h585966) + case (guard__h585967) 2'b0, 2'b01: - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q190 = - _theResult___fst_exp__h594192; + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q190 = + _theResult___fst_exp__h594193; 2'b10: - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q190 = - out_exp__h594924; + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q190 = + out_exp__h594925; 2'b11: - CASE_guard85966_0b0_theResult___fst_exp94192_0_ETC__q190 = - _theResult___exp__h594921; + CASE_guard85967_0b0_theResult___fst_exp94193_0_ETC__q190 = + _theResult___exp__h594922; endcase end - always@(guard__h595035 or - _theResult___fst_exp__h603025 or _theResult___exp__h603705) + always@(guard__h595036 or + _theResult___fst_exp__h603026 or _theResult___exp__h603706) begin - case (guard__h595035) + case (guard__h595036) 2'b0: - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q191 = - _theResult___fst_exp__h603025; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191 = + _theResult___fst_exp__h603026; 2'b01, 2'b10, 2'b11: - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q191 = - _theResult___exp__h603705; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191 = + _theResult___exp__h603706; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h603025 or + _theResult___fst_exp__h603026 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912 or - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q191) + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = - _theResult___fst_exp__h603025; + _theResult___fst_exp__h603026; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9914; @@ -36705,44 +36705,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9912; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q191; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9918 = 11'd0; endcase end - always@(guard__h595035 or - _theResult___fst_exp__h603025 or - out_exp__h603708 or _theResult___exp__h603705) + always@(guard__h595036 or + _theResult___fst_exp__h603026 or + out_exp__h603709 or _theResult___exp__h603706) begin - case (guard__h595035) + case (guard__h595036) 2'b0, 2'b01: - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q192 = - _theResult___fst_exp__h603025; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + _theResult___fst_exp__h603026; 2'b10: - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q192 = - out_exp__h603708; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + out_exp__h603709; 2'b11: - CASE_guard95035_0b0_theResult___fst_exp03025_0_ETC__q192 = - _theResult___exp__h603705; + CASE_guard95036_0b0_theResult___fst_exp03026_0_ETC__q192 = + _theResult___exp__h603706; endcase end - always@(guard__h546662 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h546663 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h546662) + case (guard__h546663) 2'b0, 2'b01, 2'b10: - CASE_guard46662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard46663_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard46662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h546662 == 2'b11 && + CASE_guard46663_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h546663 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546662) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546663) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36752,12 +36752,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h546662 == 2'b0) ? + (guard__h546663 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h546662 == 2'b01 || guard__h546662 == 2'b10 || - guard__h546662 == 2'b11) && + (guard__h546663 == 2'b01 || guard__h546663 == 2'b10 || + guard__h546663 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36768,23 +36768,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537350 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537351 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537350) + case (guard__h537351) 2'b0, 2'b01, 2'b10: - CASE_guard37350_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard37351_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37350_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h537350 == 2'b11 && + CASE_guard37351_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h537351 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537350) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537351) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36794,12 +36794,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h537350 == 2'b0) ? + (guard__h537351 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h537350 == 2'b01 || guard__h537350 == 2'b10 || - guard__h537350 == 2'b11) && + (guard__h537351 == 2'b01 || guard__h537351 == 2'b10 || + guard__h537351 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36810,23 +36810,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h555731 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h555732 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h555731) + case (guard__h555732) 2'b0, 2'b01, 2'b10: - CASE_guard55731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard55732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard55731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h555731 == 2'b11 && + CASE_guard55732_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h555732 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555731) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555732) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36836,12 +36836,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h555731 == 2'b0) ? + (guard__h555732 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h555731 == 2'b01 || guard__h555731 == 2'b10 || - guard__h555731 == 2'b11) && + (guard__h555732 == 2'b01 || guard__h555732 == 2'b10 || + guard__h555732 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36852,23 +36852,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h546662 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h546663 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h546662) + case (guard__h546663) 2'b0, 2'b01, 2'b10: - CASE_guard46662_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard46663_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard46662_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h546662 != 2'b11 || + CASE_guard46663_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h546663 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546662) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h546663) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36878,12 +36878,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h546662 == 2'b0) ? + (guard__h546663 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h546662 != 2'b01 && guard__h546662 != 2'b10 && - guard__h546662 != 2'b11 || + guard__h546663 != 2'b01 && guard__h546663 != 2'b10 && + guard__h546663 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36894,23 +36894,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h555731 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h555732 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h555731) + case (guard__h555732) 2'b0, 2'b01, 2'b10: - CASE_guard55731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard55732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard55731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h555731 != 2'b11 || + CASE_guard55732_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h555732 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555731) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h555732) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36920,12 +36920,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h555731 == 2'b0) ? + (guard__h555732 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h555731 != 2'b01 && guard__h555731 != 2'b10 && - guard__h555731 != 2'b11 || + guard__h555732 != 2'b01 && guard__h555732 != 2'b10 && + guard__h555732 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36936,23 +36936,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537350 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h537351 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h537350) + case (guard__h537351) 2'b0, 2'b01, 2'b10: - CASE_guard37350_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard37351_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard37350_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h537350 != 2'b11 || + CASE_guard37351_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h537351 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537350) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537351) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36962,12 +36962,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h537350 == 2'b0) ? + (guard__h537351 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h537350 != 2'b01 && guard__h537350 != 2'b10 && - guard__h537350 != 2'b11 || + guard__h537351 != 2'b01 && guard__h537351 != 2'b10 && + guard__h537351 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36978,28 +36978,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h537350 or - _theResult___snd__h545262 or _theResult___sfd__h545967) + always@(guard__h537351 or + _theResult___snd__h545263 or _theResult___sfd__h545968) begin - case (guard__h537350) + case (guard__h537351) 2'b0: - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q205 = - _theResult___snd__h545262[56:5]; + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q205 = + _theResult___snd__h545263[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q205 = - _theResult___sfd__h545967; + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q205 = + _theResult___sfd__h545968; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h545262 or + _theResult___snd__h545263 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10710 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708 or - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q205) + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = - _theResult___snd__h545262[56:5]; + _theResult___snd__h545263[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10710; @@ -37008,48 +37008,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10708; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q205; + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10714 = 52'd0; endcase end - always@(guard__h537350 or - _theResult___snd__h545262 or - out_sfd__h545970 or _theResult___sfd__h545967) + always@(guard__h537351 or + _theResult___snd__h545263 or + out_sfd__h545971 or _theResult___sfd__h545968) begin - case (guard__h537350) + case (guard__h537351) 2'b0, 2'b01: - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q206 = - _theResult___snd__h545262[56:5]; + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q206 = + _theResult___snd__h545263[56:5]; 2'b10: - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q206 = - out_sfd__h545970; + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q206 = + out_sfd__h545971; 2'b11: - CASE_guard37350_0b0_theResult___snd45262_BITS__ETC__q206 = - _theResult___sfd__h545967; + CASE_guard37351_0b0_theResult___snd45263_BITS__ETC__q206 = + _theResult___sfd__h545968; endcase end - always@(guard__h546662 or sfdin__h554882 or _theResult___sfd__h555618) + always@(guard__h546663 or sfdin__h554883 or _theResult___sfd__h555619) begin - case (guard__h546662) + case (guard__h546663) 2'b0: - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h554882[56:5]; + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h554883[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h555618; + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h555619; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h554882 or + sfdin__h554883 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734 or - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q207) + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = - sfdin__h554882[56:5]; + sfdin__h554883[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10736; @@ -37058,48 +37058,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10734; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q207; + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10740 = 52'd0; endcase end - always@(guard__h546662 or - sfdin__h554882 or out_sfd__h555621 or _theResult___sfd__h555618) + always@(guard__h546663 or + sfdin__h554883 or out_sfd__h555622 or _theResult___sfd__h555619) begin - case (guard__h546662) + case (guard__h546663) 2'b0, 2'b01: - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h554882[56:5]; + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h554883[56:5]; 2'b10: - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h555621; + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h555622; 2'b11: - CASE_guard46662_0b0_sfdin54882_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h555618; + CASE_guard46663_0b0_sfdin54883_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h555619; endcase end - always@(guard__h555731 or - _theResult___snd__h563667 or _theResult___sfd__h564402) + always@(guard__h555732 or + _theResult___snd__h563668 or _theResult___sfd__h564403) begin - case (guard__h555731) + case (guard__h555732) 2'b0: - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q209 = - _theResult___snd__h563667[56:5]; + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q209 = + _theResult___snd__h563668[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q209 = - _theResult___sfd__h564402; + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q209 = + _theResult___sfd__h564403; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h563667 or + _theResult___snd__h563668 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10755 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10753 or - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q209) + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = - _theResult___snd__h563667[56:5]; + _theResult___snd__h563668[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10755; @@ -37108,49 +37108,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10753; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q209; + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d10759 = 52'd0; endcase end - always@(guard__h555731 or - _theResult___snd__h563667 or - out_sfd__h564405 or _theResult___sfd__h564402) + always@(guard__h555732 or + _theResult___snd__h563668 or + out_sfd__h564406 or _theResult___sfd__h564403) begin - case (guard__h555731) + case (guard__h555732) 2'b0, 2'b01: - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q210 = - _theResult___snd__h563667[56:5]; + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q210 = + _theResult___snd__h563668[56:5]; 2'b10: - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q210 = - out_sfd__h564405; + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q210 = + out_sfd__h564406; 2'b11: - CASE_guard55731_0b0_theResult___snd63667_BITS__ETC__q210 = - _theResult___sfd__h564402; + CASE_guard55732_0b0_theResult___snd63668_BITS__ETC__q210 = + _theResult___sfd__h564403; endcase end - always@(guard__h507809 or - _theResult___fst_exp__h516035 or _theResult___exp__h516764) + always@(guard__h507810 or + _theResult___fst_exp__h516036 or _theResult___exp__h516765) begin - case (guard__h507809) + case (guard__h507810) 2'b0: - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q211 = - _theResult___fst_exp__h516035; + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q211 = + _theResult___fst_exp__h516036; 2'b01, 2'b10, 2'b11: - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q211 = - _theResult___exp__h516764; + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q211 = + _theResult___exp__h516765; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h516035 or + _theResult___fst_exp__h516036 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9173 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171 or - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q211) + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = - _theResult___fst_exp__h516035; + _theResult___fst_exp__h516036; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9173; @@ -37159,49 +37159,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9171; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q211; + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9177 = 11'd0; endcase end - always@(guard__h507809 or - _theResult___fst_exp__h516035 or - out_exp__h516767 or _theResult___exp__h516764) + always@(guard__h507810 or + _theResult___fst_exp__h516036 or + out_exp__h516768 or _theResult___exp__h516765) begin - case (guard__h507809) + case (guard__h507810) 2'b0, 2'b01: - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q212 = - _theResult___fst_exp__h516035; + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q212 = + _theResult___fst_exp__h516036; 2'b10: - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q212 = - out_exp__h516767; + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q212 = + out_exp__h516768; 2'b11: - CASE_guard07809_0b0_theResult___fst_exp16035_0_ETC__q212 = - _theResult___exp__h516764; + CASE_guard07810_0b0_theResult___fst_exp16036_0_ETC__q212 = + _theResult___exp__h516765; endcase end - always@(guard__h516878 or - _theResult___fst_exp__h524868 or _theResult___exp__h525548) + always@(guard__h516879 or + _theResult___fst_exp__h524869 or _theResult___exp__h525549) begin - case (guard__h516878) + case (guard__h516879) 2'b0: - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q213 = - _theResult___fst_exp__h524868; + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q213 = + _theResult___fst_exp__h524869; 2'b01, 2'b10, 2'b11: - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q213 = - _theResult___exp__h525548; + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q213 = + _theResult___exp__h525549; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h524868 or + _theResult___fst_exp__h524869 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9204 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9202 or - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q213) + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = - _theResult___fst_exp__h524868; + _theResult___fst_exp__h524869; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9204; @@ -37210,49 +37210,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9202; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q213; + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9208 = 11'd0; endcase end - always@(guard__h516878 or - _theResult___fst_exp__h524868 or - out_exp__h525551 or _theResult___exp__h525548) + always@(guard__h516879 or + _theResult___fst_exp__h524869 or + out_exp__h525552 or _theResult___exp__h525549) begin - case (guard__h516878) + case (guard__h516879) 2'b0, 2'b01: - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q214 = - _theResult___fst_exp__h524868; + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q214 = + _theResult___fst_exp__h524869; 2'b10: - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q214 = - out_exp__h525551; + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q214 = + out_exp__h525552; 2'b11: - CASE_guard16878_0b0_theResult___fst_exp24868_0_ETC__q214 = - _theResult___exp__h525548; + CASE_guard16879_0b0_theResult___fst_exp24869_0_ETC__q214 = + _theResult___exp__h525549; endcase end - always@(guard__h498497 or - _theResult___snd__h506409 or _theResult___sfd__h507114) + always@(guard__h498498 or + _theResult___snd__h506410 or _theResult___sfd__h507115) begin - case (guard__h498497) + case (guard__h498498) 2'b0: - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q215 = - _theResult___snd__h506409[56:5]; + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q215 = + _theResult___snd__h506410[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q215 = - _theResult___sfd__h507114; + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q215 = + _theResult___sfd__h507115; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h506409 or + _theResult___snd__h506410 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9230 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9228 or - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q215) + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = - _theResult___snd__h506409[56:5]; + _theResult___snd__h506410[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9230; @@ -37261,48 +37261,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9228; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q215; + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9234 = 52'd0; endcase end - always@(guard__h498497 or - _theResult___snd__h506409 or - out_sfd__h507117 or _theResult___sfd__h507114) + always@(guard__h498498 or + _theResult___snd__h506410 or + out_sfd__h507118 or _theResult___sfd__h507115) begin - case (guard__h498497) + case (guard__h498498) 2'b0, 2'b01: - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q216 = - _theResult___snd__h506409[56:5]; + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q216 = + _theResult___snd__h506410[56:5]; 2'b10: - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q216 = - out_sfd__h507117; + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q216 = + out_sfd__h507118; 2'b11: - CASE_guard98497_0b0_theResult___snd06409_BITS__ETC__q216 = - _theResult___sfd__h507114; + CASE_guard98498_0b0_theResult___snd06410_BITS__ETC__q216 = + _theResult___sfd__h507115; endcase end - always@(guard__h507809 or sfdin__h516029 or _theResult___sfd__h516765) + always@(guard__h507810 or sfdin__h516030 or _theResult___sfd__h516766) begin - case (guard__h507809) + case (guard__h507810) 2'b0: - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h516029[56:5]; + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h516030[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h516765; + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h516766; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h516029 or + sfdin__h516030 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9257 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255 or - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q217) + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = - sfdin__h516029[56:5]; + sfdin__h516030[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9257; @@ -37311,48 +37311,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9255; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q217; + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9261 = 52'd0; endcase end - always@(guard__h507809 or - sfdin__h516029 or out_sfd__h516768 or _theResult___sfd__h516765) + always@(guard__h507810 or + sfdin__h516030 or out_sfd__h516769 or _theResult___sfd__h516766) begin - case (guard__h507809) + case (guard__h507810) 2'b0, 2'b01: - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h516029[56:5]; + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h516030[56:5]; 2'b10: - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h516768; + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h516769; 2'b11: - CASE_guard07809_0b0_sfdin16029_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h516765; + CASE_guard07810_0b0_sfdin16030_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h516766; endcase end - always@(guard__h516878 or - _theResult___snd__h524814 or _theResult___sfd__h525549) + always@(guard__h516879 or + _theResult___snd__h524815 or _theResult___sfd__h525550) begin - case (guard__h516878) + case (guard__h516879) 2'b0: - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q219 = - _theResult___snd__h524814[56:5]; + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q219 = + _theResult___snd__h524815[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q219 = - _theResult___sfd__h525549; + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q219 = + _theResult___sfd__h525550; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h524814 or + _theResult___snd__h524815 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9276 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9274 or - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q219) + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = - _theResult___snd__h524814[56:5]; + _theResult___snd__h524815[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9276; @@ -37361,49 +37361,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9274; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q219; + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9280 = 52'd0; endcase end - always@(guard__h516878 or - _theResult___snd__h524814 or - out_sfd__h525552 or _theResult___sfd__h525549) + always@(guard__h516879 or + _theResult___snd__h524815 or + out_sfd__h525553 or _theResult___sfd__h525550) begin - case (guard__h516878) + case (guard__h516879) 2'b0, 2'b01: - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q220 = - _theResult___snd__h524814[56:5]; + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q220 = + _theResult___snd__h524815[56:5]; 2'b10: - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q220 = - out_sfd__h525552; + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q220 = + out_sfd__h525553; 2'b11: - CASE_guard16878_0b0_theResult___snd24814_BITS__ETC__q220 = - _theResult___sfd__h525549; + CASE_guard16879_0b0_theResult___snd24815_BITS__ETC__q220 = + _theResult___sfd__h525550; endcase end - always@(guard__h576654 or - _theResult___snd__h584566 or _theResult___sfd__h585271) + always@(guard__h576655 or + _theResult___snd__h584567 or _theResult___sfd__h585272) begin - case (guard__h576654) + case (guard__h576655) 2'b0: - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q221 = - _theResult___snd__h584566[56:5]; + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q221 = + _theResult___snd__h584567[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q221 = - _theResult___sfd__h585271; + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q221 = + _theResult___sfd__h585272; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h584566 or + _theResult___snd__h584567 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9940 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9938 or - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q221) + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = - _theResult___snd__h584566[56:5]; + _theResult___snd__h584567[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9940; @@ -37412,48 +37412,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9938; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q221; + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9944 = 52'd0; endcase end - always@(guard__h576654 or - _theResult___snd__h584566 or - out_sfd__h585274 or _theResult___sfd__h585271) + always@(guard__h576655 or + _theResult___snd__h584567 or + out_sfd__h585275 or _theResult___sfd__h585272) begin - case (guard__h576654) + case (guard__h576655) 2'b0, 2'b01: - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q222 = - _theResult___snd__h584566[56:5]; + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q222 = + _theResult___snd__h584567[56:5]; 2'b10: - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q222 = - out_sfd__h585274; + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q222 = + out_sfd__h585275; 2'b11: - CASE_guard76654_0b0_theResult___snd84566_BITS__ETC__q222 = - _theResult___sfd__h585271; + CASE_guard76655_0b0_theResult___snd84567_BITS__ETC__q222 = + _theResult___sfd__h585272; endcase end - always@(guard__h585966 or sfdin__h594186 or _theResult___sfd__h594922) + always@(guard__h585967 or sfdin__h594187 or _theResult___sfd__h594923) begin - case (guard__h585966) + case (guard__h585967) 2'b0: - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h594186[56:5]; + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h594187[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h594922; + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h594923; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h594186 or + sfdin__h594187 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9966 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9964 or - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q223) + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = - sfdin__h594186[56:5]; + sfdin__h594187[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9966; @@ -37462,24 +37462,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9964; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q223; + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9970 = 52'd0; endcase end - always@(guard__h585966 or - sfdin__h594186 or out_sfd__h594925 or _theResult___sfd__h594922) + always@(guard__h585967 or + sfdin__h594187 or out_sfd__h594926 or _theResult___sfd__h594923) begin - case (guard__h585966) + case (guard__h585967) 2'b0, 2'b01: - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h594186[56:5]; + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h594187[56:5]; 2'b10: - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h594925; + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h594926; 2'b11: - CASE_guard85966_0b0_sfdin94186_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h594922; + CASE_guard85967_0b0_sfdin94187_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h594923; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37514,28 +37514,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__486_BI_ETC___d10967; endcase end - always@(guard__h595035 or - _theResult___snd__h602971 or _theResult___sfd__h603706) + always@(guard__h595036 or + _theResult___snd__h602972 or _theResult___sfd__h603707) begin - case (guard__h595035) + case (guard__h595036) 2'b0: - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q225 = - _theResult___snd__h602971[56:5]; + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q225 = + _theResult___snd__h602972[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q225 = - _theResult___sfd__h603706; + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q225 = + _theResult___sfd__h603707; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h602971 or + _theResult___snd__h602972 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9985 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9983 or - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q225) + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = - _theResult___snd__h602971[56:5]; + _theResult___snd__h602972[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9985; @@ -37544,25 +37544,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9983; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q225; + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__486_ETC___d9989 = 52'd0; endcase end - always@(guard__h595035 or - _theResult___snd__h602971 or - out_sfd__h603709 or _theResult___sfd__h603706) + always@(guard__h595036 or + _theResult___snd__h602972 or + out_sfd__h603710 or _theResult___sfd__h603707) begin - case (guard__h595035) + case (guard__h595036) 2'b0, 2'b01: - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q226 = - _theResult___snd__h602971[56:5]; + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q226 = + _theResult___snd__h602972[56:5]; 2'b10: - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q226 = - out_sfd__h603709; + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q226 = + out_sfd__h603710; 2'b11: - CASE_guard95035_0b0_theResult___snd02971_BITS__ETC__q226 = - _theResult___sfd__h603706; + CASE_guard95036_0b0_theResult___snd02972_BITS__ETC__q226 = + _theResult___sfd__h603707; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37882,10 +37882,10 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h677211 or + always@(k__h677212 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h677211) + case (k__h677212) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3684_co_ETC___d13694 = coreFix_aluExe_0_rsAlu$canEnq; @@ -37924,10 +37924,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13706; endcase end - always@(k__h677211 or + always@(k__h677212 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h677211) + case (k__h677212) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__368_ETC___d13727 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -38073,14 +38073,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h693568 or + always@(idx__h693569 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13991 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2992_BITS_19_ETC___d13997 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h693568) + case (idx__h693569) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2990_AN_ETC___d14017 = fetchStage$pipelines_0_canDeq && @@ -38201,15 +38201,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3775_AND__ETC___d13983; endcase end - always@(k__h677211 or + always@(k__h677212 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h677211) + case (k__h677212) 1'd0: - CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k77212_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k77211_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k77212_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -38312,14 +38312,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2992_BITS_191_ETC___d13706; endcase end - always@(idx__h693568 or + always@(idx__h693569 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14236 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2992_BITS_194_TO_ETC___d14243 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h693568) + case (idx__h693569) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__299_ETC___d14247 = (!fetchStage$pipelines_0_canDeq || @@ -38645,16 +38645,16 @@ module mkCore(CLK, begin case (IF_rob_deqPort_0_deq_data__4646_BIT_181_4721_T_ETC___d15295) 6'd0: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38667,30 +38667,31 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 54'd0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8], - 2'b0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4], - 2'b0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; + robdeqPort_0_deq_data_BITS_95_TO_32__q245[9], + 3'd0, + robdeqPort_0_deq_data_BITS_95_TO_32__q245[5], + 3'd0, + robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], + 1'd0 }; 6'd10, 6'd23: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38702,9 +38703,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h731607 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h731608 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38712,7 +38713,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38722,7 +38723,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd22, 6'd29: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 52'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'd0, @@ -38736,12 +38737,12 @@ module mkCore(CLK, 1'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h731607 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h731608 = 64'd0; 6'd37: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h731607 = + data_warl_xformed__h731608 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38750,7 +38751,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h731607 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h731608 = rob$deqPort_0_deq_data[95:32]; endcase end always@(rob$deqPort_0_deq_data or @@ -38758,9 +38759,9 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h732275 = + x__h732276 = IF_rob_deqPort_0_deq_data__4646_BITS_329_TO_32_ETC___d15505; - default: x__h732275 = rob$deqPort_0_deq_data[425:362]; + default: x__h732276 = rob$deqPort_0_deq_data[425:362]; endcase end always@(rob$deqPort_0_deq_data) @@ -41633,7 +41634,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[95:32]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_commitStage_doCommitSystemInst && - next_pc__h731630 != + next_pc__h731631 != rob_deqPort_0_deq_data__4646_BITS_425_TO_362_4_ETC___d15496) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) @@ -41974,7 +41975,7 @@ module mkCore(CLK, coreFix_aluExe_1_regToExeQ$first[395] && (basicExec___d12137[65:2] != coreFix_aluExe_1_regToExeQ$first[112:49] || - coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626401)) + coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626402)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu && @@ -41991,7 +41992,7 @@ module mkCore(CLK, coreFix_aluExe_0_regToExeQ$first[395] && (basicExec___d12839[65:2] != coreFix_aluExe_0_regToExeQ$first[112:49] || - coreFix_aluExe_0_regToExeQ$first[112:49] != y__h649115)) + coreFix_aluExe_0_regToExeQ$first[112:49] != y__h649116)) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu && @@ -42308,7 +42309,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h609135 == 2'd0) + v__h609136 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst && diff --git a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v index 1768535..3477744 100644 --- a/src_SSITH_P3/xilinx_ip/hdl/mkCore.v +++ b/src_SSITH_P3/xilinx_ip/hdl/mkCore.v @@ -4514,36 +4514,36 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875, - addr__h290068, - curData__h192917, - data_out__h737401, - data_warl_xformed__h722429, - rVal1__h609051, - rVal1__h633779, - trap_val__h710482, - x__h197127, - x__h723033; + addr__h290069, + curData__h192918, + data_out__h737272, + data_warl_xformed__h722430, + rVal1__h609052, + rVal1__h633780, + trap_val__h710483, + x__h197128, + x__h723034; reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19, - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217, - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218, - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219, - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220, - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205, - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206, - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207, - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208, - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209, - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210, - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221, - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222, - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223, - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224, - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225, - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226, - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215, - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217, + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219, + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220, + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205, + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207, + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209, + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210, + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221, + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222, + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223, + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224, + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225, + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215, + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644, @@ -4555,45 +4555,45 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874; reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398; - reg [22 : 0] CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82, - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83, - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86, - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87, - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88, - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89, - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119, - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120, - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49, - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50, - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117, - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118, - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47, - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48, - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121, - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122, - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51, - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52, - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123, - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124, - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53, - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54, - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84, - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85, - _theResult___fst_sfd__h346069, - _theResult___fst_sfd__h354792, - _theResult___fst_sfd__h363374, - _theResult___fst_sfd__h372558, - _theResult___fst_sfd__h381194, - _theResult___fst_sfd__h391768, - _theResult___fst_sfd__h400489, - _theResult___fst_sfd__h409071, - _theResult___fst_sfd__h418255, - _theResult___fst_sfd__h426891, - _theResult___fst_sfd__h437463, - _theResult___fst_sfd__h446184, - _theResult___fst_sfd__h454766, - _theResult___fst_sfd__h463950, - _theResult___fst_sfd__h472586; + reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82, + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83, + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86, + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87, + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88, + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89, + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119, + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49, + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50, + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117, + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47, + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48, + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121, + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122, + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51, + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52, + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123, + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124, + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53, + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84, + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85, + _theResult___fst_sfd__h346070, + _theResult___fst_sfd__h354793, + _theResult___fst_sfd__h363375, + _theResult___fst_sfd__h372559, + _theResult___fst_sfd__h381195, + _theResult___fst_sfd__h391769, + _theResult___fst_sfd__h400490, + _theResult___fst_sfd__h409072, + _theResult___fst_sfd__h418256, + _theResult___fst_sfd__h426892, + _theResult___fst_sfd__h437464, + _theResult___fst_sfd__h446185, + _theResult___fst_sfd__h454767, + _theResult___fst_sfd__h463951, + _theResult___fst_sfd__h472587; reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282, @@ -4622,24 +4622,24 @@ module mkCore(CLK, reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16, CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18, - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211, - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212, - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213, - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214, - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183, - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184, - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185, - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186, - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187, - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188, - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160, - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161, - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189, - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190, - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191, - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192, - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143, - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144, + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211, + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212, + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213, + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214, + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183, + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184, + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185, + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186, + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187, + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188, + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160, + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161, + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189, + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191, + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192, + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143, + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573, @@ -4649,47 +4649,47 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803; - reg [7 : 0] CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67, - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68, - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75, - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76, - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80, - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81, - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104, - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105, - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34, - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35, - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102, - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103, - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32, - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33, - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110, - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111, - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40, - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41, - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115, - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116, - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45, - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46, - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69, - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70, + reg [7 : 0] CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67, + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68, + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75, + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76, + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80, + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81, + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104, + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105, + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34, + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35, + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102, + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103, + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32, + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33, + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110, + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111, + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40, + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41, + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115, + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116, + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45, + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46, + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69, + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70, SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420, - _theResult___fst_exp__h346068, - _theResult___fst_exp__h354791, - _theResult___fst_exp__h363373, - _theResult___fst_exp__h372557, - _theResult___fst_exp__h381193, - _theResult___fst_exp__h391767, - _theResult___fst_exp__h400488, - _theResult___fst_exp__h409070, - _theResult___fst_exp__h418254, - _theResult___fst_exp__h426890, - _theResult___fst_exp__h437462, - _theResult___fst_exp__h446183, - _theResult___fst_exp__h454765, - _theResult___fst_exp__h463949, - _theResult___fst_exp__h472585; + _theResult___fst_exp__h346069, + _theResult___fst_exp__h354792, + _theResult___fst_exp__h363374, + _theResult___fst_exp__h372558, + _theResult___fst_exp__h381194, + _theResult___fst_exp__h391768, + _theResult___fst_exp__h400489, + _theResult___fst_exp__h409071, + _theResult___fst_exp__h418255, + _theResult___fst_exp__h426891, + _theResult___fst_exp__h437463, + _theResult___fst_exp__h446184, + _theResult___fst_exp__h454766, + _theResult___fst_exp__h463950, + _theResult___fst_exp__h472586; reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280, CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9, CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276, @@ -4712,8 +4712,8 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131, IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262, - i__h709458, - i__h709618; + i__h709459, + i__h709619; reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284, CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230, CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281, @@ -4727,8 +4727,8 @@ module mkCore(CLK, CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233, CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717, - x__h285847, - x__h291617; + x__h285848, + x__h291618; reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299, @@ -4766,46 +4766,46 @@ module mkCore(CLK, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238, CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242, - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93, + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92, + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149, + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95, + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94, + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147, + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97, + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96, + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203, + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193, + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127, + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125, + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199, + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195, + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56, + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55, + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128, + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126, + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201, + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197, + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58, + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57, + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130, + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129, + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60, + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59, + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132, + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131, + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172, + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162, + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62, + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61, + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168, + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164, + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170, + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166, + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91, + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90, + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145, + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459, IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463, @@ -4927,166 +4927,166 @@ module mkCore(CLK, IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425, IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8, IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191, - _theResult___fst__h603371, - _theResult___snd__h603372, - a___1__h603090, - a___1__h603376, - a__h602949, + _theResult___fst__h603372, + _theResult___snd__h603373, + a___1__h603091, + a___1__h603377, + a__h602950, amoExec___d880, - b___1__h603091, - b___1__h603421, - b__h602950, - base__h712403, - base__h712423, + b___1__h603092, + b___1__h603422, + b__h602951, + base__h712404, + base__h712424, commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15456, - data___1__h475009, - data___1__h475817, - data__h475283, - fcsr_csr__read__h609377, - fflags_csr__read__h609352, - frm_csr__read__h609363, - mcause_csr__read__h611019, - mcounteren_csr__read__h610764, - medeleg_csr__read__h610371, - mideleg_csr__read__h610466, - mie_csr__read__h610590, - mip_csr__read__h611252, - mstatus_csr__read__h610223, - mtvec_csr__read__h610672, - n___1__h198530, - n__h194455, - n__read__h611356, - n__read__h611547, - n__read__h6760, - n__read__h726694, - next_pc__h722452, - pc__h712387, - q___1__h475882, - rVal1__h481762, - rVal2__h481763, - r___1__h475908, - res_data__h337870, - res_data__h337875, - res_data__h383572, - res_data__h383577, - res_data__h429267, - res_data__h429272, - resp_addr__h291972, - rg_tdata1__read__h612207, + data___1__h475010, + data___1__h475818, + data__h475284, + fcsr_csr__read__h609378, + fflags_csr__read__h609353, + frm_csr__read__h609364, + mcause_csr__read__h611020, + mcounteren_csr__read__h610765, + medeleg_csr__read__h610372, + mideleg_csr__read__h610467, + mie_csr__read__h610591, + mip_csr__read__h611253, + mstatus_csr__read__h610224, + mtvec_csr__read__h610673, + n___1__h198531, + n__h194456, + n__read__h611357, + n__read__h611548, + n__read__h6761, + n__read__h726565, + next_pc__h722453, + pc__h712388, + q___1__h475883, + rVal1__h481763, + rVal2__h481764, + r___1__h475909, + res_data__h337871, + res_data__h337876, + res_data__h383573, + res_data__h383578, + res_data__h429268, + res_data__h429273, + resp_addr__h291973, + rg_tdata1__read__h612208, robdeqPort_0_deq_data_BITS_95_TO_32__q245, - satp_csr__read__h610080, - scause_csr__read__h609877, - scounteren_csr__read__h609739, - shiftData__h181568, - sie_csr__read__h609643, - sip_csr__read__h610017, - sstatus_csr__read__h609573, - stvec_csr__read__h609686, - trap_val__h709444, + satp_csr__read__h610081, + scause_csr__read__h609878, + scounteren_csr__read__h609740, + shiftData__h181569, + sie_csr__read__h609644, + sip_csr__read__h610018, + sstatus_csr__read__h609574, + stvec_csr__read__h609687, + trap_val__h709445, upd__h3994, upd__h5311, - upd__h6874, - upd__h726805, - v__h607935, - v__h632818, - x__h153732, - x__h157279, - x__h160093, - x__h161941, - x__h181477, + upd__h6875, + upd__h726676, + v__h607936, + v__h632819, + x__h153733, + x__h157280, + x__h160094, + x__h161942, x__h181478, - x__h18386, - x__h183903, - x__h20924, - x__h287292, - x__h289146, - x__h46293, - x__h481671, + x__h181479, + x__h18387, + x__h183904, + x__h20925, + x__h287293, + x__h289147, + x__h46294, x__h481672, x__h481673, - x__h48829, - x__h617232, + x__h481674, + x__h48830, x__h617233, - x__h639741, + x__h617234, x__h639742, - x__h702377, - x__h714645, - x__h714837, - x__h726188, - x__h729657, - x__h732802, - x_addr__h314075, - x_quotient__h475197, - x_reg_ifc__read__h609482, - x_remainder__h475198, - y__h730489, - y__h733310, - y_avValue__h180565, - y_avValue__h181171, - y_avValue__h478807, - y_avValue__h479415, - y_avValue__h480017, - y_avValue__h608841, - y_avValue__h615057, - y_avValue__h633571, - y_avValue__h637576, - y_avValue_new_pc__h712179, - y_avValue_new_pc__h712365, - y_avValue_snd_snd_snd_snd_snd_fst__h730512, - y_avValue_snd_snd_snd_snd_snd_fst__h733371, - y_avValue_snd_snd_snd_snd_snd_fst__h733407, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784; + x__h639743, + x__h702378, + x__h714646, + x__h714838, + x__h726059, + x__h729528, + x__h732673, + x_addr__h314076, + x_quotient__h475198, + x_reg_ifc__read__h609483, + x_remainder__h475199, + y__h730360, + y__h733181, + y_avValue__h180566, + y_avValue__h181172, + y_avValue__h478808, + y_avValue__h479416, + y_avValue__h480018, + y_avValue__h608842, + y_avValue__h615058, + y_avValue__h633572, + y_avValue__h637577, + y_avValue_new_pc__h712180, + y_avValue_new_pc__h712366, + y_avValue_snd_snd_snd_snd_snd_fst__h730383, + y_avValue_snd_snd_snd_snd_snd_fst__h733242, + y_avValue_snd_snd_snd_snd_snd_fst__h733278, + y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655; wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882, IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920, - r1__read__h613050, - r1__read__h613454, - r1__read__h613964, - r1__read__h613969, - r1__read__h613988, - r1__read__h614221, - r1__read__h614387, - r1__read__h614480, - r1__read__h614485, - r1__read__h614504; - wire [61 : 0] r1__read__h613052, - r1__read__h613456, - r1__read__h613971, - r1__read__h613990, - r1__read__h614223, - r1__read__h614363, - r1__read__h614389, - r1__read__h614487, - r1__read__h614506; - wire [60 : 0] r1__read__h614225, - r1__read__h614365, - r1__read__h614391, - r1__read__h614508; - wire [59 : 0] r1__read__h613054, - r1__read__h613458, - r1__read__h613982, - r1__read__h613992, - r1__read__h614227, - r1__read__h614393, - r1__read__h614498, - r1__read__h614510; - wire [58 : 0] r1__read__h613056, - r1__read__h613460, - r1__read__h613994, - r1__read__h614229, - r1__read__h614395, - r1__read__h614512; + r1__read__h613051, + r1__read__h613455, + r1__read__h613965, + r1__read__h613970, + r1__read__h613989, + r1__read__h614222, + r1__read__h614388, + r1__read__h614481, + r1__read__h614486, + r1__read__h614505; + wire [61 : 0] r1__read__h613053, + r1__read__h613457, + r1__read__h613972, + r1__read__h613991, + r1__read__h614224, + r1__read__h614364, + r1__read__h614390, + r1__read__h614488, + r1__read__h614507; + wire [60 : 0] r1__read__h614226, + r1__read__h614366, + r1__read__h614392, + r1__read__h614509; + wire [59 : 0] r1__read__h613055, + r1__read__h613459, + r1__read__h613983, + r1__read__h613993, + r1__read__h614228, + r1__read__h614394, + r1__read__h614499, + r1__read__h614511; + wire [58 : 0] r1__read__h613057, + r1__read__h613461, + r1__read__h613995, + r1__read__h614230, + r1__read__h614396, + r1__read__h614513; wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550, IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, - r1__read__h613058, - r1__read__h613462, - r1__read__h613996, - r1__read__h614231, - r1__read__h614367, - r1__read__h614397, - r1__read__h614514, - y__h254804; + r1__read__h613059, + r1__read__h613463, + r1__read__h613997, + r1__read__h614232, + r1__read__h614368, + r1__read__h614398, + r1__read__h614515, + y__h254805; wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63, IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98, @@ -5114,187 +5114,187 @@ module mkCore(CLK, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950, _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342, - _theResult____h346086, - _theResult____h363725, - _theResult____h391785, - _theResult____h409422, - _theResult____h437480, - _theResult____h455117, - _theResult____h502870, - _theResult____h541723, - _theResult____h581027, - _theResult___snd__h354208, - _theResult___snd__h354219, - _theResult___snd__h354221, - _theResult___snd__h354231, - _theResult___snd__h354237, - _theResult___snd__h354260, - _theResult___snd__h362804, - _theResult___snd__h362806, - _theResult___snd__h362813, - _theResult___snd__h362819, - _theResult___snd__h362842, - _theResult___snd__h371974, - _theResult___snd__h371985, - _theResult___snd__h371987, - _theResult___snd__h371997, - _theResult___snd__h372003, - _theResult___snd__h372026, - _theResult___snd__h380594, - _theResult___snd__h380608, - _theResult___snd__h380614, - _theResult___snd__h380632, - _theResult___snd__h399905, - _theResult___snd__h399916, - _theResult___snd__h399918, - _theResult___snd__h399928, - _theResult___snd__h399934, - _theResult___snd__h399957, - _theResult___snd__h408501, - _theResult___snd__h408503, - _theResult___snd__h408510, - _theResult___snd__h408516, - _theResult___snd__h408539, - _theResult___snd__h417671, - _theResult___snd__h417682, - _theResult___snd__h417684, - _theResult___snd__h417694, - _theResult___snd__h417700, - _theResult___snd__h417723, - _theResult___snd__h426291, - _theResult___snd__h426305, - _theResult___snd__h426311, - _theResult___snd__h426329, - _theResult___snd__h445600, - _theResult___snd__h445611, - _theResult___snd__h445613, - _theResult___snd__h445623, - _theResult___snd__h445629, - _theResult___snd__h445652, - _theResult___snd__h454196, - _theResult___snd__h454198, - _theResult___snd__h454205, - _theResult___snd__h454211, - _theResult___snd__h454234, - _theResult___snd__h463366, - _theResult___snd__h463377, - _theResult___snd__h463379, - _theResult___snd__h463389, - _theResult___snd__h463395, - _theResult___snd__h463418, - _theResult___snd__h471986, - _theResult___snd__h472000, - _theResult___snd__h472006, - _theResult___snd__h472024, - _theResult___snd__h501480, - _theResult___snd__h501482, - _theResult___snd__h501489, - _theResult___snd__h501495, - _theResult___snd__h501518, - _theResult___snd__h511117, - _theResult___snd__h511128, - _theResult___snd__h511130, - _theResult___snd__h511140, - _theResult___snd__h511146, - _theResult___snd__h511169, - _theResult___snd__h519885, - _theResult___snd__h519899, - _theResult___snd__h519905, - _theResult___snd__h519923, - _theResult___snd__h540333, - _theResult___snd__h540335, - _theResult___snd__h540342, - _theResult___snd__h540348, - _theResult___snd__h540371, - _theResult___snd__h549970, - _theResult___snd__h549981, - _theResult___snd__h549983, - _theResult___snd__h549993, - _theResult___snd__h549999, - _theResult___snd__h550022, - _theResult___snd__h558738, - _theResult___snd__h558752, - _theResult___snd__h558758, - _theResult___snd__h558776, - _theResult___snd__h579637, - _theResult___snd__h579639, - _theResult___snd__h579646, - _theResult___snd__h579652, - _theResult___snd__h579675, - _theResult___snd__h589274, - _theResult___snd__h589285, - _theResult___snd__h589287, - _theResult___snd__h589297, - _theResult___snd__h589303, - _theResult___snd__h589326, - _theResult___snd__h598042, - _theResult___snd__h598056, - _theResult___snd__h598062, - _theResult___snd__h598080, - r1__read__h614233, - r1__read__h614369, - r1__read__h614399, - r1__read__h614516, - result__h364338, - result__h410035, - result__h455730, - result__h503483, - result__h542336, - result__h581640, - sfd__h338481, - sfd__h384183, - sfd__h429878, - sfd__h482503, - sfd__h521497, - sfd__h560801, - sfdin__h354191, - sfdin__h371957, - sfdin__h399888, - sfdin__h417654, - sfdin__h445583, - sfdin__h463349, - sfdin__h511100, - sfdin__h549953, - sfdin__h589257, - x__h364435, - x__h410132, - x__h455827, - x__h503578, - x__h542431, - x__h581735; - wire [55 : 0] r1__read__h613060, - r1__read__h613464, - r1__read__h613998, - r1__read__h614235, - r1__read__h614401, - r1__read__h614518; - wire [54 : 0] r1__read__h613062, - r1__read__h613466, - r1__read__h614000, - r1__read__h614237, - r1__read__h614403, - r1__read__h614520; - wire [53 : 0] r1__read__h614346, - r1__read__h614371, - r1__read__h614405, - r1__read__h614522, - sfd__h501547, - sfd__h511198, - sfd__h519958, - sfd__h540400, - sfd__h550051, - sfd__h558811, - sfd__h579704, - sfd__h589355, - sfd__h598115, - value__h346708, - value__h392405, - value__h438100; - wire [52 : 0] r1__read__h614239, - r1__read__h614348, - r1__read__h614373, - r1__read__h614407, - r1__read__h614524; + _theResult____h346087, + _theResult____h363726, + _theResult____h391786, + _theResult____h409423, + _theResult____h437481, + _theResult____h455118, + _theResult____h502871, + _theResult____h541724, + _theResult____h581028, + _theResult___snd__h354209, + _theResult___snd__h354220, + _theResult___snd__h354222, + _theResult___snd__h354232, + _theResult___snd__h354238, + _theResult___snd__h354261, + _theResult___snd__h362805, + _theResult___snd__h362807, + _theResult___snd__h362814, + _theResult___snd__h362820, + _theResult___snd__h362843, + _theResult___snd__h371975, + _theResult___snd__h371986, + _theResult___snd__h371988, + _theResult___snd__h371998, + _theResult___snd__h372004, + _theResult___snd__h372027, + _theResult___snd__h380595, + _theResult___snd__h380609, + _theResult___snd__h380615, + _theResult___snd__h380633, + _theResult___snd__h399906, + _theResult___snd__h399917, + _theResult___snd__h399919, + _theResult___snd__h399929, + _theResult___snd__h399935, + _theResult___snd__h399958, + _theResult___snd__h408502, + _theResult___snd__h408504, + _theResult___snd__h408511, + _theResult___snd__h408517, + _theResult___snd__h408540, + _theResult___snd__h417672, + _theResult___snd__h417683, + _theResult___snd__h417685, + _theResult___snd__h417695, + _theResult___snd__h417701, + _theResult___snd__h417724, + _theResult___snd__h426292, + _theResult___snd__h426306, + _theResult___snd__h426312, + _theResult___snd__h426330, + _theResult___snd__h445601, + _theResult___snd__h445612, + _theResult___snd__h445614, + _theResult___snd__h445624, + _theResult___snd__h445630, + _theResult___snd__h445653, + _theResult___snd__h454197, + _theResult___snd__h454199, + _theResult___snd__h454206, + _theResult___snd__h454212, + _theResult___snd__h454235, + _theResult___snd__h463367, + _theResult___snd__h463378, + _theResult___snd__h463380, + _theResult___snd__h463390, + _theResult___snd__h463396, + _theResult___snd__h463419, + _theResult___snd__h471987, + _theResult___snd__h472001, + _theResult___snd__h472007, + _theResult___snd__h472025, + _theResult___snd__h501481, + _theResult___snd__h501483, + _theResult___snd__h501490, + _theResult___snd__h501496, + _theResult___snd__h501519, + _theResult___snd__h511118, + _theResult___snd__h511129, + _theResult___snd__h511131, + _theResult___snd__h511141, + _theResult___snd__h511147, + _theResult___snd__h511170, + _theResult___snd__h519886, + _theResult___snd__h519900, + _theResult___snd__h519906, + _theResult___snd__h519924, + _theResult___snd__h540334, + _theResult___snd__h540336, + _theResult___snd__h540343, + _theResult___snd__h540349, + _theResult___snd__h540372, + _theResult___snd__h549971, + _theResult___snd__h549982, + _theResult___snd__h549984, + _theResult___snd__h549994, + _theResult___snd__h550000, + _theResult___snd__h550023, + _theResult___snd__h558739, + _theResult___snd__h558753, + _theResult___snd__h558759, + _theResult___snd__h558777, + _theResult___snd__h579638, + _theResult___snd__h579640, + _theResult___snd__h579647, + _theResult___snd__h579653, + _theResult___snd__h579676, + _theResult___snd__h589275, + _theResult___snd__h589286, + _theResult___snd__h589288, + _theResult___snd__h589298, + _theResult___snd__h589304, + _theResult___snd__h589327, + _theResult___snd__h598043, + _theResult___snd__h598057, + _theResult___snd__h598063, + _theResult___snd__h598081, + r1__read__h614234, + r1__read__h614370, + r1__read__h614400, + r1__read__h614517, + result__h364339, + result__h410036, + result__h455731, + result__h503484, + result__h542337, + result__h581641, + sfd__h338482, + sfd__h384184, + sfd__h429879, + sfd__h482504, + sfd__h521498, + sfd__h560802, + sfdin__h354192, + sfdin__h371958, + sfdin__h399889, + sfdin__h417655, + sfdin__h445584, + sfdin__h463350, + sfdin__h511101, + sfdin__h549954, + sfdin__h589258, + x__h364436, + x__h410133, + x__h455828, + x__h503579, + x__h542432, + x__h581736; + wire [55 : 0] r1__read__h613061, + r1__read__h613465, + r1__read__h613999, + r1__read__h614236, + r1__read__h614402, + r1__read__h614519; + wire [54 : 0] r1__read__h613063, + r1__read__h613467, + r1__read__h614001, + r1__read__h614238, + r1__read__h614404, + r1__read__h614521; + wire [53 : 0] r1__read__h614347, + r1__read__h614372, + r1__read__h614406, + r1__read__h614523, + sfd__h501548, + sfd__h511199, + sfd__h519959, + sfd__h540401, + sfd__h550052, + sfd__h558812, + sfd__h579705, + sfd__h589356, + sfd__h598116, + value__h346709, + value__h392406, + value__h438101; + wire [52 : 0] r1__read__h614240, + r1__read__h614349, + r1__read__h614374, + r1__read__h614408, + r1__read__h614525; wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140, @@ -5316,111 +5316,111 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881, - _theResult___fst_sfd__h486457, - _theResult___fst_sfd__h502285, - _theResult___fst_sfd__h502288, - _theResult___fst_sfd__h511936, - _theResult___fst_sfd__h511939, - _theResult___fst_sfd__h520720, - _theResult___fst_sfd__h520723, - _theResult___fst_sfd__h520732, - _theResult___fst_sfd__h520738, - _theResult___fst_sfd__h525310, - _theResult___fst_sfd__h541138, - _theResult___fst_sfd__h541141, - _theResult___fst_sfd__h550789, - _theResult___fst_sfd__h550792, - _theResult___fst_sfd__h559573, - _theResult___fst_sfd__h559576, - _theResult___fst_sfd__h559585, - _theResult___fst_sfd__h559591, - _theResult___fst_sfd__h564614, - _theResult___fst_sfd__h580442, - _theResult___fst_sfd__h580445, - _theResult___fst_sfd__h590093, - _theResult___fst_sfd__h590096, - _theResult___fst_sfd__h598877, - _theResult___fst_sfd__h598880, - _theResult___fst_sfd__h598889, - _theResult___fst_sfd__h598895, - _theResult___sfd__h502185, - _theResult___sfd__h511836, - _theResult___sfd__h520620, - _theResult___sfd__h541038, - _theResult___sfd__h550689, - _theResult___sfd__h559473, - _theResult___sfd__h580342, - _theResult___sfd__h589993, - _theResult___sfd__h598777, - _theResult___snd_fst_sfd__h482457, - _theResult___snd_fst_sfd__h502291, - _theResult___snd_fst_sfd__h520726, - _theResult___snd_fst_sfd__h521451, - _theResult___snd_fst_sfd__h541144, - _theResult___snd_fst_sfd__h559579, - _theResult___snd_fst_sfd__h560755, - _theResult___snd_fst_sfd__h580448, - _theResult___snd_fst_sfd__h598883, - out___1_sfd__h482205, - out___1_sfd__h521199, - out___1_sfd__h560503, - out_sfd__h502188, - out_sfd__h511839, - out_sfd__h520623, - out_sfd__h541041, - out_sfd__h550692, - out_sfd__h559476, - out_sfd__h580345, - out_sfd__h589996, - out_sfd__h598780; - wire [50 : 0] r1__read__h613064, r1__read__h614241; - wire [49 : 0] r1__read__h614350; - wire [48 : 0] r1__read_BITS_62_TO_14___h729677, - r1__read__h613066, - r1__read__h614352; - wire [46 : 0] r1__read__h613068, r1__read__h614245; - wire [45 : 0] r1__read__h613070, r1__read__h614247; - wire [44 : 0] r1__read__h613072, r1__read__h614249; - wire [43 : 0] r1__read__h613074, r1__read__h614251; - wire [42 : 0] r1__read__h614253; - wire [41 : 0] r1__read__h614255; - wire [40 : 0] r1__read__h614257; + _theResult___fst_sfd__h486458, + _theResult___fst_sfd__h502286, + _theResult___fst_sfd__h502289, + _theResult___fst_sfd__h511937, + _theResult___fst_sfd__h511940, + _theResult___fst_sfd__h520721, + _theResult___fst_sfd__h520724, + _theResult___fst_sfd__h520733, + _theResult___fst_sfd__h520739, + _theResult___fst_sfd__h525311, + _theResult___fst_sfd__h541139, + _theResult___fst_sfd__h541142, + _theResult___fst_sfd__h550790, + _theResult___fst_sfd__h550793, + _theResult___fst_sfd__h559574, + _theResult___fst_sfd__h559577, + _theResult___fst_sfd__h559586, + _theResult___fst_sfd__h559592, + _theResult___fst_sfd__h564615, + _theResult___fst_sfd__h580443, + _theResult___fst_sfd__h580446, + _theResult___fst_sfd__h590094, + _theResult___fst_sfd__h590097, + _theResult___fst_sfd__h598878, + _theResult___fst_sfd__h598881, + _theResult___fst_sfd__h598890, + _theResult___fst_sfd__h598896, + _theResult___sfd__h502186, + _theResult___sfd__h511837, + _theResult___sfd__h520621, + _theResult___sfd__h541039, + _theResult___sfd__h550690, + _theResult___sfd__h559474, + _theResult___sfd__h580343, + _theResult___sfd__h589994, + _theResult___sfd__h598778, + _theResult___snd_fst_sfd__h482458, + _theResult___snd_fst_sfd__h502292, + _theResult___snd_fst_sfd__h520727, + _theResult___snd_fst_sfd__h521452, + _theResult___snd_fst_sfd__h541145, + _theResult___snd_fst_sfd__h559580, + _theResult___snd_fst_sfd__h560756, + _theResult___snd_fst_sfd__h580449, + _theResult___snd_fst_sfd__h598884, + out___1_sfd__h482206, + out___1_sfd__h521200, + out___1_sfd__h560504, + out_sfd__h502189, + out_sfd__h511840, + out_sfd__h520624, + out_sfd__h541042, + out_sfd__h550693, + out_sfd__h559477, + out_sfd__h580346, + out_sfd__h589997, + out_sfd__h598781; + wire [50 : 0] r1__read__h613065, r1__read__h614242; + wire [49 : 0] r1__read__h614351; + wire [48 : 0] r1__read_BITS_62_TO_14___h729548, + r1__read__h613067, + r1__read__h614353; + wire [46 : 0] r1__read__h613069, r1__read__h614246; + wire [45 : 0] r1__read__h613071, r1__read__h614248; + wire [44 : 0] r1__read__h613073, r1__read__h614250; + wire [43 : 0] r1__read__h613075, r1__read__h614252; + wire [42 : 0] r1__read__h614254; + wire [41 : 0] r1__read__h614256; + wire [40 : 0] r1__read__h614258; wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14134, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265; wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10, - data75283_BITS_31_TO_0__q13, - imm__h655329, - r1__read__h613076, - r1__read__h614259, - x__h193680, - x__h337885, - x__h383587, - x__h429282, - x__h76238, - x_data__h66087, - x_data_imm__h676657, - x_data_imm__h692711; - wire [29 : 0] r1__read__h613078, r1__read__h614261; - wire [27 : 0] r1__read__h614263; + data75284_BITS_31_TO_0__q13, + imm__h655330, + r1__read__h613077, + r1__read__h614260, + x__h193681, + x__h337886, + x__h383588, + x__h429283, + x__h76239, + x_data__h66088, + x_data_imm__h676658, + x_data_imm__h692712; + wire [29 : 0] r1__read__h613079, r1__read__h614262; + wire [27 : 0] r1__read__h614264; wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14166, - sfd__h354289, - sfd__h362871, - sfd__h372055, - sfd__h380667, - sfd__h399986, - sfd__h408568, - sfd__h417752, - sfd__h426364, - sfd__h445681, - sfd__h454263, - sfd__h463447, - sfd__h472059, - value__h487086, - value__h525939, - value__h565243; + sfd__h354290, + sfd__h362872, + sfd__h372056, + sfd__h380668, + sfd__h399987, + sfd__h408569, + sfd__h417753, + sfd__h426365, + sfd__h445682, + sfd__h454264, + sfd__h463448, + sfd__h472060, + value__h487087, + value__h525940, + value__h565244; wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959, IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349, @@ -5445,74 +5445,74 @@ module mkCore(CLK, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806, IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808, - _theResult___fst_sfd__h354795, - _theResult___fst_sfd__h363377, - _theResult___fst_sfd__h372561, - _theResult___fst_sfd__h381197, - _theResult___fst_sfd__h381206, - _theResult___fst_sfd__h381212, - _theResult___fst_sfd__h400492, - _theResult___fst_sfd__h409074, - _theResult___fst_sfd__h418258, - _theResult___fst_sfd__h426894, - _theResult___fst_sfd__h426903, - _theResult___fst_sfd__h426909, - _theResult___fst_sfd__h446187, - _theResult___fst_sfd__h454769, - _theResult___fst_sfd__h463953, - _theResult___fst_sfd__h472589, - _theResult___fst_sfd__h472598, - _theResult___fst_sfd__h472604, - _theResult___sfd__h354714, - _theResult___sfd__h363296, - _theResult___sfd__h372480, - _theResult___sfd__h381116, - _theResult___sfd__h381218, - _theResult___sfd__h400411, - _theResult___sfd__h408993, - _theResult___sfd__h418177, - _theResult___sfd__h426813, - _theResult___sfd__h426915, - _theResult___sfd__h446106, - _theResult___sfd__h454688, - _theResult___sfd__h463872, - _theResult___sfd__h472508, - _theResult___sfd__h472610, - _theResult___snd_fst_sfd__h338431, - _theResult___snd_fst_sfd__h363380, - _theResult___snd_fst_sfd__h381200, - _theResult___snd_fst_sfd__h384133, - _theResult___snd_fst_sfd__h409077, - _theResult___snd_fst_sfd__h426897, - _theResult___snd_fst_sfd__h429828, - _theResult___snd_fst_sfd__h454772, - _theResult___snd_fst_sfd__h472592, - f1_sfd__h482142, - f2_sfd__h521136, - f3_sfd__h560440, - out_f_sfd__h381495, - out_f_sfd__h427192, - out_f_sfd__h472887, - out_sfd__h354717, - out_sfd__h363299, - out_sfd__h372483, - out_sfd__h381119, - out_sfd__h400414, - out_sfd__h408996, - out_sfd__h418180, - out_sfd__h426816, - out_sfd__h446109, - out_sfd__h454691, - out_sfd__h463875, - out_sfd__h472511; - wire [19 : 0] r1__read__h614198; + _theResult___fst_sfd__h354796, + _theResult___fst_sfd__h363378, + _theResult___fst_sfd__h372562, + _theResult___fst_sfd__h381198, + _theResult___fst_sfd__h381207, + _theResult___fst_sfd__h381213, + _theResult___fst_sfd__h400493, + _theResult___fst_sfd__h409075, + _theResult___fst_sfd__h418259, + _theResult___fst_sfd__h426895, + _theResult___fst_sfd__h426904, + _theResult___fst_sfd__h426910, + _theResult___fst_sfd__h446188, + _theResult___fst_sfd__h454770, + _theResult___fst_sfd__h463954, + _theResult___fst_sfd__h472590, + _theResult___fst_sfd__h472599, + _theResult___fst_sfd__h472605, + _theResult___sfd__h354715, + _theResult___sfd__h363297, + _theResult___sfd__h372481, + _theResult___sfd__h381117, + _theResult___sfd__h381219, + _theResult___sfd__h400412, + _theResult___sfd__h408994, + _theResult___sfd__h418178, + _theResult___sfd__h426814, + _theResult___sfd__h426916, + _theResult___sfd__h446107, + _theResult___sfd__h454689, + _theResult___sfd__h463873, + _theResult___sfd__h472509, + _theResult___sfd__h472611, + _theResult___snd_fst_sfd__h338432, + _theResult___snd_fst_sfd__h363381, + _theResult___snd_fst_sfd__h381201, + _theResult___snd_fst_sfd__h384134, + _theResult___snd_fst_sfd__h409078, + _theResult___snd_fst_sfd__h426898, + _theResult___snd_fst_sfd__h429829, + _theResult___snd_fst_sfd__h454773, + _theResult___snd_fst_sfd__h472593, + f1_sfd__h482143, + f2_sfd__h521137, + f3_sfd__h560441, + out_f_sfd__h381496, + out_f_sfd__h427193, + out_f_sfd__h472888, + out_sfd__h354718, + out_sfd__h363300, + out_sfd__h372484, + out_sfd__h381120, + out_sfd__h400415, + out_sfd__h408997, + out_sfd__h418181, + out_sfd__h426817, + out_sfd__h446110, + out_sfd__h454692, + out_sfd__h463876, + out_sfd__h472512; + wire [19 : 0] r1__read__h614199; wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824, - _theResult____h651118, - enabled_ints___1__h651643, - enabled_ints__h651689, - pend_ints__h651116, - y__h651655; - wire [13 : 0] r1__read_BITS_13_TO_0___h651665; + _theResult____h651119, + enabled_ints___1__h651644, + enabled_ints__h651690, + pend_ints__h651117, + y__h651656; + wire [13 : 0] r1__read_BITS_13_TO_0___h651666; wire [12 : 0] IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15288, fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505; @@ -5545,25 +5545,25 @@ module mkCore(CLK, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946, _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338, - csr_addr__h655327, - renaming_spec_bits__h685239, - result__h646695, - result__h646746, - spec_bits__h688398, - w__h646690, - x__h364468, - x__h410165, - x__h455860, - x__h503611, - x__h542464, - x__h581768, - x__h646694, - x__h646745, - y__h646724, - y__h688411, - y_avValue_fst__h681571, - y_avValue_fst__h681600, - y_avValue_fst__h681634; + csr_addr__h655328, + renaming_spec_bits__h685240, + result__h646696, + result__h646747, + spec_bits__h688399, + w__h646691, + x__h364469, + x__h410166, + x__h455861, + x__h503612, + x__h542465, + x__h581769, + x__h646695, + x__h646746, + y__h646725, + y__h688412, + y_avValue_fst__h681572, + y_avValue_fst__h681601, + y_avValue_fst__h681635; wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056, @@ -5585,102 +5585,102 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180, - _theResult___exp__h502184, - _theResult___exp__h511835, - _theResult___exp__h520619, - _theResult___exp__h541037, - _theResult___exp__h550688, - _theResult___exp__h559472, - _theResult___exp__h580341, - _theResult___exp__h589992, - _theResult___exp__h598776, - _theResult___fst_exp__h486456, - _theResult___fst_exp__h501520, - _theResult___fst_exp__h501526, - _theResult___fst_exp__h501529, - _theResult___fst_exp__h502284, - _theResult___fst_exp__h502287, - _theResult___fst_exp__h511106, - _theResult___fst_exp__h511171, - _theResult___fst_exp__h511177, - _theResult___fst_exp__h511180, - _theResult___fst_exp__h511935, - _theResult___fst_exp__h511938, - _theResult___fst_exp__h519891, - _theResult___fst_exp__h519930, - _theResult___fst_exp__h519936, - _theResult___fst_exp__h519939, - _theResult___fst_exp__h520719, - _theResult___fst_exp__h520722, - _theResult___fst_exp__h520731, - _theResult___fst_exp__h520734, - _theResult___fst_exp__h525309, - _theResult___fst_exp__h540373, - _theResult___fst_exp__h540379, - _theResult___fst_exp__h540382, - _theResult___fst_exp__h541137, - _theResult___fst_exp__h541140, - _theResult___fst_exp__h549959, - _theResult___fst_exp__h550024, - _theResult___fst_exp__h550030, - _theResult___fst_exp__h550033, - _theResult___fst_exp__h550788, - _theResult___fst_exp__h550791, - _theResult___fst_exp__h558744, - _theResult___fst_exp__h558783, - _theResult___fst_exp__h558789, - _theResult___fst_exp__h558792, - _theResult___fst_exp__h559572, - _theResult___fst_exp__h559575, - _theResult___fst_exp__h559584, - _theResult___fst_exp__h559587, - _theResult___fst_exp__h564613, - _theResult___fst_exp__h579677, - _theResult___fst_exp__h579683, - _theResult___fst_exp__h579686, - _theResult___fst_exp__h580441, - _theResult___fst_exp__h580444, - _theResult___fst_exp__h589263, - _theResult___fst_exp__h589328, - _theResult___fst_exp__h589334, - _theResult___fst_exp__h589337, - _theResult___fst_exp__h590092, - _theResult___fst_exp__h590095, - _theResult___fst_exp__h598048, - _theResult___fst_exp__h598087, - _theResult___fst_exp__h598093, - _theResult___fst_exp__h598096, - _theResult___fst_exp__h598876, - _theResult___fst_exp__h598879, - _theResult___fst_exp__h598888, - _theResult___fst_exp__h598891, - _theResult___snd_fst_exp__h502290, - _theResult___snd_fst_exp__h520725, - _theResult___snd_fst_exp__h541143, - _theResult___snd_fst_exp__h559578, - _theResult___snd_fst_exp__h580447, - _theResult___snd_fst_exp__h598882, + _theResult___exp__h502185, + _theResult___exp__h511836, + _theResult___exp__h520620, + _theResult___exp__h541038, + _theResult___exp__h550689, + _theResult___exp__h559473, + _theResult___exp__h580342, + _theResult___exp__h589993, + _theResult___exp__h598777, + _theResult___fst_exp__h486457, + _theResult___fst_exp__h501521, + _theResult___fst_exp__h501527, + _theResult___fst_exp__h501530, + _theResult___fst_exp__h502285, + _theResult___fst_exp__h502288, + _theResult___fst_exp__h511107, + _theResult___fst_exp__h511172, + _theResult___fst_exp__h511178, + _theResult___fst_exp__h511181, + _theResult___fst_exp__h511936, + _theResult___fst_exp__h511939, + _theResult___fst_exp__h519892, + _theResult___fst_exp__h519931, + _theResult___fst_exp__h519937, + _theResult___fst_exp__h519940, + _theResult___fst_exp__h520720, + _theResult___fst_exp__h520723, + _theResult___fst_exp__h520732, + _theResult___fst_exp__h520735, + _theResult___fst_exp__h525310, + _theResult___fst_exp__h540374, + _theResult___fst_exp__h540380, + _theResult___fst_exp__h540383, + _theResult___fst_exp__h541138, + _theResult___fst_exp__h541141, + _theResult___fst_exp__h549960, + _theResult___fst_exp__h550025, + _theResult___fst_exp__h550031, + _theResult___fst_exp__h550034, + _theResult___fst_exp__h550789, + _theResult___fst_exp__h550792, + _theResult___fst_exp__h558745, + _theResult___fst_exp__h558784, + _theResult___fst_exp__h558790, + _theResult___fst_exp__h558793, + _theResult___fst_exp__h559573, + _theResult___fst_exp__h559576, + _theResult___fst_exp__h559585, + _theResult___fst_exp__h559588, + _theResult___fst_exp__h564614, + _theResult___fst_exp__h579678, + _theResult___fst_exp__h579684, + _theResult___fst_exp__h579687, + _theResult___fst_exp__h580442, + _theResult___fst_exp__h580445, + _theResult___fst_exp__h589264, + _theResult___fst_exp__h589329, + _theResult___fst_exp__h589335, + _theResult___fst_exp__h589338, + _theResult___fst_exp__h590093, + _theResult___fst_exp__h590096, + _theResult___fst_exp__h598049, + _theResult___fst_exp__h598088, + _theResult___fst_exp__h598094, + _theResult___fst_exp__h598097, + _theResult___fst_exp__h598877, + _theResult___fst_exp__h598880, + _theResult___fst_exp__h598889, + _theResult___fst_exp__h598892, + _theResult___snd_fst_exp__h502291, + _theResult___snd_fst_exp__h520726, + _theResult___snd_fst_exp__h541144, + _theResult___snd_fst_exp__h559579, + _theResult___snd_fst_exp__h580448, + _theResult___snd_fst_exp__h598883, coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71, coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36, coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106, - din_inc___2_exp__h520779, - din_inc___2_exp__h520814, - din_inc___2_exp__h520840, - din_inc___2_exp__h559632, - din_inc___2_exp__h559667, - din_inc___2_exp__h559693, - din_inc___2_exp__h598936, - din_inc___2_exp__h598971, - din_inc___2_exp__h598997, - out_exp__h502187, - out_exp__h511838, - out_exp__h520622, - out_exp__h541040, - out_exp__h550691, - out_exp__h559475, - out_exp__h580344, - out_exp__h589995, - out_exp__h598779; + din_inc___2_exp__h520780, + din_inc___2_exp__h520815, + din_inc___2_exp__h520841, + din_inc___2_exp__h559633, + din_inc___2_exp__h559668, + din_inc___2_exp__h559694, + din_inc___2_exp__h598937, + din_inc___2_exp__h598972, + din_inc___2_exp__h598998, + out_exp__h502188, + out_exp__h511839, + out_exp__h520623, + out_exp__h541041, + out_exp__h550692, + out_exp__h559476, + out_exp__h580345, + out_exp__h589996, + out_exp__h598780; wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264, IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656; @@ -5711,124 +5711,124 @@ module mkCore(CLK, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42, SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112, - _theResult___exp__h354713, - _theResult___exp__h363295, - _theResult___exp__h372479, - _theResult___exp__h381115, - _theResult___exp__h381217, - _theResult___exp__h400410, - _theResult___exp__h408992, - _theResult___exp__h418176, - _theResult___exp__h426812, - _theResult___exp__h426914, - _theResult___exp__h446105, - _theResult___exp__h454687, - _theResult___exp__h463871, - _theResult___exp__h472507, - _theResult___exp__h472609, - _theResult___fst_exp__h354197, - _theResult___fst_exp__h354262, - _theResult___fst_exp__h354268, - _theResult___fst_exp__h354271, - _theResult___fst_exp__h354794, - _theResult___fst_exp__h362844, - _theResult___fst_exp__h362850, - _theResult___fst_exp__h362853, - _theResult___fst_exp__h363376, - _theResult___fst_exp__h371963, - _theResult___fst_exp__h372028, - _theResult___fst_exp__h372034, - _theResult___fst_exp__h372037, - _theResult___fst_exp__h372560, - _theResult___fst_exp__h380600, - _theResult___fst_exp__h380639, - _theResult___fst_exp__h380645, - _theResult___fst_exp__h380648, - _theResult___fst_exp__h381196, - _theResult___fst_exp__h381205, - _theResult___fst_exp__h381208, - _theResult___fst_exp__h399894, - _theResult___fst_exp__h399959, - _theResult___fst_exp__h399965, - _theResult___fst_exp__h399968, - _theResult___fst_exp__h400491, - _theResult___fst_exp__h408541, - _theResult___fst_exp__h408547, - _theResult___fst_exp__h408550, - _theResult___fst_exp__h409073, - _theResult___fst_exp__h417660, - _theResult___fst_exp__h417725, - _theResult___fst_exp__h417731, - _theResult___fst_exp__h417734, - _theResult___fst_exp__h418257, - _theResult___fst_exp__h426297, - _theResult___fst_exp__h426336, - _theResult___fst_exp__h426342, - _theResult___fst_exp__h426345, - _theResult___fst_exp__h426893, - _theResult___fst_exp__h426902, - _theResult___fst_exp__h426905, - _theResult___fst_exp__h445589, - _theResult___fst_exp__h445654, - _theResult___fst_exp__h445660, - _theResult___fst_exp__h445663, - _theResult___fst_exp__h446186, - _theResult___fst_exp__h454236, - _theResult___fst_exp__h454242, - _theResult___fst_exp__h454245, - _theResult___fst_exp__h454768, - _theResult___fst_exp__h463355, - _theResult___fst_exp__h463420, - _theResult___fst_exp__h463426, - _theResult___fst_exp__h463429, - _theResult___fst_exp__h463952, - _theResult___fst_exp__h471992, - _theResult___fst_exp__h472031, - _theResult___fst_exp__h472037, - _theResult___fst_exp__h472040, - _theResult___fst_exp__h472588, - _theResult___fst_exp__h472597, - _theResult___fst_exp__h472600, - _theResult___snd_fst_exp__h363379, - _theResult___snd_fst_exp__h381199, - _theResult___snd_fst_exp__h409076, - _theResult___snd_fst_exp__h426896, - _theResult___snd_fst_exp__h454771, - _theResult___snd_fst_exp__h472591, - din_inc___2_exp__h381230, - din_inc___2_exp__h381254, - din_inc___2_exp__h381284, - din_inc___2_exp__h381308, - din_inc___2_exp__h426927, - din_inc___2_exp__h426951, - din_inc___2_exp__h426981, - din_inc___2_exp__h427005, - din_inc___2_exp__h472622, - din_inc___2_exp__h472646, - din_inc___2_exp__h472676, - din_inc___2_exp__h472700, - f1_exp82141_MINUS_127__q136, - f1_exp__h482141, - f2_exp21135_MINUS_127__q176, - f2_exp__h521135, - f3_exp60439_MINUS_127__q153, - f3_exp__h560439, - out_exp__h354716, - out_exp__h363298, - out_exp__h372482, - out_exp__h381118, - out_exp__h400413, - out_exp__h408995, - out_exp__h418179, - out_exp__h426815, - out_exp__h446108, - out_exp__h454690, - out_exp__h463874, - out_exp__h472510, - out_f_exp__h381494, - out_f_exp__h427191, - out_f_exp__h472886, - x__h613035; + _theResult___exp__h354714, + _theResult___exp__h363296, + _theResult___exp__h372480, + _theResult___exp__h381116, + _theResult___exp__h381218, + _theResult___exp__h400411, + _theResult___exp__h408993, + _theResult___exp__h418177, + _theResult___exp__h426813, + _theResult___exp__h426915, + _theResult___exp__h446106, + _theResult___exp__h454688, + _theResult___exp__h463872, + _theResult___exp__h472508, + _theResult___exp__h472610, + _theResult___fst_exp__h354198, + _theResult___fst_exp__h354263, + _theResult___fst_exp__h354269, + _theResult___fst_exp__h354272, + _theResult___fst_exp__h354795, + _theResult___fst_exp__h362845, + _theResult___fst_exp__h362851, + _theResult___fst_exp__h362854, + _theResult___fst_exp__h363377, + _theResult___fst_exp__h371964, + _theResult___fst_exp__h372029, + _theResult___fst_exp__h372035, + _theResult___fst_exp__h372038, + _theResult___fst_exp__h372561, + _theResult___fst_exp__h380601, + _theResult___fst_exp__h380640, + _theResult___fst_exp__h380646, + _theResult___fst_exp__h380649, + _theResult___fst_exp__h381197, + _theResult___fst_exp__h381206, + _theResult___fst_exp__h381209, + _theResult___fst_exp__h399895, + _theResult___fst_exp__h399960, + _theResult___fst_exp__h399966, + _theResult___fst_exp__h399969, + _theResult___fst_exp__h400492, + _theResult___fst_exp__h408542, + _theResult___fst_exp__h408548, + _theResult___fst_exp__h408551, + _theResult___fst_exp__h409074, + _theResult___fst_exp__h417661, + _theResult___fst_exp__h417726, + _theResult___fst_exp__h417732, + _theResult___fst_exp__h417735, + _theResult___fst_exp__h418258, + _theResult___fst_exp__h426298, + _theResult___fst_exp__h426337, + _theResult___fst_exp__h426343, + _theResult___fst_exp__h426346, + _theResult___fst_exp__h426894, + _theResult___fst_exp__h426903, + _theResult___fst_exp__h426906, + _theResult___fst_exp__h445590, + _theResult___fst_exp__h445655, + _theResult___fst_exp__h445661, + _theResult___fst_exp__h445664, + _theResult___fst_exp__h446187, + _theResult___fst_exp__h454237, + _theResult___fst_exp__h454243, + _theResult___fst_exp__h454246, + _theResult___fst_exp__h454769, + _theResult___fst_exp__h463356, + _theResult___fst_exp__h463421, + _theResult___fst_exp__h463427, + _theResult___fst_exp__h463430, + _theResult___fst_exp__h463953, + _theResult___fst_exp__h471993, + _theResult___fst_exp__h472032, + _theResult___fst_exp__h472038, + _theResult___fst_exp__h472041, + _theResult___fst_exp__h472589, + _theResult___fst_exp__h472598, + _theResult___fst_exp__h472601, + _theResult___snd_fst_exp__h363380, + _theResult___snd_fst_exp__h381200, + _theResult___snd_fst_exp__h409077, + _theResult___snd_fst_exp__h426897, + _theResult___snd_fst_exp__h454772, + _theResult___snd_fst_exp__h472592, + din_inc___2_exp__h381231, + din_inc___2_exp__h381255, + din_inc___2_exp__h381285, + din_inc___2_exp__h381309, + din_inc___2_exp__h426928, + din_inc___2_exp__h426952, + din_inc___2_exp__h426982, + din_inc___2_exp__h427006, + din_inc___2_exp__h472623, + din_inc___2_exp__h472647, + din_inc___2_exp__h472677, + din_inc___2_exp__h472701, + f1_exp82142_MINUS_127__q136, + f1_exp__h482142, + f2_exp21136_MINUS_127__q176, + f2_exp__h521136, + f3_exp60440_MINUS_127__q153, + f3_exp__h560440, + out_exp__h354717, + out_exp__h363299, + out_exp__h372483, + out_exp__h381119, + out_exp__h400414, + out_exp__h408996, + out_exp__h418180, + out_exp__h426816, + out_exp__h446109, + out_exp__h454691, + out_exp__h463875, + out_exp__h472511, + out_f_exp__h381495, + out_f_exp__h427192, + out_f_exp__h472887, + x__h613036; wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031, @@ -5849,8 +5849,8 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262, IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16102, - x__h181700, - x__h712418; + x__h181701, + x__h712419; wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670, _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169, @@ -5870,25 +5870,25 @@ module mkCore(CLK, _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965, checkForException___d13008, checkForException___d13698, - fflags__h728014, - fflags__h730667, - fflags__h733287, - old_fflags__h732774, - po_fflags__h727999, - po_fflags__h730652, - r1__read__h614601, - res_fflags__h337871, - res_fflags__h383573, - res_fflags__h429268, + fflags__h727885, + fflags__h730538, + fflags__h733158, + old_fflags__h732645, + po_fflags__h727870, + po_fflags__h730523, + r1__read__h614602, + res_fflags__h337872, + res_fflags__h383574, + res_fflags__h429269, rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, - rs1__h655328, - x__h153726, - x__h157273, - x__h160089, - x__h287280, - y_avValue_fst__h730027, - y_avValue_fst__h733192, - y_avValue_fst__h733224; + rs1__h655329, + x__h153727, + x__h157274, + x__h160090, + x__h287281, + y_avValue_fst__h729898, + y_avValue_fst__h733063, + y_avValue_fst__h733095; wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853, IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855, @@ -5915,77 +5915,77 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, - cause_code__h709443, - vm_mode_reg__read__h614204; + cause_code__h709444, + vm_mode_reg__read__h614205; wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, - _theResult_____2__h296522, - dcsr_cause__h708962, - next_deqP___1__h296801, - v__h295942, - v__h296173, - x__h302152, - x_decodeInfo_frm__h655012; + _theResult_____2__h296523, + dcsr_cause__h708963, + next_deqP___1__h296802, + v__h295943, + v__h296174, + x__h302153, + x_decodeInfo_frm__h655013; wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689, - IF_sfdin11100_BIT_4_THEN_2_ELSE_0__q139, - IF_sfdin17654_BIT_33_THEN_2_ELSE_0__q74, - IF_sfdin45583_BIT_33_THEN_2_ELSE_0__q99, - IF_sfdin49953_BIT_4_THEN_2_ELSE_0__q179, - IF_sfdin54191_BIT_33_THEN_2_ELSE_0__q29, - IF_sfdin63349_BIT_33_THEN_2_ELSE_0__q109, - IF_sfdin71957_BIT_33_THEN_2_ELSE_0__q39, - IF_sfdin89257_BIT_4_THEN_2_ELSE_0__q156, - IF_sfdin99888_BIT_33_THEN_2_ELSE_0__q64, - IF_theResult___snd01480_BIT_4_THEN_2_ELSE_0__q135, - IF_theResult___snd08501_BIT_33_THEN_2_ELSE_0__q66, - IF_theResult___snd19885_BIT_4_THEN_2_ELSE_0__q142, - IF_theResult___snd26291_BIT_33_THEN_2_ELSE_0__q79, - IF_theResult___snd40333_BIT_4_THEN_2_ELSE_0__q175, - IF_theResult___snd54196_BIT_33_THEN_2_ELSE_0__q101, - IF_theResult___snd58738_BIT_4_THEN_2_ELSE_0__q182, - IF_theResult___snd62804_BIT_33_THEN_2_ELSE_0__q31, - IF_theResult___snd71986_BIT_33_THEN_2_ELSE_0__q114, - IF_theResult___snd79637_BIT_4_THEN_2_ELSE_0__q152, - IF_theResult___snd80594_BIT_33_THEN_2_ELSE_0__q44, - IF_theResult___snd98042_BIT_4_THEN_2_ELSE_0__q159, - guard__h346096, - guard__h354805, - guard__h363735, - guard__h372571, - guard__h391795, - guard__h400502, - guard__h409432, - guard__h418268, - guard__h437490, - guard__h446197, - guard__h455127, - guard__h463963, - guard__h493568, - guard__h502880, - guard__h511949, - guard__h532421, - guard__h541733, - guard__h550802, - guard__h571725, - guard__h581037, - guard__h590106, - prv__h734956, - prv__h735000, - r1__read_BITS_13_TO_12___h655197, - sbIdx__h157152, - v__h603884, - v__h603894, - v__h604529, - x__h722556, - x__h733551, - x_prv__h712487, - x_prv__h723013, - y_avValue_snd_snd_snd_fst__h730502, - y_avValue_snd_snd_snd_fst__h733361, - y_avValue_snd_snd_snd_fst__h733397; + IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139, + IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74, + IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99, + IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179, + IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29, + IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109, + IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39, + IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156, + IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64, + IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135, + IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66, + IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142, + IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79, + IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175, + IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101, + IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182, + IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31, + IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114, + IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152, + IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44, + IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159, + guard__h346097, + guard__h354806, + guard__h363736, + guard__h372572, + guard__h391796, + guard__h400503, + guard__h409433, + guard__h418269, + guard__h437491, + guard__h446198, + guard__h455128, + guard__h463964, + guard__h493569, + guard__h502881, + guard__h511950, + guard__h532422, + guard__h541734, + guard__h550803, + guard__h571726, + guard__h581038, + guard__h590107, + prv__h734827, + prv__h734871, + r1__read_BITS_13_TO_12___h655198, + sbIdx__h157153, + v__h603885, + v__h603895, + v__h604530, + x__h722557, + x__h733422, + x_prv__h712488, + x_prv__h723014, + y_avValue_snd_snd_snd_fst__h730373, + y_avValue_snd_snd_snd_fst__h733232, + y_avValue_snd_snd_snd_fst__h733268; wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119, IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461, @@ -6425,11 +6425,11 @@ module mkCore(CLK, _dor1sbAggr$EN_setReady_3_put, _dor1sbCons$EN_setReady_0_put, _dor1sbCons$EN_setReady_1_put, - _theResult_____2__h304518, - _theResult_____2__h310512, - _theResult_____2__h318366, - _theResult_____2__h328710, - _theResult_____2__h331935, + _theResult_____2__h304519, + _theResult_____2__h310513, + _theResult_____2__h318367, + _theResult_____2__h328711, + _theResult_____2__h331936, commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205, coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244, @@ -6565,14 +6565,14 @@ module mkCore(CLK, fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13835, fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13973, fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13985, - guard__h364333, - guard__h410030, - guard__h455725, - guard__h503478, - guard__h542331, - guard__h581635, - idx__h685370, - k__h669625, + guard__h364334, + guard__h410031, + guard__h455726, + guard__h503479, + guard__h542332, + guard__h581636, + idx__h685371, + k__h669626, mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444, mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836, mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312, @@ -6585,13 +6585,13 @@ module mkCore(CLK, mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14094, mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747, mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606, - msip__h76123, - next_deqP___1__h304797, - next_deqP___1__h311078, - next_deqP___1__h318932, - next_deqP___1__h328989, - next_deqP___1__h332214, - r1__read_BIT_20___h655893, + msip__h76124, + next_deqP___1__h304798, + next_deqP___1__h311079, + next_deqP___1__h318933, + next_deqP___1__h328990, + next_deqP___1__h332215, + r1__read_BIT_20___h655894, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309, regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13941, regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022, @@ -6621,19 +6621,19 @@ module mkCore(CLK, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294, sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295, sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632, - tsr_val__h726308, - tvm_val__h726310, - v__h299287, - v__h299805, - v__h309801, - v__h310032, - v__h313677, - v__h313908, - v__h328278, - v__h328509, - v__h331503, - v__h331734, - x__h603385; + tsr_val__h726179, + tvm_val__h726181, + v__h299288, + v__h299806, + v__h309802, + v__h310033, + v__h313678, + v__h313909, + v__h328279, + v__h328510, + v__h331504, + v__h331735, + x__h603386; // action method coreReq_start assign RDY_coreReq_start = 1'd1 ; @@ -12027,13 +12027,13 @@ module mkCore(CLK, assign MUX_commitStage_commitTrap$write_1__VAL_2 = { 1'd1, rob$deqPort_0_deq_data[425:362], - x__h702377, + x__h702378, rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[361:330] } ; assign MUX_commitStage_rg_serial_num$write_1__VAL_1 = commitStage_rg_serial_num + 64'd1 ; assign MUX_commitStage_rg_serial_num$write_1__VAL_3 = - commitStage_rg_serial_num + y__h733310 ; + commitStage_rg_serial_num + y__h733181 ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 = { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12047,7 +12047,7 @@ module mkCore(CLK, 5'd10, sbAggr$eagerLookup_0_get } ; assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 = - (k__h669625 == 1'd0 && + (k__h669626 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -12068,7 +12068,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -12159,7 +12159,7 @@ module mkCore(CLK, IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd0) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 = { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713, @@ -12173,10 +12173,10 @@ module mkCore(CLK, assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84], - x__h285847 } ; + x__h285848 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 = { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - x__h287292, + x__h287293, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 = { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, @@ -12184,7 +12184,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 = { 2'd2, - addr__h290068, + addr__h290069, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 = { 1'd1, @@ -12197,12 +12197,12 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 = - { x__h153726, x__h153732, 84'h82AAAAAAAAAAAAAAAAAAA } ; + { x__h153727, x__h153733, 84'h82AAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 = - { x__h157273, x__h157279, 84'hCAAAAAAAAAAAAAAAAAAAA } ; + { x__h157274, x__h157280, 84'hCAAAAAAAAAAAAAAAAAAAA } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 = - { x__h160089, - x__h160093, + { x__h160090, + x__h160094, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216, @@ -12213,7 +12213,7 @@ module mkCore(CLK, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247, - x__h161941, + x__h161942, IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259, coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263, @@ -12226,7 +12226,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, - resp_addr__h291972, + resp_addr__h291973, 2'd0, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ; assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 = @@ -12234,8 +12234,8 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq, coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ; assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 = - { prv__h735000, - prv__h735000 != 2'd3 && csrf_vm_mode_sv39_reg, + { prv__h734871, + prv__h734871 != 2'd3 && csrf_vm_mode_sv39_reg, csrf_mxr_reg, csrf_sum_reg, csrf_ppn_reg } ; @@ -12312,7 +12312,7 @@ module mkCore(CLK, assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148], - x__h197127 } ; + x__h197128 } ; assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 = { 5'd0, coreFix_memExe_lsq$firstSt[141:78], @@ -12347,8 +12347,8 @@ module mkCore(CLK, assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 = { 1'd1, coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ? - curData__h192917 : - { {32{x__h193680[31]}}, x__h193680 } } ; + curData__h192918 : + { {32{x__h193681[31]}}, x__h193681 } } ; assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 = { coreFix_aluExe_0_exeToFinQ$first[146:19], coreFix_aluExe_0_exeToFinQ$first[326:322], @@ -12381,7 +12381,7 @@ module mkCore(CLK, MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 || MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ; assign MUX_csrf_fflags_reg$write_1__VAL_1 = - csrf_fflags_reg | fflags__h733287 ; + csrf_fflags_reg | fflags__h733158 ; assign MUX_csrf_frm_reg$write_1__VAL_1 = (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == 6'd1) ? @@ -12424,9 +12424,9 @@ module mkCore(CLK, assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 = - n__read__h726694 + 64'd1 ; + n__read__h726565 + 64'd1 ; assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 = - n__read__h726694 + { 62'd0, x__h733551 } ; + n__read__h726565 + { 62'd0, x__h733422 } ; assign MUX_csrf_mpp_reg$write_1__VAL_1 = (rob$deqPort_0_deq_data[329:325] == 5'd13 && IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983 == @@ -12452,12 +12452,12 @@ module mkCore(CLK, 6'd40) ? MUX_csrf_mtval_csr$write_1__VAL_1[1:0] : ((rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h722556 : + x__h722557 : csrf_mpp_reg) ; assign MUX_csrf_rg_dcsr$write_1__VAL_2 = { 32'b0, csrf_rg_dcsr[31:9], - dcsr_cause__h708962, + dcsr_cause__h708963, csrf_rg_dcsr[5:2], csrf_prv_reg } ; assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; @@ -12473,7 +12473,7 @@ module mkCore(CLK, 6'd18) && MUX_csrf_sepc_csr$write_1__VAL_1[8] ; assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ; - assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h737401 } ; + assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h737272 } ; assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ; assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 = { csrf_prv_reg, @@ -12482,12 +12482,12 @@ module mkCore(CLK, csrf_sum_reg, csrf_ppn_reg } ; always@(rob$deqPort_0_deq_data or - next_pc__h722452 or csrf_sepc_csr or csrf_mepc_csr) + next_pc__h722453 or csrf_sepc_csr or csrf_mepc_csr) begin case (rob$deqPort_0_deq_data[329:325]) 5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr; 5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr; - default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h722452; + default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h722453; endcase end assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 = @@ -12522,24 +12522,24 @@ module mkCore(CLK, 56'hAAAAAAAAAAAAAA } ; assign MUX_rf$write_2_wr_2__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? - res_data__h337875 : - res_data__h337870 ; + res_data__h337876 : + res_data__h337871 ; assign MUX_rf$write_2_wr_2__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? - res_data__h383577 : - res_data__h383572 ; + res_data__h383578 : + res_data__h383573 ; assign MUX_rf$write_2_wr_2__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? - res_data__h429272 : - res_data__h429267 ; + res_data__h429273 : + res_data__h429268 ; assign MUX_rf$write_2_wr_2__VAL_5 = coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ? - data___1__h475009 : + data___1__h475010 : IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 ; assign MUX_rf$write_2_wr_2__VAL_6 = coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ? - data___1__h475817 : - data__h475283 ; + data___1__h475818 : + data__h475284 ; assign MUX_rf$write_3_wr_2__VAL_3 = coreFix_memExe_lsq$firstLd[100] ? coreFix_memExe_respLrScAmoQ_data_0 : @@ -12608,15 +12608,15 @@ module mkCore(CLK, assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] : - res_fflags__h337871 ; + res_fflags__h337872 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] : - res_fflags__h383573 ; + res_fflags__h383574 ; assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] : - res_fflags__h429268 ; + res_fflags__h429269 ; assign MUX_v_f_to_TV_0$enq_1__VAL_1 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, @@ -12632,19 +12632,19 @@ module mkCore(CLK, rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404, rob$deqPort_0_deq_data[161:98], IF_rob_deqPort_0_deq_data__4339_BITS_97_TO_96__ETC___d14512, - fflags__h728014, + fflags__h727885, rob$deqPort_0_deq_data[26], - x__h729657, + x__h729528, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_4 = { commitStage_rg_serial_num, 13'd4932, - mip_csr__read__h611252, + mip_csr__read__h611253, 721'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign MUX_v_f_to_TV_0$enq_1__VAL_5 = { commitStage_rg_serial_num, 77'h0AAAAAAAAAAAAAAAAAAA, - x__h723033, + x__h723034, rob$deqPort_0_deq_data[361:182], rob_deqPort_0_deq_data__4339_BIT_181_4414_CONC_ETC___d14505, rob$deqPort_0_deq_data[167], @@ -12940,7 +12940,7 @@ module mkCore(CLK, CAN_FIRE_RL_commitStage_rl_send_tv_reset ; // register commitStage_rg_old_mip_csr_val - assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h611252 ; + assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h611253 ; assign commitStage_rg_old_mip_csr_val$EN = CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ; @@ -13003,8 +13003,8 @@ module mkCore(CLK, // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ? - v__h604529 : - v__h603884 ; + v__h604530 : + v__h603885 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ; // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 @@ -13111,7 +13111,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - _theResult_____2__h296522 ; + _theResult_____2__h296523 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl @@ -13133,7 +13133,7 @@ module mkCore(CLK, (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ? 3'd0 : - v__h295942 ; + v__h295943 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl @@ -13179,7 +13179,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - _theResult_____2__h304518 ; + _theResult_____2__h304519 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl @@ -13197,7 +13197,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 && - v__h299287 ; + v__h299288 ; assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl @@ -13297,7 +13297,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - _theResult_____2__h310512 ; + _theResult_____2__h310513 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl @@ -13315,7 +13315,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 && - v__h309801 ; + v__h309802 ; assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl @@ -13336,7 +13336,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN = - { x_addr__h314075, + { x_addr__h314076, coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513], @@ -13366,7 +13366,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - _theResult_____2__h318366 ; + _theResult_____2__h318367 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl @@ -13384,7 +13384,7 @@ module mkCore(CLK, // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN = NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 && - v__h313677 ; + v__h313678 ; assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ; // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl @@ -13461,7 +13461,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_deqP assign coreFix_memExe_forwardQ_deqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - _theResult_____2__h331935 ; + _theResult_____2__h331936 ; assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_deqReq_rl @@ -13479,7 +13479,7 @@ module mkCore(CLK, // register coreFix_memExe_forwardQ_enqP assign coreFix_memExe_forwardQ_enqP$D_IN = NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 && - v__h331503 ; + v__h331504 ; assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ; // register coreFix_memExe_forwardQ_enqReq_rl @@ -13522,7 +13522,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_deqP assign coreFix_memExe_memRespLdQ_deqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - _theResult_____2__h328710 ; + _theResult_____2__h328711 ; assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_deqReq_rl @@ -13540,7 +13540,7 @@ module mkCore(CLK, // register coreFix_memExe_memRespLdQ_enqP assign coreFix_memExe_memRespLdQ_enqP$D_IN = NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 && - v__h328278 ; + v__h328279 ; assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ; // register coreFix_memExe_memRespLdQ_enqReq_rl @@ -13899,13 +13899,13 @@ module mkCore(CLK, always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_3$write_1__SEL_2 or - cause_code__h709443 or + cause_code__h709444 or MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mcause_code_reg$write_1__SEL_1: csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_3$write_1__SEL_2: - csrf_mcause_code_reg$D_IN = cause_code__h709443; + csrf_mcause_code_reg$D_IN = cause_code__h709444; MUX_csrf_mcause_code_reg$write_1__SEL_3: csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14168,12 +14168,12 @@ module mkCore(CLK, always@(MUX_csrf_mtval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_3$write_1__SEL_2 or - trap_val__h709444 or + trap_val__h709445 or MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_mtval_csr$write_1__SEL_1: csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h709444; + MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h709445; MUX_csrf_mtval_csr$write_1__SEL_3: csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_mtval_csr$D_IN = @@ -14300,13 +14300,13 @@ module mkCore(CLK, always@(MUX_csrf_prv_reg$write_1__SEL_1 or MUX_csrf_prv_reg$write_1__VAL_1 or MUX_commitStage_rg_serial_num$write_1__SEL_1 or - x_prv__h712487 or + x_prv__h712488 or MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_prv_reg$write_1__SEL_1: csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1; MUX_commitStage_rg_serial_num$write_1__SEL_1: - csrf_prv_reg$D_IN = x_prv__h712487; + csrf_prv_reg$D_IN = x_prv__h712488; MUX_csrf_prv_reg$write_1__SEL_3: csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0]; default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ; @@ -14463,13 +14463,13 @@ module mkCore(CLK, always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or MUX_csrf_stval_csr$write_1__VAL_1 or MUX_csrf_ie_vec_1$write_1__SEL_2 or - cause_code__h709443 or + cause_code__h709444 or MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_scause_code_reg$write_1__SEL_1: csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0]; MUX_csrf_ie_vec_1$write_1__SEL_2: - csrf_scause_code_reg$D_IN = cause_code__h709443; + csrf_scause_code_reg$D_IN = cause_code__h709444; MUX_csrf_scause_code_reg$write_1__SEL_3: csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0]; default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ; @@ -14693,12 +14693,12 @@ module mkCore(CLK, always@(MUX_csrf_stval_csr$write_1__SEL_1 or rob$deqPort_0_deq_data or MUX_csrf_ie_vec_1$write_1__SEL_2 or - trap_val__h709444 or + trap_val__h709445 or MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT) case (1'b1) MUX_csrf_stval_csr$write_1__SEL_1: csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32]; - MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h709444; + MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h709445; MUX_csrf_stval_csr$write_1__SEL_3: csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0]; default: csrf_stval_csr$D_IN = @@ -14896,7 +14896,7 @@ module mkCore(CLK, // register mmio_cRqQ_data_0 assign mmio_cRqQ_data_0$D_IN = - { x__h46293, + { x__h46294, (mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ? @@ -14908,7 +14908,7 @@ module mkCore(CLK, mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[71:64] : mmio_cRqQ_enqReq_rl[71:64], - x__h48829 } ; + x__h48830 } ; assign mmio_cRqQ_data_0$EN = NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 && mmio_cRqQ_enqReq_dummy2_2$Q_OUT && @@ -15001,7 +15001,7 @@ module mkCore(CLK, // register mmio_dataReqQ_data_0 assign mmio_dataReqQ_data_0$D_IN = - { x__h18386, + { x__h18387, (mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 : mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ? @@ -15013,7 +15013,7 @@ module mkCore(CLK, mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[71:64] : mmio_dataReqQ_enqReq_rl[71:64], - x__h20924 } ; + x__h20925 } ; assign mmio_dataReqQ_data_0$EN = NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 && mmio_dataReqQ_enqReq_dummy2_2$Q_OUT && @@ -15097,7 +15097,7 @@ module mkCore(CLK, mmio_pRqQ_enqReq_lat_0$wget[32] : mmio_pRqQ_enqReq_rl[32] } : IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766, - x_data__h66087 } ; + x_data__h66088 } ; assign mmio_pRqQ_data_0$EN = NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 && mmio_pRqQ_enqReq_dummy2_2$Q_OUT && @@ -15340,8 +15340,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286, coreFix_aluExe_0_dispToRegQ$first[118:86], coreFix_aluExe_0_dispToRegQ$first[61:17], - x__h639741, x__h639742, + x__h639743, rob$getOrigPC_0_get, rob$getOrigPredPC_0_get, rob$getOrig_Inst_0_get, @@ -15631,8 +15631,8 @@ module mkCore(CLK, CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292, coreFix_aluExe_1_dispToRegQ$first[118:86], coreFix_aluExe_1_dispToRegQ$first[61:17], - x__h617232, x__h617233, + x__h617234, rob$getOrigPC_1_get, rob$getOrigPredPC_1_get, rob$getOrig_Inst_1_get, @@ -15674,7 +15674,7 @@ module mkCore(CLK, // submodule coreFix_aluExe_1_rsAlu assign coreFix_aluExe_1_rsAlu$enq_x = - (k__h669625 == 1'd1 && + (k__h669626 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ? { fetchStage$pipelines_0_first[199:195], IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883, @@ -15695,7 +15695,7 @@ module mkCore(CLK, fetchStage$pipelines_1_first[255:232], regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16174,19 +16174,19 @@ module mkCore(CLK, // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___fst__h603371 : - a__h602949 ; + _theResult___fst__h603372 : + a__h602950 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser = - { b__h602950 == 64'd0, - a__h602949, + { b__h602951 == 64'd0, + a__h602950, coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0, - x__h603385, - a__h602949[63], + x__h603386, + a__h602950[63], 8'd0 } ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? - _theResult___snd__h603372 : - b__h602950 ; + _theResult___snd__h603373 : + b__h602951 ; assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid = WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv && coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 && @@ -16247,20 +16247,20 @@ module mkCore(CLK, 1'd1 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602949 ; - assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602950 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602950 ; + assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602951 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A = - a__h602949 ; + a__h602950 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B = - b__h602950 ; + b__h602951 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A = - a__h602949 ; + a__h602950 ; assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B = - b__h602950 ; + b__h602951 ; // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or @@ -16289,9 +16289,9 @@ module mkCore(CLK, assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x = { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298, coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12], - x__h481671, x__h481672, x__h481673, + x__h481674, coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ; assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -16343,7 +16343,7 @@ module mkCore(CLK, { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -16497,8 +16497,8 @@ module mkCore(CLK, // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r = - { x__h287280, - x__h287292, + { x__h287281, + x__h287293, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797, @@ -16509,13 +16509,13 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828, - x__h289146, + x__h289147, IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844, coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 } ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n = - x__h285847 ; + x__h285848 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n = (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] == 2'd0) ? @@ -17309,7 +17309,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685239 ; + renaming_spec_bits__h685240 ; assign coreFix_memExe_lsq$enqSt_dst = (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? @@ -17329,7 +17329,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_canDeq && regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ? specTagManager$currentSpecBits : - renaming_spec_bits__h685239 ; + renaming_spec_bits__h685240 ; assign coreFix_memExe_lsq$getHit_t = MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ? MUX_coreFix_memExe_lsq$getHit_1__VAL_1 : @@ -17409,7 +17409,7 @@ module mkCore(CLK, assign coreFix_memExe_lsq$updateData_d = (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ? coreFix_memExe_regToExeQ$first[75:12] : - shiftData__h181568 ; + shiftData__h181569 ; assign coreFix_memExe_lsq$updateData_t = coreFix_memExe_regToExeQ$first[143:140] ; assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx = @@ -17509,8 +17509,8 @@ module mkCore(CLK, assign coreFix_memExe_regToExeQ$enq_x = { coreFix_memExe_dispToRegQ$first[97:63], coreFix_memExe_dispToRegQ$first[29:12], - x__h181477, x__h181478, + x__h181479, coreFix_memExe_dispToRegQ$first[11:0] } ; assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask = IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ; @@ -17774,7 +17774,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265, regRenamingTable$rename_1_getRename, rob$enqPort_1_getEnqInstTag, - renaming_spec_bits__h685239, + renaming_spec_bits__h685240, fetchStage$pipelines_1_first[194:192] == 3'd1, specTagManager$nextSpecTag, sbAggr$eagerLookup_1_get } ; @@ -18222,7 +18222,7 @@ module mkCore(CLK, assign fetchStage$perf_req_r = 2'h0 ; assign fetchStage$perf_setStatus_doStats = 1'b0 ; always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or - pc__h712387 or + pc__h712388 or WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or coreFix_aluExe_1_exeToFinQ$first or WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or @@ -18236,7 +18236,7 @@ module mkCore(CLK, begin case (1'b1) // synopsys parallel_case MUX_commitStage_rg_serial_num$write_1__SEL_1: - fetchStage$redirect_pc = pc__h712387; + fetchStage$redirect_pc = pc__h712388; WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T: fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19]; WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T: @@ -18656,7 +18656,7 @@ module mkCore(CLK, assign regRenamingTable$rename_1_claimRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$rename_1_claimRename_sb = - renaming_spec_bits__h685239 ; + renaming_spec_bits__h685240 ; assign regRenamingTable$rename_1_getRename_r = fetchStage$pipelines_1_first[95:69] ; assign regRenamingTable$specUpdate_correctSpeculation_mask = @@ -18928,7 +18928,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306, 7'd32, - renaming_spec_bits__h685239 } ; + renaming_spec_bits__h685240 } ; assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ; assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ; assign rob$getOrigPC_2_get_x = 12'h0 ; @@ -19588,9 +19588,9 @@ module mkCore(CLK, rob$deqPort_1_deq_data[161:98], CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301, rob$deqPort_1_deq_data[95:32], - fflags__h730667, + fflags__h730538, rob$deqPort_1_deq_data[26], - x__h732802, + x__h732673, 258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign v_f_to_TV_1$ENQ = WILL_FIRE_RL_commitStage_doCommitNormalInst && @@ -19612,15 +19612,15 @@ module mkCore(CLK, // remaining internal signals module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]), - .amoExec_current_data(curData__h192917), + .amoExec_current_data(curData__h192918), .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]), .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]), - .amoExec(n__h194455)); + .amoExec(n__h194456)); module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32], 3'd0 }), .amoExec_current_data({ 63'd0, - msip__h76123 }), - .amoExec_in_data({ 32'd0, x__h76238 }), + msip__h76124 }), + .amoExec_in_data({ 32'd0, x__h76239 }), .amoExec_upper_32_bits(1'd0), .amoExec(amoExec___d880)); module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417], @@ -19652,7 +19652,7 @@ module mkCore(CLK, { { fetchStage$pipelines_0_first[173], IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 }, fetchStage$pipelines_0_first[160], - x_data_imm__h676657 } }), + x_data_imm__h676658 } }), .checkForException_regs({ fetchStage$pipelines_0_first[95], fetchStage$pipelines_0_first[94:89], { fetchStage$pipelines_0_first[88], @@ -19661,13 +19661,13 @@ module mkCore(CLK, fetchStage$pipelines_0_first[80:76], { fetchStage$pipelines_0_first[75], fetchStage$pipelines_0_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655012, - r1__read_BITS_13_TO_12___h655197 != + .checkForException_csrState({ x_decodeInfo_frm__h655013, + r1__read_BITS_13_TO_12___h655198 != 2'd0, - { prv__h734956, - tvm_val__h726310, - { r1__read_BIT_20___h655893, - tsr_val__h726308, + { prv__h734827, + tvm_val__h726181, + { r1__read_BIT_20___h655894, + tsr_val__h726179, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19682,7 +19682,7 @@ module mkCore(CLK, IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584, { fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676, fetchStage$pipelines_1_first[160], - x_data_imm__h692711 } }), + x_data_imm__h692712 } }), .checkForException_regs({ fetchStage$pipelines_1_first[95], fetchStage$pipelines_1_first[94:89], { fetchStage$pipelines_1_first[88], @@ -19691,13 +19691,13 @@ module mkCore(CLK, fetchStage$pipelines_1_first[80:76], { fetchStage$pipelines_1_first[75], fetchStage$pipelines_1_first[74:69] } } }), - .checkForException_csrState({ x_decodeInfo_frm__h655012, - r1__read_BITS_13_TO_12___h655197 != + .checkForException_csrState({ x_decodeInfo_frm__h655013, + r1__read_BITS_13_TO_12___h655198 != 2'd0, - { prv__h734956, - tvm_val__h726310, - { r1__read_BIT_20___h655893, - tsr_val__h726308, + { prv__h734827, + tvm_val__h726181, + { r1__read_BIT_20___h655894, + tsr_val__h726179, { csrf_mcounteren_cy_reg, csrf_mcounteren_cy_reg && csrf_scounteren_cy_reg, @@ -19711,1196 +19711,1196 @@ module mkCore(CLK, module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229], CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259, coreFix_fpuMulDivExe_0_regToExeQ$first[225] }), - .execFpuSimple_rVal1(rVal1__h481762), - .execFpuSimple_rVal2(rVal2__h481763), + .execFpuSimple_rVal1(rVal1__h481763), + .execFpuSimple_rVal2(rVal2__h481764), .execFpuSimple(execFpuSimple___d11056)); assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 ? - _theResult___snd__h354260 : - _theResult____h346086 ; + _theResult___snd__h354261 : + _theResult____h346087 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 ? - _theResult___snd__h399957 : - _theResult____h391785 ; + _theResult___snd__h399958 : + _theResult____h391786 ; assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 = _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 ? - _theResult___snd__h445652 : - _theResult____h437480 ; + _theResult___snd__h445653 : + _theResult____h437481 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 ? - _theResult___snd__h511169 : - _theResult____h502870 ; + _theResult___snd__h511170 : + _theResult____h502871 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 ? - _theResult___snd__h589326 : - _theResult____h581027 ; + _theResult___snd__h589327 : + _theResult____h581028 ; assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 = _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 ? - _theResult___snd__h550022 : - _theResult____h541723 ; + _theResult___snd__h550023 : + _theResult____h541724 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 ? - _theResult___snd__h463418 : - _theResult____h455117 ; + _theResult___snd__h463419 : + _theResult____h455118 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 ? - _theResult___snd__h372026 : - _theResult____h363725 ; + _theResult___snd__h372027 : + _theResult____h363726 ; assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 = _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 ? - _theResult___snd__h417723 : - _theResult____h409422 ; + _theResult___snd__h417724 : + _theResult____h409423 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 ? - _theResult___snd__h501518 : + _theResult___snd__h501519 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 ? - _theResult___snd__h501518 : - _theResult___snd__h519923 ; + _theResult___snd__h501519 : + _theResult___snd__h519924 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 ? - _theResult___snd__h579675 : + _theResult___snd__h579676 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 ? - _theResult___snd__h579675 : - _theResult___snd__h598080 ; + _theResult___snd__h579676 : + _theResult___snd__h598081 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 ? - _theResult___snd__h540371 : + _theResult___snd__h540372 : 57'd0 ; assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 = _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 ? - _theResult___snd__h540371 : - _theResult___snd__h558776 ; + _theResult___snd__h540372 : + _theResult___snd__h558777 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 ? - _theResult___snd__h454234 : + _theResult___snd__h454235 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 ? - _theResult___snd__h454234 : - _theResult___snd__h472024 ; + _theResult___snd__h454235 : + _theResult___snd__h472025 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 ? - _theResult___snd__h362842 : + _theResult___snd__h362843 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 ? - _theResult___snd__h362842 : - _theResult___snd__h380632 ; + _theResult___snd__h362843 : + _theResult___snd__h380633 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 ? - _theResult___snd__h408539 : + _theResult___snd__h408540 : 57'd0 ; assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 = _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 ? - _theResult___snd__h408539 : - _theResult___snd__h426329 ; + _theResult___snd__h408540 : + _theResult___snd__h426330 ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354197 == 8'd255) ? + ((_theResult___fst_exp__h354198 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054) : - ((_theResult___fst_exp__h362853 == 8'd255) ? + ((_theResult___fst_exp__h362854 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - ((_theResult___fst_exp__h354197 == 8'd255) ? + ((_theResult___fst_exp__h354198 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110) : - ((_theResult___fst_exp__h362853 == 8'd255) ? + ((_theResult___fst_exp__h362854 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399894 == 8'd255) ? + ((_theResult___fst_exp__h399895 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446) : - ((_theResult___fst_exp__h408550 == 8'd255) ? + ((_theResult___fst_exp__h408551 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - ((_theResult___fst_exp__h399894 == 8'd255) ? + ((_theResult___fst_exp__h399895 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502) : - ((_theResult___fst_exp__h408550 == 8'd255) ? + ((_theResult___fst_exp__h408551 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445589 == 8'd255) ? + ((_theResult___fst_exp__h445590 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838) : - ((_theResult___fst_exp__h454245 == 8'd255) ? + ((_theResult___fst_exp__h454246 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ; assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - ((_theResult___fst_exp__h445589 == 8'd255) ? + ((_theResult___fst_exp__h445590 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894) : - ((_theResult___fst_exp__h454245 == 8'd255) ? + ((_theResult___fst_exp__h454246 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901) ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 = - (_theResult____h346086[56] ? + (_theResult____h346087[56] ? 6'd0 : - (_theResult____h346086[55] ? + (_theResult____h346087[55] ? 6'd1 : - (_theResult____h346086[54] ? + (_theResult____h346087[54] ? 6'd2 : - (_theResult____h346086[53] ? + (_theResult____h346087[53] ? 6'd3 : - (_theResult____h346086[52] ? + (_theResult____h346087[52] ? 6'd4 : - (_theResult____h346086[51] ? + (_theResult____h346087[51] ? 6'd5 : - (_theResult____h346086[50] ? + (_theResult____h346087[50] ? 6'd6 : - (_theResult____h346086[49] ? + (_theResult____h346087[49] ? 6'd7 : - (_theResult____h346086[48] ? + (_theResult____h346087[48] ? 6'd8 : - (_theResult____h346086[47] ? + (_theResult____h346087[47] ? 6'd9 : - (_theResult____h346086[46] ? + (_theResult____h346087[46] ? 6'd10 : - (_theResult____h346086[45] ? + (_theResult____h346087[45] ? 6'd11 : - (_theResult____h346086[44] ? + (_theResult____h346087[44] ? 6'd12 : - (_theResult____h346086[43] ? + (_theResult____h346087[43] ? 6'd13 : - (_theResult____h346086[42] ? + (_theResult____h346087[42] ? 6'd14 : - (_theResult____h346086[41] ? + (_theResult____h346087[41] ? 6'd15 : - (_theResult____h346086[40] ? + (_theResult____h346087[40] ? 6'd16 : - (_theResult____h346086[39] ? + (_theResult____h346087[39] ? 6'd17 : - (_theResult____h346086[38] ? + (_theResult____h346087[38] ? 6'd18 : - (_theResult____h346086[37] ? + (_theResult____h346087[37] ? 6'd19 : - (_theResult____h346086[36] ? + (_theResult____h346087[36] ? 6'd20 : - (_theResult____h346086[35] ? + (_theResult____h346087[35] ? 6'd21 : - (_theResult____h346086[34] ? + (_theResult____h346087[34] ? 6'd22 : - (_theResult____h346086[33] ? + (_theResult____h346087[33] ? 6'd23 : - (_theResult____h346086[32] ? + (_theResult____h346087[32] ? 6'd24 : - (_theResult____h346086[31] ? + (_theResult____h346087[31] ? 6'd25 : - (_theResult____h346086[30] ? + (_theResult____h346087[30] ? 6'd26 : - (_theResult____h346086[29] ? + (_theResult____h346087[29] ? 6'd27 : - (_theResult____h346086[28] ? + (_theResult____h346087[28] ? 6'd28 : - (_theResult____h346086[27] ? + (_theResult____h346087[27] ? 6'd29 : - (_theResult____h346086[26] ? + (_theResult____h346087[26] ? 6'd30 : - (_theResult____h346086[25] ? + (_theResult____h346087[25] ? 6'd31 : - (_theResult____h346086[24] ? + (_theResult____h346087[24] ? 6'd32 : - (_theResult____h346086[23] ? + (_theResult____h346087[23] ? 6'd33 : - (_theResult____h346086[22] ? + (_theResult____h346087[22] ? 6'd34 : - (_theResult____h346086[21] ? + (_theResult____h346087[21] ? 6'd35 : - (_theResult____h346086[20] ? + (_theResult____h346087[20] ? 6'd36 : - (_theResult____h346086[19] ? + (_theResult____h346087[19] ? 6'd37 : - (_theResult____h346086[18] ? + (_theResult____h346087[18] ? 6'd38 : - (_theResult____h346086[17] ? + (_theResult____h346087[17] ? 6'd39 : - (_theResult____h346086[16] ? + (_theResult____h346087[16] ? 6'd40 : - (_theResult____h346086[15] ? + (_theResult____h346087[15] ? 6'd41 : - (_theResult____h346086[14] ? + (_theResult____h346087[14] ? 6'd42 : - (_theResult____h346086[13] ? + (_theResult____h346087[13] ? 6'd43 : - (_theResult____h346086[12] ? + (_theResult____h346087[12] ? 6'd44 : - (_theResult____h346086[11] ? + (_theResult____h346087[11] ? 6'd45 : - (_theResult____h346086[10] ? + (_theResult____h346087[10] ? 6'd46 : - (_theResult____h346086[9] ? + (_theResult____h346087[9] ? 6'd47 : - (_theResult____h346086[8] ? + (_theResult____h346087[8] ? 6'd48 : - (_theResult____h346086[7] ? + (_theResult____h346087[7] ? 6'd49 : - (_theResult____h346086[6] ? + (_theResult____h346087[6] ? 6'd50 : - (_theResult____h346086[5] ? + (_theResult____h346087[5] ? 6'd51 : - (_theResult____h346086[4] ? + (_theResult____h346087[4] ? 6'd52 : - (_theResult____h346086[3] ? + (_theResult____h346087[3] ? 6'd53 : - (_theResult____h346086[2] ? + (_theResult____h346087[2] ? 6'd54 : - (_theResult____h346086[1] ? + (_theResult____h346087[1] ? 6'd55 : - (_theResult____h346086[0] ? + (_theResult____h346087[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 = - (_theResult____h391785[56] ? + (_theResult____h391786[56] ? 6'd0 : - (_theResult____h391785[55] ? + (_theResult____h391786[55] ? 6'd1 : - (_theResult____h391785[54] ? + (_theResult____h391786[54] ? 6'd2 : - (_theResult____h391785[53] ? + (_theResult____h391786[53] ? 6'd3 : - (_theResult____h391785[52] ? + (_theResult____h391786[52] ? 6'd4 : - (_theResult____h391785[51] ? + (_theResult____h391786[51] ? 6'd5 : - (_theResult____h391785[50] ? + (_theResult____h391786[50] ? 6'd6 : - (_theResult____h391785[49] ? + (_theResult____h391786[49] ? 6'd7 : - (_theResult____h391785[48] ? + (_theResult____h391786[48] ? 6'd8 : - (_theResult____h391785[47] ? + (_theResult____h391786[47] ? 6'd9 : - (_theResult____h391785[46] ? + (_theResult____h391786[46] ? 6'd10 : - (_theResult____h391785[45] ? + (_theResult____h391786[45] ? 6'd11 : - (_theResult____h391785[44] ? + (_theResult____h391786[44] ? 6'd12 : - (_theResult____h391785[43] ? + (_theResult____h391786[43] ? 6'd13 : - (_theResult____h391785[42] ? + (_theResult____h391786[42] ? 6'd14 : - (_theResult____h391785[41] ? + (_theResult____h391786[41] ? 6'd15 : - (_theResult____h391785[40] ? + (_theResult____h391786[40] ? 6'd16 : - (_theResult____h391785[39] ? + (_theResult____h391786[39] ? 6'd17 : - (_theResult____h391785[38] ? + (_theResult____h391786[38] ? 6'd18 : - (_theResult____h391785[37] ? + (_theResult____h391786[37] ? 6'd19 : - (_theResult____h391785[36] ? + (_theResult____h391786[36] ? 6'd20 : - (_theResult____h391785[35] ? + (_theResult____h391786[35] ? 6'd21 : - (_theResult____h391785[34] ? + (_theResult____h391786[34] ? 6'd22 : - (_theResult____h391785[33] ? + (_theResult____h391786[33] ? 6'd23 : - (_theResult____h391785[32] ? + (_theResult____h391786[32] ? 6'd24 : - (_theResult____h391785[31] ? + (_theResult____h391786[31] ? 6'd25 : - (_theResult____h391785[30] ? + (_theResult____h391786[30] ? 6'd26 : - (_theResult____h391785[29] ? + (_theResult____h391786[29] ? 6'd27 : - (_theResult____h391785[28] ? + (_theResult____h391786[28] ? 6'd28 : - (_theResult____h391785[27] ? + (_theResult____h391786[27] ? 6'd29 : - (_theResult____h391785[26] ? + (_theResult____h391786[26] ? 6'd30 : - (_theResult____h391785[25] ? + (_theResult____h391786[25] ? 6'd31 : - (_theResult____h391785[24] ? + (_theResult____h391786[24] ? 6'd32 : - (_theResult____h391785[23] ? + (_theResult____h391786[23] ? 6'd33 : - (_theResult____h391785[22] ? + (_theResult____h391786[22] ? 6'd34 : - (_theResult____h391785[21] ? + (_theResult____h391786[21] ? 6'd35 : - (_theResult____h391785[20] ? + (_theResult____h391786[20] ? 6'd36 : - (_theResult____h391785[19] ? + (_theResult____h391786[19] ? 6'd37 : - (_theResult____h391785[18] ? + (_theResult____h391786[18] ? 6'd38 : - (_theResult____h391785[17] ? + (_theResult____h391786[17] ? 6'd39 : - (_theResult____h391785[16] ? + (_theResult____h391786[16] ? 6'd40 : - (_theResult____h391785[15] ? + (_theResult____h391786[15] ? 6'd41 : - (_theResult____h391785[14] ? + (_theResult____h391786[14] ? 6'd42 : - (_theResult____h391785[13] ? + (_theResult____h391786[13] ? 6'd43 : - (_theResult____h391785[12] ? + (_theResult____h391786[12] ? 6'd44 : - (_theResult____h391785[11] ? + (_theResult____h391786[11] ? 6'd45 : - (_theResult____h391785[10] ? + (_theResult____h391786[10] ? 6'd46 : - (_theResult____h391785[9] ? + (_theResult____h391786[9] ? 6'd47 : - (_theResult____h391785[8] ? + (_theResult____h391786[8] ? 6'd48 : - (_theResult____h391785[7] ? + (_theResult____h391786[7] ? 6'd49 : - (_theResult____h391785[6] ? + (_theResult____h391786[6] ? 6'd50 : - (_theResult____h391785[5] ? + (_theResult____h391786[5] ? 6'd51 : - (_theResult____h391785[4] ? + (_theResult____h391786[4] ? 6'd52 : - (_theResult____h391785[3] ? + (_theResult____h391786[3] ? 6'd53 : - (_theResult____h391785[2] ? + (_theResult____h391786[2] ? 6'd54 : - (_theResult____h391785[1] ? + (_theResult____h391786[1] ? 6'd55 : - (_theResult____h391785[0] ? + (_theResult____h391786[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 = - (_theResult____h437480[56] ? + (_theResult____h437481[56] ? 6'd0 : - (_theResult____h437480[55] ? + (_theResult____h437481[55] ? 6'd1 : - (_theResult____h437480[54] ? + (_theResult____h437481[54] ? 6'd2 : - (_theResult____h437480[53] ? + (_theResult____h437481[53] ? 6'd3 : - (_theResult____h437480[52] ? + (_theResult____h437481[52] ? 6'd4 : - (_theResult____h437480[51] ? + (_theResult____h437481[51] ? 6'd5 : - (_theResult____h437480[50] ? + (_theResult____h437481[50] ? 6'd6 : - (_theResult____h437480[49] ? + (_theResult____h437481[49] ? 6'd7 : - (_theResult____h437480[48] ? + (_theResult____h437481[48] ? 6'd8 : - (_theResult____h437480[47] ? + (_theResult____h437481[47] ? 6'd9 : - (_theResult____h437480[46] ? + (_theResult____h437481[46] ? 6'd10 : - (_theResult____h437480[45] ? + (_theResult____h437481[45] ? 6'd11 : - (_theResult____h437480[44] ? + (_theResult____h437481[44] ? 6'd12 : - (_theResult____h437480[43] ? + (_theResult____h437481[43] ? 6'd13 : - (_theResult____h437480[42] ? + (_theResult____h437481[42] ? 6'd14 : - (_theResult____h437480[41] ? + (_theResult____h437481[41] ? 6'd15 : - (_theResult____h437480[40] ? + (_theResult____h437481[40] ? 6'd16 : - (_theResult____h437480[39] ? + (_theResult____h437481[39] ? 6'd17 : - (_theResult____h437480[38] ? + (_theResult____h437481[38] ? 6'd18 : - (_theResult____h437480[37] ? + (_theResult____h437481[37] ? 6'd19 : - (_theResult____h437480[36] ? + (_theResult____h437481[36] ? 6'd20 : - (_theResult____h437480[35] ? + (_theResult____h437481[35] ? 6'd21 : - (_theResult____h437480[34] ? + (_theResult____h437481[34] ? 6'd22 : - (_theResult____h437480[33] ? + (_theResult____h437481[33] ? 6'd23 : - (_theResult____h437480[32] ? + (_theResult____h437481[32] ? 6'd24 : - (_theResult____h437480[31] ? + (_theResult____h437481[31] ? 6'd25 : - (_theResult____h437480[30] ? + (_theResult____h437481[30] ? 6'd26 : - (_theResult____h437480[29] ? + (_theResult____h437481[29] ? 6'd27 : - (_theResult____h437480[28] ? + (_theResult____h437481[28] ? 6'd28 : - (_theResult____h437480[27] ? + (_theResult____h437481[27] ? 6'd29 : - (_theResult____h437480[26] ? + (_theResult____h437481[26] ? 6'd30 : - (_theResult____h437480[25] ? + (_theResult____h437481[25] ? 6'd31 : - (_theResult____h437480[24] ? + (_theResult____h437481[24] ? 6'd32 : - (_theResult____h437480[23] ? + (_theResult____h437481[23] ? 6'd33 : - (_theResult____h437480[22] ? + (_theResult____h437481[22] ? 6'd34 : - (_theResult____h437480[21] ? + (_theResult____h437481[21] ? 6'd35 : - (_theResult____h437480[20] ? + (_theResult____h437481[20] ? 6'd36 : - (_theResult____h437480[19] ? + (_theResult____h437481[19] ? 6'd37 : - (_theResult____h437480[18] ? + (_theResult____h437481[18] ? 6'd38 : - (_theResult____h437480[17] ? + (_theResult____h437481[17] ? 6'd39 : - (_theResult____h437480[16] ? + (_theResult____h437481[16] ? 6'd40 : - (_theResult____h437480[15] ? + (_theResult____h437481[15] ? 6'd41 : - (_theResult____h437480[14] ? + (_theResult____h437481[14] ? 6'd42 : - (_theResult____h437480[13] ? + (_theResult____h437481[13] ? 6'd43 : - (_theResult____h437480[12] ? + (_theResult____h437481[12] ? 6'd44 : - (_theResult____h437480[11] ? + (_theResult____h437481[11] ? 6'd45 : - (_theResult____h437480[10] ? + (_theResult____h437481[10] ? 6'd46 : - (_theResult____h437480[9] ? + (_theResult____h437481[9] ? 6'd47 : - (_theResult____h437480[8] ? + (_theResult____h437481[8] ? 6'd48 : - (_theResult____h437480[7] ? + (_theResult____h437481[7] ? 6'd49 : - (_theResult____h437480[6] ? + (_theResult____h437481[6] ? 6'd50 : - (_theResult____h437480[5] ? + (_theResult____h437481[5] ? 6'd51 : - (_theResult____h437480[4] ? + (_theResult____h437481[4] ? 6'd52 : - (_theResult____h437480[3] ? + (_theResult____h437481[3] ? 6'd53 : - (_theResult____h437480[2] ? + (_theResult____h437481[2] ? 6'd54 : - (_theResult____h437480[1] ? + (_theResult____h437481[1] ? 6'd55 : - (_theResult____h437480[0] ? + (_theResult____h437481[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 = - (_theResult____h541723[56] ? + (_theResult____h541724[56] ? 6'd0 : - (_theResult____h541723[55] ? + (_theResult____h541724[55] ? 6'd1 : - (_theResult____h541723[54] ? + (_theResult____h541724[54] ? 6'd2 : - (_theResult____h541723[53] ? + (_theResult____h541724[53] ? 6'd3 : - (_theResult____h541723[52] ? + (_theResult____h541724[52] ? 6'd4 : - (_theResult____h541723[51] ? + (_theResult____h541724[51] ? 6'd5 : - (_theResult____h541723[50] ? + (_theResult____h541724[50] ? 6'd6 : - (_theResult____h541723[49] ? + (_theResult____h541724[49] ? 6'd7 : - (_theResult____h541723[48] ? + (_theResult____h541724[48] ? 6'd8 : - (_theResult____h541723[47] ? + (_theResult____h541724[47] ? 6'd9 : - (_theResult____h541723[46] ? + (_theResult____h541724[46] ? 6'd10 : - (_theResult____h541723[45] ? + (_theResult____h541724[45] ? 6'd11 : - (_theResult____h541723[44] ? + (_theResult____h541724[44] ? 6'd12 : - (_theResult____h541723[43] ? + (_theResult____h541724[43] ? 6'd13 : - (_theResult____h541723[42] ? + (_theResult____h541724[42] ? 6'd14 : - (_theResult____h541723[41] ? + (_theResult____h541724[41] ? 6'd15 : - (_theResult____h541723[40] ? + (_theResult____h541724[40] ? 6'd16 : - (_theResult____h541723[39] ? + (_theResult____h541724[39] ? 6'd17 : - (_theResult____h541723[38] ? + (_theResult____h541724[38] ? 6'd18 : - (_theResult____h541723[37] ? + (_theResult____h541724[37] ? 6'd19 : - (_theResult____h541723[36] ? + (_theResult____h541724[36] ? 6'd20 : - (_theResult____h541723[35] ? + (_theResult____h541724[35] ? 6'd21 : - (_theResult____h541723[34] ? + (_theResult____h541724[34] ? 6'd22 : - (_theResult____h541723[33] ? + (_theResult____h541724[33] ? 6'd23 : - (_theResult____h541723[32] ? + (_theResult____h541724[32] ? 6'd24 : - (_theResult____h541723[31] ? + (_theResult____h541724[31] ? 6'd25 : - (_theResult____h541723[30] ? + (_theResult____h541724[30] ? 6'd26 : - (_theResult____h541723[29] ? + (_theResult____h541724[29] ? 6'd27 : - (_theResult____h541723[28] ? + (_theResult____h541724[28] ? 6'd28 : - (_theResult____h541723[27] ? + (_theResult____h541724[27] ? 6'd29 : - (_theResult____h541723[26] ? + (_theResult____h541724[26] ? 6'd30 : - (_theResult____h541723[25] ? + (_theResult____h541724[25] ? 6'd31 : - (_theResult____h541723[24] ? + (_theResult____h541724[24] ? 6'd32 : - (_theResult____h541723[23] ? + (_theResult____h541724[23] ? 6'd33 : - (_theResult____h541723[22] ? + (_theResult____h541724[22] ? 6'd34 : - (_theResult____h541723[21] ? + (_theResult____h541724[21] ? 6'd35 : - (_theResult____h541723[20] ? + (_theResult____h541724[20] ? 6'd36 : - (_theResult____h541723[19] ? + (_theResult____h541724[19] ? 6'd37 : - (_theResult____h541723[18] ? + (_theResult____h541724[18] ? 6'd38 : - (_theResult____h541723[17] ? + (_theResult____h541724[17] ? 6'd39 : - (_theResult____h541723[16] ? + (_theResult____h541724[16] ? 6'd40 : - (_theResult____h541723[15] ? + (_theResult____h541724[15] ? 6'd41 : - (_theResult____h541723[14] ? + (_theResult____h541724[14] ? 6'd42 : - (_theResult____h541723[13] ? + (_theResult____h541724[13] ? 6'd43 : - (_theResult____h541723[12] ? + (_theResult____h541724[12] ? 6'd44 : - (_theResult____h541723[11] ? + (_theResult____h541724[11] ? 6'd45 : - (_theResult____h541723[10] ? + (_theResult____h541724[10] ? 6'd46 : - (_theResult____h541723[9] ? + (_theResult____h541724[9] ? 6'd47 : - (_theResult____h541723[8] ? + (_theResult____h541724[8] ? 6'd48 : - (_theResult____h541723[7] ? + (_theResult____h541724[7] ? 6'd49 : - (_theResult____h541723[6] ? + (_theResult____h541724[6] ? 6'd50 : - (_theResult____h541723[5] ? + (_theResult____h541724[5] ? 6'd51 : - (_theResult____h541723[4] ? + (_theResult____h541724[4] ? 6'd52 : - (_theResult____h541723[3] ? + (_theResult____h541724[3] ? 6'd53 : - (_theResult____h541723[2] ? + (_theResult____h541724[2] ? 6'd54 : - (_theResult____h541723[1] ? + (_theResult____h541724[1] ? 6'd55 : - (_theResult____h541723[0] ? + (_theResult____h541724[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 = - (_theResult____h502870[56] ? + (_theResult____h502871[56] ? 6'd0 : - (_theResult____h502870[55] ? + (_theResult____h502871[55] ? 6'd1 : - (_theResult____h502870[54] ? + (_theResult____h502871[54] ? 6'd2 : - (_theResult____h502870[53] ? + (_theResult____h502871[53] ? 6'd3 : - (_theResult____h502870[52] ? + (_theResult____h502871[52] ? 6'd4 : - (_theResult____h502870[51] ? + (_theResult____h502871[51] ? 6'd5 : - (_theResult____h502870[50] ? + (_theResult____h502871[50] ? 6'd6 : - (_theResult____h502870[49] ? + (_theResult____h502871[49] ? 6'd7 : - (_theResult____h502870[48] ? + (_theResult____h502871[48] ? 6'd8 : - (_theResult____h502870[47] ? + (_theResult____h502871[47] ? 6'd9 : - (_theResult____h502870[46] ? + (_theResult____h502871[46] ? 6'd10 : - (_theResult____h502870[45] ? + (_theResult____h502871[45] ? 6'd11 : - (_theResult____h502870[44] ? + (_theResult____h502871[44] ? 6'd12 : - (_theResult____h502870[43] ? + (_theResult____h502871[43] ? 6'd13 : - (_theResult____h502870[42] ? + (_theResult____h502871[42] ? 6'd14 : - (_theResult____h502870[41] ? + (_theResult____h502871[41] ? 6'd15 : - (_theResult____h502870[40] ? + (_theResult____h502871[40] ? 6'd16 : - (_theResult____h502870[39] ? + (_theResult____h502871[39] ? 6'd17 : - (_theResult____h502870[38] ? + (_theResult____h502871[38] ? 6'd18 : - (_theResult____h502870[37] ? + (_theResult____h502871[37] ? 6'd19 : - (_theResult____h502870[36] ? + (_theResult____h502871[36] ? 6'd20 : - (_theResult____h502870[35] ? + (_theResult____h502871[35] ? 6'd21 : - (_theResult____h502870[34] ? + (_theResult____h502871[34] ? 6'd22 : - (_theResult____h502870[33] ? + (_theResult____h502871[33] ? 6'd23 : - (_theResult____h502870[32] ? + (_theResult____h502871[32] ? 6'd24 : - (_theResult____h502870[31] ? + (_theResult____h502871[31] ? 6'd25 : - (_theResult____h502870[30] ? + (_theResult____h502871[30] ? 6'd26 : - (_theResult____h502870[29] ? + (_theResult____h502871[29] ? 6'd27 : - (_theResult____h502870[28] ? + (_theResult____h502871[28] ? 6'd28 : - (_theResult____h502870[27] ? + (_theResult____h502871[27] ? 6'd29 : - (_theResult____h502870[26] ? + (_theResult____h502871[26] ? 6'd30 : - (_theResult____h502870[25] ? + (_theResult____h502871[25] ? 6'd31 : - (_theResult____h502870[24] ? + (_theResult____h502871[24] ? 6'd32 : - (_theResult____h502870[23] ? + (_theResult____h502871[23] ? 6'd33 : - (_theResult____h502870[22] ? + (_theResult____h502871[22] ? 6'd34 : - (_theResult____h502870[21] ? + (_theResult____h502871[21] ? 6'd35 : - (_theResult____h502870[20] ? + (_theResult____h502871[20] ? 6'd36 : - (_theResult____h502870[19] ? + (_theResult____h502871[19] ? 6'd37 : - (_theResult____h502870[18] ? + (_theResult____h502871[18] ? 6'd38 : - (_theResult____h502870[17] ? + (_theResult____h502871[17] ? 6'd39 : - (_theResult____h502870[16] ? + (_theResult____h502871[16] ? 6'd40 : - (_theResult____h502870[15] ? + (_theResult____h502871[15] ? 6'd41 : - (_theResult____h502870[14] ? + (_theResult____h502871[14] ? 6'd42 : - (_theResult____h502870[13] ? + (_theResult____h502871[13] ? 6'd43 : - (_theResult____h502870[12] ? + (_theResult____h502871[12] ? 6'd44 : - (_theResult____h502870[11] ? + (_theResult____h502871[11] ? 6'd45 : - (_theResult____h502870[10] ? + (_theResult____h502871[10] ? 6'd46 : - (_theResult____h502870[9] ? + (_theResult____h502871[9] ? 6'd47 : - (_theResult____h502870[8] ? + (_theResult____h502871[8] ? 6'd48 : - (_theResult____h502870[7] ? + (_theResult____h502871[7] ? 6'd49 : - (_theResult____h502870[6] ? + (_theResult____h502871[6] ? 6'd50 : - (_theResult____h502870[5] ? + (_theResult____h502871[5] ? 6'd51 : - (_theResult____h502870[4] ? + (_theResult____h502871[4] ? 6'd52 : - (_theResult____h502870[3] ? + (_theResult____h502871[3] ? 6'd53 : - (_theResult____h502870[2] ? + (_theResult____h502871[2] ? 6'd54 : - (_theResult____h502870[1] ? + (_theResult____h502871[1] ? 6'd55 : - (_theResult____h502870[0] ? + (_theResult____h502871[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 = - (_theResult____h581027[56] ? + (_theResult____h581028[56] ? 6'd0 : - (_theResult____h581027[55] ? + (_theResult____h581028[55] ? 6'd1 : - (_theResult____h581027[54] ? + (_theResult____h581028[54] ? 6'd2 : - (_theResult____h581027[53] ? + (_theResult____h581028[53] ? 6'd3 : - (_theResult____h581027[52] ? + (_theResult____h581028[52] ? 6'd4 : - (_theResult____h581027[51] ? + (_theResult____h581028[51] ? 6'd5 : - (_theResult____h581027[50] ? + (_theResult____h581028[50] ? 6'd6 : - (_theResult____h581027[49] ? + (_theResult____h581028[49] ? 6'd7 : - (_theResult____h581027[48] ? + (_theResult____h581028[48] ? 6'd8 : - (_theResult____h581027[47] ? + (_theResult____h581028[47] ? 6'd9 : - (_theResult____h581027[46] ? + (_theResult____h581028[46] ? 6'd10 : - (_theResult____h581027[45] ? + (_theResult____h581028[45] ? 6'd11 : - (_theResult____h581027[44] ? + (_theResult____h581028[44] ? 6'd12 : - (_theResult____h581027[43] ? + (_theResult____h581028[43] ? 6'd13 : - (_theResult____h581027[42] ? + (_theResult____h581028[42] ? 6'd14 : - (_theResult____h581027[41] ? + (_theResult____h581028[41] ? 6'd15 : - (_theResult____h581027[40] ? + (_theResult____h581028[40] ? 6'd16 : - (_theResult____h581027[39] ? + (_theResult____h581028[39] ? 6'd17 : - (_theResult____h581027[38] ? + (_theResult____h581028[38] ? 6'd18 : - (_theResult____h581027[37] ? + (_theResult____h581028[37] ? 6'd19 : - (_theResult____h581027[36] ? + (_theResult____h581028[36] ? 6'd20 : - (_theResult____h581027[35] ? + (_theResult____h581028[35] ? 6'd21 : - (_theResult____h581027[34] ? + (_theResult____h581028[34] ? 6'd22 : - (_theResult____h581027[33] ? + (_theResult____h581028[33] ? 6'd23 : - (_theResult____h581027[32] ? + (_theResult____h581028[32] ? 6'd24 : - (_theResult____h581027[31] ? + (_theResult____h581028[31] ? 6'd25 : - (_theResult____h581027[30] ? + (_theResult____h581028[30] ? 6'd26 : - (_theResult____h581027[29] ? + (_theResult____h581028[29] ? 6'd27 : - (_theResult____h581027[28] ? + (_theResult____h581028[28] ? 6'd28 : - (_theResult____h581027[27] ? + (_theResult____h581028[27] ? 6'd29 : - (_theResult____h581027[26] ? + (_theResult____h581028[26] ? 6'd30 : - (_theResult____h581027[25] ? + (_theResult____h581028[25] ? 6'd31 : - (_theResult____h581027[24] ? + (_theResult____h581028[24] ? 6'd32 : - (_theResult____h581027[23] ? + (_theResult____h581028[23] ? 6'd33 : - (_theResult____h581027[22] ? + (_theResult____h581028[22] ? 6'd34 : - (_theResult____h581027[21] ? + (_theResult____h581028[21] ? 6'd35 : - (_theResult____h581027[20] ? + (_theResult____h581028[20] ? 6'd36 : - (_theResult____h581027[19] ? + (_theResult____h581028[19] ? 6'd37 : - (_theResult____h581027[18] ? + (_theResult____h581028[18] ? 6'd38 : - (_theResult____h581027[17] ? + (_theResult____h581028[17] ? 6'd39 : - (_theResult____h581027[16] ? + (_theResult____h581028[16] ? 6'd40 : - (_theResult____h581027[15] ? + (_theResult____h581028[15] ? 6'd41 : - (_theResult____h581027[14] ? + (_theResult____h581028[14] ? 6'd42 : - (_theResult____h581027[13] ? + (_theResult____h581028[13] ? 6'd43 : - (_theResult____h581027[12] ? + (_theResult____h581028[12] ? 6'd44 : - (_theResult____h581027[11] ? + (_theResult____h581028[11] ? 6'd45 : - (_theResult____h581027[10] ? + (_theResult____h581028[10] ? 6'd46 : - (_theResult____h581027[9] ? + (_theResult____h581028[9] ? 6'd47 : - (_theResult____h581027[8] ? + (_theResult____h581028[8] ? 6'd48 : - (_theResult____h581027[7] ? + (_theResult____h581028[7] ? 6'd49 : - (_theResult____h581027[6] ? + (_theResult____h581028[6] ? 6'd50 : - (_theResult____h581027[5] ? + (_theResult____h581028[5] ? 6'd51 : - (_theResult____h581027[4] ? + (_theResult____h581028[4] ? 6'd52 : - (_theResult____h581027[3] ? + (_theResult____h581028[3] ? 6'd53 : - (_theResult____h581027[2] ? + (_theResult____h581028[2] ? 6'd54 : - (_theResult____h581027[1] ? + (_theResult____h581028[1] ? 6'd55 : - (_theResult____h581027[0] ? + (_theResult____h581028[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 = - (_theResult____h363725[56] ? + (_theResult____h363726[56] ? 6'd0 : - (_theResult____h363725[55] ? + (_theResult____h363726[55] ? 6'd1 : - (_theResult____h363725[54] ? + (_theResult____h363726[54] ? 6'd2 : - (_theResult____h363725[53] ? + (_theResult____h363726[53] ? 6'd3 : - (_theResult____h363725[52] ? + (_theResult____h363726[52] ? 6'd4 : - (_theResult____h363725[51] ? + (_theResult____h363726[51] ? 6'd5 : - (_theResult____h363725[50] ? + (_theResult____h363726[50] ? 6'd6 : - (_theResult____h363725[49] ? + (_theResult____h363726[49] ? 6'd7 : - (_theResult____h363725[48] ? + (_theResult____h363726[48] ? 6'd8 : - (_theResult____h363725[47] ? + (_theResult____h363726[47] ? 6'd9 : - (_theResult____h363725[46] ? + (_theResult____h363726[46] ? 6'd10 : - (_theResult____h363725[45] ? + (_theResult____h363726[45] ? 6'd11 : - (_theResult____h363725[44] ? + (_theResult____h363726[44] ? 6'd12 : - (_theResult____h363725[43] ? + (_theResult____h363726[43] ? 6'd13 : - (_theResult____h363725[42] ? + (_theResult____h363726[42] ? 6'd14 : - (_theResult____h363725[41] ? + (_theResult____h363726[41] ? 6'd15 : - (_theResult____h363725[40] ? + (_theResult____h363726[40] ? 6'd16 : - (_theResult____h363725[39] ? + (_theResult____h363726[39] ? 6'd17 : - (_theResult____h363725[38] ? + (_theResult____h363726[38] ? 6'd18 : - (_theResult____h363725[37] ? + (_theResult____h363726[37] ? 6'd19 : - (_theResult____h363725[36] ? + (_theResult____h363726[36] ? 6'd20 : - (_theResult____h363725[35] ? + (_theResult____h363726[35] ? 6'd21 : - (_theResult____h363725[34] ? + (_theResult____h363726[34] ? 6'd22 : - (_theResult____h363725[33] ? + (_theResult____h363726[33] ? 6'd23 : - (_theResult____h363725[32] ? + (_theResult____h363726[32] ? 6'd24 : - (_theResult____h363725[31] ? + (_theResult____h363726[31] ? 6'd25 : - (_theResult____h363725[30] ? + (_theResult____h363726[30] ? 6'd26 : - (_theResult____h363725[29] ? + (_theResult____h363726[29] ? 6'd27 : - (_theResult____h363725[28] ? + (_theResult____h363726[28] ? 6'd28 : - (_theResult____h363725[27] ? + (_theResult____h363726[27] ? 6'd29 : - (_theResult____h363725[26] ? + (_theResult____h363726[26] ? 6'd30 : - (_theResult____h363725[25] ? + (_theResult____h363726[25] ? 6'd31 : - (_theResult____h363725[24] ? + (_theResult____h363726[24] ? 6'd32 : - (_theResult____h363725[23] ? + (_theResult____h363726[23] ? 6'd33 : - (_theResult____h363725[22] ? + (_theResult____h363726[22] ? 6'd34 : - (_theResult____h363725[21] ? + (_theResult____h363726[21] ? 6'd35 : - (_theResult____h363725[20] ? + (_theResult____h363726[20] ? 6'd36 : - (_theResult____h363725[19] ? + (_theResult____h363726[19] ? 6'd37 : - (_theResult____h363725[18] ? + (_theResult____h363726[18] ? 6'd38 : - (_theResult____h363725[17] ? + (_theResult____h363726[17] ? 6'd39 : - (_theResult____h363725[16] ? + (_theResult____h363726[16] ? 6'd40 : - (_theResult____h363725[15] ? + (_theResult____h363726[15] ? 6'd41 : - (_theResult____h363725[14] ? + (_theResult____h363726[14] ? 6'd42 : - (_theResult____h363725[13] ? + (_theResult____h363726[13] ? 6'd43 : - (_theResult____h363725[12] ? + (_theResult____h363726[12] ? 6'd44 : - (_theResult____h363725[11] ? + (_theResult____h363726[11] ? 6'd45 : - (_theResult____h363725[10] ? + (_theResult____h363726[10] ? 6'd46 : - (_theResult____h363725[9] ? + (_theResult____h363726[9] ? 6'd47 : - (_theResult____h363725[8] ? + (_theResult____h363726[8] ? 6'd48 : - (_theResult____h363725[7] ? + (_theResult____h363726[7] ? 6'd49 : - (_theResult____h363725[6] ? + (_theResult____h363726[6] ? 6'd50 : - (_theResult____h363725[5] ? + (_theResult____h363726[5] ? 6'd51 : - (_theResult____h363725[4] ? + (_theResult____h363726[4] ? 6'd52 : - (_theResult____h363725[3] ? + (_theResult____h363726[3] ? 6'd53 : - (_theResult____h363725[2] ? + (_theResult____h363726[2] ? 6'd54 : - (_theResult____h363725[1] ? + (_theResult____h363726[1] ? 6'd55 : - (_theResult____h363725[0] ? + (_theResult____h363726[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 = - (_theResult____h409422[56] ? + (_theResult____h409423[56] ? 6'd0 : - (_theResult____h409422[55] ? + (_theResult____h409423[55] ? 6'd1 : - (_theResult____h409422[54] ? + (_theResult____h409423[54] ? 6'd2 : - (_theResult____h409422[53] ? + (_theResult____h409423[53] ? 6'd3 : - (_theResult____h409422[52] ? + (_theResult____h409423[52] ? 6'd4 : - (_theResult____h409422[51] ? + (_theResult____h409423[51] ? 6'd5 : - (_theResult____h409422[50] ? + (_theResult____h409423[50] ? 6'd6 : - (_theResult____h409422[49] ? + (_theResult____h409423[49] ? 6'd7 : - (_theResult____h409422[48] ? + (_theResult____h409423[48] ? 6'd8 : - (_theResult____h409422[47] ? + (_theResult____h409423[47] ? 6'd9 : - (_theResult____h409422[46] ? + (_theResult____h409423[46] ? 6'd10 : - (_theResult____h409422[45] ? + (_theResult____h409423[45] ? 6'd11 : - (_theResult____h409422[44] ? + (_theResult____h409423[44] ? 6'd12 : - (_theResult____h409422[43] ? + (_theResult____h409423[43] ? 6'd13 : - (_theResult____h409422[42] ? + (_theResult____h409423[42] ? 6'd14 : - (_theResult____h409422[41] ? + (_theResult____h409423[41] ? 6'd15 : - (_theResult____h409422[40] ? + (_theResult____h409423[40] ? 6'd16 : - (_theResult____h409422[39] ? + (_theResult____h409423[39] ? 6'd17 : - (_theResult____h409422[38] ? + (_theResult____h409423[38] ? 6'd18 : - (_theResult____h409422[37] ? + (_theResult____h409423[37] ? 6'd19 : - (_theResult____h409422[36] ? + (_theResult____h409423[36] ? 6'd20 : - (_theResult____h409422[35] ? + (_theResult____h409423[35] ? 6'd21 : - (_theResult____h409422[34] ? + (_theResult____h409423[34] ? 6'd22 : - (_theResult____h409422[33] ? + (_theResult____h409423[33] ? 6'd23 : - (_theResult____h409422[32] ? + (_theResult____h409423[32] ? 6'd24 : - (_theResult____h409422[31] ? + (_theResult____h409423[31] ? 6'd25 : - (_theResult____h409422[30] ? + (_theResult____h409423[30] ? 6'd26 : - (_theResult____h409422[29] ? + (_theResult____h409423[29] ? 6'd27 : - (_theResult____h409422[28] ? + (_theResult____h409423[28] ? 6'd28 : - (_theResult____h409422[27] ? + (_theResult____h409423[27] ? 6'd29 : - (_theResult____h409422[26] ? + (_theResult____h409423[26] ? 6'd30 : - (_theResult____h409422[25] ? + (_theResult____h409423[25] ? 6'd31 : - (_theResult____h409422[24] ? + (_theResult____h409423[24] ? 6'd32 : - (_theResult____h409422[23] ? + (_theResult____h409423[23] ? 6'd33 : - (_theResult____h409422[22] ? + (_theResult____h409423[22] ? 6'd34 : - (_theResult____h409422[21] ? + (_theResult____h409423[21] ? 6'd35 : - (_theResult____h409422[20] ? + (_theResult____h409423[20] ? 6'd36 : - (_theResult____h409422[19] ? + (_theResult____h409423[19] ? 6'd37 : - (_theResult____h409422[18] ? + (_theResult____h409423[18] ? 6'd38 : - (_theResult____h409422[17] ? + (_theResult____h409423[17] ? 6'd39 : - (_theResult____h409422[16] ? + (_theResult____h409423[16] ? 6'd40 : - (_theResult____h409422[15] ? + (_theResult____h409423[15] ? 6'd41 : - (_theResult____h409422[14] ? + (_theResult____h409423[14] ? 6'd42 : - (_theResult____h409422[13] ? + (_theResult____h409423[13] ? 6'd43 : - (_theResult____h409422[12] ? + (_theResult____h409423[12] ? 6'd44 : - (_theResult____h409422[11] ? + (_theResult____h409423[11] ? 6'd45 : - (_theResult____h409422[10] ? + (_theResult____h409423[10] ? 6'd46 : - (_theResult____h409422[9] ? + (_theResult____h409423[9] ? 6'd47 : - (_theResult____h409422[8] ? + (_theResult____h409423[8] ? 6'd48 : - (_theResult____h409422[7] ? + (_theResult____h409423[7] ? 6'd49 : - (_theResult____h409422[6] ? + (_theResult____h409423[6] ? 6'd50 : - (_theResult____h409422[5] ? + (_theResult____h409423[5] ? 6'd51 : - (_theResult____h409422[4] ? + (_theResult____h409423[4] ? 6'd52 : - (_theResult____h409422[3] ? + (_theResult____h409423[3] ? 6'd53 : - (_theResult____h409422[2] ? + (_theResult____h409423[2] ? 6'd54 : - (_theResult____h409422[1] ? + (_theResult____h409423[1] ? 6'd55 : - (_theResult____h409422[0] ? + (_theResult____h409423[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 = - (_theResult____h455117[56] ? + (_theResult____h455118[56] ? 6'd0 : - (_theResult____h455117[55] ? + (_theResult____h455118[55] ? 6'd1 : - (_theResult____h455117[54] ? + (_theResult____h455118[54] ? 6'd2 : - (_theResult____h455117[53] ? + (_theResult____h455118[53] ? 6'd3 : - (_theResult____h455117[52] ? + (_theResult____h455118[52] ? 6'd4 : - (_theResult____h455117[51] ? + (_theResult____h455118[51] ? 6'd5 : - (_theResult____h455117[50] ? + (_theResult____h455118[50] ? 6'd6 : - (_theResult____h455117[49] ? + (_theResult____h455118[49] ? 6'd7 : - (_theResult____h455117[48] ? + (_theResult____h455118[48] ? 6'd8 : - (_theResult____h455117[47] ? + (_theResult____h455118[47] ? 6'd9 : - (_theResult____h455117[46] ? + (_theResult____h455118[46] ? 6'd10 : - (_theResult____h455117[45] ? + (_theResult____h455118[45] ? 6'd11 : - (_theResult____h455117[44] ? + (_theResult____h455118[44] ? 6'd12 : - (_theResult____h455117[43] ? + (_theResult____h455118[43] ? 6'd13 : - (_theResult____h455117[42] ? + (_theResult____h455118[42] ? 6'd14 : - (_theResult____h455117[41] ? + (_theResult____h455118[41] ? 6'd15 : - (_theResult____h455117[40] ? + (_theResult____h455118[40] ? 6'd16 : - (_theResult____h455117[39] ? + (_theResult____h455118[39] ? 6'd17 : - (_theResult____h455117[38] ? + (_theResult____h455118[38] ? 6'd18 : - (_theResult____h455117[37] ? + (_theResult____h455118[37] ? 6'd19 : - (_theResult____h455117[36] ? + (_theResult____h455118[36] ? 6'd20 : - (_theResult____h455117[35] ? + (_theResult____h455118[35] ? 6'd21 : - (_theResult____h455117[34] ? + (_theResult____h455118[34] ? 6'd22 : - (_theResult____h455117[33] ? + (_theResult____h455118[33] ? 6'd23 : - (_theResult____h455117[32] ? + (_theResult____h455118[32] ? 6'd24 : - (_theResult____h455117[31] ? + (_theResult____h455118[31] ? 6'd25 : - (_theResult____h455117[30] ? + (_theResult____h455118[30] ? 6'd26 : - (_theResult____h455117[29] ? + (_theResult____h455118[29] ? 6'd27 : - (_theResult____h455117[28] ? + (_theResult____h455118[28] ? 6'd28 : - (_theResult____h455117[27] ? + (_theResult____h455118[27] ? 6'd29 : - (_theResult____h455117[26] ? + (_theResult____h455118[26] ? 6'd30 : - (_theResult____h455117[25] ? + (_theResult____h455118[25] ? 6'd31 : - (_theResult____h455117[24] ? + (_theResult____h455118[24] ? 6'd32 : - (_theResult____h455117[23] ? + (_theResult____h455118[23] ? 6'd33 : - (_theResult____h455117[22] ? + (_theResult____h455118[22] ? 6'd34 : - (_theResult____h455117[21] ? + (_theResult____h455118[21] ? 6'd35 : - (_theResult____h455117[20] ? + (_theResult____h455118[20] ? 6'd36 : - (_theResult____h455117[19] ? + (_theResult____h455118[19] ? 6'd37 : - (_theResult____h455117[18] ? + (_theResult____h455118[18] ? 6'd38 : - (_theResult____h455117[17] ? + (_theResult____h455118[17] ? 6'd39 : - (_theResult____h455117[16] ? + (_theResult____h455118[16] ? 6'd40 : - (_theResult____h455117[15] ? + (_theResult____h455118[15] ? 6'd41 : - (_theResult____h455117[14] ? + (_theResult____h455118[14] ? 6'd42 : - (_theResult____h455117[13] ? + (_theResult____h455118[13] ? 6'd43 : - (_theResult____h455117[12] ? + (_theResult____h455118[12] ? 6'd44 : - (_theResult____h455117[11] ? + (_theResult____h455118[11] ? 6'd45 : - (_theResult____h455117[10] ? + (_theResult____h455118[10] ? 6'd46 : - (_theResult____h455117[9] ? + (_theResult____h455118[9] ? 6'd47 : - (_theResult____h455117[8] ? + (_theResult____h455118[8] ? 6'd48 : - (_theResult____h455117[7] ? + (_theResult____h455118[7] ? 6'd49 : - (_theResult____h455117[6] ? + (_theResult____h455118[6] ? 6'd50 : - (_theResult____h455117[5] ? + (_theResult____h455118[5] ? 6'd51 : - (_theResult____h455117[4] ? + (_theResult____h455118[4] ? 6'd52 : - (_theResult____h455117[3] ? + (_theResult____h455118[3] ? 6'd53 : - (_theResult____h455117[2] ? + (_theResult____h455118[2] ? 6'd54 : - (_theResult____h455117[1] ? + (_theResult____h455118[1] ? 6'd55 : - (_theResult____h455117[0] ? + (_theResult____h455118[0] ? 6'd56 : 6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) - 6'd1 ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 = - (_theResult___fst_exp__h549959 == 11'd2047) ? + (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20908,10 +20908,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 = - (_theResult___fst_exp__h549959 == 11'd2047) ? + (_theResult___fst_exp__h549960 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -20919,10 +20919,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 = - (_theResult___fst_exp__h511106 == 11'd2047) ? + (_theResult___fst_exp__h511107 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -20930,10 +20930,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 = - (_theResult___fst_exp__h589263 == 11'd2047) ? + (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20941,10 +20941,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ; assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 = - (_theResult___fst_exp__h589263 == 11'd2047) ? + (_theResult___fst_exp__h589264 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -20952,538 +20952,538 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 = - (guard__h346096 == 2'b0 || + (guard__h346097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h354197 : - _theResult___exp__h354713 ; + _theResult___fst_exp__h354198 : + _theResult___exp__h354714 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 = - (guard__h346096 == 2'b0) ? - _theResult___fst_exp__h354197 : + (guard__h346097 == 2'b0) ? + _theResult___fst_exp__h354198 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h354713 : - _theResult___fst_exp__h354197) ; + _theResult___exp__h354714 : + _theResult___fst_exp__h354198) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 = - (guard__h346096 == 2'b0 || + (guard__h346097 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h354191[56:34] : - _theResult___sfd__h354714 ; + sfdin__h354192[56:34] : + _theResult___sfd__h354715 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 = - (guard__h346096 == 2'b0) ? - sfdin__h354191[56:34] : + (guard__h346097 == 2'b0) ? + sfdin__h354192[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h354714 : - sfdin__h354191[56:34]) ; + _theResult___sfd__h354715 : + sfdin__h354192[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 = - (guard__h391795 == 2'b0 || + (guard__h391796 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h399894 : - _theResult___exp__h400410 ; + _theResult___fst_exp__h399895 : + _theResult___exp__h400411 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 = - (guard__h391795 == 2'b0) ? - _theResult___fst_exp__h399894 : + (guard__h391796 == 2'b0) ? + _theResult___fst_exp__h399895 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h400410 : - _theResult___fst_exp__h399894) ; + _theResult___exp__h400411 : + _theResult___fst_exp__h399895) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 = - (guard__h391795 == 2'b0 || + (guard__h391796 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h399888[56:34] : - _theResult___sfd__h400411 ; + sfdin__h399889[56:34] : + _theResult___sfd__h400412 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 = - (guard__h391795 == 2'b0) ? - sfdin__h399888[56:34] : + (guard__h391796 == 2'b0) ? + sfdin__h399889[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h400411 : - sfdin__h399888[56:34]) ; + _theResult___sfd__h400412 : + sfdin__h399889[56:34]) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 = - (guard__h437490 == 2'b0 || + (guard__h437491 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h445589 : - _theResult___exp__h446105 ; + _theResult___fst_exp__h445590 : + _theResult___exp__h446106 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 = - (guard__h437490 == 2'b0) ? - _theResult___fst_exp__h445589 : + (guard__h437491 == 2'b0) ? + _theResult___fst_exp__h445590 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h446105 : - _theResult___fst_exp__h445589) ; + _theResult___exp__h446106 : + _theResult___fst_exp__h445590) ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 = - (guard__h437490 == 2'b0 || + (guard__h437491 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h445583[56:34] : - _theResult___sfd__h446106 ; + sfdin__h445584[56:34] : + _theResult___sfd__h446107 ; assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 = - (guard__h437490 == 2'b0) ? - sfdin__h445583[56:34] : + (guard__h437491 == 2'b0) ? + sfdin__h445584[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h446106 : - sfdin__h445583[56:34]) ; + _theResult___sfd__h446107 : + sfdin__h445584[56:34]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 = - (guard__h541733 == 2'b0 || + (guard__h541734 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h549959 : - _theResult___exp__h550688 ; + _theResult___fst_exp__h549960 : + _theResult___exp__h550689 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 = - (guard__h541733 == 2'b0) ? - _theResult___fst_exp__h549959 : + (guard__h541734 == 2'b0) ? + _theResult___fst_exp__h549960 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h550688 : - _theResult___fst_exp__h549959) ; + _theResult___exp__h550689 : + _theResult___fst_exp__h549960) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 = - (guard__h541733 == 2'b0 || + (guard__h541734 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - sfdin__h549953[56:5] : - _theResult___sfd__h550689 ; + sfdin__h549954[56:5] : + _theResult___sfd__h550690 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 = - (guard__h541733 == 2'b0) ? - sfdin__h549953[56:5] : + (guard__h541734 == 2'b0) ? + sfdin__h549954[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h550689 : - sfdin__h549953[56:5]) ; + _theResult___sfd__h550690 : + sfdin__h549954[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 = - (guard__h502880 == 2'b0 || + (guard__h502881 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h511106 : - _theResult___exp__h511835 ; + _theResult___fst_exp__h511107 : + _theResult___exp__h511836 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 = - (guard__h502880 == 2'b0) ? - _theResult___fst_exp__h511106 : + (guard__h502881 == 2'b0) ? + _theResult___fst_exp__h511107 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h511835 : - _theResult___fst_exp__h511106) ; + _theResult___exp__h511836 : + _theResult___fst_exp__h511107) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 = - (guard__h502880 == 2'b0 || + (guard__h502881 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - sfdin__h511100[56:5] : - _theResult___sfd__h511836 ; + sfdin__h511101[56:5] : + _theResult___sfd__h511837 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 = - (guard__h502880 == 2'b0) ? - sfdin__h511100[56:5] : + (guard__h502881 == 2'b0) ? + sfdin__h511101[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h511836 : - sfdin__h511100[56:5]) ; + _theResult___sfd__h511837 : + sfdin__h511101[56:5]) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 = - (guard__h581037 == 2'b0 || + (guard__h581038 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h589263 : - _theResult___exp__h589992 ; + _theResult___fst_exp__h589264 : + _theResult___exp__h589993 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 = - (guard__h581037 == 2'b0) ? - _theResult___fst_exp__h589263 : + (guard__h581038 == 2'b0) ? + _theResult___fst_exp__h589264 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h589992 : - _theResult___fst_exp__h589263) ; + _theResult___exp__h589993 : + _theResult___fst_exp__h589264) ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 = - (guard__h581037 == 2'b0 || + (guard__h581038 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - sfdin__h589257[56:5] : - _theResult___sfd__h589993 ; + sfdin__h589258[56:5] : + _theResult___sfd__h589994 ; assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 = - (guard__h581037 == 2'b0) ? - sfdin__h589257[56:5] : + (guard__h581038 == 2'b0) ? + sfdin__h589258[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h589993 : - sfdin__h589257[56:5]) ; + _theResult___sfd__h589994 : + sfdin__h589258[56:5]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 = - (guard__h363735 == 2'b0 || + (guard__h363736 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h371963 : - _theResult___exp__h372479 ; + _theResult___fst_exp__h371964 : + _theResult___exp__h372480 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 = - (guard__h363735 == 2'b0) ? - _theResult___fst_exp__h371963 : + (guard__h363736 == 2'b0) ? + _theResult___fst_exp__h371964 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h372479 : - _theResult___fst_exp__h371963) ; + _theResult___exp__h372480 : + _theResult___fst_exp__h371964) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 = - (guard__h363735 == 2'b0 || + (guard__h363736 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - sfdin__h371957[56:34] : - _theResult___sfd__h372480 ; + sfdin__h371958[56:34] : + _theResult___sfd__h372481 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 = - (guard__h363735 == 2'b0) ? - sfdin__h371957[56:34] : + (guard__h363736 == 2'b0) ? + sfdin__h371958[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h372480 : - sfdin__h371957[56:34]) ; + _theResult___sfd__h372481 : + sfdin__h371958[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 = - (guard__h409432 == 2'b0 || + (guard__h409433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h417660 : - _theResult___exp__h418176 ; + _theResult___fst_exp__h417661 : + _theResult___exp__h418177 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 = - (guard__h409432 == 2'b0) ? - _theResult___fst_exp__h417660 : + (guard__h409433 == 2'b0) ? + _theResult___fst_exp__h417661 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h418176 : - _theResult___fst_exp__h417660) ; + _theResult___exp__h418177 : + _theResult___fst_exp__h417661) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 = - (guard__h409432 == 2'b0 || + (guard__h409433 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - sfdin__h417654[56:34] : - _theResult___sfd__h418177 ; + sfdin__h417655[56:34] : + _theResult___sfd__h418178 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 = - (guard__h409432 == 2'b0) ? - sfdin__h417654[56:34] : + (guard__h409433 == 2'b0) ? + sfdin__h417655[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h418177 : - sfdin__h417654[56:34]) ; + _theResult___sfd__h418178 : + sfdin__h417655[56:34]) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 = - (guard__h455127 == 2'b0 || + (guard__h455128 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h463355 : - _theResult___exp__h463871 ; + _theResult___fst_exp__h463356 : + _theResult___exp__h463872 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 = - (guard__h455127 == 2'b0) ? - _theResult___fst_exp__h463355 : + (guard__h455128 == 2'b0) ? + _theResult___fst_exp__h463356 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h463871 : - _theResult___fst_exp__h463355) ; + _theResult___exp__h463872 : + _theResult___fst_exp__h463356) ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 = - (guard__h455127 == 2'b0 || + (guard__h455128 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - sfdin__h463349[56:34] : - _theResult___sfd__h463872 ; + sfdin__h463350[56:34] : + _theResult___sfd__h463873 ; assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 = - (guard__h455127 == 2'b0) ? - sfdin__h463349[56:34] : + (guard__h455128 == 2'b0) ? + sfdin__h463350[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h463872 : - sfdin__h463349[56:34]) ; + _theResult___sfd__h463873 : + sfdin__h463350[56:34]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 = - (guard__h532421 == 2'b0 || + (guard__h532422 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h540382 : - _theResult___exp__h541037 ; + _theResult___fst_exp__h540383 : + _theResult___exp__h541038 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 = - (guard__h532421 == 2'b0) ? - _theResult___fst_exp__h540382 : + (guard__h532422 == 2'b0) ? + _theResult___fst_exp__h540383 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h541037 : - _theResult___fst_exp__h540382) ; + _theResult___exp__h541038 : + _theResult___fst_exp__h540383) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 = - (guard__h550802 == 2'b0 || + (guard__h550803 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___fst_exp__h558792 : - _theResult___exp__h559472 ; + _theResult___fst_exp__h558793 : + _theResult___exp__h559473 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 = - (guard__h550802 == 2'b0) ? - _theResult___fst_exp__h558792 : + (guard__h550803 == 2'b0) ? + _theResult___fst_exp__h558793 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___exp__h559472 : - _theResult___fst_exp__h558792) ; + _theResult___exp__h559473 : + _theResult___fst_exp__h558793) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 = - (guard__h532421 == 2'b0 || + (guard__h532422 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h540333[56:5] : - _theResult___sfd__h541038 ; + _theResult___snd__h540334[56:5] : + _theResult___sfd__h541039 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 = - (guard__h532421 == 2'b0) ? - _theResult___snd__h540333[56:5] : + (guard__h532422 == 2'b0) ? + _theResult___snd__h540334[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h541038 : - _theResult___snd__h540333[56:5]) ; + _theResult___sfd__h541039 : + _theResult___snd__h540334[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 = - (guard__h550802 == 2'b0 || + (guard__h550803 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___snd__h558738[56:5] : - _theResult___sfd__h559473 ; + _theResult___snd__h558739[56:5] : + _theResult___sfd__h559474 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 = - (guard__h550802 == 2'b0) ? - _theResult___snd__h558738[56:5] : + (guard__h550803 == 2'b0) ? + _theResult___snd__h558739[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ? - _theResult___sfd__h559473 : - _theResult___snd__h558738[56:5]) ; + _theResult___sfd__h559474 : + _theResult___snd__h558739[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 = - (guard__h493568 == 2'b0 || + (guard__h493569 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h501529 : - _theResult___exp__h502184 ; + _theResult___fst_exp__h501530 : + _theResult___exp__h502185 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 = - (guard__h493568 == 2'b0) ? - _theResult___fst_exp__h501529 : + (guard__h493569 == 2'b0) ? + _theResult___fst_exp__h501530 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h502184 : - _theResult___fst_exp__h501529) ; + _theResult___exp__h502185 : + _theResult___fst_exp__h501530) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 = - (guard__h511949 == 2'b0 || + (guard__h511950 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___fst_exp__h519939 : - _theResult___exp__h520619 ; + _theResult___fst_exp__h519940 : + _theResult___exp__h520620 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 = - (guard__h511949 == 2'b0) ? - _theResult___fst_exp__h519939 : + (guard__h511950 == 2'b0) ? + _theResult___fst_exp__h519940 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___exp__h520619 : - _theResult___fst_exp__h519939) ; + _theResult___exp__h520620 : + _theResult___fst_exp__h519940) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 = - (guard__h493568 == 2'b0 || + (guard__h493569 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h501480[56:5] : - _theResult___sfd__h502185 ; + _theResult___snd__h501481[56:5] : + _theResult___sfd__h502186 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 = - (guard__h493568 == 2'b0) ? - _theResult___snd__h501480[56:5] : + (guard__h493569 == 2'b0) ? + _theResult___snd__h501481[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h502185 : - _theResult___snd__h501480[56:5]) ; + _theResult___sfd__h502186 : + _theResult___snd__h501481[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 = - (guard__h511949 == 2'b0 || + (guard__h511950 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___snd__h519885[56:5] : - _theResult___sfd__h520620 ; + _theResult___snd__h519886[56:5] : + _theResult___sfd__h520621 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 = - (guard__h511949 == 2'b0) ? - _theResult___snd__h519885[56:5] : + (guard__h511950 == 2'b0) ? + _theResult___snd__h519886[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ? - _theResult___sfd__h520620 : - _theResult___snd__h519885[56:5]) ; + _theResult___sfd__h520621 : + _theResult___snd__h519886[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 = - (guard__h571725 == 2'b0 || + (guard__h571726 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h579686 : - _theResult___exp__h580341 ; + _theResult___fst_exp__h579687 : + _theResult___exp__h580342 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 = - (guard__h571725 == 2'b0) ? - _theResult___fst_exp__h579686 : + (guard__h571726 == 2'b0) ? + _theResult___fst_exp__h579687 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h580341 : - _theResult___fst_exp__h579686) ; + _theResult___exp__h580342 : + _theResult___fst_exp__h579687) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 = - (guard__h590106 == 2'b0 || + (guard__h590107 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___fst_exp__h598096 : - _theResult___exp__h598776 ; + _theResult___fst_exp__h598097 : + _theResult___exp__h598777 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 = - (guard__h590106 == 2'b0) ? - _theResult___fst_exp__h598096 : + (guard__h590107 == 2'b0) ? + _theResult___fst_exp__h598097 : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___exp__h598776 : - _theResult___fst_exp__h598096) ; + _theResult___exp__h598777 : + _theResult___fst_exp__h598097) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 = - (guard__h571725 == 2'b0 || + (guard__h571726 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h579637[56:5] : - _theResult___sfd__h580342 ; + _theResult___snd__h579638[56:5] : + _theResult___sfd__h580343 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 = - (guard__h571725 == 2'b0) ? - _theResult___snd__h579637[56:5] : + (guard__h571726 == 2'b0) ? + _theResult___snd__h579638[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h580342 : - _theResult___snd__h579637[56:5]) ; + _theResult___sfd__h580343 : + _theResult___snd__h579638[56:5]) ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 = - (guard__h590106 == 2'b0 || + (guard__h590107 == 2'b0 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___snd__h598042[56:5] : - _theResult___sfd__h598777 ; + _theResult___snd__h598043[56:5] : + _theResult___sfd__h598778 ; assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 = - (guard__h590106 == 2'b0) ? - _theResult___snd__h598042[56:5] : + (guard__h590107 == 2'b0) ? + _theResult___snd__h598043[56:5] : ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ? - _theResult___sfd__h598777 : - _theResult___snd__h598042[56:5]) ; + _theResult___sfd__h598778 : + _theResult___snd__h598043[56:5]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 = - (guard__h354805 == 2'b0 || + (guard__h354806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h362853 : - _theResult___exp__h363295 ; + _theResult___fst_exp__h362854 : + _theResult___exp__h363296 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 = - (guard__h354805 == 2'b0) ? - _theResult___fst_exp__h362853 : + (guard__h354806 == 2'b0) ? + _theResult___fst_exp__h362854 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h363295 : - _theResult___fst_exp__h362853) ; + _theResult___exp__h363296 : + _theResult___fst_exp__h362854) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 = - (guard__h372571 == 2'b0 || + (guard__h372572 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___fst_exp__h380648 : - _theResult___exp__h381115 ; + _theResult___fst_exp__h380649 : + _theResult___exp__h381116 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 = - (guard__h372571 == 2'b0) ? - _theResult___fst_exp__h380648 : + (guard__h372572 == 2'b0) ? + _theResult___fst_exp__h380649 : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___exp__h381115 : - _theResult___fst_exp__h380648) ; + _theResult___exp__h381116 : + _theResult___fst_exp__h380649) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 = - (guard__h354805 == 2'b0 || + (guard__h354806 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h362804[56:34] : - _theResult___sfd__h363296 ; + _theResult___snd__h362805[56:34] : + _theResult___sfd__h363297 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 = - (guard__h354805 == 2'b0) ? - _theResult___snd__h362804[56:34] : + (guard__h354806 == 2'b0) ? + _theResult___snd__h362805[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h363296 : - _theResult___snd__h362804[56:34]) ; + _theResult___sfd__h363297 : + _theResult___snd__h362805[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 = - (guard__h372571 == 2'b0 || + (guard__h372572 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ? - _theResult___snd__h380594[56:34] : - _theResult___sfd__h381116 ; + _theResult___snd__h380595[56:34] : + _theResult___sfd__h381117 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 = - (guard__h372571 == 2'b0) ? - _theResult___snd__h380594[56:34] : + (guard__h372572 == 2'b0) ? + _theResult___snd__h380595[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? - _theResult___sfd__h381116 : - _theResult___snd__h380594[56:34]) ; + _theResult___sfd__h381117 : + _theResult___snd__h380595[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 = - (guard__h400502 == 2'b0 || + (guard__h400503 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h408550 : - _theResult___exp__h408992 ; + _theResult___fst_exp__h408551 : + _theResult___exp__h408993 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 = - (guard__h400502 == 2'b0) ? - _theResult___fst_exp__h408550 : + (guard__h400503 == 2'b0) ? + _theResult___fst_exp__h408551 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h408992 : - _theResult___fst_exp__h408550) ; + _theResult___exp__h408993 : + _theResult___fst_exp__h408551) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 = - (guard__h418268 == 2'b0 || + (guard__h418269 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___fst_exp__h426345 : - _theResult___exp__h426812 ; + _theResult___fst_exp__h426346 : + _theResult___exp__h426813 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 = - (guard__h418268 == 2'b0) ? - _theResult___fst_exp__h426345 : + (guard__h418269 == 2'b0) ? + _theResult___fst_exp__h426346 : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___exp__h426812 : - _theResult___fst_exp__h426345) ; + _theResult___exp__h426813 : + _theResult___fst_exp__h426346) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 = - (guard__h400502 == 2'b0 || + (guard__h400503 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h408501[56:34] : - _theResult___sfd__h408993 ; + _theResult___snd__h408502[56:34] : + _theResult___sfd__h408994 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 = - (guard__h400502 == 2'b0) ? - _theResult___snd__h408501[56:34] : + (guard__h400503 == 2'b0) ? + _theResult___snd__h408502[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h408993 : - _theResult___snd__h408501[56:34]) ; + _theResult___sfd__h408994 : + _theResult___snd__h408502[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 = - (guard__h418268 == 2'b0 || + (guard__h418269 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ? - _theResult___snd__h426291[56:34] : - _theResult___sfd__h426813 ; + _theResult___snd__h426292[56:34] : + _theResult___sfd__h426814 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 = - (guard__h418268 == 2'b0) ? - _theResult___snd__h426291[56:34] : + (guard__h418269 == 2'b0) ? + _theResult___snd__h426292[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? - _theResult___sfd__h426813 : - _theResult___snd__h426291[56:34]) ; + _theResult___sfd__h426814 : + _theResult___snd__h426292[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 = - (guard__h446197 == 2'b0 || + (guard__h446198 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h454245 : - _theResult___exp__h454687 ; + _theResult___fst_exp__h454246 : + _theResult___exp__h454688 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 = - (guard__h446197 == 2'b0) ? - _theResult___fst_exp__h454245 : + (guard__h446198 == 2'b0) ? + _theResult___fst_exp__h454246 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h454687 : - _theResult___fst_exp__h454245) ; + _theResult___exp__h454688 : + _theResult___fst_exp__h454246) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 = - (guard__h463963 == 2'b0 || + (guard__h463964 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___fst_exp__h472040 : - _theResult___exp__h472507 ; + _theResult___fst_exp__h472041 : + _theResult___exp__h472508 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 = - (guard__h463963 == 2'b0) ? - _theResult___fst_exp__h472040 : + (guard__h463964 == 2'b0) ? + _theResult___fst_exp__h472041 : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___exp__h472507 : - _theResult___fst_exp__h472040) ; + _theResult___exp__h472508 : + _theResult___fst_exp__h472041) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 = - (guard__h446197 == 2'b0 || + (guard__h446198 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h454196[56:34] : - _theResult___sfd__h454688 ; + _theResult___snd__h454197[56:34] : + _theResult___sfd__h454689 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 = - (guard__h446197 == 2'b0) ? - _theResult___snd__h454196[56:34] : + (guard__h446198 == 2'b0) ? + _theResult___snd__h454197[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h454688 : - _theResult___snd__h454196[56:34]) ; + _theResult___sfd__h454689 : + _theResult___snd__h454197[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 = - (guard__h463963 == 2'b0 || + (guard__h463964 == 2'b0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ? - _theResult___snd__h471986[56:34] : - _theResult___sfd__h472508 ; + _theResult___snd__h471987[56:34] : + _theResult___sfd__h472509 ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 = - (guard__h463963 == 2'b0) ? - _theResult___snd__h471986[56:34] : + (guard__h463964 == 2'b0) ? + _theResult___snd__h471987[56:34] : (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? - _theResult___sfd__h472508 : - _theResult___snd__h471986[56:34]) ; + _theResult___sfd__h472509 : + _theResult___snd__h471987[56:34]) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470 = - (_theResult___fst_exp__h558792 == 11'd2047) ? + (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21491,10 +21491,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676 = - (_theResult___fst_exp__h540382 == 11'd2047) ? + (_theResult___fst_exp__h540383 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21502,10 +21502,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 = - (_theResult___fst_exp__h558792 == 11'd2047) ? + (_theResult___fst_exp__h558793 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -21513,10 +21513,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 = - (_theResult___fst_exp__h519939 == 11'd2047) ? + (_theResult___fst_exp__h519940 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -21524,10 +21524,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 = - (_theResult___fst_exp__h598096 == 11'd2047) ? + (_theResult___fst_exp__h598097 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21535,10 +21535,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907 = - (_theResult___fst_exp__h579686 == 11'd2047) ? + (_theResult___fst_exp__h579687 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21546,10 +21546,10 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ; assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 = - (_theResult___fst_exp__h598096 == 11'd2047) ? + (_theResult___fst_exp__h598097 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -21557,14 +21557,14 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 = - (_theResult____h651118 == 16'd0 && + (_theResult____h651119 == 16'd0 && (csrf_prv_reg == 2'd0 || csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ? - enabled_ints__h651689 : - _theResult____h651118 ; + enabled_ints__h651690 : + _theResult____h651119 ; assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] || IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] || @@ -21626,77 +21626,77 @@ module mkCore(CLK, checkForException___d13698[4] || csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 = - ((f2_exp__h521135 == 8'd0) ? - (f2_sfd__h521136[22] ? + ((f2_exp__h521136 == 8'd0) ? + (f2_sfd__h521137[22] ? 6'd2 : - (f2_sfd__h521136[21] ? + (f2_sfd__h521137[21] ? 6'd3 : - (f2_sfd__h521136[20] ? + (f2_sfd__h521137[20] ? 6'd4 : - (f2_sfd__h521136[19] ? + (f2_sfd__h521137[19] ? 6'd5 : - (f2_sfd__h521136[18] ? + (f2_sfd__h521137[18] ? 6'd6 : - (f2_sfd__h521136[17] ? + (f2_sfd__h521137[17] ? 6'd7 : - (f2_sfd__h521136[16] ? + (f2_sfd__h521137[16] ? 6'd8 : - (f2_sfd__h521136[15] ? + (f2_sfd__h521137[15] ? 6'd9 : - (f2_sfd__h521136[14] ? + (f2_sfd__h521137[14] ? 6'd10 : - (f2_sfd__h521136[13] ? + (f2_sfd__h521137[13] ? 6'd11 : - (f2_sfd__h521136[12] ? + (f2_sfd__h521137[12] ? 6'd12 : - (f2_sfd__h521136[11] ? + (f2_sfd__h521137[11] ? 6'd13 : - (f2_sfd__h521136[10] ? + (f2_sfd__h521137[10] ? 6'd14 : - (f2_sfd__h521136[9] ? + (f2_sfd__h521137[9] ? 6'd15 : - (f2_sfd__h521136[8] ? + (f2_sfd__h521137[8] ? 6'd16 : - (f2_sfd__h521136[7] ? + (f2_sfd__h521137[7] ? 6'd17 : - (f2_sfd__h521136[6] ? + (f2_sfd__h521137[6] ? 6'd18 : - (f2_sfd__h521136[5] ? + (f2_sfd__h521137[5] ? 6'd19 : - (f2_sfd__h521136[4] ? + (f2_sfd__h521137[4] ? 6'd20 : - (f2_sfd__h521136[3] ? + (f2_sfd__h521137[3] ? 6'd21 : - (f2_sfd__h521136[2] ? + (f2_sfd__h521137[2] ? 6'd22 : - (f2_sfd__h521136[1] ? + (f2_sfd__h521137[1] ? 6'd23 : - (f2_sfd__h521136[0] ? + (f2_sfd__h521137[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474 = - (f2_exp__h521135 == 8'd255 && f2_sfd__h521136 != 23'd0 || - (f2_exp__h521135 == 8'd255 || f2_exp__h521135 == 8'd0) && - f2_sfd__h521136 == 23'd0) ? + (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0 || + (f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) && + f2_sfd__h521137 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - ((f2_exp__h521135 == 8'd0) ? + ((f2_exp__h521136 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 = - (f2_exp__h521135 == 8'd255 && f2_sfd__h521136 != 23'd0) ? - _theResult___snd_fst_sfd__h521451 : - _theResult___fst_sfd__h559591 ; + (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0) ? + _theResult___snd_fst_sfd__h521452 : + _theResult___fst_sfd__h559592 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 = - { (f2_exp__h521135 == 8'd255) ? + { (f2_exp__h521136 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h559587, + _theResult___fst_exp__h559588, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != @@ -21706,15 +21706,15 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 = - (f2_exp__h521135 == 8'd255 && f2_sfd__h521136 != 23'd0 || - (f2_exp__h521135 == 8'd255 || f2_exp__h521135 == 8'd0) && - f2_sfd__h521136 == 23'd0) ? + (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0 || + (f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) && + f2_sfd__h521137 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[4] : @@ -21722,7 +21722,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[4] : @@ -21730,7 +21730,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[4] : @@ -21738,7 +21738,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[4] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[3] : @@ -21746,7 +21746,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[3] : @@ -21754,7 +21754,7 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[3] : @@ -21762,211 +21762,211 @@ module mkCore(CLK, SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 && _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[3] ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[2] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 && (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[1]) : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 && IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 = - (f1_exp__h482141 == 8'd0) ? + (f1_exp__h482142 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002 = - (f2_exp__h521135 == 8'd0) ? + (f2_exp__h521136 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 && _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[0] : !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 || IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 = - ((f1_exp__h482141 == 8'd0) ? - (f1_sfd__h482142[22] ? + ((f1_exp__h482142 == 8'd0) ? + (f1_sfd__h482143[22] ? 6'd2 : - (f1_sfd__h482142[21] ? + (f1_sfd__h482143[21] ? 6'd3 : - (f1_sfd__h482142[20] ? + (f1_sfd__h482143[20] ? 6'd4 : - (f1_sfd__h482142[19] ? + (f1_sfd__h482143[19] ? 6'd5 : - (f1_sfd__h482142[18] ? + (f1_sfd__h482143[18] ? 6'd6 : - (f1_sfd__h482142[17] ? + (f1_sfd__h482143[17] ? 6'd7 : - (f1_sfd__h482142[16] ? + (f1_sfd__h482143[16] ? 6'd8 : - (f1_sfd__h482142[15] ? + (f1_sfd__h482143[15] ? 6'd9 : - (f1_sfd__h482142[14] ? + (f1_sfd__h482143[14] ? 6'd10 : - (f1_sfd__h482142[13] ? + (f1_sfd__h482143[13] ? 6'd11 : - (f1_sfd__h482142[12] ? + (f1_sfd__h482143[12] ? 6'd12 : - (f1_sfd__h482142[11] ? + (f1_sfd__h482143[11] ? 6'd13 : - (f1_sfd__h482142[10] ? + (f1_sfd__h482143[10] ? 6'd14 : - (f1_sfd__h482142[9] ? + (f1_sfd__h482143[9] ? 6'd15 : - (f1_sfd__h482142[8] ? + (f1_sfd__h482143[8] ? 6'd16 : - (f1_sfd__h482142[7] ? + (f1_sfd__h482143[7] ? 6'd17 : - (f1_sfd__h482142[6] ? + (f1_sfd__h482143[6] ? 6'd18 : - (f1_sfd__h482142[5] ? + (f1_sfd__h482143[5] ? 6'd19 : - (f1_sfd__h482142[4] ? + (f1_sfd__h482143[4] ? 6'd20 : - (f1_sfd__h482142[3] ? + (f1_sfd__h482143[3] ? 6'd21 : - (f1_sfd__h482142[2] ? + (f1_sfd__h482143[2] ? 6'd22 : - (f1_sfd__h482142[1] ? + (f1_sfd__h482143[1] ? 6'd23 : - (f1_sfd__h482142[0] ? + (f1_sfd__h482143[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989 = - (f1_exp__h482141 == 8'd255 && f1_sfd__h482142 != 23'd0 || - (f1_exp__h482141 == 8'd255 || f1_exp__h482141 == 8'd0) && - f1_sfd__h482142 == 23'd0) ? + (f1_exp__h482142 == 8'd255 && f1_sfd__h482143 != 23'd0 || + (f1_exp__h482142 == 8'd255 || f1_exp__h482142 == 8'd0) && + f1_sfd__h482143 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - ((f1_exp__h482141 == 8'd0) ? + ((f1_exp__h482142 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 = - (f1_exp__h482141 == 8'd255 && f1_sfd__h482142 != 23'd0) ? - _theResult___snd_fst_sfd__h482457 : - _theResult___fst_sfd__h520738 ; + (f1_exp__h482142 == 8'd255 && f1_sfd__h482143 != 23'd0) ? + _theResult___snd_fst_sfd__h482458 : + _theResult___fst_sfd__h520739 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 = { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989, - (f1_exp__h482141 == 8'd255) ? + (f1_exp__h482142 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h520734, + _theResult___fst_exp__h520735, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 = - ((f3_exp__h560439 == 8'd0) ? - (f3_sfd__h560440[22] ? + ((f3_exp__h560440 == 8'd0) ? + (f3_sfd__h560441[22] ? 6'd2 : - (f3_sfd__h560440[21] ? + (f3_sfd__h560441[21] ? 6'd3 : - (f3_sfd__h560440[20] ? + (f3_sfd__h560441[20] ? 6'd4 : - (f3_sfd__h560440[19] ? + (f3_sfd__h560441[19] ? 6'd5 : - (f3_sfd__h560440[18] ? + (f3_sfd__h560441[18] ? 6'd6 : - (f3_sfd__h560440[17] ? + (f3_sfd__h560441[17] ? 6'd7 : - (f3_sfd__h560440[16] ? + (f3_sfd__h560441[16] ? 6'd8 : - (f3_sfd__h560440[15] ? + (f3_sfd__h560441[15] ? 6'd9 : - (f3_sfd__h560440[14] ? + (f3_sfd__h560441[14] ? 6'd10 : - (f3_sfd__h560440[13] ? + (f3_sfd__h560441[13] ? 6'd11 : - (f3_sfd__h560440[12] ? + (f3_sfd__h560441[12] ? 6'd12 : - (f3_sfd__h560440[11] ? + (f3_sfd__h560441[11] ? 6'd13 : - (f3_sfd__h560440[10] ? + (f3_sfd__h560441[10] ? 6'd14 : - (f3_sfd__h560440[9] ? + (f3_sfd__h560441[9] ? 6'd15 : - (f3_sfd__h560440[8] ? + (f3_sfd__h560441[8] ? 6'd16 : - (f3_sfd__h560440[7] ? + (f3_sfd__h560441[7] ? 6'd17 : - (f3_sfd__h560440[6] ? + (f3_sfd__h560441[6] ? 6'd18 : - (f3_sfd__h560440[5] ? + (f3_sfd__h560441[5] ? 6'd19 : - (f3_sfd__h560440[4] ? + (f3_sfd__h560441[4] ? 6'd20 : - (f3_sfd__h560440[3] ? + (f3_sfd__h560441[3] ? 6'd21 : - (f3_sfd__h560440[2] ? + (f3_sfd__h560441[2] ? 6'd22 : - (f3_sfd__h560440[1] ? + (f3_sfd__h560441[1] ? 6'd23 : - (f3_sfd__h560440[0] ? + (f3_sfd__h560441[0] ? 6'd24 : 6'd57))))))))))))))))))))))) : 6'd1) - 6'd1 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704 = - (f3_exp__h560439 == 8'd255 && f3_sfd__h560440 != 23'd0 || - (f3_exp__h560439 == 8'd255 || f3_exp__h560439 == 8'd0) && - f3_sfd__h560440 == 23'd0) ? + (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0 || + (f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) && + f3_sfd__h560441 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - ((f3_exp__h560439 == 8'd0) ? + ((f3_exp__h560440 == 8'd0) ? IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702) ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 = - (f3_exp__h560439 == 8'd255 && f3_sfd__h560440 != 23'd0) ? - _theResult___snd_fst_sfd__h560755 : - _theResult___fst_sfd__h598895 ; + (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0) ? + _theResult___snd_fst_sfd__h560756 : + _theResult___fst_sfd__h598896 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 = - { (f3_exp__h560439 == 8'd255) ? + { (f3_exp__h560440 == 8'd255) ? 11'd2047 : - _theResult___fst_exp__h598891, + _theResult___fst_exp__h598892, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 } ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 = - (f3_exp__h560439 == 8'd0) ? + (f3_exp__h560440 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != @@ -21976,9 +21976,9 @@ module mkCore(CLK, IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909) : IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 ; assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938 = - (f3_exp__h560439 == 8'd255 && f3_sfd__h560440 != 23'd0 || - (f3_exp__h560439 == 8'd255 || f3_exp__h560439 == 8'd0) && - f3_sfd__h560440 == 23'd0) ? + (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0 || + (f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) && + f3_sfd__h560441 == 23'd0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22187,7 +22187,7 @@ module mkCore(CLK, assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 || - _theResult___fst_exp__h540382 == 11'd2047) ? + _theResult___fst_exp__h540383 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : @@ -22195,12 +22195,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 || - _theResult___fst_exp__h501529 == 11'd2047) ? + _theResult___fst_exp__h501530 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : @@ -22208,12 +22208,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ; assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 = (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 || _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 || - _theResult___fst_exp__h579686 == 11'd2047) ? + _theResult___fst_exp__h579687 == 11'd2047) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : @@ -22221,7 +22221,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ; assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 = IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ? @@ -22745,48 +22745,48 @@ module mkCore(CLK, assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[2] : - _theResult___fst_exp__h520722 == 11'd2047 && - _theResult___fst_sfd__h520723 == 52'd0 ; + _theResult___fst_exp__h520723 == 11'd2047 && + _theResult___fst_sfd__h520724 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[2] : - _theResult___fst_exp__h559575 == 11'd2047 && - _theResult___fst_sfd__h559576 == 52'd0 ; + _theResult___fst_exp__h559576 == 11'd2047 && + _theResult___fst_sfd__h559577 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[2] : - _theResult___fst_exp__h598879 == 11'd2047 && - _theResult___fst_sfd__h598880 == 52'd0 ; + _theResult___fst_exp__h598880 == 11'd2047 && + _theResult___fst_sfd__h598881 == 52'd0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[1] : - _theResult___fst_exp__h519939 == 11'd0 && - guard__h511949 != 2'b0 ; + _theResult___fst_exp__h519940 == 11'd0 && + guard__h511950 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[1] : - _theResult___fst_exp__h558792 == 11'd0 && - guard__h550802 != 2'b0 ; + _theResult___fst_exp__h558793 == 11'd0 && + guard__h550803 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[1] : - _theResult___fst_exp__h598096 == 11'd0 && - guard__h590106 != 2'b0 ; + _theResult___fst_exp__h598097 == 11'd0 && + guard__h590107 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[0] : - _theResult___fst_exp__h519939 != 11'd2047 && - guard__h511949 != 2'b0 ; + _theResult___fst_exp__h519940 != 11'd2047 && + guard__h511950 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[0] : - _theResult___fst_exp__h558792 != 11'd2047 && - guard__h550802 != 2'b0 ; + _theResult___fst_exp__h558793 != 11'd2047 && + guard__h550803 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[0] : - _theResult___fst_exp__h598096 != 11'd2047 && - guard__h590106 != 2'b0 ; + _theResult___fst_exp__h598097 != 11'd2047 && + guard__h590107 != 2'b0 ; assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 = ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? @@ -22832,35 +22832,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371963 == 8'd255) ? + ((_theResult___fst_exp__h371964 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084) : - ((_theResult___fst_exp__h380648 == 8'd255) ? + ((_theResult___fst_exp__h380649 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - ((_theResult___fst_exp__h371963 == 8'd255) ? + ((_theResult___fst_exp__h371964 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127) : - ((_theResult___fst_exp__h380648 == 8'd255) ? + ((_theResult___fst_exp__h380649 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[2] : - _theResult___fst_exp__h381196 == 8'd255 && - _theResult___fst_sfd__h381197 == 23'd0 ; + _theResult___fst_exp__h381197 == 8'd255 && + _theResult___fst_sfd__h381198 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[1] : - _theResult___fst_exp__h380648 == 8'd0 && - guard__h372571 != 2'b0 ; + _theResult___fst_exp__h380649 == 8'd0 && + guard__h372572 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[0] : - _theResult___fst_exp__h380648 != 8'd255 && - guard__h372571 != 2'b0 ; + _theResult___fst_exp__h380649 != 8'd255 && + guard__h372572 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? @@ -22870,35 +22870,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417660 == 8'd255) ? + ((_theResult___fst_exp__h417661 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476) : - ((_theResult___fst_exp__h426345 == 8'd255) ? + ((_theResult___fst_exp__h426346 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - ((_theResult___fst_exp__h417660 == 8'd255) ? + ((_theResult___fst_exp__h417661 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519) : - ((_theResult___fst_exp__h426345 == 8'd255) ? + ((_theResult___fst_exp__h426346 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[2] : - _theResult___fst_exp__h426893 == 8'd255 && - _theResult___fst_sfd__h426894 == 23'd0 ; + _theResult___fst_exp__h426894 == 8'd255 && + _theResult___fst_sfd__h426895 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[1] : - _theResult___fst_exp__h426345 == 8'd0 && - guard__h418268 != 2'b0 ; + _theResult___fst_exp__h426346 == 8'd0 && + guard__h418269 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[0] : - _theResult___fst_exp__h426345 != 8'd255 && - guard__h418268 != 2'b0 ; + _theResult___fst_exp__h426346 != 8'd255 && + guard__h418269 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 = ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? @@ -22908,35 +22908,35 @@ module mkCore(CLK, 9'd386 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463355 == 8'd255) ? + ((_theResult___fst_exp__h463356 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868) : - ((_theResult___fst_exp__h472040 == 8'd255) ? + ((_theResult___fst_exp__h472041 == 8'd255) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - ((_theResult___fst_exp__h463355 == 8'd255) ? + ((_theResult___fst_exp__h463356 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911) : - ((_theResult___fst_exp__h472040 == 8'd255) ? + ((_theResult___fst_exp__h472041 == 8'd255) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918) ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[2] : - _theResult___fst_exp__h472588 == 8'd255 && - _theResult___fst_sfd__h472589 == 23'd0 ; + _theResult___fst_exp__h472589 == 8'd255 && + _theResult___fst_sfd__h472590 == 23'd0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[1] : - _theResult___fst_exp__h472040 == 8'd0 && - guard__h463963 != 2'b0 ; + _theResult___fst_exp__h472041 == 8'd0 && + guard__h463964 != 2'b0 ; assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[0] : - _theResult___fst_exp__h472040 != 8'd255 && - guard__h463963 != 2'b0 ; + _theResult___fst_exp__h472041 != 8'd255 && + guard__h463964 != 2'b0 ; assign IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 = checkForException___d13008[4] ? CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 : @@ -22947,10 +22947,10 @@ module mkCore(CLK, 5'h0A, commitStage_f_rob_data$D_OUT[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h712487, - pc__h712387, - x__h714645, - x__h714837, + x_prv__h712488, + pc__h712388, + x__h714646, + x__h714838, commitStage_commitTrap[164:101] } ; assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 = (coreFix_aluExe_0_dispToRegQ$RDY_first && @@ -23608,8 +23608,8 @@ module mkCore(CLK, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ; assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 = coreFix_globalSpecUpdate_correctSpecTag_1$whas ? - result__h646695 : - w__h646690 ; + result__h646696 : + w__h646691 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd3 && @@ -23631,39 +23631,39 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198 = { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd7) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd6) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd5) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd4) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd3) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd2) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 = { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203, (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd1) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64], (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] == 3'd0) ? - n___1__h198530 : + n___1__h198531 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == @@ -23716,7 +23716,7 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 = (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] == 3'd2) ? - x__h197127 : + x__h197128 : (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ? 64'd0 : 64'd1) ; @@ -23728,7 +23728,7 @@ module mkCore(CLK, WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry || coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 = - _theResult_____2__h296522 == v__h295942 ; + _theResult_____2__h296523 == v__h295943 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23737,7 +23737,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas || coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 = - _theResult_____2__h304518 == v__h299287 ; + _theResult_____2__h304519 == v__h299288 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 = EN_dCacheToParent_fromP_enq ? !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] : @@ -23766,7 +23766,7 @@ module mkCore(CLK, EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3], - x__h302152 } ; + x__h302153 } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 = !MUX_flush_reservation$write_1__SEL_1 && (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ? @@ -23864,35 +23864,35 @@ module mkCore(CLK, assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998 = { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd7) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd6) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd5) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd4) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd3) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008 = { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003, (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd2) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128], (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] == 3'd1) ? - n__h194455 : + n__h194456 : coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? @@ -23920,7 +23920,7 @@ module mkCore(CLK, EN_dCacheToParent_rqToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 = - _theResult_____2__h310512 == v__h309801 ; + _theResult_____2__h310513 == v__h309802 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -23929,7 +23929,7 @@ module mkCore(CLK, EN_dCacheToParent_rsToP_deq || coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 = - _theResult_____2__h318366 == v__h313677 ; + _theResult_____2__h318367 == v__h313678 ; assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] : @@ -24081,7 +24081,7 @@ module mkCore(CLK, !coreFix_aluExe_0_bypassWire_1$whas || coreFix_memExe_dispToRegQ$RDY_first ; assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 = - _theResult_____2__h331935 == v__h331503 ; + _theResult_____2__h331936 == v__h331504 ; assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 = WILL_FIRE_RL_coreFix_memExe_doRespLdForward || coreFix_memExe_forwardQ_deqReq_rl ; @@ -24130,7 +24130,7 @@ module mkCore(CLK, SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) : IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 = - _theResult_____2__h328710 == v__h328278 ; + _theResult_____2__h328711 == v__h328279 ; assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 = WILL_FIRE_RL_coreFix_memExe_doRespLdMem || coreFix_memExe_memRespLdQ_deqReq_rl ; @@ -24162,7 +24162,7 @@ module mkCore(CLK, coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ; assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 = csrf_minstret_ehr_data_lat_0$whas ? - upd__h726805 : + upd__h726676 : csrf_minstret_ehr_data_rl ; assign IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 = csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? @@ -24289,10 +24289,10 @@ module mkCore(CLK, mmio_pRsQ_enqReq_lat_0$wget[67] : mmio_pRsQ_enqReq_rl[67] ; assign IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 = - rob$deqPort_0_canDeq ? y_avValue_fst__h730027 : 5'd0 ; + rob$deqPort_0_canDeq ? y_avValue_fst__h729898 : 5'd0 ; assign IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_fst__h730502 : + y_avValue_snd_snd_snd_fst__h730373 : 2'd0 ; assign IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? @@ -24325,48 +24325,48 @@ module mkCore(CLK, rob$deqPort_1_canDeq ? IF_NOT_rob_deqPort_1_deq_data__5328_BIT_25_532_ETC___d15680 : rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ; - assign IF_sfdin11100_BIT_4_THEN_2_ELSE_0__q139 = - sfdin__h511100[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin17654_BIT_33_THEN_2_ELSE_0__q74 = - sfdin__h417654[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin45583_BIT_33_THEN_2_ELSE_0__q99 = - sfdin__h445583[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin49953_BIT_4_THEN_2_ELSE_0__q179 = - sfdin__h549953[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin54191_BIT_33_THEN_2_ELSE_0__q29 = - sfdin__h354191[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin63349_BIT_33_THEN_2_ELSE_0__q109 = - sfdin__h463349[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin71957_BIT_33_THEN_2_ELSE_0__q39 = - sfdin__h371957[33] ? 2'd2 : 2'd0 ; - assign IF_sfdin89257_BIT_4_THEN_2_ELSE_0__q156 = - sfdin__h589257[4] ? 2'd2 : 2'd0 ; - assign IF_sfdin99888_BIT_33_THEN_2_ELSE_0__q64 = - sfdin__h399888[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd01480_BIT_4_THEN_2_ELSE_0__q135 = - _theResult___snd__h501480[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd08501_BIT_33_THEN_2_ELSE_0__q66 = - _theResult___snd__h408501[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd19885_BIT_4_THEN_2_ELSE_0__q142 = - _theResult___snd__h519885[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd26291_BIT_33_THEN_2_ELSE_0__q79 = - _theResult___snd__h426291[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd40333_BIT_4_THEN_2_ELSE_0__q175 = - _theResult___snd__h540333[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd54196_BIT_33_THEN_2_ELSE_0__q101 = - _theResult___snd__h454196[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd58738_BIT_4_THEN_2_ELSE_0__q182 = - _theResult___snd__h558738[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd62804_BIT_33_THEN_2_ELSE_0__q31 = - _theResult___snd__h362804[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd71986_BIT_33_THEN_2_ELSE_0__q114 = - _theResult___snd__h471986[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd79637_BIT_4_THEN_2_ELSE_0__q152 = - _theResult___snd__h579637[4] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd80594_BIT_33_THEN_2_ELSE_0__q44 = - _theResult___snd__h380594[33] ? 2'd2 : 2'd0 ; - assign IF_theResult___snd98042_BIT_4_THEN_2_ELSE_0__q159 = - _theResult___snd__h598042[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139 = + sfdin__h511101[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74 = + sfdin__h417655[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99 = + sfdin__h445584[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179 = + sfdin__h549954[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29 = + sfdin__h354192[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109 = + sfdin__h463350[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39 = + sfdin__h371958[33] ? 2'd2 : 2'd0 ; + assign IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156 = + sfdin__h589258[4] ? 2'd2 : 2'd0 ; + assign IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64 = + sfdin__h399889[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135 = + _theResult___snd__h501481[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66 = + _theResult___snd__h408502[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142 = + _theResult___snd__h519886[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79 = + _theResult___snd__h426292[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175 = + _theResult___snd__h540334[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101 = + _theResult___snd__h454197[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182 = + _theResult___snd__h558739[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31 = + _theResult___snd__h362805[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114 = + _theResult___snd__h471987[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152 = + _theResult___snd__h579638[4] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44 = + _theResult___snd__h380595[33] ? 2'd2 : 2'd0 ; + assign IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159 = + _theResult___snd__h598043[4] ? 2'd2 : 2'd0 ; assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 = !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 || (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? @@ -24458,131 +24458,131 @@ module mkCore(CLK, !checkForException___d13698[4] && NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723 ; assign NOT_IF_NOT_rob_deqPort_0_canDeq__5320_5321_OR__ETC___d15686 = - (fflags__h733287 & csrf_fflags_reg) != fflags__h733287 || + (fflags__h733158 & csrf_fflags_reg) != fflags__h733158 || csrf_fs_reg != 2'b11 && (IF_rob_deqPort_1_canDeq__5325_THEN_IF_NOT_rob__ETC___d15681 || - fflags__h733287 != 5'd0) ; + fflags__h733158 != 5'd0) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 = - !f2_sfd__h521136[21] && !f2_sfd__h521136[20] && - !f2_sfd__h521136[19] && - !f2_sfd__h521136[18] && - !f2_sfd__h521136[17] && - !f2_sfd__h521136[16] && - !f2_sfd__h521136[15] && - !f2_sfd__h521136[14] && - !f2_sfd__h521136[13] && - !f2_sfd__h521136[12] && - !f2_sfd__h521136[11] && - !f2_sfd__h521136[10] && - !f2_sfd__h521136[9] && - !f2_sfd__h521136[8] && - !f2_sfd__h521136[7] && - !f2_sfd__h521136[6] && - !f2_sfd__h521136[5] && - !f2_sfd__h521136[4] && - !f2_sfd__h521136[3] && - !f2_sfd__h521136[2] && - !f2_sfd__h521136[1] && - !f2_sfd__h521136[0] ; + !f2_sfd__h521137[21] && !f2_sfd__h521137[20] && + !f2_sfd__h521137[19] && + !f2_sfd__h521137[18] && + !f2_sfd__h521137[17] && + !f2_sfd__h521137[16] && + !f2_sfd__h521137[15] && + !f2_sfd__h521137[14] && + !f2_sfd__h521137[13] && + !f2_sfd__h521137[12] && + !f2_sfd__h521137[11] && + !f2_sfd__h521137[10] && + !f2_sfd__h521137[9] && + !f2_sfd__h521137[8] && + !f2_sfd__h521137[7] && + !f2_sfd__h521137[6] && + !f2_sfd__h521137[5] && + !f2_sfd__h521137[4] && + !f2_sfd__h521137[3] && + !f2_sfd__h521137[2] && + !f2_sfd__h521137[1] && + !f2_sfd__h521137[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 = - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 == 23'd0) && - (f1_exp__h482141 != 8'd255 || f1_sfd__h482142 != 23'd0) && - (f1_exp__h482141 != 8'd0 || f1_sfd__h482142 != 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) && + (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) && + (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 = NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 | - ((f2_exp__h521135 != 8'd255 || f2_sfd__h521136 == 23'd0) && - (f2_exp__h521135 != 8'd255 || f2_sfd__h521136 != 23'd0) && - (f2_exp__h521135 != 8'd0 || f2_sfd__h521136 != 23'd0) && + ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) && + (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) && + (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002) ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 = - !f1_sfd__h482142[21] && !f1_sfd__h482142[20] && - !f1_sfd__h482142[19] && - !f1_sfd__h482142[18] && - !f1_sfd__h482142[17] && - !f1_sfd__h482142[16] && - !f1_sfd__h482142[15] && - !f1_sfd__h482142[14] && - !f1_sfd__h482142[13] && - !f1_sfd__h482142[12] && - !f1_sfd__h482142[11] && - !f1_sfd__h482142[10] && - !f1_sfd__h482142[9] && - !f1_sfd__h482142[8] && - !f1_sfd__h482142[7] && - !f1_sfd__h482142[6] && - !f1_sfd__h482142[5] && - !f1_sfd__h482142[4] && - !f1_sfd__h482142[3] && - !f1_sfd__h482142[2] && - !f1_sfd__h482142[1] && - !f1_sfd__h482142[0] ; + !f1_sfd__h482143[21] && !f1_sfd__h482143[20] && + !f1_sfd__h482143[19] && + !f1_sfd__h482143[18] && + !f1_sfd__h482143[17] && + !f1_sfd__h482143[16] && + !f1_sfd__h482143[15] && + !f1_sfd__h482143[14] && + !f1_sfd__h482143[13] && + !f1_sfd__h482143[12] && + !f1_sfd__h482143[11] && + !f1_sfd__h482143[10] && + !f1_sfd__h482143[9] && + !f1_sfd__h482143[8] && + !f1_sfd__h482143[7] && + !f1_sfd__h482143[6] && + !f1_sfd__h482143[5] && + !f1_sfd__h482143[4] && + !f1_sfd__h482143[3] && + !f1_sfd__h482143[2] && + !f1_sfd__h482143[1] && + !f1_sfd__h482143[0] ; assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 = - !f3_sfd__h560440[21] && !f3_sfd__h560440[20] && - !f3_sfd__h560440[19] && - !f3_sfd__h560440[18] && - !f3_sfd__h560440[17] && - !f3_sfd__h560440[16] && - !f3_sfd__h560440[15] && - !f3_sfd__h560440[14] && - !f3_sfd__h560440[13] && - !f3_sfd__h560440[12] && - !f3_sfd__h560440[11] && - !f3_sfd__h560440[10] && - !f3_sfd__h560440[9] && - !f3_sfd__h560440[8] && - !f3_sfd__h560440[7] && - !f3_sfd__h560440[6] && - !f3_sfd__h560440[5] && - !f3_sfd__h560440[4] && - !f3_sfd__h560440[3] && - !f3_sfd__h560440[2] && - !f3_sfd__h560440[1] && - !f3_sfd__h560440[0] ; + !f3_sfd__h560441[21] && !f3_sfd__h560441[20] && + !f3_sfd__h560441[19] && + !f3_sfd__h560441[18] && + !f3_sfd__h560441[17] && + !f3_sfd__h560441[16] && + !f3_sfd__h560441[15] && + !f3_sfd__h560441[14] && + !f3_sfd__h560441[13] && + !f3_sfd__h560441[12] && + !f3_sfd__h560441[11] && + !f3_sfd__h560441[10] && + !f3_sfd__h560441[9] && + !f3_sfd__h560441[8] && + !f3_sfd__h560441[7] && + !f3_sfd__h560441[6] && + !f3_sfd__h560441[5] && + !f3_sfd__h560441[4] && + !f3_sfd__h560441[3] && + !f3_sfd__h560441[2] && + !f3_sfd__h560441[1] && + !f3_sfd__h560441[0] ; assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484 = !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 && (fetchStage$pipelines_0_first[194:192] != 3'd1 || @@ -25157,7 +25157,7 @@ module mkCore(CLK, (fetchStage$pipelines_0_first[199:195] != 5'd13 || NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 && !csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 && - csr_addr__h655327 != 12'h8FF) ; + csr_addr__h655328 != 12'h8FF) ; assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420 = (csrf_fs_reg != 2'd0 || (!fetchStage$pipelines_0_first[95] || @@ -25282,9 +25282,9 @@ module mkCore(CLK, assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 = (fetchStage$pipelines_0_first[194:192] != 3'd0 || fetchStage$pipelines_0_first[178:174] != 5'd15) && - rs1__h655328 == 5'd0 && - imm__h655329 == 32'd0 || - csr_addr__h655327[11:10] != 2'b11 ; + rs1__h655329 == 5'd0 && + imm__h655330 == 32'd0 || + csr_addr__h655328[11:10] != 2'b11 ; assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && @@ -25611,7 +25611,7 @@ module mkCore(CLK, { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267, !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268, SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938, - x__h291617 } ; + x__h291618 } ; assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16102 = { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269, CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270, @@ -25630,8 +25630,8 @@ module mkCore(CLK, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262, CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 = - { {4{f2_exp21135_MINUS_127__q176[7]}}, - f2_exp21135_MINUS_127__q176 } ; + { {4{f2_exp21136_MINUS_127__q176[7]}}, + f2_exp21136_MINUS_127__q176 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^ 12'h800) <= @@ -25641,8 +25641,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 = - { {4{f1_exp82141_MINUS_127__q136[7]}}, - f1_exp82141_MINUS_127__q136 } ; + { {4{f1_exp82142_MINUS_127__q136[7]}}, + f1_exp82142_MINUS_127__q136 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^ 12'h800) <= @@ -25652,8 +25652,8 @@ module mkCore(CLK, 12'h800) < 12'd1026 ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 = - { {4{f3_exp60439_MINUS_127__q153[7]}}, - f3_exp60439_MINUS_127__q153 } ; + { {4{f3_exp60440_MINUS_127__q153[7]}}, + f3_exp60440_MINUS_127__q153 } ; assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^ 12'h800) <= @@ -25738,15 +25738,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169 = { 3'd0, - _theResult___fst_exp__h354197 == 8'd0 && - (sfdin__h354191[56:34] == 23'd0 || guard__h346096 != 2'b0), + _theResult___fst_exp__h354198 == 8'd0 && + (sfdin__h354192[56:34] == 23'd0 || guard__h346097 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h354794 == 8'd255 && - _theResult___fst_sfd__h354795 == 23'd0, + _theResult___fst_exp__h354795 == 8'd255 && + _theResult___fst_sfd__h354796 == 23'd0, 1'd0, - _theResult___fst_exp__h354197 != 8'd255 && - guard__h346096 != 2'b0 } ; + _theResult___fst_exp__h354198 != 8'd255 && + guard__h346097 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ^ @@ -25754,15 +25754,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561 = { 3'd0, - _theResult___fst_exp__h399894 == 8'd0 && - (sfdin__h399888[56:34] == 23'd0 || guard__h391795 != 2'b0), + _theResult___fst_exp__h399895 == 8'd0 && + (sfdin__h399889[56:34] == 23'd0 || guard__h391796 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h400491 == 8'd255 && - _theResult___fst_sfd__h400492 == 23'd0, + _theResult___fst_exp__h400492 == 8'd255 && + _theResult___fst_sfd__h400493 == 23'd0, 1'd0, - _theResult___fst_exp__h399894 != 8'd255 && - guard__h391795 != 2'b0 } ; + _theResult___fst_exp__h399895 != 8'd255 && + guard__h391796 != 2'b0 } ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 = ({ 3'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ^ @@ -25770,15 +25770,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953 = { 3'd0, - _theResult___fst_exp__h445589 == 8'd0 && - (sfdin__h445583[56:34] == 23'd0 || guard__h437490 != 2'b0), + _theResult___fst_exp__h445590 == 8'd0 && + (sfdin__h445584[56:34] == 23'd0 || guard__h437491 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h446186 == 8'd255 && - _theResult___fst_sfd__h446187 == 23'd0, + _theResult___fst_exp__h446187 == 8'd255 && + _theResult___fst_sfd__h446188 == 23'd0, 1'd0, - _theResult___fst_exp__h445589 != 8'd255 && - guard__h437490 != 2'b0 } ; + _theResult___fst_exp__h445590 != 8'd255 && + guard__h437491 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ^ @@ -25786,37 +25786,37 @@ module mkCore(CLK, 12'd2048 ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758 = { 3'd0, - _theResult___fst_exp__h511106 == 11'd0 && - (sfdin__h511100[56:5] == 52'd0 || guard__h502880 != 2'b0), + _theResult___fst_exp__h511107 == 11'd0 && + (sfdin__h511101[56:5] == 52'd0 || guard__h502881 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h511938 == 11'd2047 && - _theResult___fst_sfd__h511939 == 52'd0, + _theResult___fst_exp__h511939 == 11'd2047 && + _theResult___fst_sfd__h511940 == 52'd0, 1'd0, - _theResult___fst_exp__h511106 != 11'd2047 && - guard__h502880 != 2'b0 } ; + _theResult___fst_exp__h511107 != 11'd2047 && + guard__h502881 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799 = { 3'd0, - _theResult___fst_exp__h549959 == 11'd0 && - (sfdin__h549953[56:5] == 52'd0 || guard__h541733 != 2'b0), + _theResult___fst_exp__h549960 == 11'd0 && + (sfdin__h549954[56:5] == 52'd0 || guard__h541734 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h550791 == 11'd2047 && - _theResult___fst_sfd__h550792 == 52'd0, + _theResult___fst_exp__h550792 == 11'd2047 && + _theResult___fst_sfd__h550793 == 52'd0, 1'd0, - _theResult___fst_exp__h549959 != 11'd2047 && - guard__h541733 != 2'b0 } ; + _theResult___fst_exp__h549960 != 11'd2047 && + guard__h541734 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843 = { 3'd0, - _theResult___fst_exp__h589263 == 11'd0 && - (sfdin__h589257[56:5] == 52'd0 || guard__h581037 != 2'b0), + _theResult___fst_exp__h589264 == 11'd0 && + (sfdin__h589258[56:5] == 52'd0 || guard__h581038 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h590095 == 11'd2047 && - _theResult___fst_sfd__h590096 == 52'd0, + _theResult___fst_exp__h590096 == 11'd2047 && + _theResult___fst_sfd__h590097 == 52'd0, 1'd0, - _theResult___fst_exp__h589263 != 11'd2047 && - guard__h581037 != 2'b0 } ; + _theResult___fst_exp__h589264 != 11'd2047 && + guard__h581038 != 2'b0 } ; assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 = ({ 6'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ^ @@ -25834,15 +25834,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198 = { 3'd0, - _theResult___fst_exp__h371963 == 8'd0 && - (sfdin__h371957[56:34] == 23'd0 || guard__h363735 != 2'b0), + _theResult___fst_exp__h371964 == 8'd0 && + (sfdin__h371958[56:34] == 23'd0 || guard__h363736 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h372560 == 8'd255 && - _theResult___fst_sfd__h372561 == 23'd0, + _theResult___fst_exp__h372561 == 8'd255 && + _theResult___fst_sfd__h372562 == 23'd0, 1'd0, - _theResult___fst_exp__h371963 != 8'd255 && - guard__h363735 != 2'b0 } ; + _theResult___fst_exp__h371964 != 8'd255 && + guard__h363736 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ^ @@ -25850,15 +25850,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590 = { 3'd0, - _theResult___fst_exp__h417660 == 8'd0 && - (sfdin__h417654[56:34] == 23'd0 || guard__h409432 != 2'b0), + _theResult___fst_exp__h417661 == 8'd0 && + (sfdin__h417655[56:34] == 23'd0 || guard__h409433 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h418257 == 8'd255 && - _theResult___fst_sfd__h418258 == 23'd0, + _theResult___fst_exp__h418258 == 8'd255 && + _theResult___fst_sfd__h418259 == 23'd0, 1'd0, - _theResult___fst_exp__h417660 != 8'd255 && - guard__h409432 != 2'b0 } ; + _theResult___fst_exp__h417661 != 8'd255 && + guard__h409433 != 2'b0 } ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 = ({ 3'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ^ @@ -25866,15 +25866,15 @@ module mkCore(CLK, 9'd256 ; assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982 = { 3'd0, - _theResult___fst_exp__h463355 == 8'd0 && - (sfdin__h463349[56:34] == 23'd0 || guard__h455127 != 2'b0), + _theResult___fst_exp__h463356 == 8'd0 && + (sfdin__h463350[56:34] == 23'd0 || guard__h455128 != 2'b0), 1'd0 } | { 2'd0, - _theResult___fst_exp__h463952 == 8'd255 && - _theResult___fst_sfd__h463953 == 23'd0, + _theResult___fst_exp__h463953 == 8'd255 && + _theResult___fst_sfd__h463954 == 23'd0, 1'd0, - _theResult___fst_exp__h463355 != 8'd255 && - guard__h455127 != 2'b0 } ; + _theResult___fst_exp__h463356 != 8'd255 && + guard__h455128 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^ @@ -25888,37 +25888,37 @@ module mkCore(CLK, 12'h800) ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741 = { 3'd0, - _theResult___fst_exp__h501529 == 11'd0 && - guard__h493568 != 2'b0, + _theResult___fst_exp__h501530 == 11'd0 && + guard__h493569 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h502287 == 11'd2047 && - _theResult___fst_sfd__h502288 == 52'd0, + _theResult___fst_exp__h502288 == 11'd2047 && + _theResult___fst_sfd__h502289 == 52'd0, 1'd0, - _theResult___fst_exp__h501529 != 11'd2047 && - guard__h493568 != 2'b0 } ; + _theResult___fst_exp__h501530 != 11'd2047 && + guard__h493569 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782 = { 3'd0, - _theResult___fst_exp__h540382 == 11'd0 && - guard__h532421 != 2'b0, + _theResult___fst_exp__h540383 == 11'd0 && + guard__h532422 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h541140 == 11'd2047 && - _theResult___fst_sfd__h541141 == 52'd0, + _theResult___fst_exp__h541141 == 11'd2047 && + _theResult___fst_sfd__h541142 == 52'd0, 1'd0, - _theResult___fst_exp__h540382 != 11'd2047 && - guard__h532421 != 2'b0 } ; + _theResult___fst_exp__h540383 != 11'd2047 && + guard__h532422 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826 = { 3'd0, - _theResult___fst_exp__h579686 == 11'd0 && - guard__h571725 != 2'b0, + _theResult___fst_exp__h579687 == 11'd0 && + guard__h571726 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h580444 == 11'd2047 && - _theResult___fst_sfd__h580445 == 52'd0, + _theResult___fst_exp__h580445 == 11'd2047 && + _theResult___fst_sfd__h580446 == 52'd0, 1'd0, - _theResult___fst_exp__h579686 != 11'd2047 && - guard__h571725 != 2'b0 } ; + _theResult___fst_exp__h579687 != 11'd2047 && + guard__h571726 != 2'b0 } ; assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 = ({ 6'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^ @@ -25954,15 +25954,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181 = { 3'd0, - _theResult___fst_exp__h362853 == 8'd0 && - guard__h354805 != 2'b0, + _theResult___fst_exp__h362854 == 8'd0 && + guard__h354806 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h363376 == 8'd255 && - _theResult___fst_sfd__h363377 == 23'd0, + _theResult___fst_exp__h363377 == 8'd255 && + _theResult___fst_sfd__h363378 == 23'd0, 1'd0, - _theResult___fst_exp__h362853 != 8'd255 && - guard__h354805 != 2'b0 } ; + _theResult___fst_exp__h362854 != 8'd255 && + guard__h354806 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^ @@ -25976,15 +25976,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573 = { 3'd0, - _theResult___fst_exp__h408550 == 8'd0 && - guard__h400502 != 2'b0, + _theResult___fst_exp__h408551 == 8'd0 && + guard__h400503 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h409073 == 8'd255 && - _theResult___fst_sfd__h409074 == 23'd0, + _theResult___fst_exp__h409074 == 8'd255 && + _theResult___fst_sfd__h409075 == 23'd0, 1'd0, - _theResult___fst_exp__h408550 != 8'd255 && - guard__h400502 != 2'b0 } ; + _theResult___fst_exp__h408551 != 8'd255 && + guard__h400503 != 2'b0 } ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 = ({ 3'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^ @@ -25998,15 +25998,15 @@ module mkCore(CLK, 9'h100) ; assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965 = { 3'd0, - _theResult___fst_exp__h454245 == 8'd0 && - guard__h446197 != 2'b0, + _theResult___fst_exp__h454246 == 8'd0 && + guard__h446198 != 2'b0, 1'd0 } | { 2'd0, - _theResult___fst_exp__h454768 == 8'd255 && - _theResult___fst_sfd__h454769 == 23'd0, + _theResult___fst_exp__h454769 == 8'd255 && + _theResult___fst_sfd__h454770 == 23'd0, 1'd0, - _theResult___fst_exp__h454245 != 8'd255 && - guard__h446197 != 2'b0 } ; + _theResult___fst_exp__h454246 != 8'd255 && + guard__h446198 != 2'b0 } ; assign _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798 = { 4'd0, csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3, @@ -26020,7 +26020,7 @@ module mkCore(CLK, assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 = (fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$RDY_nextSpecTag) && - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ; assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829 = (fetchStage$pipelines_1_first[194:192] != 3'd1 || !fetchStage$pipelines_0_canDeq || @@ -26034,35 +26034,35 @@ module mkCore(CLK, specTagManager$RDY_nextSpecTag) && CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138 = - sfd__h521497 >> + sfd__h521498 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653 = - sfd__h482503 >> + sfd__h482504 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368 = - sfd__h560801 >> + sfd__h560802 >> _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558 = - sfd__h338481 >> + sfd__h338482 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950 = - sfd__h384183 >> + sfd__h384184 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946) ; assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342 = - sfd__h429878 >> + sfd__h429879 >> (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ? 12'hAAA : _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ; assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14324 = - mip_csr__read__h611252 == commitStage_rg_old_mip_csr_val ; + mip_csr__read__h611253 == commitStage_rg_old_mip_csr_val ; assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716 = - medeleg_csr__read__h610371[i__h709458] ; + medeleg_csr__read__h610372[i__h709459] ; assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14698 = - mideleg_csr__read__h610466[i__h709618] ; + mideleg_csr__read__h610467[i__h709619] ; assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 = 12'd3074 - { 6'd0, @@ -26468,51 +26468,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 = 12'd3970 - { 7'd0, - f2_sfd__h521136[22] ? + f2_sfd__h521137[22] ? 5'd0 : - (f2_sfd__h521136[21] ? + (f2_sfd__h521137[21] ? 5'd1 : - (f2_sfd__h521136[20] ? + (f2_sfd__h521137[20] ? 5'd2 : - (f2_sfd__h521136[19] ? + (f2_sfd__h521137[19] ? 5'd3 : - (f2_sfd__h521136[18] ? + (f2_sfd__h521137[18] ? 5'd4 : - (f2_sfd__h521136[17] ? + (f2_sfd__h521137[17] ? 5'd5 : - (f2_sfd__h521136[16] ? + (f2_sfd__h521137[16] ? 5'd6 : - (f2_sfd__h521136[15] ? + (f2_sfd__h521137[15] ? 5'd7 : - (f2_sfd__h521136[14] ? + (f2_sfd__h521137[14] ? 5'd8 : - (f2_sfd__h521136[13] ? + (f2_sfd__h521137[13] ? 5'd9 : - (f2_sfd__h521136[12] ? + (f2_sfd__h521137[12] ? 5'd10 : - (f2_sfd__h521136[11] ? + (f2_sfd__h521137[11] ? 5'd11 : - (f2_sfd__h521136[10] ? + (f2_sfd__h521137[10] ? 5'd12 : - (f2_sfd__h521136[9] ? + (f2_sfd__h521137[9] ? 5'd13 : - (f2_sfd__h521136[8] ? + (f2_sfd__h521137[8] ? 5'd14 : - (f2_sfd__h521136[7] ? + (f2_sfd__h521137[7] ? 5'd15 : - (f2_sfd__h521136[6] ? + (f2_sfd__h521137[6] ? 5'd16 : - (f2_sfd__h521136[5] ? + (f2_sfd__h521137[5] ? 5'd17 : - (f2_sfd__h521136[4] ? + (f2_sfd__h521137[4] ? 5'd18 : - (f2_sfd__h521136[3] ? + (f2_sfd__h521137[3] ? 5'd19 : - (f2_sfd__h521136[2] ? + (f2_sfd__h521137[2] ? 5'd20 : - (f2_sfd__h521136[1] ? + (f2_sfd__h521137[1] ? 5'd21 : - (f2_sfd__h521136[0] ? + (f2_sfd__h521137[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 = @@ -26526,51 +26526,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 = 12'd3970 - { 7'd0, - f1_sfd__h482142[22] ? + f1_sfd__h482143[22] ? 5'd0 : - (f1_sfd__h482142[21] ? + (f1_sfd__h482143[21] ? 5'd1 : - (f1_sfd__h482142[20] ? + (f1_sfd__h482143[20] ? 5'd2 : - (f1_sfd__h482142[19] ? + (f1_sfd__h482143[19] ? 5'd3 : - (f1_sfd__h482142[18] ? + (f1_sfd__h482143[18] ? 5'd4 : - (f1_sfd__h482142[17] ? + (f1_sfd__h482143[17] ? 5'd5 : - (f1_sfd__h482142[16] ? + (f1_sfd__h482143[16] ? 5'd6 : - (f1_sfd__h482142[15] ? + (f1_sfd__h482143[15] ? 5'd7 : - (f1_sfd__h482142[14] ? + (f1_sfd__h482143[14] ? 5'd8 : - (f1_sfd__h482142[13] ? + (f1_sfd__h482143[13] ? 5'd9 : - (f1_sfd__h482142[12] ? + (f1_sfd__h482143[12] ? 5'd10 : - (f1_sfd__h482142[11] ? + (f1_sfd__h482143[11] ? 5'd11 : - (f1_sfd__h482142[10] ? + (f1_sfd__h482143[10] ? 5'd12 : - (f1_sfd__h482142[9] ? + (f1_sfd__h482143[9] ? 5'd13 : - (f1_sfd__h482142[8] ? + (f1_sfd__h482143[8] ? 5'd14 : - (f1_sfd__h482142[7] ? + (f1_sfd__h482143[7] ? 5'd15 : - (f1_sfd__h482142[6] ? + (f1_sfd__h482143[6] ? 5'd16 : - (f1_sfd__h482142[5] ? + (f1_sfd__h482143[5] ? 5'd17 : - (f1_sfd__h482142[4] ? + (f1_sfd__h482143[4] ? 5'd18 : - (f1_sfd__h482142[3] ? + (f1_sfd__h482143[3] ? 5'd19 : - (f1_sfd__h482142[2] ? + (f1_sfd__h482143[2] ? 5'd20 : - (f1_sfd__h482142[1] ? + (f1_sfd__h482143[1] ? 5'd21 : - (f1_sfd__h482142[0] ? + (f1_sfd__h482143[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 = @@ -26584,51 +26584,51 @@ module mkCore(CLK, assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 = 12'd3970 - { 7'd0, - f3_sfd__h560440[22] ? + f3_sfd__h560441[22] ? 5'd0 : - (f3_sfd__h560440[21] ? + (f3_sfd__h560441[21] ? 5'd1 : - (f3_sfd__h560440[20] ? + (f3_sfd__h560441[20] ? 5'd2 : - (f3_sfd__h560440[19] ? + (f3_sfd__h560441[19] ? 5'd3 : - (f3_sfd__h560440[18] ? + (f3_sfd__h560441[18] ? 5'd4 : - (f3_sfd__h560440[17] ? + (f3_sfd__h560441[17] ? 5'd5 : - (f3_sfd__h560440[16] ? + (f3_sfd__h560441[16] ? 5'd6 : - (f3_sfd__h560440[15] ? + (f3_sfd__h560441[15] ? 5'd7 : - (f3_sfd__h560440[14] ? + (f3_sfd__h560441[14] ? 5'd8 : - (f3_sfd__h560440[13] ? + (f3_sfd__h560441[13] ? 5'd9 : - (f3_sfd__h560440[12] ? + (f3_sfd__h560441[12] ? 5'd10 : - (f3_sfd__h560440[11] ? + (f3_sfd__h560441[11] ? 5'd11 : - (f3_sfd__h560440[10] ? + (f3_sfd__h560441[10] ? 5'd12 : - (f3_sfd__h560440[9] ? + (f3_sfd__h560441[9] ? 5'd13 : - (f3_sfd__h560440[8] ? + (f3_sfd__h560441[8] ? 5'd14 : - (f3_sfd__h560440[7] ? + (f3_sfd__h560441[7] ? 5'd15 : - (f3_sfd__h560440[6] ? + (f3_sfd__h560441[6] ? 5'd16 : - (f3_sfd__h560440[5] ? + (f3_sfd__h560441[5] ? 5'd17 : - (f3_sfd__h560440[4] ? + (f3_sfd__h560441[4] ? 5'd18 : - (f3_sfd__h560440[3] ? + (f3_sfd__h560441[3] ? 5'd19 : - (f3_sfd__h560440[2] ? + (f3_sfd__h560441[2] ? 5'd20 : - (f3_sfd__h560440[1] ? + (f3_sfd__h560441[1] ? 5'd21 : - (f3_sfd__h560440[0] ? + (f3_sfd__h560441[0] ? 5'd22 : 5'd23)))))))))))))))))))))) } ; assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 = @@ -26657,14 +26657,14 @@ module mkCore(CLK, NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 && fetchStage$pipelines_1_first[199:195] != 5'd14 ; assign _dfoo16 = - k__h669625 == 1'd1 && + k__h669626 == 1'd1 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == 1'd1 && NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208 ; assign _dfoo18 = - k__h669625 == 1'd0 && + k__h669626 == 1'd0 && fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 || (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) == @@ -26781,1421 +26781,1421 @@ module mkCore(CLK, assign _dor1sbCons$EN_setReady_1_put = WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F || WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ; - assign _theResult_____2__h296522 = + assign _theResult_____2__h296523 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046) ? - next_deqP___1__h296801 : + next_deqP___1__h296802 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ; - assign _theResult_____2__h304518 = + assign _theResult_____2__h304519 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153) ? - next_deqP___1__h304797 : + next_deqP___1__h304798 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ; - assign _theResult_____2__h310512 = + assign _theResult_____2__h310513 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324) ? - next_deqP___1__h311078 : + next_deqP___1__h311079 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ; - assign _theResult_____2__h318366 = + assign _theResult_____2__h318367 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420) ? - next_deqP___1__h318932 : + next_deqP___1__h318933 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ; - assign _theResult_____2__h328710 = + assign _theResult_____2__h328711 = (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649) ? - next_deqP___1__h328989 : + next_deqP___1__h328990 : coreFix_memExe_memRespLdQ_deqP ; - assign _theResult_____2__h331935 = + assign _theResult_____2__h331936 = (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743) ? - next_deqP___1__h332214 : + next_deqP___1__h332215 : coreFix_memExe_forwardQ_deqP ; - assign _theResult____h346086 = - (value__h346708 == 54'd0) ? sfd__h338481 : 57'd1 ; - assign _theResult____h363725 = + assign _theResult____h346087 = + (value__h346709 == 54'd0) ? sfd__h338482 : 57'd1 ; + assign _theResult____h363726 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ^ 12'h800) < 12'd2105) ? - result__h364338 : - _theResult____h346086 ; - assign _theResult____h391785 = - (value__h392405 == 54'd0) ? sfd__h384183 : 57'd1 ; - assign _theResult____h409422 = + result__h364339 : + _theResult____h346087 ; + assign _theResult____h391786 = + (value__h392406 == 54'd0) ? sfd__h384184 : 57'd1 ; + assign _theResult____h409423 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ^ 12'h800) < 12'd2105) ? - result__h410035 : - _theResult____h391785 ; - assign _theResult____h437480 = - (value__h438100 == 54'd0) ? sfd__h429878 : 57'd1 ; - assign _theResult____h455117 = + result__h410036 : + _theResult____h391786 ; + assign _theResult____h437481 = + (value__h438101 == 54'd0) ? sfd__h429879 : 57'd1 ; + assign _theResult____h455118 = ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ^ 12'h800) < 12'd2105) ? - result__h455730 : - _theResult____h437480 ; - assign _theResult____h502870 = + result__h455731 : + _theResult____h437481 ; + assign _theResult____h502871 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ^ 12'h800) < 12'd2105) ? - result__h503483 : - ((value__h487086 == 25'd0) ? sfd__h482503 : 57'd1) ; - assign _theResult____h541723 = + result__h503484 : + ((value__h487087 == 25'd0) ? sfd__h482504 : 57'd1) ; + assign _theResult____h541724 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ^ 12'h800) < 12'd2105) ? - result__h542336 : - ((value__h525939 == 25'd0) ? sfd__h521497 : 57'd1) ; - assign _theResult____h581027 = + result__h542337 : + ((value__h525940 == 25'd0) ? sfd__h521498 : 57'd1) ; + assign _theResult____h581028 = ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ^ 12'h800) < 12'd2105) ? - result__h581640 : - ((value__h565243 == 25'd0) ? sfd__h560801 : 57'd1) ; - assign _theResult____h651118 = + result__h581641 : + ((value__h565244 == 25'd0) ? sfd__h560802 : 57'd1) ; + assign _theResult____h651119 = (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ? - enabled_ints___1__h651643 : + enabled_ints___1__h651644 : 16'd0 ; - assign _theResult___exp__h354713 = - sfd__h354289[24] ? - ((_theResult___fst_exp__h354197 == 8'd254) ? + assign _theResult___exp__h354714 = + sfd__h354290[24] ? + ((_theResult___fst_exp__h354198 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381230) : - ((_theResult___fst_exp__h354197 == 8'd0 && - sfd__h354289[24:23] == 2'b01) ? + din_inc___2_exp__h381231) : + ((_theResult___fst_exp__h354198 == 8'd0 && + sfd__h354290[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h354197) ; - assign _theResult___exp__h363295 = - sfd__h362871[24] ? - ((_theResult___fst_exp__h362853 == 8'd254) ? + _theResult___fst_exp__h354198) ; + assign _theResult___exp__h363296 = + sfd__h362872[24] ? + ((_theResult___fst_exp__h362854 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381254) : - ((_theResult___fst_exp__h362853 == 8'd0 && - sfd__h362871[24:23] == 2'b01) ? + din_inc___2_exp__h381255) : + ((_theResult___fst_exp__h362854 == 8'd0 && + sfd__h362872[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h362853) ; - assign _theResult___exp__h372479 = - sfd__h372055[24] ? - ((_theResult___fst_exp__h371963 == 8'd254) ? + _theResult___fst_exp__h362854) ; + assign _theResult___exp__h372480 = + sfd__h372056[24] ? + ((_theResult___fst_exp__h371964 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381284) : - ((_theResult___fst_exp__h371963 == 8'd0 && - sfd__h372055[24:23] == 2'b01) ? + din_inc___2_exp__h381285) : + ((_theResult___fst_exp__h371964 == 8'd0 && + sfd__h372056[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h371963) ; - assign _theResult___exp__h381115 = - sfd__h380667[24] ? - ((_theResult___fst_exp__h380648 == 8'd254) ? + _theResult___fst_exp__h371964) ; + assign _theResult___exp__h381116 = + sfd__h380668[24] ? + ((_theResult___fst_exp__h380649 == 8'd254) ? 8'd255 : - din_inc___2_exp__h381308) : - ((_theResult___fst_exp__h380648 == 8'd0 && - sfd__h380667[24:23] == 2'b01) ? + din_inc___2_exp__h381309) : + ((_theResult___fst_exp__h380649 == 8'd0 && + sfd__h380668[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h380648) ; - assign _theResult___exp__h381217 = + _theResult___fst_exp__h380649) ; + assign _theResult___exp__h381218 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381208 ; - assign _theResult___exp__h400410 = - sfd__h399986[24] ? - ((_theResult___fst_exp__h399894 == 8'd254) ? + _theResult___fst_exp__h381209 ; + assign _theResult___exp__h400411 = + sfd__h399987[24] ? + ((_theResult___fst_exp__h399895 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426927) : - ((_theResult___fst_exp__h399894 == 8'd0 && - sfd__h399986[24:23] == 2'b01) ? + din_inc___2_exp__h426928) : + ((_theResult___fst_exp__h399895 == 8'd0 && + sfd__h399987[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h399894) ; - assign _theResult___exp__h408992 = - sfd__h408568[24] ? - ((_theResult___fst_exp__h408550 == 8'd254) ? + _theResult___fst_exp__h399895) ; + assign _theResult___exp__h408993 = + sfd__h408569[24] ? + ((_theResult___fst_exp__h408551 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426951) : - ((_theResult___fst_exp__h408550 == 8'd0 && - sfd__h408568[24:23] == 2'b01) ? + din_inc___2_exp__h426952) : + ((_theResult___fst_exp__h408551 == 8'd0 && + sfd__h408569[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h408550) ; - assign _theResult___exp__h418176 = - sfd__h417752[24] ? - ((_theResult___fst_exp__h417660 == 8'd254) ? + _theResult___fst_exp__h408551) ; + assign _theResult___exp__h418177 = + sfd__h417753[24] ? + ((_theResult___fst_exp__h417661 == 8'd254) ? 8'd255 : - din_inc___2_exp__h426981) : - ((_theResult___fst_exp__h417660 == 8'd0 && - sfd__h417752[24:23] == 2'b01) ? + din_inc___2_exp__h426982) : + ((_theResult___fst_exp__h417661 == 8'd0 && + sfd__h417753[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h417660) ; - assign _theResult___exp__h426812 = - sfd__h426364[24] ? - ((_theResult___fst_exp__h426345 == 8'd254) ? + _theResult___fst_exp__h417661) ; + assign _theResult___exp__h426813 = + sfd__h426365[24] ? + ((_theResult___fst_exp__h426346 == 8'd254) ? 8'd255 : - din_inc___2_exp__h427005) : - ((_theResult___fst_exp__h426345 == 8'd0 && - sfd__h426364[24:23] == 2'b01) ? + din_inc___2_exp__h427006) : + ((_theResult___fst_exp__h426346 == 8'd0 && + sfd__h426365[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h426345) ; - assign _theResult___exp__h426914 = + _theResult___fst_exp__h426346) ; + assign _theResult___exp__h426915 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426905 ; - assign _theResult___exp__h446105 = - sfd__h445681[24] ? - ((_theResult___fst_exp__h445589 == 8'd254) ? + _theResult___fst_exp__h426906 ; + assign _theResult___exp__h446106 = + sfd__h445682[24] ? + ((_theResult___fst_exp__h445590 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472622) : - ((_theResult___fst_exp__h445589 == 8'd0 && - sfd__h445681[24:23] == 2'b01) ? + din_inc___2_exp__h472623) : + ((_theResult___fst_exp__h445590 == 8'd0 && + sfd__h445682[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h445589) ; - assign _theResult___exp__h454687 = - sfd__h454263[24] ? - ((_theResult___fst_exp__h454245 == 8'd254) ? + _theResult___fst_exp__h445590) ; + assign _theResult___exp__h454688 = + sfd__h454264[24] ? + ((_theResult___fst_exp__h454246 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472646) : - ((_theResult___fst_exp__h454245 == 8'd0 && - sfd__h454263[24:23] == 2'b01) ? + din_inc___2_exp__h472647) : + ((_theResult___fst_exp__h454246 == 8'd0 && + sfd__h454264[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h454245) ; - assign _theResult___exp__h463871 = - sfd__h463447[24] ? - ((_theResult___fst_exp__h463355 == 8'd254) ? + _theResult___fst_exp__h454246) ; + assign _theResult___exp__h463872 = + sfd__h463448[24] ? + ((_theResult___fst_exp__h463356 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472676) : - ((_theResult___fst_exp__h463355 == 8'd0 && - sfd__h463447[24:23] == 2'b01) ? + din_inc___2_exp__h472677) : + ((_theResult___fst_exp__h463356 == 8'd0 && + sfd__h463448[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h463355) ; - assign _theResult___exp__h472507 = - sfd__h472059[24] ? - ((_theResult___fst_exp__h472040 == 8'd254) ? + _theResult___fst_exp__h463356) ; + assign _theResult___exp__h472508 = + sfd__h472060[24] ? + ((_theResult___fst_exp__h472041 == 8'd254) ? 8'd255 : - din_inc___2_exp__h472700) : - ((_theResult___fst_exp__h472040 == 8'd0 && - sfd__h472059[24:23] == 2'b01) ? + din_inc___2_exp__h472701) : + ((_theResult___fst_exp__h472041 == 8'd0 && + sfd__h472060[24:23] == 2'b01) ? 8'd1 : - _theResult___fst_exp__h472040) ; - assign _theResult___exp__h472609 = + _theResult___fst_exp__h472041) ; + assign _theResult___exp__h472610 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472600 ; - assign _theResult___exp__h502184 = - sfd__h501547[53] ? - ((_theResult___fst_exp__h501529 == 11'd2046) ? + _theResult___fst_exp__h472601 ; + assign _theResult___exp__h502185 = + sfd__h501548[53] ? + ((_theResult___fst_exp__h501530 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520779) : - ((_theResult___fst_exp__h501529 == 11'd0 && - sfd__h501547[53:52] == 2'b01) ? + din_inc___2_exp__h520780) : + ((_theResult___fst_exp__h501530 == 11'd0 && + sfd__h501548[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h501529) ; - assign _theResult___exp__h511835 = - sfd__h511198[53] ? - ((_theResult___fst_exp__h511106 == 11'd2046) ? + _theResult___fst_exp__h501530) ; + assign _theResult___exp__h511836 = + sfd__h511199[53] ? + ((_theResult___fst_exp__h511107 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520814) : - ((_theResult___fst_exp__h511106 == 11'd0 && - sfd__h511198[53:52] == 2'b01) ? + din_inc___2_exp__h520815) : + ((_theResult___fst_exp__h511107 == 11'd0 && + sfd__h511199[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h511106) ; - assign _theResult___exp__h520619 = - sfd__h519958[53] ? - ((_theResult___fst_exp__h519939 == 11'd2046) ? + _theResult___fst_exp__h511107) ; + assign _theResult___exp__h520620 = + sfd__h519959[53] ? + ((_theResult___fst_exp__h519940 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h520840) : - ((_theResult___fst_exp__h519939 == 11'd0 && - sfd__h519958[53:52] == 2'b01) ? + din_inc___2_exp__h520841) : + ((_theResult___fst_exp__h519940 == 11'd0 && + sfd__h519959[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h519939) ; - assign _theResult___exp__h541037 = - sfd__h540400[53] ? - ((_theResult___fst_exp__h540382 == 11'd2046) ? + _theResult___fst_exp__h519940) ; + assign _theResult___exp__h541038 = + sfd__h540401[53] ? + ((_theResult___fst_exp__h540383 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559632) : - ((_theResult___fst_exp__h540382 == 11'd0 && - sfd__h540400[53:52] == 2'b01) ? + din_inc___2_exp__h559633) : + ((_theResult___fst_exp__h540383 == 11'd0 && + sfd__h540401[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h540382) ; - assign _theResult___exp__h550688 = - sfd__h550051[53] ? - ((_theResult___fst_exp__h549959 == 11'd2046) ? + _theResult___fst_exp__h540383) ; + assign _theResult___exp__h550689 = + sfd__h550052[53] ? + ((_theResult___fst_exp__h549960 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559667) : - ((_theResult___fst_exp__h549959 == 11'd0 && - sfd__h550051[53:52] == 2'b01) ? + din_inc___2_exp__h559668) : + ((_theResult___fst_exp__h549960 == 11'd0 && + sfd__h550052[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h549959) ; - assign _theResult___exp__h559472 = - sfd__h558811[53] ? - ((_theResult___fst_exp__h558792 == 11'd2046) ? + _theResult___fst_exp__h549960) ; + assign _theResult___exp__h559473 = + sfd__h558812[53] ? + ((_theResult___fst_exp__h558793 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h559693) : - ((_theResult___fst_exp__h558792 == 11'd0 && - sfd__h558811[53:52] == 2'b01) ? + din_inc___2_exp__h559694) : + ((_theResult___fst_exp__h558793 == 11'd0 && + sfd__h558812[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h558792) ; - assign _theResult___exp__h580341 = - sfd__h579704[53] ? - ((_theResult___fst_exp__h579686 == 11'd2046) ? + _theResult___fst_exp__h558793) ; + assign _theResult___exp__h580342 = + sfd__h579705[53] ? + ((_theResult___fst_exp__h579687 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598936) : - ((_theResult___fst_exp__h579686 == 11'd0 && - sfd__h579704[53:52] == 2'b01) ? + din_inc___2_exp__h598937) : + ((_theResult___fst_exp__h579687 == 11'd0 && + sfd__h579705[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h579686) ; - assign _theResult___exp__h589992 = - sfd__h589355[53] ? - ((_theResult___fst_exp__h589263 == 11'd2046) ? + _theResult___fst_exp__h579687) ; + assign _theResult___exp__h589993 = + sfd__h589356[53] ? + ((_theResult___fst_exp__h589264 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598971) : - ((_theResult___fst_exp__h589263 == 11'd0 && - sfd__h589355[53:52] == 2'b01) ? + din_inc___2_exp__h598972) : + ((_theResult___fst_exp__h589264 == 11'd0 && + sfd__h589356[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h589263) ; - assign _theResult___exp__h598776 = - sfd__h598115[53] ? - ((_theResult___fst_exp__h598096 == 11'd2046) ? + _theResult___fst_exp__h589264) ; + assign _theResult___exp__h598777 = + sfd__h598116[53] ? + ((_theResult___fst_exp__h598097 == 11'd2046) ? 11'd2047 : - din_inc___2_exp__h598997) : - ((_theResult___fst_exp__h598096 == 11'd0 && - sfd__h598115[53:52] == 2'b01) ? + din_inc___2_exp__h598998) : + ((_theResult___fst_exp__h598097 == 11'd0 && + sfd__h598116[53:52] == 2'b01) ? 11'd1 : - _theResult___fst_exp__h598096) ; - assign _theResult___fst__h603371 = - a__h602949[63] ? a___1__h603376 : a__h602949 ; - assign _theResult___fst_exp__h354197 = - _theResult____h346086[56] ? + _theResult___fst_exp__h598097) ; + assign _theResult___fst__h603372 = + a__h602950[63] ? a___1__h603377 : a__h602950 ; + assign _theResult___fst_exp__h354198 = + _theResult____h346087[56] ? 8'd2 : - _theResult___fst_exp__h354271 ; - assign _theResult___fst_exp__h354262 = + _theResult___fst_exp__h354272 ; + assign _theResult___fst_exp__h354263 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ; - assign _theResult___fst_exp__h354268 = - (!_theResult____h346086[56] && !_theResult____h346086[55] && - !_theResult____h346086[54] && - !_theResult____h346086[53] && - !_theResult____h346086[52] && - !_theResult____h346086[51] && - !_theResult____h346086[50] && - !_theResult____h346086[49] && - !_theResult____h346086[48] && - !_theResult____h346086[47] && - !_theResult____h346086[46] && - !_theResult____h346086[45] && - !_theResult____h346086[44] && - !_theResult____h346086[43] && - !_theResult____h346086[42] && - !_theResult____h346086[41] && - !_theResult____h346086[40] && - !_theResult____h346086[39] && - !_theResult____h346086[38] && - !_theResult____h346086[37] && - !_theResult____h346086[36] && - !_theResult____h346086[35] && - !_theResult____h346086[34] && - !_theResult____h346086[33] && - !_theResult____h346086[32] && - !_theResult____h346086[31] && - !_theResult____h346086[30] && - !_theResult____h346086[29] && - !_theResult____h346086[28] && - !_theResult____h346086[27] && - !_theResult____h346086[26] && - !_theResult____h346086[25] && - !_theResult____h346086[24] && - !_theResult____h346086[23] && - !_theResult____h346086[22] && - !_theResult____h346086[21] && - !_theResult____h346086[20] && - !_theResult____h346086[19] && - !_theResult____h346086[18] && - !_theResult____h346086[17] && - !_theResult____h346086[16] && - !_theResult____h346086[15] && - !_theResult____h346086[14] && - !_theResult____h346086[13] && - !_theResult____h346086[12] && - !_theResult____h346086[11] && - !_theResult____h346086[10] && - !_theResult____h346086[9] && - !_theResult____h346086[8] && - !_theResult____h346086[7] && - !_theResult____h346086[6] && - !_theResult____h346086[5] && - !_theResult____h346086[4] && - !_theResult____h346086[3] && - !_theResult____h346086[2] && - !_theResult____h346086[1] && - !_theResult____h346086[0] || + assign _theResult___fst_exp__h354269 = + (!_theResult____h346087[56] && !_theResult____h346087[55] && + !_theResult____h346087[54] && + !_theResult____h346087[53] && + !_theResult____h346087[52] && + !_theResult____h346087[51] && + !_theResult____h346087[50] && + !_theResult____h346087[49] && + !_theResult____h346087[48] && + !_theResult____h346087[47] && + !_theResult____h346087[46] && + !_theResult____h346087[45] && + !_theResult____h346087[44] && + !_theResult____h346087[43] && + !_theResult____h346087[42] && + !_theResult____h346087[41] && + !_theResult____h346087[40] && + !_theResult____h346087[39] && + !_theResult____h346087[38] && + !_theResult____h346087[37] && + !_theResult____h346087[36] && + !_theResult____h346087[35] && + !_theResult____h346087[34] && + !_theResult____h346087[33] && + !_theResult____h346087[32] && + !_theResult____h346087[31] && + !_theResult____h346087[30] && + !_theResult____h346087[29] && + !_theResult____h346087[28] && + !_theResult____h346087[27] && + !_theResult____h346087[26] && + !_theResult____h346087[25] && + !_theResult____h346087[24] && + !_theResult____h346087[23] && + !_theResult____h346087[22] && + !_theResult____h346087[21] && + !_theResult____h346087[20] && + !_theResult____h346087[19] && + !_theResult____h346087[18] && + !_theResult____h346087[17] && + !_theResult____h346087[16] && + !_theResult____h346087[15] && + !_theResult____h346087[14] && + !_theResult____h346087[13] && + !_theResult____h346087[12] && + !_theResult____h346087[11] && + !_theResult____h346087[10] && + !_theResult____h346087[9] && + !_theResult____h346087[8] && + !_theResult____h346087[7] && + !_theResult____h346087[6] && + !_theResult____h346087[5] && + !_theResult____h346087[4] && + !_theResult____h346087[3] && + !_theResult____h346087[2] && + !_theResult____h346087[1] && + !_theResult____h346087[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249) ? 8'd0 : - _theResult___fst_exp__h354262 ; - assign _theResult___fst_exp__h354271 = - (!_theResult____h346086[56] && _theResult____h346086[55]) ? + _theResult___fst_exp__h354263 ; + assign _theResult___fst_exp__h354272 = + (!_theResult____h346087[56] && _theResult____h346087[55]) ? 8'd1 : - _theResult___fst_exp__h354268 ; - assign _theResult___fst_exp__h354794 = - (_theResult___fst_exp__h354197 == 8'd255) ? - _theResult___fst_exp__h354197 : - _theResult___fst_exp__h354791 ; - assign _theResult___fst_exp__h362844 = + _theResult___fst_exp__h354269 ; + assign _theResult___fst_exp__h354795 = + (_theResult___fst_exp__h354198 == 8'd255) ? + _theResult___fst_exp__h354198 : + _theResult___fst_exp__h354792 ; + assign _theResult___fst_exp__h362845 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h362850 = + assign _theResult___fst_exp__h362851 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480) ? 8'd0 : - _theResult___fst_exp__h362844 ; - assign _theResult___fst_exp__h362853 = + _theResult___fst_exp__h362845 ; + assign _theResult___fst_exp__h362854 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h362850 : + _theResult___fst_exp__h362851 : 8'd129 ; - assign _theResult___fst_exp__h363376 = - (_theResult___fst_exp__h362853 == 8'd255) ? - _theResult___fst_exp__h362853 : - _theResult___fst_exp__h363373 ; - assign _theResult___fst_exp__h371963 = - _theResult____h363725[56] ? + assign _theResult___fst_exp__h363377 = + (_theResult___fst_exp__h362854 == 8'd255) ? + _theResult___fst_exp__h362854 : + _theResult___fst_exp__h363374 ; + assign _theResult___fst_exp__h371964 = + _theResult____h363726[56] ? 8'd2 : - _theResult___fst_exp__h372037 ; - assign _theResult___fst_exp__h372028 = + _theResult___fst_exp__h372038 ; + assign _theResult___fst_exp__h372029 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ; - assign _theResult___fst_exp__h372034 = - (!_theResult____h363725[56] && !_theResult____h363725[55] && - !_theResult____h363725[54] && - !_theResult____h363725[53] && - !_theResult____h363725[52] && - !_theResult____h363725[51] && - !_theResult____h363725[50] && - !_theResult____h363725[49] && - !_theResult____h363725[48] && - !_theResult____h363725[47] && - !_theResult____h363725[46] && - !_theResult____h363725[45] && - !_theResult____h363725[44] && - !_theResult____h363725[43] && - !_theResult____h363725[42] && - !_theResult____h363725[41] && - !_theResult____h363725[40] && - !_theResult____h363725[39] && - !_theResult____h363725[38] && - !_theResult____h363725[37] && - !_theResult____h363725[36] && - !_theResult____h363725[35] && - !_theResult____h363725[34] && - !_theResult____h363725[33] && - !_theResult____h363725[32] && - !_theResult____h363725[31] && - !_theResult____h363725[30] && - !_theResult____h363725[29] && - !_theResult____h363725[28] && - !_theResult____h363725[27] && - !_theResult____h363725[26] && - !_theResult____h363725[25] && - !_theResult____h363725[24] && - !_theResult____h363725[23] && - !_theResult____h363725[22] && - !_theResult____h363725[21] && - !_theResult____h363725[20] && - !_theResult____h363725[19] && - !_theResult____h363725[18] && - !_theResult____h363725[17] && - !_theResult____h363725[16] && - !_theResult____h363725[15] && - !_theResult____h363725[14] && - !_theResult____h363725[13] && - !_theResult____h363725[12] && - !_theResult____h363725[11] && - !_theResult____h363725[10] && - !_theResult____h363725[9] && - !_theResult____h363725[8] && - !_theResult____h363725[7] && - !_theResult____h363725[6] && - !_theResult____h363725[5] && - !_theResult____h363725[4] && - !_theResult____h363725[3] && - !_theResult____h363725[2] && - !_theResult____h363725[1] && - !_theResult____h363725[0] || + assign _theResult___fst_exp__h372035 = + (!_theResult____h363726[56] && !_theResult____h363726[55] && + !_theResult____h363726[54] && + !_theResult____h363726[53] && + !_theResult____h363726[52] && + !_theResult____h363726[51] && + !_theResult____h363726[50] && + !_theResult____h363726[49] && + !_theResult____h363726[48] && + !_theResult____h363726[47] && + !_theResult____h363726[46] && + !_theResult____h363726[45] && + !_theResult____h363726[44] && + !_theResult____h363726[43] && + !_theResult____h363726[42] && + !_theResult____h363726[41] && + !_theResult____h363726[40] && + !_theResult____h363726[39] && + !_theResult____h363726[38] && + !_theResult____h363726[37] && + !_theResult____h363726[36] && + !_theResult____h363726[35] && + !_theResult____h363726[34] && + !_theResult____h363726[33] && + !_theResult____h363726[32] && + !_theResult____h363726[31] && + !_theResult____h363726[30] && + !_theResult____h363726[29] && + !_theResult____h363726[28] && + !_theResult____h363726[27] && + !_theResult____h363726[26] && + !_theResult____h363726[25] && + !_theResult____h363726[24] && + !_theResult____h363726[23] && + !_theResult____h363726[22] && + !_theResult____h363726[21] && + !_theResult____h363726[20] && + !_theResult____h363726[19] && + !_theResult____h363726[18] && + !_theResult____h363726[17] && + !_theResult____h363726[16] && + !_theResult____h363726[15] && + !_theResult____h363726[14] && + !_theResult____h363726[13] && + !_theResult____h363726[12] && + !_theResult____h363726[11] && + !_theResult____h363726[10] && + !_theResult____h363726[9] && + !_theResult____h363726[8] && + !_theResult____h363726[7] && + !_theResult____h363726[6] && + !_theResult____h363726[5] && + !_theResult____h363726[4] && + !_theResult____h363726[3] && + !_theResult____h363726[2] && + !_theResult____h363726[1] && + !_theResult____h363726[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800) ? 8'd0 : - _theResult___fst_exp__h372028 ; - assign _theResult___fst_exp__h372037 = - (!_theResult____h363725[56] && _theResult____h363725[55]) ? + _theResult___fst_exp__h372029 ; + assign _theResult___fst_exp__h372038 = + (!_theResult____h363726[56] && _theResult____h363726[55]) ? 8'd1 : - _theResult___fst_exp__h372034 ; - assign _theResult___fst_exp__h372560 = - (_theResult___fst_exp__h371963 == 8'd255) ? - _theResult___fst_exp__h371963 : - _theResult___fst_exp__h372557 ; - assign _theResult___fst_exp__h380600 = + _theResult___fst_exp__h372035 ; + assign _theResult___fst_exp__h372561 = + (_theResult___fst_exp__h371964 == 8'd255) ? + _theResult___fst_exp__h371964 : + _theResult___fst_exp__h372558 ; + assign _theResult___fst_exp__h380601 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ; - assign _theResult___fst_exp__h380639 = + assign _theResult___fst_exp__h380640 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ; - assign _theResult___fst_exp__h380645 = + assign _theResult___fst_exp__h380646 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873) ? 8'd0 : - _theResult___fst_exp__h380639 ; - assign _theResult___fst_exp__h380648 = + _theResult___fst_exp__h380640 ; + assign _theResult___fst_exp__h380649 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h380645 : - _theResult___fst_exp__h380600 ; - assign _theResult___fst_exp__h381196 = - (_theResult___fst_exp__h380648 == 8'd255) ? - _theResult___fst_exp__h380648 : - _theResult___fst_exp__h381193 ; - assign _theResult___fst_exp__h381205 = + _theResult___fst_exp__h380646 : + _theResult___fst_exp__h380601 ; + assign _theResult___fst_exp__h381197 = + (_theResult___fst_exp__h380649 == 8'd255) ? + _theResult___fst_exp__h380649 : + _theResult___fst_exp__h381194 ; + assign _theResult___fst_exp__h381206 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_exp__h363379 : - _theResult___fst_exp__h346068) : + _theResult___snd_fst_exp__h363380 : + _theResult___fst_exp__h346069) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_exp__h381199 : - _theResult___fst_exp__h346068) ; - assign _theResult___fst_exp__h381208 = + _theResult___snd_fst_exp__h381200 : + _theResult___fst_exp__h346069) ; + assign _theResult___fst_exp__h381209 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h381205 ; - assign _theResult___fst_exp__h399894 = - _theResult____h391785[56] ? + _theResult___fst_exp__h381206 ; + assign _theResult___fst_exp__h399895 = + _theResult____h391786[56] ? 8'd2 : - _theResult___fst_exp__h399968 ; - assign _theResult___fst_exp__h399959 = + _theResult___fst_exp__h399969 ; + assign _theResult___fst_exp__h399960 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ; - assign _theResult___fst_exp__h399965 = - (!_theResult____h391785[56] && !_theResult____h391785[55] && - !_theResult____h391785[54] && - !_theResult____h391785[53] && - !_theResult____h391785[52] && - !_theResult____h391785[51] && - !_theResult____h391785[50] && - !_theResult____h391785[49] && - !_theResult____h391785[48] && - !_theResult____h391785[47] && - !_theResult____h391785[46] && - !_theResult____h391785[45] && - !_theResult____h391785[44] && - !_theResult____h391785[43] && - !_theResult____h391785[42] && - !_theResult____h391785[41] && - !_theResult____h391785[40] && - !_theResult____h391785[39] && - !_theResult____h391785[38] && - !_theResult____h391785[37] && - !_theResult____h391785[36] && - !_theResult____h391785[35] && - !_theResult____h391785[34] && - !_theResult____h391785[33] && - !_theResult____h391785[32] && - !_theResult____h391785[31] && - !_theResult____h391785[30] && - !_theResult____h391785[29] && - !_theResult____h391785[28] && - !_theResult____h391785[27] && - !_theResult____h391785[26] && - !_theResult____h391785[25] && - !_theResult____h391785[24] && - !_theResult____h391785[23] && - !_theResult____h391785[22] && - !_theResult____h391785[21] && - !_theResult____h391785[20] && - !_theResult____h391785[19] && - !_theResult____h391785[18] && - !_theResult____h391785[17] && - !_theResult____h391785[16] && - !_theResult____h391785[15] && - !_theResult____h391785[14] && - !_theResult____h391785[13] && - !_theResult____h391785[12] && - !_theResult____h391785[11] && - !_theResult____h391785[10] && - !_theResult____h391785[9] && - !_theResult____h391785[8] && - !_theResult____h391785[7] && - !_theResult____h391785[6] && - !_theResult____h391785[5] && - !_theResult____h391785[4] && - !_theResult____h391785[3] && - !_theResult____h391785[2] && - !_theResult____h391785[1] && - !_theResult____h391785[0] || + assign _theResult___fst_exp__h399966 = + (!_theResult____h391786[56] && !_theResult____h391786[55] && + !_theResult____h391786[54] && + !_theResult____h391786[53] && + !_theResult____h391786[52] && + !_theResult____h391786[51] && + !_theResult____h391786[50] && + !_theResult____h391786[49] && + !_theResult____h391786[48] && + !_theResult____h391786[47] && + !_theResult____h391786[46] && + !_theResult____h391786[45] && + !_theResult____h391786[44] && + !_theResult____h391786[43] && + !_theResult____h391786[42] && + !_theResult____h391786[41] && + !_theResult____h391786[40] && + !_theResult____h391786[39] && + !_theResult____h391786[38] && + !_theResult____h391786[37] && + !_theResult____h391786[36] && + !_theResult____h391786[35] && + !_theResult____h391786[34] && + !_theResult____h391786[33] && + !_theResult____h391786[32] && + !_theResult____h391786[31] && + !_theResult____h391786[30] && + !_theResult____h391786[29] && + !_theResult____h391786[28] && + !_theResult____h391786[27] && + !_theResult____h391786[26] && + !_theResult____h391786[25] && + !_theResult____h391786[24] && + !_theResult____h391786[23] && + !_theResult____h391786[22] && + !_theResult____h391786[21] && + !_theResult____h391786[20] && + !_theResult____h391786[19] && + !_theResult____h391786[18] && + !_theResult____h391786[17] && + !_theResult____h391786[16] && + !_theResult____h391786[15] && + !_theResult____h391786[14] && + !_theResult____h391786[13] && + !_theResult____h391786[12] && + !_theResult____h391786[11] && + !_theResult____h391786[10] && + !_theResult____h391786[9] && + !_theResult____h391786[8] && + !_theResult____h391786[7] && + !_theResult____h391786[6] && + !_theResult____h391786[5] && + !_theResult____h391786[4] && + !_theResult____h391786[3] && + !_theResult____h391786[2] && + !_theResult____h391786[1] && + !_theResult____h391786[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641) ? 8'd0 : - _theResult___fst_exp__h399959 ; - assign _theResult___fst_exp__h399968 = - (!_theResult____h391785[56] && _theResult____h391785[55]) ? + _theResult___fst_exp__h399960 ; + assign _theResult___fst_exp__h399969 = + (!_theResult____h391786[56] && _theResult____h391786[55]) ? 8'd1 : - _theResult___fst_exp__h399965 ; - assign _theResult___fst_exp__h400491 = - (_theResult___fst_exp__h399894 == 8'd255) ? - _theResult___fst_exp__h399894 : - _theResult___fst_exp__h400488 ; - assign _theResult___fst_exp__h408541 = + _theResult___fst_exp__h399966 ; + assign _theResult___fst_exp__h400492 = + (_theResult___fst_exp__h399895 == 8'd255) ? + _theResult___fst_exp__h399895 : + _theResult___fst_exp__h400489 ; + assign _theResult___fst_exp__h408542 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h408547 = + assign _theResult___fst_exp__h408548 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872) ? 8'd0 : - _theResult___fst_exp__h408541 ; - assign _theResult___fst_exp__h408550 = + _theResult___fst_exp__h408542 ; + assign _theResult___fst_exp__h408551 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h408547 : + _theResult___fst_exp__h408548 : 8'd129 ; - assign _theResult___fst_exp__h409073 = - (_theResult___fst_exp__h408550 == 8'd255) ? - _theResult___fst_exp__h408550 : - _theResult___fst_exp__h409070 ; - assign _theResult___fst_exp__h417660 = - _theResult____h409422[56] ? + assign _theResult___fst_exp__h409074 = + (_theResult___fst_exp__h408551 == 8'd255) ? + _theResult___fst_exp__h408551 : + _theResult___fst_exp__h409071 ; + assign _theResult___fst_exp__h417661 = + _theResult____h409423[56] ? 8'd2 : - _theResult___fst_exp__h417734 ; - assign _theResult___fst_exp__h417725 = + _theResult___fst_exp__h417735 ; + assign _theResult___fst_exp__h417726 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ; - assign _theResult___fst_exp__h417731 = - (!_theResult____h409422[56] && !_theResult____h409422[55] && - !_theResult____h409422[54] && - !_theResult____h409422[53] && - !_theResult____h409422[52] && - !_theResult____h409422[51] && - !_theResult____h409422[50] && - !_theResult____h409422[49] && - !_theResult____h409422[48] && - !_theResult____h409422[47] && - !_theResult____h409422[46] && - !_theResult____h409422[45] && - !_theResult____h409422[44] && - !_theResult____h409422[43] && - !_theResult____h409422[42] && - !_theResult____h409422[41] && - !_theResult____h409422[40] && - !_theResult____h409422[39] && - !_theResult____h409422[38] && - !_theResult____h409422[37] && - !_theResult____h409422[36] && - !_theResult____h409422[35] && - !_theResult____h409422[34] && - !_theResult____h409422[33] && - !_theResult____h409422[32] && - !_theResult____h409422[31] && - !_theResult____h409422[30] && - !_theResult____h409422[29] && - !_theResult____h409422[28] && - !_theResult____h409422[27] && - !_theResult____h409422[26] && - !_theResult____h409422[25] && - !_theResult____h409422[24] && - !_theResult____h409422[23] && - !_theResult____h409422[22] && - !_theResult____h409422[21] && - !_theResult____h409422[20] && - !_theResult____h409422[19] && - !_theResult____h409422[18] && - !_theResult____h409422[17] && - !_theResult____h409422[16] && - !_theResult____h409422[15] && - !_theResult____h409422[14] && - !_theResult____h409422[13] && - !_theResult____h409422[12] && - !_theResult____h409422[11] && - !_theResult____h409422[10] && - !_theResult____h409422[9] && - !_theResult____h409422[8] && - !_theResult____h409422[7] && - !_theResult____h409422[6] && - !_theResult____h409422[5] && - !_theResult____h409422[4] && - !_theResult____h409422[3] && - !_theResult____h409422[2] && - !_theResult____h409422[1] && - !_theResult____h409422[0] || + assign _theResult___fst_exp__h417732 = + (!_theResult____h409423[56] && !_theResult____h409423[55] && + !_theResult____h409423[54] && + !_theResult____h409423[53] && + !_theResult____h409423[52] && + !_theResult____h409423[51] && + !_theResult____h409423[50] && + !_theResult____h409423[49] && + !_theResult____h409423[48] && + !_theResult____h409423[47] && + !_theResult____h409423[46] && + !_theResult____h409423[45] && + !_theResult____h409423[44] && + !_theResult____h409423[43] && + !_theResult____h409423[42] && + !_theResult____h409423[41] && + !_theResult____h409423[40] && + !_theResult____h409423[39] && + !_theResult____h409423[38] && + !_theResult____h409423[37] && + !_theResult____h409423[36] && + !_theResult____h409423[35] && + !_theResult____h409423[34] && + !_theResult____h409423[33] && + !_theResult____h409423[32] && + !_theResult____h409423[31] && + !_theResult____h409423[30] && + !_theResult____h409423[29] && + !_theResult____h409423[28] && + !_theResult____h409423[27] && + !_theResult____h409423[26] && + !_theResult____h409423[25] && + !_theResult____h409423[24] && + !_theResult____h409423[23] && + !_theResult____h409423[22] && + !_theResult____h409423[21] && + !_theResult____h409423[20] && + !_theResult____h409423[19] && + !_theResult____h409423[18] && + !_theResult____h409423[17] && + !_theResult____h409423[16] && + !_theResult____h409423[15] && + !_theResult____h409423[14] && + !_theResult____h409423[13] && + !_theResult____h409423[12] && + !_theResult____h409423[11] && + !_theResult____h409423[10] && + !_theResult____h409423[9] && + !_theResult____h409423[8] && + !_theResult____h409423[7] && + !_theResult____h409423[6] && + !_theResult____h409423[5] && + !_theResult____h409423[4] && + !_theResult____h409423[3] && + !_theResult____h409423[2] && + !_theResult____h409423[1] && + !_theResult____h409423[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192) ? 8'd0 : - _theResult___fst_exp__h417725 ; - assign _theResult___fst_exp__h417734 = - (!_theResult____h409422[56] && _theResult____h409422[55]) ? + _theResult___fst_exp__h417726 ; + assign _theResult___fst_exp__h417735 = + (!_theResult____h409423[56] && _theResult____h409423[55]) ? 8'd1 : - _theResult___fst_exp__h417731 ; - assign _theResult___fst_exp__h418257 = - (_theResult___fst_exp__h417660 == 8'd255) ? - _theResult___fst_exp__h417660 : - _theResult___fst_exp__h418254 ; - assign _theResult___fst_exp__h426297 = + _theResult___fst_exp__h417732 ; + assign _theResult___fst_exp__h418258 = + (_theResult___fst_exp__h417661 == 8'd255) ? + _theResult___fst_exp__h417661 : + _theResult___fst_exp__h418255 ; + assign _theResult___fst_exp__h426298 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ; - assign _theResult___fst_exp__h426336 = + assign _theResult___fst_exp__h426337 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ; - assign _theResult___fst_exp__h426342 = + assign _theResult___fst_exp__h426343 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265) ? 8'd0 : - _theResult___fst_exp__h426336 ; - assign _theResult___fst_exp__h426345 = + _theResult___fst_exp__h426337 ; + assign _theResult___fst_exp__h426346 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h426342 : - _theResult___fst_exp__h426297 ; - assign _theResult___fst_exp__h426893 = - (_theResult___fst_exp__h426345 == 8'd255) ? - _theResult___fst_exp__h426345 : - _theResult___fst_exp__h426890 ; - assign _theResult___fst_exp__h426902 = + _theResult___fst_exp__h426343 : + _theResult___fst_exp__h426298 ; + assign _theResult___fst_exp__h426894 = + (_theResult___fst_exp__h426346 == 8'd255) ? + _theResult___fst_exp__h426346 : + _theResult___fst_exp__h426891 ; + assign _theResult___fst_exp__h426903 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_exp__h409076 : - _theResult___fst_exp__h391767) : + _theResult___snd_fst_exp__h409077 : + _theResult___fst_exp__h391768) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_exp__h426896 : - _theResult___fst_exp__h391767) ; - assign _theResult___fst_exp__h426905 = + _theResult___snd_fst_exp__h426897 : + _theResult___fst_exp__h391768) ; + assign _theResult___fst_exp__h426906 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h426902 ; - assign _theResult___fst_exp__h445589 = - _theResult____h437480[56] ? + _theResult___fst_exp__h426903 ; + assign _theResult___fst_exp__h445590 = + _theResult____h437481[56] ? 8'd2 : - _theResult___fst_exp__h445663 ; - assign _theResult___fst_exp__h445654 = + _theResult___fst_exp__h445664 ; + assign _theResult___fst_exp__h445655 = 8'd0 - { 2'd0, IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ; - assign _theResult___fst_exp__h445660 = - (!_theResult____h437480[56] && !_theResult____h437480[55] && - !_theResult____h437480[54] && - !_theResult____h437480[53] && - !_theResult____h437480[52] && - !_theResult____h437480[51] && - !_theResult____h437480[50] && - !_theResult____h437480[49] && - !_theResult____h437480[48] && - !_theResult____h437480[47] && - !_theResult____h437480[46] && - !_theResult____h437480[45] && - !_theResult____h437480[44] && - !_theResult____h437480[43] && - !_theResult____h437480[42] && - !_theResult____h437480[41] && - !_theResult____h437480[40] && - !_theResult____h437480[39] && - !_theResult____h437480[38] && - !_theResult____h437480[37] && - !_theResult____h437480[36] && - !_theResult____h437480[35] && - !_theResult____h437480[34] && - !_theResult____h437480[33] && - !_theResult____h437480[32] && - !_theResult____h437480[31] && - !_theResult____h437480[30] && - !_theResult____h437480[29] && - !_theResult____h437480[28] && - !_theResult____h437480[27] && - !_theResult____h437480[26] && - !_theResult____h437480[25] && - !_theResult____h437480[24] && - !_theResult____h437480[23] && - !_theResult____h437480[22] && - !_theResult____h437480[21] && - !_theResult____h437480[20] && - !_theResult____h437480[19] && - !_theResult____h437480[18] && - !_theResult____h437480[17] && - !_theResult____h437480[16] && - !_theResult____h437480[15] && - !_theResult____h437480[14] && - !_theResult____h437480[13] && - !_theResult____h437480[12] && - !_theResult____h437480[11] && - !_theResult____h437480[10] && - !_theResult____h437480[9] && - !_theResult____h437480[8] && - !_theResult____h437480[7] && - !_theResult____h437480[6] && - !_theResult____h437480[5] && - !_theResult____h437480[4] && - !_theResult____h437480[3] && - !_theResult____h437480[2] && - !_theResult____h437480[1] && - !_theResult____h437480[0] || + assign _theResult___fst_exp__h445661 = + (!_theResult____h437481[56] && !_theResult____h437481[55] && + !_theResult____h437481[54] && + !_theResult____h437481[53] && + !_theResult____h437481[52] && + !_theResult____h437481[51] && + !_theResult____h437481[50] && + !_theResult____h437481[49] && + !_theResult____h437481[48] && + !_theResult____h437481[47] && + !_theResult____h437481[46] && + !_theResult____h437481[45] && + !_theResult____h437481[44] && + !_theResult____h437481[43] && + !_theResult____h437481[42] && + !_theResult____h437481[41] && + !_theResult____h437481[40] && + !_theResult____h437481[39] && + !_theResult____h437481[38] && + !_theResult____h437481[37] && + !_theResult____h437481[36] && + !_theResult____h437481[35] && + !_theResult____h437481[34] && + !_theResult____h437481[33] && + !_theResult____h437481[32] && + !_theResult____h437481[31] && + !_theResult____h437481[30] && + !_theResult____h437481[29] && + !_theResult____h437481[28] && + !_theResult____h437481[27] && + !_theResult____h437481[26] && + !_theResult____h437481[25] && + !_theResult____h437481[24] && + !_theResult____h437481[23] && + !_theResult____h437481[22] && + !_theResult____h437481[21] && + !_theResult____h437481[20] && + !_theResult____h437481[19] && + !_theResult____h437481[18] && + !_theResult____h437481[17] && + !_theResult____h437481[16] && + !_theResult____h437481[15] && + !_theResult____h437481[14] && + !_theResult____h437481[13] && + !_theResult____h437481[12] && + !_theResult____h437481[11] && + !_theResult____h437481[10] && + !_theResult____h437481[9] && + !_theResult____h437481[8] && + !_theResult____h437481[7] && + !_theResult____h437481[6] && + !_theResult____h437481[5] && + !_theResult____h437481[4] && + !_theResult____h437481[3] && + !_theResult____h437481[2] && + !_theResult____h437481[1] && + !_theResult____h437481[0] || !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033) ? 8'd0 : - _theResult___fst_exp__h445654 ; - assign _theResult___fst_exp__h445663 = - (!_theResult____h437480[56] && _theResult____h437480[55]) ? + _theResult___fst_exp__h445655 ; + assign _theResult___fst_exp__h445664 = + (!_theResult____h437481[56] && _theResult____h437481[55]) ? 8'd1 : - _theResult___fst_exp__h445660 ; - assign _theResult___fst_exp__h446186 = - (_theResult___fst_exp__h445589 == 8'd255) ? - _theResult___fst_exp__h445589 : - _theResult___fst_exp__h446183 ; - assign _theResult___fst_exp__h454236 = + _theResult___fst_exp__h445661 ; + assign _theResult___fst_exp__h446187 = + (_theResult___fst_exp__h445590 == 8'd255) ? + _theResult___fst_exp__h445590 : + _theResult___fst_exp__h446184 ; + assign _theResult___fst_exp__h454237 = 8'd129 - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h454242 = + assign _theResult___fst_exp__h454243 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264) ? 8'd0 : - _theResult___fst_exp__h454236 ; - assign _theResult___fst_exp__h454245 = + _theResult___fst_exp__h454237 ; + assign _theResult___fst_exp__h454246 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h454242 : + _theResult___fst_exp__h454243 : 8'd129 ; - assign _theResult___fst_exp__h454768 = - (_theResult___fst_exp__h454245 == 8'd255) ? - _theResult___fst_exp__h454245 : - _theResult___fst_exp__h454765 ; - assign _theResult___fst_exp__h463355 = - _theResult____h455117[56] ? + assign _theResult___fst_exp__h454769 = + (_theResult___fst_exp__h454246 == 8'd255) ? + _theResult___fst_exp__h454246 : + _theResult___fst_exp__h454766 ; + assign _theResult___fst_exp__h463356 = + _theResult____h455118[56] ? 8'd2 : - _theResult___fst_exp__h463429 ; - assign _theResult___fst_exp__h463420 = + _theResult___fst_exp__h463430 ; + assign _theResult___fst_exp__h463421 = 8'd0 - { 2'd0, IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ; - assign _theResult___fst_exp__h463426 = - (!_theResult____h455117[56] && !_theResult____h455117[55] && - !_theResult____h455117[54] && - !_theResult____h455117[53] && - !_theResult____h455117[52] && - !_theResult____h455117[51] && - !_theResult____h455117[50] && - !_theResult____h455117[49] && - !_theResult____h455117[48] && - !_theResult____h455117[47] && - !_theResult____h455117[46] && - !_theResult____h455117[45] && - !_theResult____h455117[44] && - !_theResult____h455117[43] && - !_theResult____h455117[42] && - !_theResult____h455117[41] && - !_theResult____h455117[40] && - !_theResult____h455117[39] && - !_theResult____h455117[38] && - !_theResult____h455117[37] && - !_theResult____h455117[36] && - !_theResult____h455117[35] && - !_theResult____h455117[34] && - !_theResult____h455117[33] && - !_theResult____h455117[32] && - !_theResult____h455117[31] && - !_theResult____h455117[30] && - !_theResult____h455117[29] && - !_theResult____h455117[28] && - !_theResult____h455117[27] && - !_theResult____h455117[26] && - !_theResult____h455117[25] && - !_theResult____h455117[24] && - !_theResult____h455117[23] && - !_theResult____h455117[22] && - !_theResult____h455117[21] && - !_theResult____h455117[20] && - !_theResult____h455117[19] && - !_theResult____h455117[18] && - !_theResult____h455117[17] && - !_theResult____h455117[16] && - !_theResult____h455117[15] && - !_theResult____h455117[14] && - !_theResult____h455117[13] && - !_theResult____h455117[12] && - !_theResult____h455117[11] && - !_theResult____h455117[10] && - !_theResult____h455117[9] && - !_theResult____h455117[8] && - !_theResult____h455117[7] && - !_theResult____h455117[6] && - !_theResult____h455117[5] && - !_theResult____h455117[4] && - !_theResult____h455117[3] && - !_theResult____h455117[2] && - !_theResult____h455117[1] && - !_theResult____h455117[0] || + assign _theResult___fst_exp__h463427 = + (!_theResult____h455118[56] && !_theResult____h455118[55] && + !_theResult____h455118[54] && + !_theResult____h455118[53] && + !_theResult____h455118[52] && + !_theResult____h455118[51] && + !_theResult____h455118[50] && + !_theResult____h455118[49] && + !_theResult____h455118[48] && + !_theResult____h455118[47] && + !_theResult____h455118[46] && + !_theResult____h455118[45] && + !_theResult____h455118[44] && + !_theResult____h455118[43] && + !_theResult____h455118[42] && + !_theResult____h455118[41] && + !_theResult____h455118[40] && + !_theResult____h455118[39] && + !_theResult____h455118[38] && + !_theResult____h455118[37] && + !_theResult____h455118[36] && + !_theResult____h455118[35] && + !_theResult____h455118[34] && + !_theResult____h455118[33] && + !_theResult____h455118[32] && + !_theResult____h455118[31] && + !_theResult____h455118[30] && + !_theResult____h455118[29] && + !_theResult____h455118[28] && + !_theResult____h455118[27] && + !_theResult____h455118[26] && + !_theResult____h455118[25] && + !_theResult____h455118[24] && + !_theResult____h455118[23] && + !_theResult____h455118[22] && + !_theResult____h455118[21] && + !_theResult____h455118[20] && + !_theResult____h455118[19] && + !_theResult____h455118[18] && + !_theResult____h455118[17] && + !_theResult____h455118[16] && + !_theResult____h455118[15] && + !_theResult____h455118[14] && + !_theResult____h455118[13] && + !_theResult____h455118[12] && + !_theResult____h455118[11] && + !_theResult____h455118[10] && + !_theResult____h455118[9] && + !_theResult____h455118[8] && + !_theResult____h455118[7] && + !_theResult____h455118[6] && + !_theResult____h455118[5] && + !_theResult____h455118[4] && + !_theResult____h455118[3] && + !_theResult____h455118[2] && + !_theResult____h455118[1] && + !_theResult____h455118[0] || !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584) ? 8'd0 : - _theResult___fst_exp__h463420 ; - assign _theResult___fst_exp__h463429 = - (!_theResult____h455117[56] && _theResult____h455117[55]) ? + _theResult___fst_exp__h463421 ; + assign _theResult___fst_exp__h463430 = + (!_theResult____h455118[56] && _theResult____h455118[55]) ? 8'd1 : - _theResult___fst_exp__h463426 ; - assign _theResult___fst_exp__h463952 = - (_theResult___fst_exp__h463355 == 8'd255) ? - _theResult___fst_exp__h463355 : - _theResult___fst_exp__h463949 ; - assign _theResult___fst_exp__h471992 = + _theResult___fst_exp__h463427 ; + assign _theResult___fst_exp__h463953 = + (_theResult___fst_exp__h463356 == 8'd255) ? + _theResult___fst_exp__h463356 : + _theResult___fst_exp__h463950 ; + assign _theResult___fst_exp__h471993 = (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] == 8'd0) ? 8'd1 : SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ; - assign _theResult___fst_exp__h472031 = + assign _theResult___fst_exp__h472032 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] - { 2'd0, IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ; - assign _theResult___fst_exp__h472037 = + assign _theResult___fst_exp__h472038 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 || !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657) ? 8'd0 : - _theResult___fst_exp__h472031 ; - assign _theResult___fst_exp__h472040 = + _theResult___fst_exp__h472032 ; + assign _theResult___fst_exp__h472041 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___fst_exp__h472037 : - _theResult___fst_exp__h471992 ; - assign _theResult___fst_exp__h472588 = - (_theResult___fst_exp__h472040 == 8'd255) ? - _theResult___fst_exp__h472040 : - _theResult___fst_exp__h472585 ; - assign _theResult___fst_exp__h472597 = + _theResult___fst_exp__h472038 : + _theResult___fst_exp__h471993 ; + assign _theResult___fst_exp__h472589 = + (_theResult___fst_exp__h472041 == 8'd255) ? + _theResult___fst_exp__h472041 : + _theResult___fst_exp__h472586 ; + assign _theResult___fst_exp__h472598 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_exp__h454771 : - _theResult___fst_exp__h437462) : + _theResult___snd_fst_exp__h454772 : + _theResult___fst_exp__h437463) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_exp__h472591 : - _theResult___fst_exp__h437462) ; - assign _theResult___fst_exp__h472600 = + _theResult___snd_fst_exp__h472592 : + _theResult___fst_exp__h437463) ; + assign _theResult___fst_exp__h472601 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 8'd0 : - _theResult___fst_exp__h472597 ; - assign _theResult___fst_exp__h486456 = + _theResult___fst_exp__h472598 ; + assign _theResult___fst_exp__h486457 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ; - assign _theResult___fst_exp__h501520 = + assign _theResult___fst_exp__h501521 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h501526 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___fst_exp__h501527 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585) ? 11'd0 : - _theResult___fst_exp__h501520 ; - assign _theResult___fst_exp__h501529 = - (f1_exp__h482141 == 8'd0) ? - _theResult___fst_exp__h501526 : + _theResult___fst_exp__h501521 ; + assign _theResult___fst_exp__h501530 = + (f1_exp__h482142 == 8'd0) ? + _theResult___fst_exp__h501527 : 11'd897 ; - assign _theResult___fst_exp__h502284 = + assign _theResult___fst_exp__h502285 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 : + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 ; - assign _theResult___fst_exp__h502287 = - (_theResult___fst_exp__h501529 == 11'd2047) ? - _theResult___fst_exp__h501529 : - _theResult___fst_exp__h502284 ; - assign _theResult___fst_exp__h511106 = - _theResult____h502870[56] ? + assign _theResult___fst_exp__h502288 = + (_theResult___fst_exp__h501530 == 11'd2047) ? + _theResult___fst_exp__h501530 : + _theResult___fst_exp__h502285 ; + assign _theResult___fst_exp__h511107 = + _theResult____h502871[56] ? 11'd2 : - _theResult___fst_exp__h511180 ; - assign _theResult___fst_exp__h511171 = + _theResult___fst_exp__h511181 ; + assign _theResult___fst_exp__h511172 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ; - assign _theResult___fst_exp__h511177 = - (!_theResult____h502870[56] && !_theResult____h502870[55] && - !_theResult____h502870[54] && - !_theResult____h502870[53] && - !_theResult____h502870[52] && - !_theResult____h502870[51] && - !_theResult____h502870[50] && - !_theResult____h502870[49] && - !_theResult____h502870[48] && - !_theResult____h502870[47] && - !_theResult____h502870[46] && - !_theResult____h502870[45] && - !_theResult____h502870[44] && - !_theResult____h502870[43] && - !_theResult____h502870[42] && - !_theResult____h502870[41] && - !_theResult____h502870[40] && - !_theResult____h502870[39] && - !_theResult____h502870[38] && - !_theResult____h502870[37] && - !_theResult____h502870[36] && - !_theResult____h502870[35] && - !_theResult____h502870[34] && - !_theResult____h502870[33] && - !_theResult____h502870[32] && - !_theResult____h502870[31] && - !_theResult____h502870[30] && - !_theResult____h502870[29] && - !_theResult____h502870[28] && - !_theResult____h502870[27] && - !_theResult____h502870[26] && - !_theResult____h502870[25] && - !_theResult____h502870[24] && - !_theResult____h502870[23] && - !_theResult____h502870[22] && - !_theResult____h502870[21] && - !_theResult____h502870[20] && - !_theResult____h502870[19] && - !_theResult____h502870[18] && - !_theResult____h502870[17] && - !_theResult____h502870[16] && - !_theResult____h502870[15] && - !_theResult____h502870[14] && - !_theResult____h502870[13] && - !_theResult____h502870[12] && - !_theResult____h502870[11] && - !_theResult____h502870[10] && - !_theResult____h502870[9] && - !_theResult____h502870[8] && - !_theResult____h502870[7] && - !_theResult____h502870[6] && - !_theResult____h502870[5] && - !_theResult____h502870[4] && - !_theResult____h502870[3] && - !_theResult____h502870[2] && - !_theResult____h502870[1] && - !_theResult____h502870[0] || + assign _theResult___fst_exp__h511178 = + (!_theResult____h502871[56] && !_theResult____h502871[55] && + !_theResult____h502871[54] && + !_theResult____h502871[53] && + !_theResult____h502871[52] && + !_theResult____h502871[51] && + !_theResult____h502871[50] && + !_theResult____h502871[49] && + !_theResult____h502871[48] && + !_theResult____h502871[47] && + !_theResult____h502871[46] && + !_theResult____h502871[45] && + !_theResult____h502871[44] && + !_theResult____h502871[43] && + !_theResult____h502871[42] && + !_theResult____h502871[41] && + !_theResult____h502871[40] && + !_theResult____h502871[39] && + !_theResult____h502871[38] && + !_theResult____h502871[37] && + !_theResult____h502871[36] && + !_theResult____h502871[35] && + !_theResult____h502871[34] && + !_theResult____h502871[33] && + !_theResult____h502871[32] && + !_theResult____h502871[31] && + !_theResult____h502871[30] && + !_theResult____h502871[29] && + !_theResult____h502871[28] && + !_theResult____h502871[27] && + !_theResult____h502871[26] && + !_theResult____h502871[25] && + !_theResult____h502871[24] && + !_theResult____h502871[23] && + !_theResult____h502871[22] && + !_theResult____h502871[21] && + !_theResult____h502871[20] && + !_theResult____h502871[19] && + !_theResult____h502871[18] && + !_theResult____h502871[17] && + !_theResult____h502871[16] && + !_theResult____h502871[15] && + !_theResult____h502871[14] && + !_theResult____h502871[13] && + !_theResult____h502871[12] && + !_theResult____h502871[11] && + !_theResult____h502871[10] && + !_theResult____h502871[9] && + !_theResult____h502871[8] && + !_theResult____h502871[7] && + !_theResult____h502871[6] && + !_theResult____h502871[5] && + !_theResult____h502871[4] && + !_theResult____h502871[3] && + !_theResult____h502871[2] && + !_theResult____h502871[1] && + !_theResult____h502871[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897) ? 11'd0 : - _theResult___fst_exp__h511171 ; - assign _theResult___fst_exp__h511180 = - (!_theResult____h502870[56] && _theResult____h502870[55]) ? + _theResult___fst_exp__h511172 ; + assign _theResult___fst_exp__h511181 = + (!_theResult____h502871[56] && _theResult____h502871[55]) ? 11'd1 : - _theResult___fst_exp__h511177 ; - assign _theResult___fst_exp__h511935 = + _theResult___fst_exp__h511178 ; + assign _theResult___fst_exp__h511936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 : + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 ; - assign _theResult___fst_exp__h511938 = - (_theResult___fst_exp__h511106 == 11'd2047) ? - _theResult___fst_exp__h511106 : - _theResult___fst_exp__h511935 ; - assign _theResult___fst_exp__h519891 = + assign _theResult___fst_exp__h511939 = + (_theResult___fst_exp__h511107 == 11'd2047) ? + _theResult___fst_exp__h511107 : + _theResult___fst_exp__h511936 ; + assign _theResult___fst_exp__h519892 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ; - assign _theResult___fst_exp__h519930 = + assign _theResult___fst_exp__h519931 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ; - assign _theResult___fst_exp__h519936 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___fst_exp__h519937 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947) ? 11'd0 : - _theResult___fst_exp__h519930 ; - assign _theResult___fst_exp__h519939 = - (f1_exp__h482141 == 8'd0) ? - _theResult___fst_exp__h519936 : - _theResult___fst_exp__h519891 ; - assign _theResult___fst_exp__h520719 = + _theResult___fst_exp__h519931 ; + assign _theResult___fst_exp__h519940 = + (f1_exp__h482142 == 8'd0) ? + _theResult___fst_exp__h519937 : + _theResult___fst_exp__h519892 ; + assign _theResult___fst_exp__h520720 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 : + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 ; - assign _theResult___fst_exp__h520722 = - (_theResult___fst_exp__h519939 == 11'd2047) ? - _theResult___fst_exp__h519939 : - _theResult___fst_exp__h520719 ; - assign _theResult___fst_exp__h520731 = - (f1_exp__h482141 == 8'd0) ? + assign _theResult___fst_exp__h520723 = + (_theResult___fst_exp__h519940 == 11'd2047) ? + _theResult___fst_exp__h519940 : + _theResult___fst_exp__h520720 ; + assign _theResult___fst_exp__h520732 = + (f1_exp__h482142 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_exp__h502290 : - _theResult___fst_exp__h486456) : + _theResult___snd_fst_exp__h502291 : + _theResult___fst_exp__h486457) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_exp__h520725 : - _theResult___fst_exp__h486456) ; - assign _theResult___fst_exp__h520734 = - (f1_exp__h482141 == 8'd0 && f1_sfd__h482142 == 23'd0) ? + _theResult___snd_fst_exp__h520726 : + _theResult___fst_exp__h486457) ; + assign _theResult___fst_exp__h520735 = + (f1_exp__h482142 == 8'd0 && f1_sfd__h482143 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h520731 ; - assign _theResult___fst_exp__h525309 = + _theResult___fst_exp__h520732 ; + assign _theResult___fst_exp__h525310 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ; - assign _theResult___fst_exp__h540373 = + assign _theResult___fst_exp__h540374 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h540379 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___fst_exp__h540380 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085) ? 11'd0 : - _theResult___fst_exp__h540373 ; - assign _theResult___fst_exp__h540382 = - (f2_exp__h521135 == 8'd0) ? - _theResult___fst_exp__h540379 : + _theResult___fst_exp__h540374 ; + assign _theResult___fst_exp__h540383 = + (f2_exp__h521136 == 8'd0) ? + _theResult___fst_exp__h540380 : 11'd897 ; - assign _theResult___fst_exp__h541137 = + assign _theResult___fst_exp__h541138 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 : + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 ; - assign _theResult___fst_exp__h541140 = - (_theResult___fst_exp__h540382 == 11'd2047) ? - _theResult___fst_exp__h540382 : - _theResult___fst_exp__h541137 ; - assign _theResult___fst_exp__h549959 = - _theResult____h541723[56] ? + assign _theResult___fst_exp__h541141 = + (_theResult___fst_exp__h540383 == 11'd2047) ? + _theResult___fst_exp__h540383 : + _theResult___fst_exp__h541138 ; + assign _theResult___fst_exp__h549960 = + _theResult____h541724[56] ? 11'd2 : - _theResult___fst_exp__h550033 ; - assign _theResult___fst_exp__h550024 = + _theResult___fst_exp__h550034 ; + assign _theResult___fst_exp__h550025 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ; - assign _theResult___fst_exp__h550030 = - (!_theResult____h541723[56] && !_theResult____h541723[55] && - !_theResult____h541723[54] && - !_theResult____h541723[53] && - !_theResult____h541723[52] && - !_theResult____h541723[51] && - !_theResult____h541723[50] && - !_theResult____h541723[49] && - !_theResult____h541723[48] && - !_theResult____h541723[47] && - !_theResult____h541723[46] && - !_theResult____h541723[45] && - !_theResult____h541723[44] && - !_theResult____h541723[43] && - !_theResult____h541723[42] && - !_theResult____h541723[41] && - !_theResult____h541723[40] && - !_theResult____h541723[39] && - !_theResult____h541723[38] && - !_theResult____h541723[37] && - !_theResult____h541723[36] && - !_theResult____h541723[35] && - !_theResult____h541723[34] && - !_theResult____h541723[33] && - !_theResult____h541723[32] && - !_theResult____h541723[31] && - !_theResult____h541723[30] && - !_theResult____h541723[29] && - !_theResult____h541723[28] && - !_theResult____h541723[27] && - !_theResult____h541723[26] && - !_theResult____h541723[25] && - !_theResult____h541723[24] && - !_theResult____h541723[23] && - !_theResult____h541723[22] && - !_theResult____h541723[21] && - !_theResult____h541723[20] && - !_theResult____h541723[19] && - !_theResult____h541723[18] && - !_theResult____h541723[17] && - !_theResult____h541723[16] && - !_theResult____h541723[15] && - !_theResult____h541723[14] && - !_theResult____h541723[13] && - !_theResult____h541723[12] && - !_theResult____h541723[11] && - !_theResult____h541723[10] && - !_theResult____h541723[9] && - !_theResult____h541723[8] && - !_theResult____h541723[7] && - !_theResult____h541723[6] && - !_theResult____h541723[5] && - !_theResult____h541723[4] && - !_theResult____h541723[3] && - !_theResult____h541723[2] && - !_theResult____h541723[1] && - !_theResult____h541723[0] || + assign _theResult___fst_exp__h550031 = + (!_theResult____h541724[56] && !_theResult____h541724[55] && + !_theResult____h541724[54] && + !_theResult____h541724[53] && + !_theResult____h541724[52] && + !_theResult____h541724[51] && + !_theResult____h541724[50] && + !_theResult____h541724[49] && + !_theResult____h541724[48] && + !_theResult____h541724[47] && + !_theResult____h541724[46] && + !_theResult____h541724[45] && + !_theResult____h541724[44] && + !_theResult____h541724[43] && + !_theResult____h541724[42] && + !_theResult____h541724[41] && + !_theResult____h541724[40] && + !_theResult____h541724[39] && + !_theResult____h541724[38] && + !_theResult____h541724[37] && + !_theResult____h541724[36] && + !_theResult____h541724[35] && + !_theResult____h541724[34] && + !_theResult____h541724[33] && + !_theResult____h541724[32] && + !_theResult____h541724[31] && + !_theResult____h541724[30] && + !_theResult____h541724[29] && + !_theResult____h541724[28] && + !_theResult____h541724[27] && + !_theResult____h541724[26] && + !_theResult____h541724[25] && + !_theResult____h541724[24] && + !_theResult____h541724[23] && + !_theResult____h541724[22] && + !_theResult____h541724[21] && + !_theResult____h541724[20] && + !_theResult____h541724[19] && + !_theResult____h541724[18] && + !_theResult____h541724[17] && + !_theResult____h541724[16] && + !_theResult____h541724[15] && + !_theResult____h541724[14] && + !_theResult____h541724[13] && + !_theResult____h541724[12] && + !_theResult____h541724[11] && + !_theResult____h541724[10] && + !_theResult____h541724[9] && + !_theResult____h541724[8] && + !_theResult____h541724[7] && + !_theResult____h541724[6] && + !_theResult____h541724[5] && + !_theResult____h541724[4] && + !_theResult____h541724[3] && + !_theResult____h541724[2] && + !_theResult____h541724[1] && + !_theResult____h541724[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382) ? 11'd0 : - _theResult___fst_exp__h550024 ; - assign _theResult___fst_exp__h550033 = - (!_theResult____h541723[56] && _theResult____h541723[55]) ? + _theResult___fst_exp__h550025 ; + assign _theResult___fst_exp__h550034 = + (!_theResult____h541724[56] && _theResult____h541724[55]) ? 11'd1 : - _theResult___fst_exp__h550030 ; - assign _theResult___fst_exp__h550788 = + _theResult___fst_exp__h550031 ; + assign _theResult___fst_exp__h550789 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 : + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 ; - assign _theResult___fst_exp__h550791 = - (_theResult___fst_exp__h549959 == 11'd2047) ? - _theResult___fst_exp__h549959 : - _theResult___fst_exp__h550788 ; - assign _theResult___fst_exp__h558744 = + assign _theResult___fst_exp__h550792 = + (_theResult___fst_exp__h549960 == 11'd2047) ? + _theResult___fst_exp__h549960 : + _theResult___fst_exp__h550789 ; + assign _theResult___fst_exp__h558745 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ; - assign _theResult___fst_exp__h558783 = + assign _theResult___fst_exp__h558784 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ; - assign _theResult___fst_exp__h558789 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___fst_exp__h558790 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432) ? 11'd0 : - _theResult___fst_exp__h558783 ; - assign _theResult___fst_exp__h558792 = - (f2_exp__h521135 == 8'd0) ? - _theResult___fst_exp__h558789 : - _theResult___fst_exp__h558744 ; - assign _theResult___fst_exp__h559572 = + _theResult___fst_exp__h558784 ; + assign _theResult___fst_exp__h558793 = + (f2_exp__h521136 == 8'd0) ? + _theResult___fst_exp__h558790 : + _theResult___fst_exp__h558745 ; + assign _theResult___fst_exp__h559573 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 : + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ; - assign _theResult___fst_exp__h559575 = - (_theResult___fst_exp__h558792 == 11'd2047) ? - _theResult___fst_exp__h558792 : - _theResult___fst_exp__h559572 ; - assign _theResult___fst_exp__h559584 = - (f2_exp__h521135 == 8'd0) ? + assign _theResult___fst_exp__h559576 = + (_theResult___fst_exp__h558793 == 11'd2047) ? + _theResult___fst_exp__h558793 : + _theResult___fst_exp__h559573 ; + assign _theResult___fst_exp__h559585 = + (f2_exp__h521136 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_exp__h541143 : - _theResult___fst_exp__h525309) : + _theResult___snd_fst_exp__h541144 : + _theResult___fst_exp__h525310) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_exp__h559578 : - _theResult___fst_exp__h525309) ; - assign _theResult___fst_exp__h559587 = - (f2_exp__h521135 == 8'd0 && f2_sfd__h521136 == 23'd0) ? + _theResult___snd_fst_exp__h559579 : + _theResult___fst_exp__h525310) ; + assign _theResult___fst_exp__h559588 = + (f2_exp__h521136 == 8'd0 && f2_sfd__h521137 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h559584 ; - assign _theResult___fst_exp__h564613 = + _theResult___fst_exp__h559585 ; + assign _theResult___fst_exp__h564614 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 11'd2047 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ; - assign _theResult___fst_exp__h579677 = + assign _theResult___fst_exp__h579678 = 11'd897 - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h579683 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___fst_exp__h579684 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315) ? 11'd0 : - _theResult___fst_exp__h579677 ; - assign _theResult___fst_exp__h579686 = - (f3_exp__h560439 == 8'd0) ? - _theResult___fst_exp__h579683 : + _theResult___fst_exp__h579678 ; + assign _theResult___fst_exp__h579687 = + (f3_exp__h560440 == 8'd0) ? + _theResult___fst_exp__h579684 : 11'd897 ; - assign _theResult___fst_exp__h580441 = + assign _theResult___fst_exp__h580442 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 : + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 ; - assign _theResult___fst_exp__h580444 = - (_theResult___fst_exp__h579686 == 11'd2047) ? - _theResult___fst_exp__h579686 : - _theResult___fst_exp__h580441 ; - assign _theResult___fst_exp__h589263 = - _theResult____h581027[56] ? + assign _theResult___fst_exp__h580445 = + (_theResult___fst_exp__h579687 == 11'd2047) ? + _theResult___fst_exp__h579687 : + _theResult___fst_exp__h580442 ; + assign _theResult___fst_exp__h589264 = + _theResult____h581028[56] ? 11'd2 : - _theResult___fst_exp__h589337 ; - assign _theResult___fst_exp__h589328 = + _theResult___fst_exp__h589338 ; + assign _theResult___fst_exp__h589329 = 11'd0 - { 5'd0, IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ; - assign _theResult___fst_exp__h589334 = - (!_theResult____h581027[56] && !_theResult____h581027[55] && - !_theResult____h581027[54] && - !_theResult____h581027[53] && - !_theResult____h581027[52] && - !_theResult____h581027[51] && - !_theResult____h581027[50] && - !_theResult____h581027[49] && - !_theResult____h581027[48] && - !_theResult____h581027[47] && - !_theResult____h581027[46] && - !_theResult____h581027[45] && - !_theResult____h581027[44] && - !_theResult____h581027[43] && - !_theResult____h581027[42] && - !_theResult____h581027[41] && - !_theResult____h581027[40] && - !_theResult____h581027[39] && - !_theResult____h581027[38] && - !_theResult____h581027[37] && - !_theResult____h581027[36] && - !_theResult____h581027[35] && - !_theResult____h581027[34] && - !_theResult____h581027[33] && - !_theResult____h581027[32] && - !_theResult____h581027[31] && - !_theResult____h581027[30] && - !_theResult____h581027[29] && - !_theResult____h581027[28] && - !_theResult____h581027[27] && - !_theResult____h581027[26] && - !_theResult____h581027[25] && - !_theResult____h581027[24] && - !_theResult____h581027[23] && - !_theResult____h581027[22] && - !_theResult____h581027[21] && - !_theResult____h581027[20] && - !_theResult____h581027[19] && - !_theResult____h581027[18] && - !_theResult____h581027[17] && - !_theResult____h581027[16] && - !_theResult____h581027[15] && - !_theResult____h581027[14] && - !_theResult____h581027[13] && - !_theResult____h581027[12] && - !_theResult____h581027[11] && - !_theResult____h581027[10] && - !_theResult____h581027[9] && - !_theResult____h581027[8] && - !_theResult____h581027[7] && - !_theResult____h581027[6] && - !_theResult____h581027[5] && - !_theResult____h581027[4] && - !_theResult____h581027[3] && - !_theResult____h581027[2] && - !_theResult____h581027[1] && - !_theResult____h581027[0] || + assign _theResult___fst_exp__h589335 = + (!_theResult____h581028[56] && !_theResult____h581028[55] && + !_theResult____h581028[54] && + !_theResult____h581028[53] && + !_theResult____h581028[52] && + !_theResult____h581028[51] && + !_theResult____h581028[50] && + !_theResult____h581028[49] && + !_theResult____h581028[48] && + !_theResult____h581028[47] && + !_theResult____h581028[46] && + !_theResult____h581028[45] && + !_theResult____h581028[44] && + !_theResult____h581028[43] && + !_theResult____h581028[42] && + !_theResult____h581028[41] && + !_theResult____h581028[40] && + !_theResult____h581028[39] && + !_theResult____h581028[38] && + !_theResult____h581028[37] && + !_theResult____h581028[36] && + !_theResult____h581028[35] && + !_theResult____h581028[34] && + !_theResult____h581028[33] && + !_theResult____h581028[32] && + !_theResult____h581028[31] && + !_theResult____h581028[30] && + !_theResult____h581028[29] && + !_theResult____h581028[28] && + !_theResult____h581028[27] && + !_theResult____h581028[26] && + !_theResult____h581028[25] && + !_theResult____h581028[24] && + !_theResult____h581028[23] && + !_theResult____h581028[22] && + !_theResult____h581028[21] && + !_theResult____h581028[20] && + !_theResult____h581028[19] && + !_theResult____h581028[18] && + !_theResult____h581028[17] && + !_theResult____h581028[16] && + !_theResult____h581028[15] && + !_theResult____h581028[14] && + !_theResult____h581028[13] && + !_theResult____h581028[12] && + !_theResult____h581028[11] && + !_theResult____h581028[10] && + !_theResult____h581028[9] && + !_theResult____h581028[8] && + !_theResult____h581028[7] && + !_theResult____h581028[6] && + !_theResult____h581028[5] && + !_theResult____h581028[4] && + !_theResult____h581028[3] && + !_theResult____h581028[2] && + !_theResult____h581028[1] && + !_theResult____h581028[0] || !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612) ? 11'd0 : - _theResult___fst_exp__h589328 ; - assign _theResult___fst_exp__h589337 = - (!_theResult____h581027[56] && _theResult____h581027[55]) ? + _theResult___fst_exp__h589329 ; + assign _theResult___fst_exp__h589338 = + (!_theResult____h581028[56] && _theResult____h581028[55]) ? 11'd1 : - _theResult___fst_exp__h589334 ; - assign _theResult___fst_exp__h590092 = + _theResult___fst_exp__h589335 ; + assign _theResult___fst_exp__h590093 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 : + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ; - assign _theResult___fst_exp__h590095 = - (_theResult___fst_exp__h589263 == 11'd2047) ? - _theResult___fst_exp__h589263 : - _theResult___fst_exp__h590092 ; - assign _theResult___fst_exp__h598048 = + assign _theResult___fst_exp__h590096 = + (_theResult___fst_exp__h589264 == 11'd2047) ? + _theResult___fst_exp__h589264 : + _theResult___fst_exp__h590093 ; + assign _theResult___fst_exp__h598049 = (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] == 11'd0) ? 11'd1 : SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ; - assign _theResult___fst_exp__h598087 = + assign _theResult___fst_exp__h598088 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] - { 5'd0, IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ; - assign _theResult___fst_exp__h598093 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___fst_exp__h598094 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 || !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662) ? 11'd0 : - _theResult___fst_exp__h598087 ; - assign _theResult___fst_exp__h598096 = - (f3_exp__h560439 == 8'd0) ? - _theResult___fst_exp__h598093 : - _theResult___fst_exp__h598048 ; - assign _theResult___fst_exp__h598876 = + _theResult___fst_exp__h598088 ; + assign _theResult___fst_exp__h598097 = + (f3_exp__h560440 == 8'd0) ? + _theResult___fst_exp__h598094 : + _theResult___fst_exp__h598049 ; + assign _theResult___fst_exp__h598877 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 : + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ; - assign _theResult___fst_exp__h598879 = - (_theResult___fst_exp__h598096 == 11'd2047) ? - _theResult___fst_exp__h598096 : - _theResult___fst_exp__h598876 ; - assign _theResult___fst_exp__h598888 = - (f3_exp__h560439 == 8'd0) ? + assign _theResult___fst_exp__h598880 = + (_theResult___fst_exp__h598097 == 11'd2047) ? + _theResult___fst_exp__h598097 : + _theResult___fst_exp__h598877 ; + assign _theResult___fst_exp__h598889 = + (f3_exp__h560440 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_exp__h580447 : - _theResult___fst_exp__h564613) : + _theResult___snd_fst_exp__h580448 : + _theResult___fst_exp__h564614) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_exp__h598882 : - _theResult___fst_exp__h564613) ; - assign _theResult___fst_exp__h598891 = - (f3_exp__h560439 == 8'd0 && f3_sfd__h560440 == 23'd0) ? + _theResult___snd_fst_exp__h598883 : + _theResult___fst_exp__h564614) ; + assign _theResult___fst_exp__h598892 = + (f3_exp__h560440 == 8'd0 && f3_sfd__h560441 == 23'd0) ? 11'd0 : - _theResult___fst_exp__h598888 ; - assign _theResult___fst_sfd__h354795 = - (_theResult___fst_exp__h354197 == 8'd255) ? - sfdin__h354191[56:34] : - _theResult___fst_sfd__h354792 ; - assign _theResult___fst_sfd__h363377 = - (_theResult___fst_exp__h362853 == 8'd255) ? - _theResult___snd__h362804[56:34] : - _theResult___fst_sfd__h363374 ; - assign _theResult___fst_sfd__h372561 = - (_theResult___fst_exp__h371963 == 8'd255) ? - sfdin__h371957[56:34] : - _theResult___fst_sfd__h372558 ; - assign _theResult___fst_sfd__h381197 = - (_theResult___fst_exp__h380648 == 8'd255) ? - _theResult___snd__h380594[56:34] : - _theResult___fst_sfd__h381194 ; - assign _theResult___fst_sfd__h381206 = + _theResult___fst_exp__h598889 ; + assign _theResult___fst_sfd__h354796 = + (_theResult___fst_exp__h354198 == 8'd255) ? + sfdin__h354192[56:34] : + _theResult___fst_sfd__h354793 ; + assign _theResult___fst_sfd__h363378 = + (_theResult___fst_exp__h362854 == 8'd255) ? + _theResult___snd__h362805[56:34] : + _theResult___fst_sfd__h363375 ; + assign _theResult___fst_sfd__h372562 = + (_theResult___fst_exp__h371964 == 8'd255) ? + sfdin__h371958[56:34] : + _theResult___fst_sfd__h372559 ; + assign _theResult___fst_sfd__h381198 = + (_theResult___fst_exp__h380649 == 8'd255) ? + _theResult___snd__h380595[56:34] : + _theResult___fst_sfd__h381195 ; + assign _theResult___fst_sfd__h381207 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ? - _theResult___snd_fst_sfd__h363380 : - _theResult___fst_sfd__h346069) : + _theResult___snd_fst_sfd__h363381 : + _theResult___fst_sfd__h346070) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ? - _theResult___snd_fst_sfd__h381200 : - _theResult___fst_sfd__h346069) ; - assign _theResult___fst_sfd__h381212 = + _theResult___snd_fst_sfd__h381201 : + _theResult___fst_sfd__h346070) ; + assign _theResult___fst_sfd__h381213 = ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == @@ -28203,33 +28203,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h381206 ; - assign _theResult___fst_sfd__h400492 = - (_theResult___fst_exp__h399894 == 8'd255) ? - sfdin__h399888[56:34] : - _theResult___fst_sfd__h400489 ; - assign _theResult___fst_sfd__h409074 = - (_theResult___fst_exp__h408550 == 8'd255) ? - _theResult___snd__h408501[56:34] : - _theResult___fst_sfd__h409071 ; - assign _theResult___fst_sfd__h418258 = - (_theResult___fst_exp__h417660 == 8'd255) ? - sfdin__h417654[56:34] : - _theResult___fst_sfd__h418255 ; - assign _theResult___fst_sfd__h426894 = - (_theResult___fst_exp__h426345 == 8'd255) ? - _theResult___snd__h426291[56:34] : - _theResult___fst_sfd__h426891 ; - assign _theResult___fst_sfd__h426903 = + _theResult___fst_sfd__h381207 ; + assign _theResult___fst_sfd__h400493 = + (_theResult___fst_exp__h399895 == 8'd255) ? + sfdin__h399889[56:34] : + _theResult___fst_sfd__h400490 ; + assign _theResult___fst_sfd__h409075 = + (_theResult___fst_exp__h408551 == 8'd255) ? + _theResult___snd__h408502[56:34] : + _theResult___fst_sfd__h409072 ; + assign _theResult___fst_sfd__h418259 = + (_theResult___fst_exp__h417661 == 8'd255) ? + sfdin__h417655[56:34] : + _theResult___fst_sfd__h418256 ; + assign _theResult___fst_sfd__h426895 = + (_theResult___fst_exp__h426346 == 8'd255) ? + _theResult___snd__h426292[56:34] : + _theResult___fst_sfd__h426892 ; + assign _theResult___fst_sfd__h426904 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ? - _theResult___snd_fst_sfd__h409077 : - _theResult___fst_sfd__h391768) : + _theResult___snd_fst_sfd__h409078 : + _theResult___fst_sfd__h391769) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ? - _theResult___snd_fst_sfd__h426897 : - _theResult___fst_sfd__h391768) ; - assign _theResult___fst_sfd__h426909 = + _theResult___snd_fst_sfd__h426898 : + _theResult___fst_sfd__h391769) ; + assign _theResult___fst_sfd__h426910 = ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == @@ -28237,33 +28237,33 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h426903 ; - assign _theResult___fst_sfd__h446187 = - (_theResult___fst_exp__h445589 == 8'd255) ? - sfdin__h445583[56:34] : - _theResult___fst_sfd__h446184 ; - assign _theResult___fst_sfd__h454769 = - (_theResult___fst_exp__h454245 == 8'd255) ? - _theResult___snd__h454196[56:34] : - _theResult___fst_sfd__h454766 ; - assign _theResult___fst_sfd__h463953 = - (_theResult___fst_exp__h463355 == 8'd255) ? - sfdin__h463349[56:34] : - _theResult___fst_sfd__h463950 ; - assign _theResult___fst_sfd__h472589 = - (_theResult___fst_exp__h472040 == 8'd255) ? - _theResult___snd__h471986[56:34] : - _theResult___fst_sfd__h472586 ; - assign _theResult___fst_sfd__h472598 = + _theResult___fst_sfd__h426904 ; + assign _theResult___fst_sfd__h446188 = + (_theResult___fst_exp__h445590 == 8'd255) ? + sfdin__h445584[56:34] : + _theResult___fst_sfd__h446185 ; + assign _theResult___fst_sfd__h454770 = + (_theResult___fst_exp__h454246 == 8'd255) ? + _theResult___snd__h454197[56:34] : + _theResult___fst_sfd__h454767 ; + assign _theResult___fst_sfd__h463954 = + (_theResult___fst_exp__h463356 == 8'd255) ? + sfdin__h463350[56:34] : + _theResult___fst_sfd__h463951 ; + assign _theResult___fst_sfd__h472590 = + (_theResult___fst_exp__h472041 == 8'd255) ? + _theResult___snd__h471987[56:34] : + _theResult___fst_sfd__h472587 ; + assign _theResult___fst_sfd__h472599 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ? - _theResult___snd_fst_sfd__h454772 : - _theResult___fst_sfd__h437463) : + _theResult___snd_fst_sfd__h454773 : + _theResult___fst_sfd__h437464) : (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ? - _theResult___snd_fst_sfd__h472592 : - _theResult___fst_sfd__h437463) ; - assign _theResult___fst_sfd__h472604 = + _theResult___snd_fst_sfd__h472593 : + _theResult___fst_sfd__h437464) ; + assign _theResult___fst_sfd__h472605 = ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == @@ -28271,1308 +28271,1308 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == 52'd0) ? 23'd0 : - _theResult___fst_sfd__h472598 ; - assign _theResult___fst_sfd__h486457 = + _theResult___fst_sfd__h472599 ; + assign _theResult___fst_sfd__h486458 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ; - assign _theResult___fst_sfd__h502285 = + assign _theResult___fst_sfd__h502286 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 : + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ; - assign _theResult___fst_sfd__h502288 = - (_theResult___fst_exp__h501529 == 11'd2047) ? - _theResult___snd__h501480[56:5] : - _theResult___fst_sfd__h502285 ; - assign _theResult___fst_sfd__h511936 = + assign _theResult___fst_sfd__h502289 = + (_theResult___fst_exp__h501530 == 11'd2047) ? + _theResult___snd__h501481[56:5] : + _theResult___fst_sfd__h502286 ; + assign _theResult___fst_sfd__h511937 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 : + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ; - assign _theResult___fst_sfd__h511939 = - (_theResult___fst_exp__h511106 == 11'd2047) ? - sfdin__h511100[56:5] : - _theResult___fst_sfd__h511936 ; - assign _theResult___fst_sfd__h520720 = + assign _theResult___fst_sfd__h511940 = + (_theResult___fst_exp__h511107 == 11'd2047) ? + sfdin__h511101[56:5] : + _theResult___fst_sfd__h511937 ; + assign _theResult___fst_sfd__h520721 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 : + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ; - assign _theResult___fst_sfd__h520723 = - (_theResult___fst_exp__h519939 == 11'd2047) ? - _theResult___snd__h519885[56:5] : - _theResult___fst_sfd__h520720 ; - assign _theResult___fst_sfd__h520732 = - (f1_exp__h482141 == 8'd0) ? + assign _theResult___fst_sfd__h520724 = + (_theResult___fst_exp__h519940 == 11'd2047) ? + _theResult___snd__h519886[56:5] : + _theResult___fst_sfd__h520721 ; + assign _theResult___fst_sfd__h520733 = + (f1_exp__h482142 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ? - _theResult___snd_fst_sfd__h502291 : - _theResult___fst_sfd__h486457) : + _theResult___snd_fst_sfd__h502292 : + _theResult___fst_sfd__h486458) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ? - _theResult___snd_fst_sfd__h520726 : - _theResult___fst_sfd__h486457) ; - assign _theResult___fst_sfd__h520738 = - ((f1_exp__h482141 == 8'd255 || f1_exp__h482141 == 8'd0) && - f1_sfd__h482142 == 23'd0) ? + _theResult___snd_fst_sfd__h520727 : + _theResult___fst_sfd__h486458) ; + assign _theResult___fst_sfd__h520739 = + ((f1_exp__h482142 == 8'd255 || f1_exp__h482142 == 8'd0) && + f1_sfd__h482143 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h520732 ; - assign _theResult___fst_sfd__h525310 = + _theResult___fst_sfd__h520733 ; + assign _theResult___fst_sfd__h525311 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ; - assign _theResult___fst_sfd__h541138 = + assign _theResult___fst_sfd__h541139 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 : + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 ; - assign _theResult___fst_sfd__h541141 = - (_theResult___fst_exp__h540382 == 11'd2047) ? - _theResult___snd__h540333[56:5] : - _theResult___fst_sfd__h541138 ; - assign _theResult___fst_sfd__h550789 = + assign _theResult___fst_sfd__h541142 = + (_theResult___fst_exp__h540383 == 11'd2047) ? + _theResult___snd__h540334[56:5] : + _theResult___fst_sfd__h541139 ; + assign _theResult___fst_sfd__h550790 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 : + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ; - assign _theResult___fst_sfd__h550792 = - (_theResult___fst_exp__h549959 == 11'd2047) ? - sfdin__h549953[56:5] : - _theResult___fst_sfd__h550789 ; - assign _theResult___fst_sfd__h559573 = + assign _theResult___fst_sfd__h550793 = + (_theResult___fst_exp__h549960 == 11'd2047) ? + sfdin__h549954[56:5] : + _theResult___fst_sfd__h550790 ; + assign _theResult___fst_sfd__h559574 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 : + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ; - assign _theResult___fst_sfd__h559576 = - (_theResult___fst_exp__h558792 == 11'd2047) ? - _theResult___snd__h558738[56:5] : - _theResult___fst_sfd__h559573 ; - assign _theResult___fst_sfd__h559585 = - (f2_exp__h521135 == 8'd0) ? + assign _theResult___fst_sfd__h559577 = + (_theResult___fst_exp__h558793 == 11'd2047) ? + _theResult___snd__h558739[56:5] : + _theResult___fst_sfd__h559574 ; + assign _theResult___fst_sfd__h559586 = + (f2_exp__h521136 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ? - _theResult___snd_fst_sfd__h541144 : - _theResult___fst_sfd__h525310) : + _theResult___snd_fst_sfd__h541145 : + _theResult___fst_sfd__h525311) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ? - _theResult___snd_fst_sfd__h559579 : - _theResult___fst_sfd__h525310) ; - assign _theResult___fst_sfd__h559591 = - ((f2_exp__h521135 == 8'd255 || f2_exp__h521135 == 8'd0) && - f2_sfd__h521136 == 23'd0) ? + _theResult___snd_fst_sfd__h559580 : + _theResult___fst_sfd__h525311) ; + assign _theResult___fst_sfd__h559592 = + ((f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) && + f2_sfd__h521137 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h559585 ; - assign _theResult___fst_sfd__h564614 = + _theResult___fst_sfd__h559586 ; + assign _theResult___fst_sfd__h564615 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ? 52'd0 : CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ; - assign _theResult___fst_sfd__h580442 = + assign _theResult___fst_sfd__h580443 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 : + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 ; - assign _theResult___fst_sfd__h580445 = - (_theResult___fst_exp__h579686 == 11'd2047) ? - _theResult___snd__h579637[56:5] : - _theResult___fst_sfd__h580442 ; - assign _theResult___fst_sfd__h590093 = + assign _theResult___fst_sfd__h580446 = + (_theResult___fst_exp__h579687 == 11'd2047) ? + _theResult___snd__h579638[56:5] : + _theResult___fst_sfd__h580443 ; + assign _theResult___fst_sfd__h590094 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 : + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 ; - assign _theResult___fst_sfd__h590096 = - (_theResult___fst_exp__h589263 == 11'd2047) ? - sfdin__h589257[56:5] : - _theResult___fst_sfd__h590093 ; - assign _theResult___fst_sfd__h598877 = + assign _theResult___fst_sfd__h590097 = + (_theResult___fst_exp__h589264 == 11'd2047) ? + sfdin__h589258[56:5] : + _theResult___fst_sfd__h590094 ; + assign _theResult___fst_sfd__h598878 = (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 && coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ? - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 : + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 : IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 ; - assign _theResult___fst_sfd__h598880 = - (_theResult___fst_exp__h598096 == 11'd2047) ? - _theResult___snd__h598042[56:5] : - _theResult___fst_sfd__h598877 ; - assign _theResult___fst_sfd__h598889 = - (f3_exp__h560439 == 8'd0) ? + assign _theResult___fst_sfd__h598881 = + (_theResult___fst_exp__h598097 == 11'd2047) ? + _theResult___snd__h598043[56:5] : + _theResult___fst_sfd__h598878 ; + assign _theResult___fst_sfd__h598890 = + (f3_exp__h560440 == 8'd0) ? (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ? - _theResult___snd_fst_sfd__h580448 : - _theResult___fst_sfd__h564614) : + _theResult___snd_fst_sfd__h580449 : + _theResult___fst_sfd__h564615) : (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ? - _theResult___snd_fst_sfd__h598883 : - _theResult___fst_sfd__h564614) ; - assign _theResult___fst_sfd__h598895 = - ((f3_exp__h560439 == 8'd255 || f3_exp__h560439 == 8'd0) && - f3_sfd__h560440 == 23'd0) ? + _theResult___snd_fst_sfd__h598884 : + _theResult___fst_sfd__h564615) ; + assign _theResult___fst_sfd__h598896 = + ((f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) && + f3_sfd__h560441 == 23'd0) ? 52'd0 : - _theResult___fst_sfd__h598889 ; - assign _theResult___sfd__h354714 = - sfd__h354289[24] ? - ((_theResult___fst_exp__h354197 == 8'd254) ? + _theResult___fst_sfd__h598890 ; + assign _theResult___sfd__h354715 = + sfd__h354290[24] ? + ((_theResult___fst_exp__h354198 == 8'd254) ? 23'd0 : - sfd__h354289[23:1]) : - sfd__h354289[22:0] ; - assign _theResult___sfd__h363296 = - sfd__h362871[24] ? - ((_theResult___fst_exp__h362853 == 8'd254) ? + sfd__h354290[23:1]) : + sfd__h354290[22:0] ; + assign _theResult___sfd__h363297 = + sfd__h362872[24] ? + ((_theResult___fst_exp__h362854 == 8'd254) ? 23'd0 : - sfd__h362871[23:1]) : - sfd__h362871[22:0] ; - assign _theResult___sfd__h372480 = - sfd__h372055[24] ? - ((_theResult___fst_exp__h371963 == 8'd254) ? + sfd__h362872[23:1]) : + sfd__h362872[22:0] ; + assign _theResult___sfd__h372481 = + sfd__h372056[24] ? + ((_theResult___fst_exp__h371964 == 8'd254) ? 23'd0 : - sfd__h372055[23:1]) : - sfd__h372055[22:0] ; - assign _theResult___sfd__h381116 = - sfd__h380667[24] ? - ((_theResult___fst_exp__h380648 == 8'd254) ? + sfd__h372056[23:1]) : + sfd__h372056[22:0] ; + assign _theResult___sfd__h381117 = + sfd__h380668[24] ? + ((_theResult___fst_exp__h380649 == 8'd254) ? 23'd0 : - sfd__h380667[23:1]) : - sfd__h380667[22:0] ; - assign _theResult___sfd__h381218 = + sfd__h380668[23:1]) : + sfd__h380668[22:0] ; + assign _theResult___sfd__h381219 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h338431 : - _theResult___fst_sfd__h381212 ; - assign _theResult___sfd__h400411 = - sfd__h399986[24] ? - ((_theResult___fst_exp__h399894 == 8'd254) ? + _theResult___snd_fst_sfd__h338432 : + _theResult___fst_sfd__h381213 ; + assign _theResult___sfd__h400412 = + sfd__h399987[24] ? + ((_theResult___fst_exp__h399895 == 8'd254) ? 23'd0 : - sfd__h399986[23:1]) : - sfd__h399986[22:0] ; - assign _theResult___sfd__h408993 = - sfd__h408568[24] ? - ((_theResult___fst_exp__h408550 == 8'd254) ? + sfd__h399987[23:1]) : + sfd__h399987[22:0] ; + assign _theResult___sfd__h408994 = + sfd__h408569[24] ? + ((_theResult___fst_exp__h408551 == 8'd254) ? 23'd0 : - sfd__h408568[23:1]) : - sfd__h408568[22:0] ; - assign _theResult___sfd__h418177 = - sfd__h417752[24] ? - ((_theResult___fst_exp__h417660 == 8'd254) ? + sfd__h408569[23:1]) : + sfd__h408569[22:0] ; + assign _theResult___sfd__h418178 = + sfd__h417753[24] ? + ((_theResult___fst_exp__h417661 == 8'd254) ? 23'd0 : - sfd__h417752[23:1]) : - sfd__h417752[22:0] ; - assign _theResult___sfd__h426813 = - sfd__h426364[24] ? - ((_theResult___fst_exp__h426345 == 8'd254) ? + sfd__h417753[23:1]) : + sfd__h417753[22:0] ; + assign _theResult___sfd__h426814 = + sfd__h426365[24] ? + ((_theResult___fst_exp__h426346 == 8'd254) ? 23'd0 : - sfd__h426364[23:1]) : - sfd__h426364[22:0] ; - assign _theResult___sfd__h426915 = + sfd__h426365[23:1]) : + sfd__h426365[22:0] ; + assign _theResult___sfd__h426916 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h384133 : - _theResult___fst_sfd__h426909 ; - assign _theResult___sfd__h446106 = - sfd__h445681[24] ? - ((_theResult___fst_exp__h445589 == 8'd254) ? + _theResult___snd_fst_sfd__h384134 : + _theResult___fst_sfd__h426910 ; + assign _theResult___sfd__h446107 = + sfd__h445682[24] ? + ((_theResult___fst_exp__h445590 == 8'd254) ? 23'd0 : - sfd__h445681[23:1]) : - sfd__h445681[22:0] ; - assign _theResult___sfd__h454688 = - sfd__h454263[24] ? - ((_theResult___fst_exp__h454245 == 8'd254) ? + sfd__h445682[23:1]) : + sfd__h445682[22:0] ; + assign _theResult___sfd__h454689 = + sfd__h454264[24] ? + ((_theResult___fst_exp__h454246 == 8'd254) ? 23'd0 : - sfd__h454263[23:1]) : - sfd__h454263[22:0] ; - assign _theResult___sfd__h463872 = - sfd__h463447[24] ? - ((_theResult___fst_exp__h463355 == 8'd254) ? + sfd__h454264[23:1]) : + sfd__h454264[22:0] ; + assign _theResult___sfd__h463873 = + sfd__h463448[24] ? + ((_theResult___fst_exp__h463356 == 8'd254) ? 23'd0 : - sfd__h463447[23:1]) : - sfd__h463447[22:0] ; - assign _theResult___sfd__h472508 = - sfd__h472059[24] ? - ((_theResult___fst_exp__h472040 == 8'd254) ? + sfd__h463448[23:1]) : + sfd__h463448[22:0] ; + assign _theResult___sfd__h472509 = + sfd__h472060[24] ? + ((_theResult___fst_exp__h472041 == 8'd254) ? 23'd0 : - sfd__h472059[23:1]) : - sfd__h472059[22:0] ; - assign _theResult___sfd__h472610 = + sfd__h472060[23:1]) : + sfd__h472060[22:0] ; + assign _theResult___sfd__h472611 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) ? - _theResult___snd_fst_sfd__h429828 : - _theResult___fst_sfd__h472604 ; - assign _theResult___sfd__h502185 = - sfd__h501547[53] ? - ((_theResult___fst_exp__h501529 == 11'd2046) ? + _theResult___snd_fst_sfd__h429829 : + _theResult___fst_sfd__h472605 ; + assign _theResult___sfd__h502186 = + sfd__h501548[53] ? + ((_theResult___fst_exp__h501530 == 11'd2046) ? 52'd0 : - sfd__h501547[52:1]) : - sfd__h501547[51:0] ; - assign _theResult___sfd__h511836 = - sfd__h511198[53] ? - ((_theResult___fst_exp__h511106 == 11'd2046) ? + sfd__h501548[52:1]) : + sfd__h501548[51:0] ; + assign _theResult___sfd__h511837 = + sfd__h511199[53] ? + ((_theResult___fst_exp__h511107 == 11'd2046) ? 52'd0 : - sfd__h511198[52:1]) : - sfd__h511198[51:0] ; - assign _theResult___sfd__h520620 = - sfd__h519958[53] ? - ((_theResult___fst_exp__h519939 == 11'd2046) ? + sfd__h511199[52:1]) : + sfd__h511199[51:0] ; + assign _theResult___sfd__h520621 = + sfd__h519959[53] ? + ((_theResult___fst_exp__h519940 == 11'd2046) ? 52'd0 : - sfd__h519958[52:1]) : - sfd__h519958[51:0] ; - assign _theResult___sfd__h541038 = - sfd__h540400[53] ? - ((_theResult___fst_exp__h540382 == 11'd2046) ? + sfd__h519959[52:1]) : + sfd__h519959[51:0] ; + assign _theResult___sfd__h541039 = + sfd__h540401[53] ? + ((_theResult___fst_exp__h540383 == 11'd2046) ? 52'd0 : - sfd__h540400[52:1]) : - sfd__h540400[51:0] ; - assign _theResult___sfd__h550689 = - sfd__h550051[53] ? - ((_theResult___fst_exp__h549959 == 11'd2046) ? + sfd__h540401[52:1]) : + sfd__h540401[51:0] ; + assign _theResult___sfd__h550690 = + sfd__h550052[53] ? + ((_theResult___fst_exp__h549960 == 11'd2046) ? 52'd0 : - sfd__h550051[52:1]) : - sfd__h550051[51:0] ; - assign _theResult___sfd__h559473 = - sfd__h558811[53] ? - ((_theResult___fst_exp__h558792 == 11'd2046) ? + sfd__h550052[52:1]) : + sfd__h550052[51:0] ; + assign _theResult___sfd__h559474 = + sfd__h558812[53] ? + ((_theResult___fst_exp__h558793 == 11'd2046) ? 52'd0 : - sfd__h558811[52:1]) : - sfd__h558811[51:0] ; - assign _theResult___sfd__h580342 = - sfd__h579704[53] ? - ((_theResult___fst_exp__h579686 == 11'd2046) ? + sfd__h558812[52:1]) : + sfd__h558812[51:0] ; + assign _theResult___sfd__h580343 = + sfd__h579705[53] ? + ((_theResult___fst_exp__h579687 == 11'd2046) ? 52'd0 : - sfd__h579704[52:1]) : - sfd__h579704[51:0] ; - assign _theResult___sfd__h589993 = - sfd__h589355[53] ? - ((_theResult___fst_exp__h589263 == 11'd2046) ? + sfd__h579705[52:1]) : + sfd__h579705[51:0] ; + assign _theResult___sfd__h589994 = + sfd__h589356[53] ? + ((_theResult___fst_exp__h589264 == 11'd2046) ? 52'd0 : - sfd__h589355[52:1]) : - sfd__h589355[51:0] ; - assign _theResult___sfd__h598777 = - sfd__h598115[53] ? - ((_theResult___fst_exp__h598096 == 11'd2046) ? + sfd__h589356[52:1]) : + sfd__h589356[51:0] ; + assign _theResult___sfd__h598778 = + sfd__h598116[53] ? + ((_theResult___fst_exp__h598097 == 11'd2046) ? 52'd0 : - sfd__h598115[52:1]) : - sfd__h598115[51:0] ; - assign _theResult___snd__h354208 = { _theResult____h346086[55:0], 1'd0 } ; - assign _theResult___snd__h354219 = - (!_theResult____h346086[56] && _theResult____h346086[55]) ? - _theResult___snd__h354221 : - _theResult___snd__h354231 ; - assign _theResult___snd__h354221 = { _theResult____h346086[54:0], 2'd0 } ; - assign _theResult___snd__h354231 = - (!_theResult____h346086[56] && !_theResult____h346086[55] && - !_theResult____h346086[54] && - !_theResult____h346086[53] && - !_theResult____h346086[52] && - !_theResult____h346086[51] && - !_theResult____h346086[50] && - !_theResult____h346086[49] && - !_theResult____h346086[48] && - !_theResult____h346086[47] && - !_theResult____h346086[46] && - !_theResult____h346086[45] && - !_theResult____h346086[44] && - !_theResult____h346086[43] && - !_theResult____h346086[42] && - !_theResult____h346086[41] && - !_theResult____h346086[40] && - !_theResult____h346086[39] && - !_theResult____h346086[38] && - !_theResult____h346086[37] && - !_theResult____h346086[36] && - !_theResult____h346086[35] && - !_theResult____h346086[34] && - !_theResult____h346086[33] && - !_theResult____h346086[32] && - !_theResult____h346086[31] && - !_theResult____h346086[30] && - !_theResult____h346086[29] && - !_theResult____h346086[28] && - !_theResult____h346086[27] && - !_theResult____h346086[26] && - !_theResult____h346086[25] && - !_theResult____h346086[24] && - !_theResult____h346086[23] && - !_theResult____h346086[22] && - !_theResult____h346086[21] && - !_theResult____h346086[20] && - !_theResult____h346086[19] && - !_theResult____h346086[18] && - !_theResult____h346086[17] && - !_theResult____h346086[16] && - !_theResult____h346086[15] && - !_theResult____h346086[14] && - !_theResult____h346086[13] && - !_theResult____h346086[12] && - !_theResult____h346086[11] && - !_theResult____h346086[10] && - !_theResult____h346086[9] && - !_theResult____h346086[8] && - !_theResult____h346086[7] && - !_theResult____h346086[6] && - !_theResult____h346086[5] && - !_theResult____h346086[4] && - !_theResult____h346086[3] && - !_theResult____h346086[2] && - !_theResult____h346086[1] && - !_theResult____h346086[0]) ? - _theResult____h346086 : - _theResult___snd__h354237 ; - assign _theResult___snd__h354237 = + sfd__h598116[52:1]) : + sfd__h598116[51:0] ; + assign _theResult___snd__h354209 = { _theResult____h346087[55:0], 1'd0 } ; + assign _theResult___snd__h354220 = + (!_theResult____h346087[56] && _theResult____h346087[55]) ? + _theResult___snd__h354222 : + _theResult___snd__h354232 ; + assign _theResult___snd__h354222 = { _theResult____h346087[54:0], 2'd0 } ; + assign _theResult___snd__h354232 = + (!_theResult____h346087[56] && !_theResult____h346087[55] && + !_theResult____h346087[54] && + !_theResult____h346087[53] && + !_theResult____h346087[52] && + !_theResult____h346087[51] && + !_theResult____h346087[50] && + !_theResult____h346087[49] && + !_theResult____h346087[48] && + !_theResult____h346087[47] && + !_theResult____h346087[46] && + !_theResult____h346087[45] && + !_theResult____h346087[44] && + !_theResult____h346087[43] && + !_theResult____h346087[42] && + !_theResult____h346087[41] && + !_theResult____h346087[40] && + !_theResult____h346087[39] && + !_theResult____h346087[38] && + !_theResult____h346087[37] && + !_theResult____h346087[36] && + !_theResult____h346087[35] && + !_theResult____h346087[34] && + !_theResult____h346087[33] && + !_theResult____h346087[32] && + !_theResult____h346087[31] && + !_theResult____h346087[30] && + !_theResult____h346087[29] && + !_theResult____h346087[28] && + !_theResult____h346087[27] && + !_theResult____h346087[26] && + !_theResult____h346087[25] && + !_theResult____h346087[24] && + !_theResult____h346087[23] && + !_theResult____h346087[22] && + !_theResult____h346087[21] && + !_theResult____h346087[20] && + !_theResult____h346087[19] && + !_theResult____h346087[18] && + !_theResult____h346087[17] && + !_theResult____h346087[16] && + !_theResult____h346087[15] && + !_theResult____h346087[14] && + !_theResult____h346087[13] && + !_theResult____h346087[12] && + !_theResult____h346087[11] && + !_theResult____h346087[10] && + !_theResult____h346087[9] && + !_theResult____h346087[8] && + !_theResult____h346087[7] && + !_theResult____h346087[6] && + !_theResult____h346087[5] && + !_theResult____h346087[4] && + !_theResult____h346087[3] && + !_theResult____h346087[2] && + !_theResult____h346087[1] && + !_theResult____h346087[0]) ? + _theResult____h346087 : + _theResult___snd__h354238 ; + assign _theResult___snd__h354238 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0], 2'd0 } ; - assign _theResult___snd__h354260 = - _theResult____h346086 << + assign _theResult___snd__h354261 = + _theResult____h346087 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 ; - assign _theResult___snd__h362804 = + assign _theResult___snd__h362805 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h362813 : - _theResult___snd__h362806 ; - assign _theResult___snd__h362806 = + _theResult___snd__h362814 : + _theResult___snd__h362807 ; + assign _theResult___snd__h362807 = { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h362813 = + assign _theResult___snd__h362814 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338481 : - _theResult___snd__h362819 ; - assign _theResult___snd__h362819 = + sfd__h338482 : + _theResult___snd__h362820 ; + assign _theResult___snd__h362820 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0], 2'd0 } ; - assign _theResult___snd__h362842 = - sfd__h338481 << + assign _theResult___snd__h362843 = + sfd__h338482 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 ; - assign _theResult___snd__h371974 = { _theResult____h363725[55:0], 1'd0 } ; - assign _theResult___snd__h371985 = - (!_theResult____h363725[56] && _theResult____h363725[55]) ? - _theResult___snd__h371987 : - _theResult___snd__h371997 ; - assign _theResult___snd__h371987 = { _theResult____h363725[54:0], 2'd0 } ; - assign _theResult___snd__h371997 = - (!_theResult____h363725[56] && !_theResult____h363725[55] && - !_theResult____h363725[54] && - !_theResult____h363725[53] && - !_theResult____h363725[52] && - !_theResult____h363725[51] && - !_theResult____h363725[50] && - !_theResult____h363725[49] && - !_theResult____h363725[48] && - !_theResult____h363725[47] && - !_theResult____h363725[46] && - !_theResult____h363725[45] && - !_theResult____h363725[44] && - !_theResult____h363725[43] && - !_theResult____h363725[42] && - !_theResult____h363725[41] && - !_theResult____h363725[40] && - !_theResult____h363725[39] && - !_theResult____h363725[38] && - !_theResult____h363725[37] && - !_theResult____h363725[36] && - !_theResult____h363725[35] && - !_theResult____h363725[34] && - !_theResult____h363725[33] && - !_theResult____h363725[32] && - !_theResult____h363725[31] && - !_theResult____h363725[30] && - !_theResult____h363725[29] && - !_theResult____h363725[28] && - !_theResult____h363725[27] && - !_theResult____h363725[26] && - !_theResult____h363725[25] && - !_theResult____h363725[24] && - !_theResult____h363725[23] && - !_theResult____h363725[22] && - !_theResult____h363725[21] && - !_theResult____h363725[20] && - !_theResult____h363725[19] && - !_theResult____h363725[18] && - !_theResult____h363725[17] && - !_theResult____h363725[16] && - !_theResult____h363725[15] && - !_theResult____h363725[14] && - !_theResult____h363725[13] && - !_theResult____h363725[12] && - !_theResult____h363725[11] && - !_theResult____h363725[10] && - !_theResult____h363725[9] && - !_theResult____h363725[8] && - !_theResult____h363725[7] && - !_theResult____h363725[6] && - !_theResult____h363725[5] && - !_theResult____h363725[4] && - !_theResult____h363725[3] && - !_theResult____h363725[2] && - !_theResult____h363725[1] && - !_theResult____h363725[0]) ? - _theResult____h363725 : - _theResult___snd__h372003 ; - assign _theResult___snd__h372003 = + assign _theResult___snd__h371975 = { _theResult____h363726[55:0], 1'd0 } ; + assign _theResult___snd__h371986 = + (!_theResult____h363726[56] && _theResult____h363726[55]) ? + _theResult___snd__h371988 : + _theResult___snd__h371998 ; + assign _theResult___snd__h371988 = { _theResult____h363726[54:0], 2'd0 } ; + assign _theResult___snd__h371998 = + (!_theResult____h363726[56] && !_theResult____h363726[55] && + !_theResult____h363726[54] && + !_theResult____h363726[53] && + !_theResult____h363726[52] && + !_theResult____h363726[51] && + !_theResult____h363726[50] && + !_theResult____h363726[49] && + !_theResult____h363726[48] && + !_theResult____h363726[47] && + !_theResult____h363726[46] && + !_theResult____h363726[45] && + !_theResult____h363726[44] && + !_theResult____h363726[43] && + !_theResult____h363726[42] && + !_theResult____h363726[41] && + !_theResult____h363726[40] && + !_theResult____h363726[39] && + !_theResult____h363726[38] && + !_theResult____h363726[37] && + !_theResult____h363726[36] && + !_theResult____h363726[35] && + !_theResult____h363726[34] && + !_theResult____h363726[33] && + !_theResult____h363726[32] && + !_theResult____h363726[31] && + !_theResult____h363726[30] && + !_theResult____h363726[29] && + !_theResult____h363726[28] && + !_theResult____h363726[27] && + !_theResult____h363726[26] && + !_theResult____h363726[25] && + !_theResult____h363726[24] && + !_theResult____h363726[23] && + !_theResult____h363726[22] && + !_theResult____h363726[21] && + !_theResult____h363726[20] && + !_theResult____h363726[19] && + !_theResult____h363726[18] && + !_theResult____h363726[17] && + !_theResult____h363726[16] && + !_theResult____h363726[15] && + !_theResult____h363726[14] && + !_theResult____h363726[13] && + !_theResult____h363726[12] && + !_theResult____h363726[11] && + !_theResult____h363726[10] && + !_theResult____h363726[9] && + !_theResult____h363726[8] && + !_theResult____h363726[7] && + !_theResult____h363726[6] && + !_theResult____h363726[5] && + !_theResult____h363726[4] && + !_theResult____h363726[3] && + !_theResult____h363726[2] && + !_theResult____h363726[1] && + !_theResult____h363726[0]) ? + _theResult____h363726 : + _theResult___snd__h372004 ; + assign _theResult___snd__h372004 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0], 2'd0 } ; - assign _theResult___snd__h372026 = - _theResult____h363725 << + assign _theResult___snd__h372027 = + _theResult____h363726 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 ; - assign _theResult___snd__h380594 = + assign _theResult___snd__h380595 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0) ? - _theResult___snd__h380608 : - _theResult___snd__h362806 ; - assign _theResult___snd__h380608 = + _theResult___snd__h380609 : + _theResult___snd__h362807 ; + assign _theResult___snd__h380609 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ? - sfd__h338481 : - _theResult___snd__h380614 ; - assign _theResult___snd__h380614 = + sfd__h338482 : + _theResult___snd__h380615 ; + assign _theResult___snd__h380615 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0], 2'd0 } ; - assign _theResult___snd__h380632 = - sfd__h338481 << + assign _theResult___snd__h380633 = + sfd__h338482 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872) ; - assign _theResult___snd__h399905 = { _theResult____h391785[55:0], 1'd0 } ; - assign _theResult___snd__h399916 = - (!_theResult____h391785[56] && _theResult____h391785[55]) ? - _theResult___snd__h399918 : - _theResult___snd__h399928 ; - assign _theResult___snd__h399918 = { _theResult____h391785[54:0], 2'd0 } ; - assign _theResult___snd__h399928 = - (!_theResult____h391785[56] && !_theResult____h391785[55] && - !_theResult____h391785[54] && - !_theResult____h391785[53] && - !_theResult____h391785[52] && - !_theResult____h391785[51] && - !_theResult____h391785[50] && - !_theResult____h391785[49] && - !_theResult____h391785[48] && - !_theResult____h391785[47] && - !_theResult____h391785[46] && - !_theResult____h391785[45] && - !_theResult____h391785[44] && - !_theResult____h391785[43] && - !_theResult____h391785[42] && - !_theResult____h391785[41] && - !_theResult____h391785[40] && - !_theResult____h391785[39] && - !_theResult____h391785[38] && - !_theResult____h391785[37] && - !_theResult____h391785[36] && - !_theResult____h391785[35] && - !_theResult____h391785[34] && - !_theResult____h391785[33] && - !_theResult____h391785[32] && - !_theResult____h391785[31] && - !_theResult____h391785[30] && - !_theResult____h391785[29] && - !_theResult____h391785[28] && - !_theResult____h391785[27] && - !_theResult____h391785[26] && - !_theResult____h391785[25] && - !_theResult____h391785[24] && - !_theResult____h391785[23] && - !_theResult____h391785[22] && - !_theResult____h391785[21] && - !_theResult____h391785[20] && - !_theResult____h391785[19] && - !_theResult____h391785[18] && - !_theResult____h391785[17] && - !_theResult____h391785[16] && - !_theResult____h391785[15] && - !_theResult____h391785[14] && - !_theResult____h391785[13] && - !_theResult____h391785[12] && - !_theResult____h391785[11] && - !_theResult____h391785[10] && - !_theResult____h391785[9] && - !_theResult____h391785[8] && - !_theResult____h391785[7] && - !_theResult____h391785[6] && - !_theResult____h391785[5] && - !_theResult____h391785[4] && - !_theResult____h391785[3] && - !_theResult____h391785[2] && - !_theResult____h391785[1] && - !_theResult____h391785[0]) ? - _theResult____h391785 : - _theResult___snd__h399934 ; - assign _theResult___snd__h399934 = + assign _theResult___snd__h399906 = { _theResult____h391786[55:0], 1'd0 } ; + assign _theResult___snd__h399917 = + (!_theResult____h391786[56] && _theResult____h391786[55]) ? + _theResult___snd__h399919 : + _theResult___snd__h399929 ; + assign _theResult___snd__h399919 = { _theResult____h391786[54:0], 2'd0 } ; + assign _theResult___snd__h399929 = + (!_theResult____h391786[56] && !_theResult____h391786[55] && + !_theResult____h391786[54] && + !_theResult____h391786[53] && + !_theResult____h391786[52] && + !_theResult____h391786[51] && + !_theResult____h391786[50] && + !_theResult____h391786[49] && + !_theResult____h391786[48] && + !_theResult____h391786[47] && + !_theResult____h391786[46] && + !_theResult____h391786[45] && + !_theResult____h391786[44] && + !_theResult____h391786[43] && + !_theResult____h391786[42] && + !_theResult____h391786[41] && + !_theResult____h391786[40] && + !_theResult____h391786[39] && + !_theResult____h391786[38] && + !_theResult____h391786[37] && + !_theResult____h391786[36] && + !_theResult____h391786[35] && + !_theResult____h391786[34] && + !_theResult____h391786[33] && + !_theResult____h391786[32] && + !_theResult____h391786[31] && + !_theResult____h391786[30] && + !_theResult____h391786[29] && + !_theResult____h391786[28] && + !_theResult____h391786[27] && + !_theResult____h391786[26] && + !_theResult____h391786[25] && + !_theResult____h391786[24] && + !_theResult____h391786[23] && + !_theResult____h391786[22] && + !_theResult____h391786[21] && + !_theResult____h391786[20] && + !_theResult____h391786[19] && + !_theResult____h391786[18] && + !_theResult____h391786[17] && + !_theResult____h391786[16] && + !_theResult____h391786[15] && + !_theResult____h391786[14] && + !_theResult____h391786[13] && + !_theResult____h391786[12] && + !_theResult____h391786[11] && + !_theResult____h391786[10] && + !_theResult____h391786[9] && + !_theResult____h391786[8] && + !_theResult____h391786[7] && + !_theResult____h391786[6] && + !_theResult____h391786[5] && + !_theResult____h391786[4] && + !_theResult____h391786[3] && + !_theResult____h391786[2] && + !_theResult____h391786[1] && + !_theResult____h391786[0]) ? + _theResult____h391786 : + _theResult___snd__h399935 ; + assign _theResult___snd__h399935 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0], 2'd0 } ; - assign _theResult___snd__h399957 = - _theResult____h391785 << + assign _theResult___snd__h399958 = + _theResult____h391786 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 ; - assign _theResult___snd__h408501 = + assign _theResult___snd__h408502 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h408510 : - _theResult___snd__h408503 ; - assign _theResult___snd__h408503 = + _theResult___snd__h408511 : + _theResult___snd__h408504 ; + assign _theResult___snd__h408504 = { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h408510 = + assign _theResult___snd__h408511 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384183 : - _theResult___snd__h408516 ; - assign _theResult___snd__h408516 = + sfd__h384184 : + _theResult___snd__h408517 ; + assign _theResult___snd__h408517 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0], 2'd0 } ; - assign _theResult___snd__h408539 = - sfd__h384183 << + assign _theResult___snd__h408540 = + sfd__h384184 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 ; - assign _theResult___snd__h417671 = { _theResult____h409422[55:0], 1'd0 } ; - assign _theResult___snd__h417682 = - (!_theResult____h409422[56] && _theResult____h409422[55]) ? - _theResult___snd__h417684 : - _theResult___snd__h417694 ; - assign _theResult___snd__h417684 = { _theResult____h409422[54:0], 2'd0 } ; - assign _theResult___snd__h417694 = - (!_theResult____h409422[56] && !_theResult____h409422[55] && - !_theResult____h409422[54] && - !_theResult____h409422[53] && - !_theResult____h409422[52] && - !_theResult____h409422[51] && - !_theResult____h409422[50] && - !_theResult____h409422[49] && - !_theResult____h409422[48] && - !_theResult____h409422[47] && - !_theResult____h409422[46] && - !_theResult____h409422[45] && - !_theResult____h409422[44] && - !_theResult____h409422[43] && - !_theResult____h409422[42] && - !_theResult____h409422[41] && - !_theResult____h409422[40] && - !_theResult____h409422[39] && - !_theResult____h409422[38] && - !_theResult____h409422[37] && - !_theResult____h409422[36] && - !_theResult____h409422[35] && - !_theResult____h409422[34] && - !_theResult____h409422[33] && - !_theResult____h409422[32] && - !_theResult____h409422[31] && - !_theResult____h409422[30] && - !_theResult____h409422[29] && - !_theResult____h409422[28] && - !_theResult____h409422[27] && - !_theResult____h409422[26] && - !_theResult____h409422[25] && - !_theResult____h409422[24] && - !_theResult____h409422[23] && - !_theResult____h409422[22] && - !_theResult____h409422[21] && - !_theResult____h409422[20] && - !_theResult____h409422[19] && - !_theResult____h409422[18] && - !_theResult____h409422[17] && - !_theResult____h409422[16] && - !_theResult____h409422[15] && - !_theResult____h409422[14] && - !_theResult____h409422[13] && - !_theResult____h409422[12] && - !_theResult____h409422[11] && - !_theResult____h409422[10] && - !_theResult____h409422[9] && - !_theResult____h409422[8] && - !_theResult____h409422[7] && - !_theResult____h409422[6] && - !_theResult____h409422[5] && - !_theResult____h409422[4] && - !_theResult____h409422[3] && - !_theResult____h409422[2] && - !_theResult____h409422[1] && - !_theResult____h409422[0]) ? - _theResult____h409422 : - _theResult___snd__h417700 ; - assign _theResult___snd__h417700 = + assign _theResult___snd__h417672 = { _theResult____h409423[55:0], 1'd0 } ; + assign _theResult___snd__h417683 = + (!_theResult____h409423[56] && _theResult____h409423[55]) ? + _theResult___snd__h417685 : + _theResult___snd__h417695 ; + assign _theResult___snd__h417685 = { _theResult____h409423[54:0], 2'd0 } ; + assign _theResult___snd__h417695 = + (!_theResult____h409423[56] && !_theResult____h409423[55] && + !_theResult____h409423[54] && + !_theResult____h409423[53] && + !_theResult____h409423[52] && + !_theResult____h409423[51] && + !_theResult____h409423[50] && + !_theResult____h409423[49] && + !_theResult____h409423[48] && + !_theResult____h409423[47] && + !_theResult____h409423[46] && + !_theResult____h409423[45] && + !_theResult____h409423[44] && + !_theResult____h409423[43] && + !_theResult____h409423[42] && + !_theResult____h409423[41] && + !_theResult____h409423[40] && + !_theResult____h409423[39] && + !_theResult____h409423[38] && + !_theResult____h409423[37] && + !_theResult____h409423[36] && + !_theResult____h409423[35] && + !_theResult____h409423[34] && + !_theResult____h409423[33] && + !_theResult____h409423[32] && + !_theResult____h409423[31] && + !_theResult____h409423[30] && + !_theResult____h409423[29] && + !_theResult____h409423[28] && + !_theResult____h409423[27] && + !_theResult____h409423[26] && + !_theResult____h409423[25] && + !_theResult____h409423[24] && + !_theResult____h409423[23] && + !_theResult____h409423[22] && + !_theResult____h409423[21] && + !_theResult____h409423[20] && + !_theResult____h409423[19] && + !_theResult____h409423[18] && + !_theResult____h409423[17] && + !_theResult____h409423[16] && + !_theResult____h409423[15] && + !_theResult____h409423[14] && + !_theResult____h409423[13] && + !_theResult____h409423[12] && + !_theResult____h409423[11] && + !_theResult____h409423[10] && + !_theResult____h409423[9] && + !_theResult____h409423[8] && + !_theResult____h409423[7] && + !_theResult____h409423[6] && + !_theResult____h409423[5] && + !_theResult____h409423[4] && + !_theResult____h409423[3] && + !_theResult____h409423[2] && + !_theResult____h409423[1] && + !_theResult____h409423[0]) ? + _theResult____h409423 : + _theResult___snd__h417701 ; + assign _theResult___snd__h417701 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0], 2'd0 } ; - assign _theResult___snd__h417723 = - _theResult____h409422 << + assign _theResult___snd__h417724 = + _theResult____h409423 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 ; - assign _theResult___snd__h426291 = + assign _theResult___snd__h426292 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0) ? - _theResult___snd__h426305 : - _theResult___snd__h408503 ; - assign _theResult___snd__h426305 = + _theResult___snd__h426306 : + _theResult___snd__h408504 ; + assign _theResult___snd__h426306 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ? - sfd__h384183 : - _theResult___snd__h426311 ; - assign _theResult___snd__h426311 = + sfd__h384184 : + _theResult___snd__h426312 ; + assign _theResult___snd__h426312 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0], 2'd0 } ; - assign _theResult___snd__h426329 = - sfd__h384183 << + assign _theResult___snd__h426330 = + sfd__h384184 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264) ; - assign _theResult___snd__h445600 = { _theResult____h437480[55:0], 1'd0 } ; - assign _theResult___snd__h445611 = - (!_theResult____h437480[56] && _theResult____h437480[55]) ? - _theResult___snd__h445613 : - _theResult___snd__h445623 ; - assign _theResult___snd__h445613 = { _theResult____h437480[54:0], 2'd0 } ; - assign _theResult___snd__h445623 = - (!_theResult____h437480[56] && !_theResult____h437480[55] && - !_theResult____h437480[54] && - !_theResult____h437480[53] && - !_theResult____h437480[52] && - !_theResult____h437480[51] && - !_theResult____h437480[50] && - !_theResult____h437480[49] && - !_theResult____h437480[48] && - !_theResult____h437480[47] && - !_theResult____h437480[46] && - !_theResult____h437480[45] && - !_theResult____h437480[44] && - !_theResult____h437480[43] && - !_theResult____h437480[42] && - !_theResult____h437480[41] && - !_theResult____h437480[40] && - !_theResult____h437480[39] && - !_theResult____h437480[38] && - !_theResult____h437480[37] && - !_theResult____h437480[36] && - !_theResult____h437480[35] && - !_theResult____h437480[34] && - !_theResult____h437480[33] && - !_theResult____h437480[32] && - !_theResult____h437480[31] && - !_theResult____h437480[30] && - !_theResult____h437480[29] && - !_theResult____h437480[28] && - !_theResult____h437480[27] && - !_theResult____h437480[26] && - !_theResult____h437480[25] && - !_theResult____h437480[24] && - !_theResult____h437480[23] && - !_theResult____h437480[22] && - !_theResult____h437480[21] && - !_theResult____h437480[20] && - !_theResult____h437480[19] && - !_theResult____h437480[18] && - !_theResult____h437480[17] && - !_theResult____h437480[16] && - !_theResult____h437480[15] && - !_theResult____h437480[14] && - !_theResult____h437480[13] && - !_theResult____h437480[12] && - !_theResult____h437480[11] && - !_theResult____h437480[10] && - !_theResult____h437480[9] && - !_theResult____h437480[8] && - !_theResult____h437480[7] && - !_theResult____h437480[6] && - !_theResult____h437480[5] && - !_theResult____h437480[4] && - !_theResult____h437480[3] && - !_theResult____h437480[2] && - !_theResult____h437480[1] && - !_theResult____h437480[0]) ? - _theResult____h437480 : - _theResult___snd__h445629 ; - assign _theResult___snd__h445629 = + assign _theResult___snd__h445601 = { _theResult____h437481[55:0], 1'd0 } ; + assign _theResult___snd__h445612 = + (!_theResult____h437481[56] && _theResult____h437481[55]) ? + _theResult___snd__h445614 : + _theResult___snd__h445624 ; + assign _theResult___snd__h445614 = { _theResult____h437481[54:0], 2'd0 } ; + assign _theResult___snd__h445624 = + (!_theResult____h437481[56] && !_theResult____h437481[55] && + !_theResult____h437481[54] && + !_theResult____h437481[53] && + !_theResult____h437481[52] && + !_theResult____h437481[51] && + !_theResult____h437481[50] && + !_theResult____h437481[49] && + !_theResult____h437481[48] && + !_theResult____h437481[47] && + !_theResult____h437481[46] && + !_theResult____h437481[45] && + !_theResult____h437481[44] && + !_theResult____h437481[43] && + !_theResult____h437481[42] && + !_theResult____h437481[41] && + !_theResult____h437481[40] && + !_theResult____h437481[39] && + !_theResult____h437481[38] && + !_theResult____h437481[37] && + !_theResult____h437481[36] && + !_theResult____h437481[35] && + !_theResult____h437481[34] && + !_theResult____h437481[33] && + !_theResult____h437481[32] && + !_theResult____h437481[31] && + !_theResult____h437481[30] && + !_theResult____h437481[29] && + !_theResult____h437481[28] && + !_theResult____h437481[27] && + !_theResult____h437481[26] && + !_theResult____h437481[25] && + !_theResult____h437481[24] && + !_theResult____h437481[23] && + !_theResult____h437481[22] && + !_theResult____h437481[21] && + !_theResult____h437481[20] && + !_theResult____h437481[19] && + !_theResult____h437481[18] && + !_theResult____h437481[17] && + !_theResult____h437481[16] && + !_theResult____h437481[15] && + !_theResult____h437481[14] && + !_theResult____h437481[13] && + !_theResult____h437481[12] && + !_theResult____h437481[11] && + !_theResult____h437481[10] && + !_theResult____h437481[9] && + !_theResult____h437481[8] && + !_theResult____h437481[7] && + !_theResult____h437481[6] && + !_theResult____h437481[5] && + !_theResult____h437481[4] && + !_theResult____h437481[3] && + !_theResult____h437481[2] && + !_theResult____h437481[1] && + !_theResult____h437481[0]) ? + _theResult____h437481 : + _theResult___snd__h445630 ; + assign _theResult___snd__h445630 = { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0], 2'd0 } ; - assign _theResult___snd__h445652 = - _theResult____h437480 << + assign _theResult___snd__h445653 = + _theResult____h437481 << IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 ; - assign _theResult___snd__h454196 = + assign _theResult___snd__h454197 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h454205 : - _theResult___snd__h454198 ; - assign _theResult___snd__h454198 = + _theResult___snd__h454206 : + _theResult___snd__h454199 ; + assign _theResult___snd__h454199 = { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5], 5'd0 } ; - assign _theResult___snd__h454205 = + assign _theResult___snd__h454206 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429878 : - _theResult___snd__h454211 ; - assign _theResult___snd__h454211 = + sfd__h429879 : + _theResult___snd__h454212 ; + assign _theResult___snd__h454212 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0], 2'd0 } ; - assign _theResult___snd__h454234 = - sfd__h429878 << + assign _theResult___snd__h454235 = + sfd__h429879 << IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 ; - assign _theResult___snd__h463366 = { _theResult____h455117[55:0], 1'd0 } ; - assign _theResult___snd__h463377 = - (!_theResult____h455117[56] && _theResult____h455117[55]) ? - _theResult___snd__h463379 : - _theResult___snd__h463389 ; - assign _theResult___snd__h463379 = { _theResult____h455117[54:0], 2'd0 } ; - assign _theResult___snd__h463389 = - (!_theResult____h455117[56] && !_theResult____h455117[55] && - !_theResult____h455117[54] && - !_theResult____h455117[53] && - !_theResult____h455117[52] && - !_theResult____h455117[51] && - !_theResult____h455117[50] && - !_theResult____h455117[49] && - !_theResult____h455117[48] && - !_theResult____h455117[47] && - !_theResult____h455117[46] && - !_theResult____h455117[45] && - !_theResult____h455117[44] && - !_theResult____h455117[43] && - !_theResult____h455117[42] && - !_theResult____h455117[41] && - !_theResult____h455117[40] && - !_theResult____h455117[39] && - !_theResult____h455117[38] && - !_theResult____h455117[37] && - !_theResult____h455117[36] && - !_theResult____h455117[35] && - !_theResult____h455117[34] && - !_theResult____h455117[33] && - !_theResult____h455117[32] && - !_theResult____h455117[31] && - !_theResult____h455117[30] && - !_theResult____h455117[29] && - !_theResult____h455117[28] && - !_theResult____h455117[27] && - !_theResult____h455117[26] && - !_theResult____h455117[25] && - !_theResult____h455117[24] && - !_theResult____h455117[23] && - !_theResult____h455117[22] && - !_theResult____h455117[21] && - !_theResult____h455117[20] && - !_theResult____h455117[19] && - !_theResult____h455117[18] && - !_theResult____h455117[17] && - !_theResult____h455117[16] && - !_theResult____h455117[15] && - !_theResult____h455117[14] && - !_theResult____h455117[13] && - !_theResult____h455117[12] && - !_theResult____h455117[11] && - !_theResult____h455117[10] && - !_theResult____h455117[9] && - !_theResult____h455117[8] && - !_theResult____h455117[7] && - !_theResult____h455117[6] && - !_theResult____h455117[5] && - !_theResult____h455117[4] && - !_theResult____h455117[3] && - !_theResult____h455117[2] && - !_theResult____h455117[1] && - !_theResult____h455117[0]) ? - _theResult____h455117 : - _theResult___snd__h463395 ; - assign _theResult___snd__h463395 = + assign _theResult___snd__h463367 = { _theResult____h455118[55:0], 1'd0 } ; + assign _theResult___snd__h463378 = + (!_theResult____h455118[56] && _theResult____h455118[55]) ? + _theResult___snd__h463380 : + _theResult___snd__h463390 ; + assign _theResult___snd__h463380 = { _theResult____h455118[54:0], 2'd0 } ; + assign _theResult___snd__h463390 = + (!_theResult____h455118[56] && !_theResult____h455118[55] && + !_theResult____h455118[54] && + !_theResult____h455118[53] && + !_theResult____h455118[52] && + !_theResult____h455118[51] && + !_theResult____h455118[50] && + !_theResult____h455118[49] && + !_theResult____h455118[48] && + !_theResult____h455118[47] && + !_theResult____h455118[46] && + !_theResult____h455118[45] && + !_theResult____h455118[44] && + !_theResult____h455118[43] && + !_theResult____h455118[42] && + !_theResult____h455118[41] && + !_theResult____h455118[40] && + !_theResult____h455118[39] && + !_theResult____h455118[38] && + !_theResult____h455118[37] && + !_theResult____h455118[36] && + !_theResult____h455118[35] && + !_theResult____h455118[34] && + !_theResult____h455118[33] && + !_theResult____h455118[32] && + !_theResult____h455118[31] && + !_theResult____h455118[30] && + !_theResult____h455118[29] && + !_theResult____h455118[28] && + !_theResult____h455118[27] && + !_theResult____h455118[26] && + !_theResult____h455118[25] && + !_theResult____h455118[24] && + !_theResult____h455118[23] && + !_theResult____h455118[22] && + !_theResult____h455118[21] && + !_theResult____h455118[20] && + !_theResult____h455118[19] && + !_theResult____h455118[18] && + !_theResult____h455118[17] && + !_theResult____h455118[16] && + !_theResult____h455118[15] && + !_theResult____h455118[14] && + !_theResult____h455118[13] && + !_theResult____h455118[12] && + !_theResult____h455118[11] && + !_theResult____h455118[10] && + !_theResult____h455118[9] && + !_theResult____h455118[8] && + !_theResult____h455118[7] && + !_theResult____h455118[6] && + !_theResult____h455118[5] && + !_theResult____h455118[4] && + !_theResult____h455118[3] && + !_theResult____h455118[2] && + !_theResult____h455118[1] && + !_theResult____h455118[0]) ? + _theResult____h455118 : + _theResult___snd__h463396 ; + assign _theResult___snd__h463396 = { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0], 2'd0 } ; - assign _theResult___snd__h463418 = - _theResult____h455117 << + assign _theResult___snd__h463419 = + _theResult____h455118 << IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 ; - assign _theResult___snd__h471986 = + assign _theResult___snd__h471987 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0) ? - _theResult___snd__h472000 : - _theResult___snd__h454198 ; - assign _theResult___snd__h472000 = + _theResult___snd__h472001 : + _theResult___snd__h454199 ; + assign _theResult___snd__h472001 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd0 && NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ? - sfd__h429878 : - _theResult___snd__h472006 ; - assign _theResult___snd__h472006 = + sfd__h429879 : + _theResult___snd__h472007 ; + assign _theResult___snd__h472007 = { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0], 2'd0 } ; - assign _theResult___snd__h472024 = - sfd__h429878 << + assign _theResult___snd__h472025 = + sfd__h429879 << (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656[8] ? 9'h0AA : IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656) ; - assign _theResult___snd__h501480 = - (f1_exp__h482141 == 8'd0) ? - _theResult___snd__h501489 : - _theResult___snd__h501482 ; - assign _theResult___snd__h501482 = { f1_sfd__h482142, 34'd0 } ; - assign _theResult___snd__h501489 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___snd__h501481 = + (f1_exp__h482142 == 8'd0) ? + _theResult___snd__h501490 : + _theResult___snd__h501483 ; + assign _theResult___snd__h501483 = { f1_sfd__h482143, 34'd0 } ; + assign _theResult___snd__h501490 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482503 : - _theResult___snd__h501495 ; - assign _theResult___snd__h501495 = + sfd__h482504 : + _theResult___snd__h501496 ; + assign _theResult___snd__h501496 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0], 2'd0 } ; - assign _theResult___snd__h501518 = - sfd__h482503 << + assign _theResult___snd__h501519 = + sfd__h482504 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 ; - assign _theResult___snd__h511117 = { _theResult____h502870[55:0], 1'd0 } ; - assign _theResult___snd__h511128 = - (!_theResult____h502870[56] && _theResult____h502870[55]) ? - _theResult___snd__h511130 : - _theResult___snd__h511140 ; - assign _theResult___snd__h511130 = { _theResult____h502870[54:0], 2'd0 } ; - assign _theResult___snd__h511140 = - (!_theResult____h502870[56] && !_theResult____h502870[55] && - !_theResult____h502870[54] && - !_theResult____h502870[53] && - !_theResult____h502870[52] && - !_theResult____h502870[51] && - !_theResult____h502870[50] && - !_theResult____h502870[49] && - !_theResult____h502870[48] && - !_theResult____h502870[47] && - !_theResult____h502870[46] && - !_theResult____h502870[45] && - !_theResult____h502870[44] && - !_theResult____h502870[43] && - !_theResult____h502870[42] && - !_theResult____h502870[41] && - !_theResult____h502870[40] && - !_theResult____h502870[39] && - !_theResult____h502870[38] && - !_theResult____h502870[37] && - !_theResult____h502870[36] && - !_theResult____h502870[35] && - !_theResult____h502870[34] && - !_theResult____h502870[33] && - !_theResult____h502870[32] && - !_theResult____h502870[31] && - !_theResult____h502870[30] && - !_theResult____h502870[29] && - !_theResult____h502870[28] && - !_theResult____h502870[27] && - !_theResult____h502870[26] && - !_theResult____h502870[25] && - !_theResult____h502870[24] && - !_theResult____h502870[23] && - !_theResult____h502870[22] && - !_theResult____h502870[21] && - !_theResult____h502870[20] && - !_theResult____h502870[19] && - !_theResult____h502870[18] && - !_theResult____h502870[17] && - !_theResult____h502870[16] && - !_theResult____h502870[15] && - !_theResult____h502870[14] && - !_theResult____h502870[13] && - !_theResult____h502870[12] && - !_theResult____h502870[11] && - !_theResult____h502870[10] && - !_theResult____h502870[9] && - !_theResult____h502870[8] && - !_theResult____h502870[7] && - !_theResult____h502870[6] && - !_theResult____h502870[5] && - !_theResult____h502870[4] && - !_theResult____h502870[3] && - !_theResult____h502870[2] && - !_theResult____h502870[1] && - !_theResult____h502870[0]) ? - _theResult____h502870 : - _theResult___snd__h511146 ; - assign _theResult___snd__h511146 = + assign _theResult___snd__h511118 = { _theResult____h502871[55:0], 1'd0 } ; + assign _theResult___snd__h511129 = + (!_theResult____h502871[56] && _theResult____h502871[55]) ? + _theResult___snd__h511131 : + _theResult___snd__h511141 ; + assign _theResult___snd__h511131 = { _theResult____h502871[54:0], 2'd0 } ; + assign _theResult___snd__h511141 = + (!_theResult____h502871[56] && !_theResult____h502871[55] && + !_theResult____h502871[54] && + !_theResult____h502871[53] && + !_theResult____h502871[52] && + !_theResult____h502871[51] && + !_theResult____h502871[50] && + !_theResult____h502871[49] && + !_theResult____h502871[48] && + !_theResult____h502871[47] && + !_theResult____h502871[46] && + !_theResult____h502871[45] && + !_theResult____h502871[44] && + !_theResult____h502871[43] && + !_theResult____h502871[42] && + !_theResult____h502871[41] && + !_theResult____h502871[40] && + !_theResult____h502871[39] && + !_theResult____h502871[38] && + !_theResult____h502871[37] && + !_theResult____h502871[36] && + !_theResult____h502871[35] && + !_theResult____h502871[34] && + !_theResult____h502871[33] && + !_theResult____h502871[32] && + !_theResult____h502871[31] && + !_theResult____h502871[30] && + !_theResult____h502871[29] && + !_theResult____h502871[28] && + !_theResult____h502871[27] && + !_theResult____h502871[26] && + !_theResult____h502871[25] && + !_theResult____h502871[24] && + !_theResult____h502871[23] && + !_theResult____h502871[22] && + !_theResult____h502871[21] && + !_theResult____h502871[20] && + !_theResult____h502871[19] && + !_theResult____h502871[18] && + !_theResult____h502871[17] && + !_theResult____h502871[16] && + !_theResult____h502871[15] && + !_theResult____h502871[14] && + !_theResult____h502871[13] && + !_theResult____h502871[12] && + !_theResult____h502871[11] && + !_theResult____h502871[10] && + !_theResult____h502871[9] && + !_theResult____h502871[8] && + !_theResult____h502871[7] && + !_theResult____h502871[6] && + !_theResult____h502871[5] && + !_theResult____h502871[4] && + !_theResult____h502871[3] && + !_theResult____h502871[2] && + !_theResult____h502871[1] && + !_theResult____h502871[0]) ? + _theResult____h502871 : + _theResult___snd__h511147 ; + assign _theResult___snd__h511147 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0], 2'd0 } ; - assign _theResult___snd__h511169 = - _theResult____h502870 << + assign _theResult___snd__h511170 = + _theResult____h502871 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 ; - assign _theResult___snd__h519885 = - (f1_exp__h482141 == 8'd0) ? - _theResult___snd__h519899 : - _theResult___snd__h501482 ; - assign _theResult___snd__h519899 = - (f1_exp__h482141 == 8'd0 && !f1_sfd__h482142[22] && + assign _theResult___snd__h519886 = + (f1_exp__h482142 == 8'd0) ? + _theResult___snd__h519900 : + _theResult___snd__h501483 ; + assign _theResult___snd__h519900 = + (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ? - sfd__h482503 : - _theResult___snd__h519905 ; - assign _theResult___snd__h519905 = + sfd__h482504 : + _theResult___snd__h519906 ; + assign _theResult___snd__h519906 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0], 2'd0 } ; - assign _theResult___snd__h519923 = - sfd__h482503 << + assign _theResult___snd__h519924 = + sfd__h482504 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ; - assign _theResult___snd__h540333 = - (f2_exp__h521135 == 8'd0) ? - _theResult___snd__h540342 : - _theResult___snd__h540335 ; - assign _theResult___snd__h540335 = { f2_sfd__h521136, 34'd0 } ; - assign _theResult___snd__h540342 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___snd__h540334 = + (f2_exp__h521136 == 8'd0) ? + _theResult___snd__h540343 : + _theResult___snd__h540336 ; + assign _theResult___snd__h540336 = { f2_sfd__h521137, 34'd0 } ; + assign _theResult___snd__h540343 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521497 : - _theResult___snd__h540348 ; - assign _theResult___snd__h540348 = + sfd__h521498 : + _theResult___snd__h540349 ; + assign _theResult___snd__h540349 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0], 2'd0 } ; - assign _theResult___snd__h540371 = - sfd__h521497 << + assign _theResult___snd__h540372 = + sfd__h521498 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 ; - assign _theResult___snd__h549970 = { _theResult____h541723[55:0], 1'd0 } ; - assign _theResult___snd__h549981 = - (!_theResult____h541723[56] && _theResult____h541723[55]) ? - _theResult___snd__h549983 : - _theResult___snd__h549993 ; - assign _theResult___snd__h549983 = { _theResult____h541723[54:0], 2'd0 } ; - assign _theResult___snd__h549993 = - (!_theResult____h541723[56] && !_theResult____h541723[55] && - !_theResult____h541723[54] && - !_theResult____h541723[53] && - !_theResult____h541723[52] && - !_theResult____h541723[51] && - !_theResult____h541723[50] && - !_theResult____h541723[49] && - !_theResult____h541723[48] && - !_theResult____h541723[47] && - !_theResult____h541723[46] && - !_theResult____h541723[45] && - !_theResult____h541723[44] && - !_theResult____h541723[43] && - !_theResult____h541723[42] && - !_theResult____h541723[41] && - !_theResult____h541723[40] && - !_theResult____h541723[39] && - !_theResult____h541723[38] && - !_theResult____h541723[37] && - !_theResult____h541723[36] && - !_theResult____h541723[35] && - !_theResult____h541723[34] && - !_theResult____h541723[33] && - !_theResult____h541723[32] && - !_theResult____h541723[31] && - !_theResult____h541723[30] && - !_theResult____h541723[29] && - !_theResult____h541723[28] && - !_theResult____h541723[27] && - !_theResult____h541723[26] && - !_theResult____h541723[25] && - !_theResult____h541723[24] && - !_theResult____h541723[23] && - !_theResult____h541723[22] && - !_theResult____h541723[21] && - !_theResult____h541723[20] && - !_theResult____h541723[19] && - !_theResult____h541723[18] && - !_theResult____h541723[17] && - !_theResult____h541723[16] && - !_theResult____h541723[15] && - !_theResult____h541723[14] && - !_theResult____h541723[13] && - !_theResult____h541723[12] && - !_theResult____h541723[11] && - !_theResult____h541723[10] && - !_theResult____h541723[9] && - !_theResult____h541723[8] && - !_theResult____h541723[7] && - !_theResult____h541723[6] && - !_theResult____h541723[5] && - !_theResult____h541723[4] && - !_theResult____h541723[3] && - !_theResult____h541723[2] && - !_theResult____h541723[1] && - !_theResult____h541723[0]) ? - _theResult____h541723 : - _theResult___snd__h549999 ; - assign _theResult___snd__h549999 = + assign _theResult___snd__h549971 = { _theResult____h541724[55:0], 1'd0 } ; + assign _theResult___snd__h549982 = + (!_theResult____h541724[56] && _theResult____h541724[55]) ? + _theResult___snd__h549984 : + _theResult___snd__h549994 ; + assign _theResult___snd__h549984 = { _theResult____h541724[54:0], 2'd0 } ; + assign _theResult___snd__h549994 = + (!_theResult____h541724[56] && !_theResult____h541724[55] && + !_theResult____h541724[54] && + !_theResult____h541724[53] && + !_theResult____h541724[52] && + !_theResult____h541724[51] && + !_theResult____h541724[50] && + !_theResult____h541724[49] && + !_theResult____h541724[48] && + !_theResult____h541724[47] && + !_theResult____h541724[46] && + !_theResult____h541724[45] && + !_theResult____h541724[44] && + !_theResult____h541724[43] && + !_theResult____h541724[42] && + !_theResult____h541724[41] && + !_theResult____h541724[40] && + !_theResult____h541724[39] && + !_theResult____h541724[38] && + !_theResult____h541724[37] && + !_theResult____h541724[36] && + !_theResult____h541724[35] && + !_theResult____h541724[34] && + !_theResult____h541724[33] && + !_theResult____h541724[32] && + !_theResult____h541724[31] && + !_theResult____h541724[30] && + !_theResult____h541724[29] && + !_theResult____h541724[28] && + !_theResult____h541724[27] && + !_theResult____h541724[26] && + !_theResult____h541724[25] && + !_theResult____h541724[24] && + !_theResult____h541724[23] && + !_theResult____h541724[22] && + !_theResult____h541724[21] && + !_theResult____h541724[20] && + !_theResult____h541724[19] && + !_theResult____h541724[18] && + !_theResult____h541724[17] && + !_theResult____h541724[16] && + !_theResult____h541724[15] && + !_theResult____h541724[14] && + !_theResult____h541724[13] && + !_theResult____h541724[12] && + !_theResult____h541724[11] && + !_theResult____h541724[10] && + !_theResult____h541724[9] && + !_theResult____h541724[8] && + !_theResult____h541724[7] && + !_theResult____h541724[6] && + !_theResult____h541724[5] && + !_theResult____h541724[4] && + !_theResult____h541724[3] && + !_theResult____h541724[2] && + !_theResult____h541724[1] && + !_theResult____h541724[0]) ? + _theResult____h541724 : + _theResult___snd__h550000 ; + assign _theResult___snd__h550000 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0], 2'd0 } ; - assign _theResult___snd__h550022 = - _theResult____h541723 << + assign _theResult___snd__h550023 = + _theResult____h541724 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 ; - assign _theResult___snd__h558738 = - (f2_exp__h521135 == 8'd0) ? - _theResult___snd__h558752 : - _theResult___snd__h540335 ; - assign _theResult___snd__h558752 = - (f2_exp__h521135 == 8'd0 && !f2_sfd__h521136[22] && + assign _theResult___snd__h558739 = + (f2_exp__h521136 == 8'd0) ? + _theResult___snd__h558753 : + _theResult___snd__h540336 ; + assign _theResult___snd__h558753 = + (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ? - sfd__h521497 : - _theResult___snd__h558758 ; - assign _theResult___snd__h558758 = + sfd__h521498 : + _theResult___snd__h558759 ; + assign _theResult___snd__h558759 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0], 2'd0 } ; - assign _theResult___snd__h558776 = - sfd__h521497 << + assign _theResult___snd__h558777 = + sfd__h521498 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ; - assign _theResult___snd__h579637 = - (f3_exp__h560439 == 8'd0) ? - _theResult___snd__h579646 : - _theResult___snd__h579639 ; - assign _theResult___snd__h579639 = { f3_sfd__h560440, 34'd0 } ; - assign _theResult___snd__h579646 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___snd__h579638 = + (f3_exp__h560440 == 8'd0) ? + _theResult___snd__h579647 : + _theResult___snd__h579640 ; + assign _theResult___snd__h579640 = { f3_sfd__h560441, 34'd0 } ; + assign _theResult___snd__h579647 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560801 : - _theResult___snd__h579652 ; - assign _theResult___snd__h579652 = + sfd__h560802 : + _theResult___snd__h579653 ; + assign _theResult___snd__h579653 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0], 2'd0 } ; - assign _theResult___snd__h579675 = - sfd__h560801 << + assign _theResult___snd__h579676 = + sfd__h560802 << IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 ; - assign _theResult___snd__h589274 = { _theResult____h581027[55:0], 1'd0 } ; - assign _theResult___snd__h589285 = - (!_theResult____h581027[56] && _theResult____h581027[55]) ? - _theResult___snd__h589287 : - _theResult___snd__h589297 ; - assign _theResult___snd__h589287 = { _theResult____h581027[54:0], 2'd0 } ; - assign _theResult___snd__h589297 = - (!_theResult____h581027[56] && !_theResult____h581027[55] && - !_theResult____h581027[54] && - !_theResult____h581027[53] && - !_theResult____h581027[52] && - !_theResult____h581027[51] && - !_theResult____h581027[50] && - !_theResult____h581027[49] && - !_theResult____h581027[48] && - !_theResult____h581027[47] && - !_theResult____h581027[46] && - !_theResult____h581027[45] && - !_theResult____h581027[44] && - !_theResult____h581027[43] && - !_theResult____h581027[42] && - !_theResult____h581027[41] && - !_theResult____h581027[40] && - !_theResult____h581027[39] && - !_theResult____h581027[38] && - !_theResult____h581027[37] && - !_theResult____h581027[36] && - !_theResult____h581027[35] && - !_theResult____h581027[34] && - !_theResult____h581027[33] && - !_theResult____h581027[32] && - !_theResult____h581027[31] && - !_theResult____h581027[30] && - !_theResult____h581027[29] && - !_theResult____h581027[28] && - !_theResult____h581027[27] && - !_theResult____h581027[26] && - !_theResult____h581027[25] && - !_theResult____h581027[24] && - !_theResult____h581027[23] && - !_theResult____h581027[22] && - !_theResult____h581027[21] && - !_theResult____h581027[20] && - !_theResult____h581027[19] && - !_theResult____h581027[18] && - !_theResult____h581027[17] && - !_theResult____h581027[16] && - !_theResult____h581027[15] && - !_theResult____h581027[14] && - !_theResult____h581027[13] && - !_theResult____h581027[12] && - !_theResult____h581027[11] && - !_theResult____h581027[10] && - !_theResult____h581027[9] && - !_theResult____h581027[8] && - !_theResult____h581027[7] && - !_theResult____h581027[6] && - !_theResult____h581027[5] && - !_theResult____h581027[4] && - !_theResult____h581027[3] && - !_theResult____h581027[2] && - !_theResult____h581027[1] && - !_theResult____h581027[0]) ? - _theResult____h581027 : - _theResult___snd__h589303 ; - assign _theResult___snd__h589303 = + assign _theResult___snd__h589275 = { _theResult____h581028[55:0], 1'd0 } ; + assign _theResult___snd__h589286 = + (!_theResult____h581028[56] && _theResult____h581028[55]) ? + _theResult___snd__h589288 : + _theResult___snd__h589298 ; + assign _theResult___snd__h589288 = { _theResult____h581028[54:0], 2'd0 } ; + assign _theResult___snd__h589298 = + (!_theResult____h581028[56] && !_theResult____h581028[55] && + !_theResult____h581028[54] && + !_theResult____h581028[53] && + !_theResult____h581028[52] && + !_theResult____h581028[51] && + !_theResult____h581028[50] && + !_theResult____h581028[49] && + !_theResult____h581028[48] && + !_theResult____h581028[47] && + !_theResult____h581028[46] && + !_theResult____h581028[45] && + !_theResult____h581028[44] && + !_theResult____h581028[43] && + !_theResult____h581028[42] && + !_theResult____h581028[41] && + !_theResult____h581028[40] && + !_theResult____h581028[39] && + !_theResult____h581028[38] && + !_theResult____h581028[37] && + !_theResult____h581028[36] && + !_theResult____h581028[35] && + !_theResult____h581028[34] && + !_theResult____h581028[33] && + !_theResult____h581028[32] && + !_theResult____h581028[31] && + !_theResult____h581028[30] && + !_theResult____h581028[29] && + !_theResult____h581028[28] && + !_theResult____h581028[27] && + !_theResult____h581028[26] && + !_theResult____h581028[25] && + !_theResult____h581028[24] && + !_theResult____h581028[23] && + !_theResult____h581028[22] && + !_theResult____h581028[21] && + !_theResult____h581028[20] && + !_theResult____h581028[19] && + !_theResult____h581028[18] && + !_theResult____h581028[17] && + !_theResult____h581028[16] && + !_theResult____h581028[15] && + !_theResult____h581028[14] && + !_theResult____h581028[13] && + !_theResult____h581028[12] && + !_theResult____h581028[11] && + !_theResult____h581028[10] && + !_theResult____h581028[9] && + !_theResult____h581028[8] && + !_theResult____h581028[7] && + !_theResult____h581028[6] && + !_theResult____h581028[5] && + !_theResult____h581028[4] && + !_theResult____h581028[3] && + !_theResult____h581028[2] && + !_theResult____h581028[1] && + !_theResult____h581028[0]) ? + _theResult____h581028 : + _theResult___snd__h589304 ; + assign _theResult___snd__h589304 = { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0], 2'd0 } ; - assign _theResult___snd__h589326 = - _theResult____h581027 << + assign _theResult___snd__h589327 = + _theResult____h581028 << IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 ; - assign _theResult___snd__h598042 = - (f3_exp__h560439 == 8'd0) ? - _theResult___snd__h598056 : - _theResult___snd__h579639 ; - assign _theResult___snd__h598056 = - (f3_exp__h560439 == 8'd0 && !f3_sfd__h560440[22] && + assign _theResult___snd__h598043 = + (f3_exp__h560440 == 8'd0) ? + _theResult___snd__h598057 : + _theResult___snd__h579640 ; + assign _theResult___snd__h598057 = + (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ? - sfd__h560801 : - _theResult___snd__h598062 ; - assign _theResult___snd__h598062 = + sfd__h560802 : + _theResult___snd__h598063 ; + assign _theResult___snd__h598063 = { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0], 2'd0 } ; - assign _theResult___snd__h598080 = - sfd__h560801 << + assign _theResult___snd__h598081 = + sfd__h560802 << IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ; - assign _theResult___snd__h603372 = - b__h602950[63] ? b___1__h603421 : b__h602950 ; - assign _theResult___snd_fst_exp__h363379 = + assign _theResult___snd__h603373 = + b__h602951[63] ? b___1__h603422 : b__h602951 ; + assign _theResult___snd_fst_exp__h363380 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_exp__h354794 : - _theResult___fst_exp__h363376 ; - assign _theResult___snd_fst_exp__h381199 = + _theResult___fst_exp__h354795 : + _theResult___fst_exp__h363377 ; + assign _theResult___snd_fst_exp__h381200 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_exp__h372560 : - _theResult___fst_exp__h381196 ; - assign _theResult___snd_fst_exp__h409076 = + _theResult___fst_exp__h372561 : + _theResult___fst_exp__h381197 ; + assign _theResult___snd_fst_exp__h409077 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_exp__h400491 : - _theResult___fst_exp__h409073 ; - assign _theResult___snd_fst_exp__h426896 = + _theResult___fst_exp__h400492 : + _theResult___fst_exp__h409074 ; + assign _theResult___snd_fst_exp__h426897 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_exp__h418257 : - _theResult___fst_exp__h426893 ; - assign _theResult___snd_fst_exp__h454771 = + _theResult___fst_exp__h418258 : + _theResult___fst_exp__h426894 ; + assign _theResult___snd_fst_exp__h454772 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_exp__h446186 : - _theResult___fst_exp__h454768 ; - assign _theResult___snd_fst_exp__h472591 = + _theResult___fst_exp__h446187 : + _theResult___fst_exp__h454769 ; + assign _theResult___snd_fst_exp__h472592 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_exp__h463952 : - _theResult___fst_exp__h472588 ; - assign _theResult___snd_fst_exp__h502290 = + _theResult___fst_exp__h463953 : + _theResult___fst_exp__h472589 ; + assign _theResult___snd_fst_exp__h502291 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 11'd0 : - _theResult___fst_exp__h502287 ; - assign _theResult___snd_fst_exp__h520725 = + _theResult___fst_exp__h502288 ; + assign _theResult___snd_fst_exp__h520726 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_exp__h511938 : - _theResult___fst_exp__h520722 ; - assign _theResult___snd_fst_exp__h541143 = + _theResult___fst_exp__h511939 : + _theResult___fst_exp__h520723 ; + assign _theResult___snd_fst_exp__h541144 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 11'd0 : - _theResult___fst_exp__h541140 ; - assign _theResult___snd_fst_exp__h559578 = + _theResult___fst_exp__h541141 ; + assign _theResult___snd_fst_exp__h559579 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_exp__h550791 : - _theResult___fst_exp__h559575 ; - assign _theResult___snd_fst_exp__h580447 = + _theResult___fst_exp__h550792 : + _theResult___fst_exp__h559576 ; + assign _theResult___snd_fst_exp__h580448 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 11'd0 : - _theResult___fst_exp__h580444 ; - assign _theResult___snd_fst_exp__h598882 = + _theResult___fst_exp__h580445 ; + assign _theResult___snd_fst_exp__h598883 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_exp__h590095 : - _theResult___fst_exp__h598879 ; - assign _theResult___snd_fst_sfd__h338431 = + _theResult___fst_exp__h590096 : + _theResult___fst_exp__h598880 ; + assign _theResult___snd_fst_sfd__h338432 = (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h363380 = + assign _theResult___snd_fst_sfd__h363381 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ? - _theResult___fst_sfd__h354795 : - _theResult___fst_sfd__h363377 ; - assign _theResult___snd_fst_sfd__h381200 = + _theResult___fst_sfd__h354796 : + _theResult___fst_sfd__h363378 ; + assign _theResult___snd_fst_sfd__h381201 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ? - _theResult___fst_sfd__h372561 : - _theResult___fst_sfd__h381197 ; - assign _theResult___snd_fst_sfd__h384133 = + _theResult___fst_sfd__h372562 : + _theResult___fst_sfd__h381198 ; + assign _theResult___snd_fst_sfd__h384134 = (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h409077 = + assign _theResult___snd_fst_sfd__h409078 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ? - _theResult___fst_sfd__h400492 : - _theResult___fst_sfd__h409074 ; - assign _theResult___snd_fst_sfd__h426897 = + _theResult___fst_sfd__h400493 : + _theResult___fst_sfd__h409075 ; + assign _theResult___snd_fst_sfd__h426898 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ? - _theResult___fst_sfd__h418258 : - _theResult___fst_sfd__h426894 ; - assign _theResult___snd_fst_sfd__h429828 = + _theResult___fst_sfd__h418259 : + _theResult___fst_sfd__h426895 ; + assign _theResult___snd_fst_sfd__h429829 = (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] == 23'd0) ? 23'd2097152 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ; - assign _theResult___snd_fst_sfd__h454772 = + assign _theResult___snd_fst_sfd__h454773 = _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ? - _theResult___fst_sfd__h446187 : - _theResult___fst_sfd__h454769 ; - assign _theResult___snd_fst_sfd__h472592 = + _theResult___fst_sfd__h446188 : + _theResult___fst_sfd__h454770 ; + assign _theResult___snd_fst_sfd__h472593 = SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ? - _theResult___fst_sfd__h463953 : - _theResult___fst_sfd__h472589 ; - assign _theResult___snd_fst_sfd__h482457 = - (f1_sfd__h482142 == 23'd0) ? + _theResult___fst_sfd__h463954 : + _theResult___fst_sfd__h472590 ; + assign _theResult___snd_fst_sfd__h482458 = + (f1_sfd__h482143 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h482205 ; - assign _theResult___snd_fst_sfd__h502291 = + out___1_sfd__h482206 ; + assign _theResult___snd_fst_sfd__h502292 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ? 52'd0 : - _theResult___fst_sfd__h502288 ; - assign _theResult___snd_fst_sfd__h520726 = + _theResult___fst_sfd__h502289 ; + assign _theResult___snd_fst_sfd__h520727 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ? - _theResult___fst_sfd__h511939 : - _theResult___fst_sfd__h520723 ; - assign _theResult___snd_fst_sfd__h521451 = - (f2_sfd__h521136 == 23'd0) ? + _theResult___fst_sfd__h511940 : + _theResult___fst_sfd__h520724 ; + assign _theResult___snd_fst_sfd__h521452 = + (f2_sfd__h521137 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h521199 ; - assign _theResult___snd_fst_sfd__h541144 = + out___1_sfd__h521200 ; + assign _theResult___snd_fst_sfd__h541145 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ? 52'd0 : - _theResult___fst_sfd__h541141 ; - assign _theResult___snd_fst_sfd__h559579 = + _theResult___fst_sfd__h541142 ; + assign _theResult___snd_fst_sfd__h559580 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ? - _theResult___fst_sfd__h550792 : - _theResult___fst_sfd__h559576 ; - assign _theResult___snd_fst_sfd__h560755 = - (f3_sfd__h560440 == 23'd0) ? + _theResult___fst_sfd__h550793 : + _theResult___fst_sfd__h559577 ; + assign _theResult___snd_fst_sfd__h560756 = + (f3_sfd__h560441 == 23'd0) ? 52'h4000000000000 : - out___1_sfd__h560503 ; - assign _theResult___snd_fst_sfd__h580448 = + out___1_sfd__h560504 ; + assign _theResult___snd_fst_sfd__h580449 = _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ? 52'd0 : - _theResult___fst_sfd__h580445 ; - assign _theResult___snd_fst_sfd__h598883 = + _theResult___fst_sfd__h580446 ; + assign _theResult___snd_fst_sfd__h598884 = SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ? - _theResult___fst_sfd__h590096 : - _theResult___fst_sfd__h598880 ; - assign a___1__h603090 = + _theResult___fst_sfd__h590097 : + _theResult___fst_sfd__h598881 ; + assign a___1__h603091 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ? { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } : { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ; - assign a___1__h603376 = 64'd0 - a__h602949 ; - assign a__h602949 = + assign a___1__h603377 = 64'd0 - a__h602950 ; + assign a__h602950 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - a___1__h603090 : + a___1__h603091 : coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign b___1__h603091 = + assign b___1__h603092 = (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ? { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}}, coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } : { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ; - assign b___1__h603421 = 64'd0 - b__h602950 ; - assign b__h602950 = + assign b___1__h603422 = 64'd0 - b__h602951 ; + assign b__h602951 = coreFix_fpuMulDivExe_0_regToExeQ$first[227] ? - b___1__h603091 : + b___1__h603092 : coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign base__h712403 = { csrf_stvec_base_hi_reg, 2'b0 } ; - assign base__h712423 = { csrf_mtvec_base_hi_reg, 2'b0 } ; - assign cause_code__h709443 = - commitStage_commitTrap[36] ? i__h709618 : i__h709458 ; + assign base__h712404 = { csrf_stvec_base_hi_reg, 2'b0 } ; + assign base__h712424 = { csrf_mtvec_base_hi_reg, 2'b0 } ; + assign cause_code__h709444 = + commitStage_commitTrap[36] ? i__h709619 : i__h709459 ; assign commitStage_commitTrap_4347_BIT_36_4589_AND_co_ETC___d14654 = commitStage_commitTrap[36] && commitStage_commitTrap[35:32] != 4'd0 && @@ -29592,10 +29592,10 @@ module mkCore(CLK, commitStage_f_rob_data$D_OUT[166] ? CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 : CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251, - trap_val__h709444, + trap_val__h709445, IF_commitStage_f_rob_data_first__4755_BITS_97__ETC___d14926 } ; assign commitStage_rg_serial_num_4328_PLUS_IF_rob_deq_ETC___d15456 = - commitStage_rg_serial_num + y__h730489 ; + commitStage_rg_serial_num + y__h730360 ; assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 = coreFix_aluExe_0_bypassWire_0$wget[70:64] == coreFix_aluExe_0_dispToRegQ$first[84:78] ; @@ -29743,9 +29743,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29753,9 +29753,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29763,9 +29763,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29773,9 +29773,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973) ; assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 = (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 || @@ -29783,9 +29783,9 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 || coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) && NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 | - ((f3_exp__h560439 != 8'd255 || f3_sfd__h560440 == 23'd0) && - (f3_exp__h560439 != 8'd255 || f3_sfd__h560440 != 23'd0) && - (f3_exp__h560439 != 8'd0 || f3_sfd__h560440 != 23'd0) && + ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) && + (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) && + (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) && IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015) ; assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 = coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ; @@ -29825,7 +29825,7 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] && coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] == - y__h254804 ; + y__h254805 ; assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 || @@ -30043,15 +30043,15 @@ module mkCore(CLK, !coreFix_memExe_forwardQ_deqReq_rl) && coreFix_memExe_forwardQ_full ; assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706 = - { coreFix_memExe_lsq$getOrigBE << x__h183903[2:0], - x__h183903, + { coreFix_memExe_lsq$getOrigBE << x__h183904[2:0], + x__h183904, coreFix_memExe_regToExeQ$first[75:12], coreFix_memExe_lsq$getOrigBE, coreFix_memExe_lsq$getOrigBE[7] ? - x__h183903[2:0] != 3'd0 : + x__h183904[2:0] != 3'd0 : (coreFix_memExe_lsq$getOrigBE[3] ? - x__h183903[1:0] != 2'd0 : - coreFix_memExe_lsq$getOrigBE[1] && x__h183903[0]) } ; + x__h183904[1:0] != 2'd0 : + coreFix_memExe_lsq$getOrigBE[1] && x__h183904[0]) } ; assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 = coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 || @@ -30128,7 +30128,7 @@ module mkCore(CLK, v_f_to_TV_0$FULL_N && fetchStage$iTlbIfc_noPendingReq && coreFix_memExe_dTlb$noPendingReq ; - assign csr_addr__h655327 = + assign csr_addr__h655328 = fetchStage$pipelines_0_first[173] ? IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 : 12'hCFF ; @@ -30144,7 +30144,7 @@ module mkCore(CLK, fetchStage$pipelines_0_first[199:195] == 5'd13 && (fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 || csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 || - csr_addr__h655327 == 12'h8FF) ; + csr_addr__h655328 == 12'h8FF) ; assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 = csrf_fs_reg == 2'd0 && (fetchStage$pipelines_0_first[95] && @@ -30176,24 +30176,24 @@ module mkCore(CLK, _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14716) ; assign csrf_prv_reg_read__2787_ULE_1___d14696 = csrf_prv_reg <= 2'd1 ; assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 = - csrf_prv_reg < csr_addr__h655327[9:8] ; + csrf_prv_reg < csr_addr__h655328[9:8] ; assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498 = csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq || fetchStage$RDY_pipelines_0_first && IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435 ; - assign data75283_BITS_31_TO_0__q13 = data__h475283[31:0] ; - assign data___1__h475009 = + assign data75284_BITS_31_TO_0__q13 = data__h475284[31:0] ; + assign data___1__h475010 = { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}}, IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ; - assign data___1__h475817 = - { {32{data75283_BITS_31_TO_0__q13[31]}}, - data75283_BITS_31_TO_0__q13 } ; - assign data__h475283 = + assign data___1__h475818 = + { {32{data75284_BITS_31_TO_0__q13[31]}}, + data75284_BITS_31_TO_0__q13 } ; + assign data__h475284 = (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] == 2'd2) ? - x_quotient__h475197 : - x_remainder__h475198 ; - assign dcsr_cause__h708962 = + x_quotient__h475198 : + x_remainder__h475199 ; + assign dcsr_cause__h708963 = (commitStage_commitTrap[36] && commitStage_commitTrap[35:32] == 4'd14) ? 3'd3 : @@ -30210,31 +30210,31 @@ module mkCore(CLK, commitStage_commitTrap[35:32] != 4'd14) ? 3'd4 : 3'd1) ; - assign din_inc___2_exp__h381230 = _theResult___fst_exp__h354197 + 8'd1 ; - assign din_inc___2_exp__h381254 = _theResult___fst_exp__h362853 + 8'd1 ; - assign din_inc___2_exp__h381284 = _theResult___fst_exp__h371963 + 8'd1 ; - assign din_inc___2_exp__h381308 = _theResult___fst_exp__h380648 + 8'd1 ; - assign din_inc___2_exp__h426927 = _theResult___fst_exp__h399894 + 8'd1 ; - assign din_inc___2_exp__h426951 = _theResult___fst_exp__h408550 + 8'd1 ; - assign din_inc___2_exp__h426981 = _theResult___fst_exp__h417660 + 8'd1 ; - assign din_inc___2_exp__h427005 = _theResult___fst_exp__h426345 + 8'd1 ; - assign din_inc___2_exp__h472622 = _theResult___fst_exp__h445589 + 8'd1 ; - assign din_inc___2_exp__h472646 = _theResult___fst_exp__h454245 + 8'd1 ; - assign din_inc___2_exp__h472676 = _theResult___fst_exp__h463355 + 8'd1 ; - assign din_inc___2_exp__h472700 = _theResult___fst_exp__h472040 + 8'd1 ; - assign din_inc___2_exp__h520779 = _theResult___fst_exp__h501529 + 11'd1 ; - assign din_inc___2_exp__h520814 = _theResult___fst_exp__h511106 + 11'd1 ; - assign din_inc___2_exp__h520840 = _theResult___fst_exp__h519939 + 11'd1 ; - assign din_inc___2_exp__h559632 = _theResult___fst_exp__h540382 + 11'd1 ; - assign din_inc___2_exp__h559667 = _theResult___fst_exp__h549959 + 11'd1 ; - assign din_inc___2_exp__h559693 = _theResult___fst_exp__h558792 + 11'd1 ; - assign din_inc___2_exp__h598936 = _theResult___fst_exp__h579686 + 11'd1 ; - assign din_inc___2_exp__h598971 = _theResult___fst_exp__h589263 + 11'd1 ; - assign din_inc___2_exp__h598997 = _theResult___fst_exp__h598096 + 11'd1 ; - assign enabled_ints___1__h651643 = pend_ints__h651116 & y__h651655 ; - assign enabled_ints__h651689 = - pend_ints__h651116 & - { r1__read_BITS_13_TO_0___h651665, csrf_mideleg_1_0_reg } ; + assign din_inc___2_exp__h381231 = _theResult___fst_exp__h354198 + 8'd1 ; + assign din_inc___2_exp__h381255 = _theResult___fst_exp__h362854 + 8'd1 ; + assign din_inc___2_exp__h381285 = _theResult___fst_exp__h371964 + 8'd1 ; + assign din_inc___2_exp__h381309 = _theResult___fst_exp__h380649 + 8'd1 ; + assign din_inc___2_exp__h426928 = _theResult___fst_exp__h399895 + 8'd1 ; + assign din_inc___2_exp__h426952 = _theResult___fst_exp__h408551 + 8'd1 ; + assign din_inc___2_exp__h426982 = _theResult___fst_exp__h417661 + 8'd1 ; + assign din_inc___2_exp__h427006 = _theResult___fst_exp__h426346 + 8'd1 ; + assign din_inc___2_exp__h472623 = _theResult___fst_exp__h445590 + 8'd1 ; + assign din_inc___2_exp__h472647 = _theResult___fst_exp__h454246 + 8'd1 ; + assign din_inc___2_exp__h472677 = _theResult___fst_exp__h463356 + 8'd1 ; + assign din_inc___2_exp__h472701 = _theResult___fst_exp__h472041 + 8'd1 ; + assign din_inc___2_exp__h520780 = _theResult___fst_exp__h501530 + 11'd1 ; + assign din_inc___2_exp__h520815 = _theResult___fst_exp__h511107 + 11'd1 ; + assign din_inc___2_exp__h520841 = _theResult___fst_exp__h519940 + 11'd1 ; + assign din_inc___2_exp__h559633 = _theResult___fst_exp__h540383 + 11'd1 ; + assign din_inc___2_exp__h559668 = _theResult___fst_exp__h549960 + 11'd1 ; + assign din_inc___2_exp__h559694 = _theResult___fst_exp__h558793 + 11'd1 ; + assign din_inc___2_exp__h598937 = _theResult___fst_exp__h579687 + 11'd1 ; + assign din_inc___2_exp__h598972 = _theResult___fst_exp__h589264 + 11'd1 ; + assign din_inc___2_exp__h598998 = _theResult___fst_exp__h598097 + 11'd1 ; + assign enabled_ints___1__h651644 = pend_ints__h651117 & y__h651656 ; + assign enabled_ints__h651690 = + pend_ints__h651117 & + { r1__read_BITS_13_TO_0___h651666, csrf_mideleg_1_0_reg } ; assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734 = epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] && (!fetchStage$pipelines_0_canDeq || @@ -30256,34 +30256,34 @@ module mkCore(CLK, specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 && IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890) ; - assign f1_exp82141_MINUS_127__q136 = f1_exp__h482141 - 8'd127 ; - assign f1_exp__h482141 = + assign f1_exp82142_MINUS_127__q136 = f1_exp__h482142 - 8'd127 ; + assign f1_exp__h482142 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] : 8'd255 ; - assign f1_sfd__h482142 = + assign f1_sfd__h482143 = (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] : 23'd4194304 ; - assign f2_exp21135_MINUS_127__q176 = f2_exp__h521135 - 8'd127 ; - assign f2_exp__h521135 = + assign f2_exp21136_MINUS_127__q176 = f2_exp__h521136 - 8'd127 ; + assign f2_exp__h521136 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] : 8'd255 ; - assign f2_sfd__h521136 = + assign f2_sfd__h521137 = (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] : 23'd4194304 ; - assign f3_exp60439_MINUS_127__q153 = f3_exp__h560439 - 8'd127 ; - assign f3_exp__h560439 = + assign f3_exp60440_MINUS_127__q153 = f3_exp__h560440 - 8'd127 ; + assign f3_exp__h560440 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] : 8'd255 ; - assign f3_sfd__h560440 = + assign f3_sfd__h560441 = (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ? coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] : 23'd4194304 ; @@ -30293,7 +30293,7 @@ module mkCore(CLK, csrf_stats_module_writeQ$FULL_N) && (f_csr_reqs$D_OUT[75:64] != 12'd2048 || csrf_terminate_module_terminateQ$FULL_N) ; - assign fcsr_csr__read__h609377 = { 56'd0, x__h613035 } ; + assign fcsr_csr__read__h609378 = { 56'd0, x__h613036 } ; assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078 = fetchStage$RDY_pipelines_1_deq && (!fetchStage$pipelines_0_canDeq || @@ -30374,9 +30374,9 @@ module mkCore(CLK, assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 = (fetchStage$pipelines_0_first[194:192] == 3'd0 && fetchStage$pipelines_0_first[178:174] == 5'd15 || - rs1__h655328 != 5'd0 || - imm__h655329 != 32'd0) && - csr_addr__h655327[11:10] == 2'b11 ; + rs1__h655329 != 5'd0 || + imm__h655330 != 32'd0) && + csr_addr__h655328[11:10] == 2'b11 ; assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 = (fetchStage$pipelines_0_first[194:192] == 3'd0 || fetchStage$pipelines_0_first[194:192] == 3'd1) && @@ -30483,7 +30483,7 @@ module mkCore(CLK, assign fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676 = { fetchStage$pipelines_1_first[173], CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ; - assign fflags__h728014 = + assign fflags__h727885 = ({ rob$deqPort_0_deq_data[361:356], 1'd0, rob$deqPort_0_deq_data[354:350], @@ -30493,8 +30493,8 @@ module mkCore(CLK, rob$deqPort_0_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h727999 ; - assign fflags__h730667 = + po_fflags__h727870 ; + assign fflags__h730538 = ({ rob$deqPort_1_deq_data[361:356], 1'd0, rob$deqPort_1_deq_data[354:350], @@ -30504,105 +30504,105 @@ module mkCore(CLK, rob$deqPort_1_deq_data[336:330] } == 32'hE0000053) ? 5'b0 : - po_fflags__h730652 ; - assign fflags__h733287 = + po_fflags__h730523 ; + assign fflags__h733158 = NOT_rob_deqPort_0_canDeq__5320_5321_OR_rob_deq_ETC___d15664 ? - y_avValue_fst__h733224 : + y_avValue_fst__h733095 : IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 ; - assign fflags_csr__read__h609352 = { 59'd0, csrf_fflags_reg } ; - assign frm_csr__read__h609363 = { 61'd0, csrf_frm_reg } ; - assign guard__h346096 = - { IF_sfdin54191_BIT_33_THEN_2_ELSE_0__q29[1], - { sfdin__h354191[32:0], 23'd0 } != 56'd0 } ; - assign guard__h354805 = - { IF_theResult___snd62804_BIT_33_THEN_2_ELSE_0__q31[1], - { _theResult___snd__h362804[32:0], 23'd0 } != 56'd0 } ; - assign guard__h363735 = - { IF_sfdin71957_BIT_33_THEN_2_ELSE_0__q39[1], - { sfdin__h371957[32:0], 23'd0 } != 56'd0 } ; - assign guard__h364333 = x__h364435 != 57'd0 ; - assign guard__h372571 = - { IF_theResult___snd80594_BIT_33_THEN_2_ELSE_0__q44[1], - { _theResult___snd__h380594[32:0], 23'd0 } != 56'd0 } ; - assign guard__h391795 = - { IF_sfdin99888_BIT_33_THEN_2_ELSE_0__q64[1], - { sfdin__h399888[32:0], 23'd0 } != 56'd0 } ; - assign guard__h400502 = - { IF_theResult___snd08501_BIT_33_THEN_2_ELSE_0__q66[1], - { _theResult___snd__h408501[32:0], 23'd0 } != 56'd0 } ; - assign guard__h409432 = - { IF_sfdin17654_BIT_33_THEN_2_ELSE_0__q74[1], - { sfdin__h417654[32:0], 23'd0 } != 56'd0 } ; - assign guard__h410030 = x__h410132 != 57'd0 ; - assign guard__h418268 = - { IF_theResult___snd26291_BIT_33_THEN_2_ELSE_0__q79[1], - { _theResult___snd__h426291[32:0], 23'd0 } != 56'd0 } ; - assign guard__h437490 = - { IF_sfdin45583_BIT_33_THEN_2_ELSE_0__q99[1], - { sfdin__h445583[32:0], 23'd0 } != 56'd0 } ; - assign guard__h446197 = - { IF_theResult___snd54196_BIT_33_THEN_2_ELSE_0__q101[1], - { _theResult___snd__h454196[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455127 = - { IF_sfdin63349_BIT_33_THEN_2_ELSE_0__q109[1], - { sfdin__h463349[32:0], 23'd0 } != 56'd0 } ; - assign guard__h455725 = x__h455827 != 57'd0 ; - assign guard__h463963 = - { IF_theResult___snd71986_BIT_33_THEN_2_ELSE_0__q114[1], - { _theResult___snd__h471986[32:0], 23'd0 } != 56'd0 } ; - assign guard__h493568 = - { IF_theResult___snd01480_BIT_4_THEN_2_ELSE_0__q135[1], - { _theResult___snd__h501480[3:0], 52'd0 } != 56'd0 } ; - assign guard__h502880 = - { IF_sfdin11100_BIT_4_THEN_2_ELSE_0__q139[1], - { sfdin__h511100[3:0], 52'd0 } != 56'd0 } ; - assign guard__h503478 = x__h503578 != 57'd0 ; - assign guard__h511949 = - { IF_theResult___snd19885_BIT_4_THEN_2_ELSE_0__q142[1], - { _theResult___snd__h519885[3:0], 52'd0 } != 56'd0 } ; - assign guard__h532421 = - { IF_theResult___snd40333_BIT_4_THEN_2_ELSE_0__q175[1], - { _theResult___snd__h540333[3:0], 52'd0 } != 56'd0 } ; - assign guard__h541733 = - { IF_sfdin49953_BIT_4_THEN_2_ELSE_0__q179[1], - { sfdin__h549953[3:0], 52'd0 } != 56'd0 } ; - assign guard__h542331 = x__h542431 != 57'd0 ; - assign guard__h550802 = - { IF_theResult___snd58738_BIT_4_THEN_2_ELSE_0__q182[1], - { _theResult___snd__h558738[3:0], 52'd0 } != 56'd0 } ; - assign guard__h571725 = - { IF_theResult___snd79637_BIT_4_THEN_2_ELSE_0__q152[1], - { _theResult___snd__h579637[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581037 = - { IF_sfdin89257_BIT_4_THEN_2_ELSE_0__q156[1], - { sfdin__h589257[3:0], 52'd0 } != 56'd0 } ; - assign guard__h581635 = x__h581735 != 57'd0 ; - assign guard__h590106 = - { IF_theResult___snd98042_BIT_4_THEN_2_ELSE_0__q159[1], - { _theResult___snd__h598042[3:0], 52'd0 } != 56'd0 } ; - assign idx__h685370 = + assign fflags_csr__read__h609353 = { 59'd0, csrf_fflags_reg } ; + assign frm_csr__read__h609364 = { 61'd0, csrf_frm_reg } ; + assign guard__h346097 = + { IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29[1], + { sfdin__h354192[32:0], 23'd0 } != 56'd0 } ; + assign guard__h354806 = + { IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31[1], + { _theResult___snd__h362805[32:0], 23'd0 } != 56'd0 } ; + assign guard__h363736 = + { IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39[1], + { sfdin__h371958[32:0], 23'd0 } != 56'd0 } ; + assign guard__h364334 = x__h364436 != 57'd0 ; + assign guard__h372572 = + { IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44[1], + { _theResult___snd__h380595[32:0], 23'd0 } != 56'd0 } ; + assign guard__h391796 = + { IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64[1], + { sfdin__h399889[32:0], 23'd0 } != 56'd0 } ; + assign guard__h400503 = + { IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66[1], + { _theResult___snd__h408502[32:0], 23'd0 } != 56'd0 } ; + assign guard__h409433 = + { IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74[1], + { sfdin__h417655[32:0], 23'd0 } != 56'd0 } ; + assign guard__h410031 = x__h410133 != 57'd0 ; + assign guard__h418269 = + { IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79[1], + { _theResult___snd__h426292[32:0], 23'd0 } != 56'd0 } ; + assign guard__h437491 = + { IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99[1], + { sfdin__h445584[32:0], 23'd0 } != 56'd0 } ; + assign guard__h446198 = + { IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101[1], + { _theResult___snd__h454197[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455128 = + { IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109[1], + { sfdin__h463350[32:0], 23'd0 } != 56'd0 } ; + assign guard__h455726 = x__h455828 != 57'd0 ; + assign guard__h463964 = + { IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114[1], + { _theResult___snd__h471987[32:0], 23'd0 } != 56'd0 } ; + assign guard__h493569 = + { IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135[1], + { _theResult___snd__h501481[3:0], 52'd0 } != 56'd0 } ; + assign guard__h502881 = + { IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139[1], + { sfdin__h511101[3:0], 52'd0 } != 56'd0 } ; + assign guard__h503479 = x__h503579 != 57'd0 ; + assign guard__h511950 = + { IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142[1], + { _theResult___snd__h519886[3:0], 52'd0 } != 56'd0 } ; + assign guard__h532422 = + { IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175[1], + { _theResult___snd__h540334[3:0], 52'd0 } != 56'd0 } ; + assign guard__h541734 = + { IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179[1], + { sfdin__h549954[3:0], 52'd0 } != 56'd0 } ; + assign guard__h542332 = x__h542432 != 57'd0 ; + assign guard__h550803 = + { IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182[1], + { _theResult___snd__h558739[3:0], 52'd0 } != 56'd0 } ; + assign guard__h571726 = + { IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152[1], + { _theResult___snd__h579638[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581038 = + { IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156[1], + { sfdin__h589258[3:0], 52'd0 } != 56'd0 } ; + assign guard__h581636 = x__h581736 != 57'd0 ; + assign guard__h590107 = + { IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159[1], + { _theResult___snd__h598043[3:0], 52'd0 } != 56'd0 } ; + assign idx__h685371 = fetchStage$pipelines_0_canDeq && NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 || !coreFix_aluExe_0_rsAlu$canEnq || NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770 ; - assign imm__h655329 = + assign imm__h655330 = fetchStage$pipelines_0_first[160] ? fetchStage$pipelines_0_first[159:128] : 32'd0 ; - assign k__h669625 = + assign k__h669626 = !coreFix_aluExe_0_rsAlu$canEnq || coreFix_aluExe_1_rsAlu$canEnq && !coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ; - assign mcause_csr__read__h611019 = - { r1__read__h614498, csrf_mcause_code_reg } ; - assign mcounteren_csr__read__h610764 = - { r1__read__h614485, csrf_mcounteren_cy_reg } ; - assign medeleg_csr__read__h610371 = - { r1__read__h614346, csrf_medeleg_9_0_reg } ; - assign mideleg_csr__read__h610466 = - { r1__read__h614363, csrf_mideleg_1_0_reg } ; - assign mie_csr__read__h610590 = { r1__read__h614387, 1'b0 } ; - assign mip_csr__read__h611252 = { r1__read__h614504, 1'b0 } ; + assign mcause_csr__read__h611020 = + { r1__read__h614499, csrf_mcause_code_reg } ; + assign mcounteren_csr__read__h610765 = + { r1__read__h614486, csrf_mcounteren_cy_reg } ; + assign medeleg_csr__read__h610372 = + { r1__read__h614347, csrf_medeleg_9_0_reg } ; + assign mideleg_csr__read__h610467 = + { r1__read__h614364, csrf_mideleg_1_0_reg } ; + assign mie_csr__read__h610591 = { r1__read__h614388, 1'b0 } ; + assign mip_csr__read__h611253 = { r1__read__h614505, 1'b0 } ; assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 = mmio_cRqQ_enqReq_dummy2_2$Q_OUT && IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 || @@ -30686,302 +30686,302 @@ module mkCore(CLK, (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT || !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) && mmio_pRsQ_full ; - assign msip__h76123 = csrf_software_int_pend_vec_3 ; - assign mstatus_csr__read__h610223 = { r1__read__h614221, csrf_ie_vec_0 } ; - assign mtvec_csr__read__h610672 = - { r1__read__h614480, csrf_mtvec_mode_low_reg } ; - assign n___1__h198530 = + assign msip__h76124 = csrf_software_int_pend_vec_3 ; + assign mstatus_csr__read__h610224 = { r1__read__h614222, csrf_ie_vec_0 } ; + assign mtvec_csr__read__h610673 = + { r1__read__h614481, csrf_mtvec_mode_low_reg } ; + assign n___1__h198531 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] : - x__h197127[63:56], + x__h197128[63:56], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] : - x__h197127[55:48], + x__h197128[55:48], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] : - x__h197127[47:40], + x__h197128[47:40], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] : - x__h197127[39:32], + x__h197128[39:32], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] : - x__h197127[31:24], + x__h197128[31:24], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] : - x__h197127[23:16], + x__h197128[23:16], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] : - x__h197127[15:8], + x__h197128[15:8], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ? coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] : - x__h197127[7:0] } ; - assign n__read__h611356 = + x__h197128[7:0] } ; + assign n__read__h611357 = (csrf_mcycle_ehr_data_dummy2_0$Q_OUT && csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ? csrf_mcycle_ehr_data_rl : 64'd0 ; - assign n__read__h611547 = + assign n__read__h611548 = (csrf_minstret_ehr_data_dummy2_0$Q_OUT && csrf_minstret_ehr_data_dummy2_1$Q_OUT) ? csrf_minstret_ehr_data_rl : 64'd0 ; - assign n__read__h6760 = + assign n__read__h6761 = csrf_mcycle_ehr_data_dummy2_1$Q_OUT ? (csrf_mcycle_ehr_data_lat_0$whas ? - upd__h6874 : + upd__h6875 : csrf_mcycle_ehr_data_rl) : 64'd0 ; - assign n__read__h726694 = + assign n__read__h726565 = csrf_minstret_ehr_data_dummy2_1$Q_OUT ? IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 : 64'd0 ; - assign next_deqP___1__h296801 = + assign next_deqP___1__h296802 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP + 3'd1 ; - assign next_deqP___1__h304797 = + assign next_deqP___1__h304798 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ; - assign next_deqP___1__h311078 = + assign next_deqP___1__h311079 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ; - assign next_deqP___1__h318932 = + assign next_deqP___1__h318933 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ; - assign next_deqP___1__h328989 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; - assign next_deqP___1__h332214 = coreFix_memExe_forwardQ_deqP + 1'd1 ; - assign next_pc__h722452 = + assign next_deqP___1__h328990 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ; + assign next_deqP___1__h332215 = coreFix_memExe_forwardQ_deqP + 1'd1 ; + assign next_pc__h722453 = (rob$deqPort_0_deq_data[329:325] != 5'd13 && rob$deqPort_0_deq_data[97:96] == 2'd0) ? rob$deqPort_0_deq_data[95:32] : rob$deqPort_0_deq_data[425:362] + 64'd4 ; - assign old_fflags__h732774 = + assign old_fflags__h732645 = csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ; - assign out___1_sfd__h482205 = { f1_sfd__h482142, 29'd0 } ; - assign out___1_sfd__h521199 = { f2_sfd__h521136, 29'd0 } ; - assign out___1_sfd__h560503 = { f3_sfd__h560440, 29'd0 } ; - assign out_exp__h354716 = - sfdin__h354191[34] ? - _theResult___exp__h354713 : - _theResult___fst_exp__h354197 ; - assign out_exp__h363298 = - _theResult___snd__h362804[34] ? - _theResult___exp__h363295 : - _theResult___fst_exp__h362853 ; - assign out_exp__h372482 = - sfdin__h371957[34] ? - _theResult___exp__h372479 : - _theResult___fst_exp__h371963 ; - assign out_exp__h381118 = - _theResult___snd__h380594[34] ? - _theResult___exp__h381115 : - _theResult___fst_exp__h380648 ; - assign out_exp__h400413 = - sfdin__h399888[34] ? - _theResult___exp__h400410 : - _theResult___fst_exp__h399894 ; - assign out_exp__h408995 = - _theResult___snd__h408501[34] ? - _theResult___exp__h408992 : - _theResult___fst_exp__h408550 ; - assign out_exp__h418179 = - sfdin__h417654[34] ? - _theResult___exp__h418176 : - _theResult___fst_exp__h417660 ; - assign out_exp__h426815 = - _theResult___snd__h426291[34] ? - _theResult___exp__h426812 : - _theResult___fst_exp__h426345 ; - assign out_exp__h446108 = - sfdin__h445583[34] ? - _theResult___exp__h446105 : - _theResult___fst_exp__h445589 ; - assign out_exp__h454690 = - _theResult___snd__h454196[34] ? - _theResult___exp__h454687 : - _theResult___fst_exp__h454245 ; - assign out_exp__h463874 = - sfdin__h463349[34] ? - _theResult___exp__h463871 : - _theResult___fst_exp__h463355 ; - assign out_exp__h472510 = - _theResult___snd__h471986[34] ? - _theResult___exp__h472507 : - _theResult___fst_exp__h472040 ; - assign out_exp__h502187 = - _theResult___snd__h501480[5] ? - _theResult___exp__h502184 : - _theResult___fst_exp__h501529 ; - assign out_exp__h511838 = - sfdin__h511100[5] ? - _theResult___exp__h511835 : - _theResult___fst_exp__h511106 ; - assign out_exp__h520622 = - _theResult___snd__h519885[5] ? - _theResult___exp__h520619 : - _theResult___fst_exp__h519939 ; - assign out_exp__h541040 = - _theResult___snd__h540333[5] ? - _theResult___exp__h541037 : - _theResult___fst_exp__h540382 ; - assign out_exp__h550691 = - sfdin__h549953[5] ? - _theResult___exp__h550688 : - _theResult___fst_exp__h549959 ; - assign out_exp__h559475 = - _theResult___snd__h558738[5] ? - _theResult___exp__h559472 : - _theResult___fst_exp__h558792 ; - assign out_exp__h580344 = - _theResult___snd__h579637[5] ? - _theResult___exp__h580341 : - _theResult___fst_exp__h579686 ; - assign out_exp__h589995 = - sfdin__h589257[5] ? - _theResult___exp__h589992 : - _theResult___fst_exp__h589263 ; - assign out_exp__h598779 = - _theResult___snd__h598042[5] ? - _theResult___exp__h598776 : - _theResult___fst_exp__h598096 ; - assign out_f_exp__h381494 = - (_theResult___exp__h381217 == 8'd255 && - _theResult___sfd__h381218 != 23'd0 || + assign out___1_sfd__h482206 = { f1_sfd__h482143, 29'd0 } ; + assign out___1_sfd__h521200 = { f2_sfd__h521137, 29'd0 } ; + assign out___1_sfd__h560504 = { f3_sfd__h560441, 29'd0 } ; + assign out_exp__h354717 = + sfdin__h354192[34] ? + _theResult___exp__h354714 : + _theResult___fst_exp__h354198 ; + assign out_exp__h363299 = + _theResult___snd__h362805[34] ? + _theResult___exp__h363296 : + _theResult___fst_exp__h362854 ; + assign out_exp__h372483 = + sfdin__h371958[34] ? + _theResult___exp__h372480 : + _theResult___fst_exp__h371964 ; + assign out_exp__h381119 = + _theResult___snd__h380595[34] ? + _theResult___exp__h381116 : + _theResult___fst_exp__h380649 ; + assign out_exp__h400414 = + sfdin__h399889[34] ? + _theResult___exp__h400411 : + _theResult___fst_exp__h399895 ; + assign out_exp__h408996 = + _theResult___snd__h408502[34] ? + _theResult___exp__h408993 : + _theResult___fst_exp__h408551 ; + assign out_exp__h418180 = + sfdin__h417655[34] ? + _theResult___exp__h418177 : + _theResult___fst_exp__h417661 ; + assign out_exp__h426816 = + _theResult___snd__h426292[34] ? + _theResult___exp__h426813 : + _theResult___fst_exp__h426346 ; + assign out_exp__h446109 = + sfdin__h445584[34] ? + _theResult___exp__h446106 : + _theResult___fst_exp__h445590 ; + assign out_exp__h454691 = + _theResult___snd__h454197[34] ? + _theResult___exp__h454688 : + _theResult___fst_exp__h454246 ; + assign out_exp__h463875 = + sfdin__h463350[34] ? + _theResult___exp__h463872 : + _theResult___fst_exp__h463356 ; + assign out_exp__h472511 = + _theResult___snd__h471987[34] ? + _theResult___exp__h472508 : + _theResult___fst_exp__h472041 ; + assign out_exp__h502188 = + _theResult___snd__h501481[5] ? + _theResult___exp__h502185 : + _theResult___fst_exp__h501530 ; + assign out_exp__h511839 = + sfdin__h511101[5] ? + _theResult___exp__h511836 : + _theResult___fst_exp__h511107 ; + assign out_exp__h520623 = + _theResult___snd__h519886[5] ? + _theResult___exp__h520620 : + _theResult___fst_exp__h519940 ; + assign out_exp__h541041 = + _theResult___snd__h540334[5] ? + _theResult___exp__h541038 : + _theResult___fst_exp__h540383 ; + assign out_exp__h550692 = + sfdin__h549954[5] ? + _theResult___exp__h550689 : + _theResult___fst_exp__h549960 ; + assign out_exp__h559476 = + _theResult___snd__h558739[5] ? + _theResult___exp__h559473 : + _theResult___fst_exp__h558793 ; + assign out_exp__h580345 = + _theResult___snd__h579638[5] ? + _theResult___exp__h580342 : + _theResult___fst_exp__h579687 ; + assign out_exp__h589996 = + sfdin__h589258[5] ? + _theResult___exp__h589993 : + _theResult___fst_exp__h589264 ; + assign out_exp__h598780 = + _theResult___snd__h598043[5] ? + _theResult___exp__h598777 : + _theResult___fst_exp__h598097 ; + assign out_f_exp__h381495 = + (_theResult___exp__h381218 == 8'd255 && + _theResult___sfd__h381219 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h381208 ; - assign out_f_exp__h427191 = - (_theResult___exp__h426914 == 8'd255 && - _theResult___sfd__h426915 != 23'd0 || + _theResult___fst_exp__h381209 ; + assign out_f_exp__h427192 = + (_theResult___exp__h426915 == 8'd255 && + _theResult___sfd__h426916 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h426905 ; - assign out_f_exp__h472886 = - (_theResult___exp__h472609 == 8'd255 && - _theResult___sfd__h472610 != 23'd0 || + _theResult___fst_exp__h426906 ; + assign out_f_exp__h472887 = + (_theResult___exp__h472610 == 8'd255 && + _theResult___sfd__h472611 != 23'd0 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] == 11'd2047) ? 8'd255 : - _theResult___fst_exp__h472600 ; - assign out_f_sfd__h381495 = - (_theResult___exp__h381217 == 8'd255 && - _theResult___sfd__h381218 != 23'd0) ? + _theResult___fst_exp__h472601 ; + assign out_f_sfd__h381496 = + (_theResult___exp__h381218 == 8'd255 && + _theResult___sfd__h381219 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h381218 ; - assign out_f_sfd__h427192 = - (_theResult___exp__h426914 == 8'd255 && - _theResult___sfd__h426915 != 23'd0) ? + _theResult___sfd__h381219 ; + assign out_f_sfd__h427193 = + (_theResult___exp__h426915 == 8'd255 && + _theResult___sfd__h426916 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h426915 ; - assign out_f_sfd__h472887 = - (_theResult___exp__h472609 == 8'd255 && - _theResult___sfd__h472610 != 23'd0) ? + _theResult___sfd__h426916 ; + assign out_f_sfd__h472888 = + (_theResult___exp__h472610 == 8'd255 && + _theResult___sfd__h472611 != 23'd0) ? 23'd4194304 : - _theResult___sfd__h472610 ; - assign out_sfd__h354717 = - sfdin__h354191[34] ? - _theResult___sfd__h354714 : - sfdin__h354191[56:34] ; - assign out_sfd__h363299 = - _theResult___snd__h362804[34] ? - _theResult___sfd__h363296 : - _theResult___snd__h362804[56:34] ; - assign out_sfd__h372483 = - sfdin__h371957[34] ? - _theResult___sfd__h372480 : - sfdin__h371957[56:34] ; - assign out_sfd__h381119 = - _theResult___snd__h380594[34] ? - _theResult___sfd__h381116 : - _theResult___snd__h380594[56:34] ; - assign out_sfd__h400414 = - sfdin__h399888[34] ? - _theResult___sfd__h400411 : - sfdin__h399888[56:34] ; - assign out_sfd__h408996 = - _theResult___snd__h408501[34] ? - _theResult___sfd__h408993 : - _theResult___snd__h408501[56:34] ; - assign out_sfd__h418180 = - sfdin__h417654[34] ? - _theResult___sfd__h418177 : - sfdin__h417654[56:34] ; - assign out_sfd__h426816 = - _theResult___snd__h426291[34] ? - _theResult___sfd__h426813 : - _theResult___snd__h426291[56:34] ; - assign out_sfd__h446109 = - sfdin__h445583[34] ? - _theResult___sfd__h446106 : - sfdin__h445583[56:34] ; - assign out_sfd__h454691 = - _theResult___snd__h454196[34] ? - _theResult___sfd__h454688 : - _theResult___snd__h454196[56:34] ; - assign out_sfd__h463875 = - sfdin__h463349[34] ? - _theResult___sfd__h463872 : - sfdin__h463349[56:34] ; - assign out_sfd__h472511 = - _theResult___snd__h471986[34] ? - _theResult___sfd__h472508 : - _theResult___snd__h471986[56:34] ; - assign out_sfd__h502188 = - _theResult___snd__h501480[5] ? - _theResult___sfd__h502185 : - _theResult___snd__h501480[56:5] ; - assign out_sfd__h511839 = - sfdin__h511100[5] ? - _theResult___sfd__h511836 : - sfdin__h511100[56:5] ; - assign out_sfd__h520623 = - _theResult___snd__h519885[5] ? - _theResult___sfd__h520620 : - _theResult___snd__h519885[56:5] ; - assign out_sfd__h541041 = - _theResult___snd__h540333[5] ? - _theResult___sfd__h541038 : - _theResult___snd__h540333[56:5] ; - assign out_sfd__h550692 = - sfdin__h549953[5] ? - _theResult___sfd__h550689 : - sfdin__h549953[56:5] ; - assign out_sfd__h559476 = - _theResult___snd__h558738[5] ? - _theResult___sfd__h559473 : - _theResult___snd__h558738[56:5] ; - assign out_sfd__h580345 = - _theResult___snd__h579637[5] ? - _theResult___sfd__h580342 : - _theResult___snd__h579637[56:5] ; - assign out_sfd__h589996 = - sfdin__h589257[5] ? - _theResult___sfd__h589993 : - sfdin__h589257[56:5] ; - assign out_sfd__h598780 = - _theResult___snd__h598042[5] ? - _theResult___sfd__h598777 : - _theResult___snd__h598042[56:5] ; - assign pc__h712387 = + _theResult___sfd__h472611 ; + assign out_sfd__h354718 = + sfdin__h354192[34] ? + _theResult___sfd__h354715 : + sfdin__h354192[56:34] ; + assign out_sfd__h363300 = + _theResult___snd__h362805[34] ? + _theResult___sfd__h363297 : + _theResult___snd__h362805[56:34] ; + assign out_sfd__h372484 = + sfdin__h371958[34] ? + _theResult___sfd__h372481 : + sfdin__h371958[56:34] ; + assign out_sfd__h381120 = + _theResult___snd__h380595[34] ? + _theResult___sfd__h381117 : + _theResult___snd__h380595[56:34] ; + assign out_sfd__h400415 = + sfdin__h399889[34] ? + _theResult___sfd__h400412 : + sfdin__h399889[56:34] ; + assign out_sfd__h408997 = + _theResult___snd__h408502[34] ? + _theResult___sfd__h408994 : + _theResult___snd__h408502[56:34] ; + assign out_sfd__h418181 = + sfdin__h417655[34] ? + _theResult___sfd__h418178 : + sfdin__h417655[56:34] ; + assign out_sfd__h426817 = + _theResult___snd__h426292[34] ? + _theResult___sfd__h426814 : + _theResult___snd__h426292[56:34] ; + assign out_sfd__h446110 = + sfdin__h445584[34] ? + _theResult___sfd__h446107 : + sfdin__h445584[56:34] ; + assign out_sfd__h454692 = + _theResult___snd__h454197[34] ? + _theResult___sfd__h454689 : + _theResult___snd__h454197[56:34] ; + assign out_sfd__h463876 = + sfdin__h463350[34] ? + _theResult___sfd__h463873 : + sfdin__h463350[56:34] ; + assign out_sfd__h472512 = + _theResult___snd__h471987[34] ? + _theResult___sfd__h472509 : + _theResult___snd__h471987[56:34] ; + assign out_sfd__h502189 = + _theResult___snd__h501481[5] ? + _theResult___sfd__h502186 : + _theResult___snd__h501481[56:5] ; + assign out_sfd__h511840 = + sfdin__h511101[5] ? + _theResult___sfd__h511837 : + sfdin__h511101[56:5] ; + assign out_sfd__h520624 = + _theResult___snd__h519886[5] ? + _theResult___sfd__h520621 : + _theResult___snd__h519886[56:5] ; + assign out_sfd__h541042 = + _theResult___snd__h540334[5] ? + _theResult___sfd__h541039 : + _theResult___snd__h540334[56:5] ; + assign out_sfd__h550693 = + sfdin__h549954[5] ? + _theResult___sfd__h550690 : + sfdin__h549954[56:5] ; + assign out_sfd__h559477 = + _theResult___snd__h558739[5] ? + _theResult___sfd__h559474 : + _theResult___snd__h558739[56:5] ; + assign out_sfd__h580346 = + _theResult___snd__h579638[5] ? + _theResult___sfd__h580343 : + _theResult___snd__h579638[56:5] ; + assign out_sfd__h589997 = + sfdin__h589258[5] ? + _theResult___sfd__h589994 : + sfdin__h589258[56:5] ; + assign out_sfd__h598781 = + _theResult___snd__h598043[5] ? + _theResult___sfd__h598778 : + _theResult___snd__h598043[56:5] ; + assign pc__h712388 = csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? - y_avValue_new_pc__h712179 : - y_avValue_new_pc__h712365 ; - assign pend_ints__h651116 = + y_avValue_new_pc__h712180 : + y_avValue_new_pc__h712366 ; + assign pend_ints__h651117 = { _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798, csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3, 1'd0, csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1, 1'd0 } ; - assign po_fflags__h727999 = old_fflags__h732774 ; - assign po_fflags__h730652 = - old_fflags__h732774 | rob$deqPort_1_deq_data[31:27] ; - assign prv__h734956 = csrf_prv_reg ; - assign prv__h735000 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; - assign q___1__h475882 = + assign po_fflags__h727870 = old_fflags__h732645 ; + assign po_fflags__h730523 = + old_fflags__h732645 | rob$deqPort_1_deq_data[31:27] ; + assign prv__h734827 = csrf_prv_reg ; + assign prv__h734871 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ; + assign q___1__h475883 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ; - assign r1__read_BITS_13_TO_0___h651665 = + assign r1__read_BITS_13_TO_0___h651666 = { 4'd0, csrf_mideleg_11_reg, 1'b0, @@ -30989,116 +30989,116 @@ module mkCore(CLK, 1'b0, csrf_mideleg_5_3_reg, 1'b0 } ; - assign r1__read_BITS_13_TO_12___h655197 = csrf_fs_reg ; - assign r1__read_BITS_62_TO_14___h729677 = { r1__read__h614245, 2'd0 } ; - assign r1__read_BIT_20___h655893 = csrf_tw_reg ; - assign r1__read__h613050 = { r1__read__h613052, csrf_ie_vec_1 } ; - assign r1__read__h613052 = { r1__read__h613054, 2'b0 } ; - assign r1__read__h613054 = { r1__read__h613056, csrf_prev_ie_vec_0 } ; - assign r1__read__h613056 = { r1__read__h613058, csrf_prev_ie_vec_1 } ; - assign r1__read__h613058 = { r1__read__h613060, 2'b0 } ; - assign r1__read__h613060 = { r1__read__h613062, csrf_spp_reg } ; - assign r1__read__h613062 = { r1__read__h613064, 4'b0 } ; - assign r1__read__h613064 = { r1__read__h613066, csrf_fs_reg } ; - assign r1__read__h613066 = { r1__read__h613068, 2'd0 } ; - assign r1__read__h613068 = { r1__read__h613070, 1'b0 } ; - assign r1__read__h613070 = { r1__read__h613072, csrf_sum_reg } ; - assign r1__read__h613072 = { r1__read__h613074, csrf_mxr_reg } ; - assign r1__read__h613074 = { r1__read__h613076, 12'b0 } ; - assign r1__read__h613076 = { r1__read__h613078, 2'b10 } ; - assign r1__read__h613078 = { csrf_fs_reg == 2'b11, 29'b0 } ; - assign r1__read__h613454 = - { r1__read__h613456, csrf_software_int_en_vec_1 } ; - assign r1__read__h613456 = { r1__read__h613458, 2'b0 } ; - assign r1__read__h613458 = { r1__read__h613460, 1'b0 } ; - assign r1__read__h613460 = { r1__read__h613462, csrf_timer_int_en_vec_1 } ; - assign r1__read__h613462 = { r1__read__h613464, 2'b0 } ; - assign r1__read__h613464 = { r1__read__h613466, 1'b0 } ; - assign r1__read__h613466 = { 54'b0, csrf_external_int_en_vec_1 } ; - assign r1__read__h613964 = { csrf_stvec_base_hi_reg, 1'b0 } ; - assign r1__read__h613969 = { r1__read__h613971, csrf_scounteren_tm_reg } ; - assign r1__read__h613971 = { 61'd0, csrf_scounteren_ir_reg } ; - assign r1__read__h613982 = { csrf_scause_interrupt_reg, 59'b0 } ; - assign r1__read__h613988 = - { r1__read__h613990, csrf_software_int_pend_vec_1 } ; - assign r1__read__h613990 = { r1__read__h613992, 2'b0 } ; - assign r1__read__h613992 = { r1__read__h613994, 1'b0 } ; - assign r1__read__h613994 = - { r1__read__h613996, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h613996 = { r1__read__h613998, 2'b0 } ; - assign r1__read__h613998 = { r1__read__h614000, 1'b0 } ; - assign r1__read__h614000 = { 54'b0, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614198 = { vm_mode_reg__read__h614204, 16'd0 } ; - assign r1__read__h614221 = { r1__read__h614223, csrf_ie_vec_1 } ; - assign r1__read__h614223 = { r1__read__h614225, 1'b0 } ; - assign r1__read__h614225 = { r1__read__h614227, csrf_ie_vec_3 } ; - assign r1__read__h614227 = { r1__read__h614229, csrf_prev_ie_vec_0 } ; - assign r1__read__h614229 = { r1__read__h614231, csrf_prev_ie_vec_1 } ; - assign r1__read__h614231 = { r1__read__h614233, 1'b0 } ; - assign r1__read__h614233 = { r1__read__h614235, csrf_prev_ie_vec_3 } ; - assign r1__read__h614235 = { r1__read__h614237, csrf_spp_reg } ; - assign r1__read__h614237 = { r1__read__h614239, 2'b0 } ; - assign r1__read__h614239 = { r1__read__h614241, csrf_mpp_reg } ; - assign r1__read__h614241 = - { r1__read_BITS_62_TO_14___h729677, csrf_fs_reg } ; - assign r1__read__h614245 = { r1__read__h614247, csrf_mprv_reg } ; - assign r1__read__h614247 = { r1__read__h614249, csrf_sum_reg } ; - assign r1__read__h614249 = { r1__read__h614251, csrf_mxr_reg } ; - assign r1__read__h614251 = { r1__read__h614253, csrf_tvm_reg } ; - assign r1__read__h614253 = { r1__read__h614255, csrf_tw_reg } ; - assign r1__read__h614255 = { r1__read__h614257, csrf_tsr_reg } ; - assign r1__read__h614257 = { r1__read__h614259, 9'b0 } ; - assign r1__read__h614259 = { r1__read__h614261, 2'b10 } ; - assign r1__read__h614261 = { r1__read__h614263, 2'b10 } ; - assign r1__read__h614263 = { csrf_fs_reg == 2'b11, 27'b0 } ; - assign r1__read__h614346 = { r1__read__h614348, 1'b0 } ; - assign r1__read__h614348 = { r1__read__h614350, csrf_medeleg_13_11_reg } ; - assign r1__read__h614350 = { r1__read__h614352, 1'b0 } ; - assign r1__read__h614352 = { 48'b0, csrf_medeleg_15_reg } ; - assign r1__read__h614363 = { r1__read__h614365, 1'b0 } ; - assign r1__read__h614365 = { r1__read__h614367, csrf_mideleg_5_3_reg } ; - assign r1__read__h614367 = { r1__read__h614369, 1'b0 } ; - assign r1__read__h614369 = { r1__read__h614371, csrf_mideleg_9_7_reg } ; - assign r1__read__h614371 = { r1__read__h614373, 1'b0 } ; - assign r1__read__h614373 = { 52'b0, csrf_mideleg_11_reg } ; - assign r1__read__h614387 = - { r1__read__h614389, csrf_software_int_en_vec_1 } ; - assign r1__read__h614389 = { r1__read__h614391, 1'b0 } ; - assign r1__read__h614391 = - { r1__read__h614393, csrf_software_int_en_vec_3 } ; - assign r1__read__h614393 = { r1__read__h614395, 1'b0 } ; - assign r1__read__h614395 = { r1__read__h614397, csrf_timer_int_en_vec_1 } ; - assign r1__read__h614397 = { r1__read__h614399, 1'b0 } ; - assign r1__read__h614399 = { r1__read__h614401, csrf_timer_int_en_vec_3 } ; - assign r1__read__h614401 = { r1__read__h614403, 1'b0 } ; - assign r1__read__h614403 = - { r1__read__h614405, csrf_external_int_en_vec_1 } ; - assign r1__read__h614405 = { r1__read__h614407, 1'b0 } ; - assign r1__read__h614407 = { 52'b0, csrf_external_int_en_vec_3 } ; - assign r1__read__h614480 = { csrf_mtvec_base_hi_reg, 1'b0 } ; - assign r1__read__h614485 = { r1__read__h614487, csrf_mcounteren_tm_reg } ; - assign r1__read__h614487 = { 61'd0, csrf_mcounteren_ir_reg } ; - assign r1__read__h614498 = { csrf_mcause_interrupt_reg, 59'b0 } ; - assign r1__read__h614504 = - { r1__read__h614506, csrf_software_int_pend_vec_1 } ; - assign r1__read__h614506 = { r1__read__h614508, 1'b0 } ; - assign r1__read__h614508 = - { r1__read__h614510, csrf_software_int_pend_vec_3 } ; - assign r1__read__h614510 = { r1__read__h614512, 1'b0 } ; - assign r1__read__h614512 = - { r1__read__h614514, csrf_timer_int_pend_vec_1 } ; - assign r1__read__h614514 = { r1__read__h614516, 1'b0 } ; - assign r1__read__h614516 = - { r1__read__h614518, csrf_timer_int_pend_vec_3 } ; - assign r1__read__h614518 = { r1__read__h614520, 1'b0 } ; - assign r1__read__h614520 = - { r1__read__h614522, csrf_external_int_pend_vec_1 } ; - assign r1__read__h614522 = { r1__read__h614524, 1'b0 } ; - assign r1__read__h614524 = { 52'b0, csrf_external_int_pend_vec_3 } ; - assign r1__read__h614601 = { 4'd0, csrf_rg_tdata1_dmode } ; - assign rVal1__h481762 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; - assign rVal2__h481763 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; - assign r___1__h475908 = + assign r1__read_BITS_13_TO_12___h655198 = csrf_fs_reg ; + assign r1__read_BITS_62_TO_14___h729548 = { r1__read__h614246, 2'd0 } ; + assign r1__read_BIT_20___h655894 = csrf_tw_reg ; + assign r1__read__h613051 = { r1__read__h613053, csrf_ie_vec_1 } ; + assign r1__read__h613053 = { r1__read__h613055, 2'b0 } ; + assign r1__read__h613055 = { r1__read__h613057, csrf_prev_ie_vec_0 } ; + assign r1__read__h613057 = { r1__read__h613059, csrf_prev_ie_vec_1 } ; + assign r1__read__h613059 = { r1__read__h613061, 2'b0 } ; + assign r1__read__h613061 = { r1__read__h613063, csrf_spp_reg } ; + assign r1__read__h613063 = { r1__read__h613065, 4'b0 } ; + assign r1__read__h613065 = { r1__read__h613067, csrf_fs_reg } ; + assign r1__read__h613067 = { r1__read__h613069, 2'd0 } ; + assign r1__read__h613069 = { r1__read__h613071, 1'b0 } ; + assign r1__read__h613071 = { r1__read__h613073, csrf_sum_reg } ; + assign r1__read__h613073 = { r1__read__h613075, csrf_mxr_reg } ; + assign r1__read__h613075 = { r1__read__h613077, 12'b0 } ; + assign r1__read__h613077 = { r1__read__h613079, 2'b10 } ; + assign r1__read__h613079 = { csrf_fs_reg == 2'b11, 29'b0 } ; + assign r1__read__h613455 = + { r1__read__h613457, csrf_software_int_en_vec_1 } ; + assign r1__read__h613457 = { r1__read__h613459, 2'b0 } ; + assign r1__read__h613459 = { r1__read__h613461, 1'b0 } ; + assign r1__read__h613461 = { r1__read__h613463, csrf_timer_int_en_vec_1 } ; + assign r1__read__h613463 = { r1__read__h613465, 2'b0 } ; + assign r1__read__h613465 = { r1__read__h613467, 1'b0 } ; + assign r1__read__h613467 = { 54'b0, csrf_external_int_en_vec_1 } ; + assign r1__read__h613965 = { csrf_stvec_base_hi_reg, 1'b0 } ; + assign r1__read__h613970 = { r1__read__h613972, csrf_scounteren_tm_reg } ; + assign r1__read__h613972 = { 61'd0, csrf_scounteren_ir_reg } ; + assign r1__read__h613983 = { csrf_scause_interrupt_reg, 59'b0 } ; + assign r1__read__h613989 = + { r1__read__h613991, csrf_software_int_pend_vec_1 } ; + assign r1__read__h613991 = { r1__read__h613993, 2'b0 } ; + assign r1__read__h613993 = { r1__read__h613995, 1'b0 } ; + assign r1__read__h613995 = + { r1__read__h613997, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h613997 = { r1__read__h613999, 2'b0 } ; + assign r1__read__h613999 = { r1__read__h614001, 1'b0 } ; + assign r1__read__h614001 = { 54'b0, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614199 = { vm_mode_reg__read__h614205, 16'd0 } ; + assign r1__read__h614222 = { r1__read__h614224, csrf_ie_vec_1 } ; + assign r1__read__h614224 = { r1__read__h614226, 1'b0 } ; + assign r1__read__h614226 = { r1__read__h614228, csrf_ie_vec_3 } ; + assign r1__read__h614228 = { r1__read__h614230, csrf_prev_ie_vec_0 } ; + assign r1__read__h614230 = { r1__read__h614232, csrf_prev_ie_vec_1 } ; + assign r1__read__h614232 = { r1__read__h614234, 1'b0 } ; + assign r1__read__h614234 = { r1__read__h614236, csrf_prev_ie_vec_3 } ; + assign r1__read__h614236 = { r1__read__h614238, csrf_spp_reg } ; + assign r1__read__h614238 = { r1__read__h614240, 2'b0 } ; + assign r1__read__h614240 = { r1__read__h614242, csrf_mpp_reg } ; + assign r1__read__h614242 = + { r1__read_BITS_62_TO_14___h729548, csrf_fs_reg } ; + assign r1__read__h614246 = { r1__read__h614248, csrf_mprv_reg } ; + assign r1__read__h614248 = { r1__read__h614250, csrf_sum_reg } ; + assign r1__read__h614250 = { r1__read__h614252, csrf_mxr_reg } ; + assign r1__read__h614252 = { r1__read__h614254, csrf_tvm_reg } ; + assign r1__read__h614254 = { r1__read__h614256, csrf_tw_reg } ; + assign r1__read__h614256 = { r1__read__h614258, csrf_tsr_reg } ; + assign r1__read__h614258 = { r1__read__h614260, 9'b0 } ; + assign r1__read__h614260 = { r1__read__h614262, 2'b10 } ; + assign r1__read__h614262 = { r1__read__h614264, 2'b10 } ; + assign r1__read__h614264 = { csrf_fs_reg == 2'b11, 27'b0 } ; + assign r1__read__h614347 = { r1__read__h614349, 1'b0 } ; + assign r1__read__h614349 = { r1__read__h614351, csrf_medeleg_13_11_reg } ; + assign r1__read__h614351 = { r1__read__h614353, 1'b0 } ; + assign r1__read__h614353 = { 48'b0, csrf_medeleg_15_reg } ; + assign r1__read__h614364 = { r1__read__h614366, 1'b0 } ; + assign r1__read__h614366 = { r1__read__h614368, csrf_mideleg_5_3_reg } ; + assign r1__read__h614368 = { r1__read__h614370, 1'b0 } ; + assign r1__read__h614370 = { r1__read__h614372, csrf_mideleg_9_7_reg } ; + assign r1__read__h614372 = { r1__read__h614374, 1'b0 } ; + assign r1__read__h614374 = { 52'b0, csrf_mideleg_11_reg } ; + assign r1__read__h614388 = + { r1__read__h614390, csrf_software_int_en_vec_1 } ; + assign r1__read__h614390 = { r1__read__h614392, 1'b0 } ; + assign r1__read__h614392 = + { r1__read__h614394, csrf_software_int_en_vec_3 } ; + assign r1__read__h614394 = { r1__read__h614396, 1'b0 } ; + assign r1__read__h614396 = { r1__read__h614398, csrf_timer_int_en_vec_1 } ; + assign r1__read__h614398 = { r1__read__h614400, 1'b0 } ; + assign r1__read__h614400 = { r1__read__h614402, csrf_timer_int_en_vec_3 } ; + assign r1__read__h614402 = { r1__read__h614404, 1'b0 } ; + assign r1__read__h614404 = + { r1__read__h614406, csrf_external_int_en_vec_1 } ; + assign r1__read__h614406 = { r1__read__h614408, 1'b0 } ; + assign r1__read__h614408 = { 52'b0, csrf_external_int_en_vec_3 } ; + assign r1__read__h614481 = { csrf_mtvec_base_hi_reg, 1'b0 } ; + assign r1__read__h614486 = { r1__read__h614488, csrf_mcounteren_tm_reg } ; + assign r1__read__h614488 = { 61'd0, csrf_mcounteren_ir_reg } ; + assign r1__read__h614499 = { csrf_mcause_interrupt_reg, 59'b0 } ; + assign r1__read__h614505 = + { r1__read__h614507, csrf_software_int_pend_vec_1 } ; + assign r1__read__h614507 = { r1__read__h614509, 1'b0 } ; + assign r1__read__h614509 = + { r1__read__h614511, csrf_software_int_pend_vec_3 } ; + assign r1__read__h614511 = { r1__read__h614513, 1'b0 } ; + assign r1__read__h614513 = + { r1__read__h614515, csrf_timer_int_pend_vec_1 } ; + assign r1__read__h614515 = { r1__read__h614517, 1'b0 } ; + assign r1__read__h614517 = + { r1__read__h614519, csrf_timer_int_pend_vec_3 } ; + assign r1__read__h614519 = { r1__read__h614521, 1'b0 } ; + assign r1__read__h614521 = + { r1__read__h614523, csrf_external_int_pend_vec_1 } ; + assign r1__read__h614523 = { r1__read__h614525, 1'b0 } ; + assign r1__read__h614525 = { 52'b0, csrf_external_int_pend_vec_3 } ; + assign r1__read__h614602 = { 4'd0, csrf_rg_tdata1_dmode } ; + assign rVal1__h481763 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ; + assign rVal2__h481764 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ; + assign r___1__h475909 = 64'd0 - coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ; assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13309 = @@ -31319,12 +31319,12 @@ module mkCore(CLK, fetchStage$pipelines_0_first[68] || checkForException___d13008[4] || !rob$enqPort_0_canEnq ; - assign renaming_spec_bits__h685239 = + assign renaming_spec_bits__h685240 = fetchStage$pipelines_0_canDeq ? - y_avValue_fst__h681634 : + y_avValue_fst__h681635 : specTagManager$currentSpecBits ; - assign res_data__h337870 = { 32'hFFFFFFFF, x__h337885 } ; - assign res_data__h337875 = + assign res_data__h337871 = { 32'hFFFFFFFF, x__h337886 } ; + assign res_data__h337876 = { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] == @@ -31337,8 +31337,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ; - assign res_data__h383572 = { 32'hFFFFFFFF, x__h383587 } ; - assign res_data__h383577 = + assign res_data__h383573 = { 32'hFFFFFFFF, x__h383588 } ; + assign res_data__h383578 = { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] == @@ -31351,8 +31351,8 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ; - assign res_data__h429267 = { 32'hFFFFFFFF, x__h429282 } ; - assign res_data__h429272 = + assign res_data__h429268 = { 32'hFFFFFFFF, x__h429283 } ; + assign res_data__h429273 = { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd2047 || coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] == @@ -31365,7 +31365,7 @@ module mkCore(CLK, 52'd0) ? 63'h7FF8000000000000 : coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ; - assign res_fflags__h337871 = + assign res_fflags__h337872 = coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != @@ -31433,7 +31433,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 } ; - assign res_fflags__h383573 = + assign res_fflags__h383574 = coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != @@ -31501,7 +31501,7 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 } ; - assign res_fflags__h429268 = + assign res_fflags__h429269 = coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] | coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] | { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != @@ -31569,43 +31569,43 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] != 52'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 } ; - assign resp_addr__h291972 = + assign resp_addr__h291973 = { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ; - assign result__h364338 = + assign result__h364339 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[0] | - guard__h364333 } ; - assign result__h410035 = + guard__h364334 } ; + assign result__h410036 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[0] | - guard__h410030 } ; - assign result__h455730 = + guard__h410031 } ; + assign result__h455731 = { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[56:1], _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[0] | - guard__h455725 } ; - assign result__h503483 = + guard__h455726 } ; + assign result__h503484 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[0] | - guard__h503478 } ; - assign result__h542336 = + guard__h503479 } ; + assign result__h542337 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[0] | - guard__h542331 } ; - assign result__h581640 = + guard__h542332 } ; + assign result__h581641 = { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[56:1], _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[0] | - guard__h581635 } ; - assign result__h646695 = w__h646690 & y__h646724 ; - assign result__h646746 = ~x__h646745 ; + guard__h581636 } ; + assign result__h646696 = w__h646691 & y__h646725 ; + assign result__h646747 = ~x__h646746 ; assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15735 = rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs && !update_vm_info && fetchStage$iTlbIfc_flush_done && coreFix_memExe_dTlb$flush_done && !flush_caches ; - assign rg_tdata1__read__h612207 = - { r1__read__h614601, csrf_rg_tdata1_data } ; + assign rg_tdata1__read__h612208 = + { r1__read__h614602, csrf_rg_tdata1_data } ; assign rob_RDY_deqPort_0_deq__4336_AND_rob_RDY_deqPor_ETC___d14998 = rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data && regRenamingTable$RDY_commit_0_commit && @@ -31623,14 +31623,14 @@ module mkCore(CLK, { 2'd1, rob$deqPort_0_deq_data[95:32] } : { 2'd2, (rob$deqPort_0_deq_data[329:325] == 5'd13) ? - data_warl_xformed__h722429 : + data_warl_xformed__h722430 : rob$deqPort_0_deq_data[95:32] }), 5'h0A, rob$deqPort_0_deq_data[26], 64'hAAAAAAAAAAAAAAAA, - x_prv__h723013, + x_prv__h723014, 64'hAAAAAAAAAAAAAAAA, - x__h726188, + x__h726059, 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; assign rob_deqPort_0_deq_data__4339_BIT_166_4355_CONC_ETC___d14404 = { rob$deqPort_0_deq_data[166], @@ -31642,12 +31642,12 @@ module mkCore(CLK, CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ; assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 = rob$deqPort_0_deq_data[95:32] ; - assign rs1__h655328 = + assign rs1__h655329 = (fetchStage$pipelines_0_first[88] && !fetchStage$pipelines_0_first[87]) ? fetchStage$pipelines_0_first[86:82] : 5'd0 ; - assign satp_csr__read__h610080 = { r1__read__h614198, csrf_ppn_reg } ; + assign satp_csr__read__h610081 = { r1__read__h614199, csrf_ppn_reg } ; assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 = (sbCons$lazyLookup_2_get[2] || IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 && @@ -31667,432 +31667,432 @@ module mkCore(CLK, (sbCons$lazyLookup_3_get[2] || IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 && IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629) ; - assign sbIdx__h157152 = + assign sbIdx__h157153 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] : coreFix_memExe_reqStQ_data_0_rl[65:64]) : 2'd0 ; - assign scause_csr__read__h609877 = - { r1__read__h613982, csrf_scause_code_reg } ; - assign scounteren_csr__read__h609739 = - { r1__read__h613969, csrf_scounteren_cy_reg } ; - assign sfd__h338481 = { value__h346708, 3'd0 } ; - assign sfd__h354289 = + assign scause_csr__read__h609878 = + { r1__read__h613983, csrf_scause_code_reg } ; + assign scounteren_csr__read__h609740 = + { r1__read__h613970, csrf_scounteren_cy_reg } ; + assign sfd__h338482 = { value__h346709, 3'd0 } ; + assign sfd__h354290 = { 1'b0, - _theResult___fst_exp__h354197 != 8'd0, - sfdin__h354191[56:34] } + + _theResult___fst_exp__h354198 != 8'd0, + sfdin__h354192[56:34] } + 25'd1 ; - assign sfd__h362871 = + assign sfd__h362872 = { 1'b0, - _theResult___fst_exp__h362853 != 8'd0, - _theResult___snd__h362804[56:34] } + + _theResult___fst_exp__h362854 != 8'd0, + _theResult___snd__h362805[56:34] } + 25'd1 ; - assign sfd__h372055 = + assign sfd__h372056 = { 1'b0, - _theResult___fst_exp__h371963 != 8'd0, - sfdin__h371957[56:34] } + + _theResult___fst_exp__h371964 != 8'd0, + sfdin__h371958[56:34] } + 25'd1 ; - assign sfd__h380667 = + assign sfd__h380668 = { 1'b0, - _theResult___fst_exp__h380648 != 8'd0, - _theResult___snd__h380594[56:34] } + + _theResult___fst_exp__h380649 != 8'd0, + _theResult___snd__h380595[56:34] } + 25'd1 ; - assign sfd__h384183 = { value__h392405, 3'd0 } ; - assign sfd__h399986 = + assign sfd__h384184 = { value__h392406, 3'd0 } ; + assign sfd__h399987 = { 1'b0, - _theResult___fst_exp__h399894 != 8'd0, - sfdin__h399888[56:34] } + + _theResult___fst_exp__h399895 != 8'd0, + sfdin__h399889[56:34] } + 25'd1 ; - assign sfd__h408568 = + assign sfd__h408569 = { 1'b0, - _theResult___fst_exp__h408550 != 8'd0, - _theResult___snd__h408501[56:34] } + + _theResult___fst_exp__h408551 != 8'd0, + _theResult___snd__h408502[56:34] } + 25'd1 ; - assign sfd__h417752 = + assign sfd__h417753 = { 1'b0, - _theResult___fst_exp__h417660 != 8'd0, - sfdin__h417654[56:34] } + + _theResult___fst_exp__h417661 != 8'd0, + sfdin__h417655[56:34] } + 25'd1 ; - assign sfd__h426364 = + assign sfd__h426365 = { 1'b0, - _theResult___fst_exp__h426345 != 8'd0, - _theResult___snd__h426291[56:34] } + + _theResult___fst_exp__h426346 != 8'd0, + _theResult___snd__h426292[56:34] } + 25'd1 ; - assign sfd__h429878 = { value__h438100, 3'd0 } ; - assign sfd__h445681 = + assign sfd__h429879 = { value__h438101, 3'd0 } ; + assign sfd__h445682 = { 1'b0, - _theResult___fst_exp__h445589 != 8'd0, - sfdin__h445583[56:34] } + + _theResult___fst_exp__h445590 != 8'd0, + sfdin__h445584[56:34] } + 25'd1 ; - assign sfd__h454263 = + assign sfd__h454264 = { 1'b0, - _theResult___fst_exp__h454245 != 8'd0, - _theResult___snd__h454196[56:34] } + + _theResult___fst_exp__h454246 != 8'd0, + _theResult___snd__h454197[56:34] } + 25'd1 ; - assign sfd__h463447 = + assign sfd__h463448 = { 1'b0, - _theResult___fst_exp__h463355 != 8'd0, - sfdin__h463349[56:34] } + + _theResult___fst_exp__h463356 != 8'd0, + sfdin__h463350[56:34] } + 25'd1 ; - assign sfd__h472059 = + assign sfd__h472060 = { 1'b0, - _theResult___fst_exp__h472040 != 8'd0, - _theResult___snd__h471986[56:34] } + + _theResult___fst_exp__h472041 != 8'd0, + _theResult___snd__h471987[56:34] } + 25'd1 ; - assign sfd__h482503 = { value__h487086, 32'd0 } ; - assign sfd__h501547 = + assign sfd__h482504 = { value__h487087, 32'd0 } ; + assign sfd__h501548 = { 1'b0, - _theResult___fst_exp__h501529 != 11'd0, - _theResult___snd__h501480[56:5] } + + _theResult___fst_exp__h501530 != 11'd0, + _theResult___snd__h501481[56:5] } + 54'd1 ; - assign sfd__h511198 = + assign sfd__h511199 = { 1'b0, - _theResult___fst_exp__h511106 != 11'd0, - sfdin__h511100[56:5] } + + _theResult___fst_exp__h511107 != 11'd0, + sfdin__h511101[56:5] } + 54'd1 ; - assign sfd__h519958 = + assign sfd__h519959 = { 1'b0, - _theResult___fst_exp__h519939 != 11'd0, - _theResult___snd__h519885[56:5] } + + _theResult___fst_exp__h519940 != 11'd0, + _theResult___snd__h519886[56:5] } + 54'd1 ; - assign sfd__h521497 = { value__h525939, 32'd0 } ; - assign sfd__h540400 = + assign sfd__h521498 = { value__h525940, 32'd0 } ; + assign sfd__h540401 = { 1'b0, - _theResult___fst_exp__h540382 != 11'd0, - _theResult___snd__h540333[56:5] } + + _theResult___fst_exp__h540383 != 11'd0, + _theResult___snd__h540334[56:5] } + 54'd1 ; - assign sfd__h550051 = + assign sfd__h550052 = { 1'b0, - _theResult___fst_exp__h549959 != 11'd0, - sfdin__h549953[56:5] } + + _theResult___fst_exp__h549960 != 11'd0, + sfdin__h549954[56:5] } + 54'd1 ; - assign sfd__h558811 = + assign sfd__h558812 = { 1'b0, - _theResult___fst_exp__h558792 != 11'd0, - _theResult___snd__h558738[56:5] } + + _theResult___fst_exp__h558793 != 11'd0, + _theResult___snd__h558739[56:5] } + 54'd1 ; - assign sfd__h560801 = { value__h565243, 32'd0 } ; - assign sfd__h579704 = + assign sfd__h560802 = { value__h565244, 32'd0 } ; + assign sfd__h579705 = { 1'b0, - _theResult___fst_exp__h579686 != 11'd0, - _theResult___snd__h579637[56:5] } + + _theResult___fst_exp__h579687 != 11'd0, + _theResult___snd__h579638[56:5] } + 54'd1 ; - assign sfd__h589355 = + assign sfd__h589356 = { 1'b0, - _theResult___fst_exp__h589263 != 11'd0, - sfdin__h589257[56:5] } + + _theResult___fst_exp__h589264 != 11'd0, + sfdin__h589258[56:5] } + 54'd1 ; - assign sfd__h598115 = + assign sfd__h598116 = { 1'b0, - _theResult___fst_exp__h598096 != 11'd0, - _theResult___snd__h598042[56:5] } + + _theResult___fst_exp__h598097 != 11'd0, + _theResult___snd__h598043[56:5] } + 54'd1 ; - assign sfdin__h354191 = - _theResult____h346086[56] ? - _theResult___snd__h354208 : - _theResult___snd__h354219 ; - assign sfdin__h371957 = - _theResult____h363725[56] ? - _theResult___snd__h371974 : - _theResult___snd__h371985 ; - assign sfdin__h399888 = - _theResult____h391785[56] ? - _theResult___snd__h399905 : - _theResult___snd__h399916 ; - assign sfdin__h417654 = - _theResult____h409422[56] ? - _theResult___snd__h417671 : - _theResult___snd__h417682 ; - assign sfdin__h445583 = - _theResult____h437480[56] ? - _theResult___snd__h445600 : - _theResult___snd__h445611 ; - assign sfdin__h463349 = - _theResult____h455117[56] ? - _theResult___snd__h463366 : - _theResult___snd__h463377 ; - assign sfdin__h511100 = - _theResult____h502870[56] ? - _theResult___snd__h511117 : - _theResult___snd__h511128 ; - assign sfdin__h549953 = - _theResult____h541723[56] ? - _theResult___snd__h549970 : - _theResult___snd__h549981 ; - assign sfdin__h589257 = - _theResult____h581027[56] ? - _theResult___snd__h589274 : - _theResult___snd__h589285 ; - assign shiftData__h181568 = - coreFix_memExe_regToExeQ$first[75:12] << x__h181700 ; - assign sie_csr__read__h609643 = { r1__read__h613454, 1'b0 } ; - assign sip_csr__read__h610017 = { r1__read__h613988, 1'b0 } ; - assign spec_bits__h688398 = specTagManager$currentSpecBits | y__h688411 ; - assign sstatus_csr__read__h609573 = { r1__read__h613050, csrf_ie_vec_0 } ; - assign stvec_csr__read__h609686 = - { r1__read__h613964, csrf_stvec_mode_low_reg } ; - assign trap_val__h709444 = - commitStage_commitTrap[36] ? 64'd0 : trap_val__h710482 ; - assign tsr_val__h726308 = csrf_tsr_reg ; - assign tvm_val__h726310 = csrf_tvm_reg ; + assign sfdin__h354192 = + _theResult____h346087[56] ? + _theResult___snd__h354209 : + _theResult___snd__h354220 ; + assign sfdin__h371958 = + _theResult____h363726[56] ? + _theResult___snd__h371975 : + _theResult___snd__h371986 ; + assign sfdin__h399889 = + _theResult____h391786[56] ? + _theResult___snd__h399906 : + _theResult___snd__h399917 ; + assign sfdin__h417655 = + _theResult____h409423[56] ? + _theResult___snd__h417672 : + _theResult___snd__h417683 ; + assign sfdin__h445584 = + _theResult____h437481[56] ? + _theResult___snd__h445601 : + _theResult___snd__h445612 ; + assign sfdin__h463350 = + _theResult____h455118[56] ? + _theResult___snd__h463367 : + _theResult___snd__h463378 ; + assign sfdin__h511101 = + _theResult____h502871[56] ? + _theResult___snd__h511118 : + _theResult___snd__h511129 ; + assign sfdin__h549954 = + _theResult____h541724[56] ? + _theResult___snd__h549971 : + _theResult___snd__h549982 ; + assign sfdin__h589258 = + _theResult____h581028[56] ? + _theResult___snd__h589275 : + _theResult___snd__h589286 ; + assign shiftData__h181569 = + coreFix_memExe_regToExeQ$first[75:12] << x__h181701 ; + assign sie_csr__read__h609644 = { r1__read__h613455, 1'b0 } ; + assign sip_csr__read__h610018 = { r1__read__h613989, 1'b0 } ; + assign spec_bits__h688399 = specTagManager$currentSpecBits | y__h688412 ; + assign sstatus_csr__read__h609574 = { r1__read__h613051, csrf_ie_vec_0 } ; + assign stvec_csr__read__h609687 = + { r1__read__h613965, csrf_stvec_mode_low_reg } ; + assign trap_val__h709445 = + commitStage_commitTrap[36] ? 64'd0 : trap_val__h710483 ; + assign tsr_val__h726179 = csrf_tsr_reg ; + assign tvm_val__h726181 = csrf_tvm_reg ; assign upd__h3994 = WILL_FIRE_RL_commitStage_doCommitSystemInst ? MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 : MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ; - assign upd__h5311 = n__read__h6760 + 64'd1 ; - assign upd__h6874 = + assign upd__h5311 = n__read__h6761 + 64'd1 ; + assign upd__h6875 = MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign upd__h726805 = + assign upd__h726676 = MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ? f_csr_reqs$D_OUT[63:0] : rob$deqPort_0_deq_data[95:32] ; - assign v__h295942 = + assign v__h295943 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031) ? - v__h296173 : + v__h296174 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ; - assign v__h296173 = + assign v__h296174 = (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP == 3'd7) ? 3'd0 : coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP + 3'd1 ; - assign v__h299287 = + assign v__h299288 = (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138) ? - v__h299805 : + v__h299806 : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ; - assign v__h299805 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; - assign v__h309801 = + assign v__h299806 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ; + assign v__h309802 = (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309) ? - v__h310032 : + v__h310033 : coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ; - assign v__h310032 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; - assign v__h313677 = + assign v__h310033 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ; + assign v__h313678 = (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405) ? - v__h313908 : + v__h313909 : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ; - assign v__h313908 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; - assign v__h328278 = + assign v__h313909 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ; + assign v__h328279 = (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634) ? - v__h328509 : + v__h328510 : coreFix_memExe_memRespLdQ_enqP ; - assign v__h328509 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; - assign v__h331503 = + assign v__h328510 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ; + assign v__h331504 = (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT && IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728) ? - v__h331734 : + v__h331735 : coreFix_memExe_forwardQ_enqP ; - assign v__h331734 = coreFix_memExe_forwardQ_enqP + 1'd1 ; - assign v__h603884 = + assign v__h331735 = coreFix_memExe_forwardQ_enqP + 1'd1 ; + assign v__h603885 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ? - v__h603894 : + v__h603895 : coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ; - assign v__h603894 = + assign v__h603895 = coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ; - assign v__h604529 = v__h603884 - 2'd1 ; - assign v__h607935 = - sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608841 ; - assign v__h632818 = - sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633571 ; - assign value__h346708 = + assign v__h604530 = v__h603885 - 2'd1 ; + assign v__h607936 = + sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608842 ; + assign v__h632819 = + sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633572 ; + assign value__h346709 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ; - assign value__h392405 = + assign value__h392406 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ; - assign value__h438100 = + assign value__h438101 = { 1'b0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] != 11'd0, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ; - assign value__h487086 = { 1'b0, f1_exp__h482141 != 8'd0, f1_sfd__h482142 } ; - assign value__h525939 = { 1'b0, f2_exp__h521135 != 8'd0, f2_sfd__h521136 } ; - assign value__h565243 = { 1'b0, f3_exp__h560439 != 8'd0, f3_sfd__h560440 } ; - assign vm_mode_reg__read__h614204 = { csrf_vm_mode_sv39_reg, 3'b0 } ; - assign w__h646690 = + assign value__h487087 = { 1'b0, f1_exp__h482142 != 8'd0, f1_sfd__h482143 } ; + assign value__h525940 = { 1'b0, f2_exp__h521136 != 8'd0, f2_sfd__h521137 } ; + assign value__h565244 = { 1'b0, f3_exp__h560440 != 8'd0, f3_sfd__h560441 } ; + assign vm_mode_reg__read__h614205 = { csrf_vm_mode_sv39_reg, 3'b0 } ; + assign w__h646691 = coreFix_globalSpecUpdate_correctSpecTag_0$whas ? - result__h646746 : + result__h646747 : 12'd4095 ; - assign x__h153726 = + assign x__h153727 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] : coreFix_memExe_reqLdQ_data_0_rl[68:64]) : 5'd0 ; - assign x__h153732 = + assign x__h153733 = coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLdQ_data_0_lat_0$whas ? coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqLdQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h157273 = { 3'd0, sbIdx__h157152 } ; - assign x__h157279 = + assign x__h157274 = { 3'd0, sbIdx__h157153 } ; + assign x__h157280 = coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ? (CAN_FIRE_RL_coreFix_memExe_doIssueSB ? coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] : coreFix_memExe_reqStQ_data_0_rl[63:0]) : 64'd0 ; - assign x__h160089 = + assign x__h160090 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] : coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h160093 = + assign x__h160094 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] : coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h161941 = + assign x__h161942 = coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ? coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] : coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h181477 = - sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180565 ; assign x__h181478 = - sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181171 ; - assign x__h181700 = { x__h183903[2:0], 3'b0 } ; - assign x__h18386 = + sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180566 ; + assign x__h181479 = + sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181172 ; + assign x__h181701 = { x__h183904[2:0], 3'b0 } ; + assign x__h18387 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[141:78] : mmio_dataReqQ_enqReq_rl[141:78] ; - assign x__h183903 = + assign x__h183904 = coreFix_memExe_regToExeQ$first[139:76] + { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}}, coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ; - assign x__h193680 = + assign x__h193681 = coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ? - curData__h192917[63:32] : - curData__h192917[31:0] ; - assign x__h20924 = + curData__h192918[63:32] : + curData__h192918[31:0] ; + assign x__h20925 = mmio_dataReqQ_enqReq_lat_0$whas ? mmio_dataReqQ_enqReq_lat_0$wget[63:0] : mmio_dataReqQ_enqReq_rl[63:0] ; - assign x__h287280 = + assign x__h287281 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) : 5'd0 ; - assign x__h287292 = + assign x__h287293 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) : 64'd0 ; - assign x__h289146 = + assign x__h289147 = coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ? (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] : coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) : 64'd0 ; - assign x__h302152 = + assign x__h302153 = EN_dCacheToParent_fromP_enq ? coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] : coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ; - assign x__h337885 = - { (_theResult___exp__h381217 != 8'd255 || - _theResult___sfd__h381218 == 23'd0) && + assign x__h337886 = + { (_theResult___exp__h381218 != 8'd255 || + _theResult___sfd__h381219 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140, - out_f_exp__h381494, - out_f_sfd__h381495 } ; - assign x__h364435 = - sfd__h338481 << (x__h364468[11] ? 12'hAAA : x__h364468) ; - assign x__h364468 = + out_f_exp__h381495, + out_f_sfd__h381496 } ; + assign x__h364436 = + sfd__h338482 << (x__h364469[11] ? 12'hAAA : x__h364469) ; + assign x__h364469 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ; - assign x__h383587 = - { (_theResult___exp__h426914 != 8'd255 || - _theResult___sfd__h426915 == 23'd0) && + assign x__h383588 = + { (_theResult___exp__h426915 != 8'd255 || + _theResult___sfd__h426916 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532, - out_f_exp__h427191, - out_f_sfd__h427192 } ; - assign x__h410132 = - sfd__h384183 << (x__h410165[11] ? 12'hAAA : x__h410165) ; - assign x__h410165 = + out_f_exp__h427192, + out_f_sfd__h427193 } ; + assign x__h410133 = + sfd__h384184 << (x__h410166[11] ? 12'hAAA : x__h410166) ; + assign x__h410166 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ; - assign x__h429282 = - { (_theResult___exp__h472609 != 8'd255 || - _theResult___sfd__h472610 == 23'd0) && + assign x__h429283 = + { (_theResult___exp__h472610 != 8'd255 || + _theResult___sfd__h472611 == 23'd0) && IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924, - out_f_exp__h472886, - out_f_sfd__h472887 } ; - assign x__h455827 = - sfd__h429878 << (x__h455860[11] ? 12'hAAA : x__h455860) ; - assign x__h455860 = + out_f_exp__h472887, + out_f_sfd__h472888 } ; + assign x__h455828 = + sfd__h429879 << (x__h455861[11] ? 12'hAAA : x__h455861) ; + assign x__h455861 = 12'd57 - _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ; - assign x__h46293 = + assign x__h46294 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[141:78] : mmio_cRqQ_enqReq_rl[141:78] ; - assign x__h481671 = - sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478807 ; assign x__h481672 = - sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479415 ; + sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478808 ; assign x__h481673 = - sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480017 ; - assign x__h48829 = + sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479416 ; + assign x__h481674 = + sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480018 ; + assign x__h48830 = mmio_cRqQ_enqReq_lat_0$whas ? mmio_cRqQ_enqReq_lat_0$wget[63:0] : mmio_cRqQ_enqReq_rl[63:0] ; - assign x__h503578 = sfd__h482503 << x__h503611 ; - assign x__h503611 = + assign x__h503579 = sfd__h482504 << x__h503612 ; + assign x__h503612 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ; - assign x__h542431 = sfd__h521497 << x__h542464 ; - assign x__h542464 = + assign x__h542432 = sfd__h521498 << x__h542465 ; + assign x__h542465 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ; - assign x__h581735 = sfd__h560801 << x__h581768 ; - assign x__h581768 = + assign x__h581736 = sfd__h560802 << x__h581769 ; + assign x__h581769 = 12'd57 - _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ; - assign x__h603385 = a__h602949[63] ^ b__h602950[63] ; - assign x__h613035 = { csrf_frm_reg, csrf_fflags_reg } ; - assign x__h617232 = - coreFix_aluExe_1_dispToRegQ$first[131] ? - rVal1__h609051 : - v__h607935 ; + assign x__h603386 = a__h602950[63] ^ b__h602951[63] ; + assign x__h613036 = { csrf_frm_reg, csrf_fflags_reg } ; assign x__h617233 = - sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615057 ; - assign x__h639741 = - coreFix_aluExe_0_dispToRegQ$first[131] ? - rVal1__h633779 : - v__h632818 ; + coreFix_aluExe_1_dispToRegQ$first[131] ? + rVal1__h609052 : + v__h607936 ; + assign x__h617234 = + sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615058 ; assign x__h639742 = - sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637576 ; - assign x__h646694 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; - assign x__h646745 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; - assign x__h702377 = + coreFix_aluExe_0_dispToRegQ$first[131] ? + rVal1__h633780 : + v__h632819 ; + assign x__h639743 = + sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637577 ; + assign x__h646695 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ; + assign x__h646746 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ; + assign x__h702378 = (!rob$deqPort_0_deq_data[166] && (rob$deqPort_0_deq_data[165:162] == 4'd1 || rob$deqPort_0_deq_data[165:162] == 4'd12)) ? rob$deqPort_0_deq_data[161:98] : rob$deqPort_0_deq_data[95:32] ; - assign x__h712418 = { cause_code__h709443, 2'b0 } ; - assign x__h714645 = + assign x__h712419 = { cause_code__h709444, 2'b0 } ; + assign x__h714646 = { csrf_fs_reg == 2'b11, IF_csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_c_ETC___d14920 } ; - assign x__h714837 = - { commitStage_commitTrap[36], 59'b0, cause_code__h709443 } ; - assign x__h722556 = { 1'b0, csrf_spp_reg } ; - assign x__h726188 = + assign x__h714838 = + { commitStage_commitTrap[36], 59'b0, cause_code__h709444 } ; + assign x__h722557 = { 1'b0, csrf_spp_reg } ; + assign x__h726059 = { csrf_fs_reg == 2'b11, 40'd5120, csrf_tsr_reg, @@ -32104,8 +32104,8 @@ module mkCore(CLK, 2'd0, csrf_fs_reg, IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15288 } ; - assign x__h729657 = - { r1__read_BITS_62_TO_14___h729677, + assign x__h729528 = + { r1__read_BITS_62_TO_14___h729548, 2'b11, csrf_mpp_reg, 2'b0, @@ -32118,54 +32118,54 @@ module mkCore(CLK, 1'b0, csrf_ie_vec_1, csrf_ie_vec_0 } ; - assign x__h732802 = - { y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784[63:15], + assign x__h732673 = + { y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655[63:15], 2'b11, - y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784[12:0] } ; - assign x__h733551 = + y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655[12:0] } ; + assign x__h733422 = NOT_rob_deqPort_0_canDeq__5320_5321_OR_rob_deq_ETC___d15664 ? - y_avValue_snd_snd_snd_fst__h733361 : + y_avValue_snd_snd_snd_fst__h733232 : IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 ; - assign x__h76238 = mmio_pRqQ_data_0[31:0] ; - assign x_addr__h314075 = + assign x__h76239 = mmio_pRqQ_data_0[31:0] ; + assign x_addr__h314076 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ? coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] : coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ; - assign x_data__h66087 = + assign x_data__h66088 = EN_mmioToPlatform_pRq_enq ? mmio_pRqQ_enqReq_lat_0$wget[31:0] : mmio_pRqQ_enqReq_rl[31:0] ; - assign x_data_imm__h676657 = fetchStage$pipelines_0_first[159:128] ; - assign x_data_imm__h692711 = fetchStage$pipelines_1_first[159:128] ; - assign x_decodeInfo_frm__h655012 = csrf_frm_reg ; - assign x_prv__h712487 = + assign x_data_imm__h676658 = fetchStage$pipelines_0_first[159:128] ; + assign x_data_imm__h692712 = fetchStage$pipelines_1_first[159:128] ; + assign x_decodeInfo_frm__h655013 = csrf_frm_reg ; + assign x_prv__h712488 = csrf_prv_reg_read__2787_ULE_1_4696_AND_IF_comm_ETC___d14718 ? 2'd1 : 2'd3 ; - assign x_prv__h723013 = + assign x_prv__h723014 = (rob$deqPort_0_deq_data[329:325] == 5'd19) ? - x__h722556 : + x__h722557 : csrf_mpp_reg ; - assign x_quotient__h475197 = + assign x_quotient__h475198 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? 64'hFFFFFFFFFFFFFFFF : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ? - q___1__h475882 : + q___1__h475883 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ; - assign x_reg_ifc__read__h609482 = { 63'd0, csrf_stats_module_doStats } ; - assign x_remainder__h475198 = + assign x_reg_ifc__read__h609483 = { 63'd0, csrf_stats_module_doStats } ; + assign x_remainder__h475199 = coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ? coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] : ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] && coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ? - r___1__h475908 : + r___1__h475909 : coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ; - assign y__h254804 = + assign y__h254805 = { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518], coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ; - assign y__h646724 = ~x__h646694 ; - assign y__h651655 = + assign y__h646725 = ~x__h646695 ; + assign y__h651656 = { 4'd15, ~csrf_mideleg_11_reg, 1'd1, @@ -32174,66 +32174,66 @@ module mkCore(CLK, ~csrf_mideleg_5_3_reg, 1'd1, ~csrf_mideleg_1_0_reg } ; - assign y__h688411 = 12'd1 << specTagManager$nextSpecTag ; - assign y__h730489 = + assign y__h688412 = 12'd1 << specTagManager$nextSpecTag ; + assign y__h730360 = rob$deqPort_0_canDeq ? - y_avValue_snd_snd_snd_snd_snd_fst__h730512 : + y_avValue_snd_snd_snd_snd_snd_fst__h730383 : 64'd0 ; - assign y__h733310 = + assign y__h733181 = NOT_rob_deqPort_0_canDeq__5320_5321_OR_rob_deq_ETC___d15664 ? - y_avValue_snd_snd_snd_snd_snd_fst__h733371 : - y__h730489 ; - assign y_avValue__h180565 = + y_avValue_snd_snd_snd_snd_snd_fst__h733242 : + y__h730360 ; + assign y_avValue__h180566 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 ; - assign y_avValue__h181171 = + assign y_avValue__h181172 = NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 ; - assign y_avValue__h478807 = + assign y_avValue__h478808 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 ; - assign y_avValue__h479415 = + assign y_avValue__h479416 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 ; - assign y_avValue__h480017 = + assign y_avValue__h480018 = NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 ; - assign y_avValue__h608841 = + assign y_avValue__h608842 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 ; - assign y_avValue__h615057 = + assign y_avValue__h615058 = NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 ; - assign y_avValue__h633571 = + assign y_avValue__h633572 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 ; - assign y_avValue__h637576 = + assign y_avValue__h637577 = NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ? coreFix_aluExe_0_bypassWire_3$wget[63:0] : IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ; - assign y_avValue_fst__h681571 = + assign y_avValue_fst__h681572 = (fetchStage$pipelines_0_first[194:192] == 3'd1) ? - spec_bits__h688398 : + spec_bits__h688399 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681600 = + assign y_avValue_fst__h681601 = IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ? - y_avValue_fst__h681571 : + y_avValue_fst__h681572 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h681634 = + assign y_avValue_fst__h681635 = ((fetchStage$pipelines_0_first[194:192] != 3'd1 || specTagManager$canClaim) && regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429) ? - y_avValue_fst__h681600 : + y_avValue_fst__h681601 : specTagManager$currentSpecBits ; - assign y_avValue_fst__h730027 = + assign y_avValue_fst__h729898 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32247,10 +32247,10 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 5'd0 : rob$deqPort_0_deq_data[31:27] ; - assign y_avValue_fst__h733192 = + assign y_avValue_fst__h733063 = IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 | rob$deqPort_1_deq_data[31:27] ; - assign y_avValue_fst__h733224 = + assign y_avValue_fst__h733095 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32263,16 +32263,16 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15670 : - y_avValue_fst__h733192 ; - assign y_avValue_new_pc__h712179 = + y_avValue_fst__h733063 ; + assign y_avValue_new_pc__h712180 = (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h712403 + { 58'd0, x__h712418 } : - base__h712403 ; - assign y_avValue_new_pc__h712365 = + base__h712404 + { 58'd0, x__h712419 } : + base__h712404 ; + assign y_avValue_new_pc__h712366 = (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ? - base__h712423 + { 58'd0, x__h712418 } : - base__h712423 ; - assign y_avValue_snd_snd_snd_fst__h730502 = + base__h712424 + { 58'd0, x__h712419 } : + base__h712424 ; + assign y_avValue_snd_snd_snd_fst__h730373 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32286,7 +32286,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 2'd0 : 2'd1 ; - assign y_avValue_snd_snd_snd_fst__h733361 = + assign y_avValue_snd_snd_snd_fst__h733232 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32299,11 +32299,11 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 : - y_avValue_snd_snd_snd_fst__h733397 ; - assign y_avValue_snd_snd_snd_fst__h733397 = + y_avValue_snd_snd_snd_fst__h733268 ; + assign y_avValue_snd_snd_snd_fst__h733268 = IF_rob_deqPort_0_canDeq__5320_THEN_IF_NOT_rob__ETC___d15689 + 2'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h730512 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h730383 = (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] || rob$deqPort_0_deq_data[167] || rob$deqPort_0_deq_data[329:325] == 5'd0 || @@ -32317,7 +32317,7 @@ module mkCore(CLK, rob$deqPort_0_deq_data[329:325] == 5'd20) ? 64'd0 : 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h733371 = + assign y_avValue_snd_snd_snd_snd_snd_fst__h733242 = (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] || rob$deqPort_1_deq_data[167] || rob$deqPort_1_deq_data[329:325] == 5'd0 || @@ -32329,10 +32329,10 @@ module mkCore(CLK, rob$deqPort_1_deq_data[329:325] == 5'd15 || rob$deqPort_1_deq_data[329:325] == 5'd19 || rob$deqPort_1_deq_data[329:325] == 5'd20) ? - y__h730489 : - y_avValue_snd_snd_snd_snd_snd_fst__h733407 ; - assign y_avValue_snd_snd_snd_snd_snd_fst__h733407 = y__h730489 + 64'd1 ; - assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h732784 = x__h729657 ; + y__h730360 : + y_avValue_snd_snd_snd_snd_snd_fst__h733278 ; + assign y_avValue_snd_snd_snd_snd_snd_fst__h733278 = y__h730360 + 64'd1 ; + assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h732655 = x__h729528 ; always@(v_f_to_TV_1$D_OUT) begin case (v_f_to_TV_1$D_OUT[475:464]) @@ -32533,28 +32533,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87]) 3'd0: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - x__h197127 = + x__h197128 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end @@ -32570,28 +32570,28 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP) 3'd0: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0; 3'd1: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1; 3'd2: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2; 3'd3: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3; 3'd4: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4; 3'd5: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5; 3'd6: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6; 3'd7: - x__h285847 = + x__h285848 = coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7; endcase end @@ -32601,10 +32601,10 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - addr__h290068 = + addr__h290069 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518]; 1'd1: - addr__h290068 = + addr__h290069 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518]; endcase end @@ -32613,37 +32613,37 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91]) 3'd0: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0]; 3'd1: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64]; 3'd2: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128]; 3'd3: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192]; 3'd4: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256]; 3'd5: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320]; 3'd6: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384]; 3'd7: - curData__h192917 = + curData__h192918 = coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448]; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) - 4'd0, 4'd3: trap_val__h710482 = commitStage_commitTrap[164:101]; - 4'd2: trap_val__h710482 = { 32'd0, commitStage_commitTrap[31:0] }; - default: trap_val__h710482 = + 4'd0, 4'd3: trap_val__h710483 = commitStage_commitTrap[164:101]; + 4'd2: trap_val__h710483 = { 32'd0, commitStage_commitTrap[31:0] }; + default: trap_val__h710483 = (commitStage_commitTrap[35:32] != 4'd8 && commitStage_commitTrap[35:32] != 4'd9 && commitStage_commitTrap[35:32] != 4'd11) ? @@ -32657,360 +32657,360 @@ module mkCore(CLK, begin case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP) 1'd0: - x__h291617 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; + x__h291618 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0]; 1'd1: - x__h291617 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; + x__h291618 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0]; endcase end always@(f_csr_reqs$D_OUT or - fflags_csr__read__h609352 or - frm_csr__read__h609363 or - fcsr_csr__read__h609377 or - sstatus_csr__read__h609573 or - sie_csr__read__h609643 or - stvec_csr__read__h609686 or - scounteren_csr__read__h609739 or + fflags_csr__read__h609353 or + frm_csr__read__h609364 or + fcsr_csr__read__h609378 or + sstatus_csr__read__h609574 or + sie_csr__read__h609644 or + stvec_csr__read__h609687 or + scounteren_csr__read__h609740 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609877 or + scause_csr__read__h609878 or csrf_stval_csr or - sip_csr__read__h610017 or - satp_csr__read__h610080 or - mstatus_csr__read__h610223 or - medeleg_csr__read__h610371 or - mideleg_csr__read__h610466 or - mie_csr__read__h610590 or - mtvec_csr__read__h610672 or - mcounteren_csr__read__h610764 or + sip_csr__read__h610018 or + satp_csr__read__h610081 or + mstatus_csr__read__h610224 or + medeleg_csr__read__h610372 or + mideleg_csr__read__h610467 or + mie_csr__read__h610591 or + mtvec_csr__read__h610673 or + mcounteren_csr__read__h610765 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611019 or + mcause_csr__read__h611020 or csrf_mtval_csr or - mip_csr__read__h611252 or + mip_csr__read__h611253 or csrf_rg_tselect or - rg_tdata1__read__h612207 or + rg_tdata1__read__h612208 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609482 or - n__read__h611356 or n__read__h611547 or csrf_time_reg) + x_reg_ifc__read__h609483 or + n__read__h611357 or n__read__h611548 or csrf_time_reg) begin case (f_csr_reqs$D_OUT[75:64]) - 12'd1: data_out__h737401 = fflags_csr__read__h609352; - 12'd2: data_out__h737401 = frm_csr__read__h609363; - 12'd3: data_out__h737401 = fcsr_csr__read__h609377; - 12'd256: data_out__h737401 = sstatus_csr__read__h609573; - 12'd260: data_out__h737401 = sie_csr__read__h609643; - 12'd261: data_out__h737401 = stvec_csr__read__h609686; - 12'd262: data_out__h737401 = scounteren_csr__read__h609739; - 12'd320: data_out__h737401 = csrf_sscratch_csr; - 12'd321: data_out__h737401 = csrf_sepc_csr; - 12'd322: data_out__h737401 = scause_csr__read__h609877; - 12'd323: data_out__h737401 = csrf_stval_csr; - 12'd324: data_out__h737401 = sip_csr__read__h610017; - 12'd384: data_out__h737401 = satp_csr__read__h610080; - 12'd768: data_out__h737401 = mstatus_csr__read__h610223; - 12'd769: data_out__h737401 = 64'h800000000014112D; - 12'd770: data_out__h737401 = medeleg_csr__read__h610371; - 12'd771: data_out__h737401 = mideleg_csr__read__h610466; - 12'd772: data_out__h737401 = mie_csr__read__h610590; - 12'd773: data_out__h737401 = mtvec_csr__read__h610672; - 12'd774: data_out__h737401 = mcounteren_csr__read__h610764; - 12'd832: data_out__h737401 = csrf_mscratch_csr; - 12'd833: data_out__h737401 = csrf_mepc_csr; - 12'd834: data_out__h737401 = mcause_csr__read__h611019; - 12'd835: data_out__h737401 = csrf_mtval_csr; - 12'd836: data_out__h737401 = mip_csr__read__h611252; - 12'd1952: data_out__h737401 = csrf_rg_tselect; - 12'd1953: data_out__h737401 = rg_tdata1__read__h612207; - 12'd1954: data_out__h737401 = csrf_rg_tdata2; - 12'd1955: data_out__h737401 = csrf_rg_tdata3; - 12'd1968: data_out__h737401 = csrf_rg_dcsr; - 12'd1969: data_out__h737401 = csrf_rg_dpc; - 12'd1970: data_out__h737401 = csrf_rg_dscratch0; - 12'd1971: data_out__h737401 = csrf_rg_dscratch1; + 12'd1: data_out__h737272 = fflags_csr__read__h609353; + 12'd2: data_out__h737272 = frm_csr__read__h609364; + 12'd3: data_out__h737272 = fcsr_csr__read__h609378; + 12'd256: data_out__h737272 = sstatus_csr__read__h609574; + 12'd260: data_out__h737272 = sie_csr__read__h609644; + 12'd261: data_out__h737272 = stvec_csr__read__h609687; + 12'd262: data_out__h737272 = scounteren_csr__read__h609740; + 12'd320: data_out__h737272 = csrf_sscratch_csr; + 12'd321: data_out__h737272 = csrf_sepc_csr; + 12'd322: data_out__h737272 = scause_csr__read__h609878; + 12'd323: data_out__h737272 = csrf_stval_csr; + 12'd324: data_out__h737272 = sip_csr__read__h610018; + 12'd384: data_out__h737272 = satp_csr__read__h610081; + 12'd768: data_out__h737272 = mstatus_csr__read__h610224; + 12'd769: data_out__h737272 = 64'h800000000014112D; + 12'd770: data_out__h737272 = medeleg_csr__read__h610372; + 12'd771: data_out__h737272 = mideleg_csr__read__h610467; + 12'd772: data_out__h737272 = mie_csr__read__h610591; + 12'd773: data_out__h737272 = mtvec_csr__read__h610673; + 12'd774: data_out__h737272 = mcounteren_csr__read__h610765; + 12'd832: data_out__h737272 = csrf_mscratch_csr; + 12'd833: data_out__h737272 = csrf_mepc_csr; + 12'd834: data_out__h737272 = mcause_csr__read__h611020; + 12'd835: data_out__h737272 = csrf_mtval_csr; + 12'd836: data_out__h737272 = mip_csr__read__h611253; + 12'd1952: data_out__h737272 = csrf_rg_tselect; + 12'd1953: data_out__h737272 = rg_tdata1__read__h612208; + 12'd1954: data_out__h737272 = csrf_rg_tdata2; + 12'd1955: data_out__h737272 = csrf_rg_tdata3; + 12'd1968: data_out__h737272 = csrf_rg_dcsr; + 12'd1969: data_out__h737272 = csrf_rg_dpc; + 12'd1970: data_out__h737272 = csrf_rg_dscratch0; + 12'd1971: data_out__h737272 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - data_out__h737401 = 64'd0; - 12'd2049: data_out__h737401 = x_reg_ifc__read__h609482; - 12'd2816, 12'd3072: data_out__h737401 = n__read__h611356; - 12'd2818, 12'd3074: data_out__h737401 = n__read__h611547; - 12'd3073: data_out__h737401 = csrf_time_reg; - default: data_out__h737401 = 64'b0; + data_out__h737272 = 64'd0; + 12'd2049: data_out__h737272 = x_reg_ifc__read__h609483; + 12'd2816, 12'd3072: data_out__h737272 = n__read__h611357; + 12'd2818, 12'd3074: data_out__h737272 = n__read__h611548; + 12'd3073: data_out__h737272 = csrf_time_reg; + default: data_out__h737272 = 64'b0; endcase end always@(coreFix_aluExe_1_dispToRegQ$first or - fflags_csr__read__h609352 or - frm_csr__read__h609363 or - fcsr_csr__read__h609377 or - sstatus_csr__read__h609573 or - sie_csr__read__h609643 or - stvec_csr__read__h609686 or - scounteren_csr__read__h609739 or + fflags_csr__read__h609353 or + frm_csr__read__h609364 or + fcsr_csr__read__h609378 or + sstatus_csr__read__h609574 or + sie_csr__read__h609644 or + stvec_csr__read__h609687 or + scounteren_csr__read__h609740 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609877 or + scause_csr__read__h609878 or csrf_stval_csr or - sip_csr__read__h610017 or - satp_csr__read__h610080 or - mstatus_csr__read__h610223 or - medeleg_csr__read__h610371 or - mideleg_csr__read__h610466 or - mie_csr__read__h610590 or - mtvec_csr__read__h610672 or - mcounteren_csr__read__h610764 or + sip_csr__read__h610018 or + satp_csr__read__h610081 or + mstatus_csr__read__h610224 or + medeleg_csr__read__h610372 or + mideleg_csr__read__h610467 or + mie_csr__read__h610591 or + mtvec_csr__read__h610673 or + mcounteren_csr__read__h610765 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611019 or + mcause_csr__read__h611020 or csrf_mtval_csr or - mip_csr__read__h611252 or + mip_csr__read__h611253 or csrf_rg_tselect or - rg_tdata1__read__h612207 or + rg_tdata1__read__h612208 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609482 or - n__read__h611356 or n__read__h611547 or csrf_time_reg) + x_reg_ifc__read__h609483 or + n__read__h611357 or n__read__h611548 or csrf_time_reg) begin case (coreFix_aluExe_1_dispToRegQ$first[130:119]) - 12'd1: rVal1__h609051 = fflags_csr__read__h609352; - 12'd2: rVal1__h609051 = frm_csr__read__h609363; - 12'd3: rVal1__h609051 = fcsr_csr__read__h609377; - 12'd256: rVal1__h609051 = sstatus_csr__read__h609573; - 12'd260: rVal1__h609051 = sie_csr__read__h609643; - 12'd261: rVal1__h609051 = stvec_csr__read__h609686; - 12'd262: rVal1__h609051 = scounteren_csr__read__h609739; - 12'd320: rVal1__h609051 = csrf_sscratch_csr; - 12'd321: rVal1__h609051 = csrf_sepc_csr; - 12'd322: rVal1__h609051 = scause_csr__read__h609877; - 12'd323: rVal1__h609051 = csrf_stval_csr; - 12'd324: rVal1__h609051 = sip_csr__read__h610017; - 12'd384: rVal1__h609051 = satp_csr__read__h610080; - 12'd768: rVal1__h609051 = mstatus_csr__read__h610223; - 12'd769: rVal1__h609051 = 64'h800000000014112D; - 12'd770: rVal1__h609051 = medeleg_csr__read__h610371; - 12'd771: rVal1__h609051 = mideleg_csr__read__h610466; - 12'd772: rVal1__h609051 = mie_csr__read__h610590; - 12'd773: rVal1__h609051 = mtvec_csr__read__h610672; - 12'd774: rVal1__h609051 = mcounteren_csr__read__h610764; - 12'd832: rVal1__h609051 = csrf_mscratch_csr; - 12'd833: rVal1__h609051 = csrf_mepc_csr; - 12'd834: rVal1__h609051 = mcause_csr__read__h611019; - 12'd835: rVal1__h609051 = csrf_mtval_csr; - 12'd836: rVal1__h609051 = mip_csr__read__h611252; - 12'd1952: rVal1__h609051 = csrf_rg_tselect; - 12'd1953: rVal1__h609051 = rg_tdata1__read__h612207; - 12'd1954: rVal1__h609051 = csrf_rg_tdata2; - 12'd1955: rVal1__h609051 = csrf_rg_tdata3; - 12'd1968: rVal1__h609051 = csrf_rg_dcsr; - 12'd1969: rVal1__h609051 = csrf_rg_dpc; - 12'd1970: rVal1__h609051 = csrf_rg_dscratch0; - 12'd1971: rVal1__h609051 = csrf_rg_dscratch1; + 12'd1: rVal1__h609052 = fflags_csr__read__h609353; + 12'd2: rVal1__h609052 = frm_csr__read__h609364; + 12'd3: rVal1__h609052 = fcsr_csr__read__h609378; + 12'd256: rVal1__h609052 = sstatus_csr__read__h609574; + 12'd260: rVal1__h609052 = sie_csr__read__h609644; + 12'd261: rVal1__h609052 = stvec_csr__read__h609687; + 12'd262: rVal1__h609052 = scounteren_csr__read__h609740; + 12'd320: rVal1__h609052 = csrf_sscratch_csr; + 12'd321: rVal1__h609052 = csrf_sepc_csr; + 12'd322: rVal1__h609052 = scause_csr__read__h609878; + 12'd323: rVal1__h609052 = csrf_stval_csr; + 12'd324: rVal1__h609052 = sip_csr__read__h610018; + 12'd384: rVal1__h609052 = satp_csr__read__h610081; + 12'd768: rVal1__h609052 = mstatus_csr__read__h610224; + 12'd769: rVal1__h609052 = 64'h800000000014112D; + 12'd770: rVal1__h609052 = medeleg_csr__read__h610372; + 12'd771: rVal1__h609052 = mideleg_csr__read__h610467; + 12'd772: rVal1__h609052 = mie_csr__read__h610591; + 12'd773: rVal1__h609052 = mtvec_csr__read__h610673; + 12'd774: rVal1__h609052 = mcounteren_csr__read__h610765; + 12'd832: rVal1__h609052 = csrf_mscratch_csr; + 12'd833: rVal1__h609052 = csrf_mepc_csr; + 12'd834: rVal1__h609052 = mcause_csr__read__h611020; + 12'd835: rVal1__h609052 = csrf_mtval_csr; + 12'd836: rVal1__h609052 = mip_csr__read__h611253; + 12'd1952: rVal1__h609052 = csrf_rg_tselect; + 12'd1953: rVal1__h609052 = rg_tdata1__read__h612208; + 12'd1954: rVal1__h609052 = csrf_rg_tdata2; + 12'd1955: rVal1__h609052 = csrf_rg_tdata3; + 12'd1968: rVal1__h609052 = csrf_rg_dcsr; + 12'd1969: rVal1__h609052 = csrf_rg_dpc; + 12'd1970: rVal1__h609052 = csrf_rg_dscratch0; + 12'd1971: rVal1__h609052 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h609051 = 64'd0; - 12'd2049: rVal1__h609051 = x_reg_ifc__read__h609482; - 12'd2816, 12'd3072: rVal1__h609051 = n__read__h611356; - 12'd2818, 12'd3074: rVal1__h609051 = n__read__h611547; - 12'd3073: rVal1__h609051 = csrf_time_reg; - default: rVal1__h609051 = 64'b0; + rVal1__h609052 = 64'd0; + 12'd2049: rVal1__h609052 = x_reg_ifc__read__h609483; + 12'd2816, 12'd3072: rVal1__h609052 = n__read__h611357; + 12'd2818, 12'd3074: rVal1__h609052 = n__read__h611548; + 12'd3073: rVal1__h609052 = csrf_time_reg; + default: rVal1__h609052 = 64'b0; endcase end always@(coreFix_aluExe_0_dispToRegQ$first or - fflags_csr__read__h609352 or - frm_csr__read__h609363 or - fcsr_csr__read__h609377 or - sstatus_csr__read__h609573 or - sie_csr__read__h609643 or - stvec_csr__read__h609686 or - scounteren_csr__read__h609739 or + fflags_csr__read__h609353 or + frm_csr__read__h609364 or + fcsr_csr__read__h609378 or + sstatus_csr__read__h609574 or + sie_csr__read__h609644 or + stvec_csr__read__h609687 or + scounteren_csr__read__h609740 or csrf_sscratch_csr or csrf_sepc_csr or - scause_csr__read__h609877 or + scause_csr__read__h609878 or csrf_stval_csr or - sip_csr__read__h610017 or - satp_csr__read__h610080 or - mstatus_csr__read__h610223 or - medeleg_csr__read__h610371 or - mideleg_csr__read__h610466 or - mie_csr__read__h610590 or - mtvec_csr__read__h610672 or - mcounteren_csr__read__h610764 or + sip_csr__read__h610018 or + satp_csr__read__h610081 or + mstatus_csr__read__h610224 or + medeleg_csr__read__h610372 or + mideleg_csr__read__h610467 or + mie_csr__read__h610591 or + mtvec_csr__read__h610673 or + mcounteren_csr__read__h610765 or csrf_mscratch_csr or csrf_mepc_csr or - mcause_csr__read__h611019 or + mcause_csr__read__h611020 or csrf_mtval_csr or - mip_csr__read__h611252 or + mip_csr__read__h611253 or csrf_rg_tselect or - rg_tdata1__read__h612207 or + rg_tdata1__read__h612208 or csrf_rg_tdata2 or csrf_rg_tdata3 or csrf_rg_dcsr or csrf_rg_dpc or csrf_rg_dscratch0 or csrf_rg_dscratch1 or - x_reg_ifc__read__h609482 or - n__read__h611356 or n__read__h611547 or csrf_time_reg) + x_reg_ifc__read__h609483 or + n__read__h611357 or n__read__h611548 or csrf_time_reg) begin case (coreFix_aluExe_0_dispToRegQ$first[130:119]) - 12'd1: rVal1__h633779 = fflags_csr__read__h609352; - 12'd2: rVal1__h633779 = frm_csr__read__h609363; - 12'd3: rVal1__h633779 = fcsr_csr__read__h609377; - 12'd256: rVal1__h633779 = sstatus_csr__read__h609573; - 12'd260: rVal1__h633779 = sie_csr__read__h609643; - 12'd261: rVal1__h633779 = stvec_csr__read__h609686; - 12'd262: rVal1__h633779 = scounteren_csr__read__h609739; - 12'd320: rVal1__h633779 = csrf_sscratch_csr; - 12'd321: rVal1__h633779 = csrf_sepc_csr; - 12'd322: rVal1__h633779 = scause_csr__read__h609877; - 12'd323: rVal1__h633779 = csrf_stval_csr; - 12'd324: rVal1__h633779 = sip_csr__read__h610017; - 12'd384: rVal1__h633779 = satp_csr__read__h610080; - 12'd768: rVal1__h633779 = mstatus_csr__read__h610223; - 12'd769: rVal1__h633779 = 64'h800000000014112D; - 12'd770: rVal1__h633779 = medeleg_csr__read__h610371; - 12'd771: rVal1__h633779 = mideleg_csr__read__h610466; - 12'd772: rVal1__h633779 = mie_csr__read__h610590; - 12'd773: rVal1__h633779 = mtvec_csr__read__h610672; - 12'd774: rVal1__h633779 = mcounteren_csr__read__h610764; - 12'd832: rVal1__h633779 = csrf_mscratch_csr; - 12'd833: rVal1__h633779 = csrf_mepc_csr; - 12'd834: rVal1__h633779 = mcause_csr__read__h611019; - 12'd835: rVal1__h633779 = csrf_mtval_csr; - 12'd836: rVal1__h633779 = mip_csr__read__h611252; - 12'd1952: rVal1__h633779 = csrf_rg_tselect; - 12'd1953: rVal1__h633779 = rg_tdata1__read__h612207; - 12'd1954: rVal1__h633779 = csrf_rg_tdata2; - 12'd1955: rVal1__h633779 = csrf_rg_tdata3; - 12'd1968: rVal1__h633779 = csrf_rg_dcsr; - 12'd1969: rVal1__h633779 = csrf_rg_dpc; - 12'd1970: rVal1__h633779 = csrf_rg_dscratch0; - 12'd1971: rVal1__h633779 = csrf_rg_dscratch1; + 12'd1: rVal1__h633780 = fflags_csr__read__h609353; + 12'd2: rVal1__h633780 = frm_csr__read__h609364; + 12'd3: rVal1__h633780 = fcsr_csr__read__h609378; + 12'd256: rVal1__h633780 = sstatus_csr__read__h609574; + 12'd260: rVal1__h633780 = sie_csr__read__h609644; + 12'd261: rVal1__h633780 = stvec_csr__read__h609687; + 12'd262: rVal1__h633780 = scounteren_csr__read__h609740; + 12'd320: rVal1__h633780 = csrf_sscratch_csr; + 12'd321: rVal1__h633780 = csrf_sepc_csr; + 12'd322: rVal1__h633780 = scause_csr__read__h609878; + 12'd323: rVal1__h633780 = csrf_stval_csr; + 12'd324: rVal1__h633780 = sip_csr__read__h610018; + 12'd384: rVal1__h633780 = satp_csr__read__h610081; + 12'd768: rVal1__h633780 = mstatus_csr__read__h610224; + 12'd769: rVal1__h633780 = 64'h800000000014112D; + 12'd770: rVal1__h633780 = medeleg_csr__read__h610372; + 12'd771: rVal1__h633780 = mideleg_csr__read__h610467; + 12'd772: rVal1__h633780 = mie_csr__read__h610591; + 12'd773: rVal1__h633780 = mtvec_csr__read__h610673; + 12'd774: rVal1__h633780 = mcounteren_csr__read__h610765; + 12'd832: rVal1__h633780 = csrf_mscratch_csr; + 12'd833: rVal1__h633780 = csrf_mepc_csr; + 12'd834: rVal1__h633780 = mcause_csr__read__h611020; + 12'd835: rVal1__h633780 = csrf_mtval_csr; + 12'd836: rVal1__h633780 = mip_csr__read__h611253; + 12'd1952: rVal1__h633780 = csrf_rg_tselect; + 12'd1953: rVal1__h633780 = rg_tdata1__read__h612208; + 12'd1954: rVal1__h633780 = csrf_rg_tdata2; + 12'd1955: rVal1__h633780 = csrf_rg_tdata3; + 12'd1968: rVal1__h633780 = csrf_rg_dcsr; + 12'd1969: rVal1__h633780 = csrf_rg_dpc; + 12'd1970: rVal1__h633780 = csrf_rg_dscratch0; + 12'd1971: rVal1__h633780 = csrf_rg_dscratch1; 12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860: - rVal1__h633779 = 64'd0; - 12'd2049: rVal1__h633779 = x_reg_ifc__read__h609482; - 12'd2816, 12'd3072: rVal1__h633779 = n__read__h611356; - 12'd2818, 12'd3074: rVal1__h633779 = n__read__h611547; - 12'd3073: rVal1__h633779 = csrf_time_reg; - default: rVal1__h633779 = 64'b0; + rVal1__h633780 = 64'd0; + 12'd2049: rVal1__h633780 = x_reg_ifc__read__h609483; + 12'd2816, 12'd3072: rVal1__h633780 = n__read__h611357; + 12'd2818, 12'd3074: rVal1__h633780 = n__read__h611548; + 12'd3073: rVal1__h633780 = csrf_time_reg; + default: rVal1__h633780 = 64'b0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h346068 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h346069 = 8'd255; 3'd2: - _theResult___fst_exp__h346068 = + _theResult___fst_exp__h346069 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h346068 = + _theResult___fst_exp__h346069 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h346068 = 8'd254; - default: _theResult___fst_exp__h346068 = 8'd0; + 3'd4: _theResult___fst_exp__h346069 = 8'd254; + default: _theResult___fst_exp__h346069 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h346069 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h346070 = 23'd0; 3'd2: - _theResult___fst_sfd__h346069 = + _theResult___fst_sfd__h346070 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h346069 = + _theResult___fst_sfd__h346070 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h346069 = 23'd8388607; - default: _theResult___fst_sfd__h346069 = 23'd0; + 3'd4: _theResult___fst_sfd__h346070 = 23'd8388607; + default: _theResult___fst_sfd__h346070 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h391767 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h391768 = 8'd255; 3'd2: - _theResult___fst_exp__h391767 = + _theResult___fst_exp__h391768 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h391767 = + _theResult___fst_exp__h391768 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h391767 = 8'd254; - default: _theResult___fst_exp__h391767 = 8'd0; + 3'd4: _theResult___fst_exp__h391768 = 8'd254; + default: _theResult___fst_exp__h391768 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h391768 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h391769 = 23'd0; 3'd2: - _theResult___fst_sfd__h391768 = + _theResult___fst_sfd__h391769 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h391768 = + _theResult___fst_sfd__h391769 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h391768 = 23'd8388607; - default: _theResult___fst_sfd__h391768 = 23'd0; + 3'd4: _theResult___fst_sfd__h391769 = 23'd8388607; + default: _theResult___fst_sfd__h391769 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_exp__h437462 = 8'd255; + 3'd0, 3'd1: _theResult___fst_exp__h437463 = 8'd255; 3'd2: - _theResult___fst_exp__h437462 = + _theResult___fst_exp__h437463 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd254 : 8'd255; 3'd3: - _theResult___fst_exp__h437462 = + _theResult___fst_exp__h437463 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 8'd255 : 8'd254; - 3'd4: _theResult___fst_exp__h437462 = 8'd254; - default: _theResult___fst_exp__h437462 = 8'd0; + 3'd4: _theResult___fst_exp__h437463 = 8'd254; + default: _theResult___fst_exp__h437463 = 8'd0; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) - 3'd0, 3'd1: _theResult___fst_sfd__h437463 = 23'd0; + 3'd0, 3'd1: _theResult___fst_sfd__h437464 = 23'd0; 3'd2: - _theResult___fst_sfd__h437463 = + _theResult___fst_sfd__h437464 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd8388607 : 23'd0; 3'd3: - _theResult___fst_sfd__h437463 = + _theResult___fst_sfd__h437464 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ? 23'd0 : 23'd8388607; - 3'd4: _theResult___fst_sfd__h437463 = 23'd8388607; - default: _theResult___fst_sfd__h437463 = 23'd0; + 3'd4: _theResult___fst_sfd__h437464 = 23'd8388607; + default: _theResult___fst_sfd__h437464 = 23'd0; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first) @@ -33161,16 +33161,16 @@ module mkCore(CLK, 4'd11, 4'd12, 4'd13: - i__h709458 = commitStage_commitTrap[35:32]; - default: i__h709458 = 4'd15; + i__h709459 = commitStage_commitTrap[35:32]; + default: i__h709459 = 4'd15; endcase end always@(commitStage_commitTrap) begin case (commitStage_commitTrap[35:32]) 4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14: - i__h709618 = commitStage_commitTrap[35:32]; - default: i__h709618 = 4'd15; + i__h709619 = commitStage_commitTrap[35:32]; + default: i__h709619 = 4'd15; endcase end always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0) @@ -33398,446 +33398,446 @@ module mkCore(CLK, coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131]; endcase end - always@(guard__h354805 or - _theResult___fst_exp__h362853 or - out_exp__h363298 or _theResult___exp__h363295) + always@(guard__h354806 or + _theResult___fst_exp__h362854 or + out_exp__h363299 or _theResult___exp__h363296) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 = - _theResult___fst_exp__h362853; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 = + _theResult___fst_exp__h362854; 2'b10: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 = - out_exp__h363298; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 = + out_exp__h363299; 2'b11: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 = - _theResult___exp__h363295; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 = + _theResult___exp__h363296; endcase end - always@(guard__h354805 or - _theResult___fst_exp__h362853 or _theResult___exp__h363295) + always@(guard__h354806 or + _theResult___fst_exp__h362854 or _theResult___exp__h363296) begin - case (guard__h354805) + case (guard__h354806) 2'b0: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33 = - _theResult___fst_exp__h362853; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 = + _theResult___fst_exp__h362854; 2'b01, 2'b10, 2'b11: - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33 = - _theResult___exp__h363295; + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 = + _theResult___exp__h363296; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32 or - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33 or + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 or + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 or - _theResult___fst_exp__h362853) + _theResult___fst_exp__h362854) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h363373 = - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q32; + _theResult___fst_exp__h363374 = + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32; 3'd1: - _theResult___fst_exp__h363373 = - CASE_guard54805_0b0_theResult___fst_exp62853_0_ETC__q33; + _theResult___fst_exp__h363374 = + CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33; 3'd2: - _theResult___fst_exp__h363373 = + _theResult___fst_exp__h363374 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532; 3'd3: - _theResult___fst_exp__h363373 = + _theResult___fst_exp__h363374 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534; - 3'd4: _theResult___fst_exp__h363373 = _theResult___fst_exp__h362853; - default: _theResult___fst_exp__h363373 = 8'd0; + 3'd4: _theResult___fst_exp__h363374 = _theResult___fst_exp__h362854; + default: _theResult___fst_exp__h363374 = 8'd0; endcase end - always@(guard__h346096 or - _theResult___fst_exp__h354197 or - out_exp__h354716 or _theResult___exp__h354713) + always@(guard__h346097 or + _theResult___fst_exp__h354198 or + out_exp__h354717 or _theResult___exp__h354714) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 = - _theResult___fst_exp__h354197; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 = + _theResult___fst_exp__h354198; 2'b10: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 = - out_exp__h354716; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 = + out_exp__h354717; 2'b11: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 = - _theResult___exp__h354713; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 = + _theResult___exp__h354714; endcase end - always@(guard__h346096 or - _theResult___fst_exp__h354197 or _theResult___exp__h354713) + always@(guard__h346097 or + _theResult___fst_exp__h354198 or _theResult___exp__h354714) begin - case (guard__h346096) + case (guard__h346097) 2'b0: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35 = - _theResult___fst_exp__h354197; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 = + _theResult___fst_exp__h354198; 2'b01, 2'b10, 2'b11: - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35 = - _theResult___exp__h354713; + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 = + _theResult___exp__h354714; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34 or - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35 or + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 or + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 or - _theResult___fst_exp__h354197) + _theResult___fst_exp__h354198) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h354791 = - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q34; + _theResult___fst_exp__h354792 = + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34; 3'd1: - _theResult___fst_exp__h354791 = - CASE_guard46096_0b0_theResult___fst_exp54197_0_ETC__q35; + _theResult___fst_exp__h354792 = + CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35; 3'd2: - _theResult___fst_exp__h354791 = + _theResult___fst_exp__h354792 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310; 3'd3: - _theResult___fst_exp__h354791 = + _theResult___fst_exp__h354792 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313; - 3'd4: _theResult___fst_exp__h354791 = _theResult___fst_exp__h354197; - default: _theResult___fst_exp__h354791 = 8'd0; + 3'd4: _theResult___fst_exp__h354792 = _theResult___fst_exp__h354198; + default: _theResult___fst_exp__h354792 = 8'd0; endcase end - always@(guard__h363735 or - _theResult___fst_exp__h371963 or - out_exp__h372482 or _theResult___exp__h372479) + always@(guard__h363736 or + _theResult___fst_exp__h371964 or + out_exp__h372483 or _theResult___exp__h372480) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 = - _theResult___fst_exp__h371963; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 = + _theResult___fst_exp__h371964; 2'b10: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 = - out_exp__h372482; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 = + out_exp__h372483; 2'b11: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 = - _theResult___exp__h372479; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 = + _theResult___exp__h372480; endcase end - always@(guard__h363735 or - _theResult___fst_exp__h371963 or _theResult___exp__h372479) + always@(guard__h363736 or + _theResult___fst_exp__h371964 or _theResult___exp__h372480) begin - case (guard__h363735) + case (guard__h363736) 2'b0: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41 = - _theResult___fst_exp__h371963; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 = + _theResult___fst_exp__h371964; 2'b01, 2'b10, 2'b11: - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41 = - _theResult___exp__h372479; + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 = + _theResult___exp__h372480; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40 or - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41 or + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 or + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 or - _theResult___fst_exp__h371963) + _theResult___fst_exp__h371964) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h372557 = - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q40; + _theResult___fst_exp__h372558 = + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40; 3'd1: - _theResult___fst_exp__h372557 = - CASE_guard63735_0b0_theResult___fst_exp71963_0_ETC__q41; + _theResult___fst_exp__h372558 = + CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41; 3'd2: - _theResult___fst_exp__h372557 = + _theResult___fst_exp__h372558 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857; 3'd3: - _theResult___fst_exp__h372557 = + _theResult___fst_exp__h372558 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859; - 3'd4: _theResult___fst_exp__h372557 = _theResult___fst_exp__h371963; - default: _theResult___fst_exp__h372557 = 8'd0; + 3'd4: _theResult___fst_exp__h372558 = _theResult___fst_exp__h371964; + default: _theResult___fst_exp__h372558 = 8'd0; endcase end - always@(guard__h372571 or - _theResult___fst_exp__h380648 or - out_exp__h381118 or _theResult___exp__h381115) + always@(guard__h372572 or + _theResult___fst_exp__h380649 or + out_exp__h381119 or _theResult___exp__h381116) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 = - _theResult___fst_exp__h380648; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 = + _theResult___fst_exp__h380649; 2'b10: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 = - out_exp__h381118; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 = + out_exp__h381119; 2'b11: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 = - _theResult___exp__h381115; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 = + _theResult___exp__h381116; endcase end - always@(guard__h372571 or - _theResult___fst_exp__h380648 or _theResult___exp__h381115) + always@(guard__h372572 or + _theResult___fst_exp__h380649 or _theResult___exp__h381116) begin - case (guard__h372571) + case (guard__h372572) 2'b0: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46 = - _theResult___fst_exp__h380648; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 = + _theResult___fst_exp__h380649; 2'b01, 2'b10, 2'b11: - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46 = - _theResult___exp__h381115; + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 = + _theResult___exp__h381116; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45 or - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46 or + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 or + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 or - _theResult___fst_exp__h380648) + _theResult___fst_exp__h380649) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h381193 = - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q45; + _theResult___fst_exp__h381194 = + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45; 3'd1: - _theResult___fst_exp__h381193 = - CASE_guard72571_0b0_theResult___fst_exp80648_0_ETC__q46; + _theResult___fst_exp__h381194 = + CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46; 3'd2: - _theResult___fst_exp__h381193 = + _theResult___fst_exp__h381194 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926; 3'd3: - _theResult___fst_exp__h381193 = + _theResult___fst_exp__h381194 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928; - 3'd4: _theResult___fst_exp__h381193 = _theResult___fst_exp__h380648; - default: _theResult___fst_exp__h381193 = 8'd0; + 3'd4: _theResult___fst_exp__h381194 = _theResult___fst_exp__h380649; + default: _theResult___fst_exp__h381194 = 8'd0; endcase end - always@(guard__h354805 or - _theResult___snd__h362804 or - out_sfd__h363299 or _theResult___sfd__h363296) + always@(guard__h354806 or + _theResult___snd__h362805 or + out_sfd__h363300 or _theResult___sfd__h363297) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 = - _theResult___snd__h362804[56:34]; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = + _theResult___snd__h362805[56:34]; 2'b10: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 = - out_sfd__h363299; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = + out_sfd__h363300; 2'b11: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 = - _theResult___sfd__h363296; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 = + _theResult___sfd__h363297; endcase end - always@(guard__h354805 or - _theResult___snd__h362804 or _theResult___sfd__h363296) + always@(guard__h354806 or + _theResult___snd__h362805 or _theResult___sfd__h363297) begin - case (guard__h354805) + case (guard__h354806) 2'b0: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48 = - _theResult___snd__h362804[56:34]; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = + _theResult___snd__h362805[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48 = - _theResult___sfd__h363296; + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 = + _theResult___sfd__h363297; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47 or - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 or + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or - _theResult___snd__h362804) + _theResult___snd__h362805) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h363374 = - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q47; + _theResult___fst_sfd__h363375 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47; 3'd1: - _theResult___fst_sfd__h363374 = - CASE_guard54805_0b0_theResult___snd62804_BITS__ETC__q48; + _theResult___fst_sfd__h363375 = + CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48; 3'd2: - _theResult___fst_sfd__h363374 = + _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976; 3'd3: - _theResult___fst_sfd__h363374 = + _theResult___fst_sfd__h363375 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978; - 3'd4: _theResult___fst_sfd__h363374 = _theResult___snd__h362804[56:34]; - default: _theResult___fst_sfd__h363374 = 23'd0; + 3'd4: _theResult___fst_sfd__h363375 = _theResult___snd__h362805[56:34]; + default: _theResult___fst_sfd__h363375 = 23'd0; endcase end - always@(guard__h346096 or - sfdin__h354191 or out_sfd__h354717 or _theResult___sfd__h354714) + always@(guard__h346097 or + sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 = - sfdin__h354191[56:34]; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + sfdin__h354192[56:34]; 2'b10: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 = - out_sfd__h354717; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + out_sfd__h354718; 2'b11: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 = - _theResult___sfd__h354714; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 = + _theResult___sfd__h354715; endcase end - always@(guard__h346096 or sfdin__h354191 or _theResult___sfd__h354714) + always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715) begin - case (guard__h346096) + case (guard__h346097) 2'b0: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50 = - sfdin__h354191[56:34]; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + sfdin__h354192[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50 = - _theResult___sfd__h354714; + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 = + _theResult___sfd__h354715; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49 or - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 or + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or - sfdin__h354191) + sfdin__h354192) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h354792 = - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q49; + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49; 3'd1: - _theResult___fst_sfd__h354792 = - CASE_guard46096_0b0_sfdin54191_BITS_56_TO_34_0_ETC__q50; + _theResult___fst_sfd__h354793 = + CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50; 3'd2: - _theResult___fst_sfd__h354792 = + _theResult___fst_sfd__h354793 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957; 3'd3: - _theResult___fst_sfd__h354792 = + _theResult___fst_sfd__h354793 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959; - 3'd4: _theResult___fst_sfd__h354792 = sfdin__h354191[56:34]; - default: _theResult___fst_sfd__h354792 = 23'd0; + 3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34]; + default: _theResult___fst_sfd__h354793 = 23'd0; endcase end - always@(guard__h363735 or - sfdin__h371957 or out_sfd__h372483 or _theResult___sfd__h372480) + always@(guard__h363736 or + sfdin__h371958 or out_sfd__h372484 or _theResult___sfd__h372481) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 = - sfdin__h371957[56:34]; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 = + sfdin__h371958[56:34]; 2'b10: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 = - out_sfd__h372483; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 = + out_sfd__h372484; 2'b11: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 = - _theResult___sfd__h372480; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 = + _theResult___sfd__h372481; endcase end - always@(guard__h363735 or sfdin__h371957 or _theResult___sfd__h372480) + always@(guard__h363736 or sfdin__h371958 or _theResult___sfd__h372481) begin - case (guard__h363735) + case (guard__h363736) 2'b0: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52 = - sfdin__h371957[56:34]; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 = + sfdin__h371958[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52 = - _theResult___sfd__h372480; + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 = + _theResult___sfd__h372481; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51 or - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52 or + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 or + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 or - sfdin__h371957) + sfdin__h371958) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h372558 = - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q51; + _theResult___fst_sfd__h372559 = + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51; 3'd1: - _theResult___fst_sfd__h372558 = - CASE_guard63735_0b0_sfdin71957_BITS_56_TO_34_0_ETC__q52; + _theResult___fst_sfd__h372559 = + CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52; 3'd2: - _theResult___fst_sfd__h372558 = + _theResult___fst_sfd__h372559 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003; 3'd3: - _theResult___fst_sfd__h372558 = + _theResult___fst_sfd__h372559 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005; - 3'd4: _theResult___fst_sfd__h372558 = sfdin__h371957[56:34]; - default: _theResult___fst_sfd__h372558 = 23'd0; + 3'd4: _theResult___fst_sfd__h372559 = sfdin__h371958[56:34]; + default: _theResult___fst_sfd__h372559 = 23'd0; endcase end - always@(guard__h372571 or - _theResult___snd__h380594 or - out_sfd__h381119 or _theResult___sfd__h381116) + always@(guard__h372572 or + _theResult___snd__h380595 or + out_sfd__h381120 or _theResult___sfd__h381117) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 = - _theResult___snd__h380594[56:34]; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 = + _theResult___snd__h380595[56:34]; 2'b10: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 = - out_sfd__h381119; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 = + out_sfd__h381120; 2'b11: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 = - _theResult___sfd__h381116; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 = + _theResult___sfd__h381117; endcase end - always@(guard__h372571 or - _theResult___snd__h380594 or _theResult___sfd__h381116) + always@(guard__h372572 or + _theResult___snd__h380595 or _theResult___sfd__h381117) begin - case (guard__h372571) + case (guard__h372572) 2'b0: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54 = - _theResult___snd__h380594[56:34]; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 = + _theResult___snd__h380595[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54 = - _theResult___sfd__h381116; + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 = + _theResult___sfd__h381117; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53 or - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54 or + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 or + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or - _theResult___snd__h380594) + _theResult___snd__h380595) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h381194 = - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q53; + _theResult___fst_sfd__h381195 = + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53; 3'd1: - _theResult___fst_sfd__h381194 = - CASE_guard72571_0b0_theResult___snd80594_BITS__ETC__q54; + _theResult___fst_sfd__h381195 = + CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54; 3'd2: - _theResult___fst_sfd__h381194 = + _theResult___fst_sfd__h381195 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022; 3'd3: - _theResult___fst_sfd__h381194 = + _theResult___fst_sfd__h381195 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024; - 3'd4: _theResult___fst_sfd__h381194 = _theResult___snd__h380594[56:34]; - default: _theResult___fst_sfd__h381194 = 23'd0; + 3'd4: _theResult___fst_sfd__h381195 = _theResult___snd__h380595[56:34]; + default: _theResult___fst_sfd__h381195 = 23'd0; endcase end - always@(guard__h346096 or + always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = - guard__h346096 == 2'b11 && + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 = + guard__h346097 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or - guard__h346096) + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or + guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - CASE_guard46096_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; + CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = - (guard__h346096 == 2'b0) ? + (guard__h346097 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h346096 == 2'b01 || guard__h346096 == 2'b10 || - guard__h346096 == 2'b11) && + (guard__h346097 == 2'b01 || guard__h346097 == 2'b10 || + guard__h346097 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 = @@ -33848,34 +33848,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h346096 or + always@(guard__h346097 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h346096) + case (guard__h346097) 2'b0, 2'b01, 2'b10: - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = - guard__h346096 != 2'b11 || + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 = + guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or - guard__h346096) + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or + guard__h346097) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - CASE_guard46096_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; + CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = - (guard__h346096 == 2'b0) ? + (guard__h346097 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h346096 != 2'b01 && guard__h346096 != 2'b10 && - guard__h346096 != 2'b11 || + guard__h346097 != 2'b01 && guard__h346097 != 2'b10 && + guard__h346097 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 = @@ -33886,34 +33886,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354805 or + always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01, 2'b10: - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = - guard__h354805 == 2'b11 && + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 = + guard__h354806 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or - guard__h354805) + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or + guard__h354806) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - CASE_guard54805_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; + CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = - (guard__h354805 == 2'b0) ? + (guard__h354806 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h354805 == 2'b01 || guard__h354805 == 2'b10 || - guard__h354805 == 2'b11) && + (guard__h354806 == 2'b01 || guard__h354806 == 2'b10 || + guard__h354806 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 = @@ -33924,34 +33924,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h354805 or + always@(guard__h354806 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h354805) + case (guard__h354806) 2'b0, 2'b01, 2'b10: - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = - guard__h354805 != 2'b11 || + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 = + guard__h354806 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or - guard__h354805) + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or + guard__h354806) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - CASE_guard54805_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; + CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = - (guard__h354805 == 2'b0) ? + (guard__h354806 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h354805 != 2'b01 && guard__h354805 != 2'b10 && - guard__h354805 != 2'b11 || + guard__h354806 != 2'b01 && guard__h354806 != 2'b10 && + guard__h354806 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 = @@ -33962,34 +33962,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363735 or + always@(guard__h363736 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01, 2'b10: - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = - guard__h363735 == 2'b11 && + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 = + guard__h363736 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or - guard__h363735) + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or + guard__h363736) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - CASE_guard63735_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; + CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = - (guard__h363735 == 2'b0) ? + (guard__h363736 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h363735 == 2'b01 || guard__h363735 == 2'b10 || - guard__h363735 == 2'b11) && + (guard__h363736 == 2'b01 || guard__h363736 == 2'b10 || + guard__h363736 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 = @@ -34000,34 +34000,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h363735 or + always@(guard__h363736 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h363735) + case (guard__h363736) 2'b0, 2'b01, 2'b10: - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = - guard__h363735 != 2'b11 || + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 = + guard__h363736 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or - guard__h363735) + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or + guard__h363736) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - CASE_guard63735_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; + CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = - (guard__h363735 == 2'b0) ? + (guard__h363736 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h363735 != 2'b01 && guard__h363735 != 2'b10 && - guard__h363735 != 2'b11 || + guard__h363736 != 2'b01 && guard__h363736 != 2'b10 && + guard__h363736 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 = @@ -34038,34 +34038,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372571 or + always@(guard__h372572 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01, 2'b10: - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = - guard__h372571 == 2'b11 && + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 = + guard__h372572 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or - guard__h372571) + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or + guard__h372572) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - CASE_guard72571_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; + CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = - (guard__h372571 == 2'b0) ? + (guard__h372572 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - (guard__h372571 == 2'b01 || guard__h372571 == 2'b10 || - guard__h372571 == 2'b11) && + (guard__h372572 == 2'b01 || guard__h372572 == 2'b10 || + guard__h372572 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 = @@ -34076,34 +34076,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h372571 or + always@(guard__h372572 or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get) begin - case (guard__h372571) + case (guard__h372572) 2'b0, 2'b01, 2'b10: - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 2'd3: - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = - guard__h372571 != 2'b11 || + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 = + guard__h372572 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or - guard__h372571) + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or + guard__h372572) begin case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - CASE_guard72571_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; + CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = - (guard__h372571 == 2'b0) ? + (guard__h372572 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] : - guard__h372571 != 2'b01 && guard__h372571 != 2'b10 && - guard__h372571 != 2'b11 || + guard__h372572 != 2'b01 && guard__h372572 != 2'b10 && + guard__h372572 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 = @@ -34140,446 +34140,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]; endcase end - always@(guard__h400502 or - _theResult___fst_exp__h408550 or - out_exp__h408995 or _theResult___exp__h408992) + always@(guard__h400503 or + _theResult___fst_exp__h408551 or + out_exp__h408996 or _theResult___exp__h408993) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 = - _theResult___fst_exp__h408550; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 = + _theResult___fst_exp__h408551; 2'b10: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 = - out_exp__h408995; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 = + out_exp__h408996; 2'b11: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 = - _theResult___exp__h408992; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 = + _theResult___exp__h408993; endcase end - always@(guard__h400502 or - _theResult___fst_exp__h408550 or _theResult___exp__h408992) + always@(guard__h400503 or + _theResult___fst_exp__h408551 or _theResult___exp__h408993) begin - case (guard__h400502) + case (guard__h400503) 2'b0: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68 = - _theResult___fst_exp__h408550; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 = + _theResult___fst_exp__h408551; 2'b01, 2'b10, 2'b11: - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68 = - _theResult___exp__h408992; + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 = + _theResult___exp__h408993; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67 or - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68 or + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 or + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 or - _theResult___fst_exp__h408550) + _theResult___fst_exp__h408551) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h409070 = - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q67; + _theResult___fst_exp__h409071 = + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67; 3'd1: - _theResult___fst_exp__h409070 = - CASE_guard00502_0b0_theResult___fst_exp08550_0_ETC__q68; + _theResult___fst_exp__h409071 = + CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68; 3'd2: - _theResult___fst_exp__h409070 = + _theResult___fst_exp__h409071 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924; 3'd3: - _theResult___fst_exp__h409070 = + _theResult___fst_exp__h409071 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926; - 3'd4: _theResult___fst_exp__h409070 = _theResult___fst_exp__h408550; - default: _theResult___fst_exp__h409070 = 8'd0; + 3'd4: _theResult___fst_exp__h409071 = _theResult___fst_exp__h408551; + default: _theResult___fst_exp__h409071 = 8'd0; endcase end - always@(guard__h391795 or - _theResult___fst_exp__h399894 or - out_exp__h400413 or _theResult___exp__h400410) + always@(guard__h391796 or + _theResult___fst_exp__h399895 or + out_exp__h400414 or _theResult___exp__h400411) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 = - _theResult___fst_exp__h399894; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 = + _theResult___fst_exp__h399895; 2'b10: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 = - out_exp__h400413; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 = + out_exp__h400414; 2'b11: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 = - _theResult___exp__h400410; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 = + _theResult___exp__h400411; endcase end - always@(guard__h391795 or - _theResult___fst_exp__h399894 or _theResult___exp__h400410) + always@(guard__h391796 or + _theResult___fst_exp__h399895 or _theResult___exp__h400411) begin - case (guard__h391795) + case (guard__h391796) 2'b0: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70 = - _theResult___fst_exp__h399894; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 = + _theResult___fst_exp__h399895; 2'b01, 2'b10, 2'b11: - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70 = - _theResult___exp__h400410; + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 = + _theResult___exp__h400411; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69 or - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70 or + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 or + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 or - _theResult___fst_exp__h399894) + _theResult___fst_exp__h399895) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h400488 = - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q69; + _theResult___fst_exp__h400489 = + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69; 3'd1: - _theResult___fst_exp__h400488 = - CASE_guard91795_0b0_theResult___fst_exp99894_0_ETC__q70; + _theResult___fst_exp__h400489 = + CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70; 3'd2: - _theResult___fst_exp__h400488 = + _theResult___fst_exp__h400489 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702; 3'd3: - _theResult___fst_exp__h400488 = + _theResult___fst_exp__h400489 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705; - 3'd4: _theResult___fst_exp__h400488 = _theResult___fst_exp__h399894; - default: _theResult___fst_exp__h400488 = 8'd0; + 3'd4: _theResult___fst_exp__h400489 = _theResult___fst_exp__h399895; + default: _theResult___fst_exp__h400489 = 8'd0; endcase end - always@(guard__h409432 or - _theResult___fst_exp__h417660 or - out_exp__h418179 or _theResult___exp__h418176) + always@(guard__h409433 or + _theResult___fst_exp__h417661 or + out_exp__h418180 or _theResult___exp__h418177) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 = - _theResult___fst_exp__h417660; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 = + _theResult___fst_exp__h417661; 2'b10: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 = - out_exp__h418179; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 = + out_exp__h418180; 2'b11: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 = - _theResult___exp__h418176; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 = + _theResult___exp__h418177; endcase end - always@(guard__h409432 or - _theResult___fst_exp__h417660 or _theResult___exp__h418176) + always@(guard__h409433 or + _theResult___fst_exp__h417661 or _theResult___exp__h418177) begin - case (guard__h409432) + case (guard__h409433) 2'b0: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76 = - _theResult___fst_exp__h417660; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 = + _theResult___fst_exp__h417661; 2'b01, 2'b10, 2'b11: - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76 = - _theResult___exp__h418176; + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 = + _theResult___exp__h418177; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75 or - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76 or + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 or + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 or - _theResult___fst_exp__h417660) + _theResult___fst_exp__h417661) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h418254 = - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q75; + _theResult___fst_exp__h418255 = + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75; 3'd1: - _theResult___fst_exp__h418254 = - CASE_guard09432_0b0_theResult___fst_exp17660_0_ETC__q76; + _theResult___fst_exp__h418255 = + CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76; 3'd2: - _theResult___fst_exp__h418254 = + _theResult___fst_exp__h418255 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249; 3'd3: - _theResult___fst_exp__h418254 = + _theResult___fst_exp__h418255 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251; - 3'd4: _theResult___fst_exp__h418254 = _theResult___fst_exp__h417660; - default: _theResult___fst_exp__h418254 = 8'd0; + 3'd4: _theResult___fst_exp__h418255 = _theResult___fst_exp__h417661; + default: _theResult___fst_exp__h418255 = 8'd0; endcase end - always@(guard__h418268 or - _theResult___fst_exp__h426345 or - out_exp__h426815 or _theResult___exp__h426812) + always@(guard__h418269 or + _theResult___fst_exp__h426346 or + out_exp__h426816 or _theResult___exp__h426813) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 = - _theResult___fst_exp__h426345; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 = + _theResult___fst_exp__h426346; 2'b10: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 = - out_exp__h426815; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 = + out_exp__h426816; 2'b11: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 = - _theResult___exp__h426812; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 = + _theResult___exp__h426813; endcase end - always@(guard__h418268 or - _theResult___fst_exp__h426345 or _theResult___exp__h426812) + always@(guard__h418269 or + _theResult___fst_exp__h426346 or _theResult___exp__h426813) begin - case (guard__h418268) + case (guard__h418269) 2'b0: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81 = - _theResult___fst_exp__h426345; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 = + _theResult___fst_exp__h426346; 2'b01, 2'b10, 2'b11: - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81 = - _theResult___exp__h426812; + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 = + _theResult___exp__h426813; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80 or - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81 or + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 or + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 or - _theResult___fst_exp__h426345) + _theResult___fst_exp__h426346) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h426890 = - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q80; + _theResult___fst_exp__h426891 = + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80; 3'd1: - _theResult___fst_exp__h426890 = - CASE_guard18268_0b0_theResult___fst_exp26345_0_ETC__q81; + _theResult___fst_exp__h426891 = + CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81; 3'd2: - _theResult___fst_exp__h426890 = + _theResult___fst_exp__h426891 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318; 3'd3: - _theResult___fst_exp__h426890 = + _theResult___fst_exp__h426891 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320; - 3'd4: _theResult___fst_exp__h426890 = _theResult___fst_exp__h426345; - default: _theResult___fst_exp__h426890 = 8'd0; + 3'd4: _theResult___fst_exp__h426891 = _theResult___fst_exp__h426346; + default: _theResult___fst_exp__h426891 = 8'd0; endcase end - always@(guard__h400502 or - _theResult___snd__h408501 or - out_sfd__h408996 or _theResult___sfd__h408993) + always@(guard__h400503 or + _theResult___snd__h408502 or + out_sfd__h408997 or _theResult___sfd__h408994) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 = - _theResult___snd__h408501[56:34]; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = + _theResult___snd__h408502[56:34]; 2'b10: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 = - out_sfd__h408996; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = + out_sfd__h408997; 2'b11: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 = - _theResult___sfd__h408993; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 = + _theResult___sfd__h408994; endcase end - always@(guard__h400502 or - _theResult___snd__h408501 or _theResult___sfd__h408993) + always@(guard__h400503 or + _theResult___snd__h408502 or _theResult___sfd__h408994) begin - case (guard__h400502) + case (guard__h400503) 2'b0: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83 = - _theResult___snd__h408501[56:34]; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = + _theResult___snd__h408502[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83 = - _theResult___sfd__h408993; + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 = + _theResult___sfd__h408994; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82 or - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 or + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or - _theResult___snd__h408501) + _theResult___snd__h408502) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h409071 = - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q82; + _theResult___fst_sfd__h409072 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82; 3'd1: - _theResult___fst_sfd__h409071 = - CASE_guard00502_0b0_theResult___snd08501_BITS__ETC__q83; + _theResult___fst_sfd__h409072 = + CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83; 3'd2: - _theResult___fst_sfd__h409071 = + _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368; 3'd3: - _theResult___fst_sfd__h409071 = + _theResult___fst_sfd__h409072 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370; - 3'd4: _theResult___fst_sfd__h409071 = _theResult___snd__h408501[56:34]; - default: _theResult___fst_sfd__h409071 = 23'd0; + 3'd4: _theResult___fst_sfd__h409072 = _theResult___snd__h408502[56:34]; + default: _theResult___fst_sfd__h409072 = 23'd0; endcase end - always@(guard__h391795 or - sfdin__h399888 or out_sfd__h400414 or _theResult___sfd__h400411) + always@(guard__h391796 or + sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 = - sfdin__h399888[56:34]; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + sfdin__h399889[56:34]; 2'b10: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 = - out_sfd__h400414; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + out_sfd__h400415; 2'b11: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 = - _theResult___sfd__h400411; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 = + _theResult___sfd__h400412; endcase end - always@(guard__h391795 or sfdin__h399888 or _theResult___sfd__h400411) + always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412) begin - case (guard__h391795) + case (guard__h391796) 2'b0: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85 = - sfdin__h399888[56:34]; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + sfdin__h399889[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85 = - _theResult___sfd__h400411; + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 = + _theResult___sfd__h400412; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84 or - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 or + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or - sfdin__h399888) + sfdin__h399889) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h400489 = - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q84; + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84; 3'd1: - _theResult___fst_sfd__h400489 = - CASE_guard91795_0b0_sfdin99888_BITS_56_TO_34_0_ETC__q85; + _theResult___fst_sfd__h400490 = + CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85; 3'd2: - _theResult___fst_sfd__h400489 = + _theResult___fst_sfd__h400490 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349; 3'd3: - _theResult___fst_sfd__h400489 = + _theResult___fst_sfd__h400490 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351; - 3'd4: _theResult___fst_sfd__h400489 = sfdin__h399888[56:34]; - default: _theResult___fst_sfd__h400489 = 23'd0; + 3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34]; + default: _theResult___fst_sfd__h400490 = 23'd0; endcase end - always@(guard__h409432 or - sfdin__h417654 or out_sfd__h418180 or _theResult___sfd__h418177) + always@(guard__h409433 or + sfdin__h417655 or out_sfd__h418181 or _theResult___sfd__h418178) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 = - sfdin__h417654[56:34]; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 = + sfdin__h417655[56:34]; 2'b10: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 = - out_sfd__h418180; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 = + out_sfd__h418181; 2'b11: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 = - _theResult___sfd__h418177; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 = + _theResult___sfd__h418178; endcase end - always@(guard__h409432 or sfdin__h417654 or _theResult___sfd__h418177) + always@(guard__h409433 or sfdin__h417655 or _theResult___sfd__h418178) begin - case (guard__h409432) + case (guard__h409433) 2'b0: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87 = - sfdin__h417654[56:34]; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 = + sfdin__h417655[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87 = - _theResult___sfd__h418177; + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 = + _theResult___sfd__h418178; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86 or - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87 or + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 or + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 or - sfdin__h417654) + sfdin__h417655) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h418255 = - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q86; + _theResult___fst_sfd__h418256 = + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86; 3'd1: - _theResult___fst_sfd__h418255 = - CASE_guard09432_0b0_sfdin17654_BITS_56_TO_34_0_ETC__q87; + _theResult___fst_sfd__h418256 = + CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87; 3'd2: - _theResult___fst_sfd__h418255 = + _theResult___fst_sfd__h418256 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395; 3'd3: - _theResult___fst_sfd__h418255 = + _theResult___fst_sfd__h418256 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397; - 3'd4: _theResult___fst_sfd__h418255 = sfdin__h417654[56:34]; - default: _theResult___fst_sfd__h418255 = 23'd0; + 3'd4: _theResult___fst_sfd__h418256 = sfdin__h417655[56:34]; + default: _theResult___fst_sfd__h418256 = 23'd0; endcase end - always@(guard__h418268 or - _theResult___snd__h426291 or - out_sfd__h426816 or _theResult___sfd__h426813) + always@(guard__h418269 or + _theResult___snd__h426292 or + out_sfd__h426817 or _theResult___sfd__h426814) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 = - _theResult___snd__h426291[56:34]; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 = + _theResult___snd__h426292[56:34]; 2'b10: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 = - out_sfd__h426816; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 = + out_sfd__h426817; 2'b11: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 = - _theResult___sfd__h426813; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 = + _theResult___sfd__h426814; endcase end - always@(guard__h418268 or - _theResult___snd__h426291 or _theResult___sfd__h426813) + always@(guard__h418269 or + _theResult___snd__h426292 or _theResult___sfd__h426814) begin - case (guard__h418268) + case (guard__h418269) 2'b0: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89 = - _theResult___snd__h426291[56:34]; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 = + _theResult___snd__h426292[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89 = - _theResult___sfd__h426813; + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 = + _theResult___sfd__h426814; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88 or - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89 or + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 or + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or - _theResult___snd__h426291) + _theResult___snd__h426292) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h426891 = - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q88; + _theResult___fst_sfd__h426892 = + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88; 3'd1: - _theResult___fst_sfd__h426891 = - CASE_guard18268_0b0_theResult___snd26291_BITS__ETC__q89; + _theResult___fst_sfd__h426892 = + CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89; 3'd2: - _theResult___fst_sfd__h426891 = + _theResult___fst_sfd__h426892 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414; 3'd3: - _theResult___fst_sfd__h426891 = + _theResult___fst_sfd__h426892 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416; - 3'd4: _theResult___fst_sfd__h426891 = _theResult___snd__h426291[56:34]; - default: _theResult___fst_sfd__h426891 = 23'd0; + 3'd4: _theResult___fst_sfd__h426892 = _theResult___snd__h426292[56:34]; + default: _theResult___fst_sfd__h426892 = 23'd0; endcase end - always@(guard__h391795 or + always@(guard__h391796 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01, 2'b10: - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = - guard__h391795 == 2'b11 && + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 = + guard__h391796 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or - guard__h391795) + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or + guard__h391796) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - CASE_guard91795_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; + CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = - (guard__h391795 == 2'b0) ? + (guard__h391796 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h391795 == 2'b01 || guard__h391795 == 2'b10 || - guard__h391795 == 2'b11) && + (guard__h391796 == 2'b01 || guard__h391796 == 2'b10 || + guard__h391796 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 = @@ -34590,34 +34590,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h391795 or + always@(guard__h391796 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h391795) + case (guard__h391796) 2'b0, 2'b01, 2'b10: - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = - guard__h391795 != 2'b11 || + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 = + guard__h391796 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or - guard__h391795) + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or + guard__h391796) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - CASE_guard91795_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; + CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = - (guard__h391795 == 2'b0) ? + (guard__h391796 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h391795 != 2'b01 && guard__h391795 != 2'b10 && - guard__h391795 != 2'b11 || + guard__h391796 != 2'b01 && guard__h391796 != 2'b10 && + guard__h391796 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 = @@ -34628,34 +34628,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400502 or + always@(guard__h400503 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01, 2'b10: - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = - guard__h400502 == 2'b11 && + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 = + guard__h400503 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or - guard__h400502) + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or + guard__h400503) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - CASE_guard00502_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; + CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = - (guard__h400502 == 2'b0) ? + (guard__h400503 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h400502 == 2'b01 || guard__h400502 == 2'b10 || - guard__h400502 == 2'b11) && + (guard__h400503 == 2'b01 || guard__h400503 == 2'b10 || + guard__h400503 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 = @@ -34666,34 +34666,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h400502 or + always@(guard__h400503 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h400502) + case (guard__h400503) 2'b0, 2'b01, 2'b10: - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = - guard__h400502 != 2'b11 || + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 = + guard__h400503 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or - guard__h400502) + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or + guard__h400503) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - CASE_guard00502_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; + CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = - (guard__h400502 == 2'b0) ? + (guard__h400503 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h400502 != 2'b01 && guard__h400502 != 2'b10 && - guard__h400502 != 2'b11 || + guard__h400503 != 2'b01 && guard__h400503 != 2'b10 && + guard__h400503 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 = @@ -34704,34 +34704,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409432 or + always@(guard__h409433 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01, 2'b10: - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = - guard__h409432 == 2'b11 && + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 = + guard__h409433 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or - guard__h409432) + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or + guard__h409433) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - CASE_guard09432_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; + CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = - (guard__h409432 == 2'b0) ? + (guard__h409433 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h409432 == 2'b01 || guard__h409432 == 2'b10 || - guard__h409432 == 2'b11) && + (guard__h409433 == 2'b01 || guard__h409433 == 2'b10 || + guard__h409433 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 = @@ -34742,34 +34742,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h409432 or + always@(guard__h409433 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h409432) + case (guard__h409433) 2'b0, 2'b01, 2'b10: - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = - guard__h409432 != 2'b11 || + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 = + guard__h409433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or - guard__h409432) + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or + guard__h409433) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - CASE_guard09432_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; + CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = - (guard__h409432 == 2'b0) ? + (guard__h409433 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h409432 != 2'b01 && guard__h409432 != 2'b10 && - guard__h409432 != 2'b11 || + guard__h409433 != 2'b01 && guard__h409433 != 2'b10 && + guard__h409433 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 = @@ -34780,34 +34780,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418268 or + always@(guard__h418269 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = - guard__h418268 == 2'b11 && + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 = + guard__h418269 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or - guard__h418268) + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or + guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - CASE_guard18268_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; + CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = - (guard__h418268 == 2'b0) ? + (guard__h418269 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - (guard__h418268 == 2'b01 || guard__h418268 == 2'b10 || - guard__h418268 == 2'b11) && + (guard__h418269 == 2'b01 || guard__h418269 == 2'b10 || + guard__h418269 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 = @@ -34818,34 +34818,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h418268 or + always@(guard__h418269 or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get) begin - case (guard__h418268) + case (guard__h418269) 2'b0, 2'b01, 2'b10: - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 2'd3: - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = - guard__h418268 != 2'b11 || + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 = + guard__h418269 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or - guard__h418268) + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or + guard__h418269) begin case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - CASE_guard18268_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; + CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = - (guard__h418268 == 2'b0) ? + (guard__h418269 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] : - guard__h418268 != 2'b01 && guard__h418268 != 2'b10 && - guard__h418268 != 2'b11 || + guard__h418269 != 2'b01 && guard__h418269 != 2'b10 && + guard__h418269 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 = @@ -34882,446 +34882,446 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]; endcase end - always@(guard__h446197 or - _theResult___fst_exp__h454245 or - out_exp__h454690 or _theResult___exp__h454687) + always@(guard__h446198 or + _theResult___fst_exp__h454246 or + out_exp__h454691 or _theResult___exp__h454688) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 = - _theResult___fst_exp__h454245; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 = + _theResult___fst_exp__h454246; 2'b10: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 = - out_exp__h454690; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 = + out_exp__h454691; 2'b11: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 = - _theResult___exp__h454687; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 = + _theResult___exp__h454688; endcase end - always@(guard__h446197 or - _theResult___fst_exp__h454245 or _theResult___exp__h454687) + always@(guard__h446198 or + _theResult___fst_exp__h454246 or _theResult___exp__h454688) begin - case (guard__h446197) + case (guard__h446198) 2'b0: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103 = - _theResult___fst_exp__h454245; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 = + _theResult___fst_exp__h454246; 2'b01, 2'b10, 2'b11: - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103 = - _theResult___exp__h454687; + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 = + _theResult___exp__h454688; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102 or - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103 or + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 or + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 or - _theResult___fst_exp__h454245) + _theResult___fst_exp__h454246) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h454765 = - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q102; + _theResult___fst_exp__h454766 = + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102; 3'd1: - _theResult___fst_exp__h454765 = - CASE_guard46197_0b0_theResult___fst_exp54245_0_ETC__q103; + _theResult___fst_exp__h454766 = + CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103; 3'd2: - _theResult___fst_exp__h454765 = + _theResult___fst_exp__h454766 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316; 3'd3: - _theResult___fst_exp__h454765 = + _theResult___fst_exp__h454766 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318; - 3'd4: _theResult___fst_exp__h454765 = _theResult___fst_exp__h454245; - default: _theResult___fst_exp__h454765 = 8'd0; + 3'd4: _theResult___fst_exp__h454766 = _theResult___fst_exp__h454246; + default: _theResult___fst_exp__h454766 = 8'd0; endcase end - always@(guard__h437490 or - _theResult___fst_exp__h445589 or - out_exp__h446108 or _theResult___exp__h446105) + always@(guard__h437491 or + _theResult___fst_exp__h445590 or + out_exp__h446109 or _theResult___exp__h446106) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 = - _theResult___fst_exp__h445589; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 = + _theResult___fst_exp__h445590; 2'b10: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 = - out_exp__h446108; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 = + out_exp__h446109; 2'b11: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 = - _theResult___exp__h446105; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 = + _theResult___exp__h446106; endcase end - always@(guard__h437490 or - _theResult___fst_exp__h445589 or _theResult___exp__h446105) + always@(guard__h437491 or + _theResult___fst_exp__h445590 or _theResult___exp__h446106) begin - case (guard__h437490) + case (guard__h437491) 2'b0: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105 = - _theResult___fst_exp__h445589; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 = + _theResult___fst_exp__h445590; 2'b01, 2'b10, 2'b11: - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105 = - _theResult___exp__h446105; + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 = + _theResult___exp__h446106; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104 or - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105 or + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 or + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 or - _theResult___fst_exp__h445589) + _theResult___fst_exp__h445590) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h446183 = - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q104; + _theResult___fst_exp__h446184 = + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104; 3'd1: - _theResult___fst_exp__h446183 = - CASE_guard37490_0b0_theResult___fst_exp45589_0_ETC__q105; + _theResult___fst_exp__h446184 = + CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105; 3'd2: - _theResult___fst_exp__h446183 = + _theResult___fst_exp__h446184 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094; 3'd3: - _theResult___fst_exp__h446183 = + _theResult___fst_exp__h446184 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097; - 3'd4: _theResult___fst_exp__h446183 = _theResult___fst_exp__h445589; - default: _theResult___fst_exp__h446183 = 8'd0; + 3'd4: _theResult___fst_exp__h446184 = _theResult___fst_exp__h445590; + default: _theResult___fst_exp__h446184 = 8'd0; endcase end - always@(guard__h455127 or - _theResult___fst_exp__h463355 or - out_exp__h463874 or _theResult___exp__h463871) + always@(guard__h455128 or + _theResult___fst_exp__h463356 or + out_exp__h463875 or _theResult___exp__h463872) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 = - _theResult___fst_exp__h463355; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 = + _theResult___fst_exp__h463356; 2'b10: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 = - out_exp__h463874; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 = + out_exp__h463875; 2'b11: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 = - _theResult___exp__h463871; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 = + _theResult___exp__h463872; endcase end - always@(guard__h455127 or - _theResult___fst_exp__h463355 or _theResult___exp__h463871) + always@(guard__h455128 or + _theResult___fst_exp__h463356 or _theResult___exp__h463872) begin - case (guard__h455127) + case (guard__h455128) 2'b0: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111 = - _theResult___fst_exp__h463355; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 = + _theResult___fst_exp__h463356; 2'b01, 2'b10, 2'b11: - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111 = - _theResult___exp__h463871; + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 = + _theResult___exp__h463872; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110 or - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111 or + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 or + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 or - _theResult___fst_exp__h463355) + _theResult___fst_exp__h463356) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h463949 = - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q110; + _theResult___fst_exp__h463950 = + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110; 3'd1: - _theResult___fst_exp__h463949 = - CASE_guard55127_0b0_theResult___fst_exp63355_0_ETC__q111; + _theResult___fst_exp__h463950 = + CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111; 3'd2: - _theResult___fst_exp__h463949 = + _theResult___fst_exp__h463950 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641; 3'd3: - _theResult___fst_exp__h463949 = + _theResult___fst_exp__h463950 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643; - 3'd4: _theResult___fst_exp__h463949 = _theResult___fst_exp__h463355; - default: _theResult___fst_exp__h463949 = 8'd0; + 3'd4: _theResult___fst_exp__h463950 = _theResult___fst_exp__h463356; + default: _theResult___fst_exp__h463950 = 8'd0; endcase end - always@(guard__h463963 or - _theResult___fst_exp__h472040 or - out_exp__h472510 or _theResult___exp__h472507) + always@(guard__h463964 or + _theResult___fst_exp__h472041 or + out_exp__h472511 or _theResult___exp__h472508) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 = - _theResult___fst_exp__h472040; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 = + _theResult___fst_exp__h472041; 2'b10: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 = - out_exp__h472510; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 = + out_exp__h472511; 2'b11: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 = - _theResult___exp__h472507; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 = + _theResult___exp__h472508; endcase end - always@(guard__h463963 or - _theResult___fst_exp__h472040 or _theResult___exp__h472507) + always@(guard__h463964 or + _theResult___fst_exp__h472041 or _theResult___exp__h472508) begin - case (guard__h463963) + case (guard__h463964) 2'b0: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116 = - _theResult___fst_exp__h472040; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 = + _theResult___fst_exp__h472041; 2'b01, 2'b10, 2'b11: - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116 = - _theResult___exp__h472507; + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 = + _theResult___exp__h472508; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115 or - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116 or + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 or + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 or - _theResult___fst_exp__h472040) + _theResult___fst_exp__h472041) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_exp__h472585 = - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q115; + _theResult___fst_exp__h472586 = + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115; 3'd1: - _theResult___fst_exp__h472585 = - CASE_guard63963_0b0_theResult___fst_exp72040_0_ETC__q116; + _theResult___fst_exp__h472586 = + CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116; 3'd2: - _theResult___fst_exp__h472585 = + _theResult___fst_exp__h472586 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710; 3'd3: - _theResult___fst_exp__h472585 = + _theResult___fst_exp__h472586 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712; - 3'd4: _theResult___fst_exp__h472585 = _theResult___fst_exp__h472040; - default: _theResult___fst_exp__h472585 = 8'd0; + 3'd4: _theResult___fst_exp__h472586 = _theResult___fst_exp__h472041; + default: _theResult___fst_exp__h472586 = 8'd0; endcase end - always@(guard__h446197 or - _theResult___snd__h454196 or - out_sfd__h454691 or _theResult___sfd__h454688) + always@(guard__h446198 or + _theResult___snd__h454197 or + out_sfd__h454692 or _theResult___sfd__h454689) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 = - _theResult___snd__h454196[56:34]; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 = + _theResult___snd__h454197[56:34]; 2'b10: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 = - out_sfd__h454691; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 = + out_sfd__h454692; 2'b11: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 = - _theResult___sfd__h454688; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 = + _theResult___sfd__h454689; endcase end - always@(guard__h446197 or - _theResult___snd__h454196 or _theResult___sfd__h454688) + always@(guard__h446198 or + _theResult___snd__h454197 or _theResult___sfd__h454689) begin - case (guard__h446197) + case (guard__h446198) 2'b0: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118 = - _theResult___snd__h454196[56:34]; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 = + _theResult___snd__h454197[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118 = - _theResult___sfd__h454688; + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 = + _theResult___sfd__h454689; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117 or - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118 or + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 or + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 or - _theResult___snd__h454196) + _theResult___snd__h454197) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h454766 = - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q117; + _theResult___fst_sfd__h454767 = + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117; 3'd1: - _theResult___fst_sfd__h454766 = - CASE_guard46197_0b0_theResult___snd54196_BITS__ETC__q118; + _theResult___fst_sfd__h454767 = + CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118; 3'd2: - _theResult___fst_sfd__h454766 = + _theResult___fst_sfd__h454767 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760; 3'd3: - _theResult___fst_sfd__h454766 = + _theResult___fst_sfd__h454767 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762; - 3'd4: _theResult___fst_sfd__h454766 = _theResult___snd__h454196[56:34]; - default: _theResult___fst_sfd__h454766 = 23'd0; + 3'd4: _theResult___fst_sfd__h454767 = _theResult___snd__h454197[56:34]; + default: _theResult___fst_sfd__h454767 = 23'd0; endcase end - always@(guard__h437490 or - sfdin__h445583 or out_sfd__h446109 or _theResult___sfd__h446106) + always@(guard__h437491 or + sfdin__h445584 or out_sfd__h446110 or _theResult___sfd__h446107) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 = - sfdin__h445583[56:34]; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 = + sfdin__h445584[56:34]; 2'b10: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 = - out_sfd__h446109; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 = + out_sfd__h446110; 2'b11: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 = - _theResult___sfd__h446106; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 = + _theResult___sfd__h446107; endcase end - always@(guard__h437490 or sfdin__h445583 or _theResult___sfd__h446106) + always@(guard__h437491 or sfdin__h445584 or _theResult___sfd__h446107) begin - case (guard__h437490) + case (guard__h437491) 2'b0: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120 = - sfdin__h445583[56:34]; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 = + sfdin__h445584[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120 = - _theResult___sfd__h446106; + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 = + _theResult___sfd__h446107; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119 or - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120 or + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 or + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 or IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 or - sfdin__h445583) + sfdin__h445584) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h446184 = - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q119; + _theResult___fst_sfd__h446185 = + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119; 3'd1: - _theResult___fst_sfd__h446184 = - CASE_guard37490_0b0_sfdin45583_BITS_56_TO_34_0_ETC__q120; + _theResult___fst_sfd__h446185 = + CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120; 3'd2: - _theResult___fst_sfd__h446184 = + _theResult___fst_sfd__h446185 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741; 3'd3: - _theResult___fst_sfd__h446184 = + _theResult___fst_sfd__h446185 = IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743; - 3'd4: _theResult___fst_sfd__h446184 = sfdin__h445583[56:34]; - default: _theResult___fst_sfd__h446184 = 23'd0; + 3'd4: _theResult___fst_sfd__h446185 = sfdin__h445584[56:34]; + default: _theResult___fst_sfd__h446185 = 23'd0; endcase end - always@(guard__h455127 or - sfdin__h463349 or out_sfd__h463875 or _theResult___sfd__h463872) + always@(guard__h455128 or + sfdin__h463350 or out_sfd__h463876 or _theResult___sfd__h463873) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 = - sfdin__h463349[56:34]; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 = + sfdin__h463350[56:34]; 2'b10: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 = - out_sfd__h463875; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 = + out_sfd__h463876; 2'b11: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 = - _theResult___sfd__h463872; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 = + _theResult___sfd__h463873; endcase end - always@(guard__h455127 or sfdin__h463349 or _theResult___sfd__h463872) + always@(guard__h455128 or sfdin__h463350 or _theResult___sfd__h463873) begin - case (guard__h455127) + case (guard__h455128) 2'b0: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122 = - sfdin__h463349[56:34]; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 = + sfdin__h463350[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122 = - _theResult___sfd__h463872; + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 = + _theResult___sfd__h463873; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121 or - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122 or + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 or + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 or IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 or - sfdin__h463349) + sfdin__h463350) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h463950 = - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q121; + _theResult___fst_sfd__h463951 = + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121; 3'd1: - _theResult___fst_sfd__h463950 = - CASE_guard55127_0b0_sfdin63349_BITS_56_TO_34_0_ETC__q122; + _theResult___fst_sfd__h463951 = + CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122; 3'd2: - _theResult___fst_sfd__h463950 = + _theResult___fst_sfd__h463951 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787; 3'd3: - _theResult___fst_sfd__h463950 = + _theResult___fst_sfd__h463951 = IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789; - 3'd4: _theResult___fst_sfd__h463950 = sfdin__h463349[56:34]; - default: _theResult___fst_sfd__h463950 = 23'd0; + 3'd4: _theResult___fst_sfd__h463951 = sfdin__h463350[56:34]; + default: _theResult___fst_sfd__h463951 = 23'd0; endcase end - always@(guard__h463963 or - _theResult___snd__h471986 or - out_sfd__h472511 or _theResult___sfd__h472508) + always@(guard__h463964 or + _theResult___snd__h471987 or + out_sfd__h472512 or _theResult___sfd__h472509) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 = - _theResult___snd__h471986[56:34]; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 = + _theResult___snd__h471987[56:34]; 2'b10: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 = - out_sfd__h472511; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 = + out_sfd__h472512; 2'b11: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 = - _theResult___sfd__h472508; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 = + _theResult___sfd__h472509; endcase end - always@(guard__h463963 or - _theResult___snd__h471986 or _theResult___sfd__h472508) + always@(guard__h463964 or + _theResult___snd__h471987 or _theResult___sfd__h472509) begin - case (guard__h463963) + case (guard__h463964) 2'b0: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124 = - _theResult___snd__h471986[56:34]; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 = + _theResult___snd__h471987[56:34]; 2'b01, 2'b10, 2'b11: - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124 = - _theResult___sfd__h472508; + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 = + _theResult___sfd__h472509; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123 or - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124 or + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 or + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or - _theResult___snd__h471986) + _theResult___snd__h471987) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: - _theResult___fst_sfd__h472586 = - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q123; + _theResult___fst_sfd__h472587 = + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123; 3'd1: - _theResult___fst_sfd__h472586 = - CASE_guard63963_0b0_theResult___snd71986_BITS__ETC__q124; + _theResult___fst_sfd__h472587 = + CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124; 3'd2: - _theResult___fst_sfd__h472586 = + _theResult___fst_sfd__h472587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806; 3'd3: - _theResult___fst_sfd__h472586 = + _theResult___fst_sfd__h472587 = IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808; - 3'd4: _theResult___fst_sfd__h472586 = _theResult___snd__h471986[56:34]; - default: _theResult___fst_sfd__h472586 = 23'd0; + 3'd4: _theResult___fst_sfd__h472587 = _theResult___snd__h471987[56:34]; + default: _theResult___fst_sfd__h472587 = 23'd0; endcase end - always@(guard__h437490 or + always@(guard__h437491 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01, 2'b10: - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = - guard__h437490 == 2'b11 && + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 = + guard__h437491 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or - guard__h437490) + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or + guard__h437491) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - CASE_guard37490_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; + CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = - (guard__h437490 == 2'b0) ? + (guard__h437491 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h437490 == 2'b01 || guard__h437490 == 2'b10 || - guard__h437490 == 2'b11) && + (guard__h437491 == 2'b01 || guard__h437491 == 2'b10 || + guard__h437491 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 = @@ -35332,34 +35332,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h446197 or + always@(guard__h446198 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01, 2'b10: - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = - guard__h446197 == 2'b11 && + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 = + guard__h446198 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or - guard__h446197) + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or + guard__h446198) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - CASE_guard46197_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; + CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = - (guard__h446197 == 2'b0) ? + (guard__h446198 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h446197 == 2'b01 || guard__h446197 == 2'b10 || - guard__h446197 == 2'b11) && + (guard__h446198 == 2'b01 || guard__h446198 == 2'b10 || + guard__h446198 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 = @@ -35370,34 +35370,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h437490 or + always@(guard__h437491 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h437490) + case (guard__h437491) 2'b0, 2'b01, 2'b10: - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = - guard__h437490 != 2'b11 || + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 = + guard__h437491 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or - guard__h437490) + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127 or + guard__h437491) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - CASE_guard37490_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; + CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q127; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = - (guard__h437490 == 2'b0) ? + (guard__h437491 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h437490 != 2'b01 && guard__h437490 != 2'b10 && - guard__h437490 != 2'b11 || + guard__h437491 != 2'b01 && guard__h437491 != 2'b10 && + guard__h437491 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 = @@ -35408,34 +35408,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h446197 or + always@(guard__h446198 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h446197) + case (guard__h446198) 2'b0, 2'b01, 2'b10: - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = - guard__h446197 != 2'b11 || + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 = + guard__h446198 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or - guard__h446197) + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or + guard__h446198) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - CASE_guard46197_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; + CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = - (guard__h446197 == 2'b0) ? + (guard__h446198 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h446197 != 2'b01 && guard__h446197 != 2'b10 && - guard__h446197 != 2'b11 || + guard__h446198 != 2'b01 && guard__h446198 != 2'b10 && + guard__h446198 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 = @@ -35446,34 +35446,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455127 or + always@(guard__h455128 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01, 2'b10: - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = - guard__h455127 == 2'b11 && + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 = + guard__h455128 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or - guard__h455127) + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or + guard__h455128) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - CASE_guard55127_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; + CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = - (guard__h455127 == 2'b0) ? + (guard__h455128 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h455127 == 2'b01 || guard__h455127 == 2'b10 || - guard__h455127 == 2'b11) && + (guard__h455128 == 2'b01 || guard__h455128 == 2'b10 || + guard__h455128 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 = @@ -35484,34 +35484,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h455127 or + always@(guard__h455128 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h455127) + case (guard__h455128) 2'b0, 2'b01, 2'b10: - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = - guard__h455127 != 2'b11 || + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 = + guard__h455128 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or - guard__h455127) + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or + guard__h455128) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - CASE_guard55127_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; + CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = - (guard__h455127 == 2'b0) ? + (guard__h455128 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h455127 != 2'b01 && guard__h455127 != 2'b10 && - guard__h455127 != 2'b11 || + guard__h455128 != 2'b01 && guard__h455128 != 2'b10 && + guard__h455128 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 = @@ -35522,34 +35522,34 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463963 or + always@(guard__h463964 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01, 2'b10: - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = - guard__h463963 == 2'b11 && + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 = + guard__h463964 == 2'b11 && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or - guard__h463963) + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or + guard__h463964) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - CASE_guard63963_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; + CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = - (guard__h463963 == 2'b0) ? + (guard__h463964 == 2'b0) ? coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - (guard__h463963 == 2'b01 || guard__h463963 == 2'b10 || - guard__h463963 == 2'b11) && + (guard__h463964 == 2'b01 || guard__h463964 == 2'b10 || + guard__h463964 == 2'b11) && coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 = @@ -35560,34 +35560,34 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end - always@(guard__h463963 or + always@(guard__h463964 or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get) begin - case (guard__h463963) + case (guard__h463964) 2'b0, 2'b01, 2'b10: - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 2'd3: - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = - guard__h463963 != 2'b11 || + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 = + guard__h463964 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; endcase end always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or - guard__h463963) + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or + guard__h463964) begin case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40]) 3'd0: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - CASE_guard63963_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; + CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132; 3'd1: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = - (guard__h463963 == 2'b0) ? + (guard__h463964 == 2'b0) ? !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] : - guard__h463963 != 2'b01 && guard__h463963 != 2'b10 && - guard__h463963 != 2'b11 || + guard__h463964 != 2'b01 && guard__h463964 != 2'b10 && + guard__h463964 != 2'b11 || !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]; 3'd2, 3'd3: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 = @@ -35644,28 +35644,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put; endcase end - always@(guard__h493568 or - _theResult___fst_exp__h501529 or _theResult___exp__h502184) + always@(guard__h493569 or + _theResult___fst_exp__h501530 or _theResult___exp__h502185) begin - case (guard__h493568) + case (guard__h493569) 2'b0: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143 = - _theResult___fst_exp__h501529; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143 = + _theResult___fst_exp__h501530; 2'b01, 2'b10, 2'b11: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143 = - _theResult___exp__h502184; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143 = + _theResult___exp__h502185; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h501529 or + _theResult___fst_exp__h501530 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 or - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143) + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - _theResult___fst_exp__h501529; + _theResult___fst_exp__h501530; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015; @@ -35674,44 +35674,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q143; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 = 11'd0; endcase end - always@(guard__h493568 or - _theResult___fst_exp__h501529 or - out_exp__h502187 or _theResult___exp__h502184) + always@(guard__h493569 or + _theResult___fst_exp__h501530 or + out_exp__h502188 or _theResult___exp__h502185) begin - case (guard__h493568) + case (guard__h493569) 2'b0, 2'b01: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 = - _theResult___fst_exp__h501529; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 = + _theResult___fst_exp__h501530; 2'b10: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 = - out_exp__h502187; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 = + out_exp__h502188; 2'b11: - CASE_guard93568_0b0_theResult___fst_exp01529_0_ETC__q144 = - _theResult___exp__h502184; + CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 = + _theResult___exp__h502185; endcase end - always@(guard__h493568 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h493569 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h493568) + case (guard__h493569) 2'b0, 2'b01, 2'b10: - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard93568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = - guard__h493568 == 2'b11 && + CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 = + guard__h493569 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493568) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493569) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35721,12 +35721,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 = - (guard__h493568 == 2'b0) ? + (guard__h493569 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h493568 == 2'b01 || guard__h493568 == 2'b10 || - guard__h493568 == 2'b11) && + (guard__h493569 == 2'b01 || guard__h493569 == 2'b10 || + guard__h493569 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35737,23 +35737,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h511949 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h511950 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h511949) + case (guard__h511950) 2'b0, 2'b01, 2'b10: - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard11949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = - guard__h511949 == 2'b11 && + CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 = + guard__h511950 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511949) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511950) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35763,12 +35763,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 = - (guard__h511949 == 2'b0) ? + (guard__h511950 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h511949 == 2'b01 || guard__h511949 == 2'b10 || - guard__h511949 == 2'b11) && + (guard__h511950 == 2'b01 || guard__h511950 == 2'b10 || + guard__h511950 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35779,23 +35779,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h502880 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h502881 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h502880) + case (guard__h502881) 2'b0, 2'b01, 2'b10: - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 2'd3: - CASE_guard02880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = - guard__h502880 == 2'b11 && + CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 = + guard__h502881 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502880) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502881) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35805,12 +35805,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 = - (guard__h502880 == 2'b0) ? + (guard__h502881 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171] : - (guard__h502880 == 2'b01 || guard__h502880 == 2'b10 || - guard__h502880 == 2'b11) && + (guard__h502881 == 2'b01 || guard__h502881 == 2'b10 || + guard__h502881 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[171]; @@ -35821,28 +35821,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[171]; endcase end - always@(guard__h571725 or - _theResult___fst_exp__h579686 or _theResult___exp__h580341) + always@(guard__h571726 or + _theResult___fst_exp__h579687 or _theResult___exp__h580342) begin - case (guard__h571725) + case (guard__h571726) 2'b0: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160 = - _theResult___fst_exp__h579686; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160 = + _theResult___fst_exp__h579687; 2'b01, 2'b10, 2'b11: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160 = - _theResult___exp__h580341; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160 = + _theResult___exp__h580342; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h579686 or + _theResult___fst_exp__h579687 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 or - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160) + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - _theResult___fst_exp__h579686; + _theResult___fst_exp__h579687; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730; @@ -35851,42 +35851,42 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q160; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 = 11'd0; endcase end - always@(guard__h571725 or - _theResult___fst_exp__h579686 or - out_exp__h580344 or _theResult___exp__h580341) + always@(guard__h571726 or + _theResult___fst_exp__h579687 or + out_exp__h580345 or _theResult___exp__h580342) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 = - _theResult___fst_exp__h579686; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 = + _theResult___fst_exp__h579687; 2'b10: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 = - out_exp__h580344; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 = + out_exp__h580345; 2'b11: - CASE_guard71725_0b0_theResult___fst_exp79686_0_ETC__q161 = - _theResult___exp__h580341; + CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 = + _theResult___exp__h580342; endcase end - always@(guard__h571725 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71725_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = - guard__h571725 == 2'b11 && + CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 = + guard__h571726 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571725) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35895,12 +35895,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 = - (guard__h571725 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h571725 == 2'b01 || guard__h571725 == 2'b10 || - guard__h571725 == 2'b11) && + (guard__h571726 == 2'b01 || guard__h571726 == 2'b10 || + guard__h571726 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35911,21 +35911,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581037 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81037_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = - guard__h581037 == 2'b11 && + CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 = + guard__h581038 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581037) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35934,12 +35934,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 = - (guard__h581037 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h581037 == 2'b01 || guard__h581037 == 2'b10 || - guard__h581037 == 2'b11) && + (guard__h581038 == 2'b01 || guard__h581038 == 2'b10 || + guard__h581038 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35950,21 +35950,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590106 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590107 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01, 2'b10: - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90106_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = - guard__h590106 == 2'b11 && + CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 = + guard__h590107 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590106) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590107) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -35973,12 +35973,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 = - (guard__h590106 == 2'b0) ? + (guard__h590107 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - (guard__h590106 == 2'b01 || guard__h590106 == 2'b10 || - guard__h590106 == 2'b11) && + (guard__h590107 == 2'b01 || guard__h590107 == 2'b10 || + guard__h590107 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -35989,21 +35989,21 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h581037 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01, 2'b10: - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard81037_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = - guard__h581037 != 2'b11 || + CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 = + guard__h581038 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581037) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36012,12 +36012,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 = - (guard__h581037 == 2'b0) ? + (guard__h581038 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h581037 != 2'b01 && guard__h581037 != 2'b10 && - guard__h581037 != 2'b11 || + guard__h581038 != 2'b01 && guard__h581038 != 2'b10 && + guard__h581038 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36028,21 +36028,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h590106 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h590107 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01, 2'b10: - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard90106_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = - guard__h590106 != 2'b11 || + CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 = + guard__h590107 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590106) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590107) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36051,12 +36051,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 = - (guard__h590106 == 2'b0) ? + (guard__h590107 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h590106 != 2'b01 && guard__h590106 != 2'b10 && - guard__h590106 != 2'b11 || + guard__h590107 != 2'b01 && guard__h590107 != 2'b10 && + guard__h590107 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36067,21 +36067,21 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h571725 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01, 2'b10: - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 2'd3: - CASE_guard71725_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = - guard__h571725 != 2'b11 || + CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 = + guard__h571726 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571725) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36090,12 +36090,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 = - (guard__h571725 == 2'b0) ? + (guard__h571726 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43] : - guard__h571725 != 2'b01 && guard__h571725 != 2'b10 && - guard__h571725 != 2'b11 || + guard__h571726 != 2'b01 && guard__h571726 != 2'b10 && + guard__h571726 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; @@ -36106,28 +36106,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[43]; endcase end - always@(guard__h532421 or - _theResult___fst_exp__h540382 or _theResult___exp__h541037) + always@(guard__h532422 or + _theResult___fst_exp__h540383 or _theResult___exp__h541038) begin - case (guard__h532421) + case (guard__h532422) 2'b0: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183 = - _theResult___fst_exp__h540382; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183 = + _theResult___fst_exp__h540383; 2'b01, 2'b10, 2'b11: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183 = - _theResult___exp__h541037; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183 = + _theResult___exp__h541038; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h540382 or + _theResult___fst_exp__h540383 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 or - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183) + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - _theResult___fst_exp__h540382; + _theResult___fst_exp__h540383; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500; @@ -36136,49 +36136,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q183; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 = 11'd0; endcase end - always@(guard__h532421 or - _theResult___fst_exp__h540382 or - out_exp__h541040 or _theResult___exp__h541037) + always@(guard__h532422 or + _theResult___fst_exp__h540383 or + out_exp__h541041 or _theResult___exp__h541038) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 = - _theResult___fst_exp__h540382; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 = + _theResult___fst_exp__h540383; 2'b10: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 = - out_exp__h541040; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 = + out_exp__h541041; 2'b11: - CASE_guard32421_0b0_theResult___fst_exp40382_0_ETC__q184 = - _theResult___exp__h541037; + CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 = + _theResult___exp__h541038; endcase end - always@(guard__h541733 or - _theResult___fst_exp__h549959 or _theResult___exp__h550688) + always@(guard__h541734 or + _theResult___fst_exp__h549960 or _theResult___exp__h550689) begin - case (guard__h541733) + case (guard__h541734) 2'b0: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185 = - _theResult___fst_exp__h549959; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185 = + _theResult___fst_exp__h549960; 2'b01, 2'b10, 2'b11: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185 = - _theResult___exp__h550688; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185 = + _theResult___exp__h550689; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h549959 or + _theResult___fst_exp__h549960 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 or - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185) + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - _theResult___fst_exp__h549959; + _theResult___fst_exp__h549960; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538; @@ -36187,49 +36187,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q185; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 = 11'd0; endcase end - always@(guard__h541733 or - _theResult___fst_exp__h549959 or - out_exp__h550691 or _theResult___exp__h550688) + always@(guard__h541734 or + _theResult___fst_exp__h549960 or + out_exp__h550692 or _theResult___exp__h550689) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 = - _theResult___fst_exp__h549959; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 = + _theResult___fst_exp__h549960; 2'b10: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 = - out_exp__h550691; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 = + out_exp__h550692; 2'b11: - CASE_guard41733_0b0_theResult___fst_exp49959_0_ETC__q186 = - _theResult___exp__h550688; + CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 = + _theResult___exp__h550689; endcase end - always@(guard__h550802 or - _theResult___fst_exp__h558792 or _theResult___exp__h559472) + always@(guard__h550803 or + _theResult___fst_exp__h558793 or _theResult___exp__h559473) begin - case (guard__h550802) + case (guard__h550803) 2'b0: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187 = - _theResult___fst_exp__h558792; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187 = + _theResult___fst_exp__h558793; 2'b01, 2'b10, 2'b11: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187 = - _theResult___exp__h559472; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187 = + _theResult___exp__h559473; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h558792 or + _theResult___fst_exp__h558793 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187) + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - _theResult___fst_exp__h558792; + _theResult___fst_exp__h558793; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569; @@ -36238,49 +36238,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q187; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 = 11'd0; endcase end - always@(guard__h550802 or - _theResult___fst_exp__h558792 or - out_exp__h559475 or _theResult___exp__h559472) + always@(guard__h550803 or + _theResult___fst_exp__h558793 or + out_exp__h559476 or _theResult___exp__h559473) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 = - _theResult___fst_exp__h558792; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 = + _theResult___fst_exp__h558793; 2'b10: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 = - out_exp__h559475; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 = + out_exp__h559476; 2'b11: - CASE_guard50802_0b0_theResult___fst_exp58792_0_ETC__q188 = - _theResult___exp__h559472; + CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 = + _theResult___exp__h559473; endcase end - always@(guard__h581037 or - _theResult___fst_exp__h589263 or _theResult___exp__h589992) + always@(guard__h581038 or + _theResult___fst_exp__h589264 or _theResult___exp__h589993) begin - case (guard__h581037) + case (guard__h581038) 2'b0: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189 = - _theResult___fst_exp__h589263; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189 = + _theResult___fst_exp__h589264; 2'b01, 2'b10, 2'b11: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189 = - _theResult___exp__h589992; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189 = + _theResult___exp__h589993; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h589263 or + _theResult___fst_exp__h589264 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189) + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - _theResult___fst_exp__h589263; + _theResult___fst_exp__h589264; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768; @@ -36289,49 +36289,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q189; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 = 11'd0; endcase end - always@(guard__h581037 or - _theResult___fst_exp__h589263 or - out_exp__h589995 or _theResult___exp__h589992) + always@(guard__h581038 or + _theResult___fst_exp__h589264 or + out_exp__h589996 or _theResult___exp__h589993) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 = - _theResult___fst_exp__h589263; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 = + _theResult___fst_exp__h589264; 2'b10: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 = - out_exp__h589995; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 = + out_exp__h589996; 2'b11: - CASE_guard81037_0b0_theResult___fst_exp89263_0_ETC__q190 = - _theResult___exp__h589992; + CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 = + _theResult___exp__h589993; endcase end - always@(guard__h590106 or - _theResult___fst_exp__h598096 or _theResult___exp__h598776) + always@(guard__h590107 or + _theResult___fst_exp__h598097 or _theResult___exp__h598777) begin - case (guard__h590106) + case (guard__h590107) 2'b0: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191 = - _theResult___fst_exp__h598096; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = + _theResult___fst_exp__h598097; 2'b01, 2'b10, 2'b11: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191 = - _theResult___exp__h598776; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 = + _theResult___exp__h598777; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h598096 or + _theResult___fst_exp__h598097 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191) + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - _theResult___fst_exp__h598096; + _theResult___fst_exp__h598097; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799; @@ -36340,44 +36340,44 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q191; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 = 11'd0; endcase end - always@(guard__h590106 or - _theResult___fst_exp__h598096 or - out_exp__h598779 or _theResult___exp__h598776) + always@(guard__h590107 or + _theResult___fst_exp__h598097 or + out_exp__h598780 or _theResult___exp__h598777) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 = - _theResult___fst_exp__h598096; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = + _theResult___fst_exp__h598097; 2'b10: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 = - out_exp__h598779; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = + out_exp__h598780; 2'b11: - CASE_guard90106_0b0_theResult___fst_exp98096_0_ETC__q192 = - _theResult___exp__h598776; + CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 = + _theResult___exp__h598777; endcase end - always@(guard__h532421 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01, 2'b10: - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32421_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = - guard__h532421 == 2'b11 && + CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 = + guard__h532422 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532421) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36387,12 +36387,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 = - (guard__h532421 == 2'b0) ? + (guard__h532422 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h532421 == 2'b01 || guard__h532421 == 2'b10 || - guard__h532421 == 2'b11) && + (guard__h532422 == 2'b01 || guard__h532422 == 2'b10 || + guard__h532422 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36403,23 +36403,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541733 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541734 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41733_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = - guard__h541733 == 2'b11 && + CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 = + guard__h541734 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541733) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541734) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36429,12 +36429,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 = - (guard__h541733 == 2'b0) ? + (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h541733 == 2'b01 || guard__h541733 == 2'b10 || - guard__h541733 == 2'b11) && + (guard__h541734 == 2'b01 || guard__h541734 == 2'b10 || + guard__h541734 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36445,23 +36445,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550802 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50802_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = - guard__h550802 == 2'b11 && + CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 = + guard__h550803 == 2'b11 && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550802) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550803) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36471,12 +36471,12 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 = - (guard__h550802 == 2'b0) ? + (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - (guard__h550802 == 2'b01 || guard__h550802 == 2'b10 || - guard__h550802 == 2'b11) && + (guard__h550803 == 2'b01 || guard__h550803 == 2'b10 || + guard__h550803 == 2'b11) && coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] == 32'hFFFFFFFF && coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36487,23 +36487,23 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h541733 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h541734 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01, 2'b10: - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard41733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = - guard__h541733 != 2'b11 || + CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 = + guard__h541734 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541733) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541734) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36513,12 +36513,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 = - (guard__h541733 == 2'b0) ? + (guard__h541734 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h541733 != 2'b01 && guard__h541733 != 2'b10 && - guard__h541733 != 2'b11 || + guard__h541734 != 2'b01 && guard__h541734 != 2'b10 && + guard__h541734 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36529,23 +36529,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h550802 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01, 2'b10: - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard50802_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = - guard__h550802 != 2'b11 || + CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 = + guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550802) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550803) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36555,12 +36555,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 = - (guard__h550802 == 2'b0) ? + (guard__h550803 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h550802 != 2'b01 && guard__h550802 != 2'b10 && - guard__h550802 != 2'b11 || + guard__h550803 != 2'b01 && guard__h550803 != 2'b10 && + guard__h550803 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36571,23 +36571,23 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532421 or coreFix_fpuMulDivExe_0_regToExeQ$first) + always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01, 2'b10: - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 2'd3: - CASE_guard32421_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = - guard__h532421 != 2'b11 || + CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 = + guard__h532422 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532421) + always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd2, 3'd3: @@ -36597,12 +36597,12 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; 3'd4: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 = - (guard__h532421 == 2'b0) ? + (guard__h532422 == 2'b0) ? coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107] : - guard__h532421 != 2'b01 && guard__h532421 != 2'b10 && - guard__h532421 != 2'b11 || + guard__h532422 != 2'b01 && guard__h532422 != 2'b10 && + guard__h532422 != 2'b11 || coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] != 32'hFFFFFFFF || !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; @@ -36613,28 +36613,28 @@ module mkCore(CLK, !coreFix_fpuMulDivExe_0_regToExeQ$first[107]; endcase end - always@(guard__h532421 or - _theResult___snd__h540333 or _theResult___sfd__h541038) + always@(guard__h532422 or + _theResult___snd__h540334 or _theResult___sfd__h541039) begin - case (guard__h532421) + case (guard__h532422) 2'b0: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205 = - _theResult___snd__h540333[56:5]; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205 = + _theResult___snd__h540334[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205 = - _theResult___sfd__h541038; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205 = + _theResult___sfd__h541039; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h540333 or + _theResult___snd__h540334 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 or - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205) + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - _theResult___snd__h540333[56:5]; + _theResult___snd__h540334[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595; @@ -36643,48 +36643,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q205; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 = 52'd0; endcase end - always@(guard__h532421 or - _theResult___snd__h540333 or - out_sfd__h541041 or _theResult___sfd__h541038) + always@(guard__h532422 or + _theResult___snd__h540334 or + out_sfd__h541042 or _theResult___sfd__h541039) begin - case (guard__h532421) + case (guard__h532422) 2'b0, 2'b01: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 = - _theResult___snd__h540333[56:5]; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 = + _theResult___snd__h540334[56:5]; 2'b10: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 = - out_sfd__h541041; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 = + out_sfd__h541042; 2'b11: - CASE_guard32421_0b0_theResult___snd40333_BITS__ETC__q206 = - _theResult___sfd__h541038; + CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 = + _theResult___sfd__h541039; endcase end - always@(guard__h541733 or sfdin__h549953 or _theResult___sfd__h550689) + always@(guard__h541734 or sfdin__h549954 or _theResult___sfd__h550690) begin - case (guard__h541733) + case (guard__h541734) 2'b0: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207 = - sfdin__h549953[56:5]; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = + sfdin__h549954[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207 = - _theResult___sfd__h550689; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 = + _theResult___sfd__h550690; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h549953 or + sfdin__h549954 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207) + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - sfdin__h549953[56:5]; + sfdin__h549954[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621; @@ -36693,48 +36693,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q207; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 = 52'd0; endcase end - always@(guard__h541733 or - sfdin__h549953 or out_sfd__h550692 or _theResult___sfd__h550689) + always@(guard__h541734 or + sfdin__h549954 or out_sfd__h550693 or _theResult___sfd__h550690) begin - case (guard__h541733) + case (guard__h541734) 2'b0, 2'b01: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 = - sfdin__h549953[56:5]; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = + sfdin__h549954[56:5]; 2'b10: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 = - out_sfd__h550692; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = + out_sfd__h550693; 2'b11: - CASE_guard41733_0b0_sfdin49953_BITS_56_TO_5_0b_ETC__q208 = - _theResult___sfd__h550689; + CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 = + _theResult___sfd__h550690; endcase end - always@(guard__h550802 or - _theResult___snd__h558738 or _theResult___sfd__h559473) + always@(guard__h550803 or + _theResult___snd__h558739 or _theResult___sfd__h559474) begin - case (guard__h550802) + case (guard__h550803) 2'b0: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209 = - _theResult___snd__h558738[56:5]; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___snd__h558739[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209 = - _theResult___sfd__h559473; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 = + _theResult___sfd__h559474; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h558738 or + _theResult___snd__h558739 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209) + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - _theResult___snd__h558738[56:5]; + _theResult___snd__h558739[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640; @@ -36743,49 +36743,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q209; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 = 52'd0; endcase end - always@(guard__h550802 or - _theResult___snd__h558738 or - out_sfd__h559476 or _theResult___sfd__h559473) + always@(guard__h550803 or + _theResult___snd__h558739 or + out_sfd__h559477 or _theResult___sfd__h559474) begin - case (guard__h550802) + case (guard__h550803) 2'b0, 2'b01: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 = - _theResult___snd__h558738[56:5]; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___snd__h558739[56:5]; 2'b10: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 = - out_sfd__h559476; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + out_sfd__h559477; 2'b11: - CASE_guard50802_0b0_theResult___snd58738_BITS__ETC__q210 = - _theResult___sfd__h559473; + CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 = + _theResult___sfd__h559474; endcase end - always@(guard__h502880 or - _theResult___fst_exp__h511106 or _theResult___exp__h511835) + always@(guard__h502881 or + _theResult___fst_exp__h511107 or _theResult___exp__h511836) begin - case (guard__h502880) + case (guard__h502881) 2'b0: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211 = - _theResult___fst_exp__h511106; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211 = + _theResult___fst_exp__h511107; 2'b01, 2'b10, 2'b11: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211 = - _theResult___exp__h511835; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211 = + _theResult___exp__h511836; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h511106 or + _theResult___fst_exp__h511107 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 or - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211) + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - _theResult___fst_exp__h511106; + _theResult___fst_exp__h511107; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058; @@ -36794,49 +36794,49 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q211; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 = 11'd0; endcase end - always@(guard__h502880 or - _theResult___fst_exp__h511106 or - out_exp__h511838 or _theResult___exp__h511835) + always@(guard__h502881 or + _theResult___fst_exp__h511107 or + out_exp__h511839 or _theResult___exp__h511836) begin - case (guard__h502880) + case (guard__h502881) 2'b0, 2'b01: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 = - _theResult___fst_exp__h511106; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 = + _theResult___fst_exp__h511107; 2'b10: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 = - out_exp__h511838; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 = + out_exp__h511839; 2'b11: - CASE_guard02880_0b0_theResult___fst_exp11106_0_ETC__q212 = - _theResult___exp__h511835; + CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 = + _theResult___exp__h511836; endcase end - always@(guard__h511949 or - _theResult___fst_exp__h519939 or _theResult___exp__h520619) + always@(guard__h511950 or + _theResult___fst_exp__h519940 or _theResult___exp__h520620) begin - case (guard__h511949) + case (guard__h511950) 2'b0: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213 = - _theResult___fst_exp__h519939; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213 = + _theResult___fst_exp__h519940; 2'b01, 2'b10, 2'b11: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213 = - _theResult___exp__h520619; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213 = + _theResult___exp__h520620; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___fst_exp__h519939 or + _theResult___fst_exp__h519940 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 or - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213) + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - _theResult___fst_exp__h519939; + _theResult___fst_exp__h519940; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089; @@ -36845,49 +36845,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q213; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 = 11'd0; endcase end - always@(guard__h511949 or - _theResult___fst_exp__h519939 or - out_exp__h520622 or _theResult___exp__h520619) + always@(guard__h511950 or + _theResult___fst_exp__h519940 or + out_exp__h520623 or _theResult___exp__h520620) begin - case (guard__h511949) + case (guard__h511950) 2'b0, 2'b01: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 = - _theResult___fst_exp__h519939; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 = + _theResult___fst_exp__h519940; 2'b10: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 = - out_exp__h520622; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 = + out_exp__h520623; 2'b11: - CASE_guard11949_0b0_theResult___fst_exp19939_0_ETC__q214 = - _theResult___exp__h520619; + CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 = + _theResult___exp__h520620; endcase end - always@(guard__h493568 or - _theResult___snd__h501480 or _theResult___sfd__h502185) + always@(guard__h493569 or + _theResult___snd__h501481 or _theResult___sfd__h502186) begin - case (guard__h493568) + case (guard__h493569) 2'b0: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215 = - _theResult___snd__h501480[56:5]; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = + _theResult___snd__h501481[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215 = - _theResult___sfd__h502185; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 = + _theResult___sfd__h502186; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h501480 or + _theResult___snd__h501481 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215) + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - _theResult___snd__h501480[56:5]; + _theResult___snd__h501481[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115; @@ -36896,48 +36896,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q215; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 = 52'd0; endcase end - always@(guard__h493568 or - _theResult___snd__h501480 or - out_sfd__h502188 or _theResult___sfd__h502185) + always@(guard__h493569 or + _theResult___snd__h501481 or + out_sfd__h502189 or _theResult___sfd__h502186) begin - case (guard__h493568) + case (guard__h493569) 2'b0, 2'b01: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 = - _theResult___snd__h501480[56:5]; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = + _theResult___snd__h501481[56:5]; 2'b10: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 = - out_sfd__h502188; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = + out_sfd__h502189; 2'b11: - CASE_guard93568_0b0_theResult___snd01480_BITS__ETC__q216 = - _theResult___sfd__h502185; + CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 = + _theResult___sfd__h502186; endcase end - always@(guard__h502880 or sfdin__h511100 or _theResult___sfd__h511836) + always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837) begin - case (guard__h502880) + case (guard__h502881) 2'b0: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217 = - sfdin__h511100[56:5]; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217 = + sfdin__h511101[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217 = - _theResult___sfd__h511836; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217 = + _theResult___sfd__h511837; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h511100 or + sfdin__h511101 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217) + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - sfdin__h511100[56:5]; + sfdin__h511101[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142; @@ -36946,48 +36946,48 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q217; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q217; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 = 52'd0; endcase end - always@(guard__h502880 or - sfdin__h511100 or out_sfd__h511839 or _theResult___sfd__h511836) + always@(guard__h502881 or + sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837) begin - case (guard__h502880) + case (guard__h502881) 2'b0, 2'b01: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 = - sfdin__h511100[56:5]; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 = + sfdin__h511101[56:5]; 2'b10: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 = - out_sfd__h511839; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 = + out_sfd__h511840; 2'b11: - CASE_guard02880_0b0_sfdin11100_BITS_56_TO_5_0b_ETC__q218 = - _theResult___sfd__h511836; + CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q218 = + _theResult___sfd__h511837; endcase end - always@(guard__h511949 or - _theResult___snd__h519885 or _theResult___sfd__h520620) + always@(guard__h511950 or + _theResult___snd__h519886 or _theResult___sfd__h520621) begin - case (guard__h511949) + case (guard__h511950) 2'b0: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219 = - _theResult___snd__h519885[56:5]; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + _theResult___snd__h519886[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219 = - _theResult___sfd__h520620; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219 = + _theResult___sfd__h520621; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h519885 or + _theResult___snd__h519886 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219) + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - _theResult___snd__h519885[56:5]; + _theResult___snd__h519886[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161; @@ -36996,49 +36996,49 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q219; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q219; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 = 52'd0; endcase end - always@(guard__h511949 or - _theResult___snd__h519885 or - out_sfd__h520623 or _theResult___sfd__h520620) + always@(guard__h511950 or + _theResult___snd__h519886 or + out_sfd__h520624 or _theResult___sfd__h520621) begin - case (guard__h511949) + case (guard__h511950) 2'b0, 2'b01: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 = - _theResult___snd__h519885[56:5]; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + _theResult___snd__h519886[56:5]; 2'b10: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 = - out_sfd__h520623; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + out_sfd__h520624; 2'b11: - CASE_guard11949_0b0_theResult___snd19885_BITS__ETC__q220 = - _theResult___sfd__h520620; + CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q220 = + _theResult___sfd__h520621; endcase end - always@(guard__h571725 or - _theResult___snd__h579637 or _theResult___sfd__h580342) + always@(guard__h571726 or + _theResult___snd__h579638 or _theResult___sfd__h580343) begin - case (guard__h571725) + case (guard__h571726) 2'b0: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221 = - _theResult___snd__h579637[56:5]; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221 = + _theResult___snd__h579638[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221 = - _theResult___sfd__h580342; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221 = + _theResult___sfd__h580343; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h579637 or + _theResult___snd__h579638 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 or - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221) + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - _theResult___snd__h579637[56:5]; + _theResult___snd__h579638[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825; @@ -37047,48 +37047,48 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q221; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 = 52'd0; endcase end - always@(guard__h571725 or - _theResult___snd__h579637 or - out_sfd__h580345 or _theResult___sfd__h580342) + always@(guard__h571726 or + _theResult___snd__h579638 or + out_sfd__h580346 or _theResult___sfd__h580343) begin - case (guard__h571725) + case (guard__h571726) 2'b0, 2'b01: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 = - _theResult___snd__h579637[56:5]; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 = + _theResult___snd__h579638[56:5]; 2'b10: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 = - out_sfd__h580345; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 = + out_sfd__h580346; 2'b11: - CASE_guard71725_0b0_theResult___snd79637_BITS__ETC__q222 = - _theResult___sfd__h580342; + CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 = + _theResult___sfd__h580343; endcase end - always@(guard__h581037 or sfdin__h589257 or _theResult___sfd__h589993) + always@(guard__h581038 or sfdin__h589258 or _theResult___sfd__h589994) begin - case (guard__h581037) + case (guard__h581038) 2'b0: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223 = - sfdin__h589257[56:5]; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223 = + sfdin__h589258[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223 = - _theResult___sfd__h589993; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223 = + _theResult___sfd__h589994; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - sfdin__h589257 or + sfdin__h589258 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 or IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 or - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223) + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - sfdin__h589257[56:5]; + sfdin__h589258[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851; @@ -37097,24 +37097,24 @@ module mkCore(CLK, IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q223; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 = 52'd0; endcase end - always@(guard__h581037 or - sfdin__h589257 or out_sfd__h589996 or _theResult___sfd__h589993) + always@(guard__h581038 or + sfdin__h589258 or out_sfd__h589997 or _theResult___sfd__h589994) begin - case (guard__h581037) + case (guard__h581038) 2'b0, 2'b01: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 = - sfdin__h589257[56:5]; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 = + sfdin__h589258[56:5]; 2'b10: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 = - out_sfd__h589996; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 = + out_sfd__h589997; 2'b11: - CASE_guard81037_0b0_sfdin89257_BITS_56_TO_5_0b_ETC__q224 = - _theResult___sfd__h589993; + CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 = + _theResult___sfd__h589994; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37149,28 +37149,28 @@ module mkCore(CLK, coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852; endcase end - always@(guard__h590106 or - _theResult___snd__h598042 or _theResult___sfd__h598777) + always@(guard__h590107 or + _theResult___snd__h598043 or _theResult___sfd__h598778) begin - case (guard__h590106) + case (guard__h590107) 2'b0: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225 = - _theResult___snd__h598042[56:5]; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225 = + _theResult___snd__h598043[56:5]; 2'b01, 2'b10, 2'b11: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225 = - _theResult___sfd__h598777; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225 = + _theResult___sfd__h598778; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or - _theResult___snd__h598042 or + _theResult___snd__h598043 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 or IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 or - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225) + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225) begin case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226]) 3'd1: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - _theResult___snd__h598042[56:5]; + _theResult___snd__h598043[56:5]; 3'd2: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870; @@ -37179,25 +37179,25 @@ module mkCore(CLK, IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868; 3'd4: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q225; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225; default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 = 52'd0; endcase end - always@(guard__h590106 or - _theResult___snd__h598042 or - out_sfd__h598780 or _theResult___sfd__h598777) + always@(guard__h590107 or + _theResult___snd__h598043 or + out_sfd__h598781 or _theResult___sfd__h598778) begin - case (guard__h590106) + case (guard__h590107) 2'b0, 2'b01: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 = - _theResult___snd__h598042[56:5]; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 = + _theResult___snd__h598043[56:5]; 2'b10: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 = - out_sfd__h598780; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 = + out_sfd__h598781; 2'b11: - CASE_guard90106_0b0_theResult___snd98042_BITS__ETC__q226 = - _theResult___sfd__h598777; + CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 = + _theResult___sfd__h598778; endcase end always@(coreFix_fpuMulDivExe_0_regToExeQ$first or @@ -37517,10 +37517,10 @@ module mkCore(CLK, 4'd13; endcase end - always@(k__h669625 or + always@(k__h669626 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669625) + case (k__h669626) 1'd0: SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 = coreFix_aluExe_0_rsAlu$canEnq; @@ -37559,10 +37559,10 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(k__h669625 or + always@(k__h669626 or coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq) begin - case (k__h669625) + case (k__h669626) 1'd0: SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 = !coreFix_aluExe_0_rsAlu$canEnq; @@ -37708,14 +37708,14 @@ module mkCore(CLK, 21'd1485482; endcase end - always@(idx__h685370 or + always@(idx__h685371 or fetchStage$pipelines_0_canDeq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 or coreFix_aluExe_0_rsAlu$canEnq or NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685370) + case (idx__h685371) 1'd0: SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 = fetchStage$pipelines_0_canDeq && @@ -37836,15 +37836,15 @@ module mkCore(CLK, regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738; endcase end - always@(k__h669625 or + always@(k__h669626 or coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq) begin - case (k__h669625) + case (k__h669626) 1'd0: - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_0_rsAlu$RDY_enq; 1'd1: - CASE_k69625_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = + CASE_k69626_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 = coreFix_aluExe_1_rsAlu$RDY_enq; endcase end @@ -37947,14 +37947,14 @@ module mkCore(CLK, IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461; endcase end - always@(idx__h685370 or + always@(idx__h685371 or fetchStage$pipelines_0_canDeq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991 or coreFix_aluExe_0_rsAlu$canEnq or fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998 or coreFix_aluExe_1_rsAlu$canEnq) begin - case (idx__h685370) + case (idx__h685371) 1'd0: SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 = (!fetchStage$pipelines_0_canDeq || @@ -38280,16 +38280,16 @@ module mkCore(CLK, begin case (IF_rob_deqPort_0_deq_data__4339_BIT_181_4414_T_ETC___d14983) 6'd0: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; 6'd1, 6'd11, 6'd24: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] }; 6'd2: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] }; 6'd8: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 43'd8192, robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18], @@ -38302,30 +38302,31 @@ module mkCore(CLK, 2'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd9, 6'd16: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 54'd0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8], - 2'b0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4], - 2'b0, - robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; + robdeqPort_0_deq_data_BITS_95_TO_32__q245[9], + 3'd0, + robdeqPort_0_deq_data_BITS_95_TO_32__q245[5], + 3'd0, + robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], + 1'd0 }; 6'd10, 6'd23: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] }; 6'd14, 6'd27: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] }; 6'd17: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63], 19'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] }; 6'd18: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11, 40'd5120, robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17], @@ -38337,9 +38338,9 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; - 6'd19: data_warl_xformed__h722429 = 64'h800000000014112D; + 6'd19: data_warl_xformed__h722430 = 64'h800000000014112D; 6'd20: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 48'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[15], 1'b0, @@ -38347,7 +38348,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] }; 6'd21: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 52'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'b0, @@ -38357,7 +38358,7 @@ module mkCore(CLK, 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] }; 6'd22, 6'd29: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 52'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[11], 1'd0, @@ -38371,12 +38372,12 @@ module mkCore(CLK, 1'd0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[1], 1'd0 }; - 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h722429 = 64'd0; + 6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h722430 = 64'd0; 6'd37: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] }; 6'd40: - data_warl_xformed__h722429 = + data_warl_xformed__h722430 = { 32'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28], 12'b0, @@ -38385,7 +38386,7 @@ module mkCore(CLK, robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6], 1'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] }; - default: data_warl_xformed__h722429 = rob$deqPort_0_deq_data[95:32]; + default: data_warl_xformed__h722430 = rob$deqPort_0_deq_data[95:32]; endcase end always@(rob$deqPort_0_deq_data) @@ -38446,9 +38447,9 @@ module mkCore(CLK, begin case (rob$deqPort_0_deq_data[329:325]) 5'd19, 5'd20: - x__h723033 = + x__h723034 = IF_rob_deqPort_0_deq_data__4339_BITS_329_TO_32_ETC___d15191; - default: x__h723033 = rob$deqPort_0_deq_data[425:362]; + default: x__h723034 = rob$deqPort_0_deq_data[425:362]; endcase end always@(rob$deqPort_0_deq_data) @@ -41427,7 +41428,7 @@ module mkCore(CLK, $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); if (RST_N != `BSV_RESET_VALUE) if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas && - v__h603884 == 2'd0) + v__h603885 == 2'd0) $fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!"); end // synopsys translate_on