pushed comparitive benchmark Toooba

Tests/isa/build-assembly.sh

@@ -0,0 +1,17 @@
+# Send assembler file to remote machine to run
+# scp Cprograms/start.S home:/home/akilan/cheri/output/sdk/bin/
+# scp Cprograms/main.c home:/home/akilan/cheri/output/sdk/bin/
+
+scp cheri.S home:/home/akilan/cheri/output/sdk/bin/
+
+# Run compiled instruction remotely
+ssh home 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang   --target=riscv64-unknown-elf   -march=rv64gcxcheri -mabi=l64pc128 -nostdlib -nostartfiles   -Wl,-Ttext=0x80000000 -o testC cheri.S'
+
+# ssh home 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang   --target=riscv64-unknown-elf   -march=rv64gcxcheri -mabi=lp64d -nostdlib -nostartfiles   -Wl,-Ttext=0x80000000 -o testC start.S main.c'
+
+# Disassembly ouput
+ssh home 'cd /home/akilan/cheri/output/sdk/bin/ && ./llvm-objdump -d testC'
+
+# Copy file back for testing
+scp home:/home/akilan/cheri/output/sdk/bin/testC .
+

Tests/isa/cheri.S

@@ -0,0 +1,56 @@
+.section .text
+    .globl _start
+    .align 4
+_start:
+    # 1. Setup the Page Table Root (Sv39)
+    # The PPN points to the physical location of your root table.
+    li      t0, (0x80000000 >> 12) 
+    li      t1, (8 << 60)          # Mode 8 = Sv39
+    or      t0, t0, t1
+    csrw    satp, t0               
+    sfence.vma                     # All addresses below are now VIRTUAL
+
+    # 2. Get the root capability (PCC)
+    # Since we are running in VA space, ct0 now describes a VA range.
+    cspecialr ct0, pcc
+
+    # ----------------------------------------------------------------
+    # 3. Create Virtual Address Silos (ca1 - ca4)
+    # ----------------------------------------------------------------
+    
+    # Silo 1: VA 0x80006000
+    li      t1, 0x80006000        
+    csetaddr ca1, ct0, t1
+    li      t2, 8
+    csetbounds ca1, ca1, t2
+    ld      t0, 0(ca1)             # Accessing VA 0x80006000
+
+    # ... (Repeat for ca2, ca3, ca4 as in your previous logic) ...
+
+    # ----------------------------------------------------------------
+    # 4. FIX: The 'tohost' Exit Mechanism (Virtual Address)
+    # ----------------------------------------------------------------
+
+    # 'la' loads the Virtual Address of the label 'tohost'
+    la      t0, tohost             
+    
+    # We MUST derive c1 from a valid capability (ct0) to keep the TAG bit
+    csetaddr c1, ct0, t0           
+    
+    # Set bounds to 8 bytes (size of a dword)
+    li      t1, 8
+    csetbounds c1, c1, t1
+
+    # Final Store to signal the simulator (Success = 1)
+    li      t1, 1
+    csd     t1, 0(c1)              # Store 1 to the VA of tohost
+
+# ----------------------------------------------------------------
+# Data Section: Needs to be mapped in your Sv39 Page Tables
+# ----------------------------------------------------------------
+.section ".tohost","aw",@progbits
+.align 6
+.globl tohost
+tohost:   .dword 0
+.globl fromhost
+fromhost: .dword 0

builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile

@@ -13,7 +13,8 @@ BSC_COMPILATION_FLAGS += -verbose
 # TEST ?= Page
 # TEST ?= PageReadWrite
 # TEST ?= CheriPage
-TEST ?= MemoryAllocator
+# TEST ?= MemoryAllocator
+TEST ?= testC
 
 #================================================================
 # Parameter settings for MIT RISCY, setup paths etc. for Include_Common

builds/Resources/Include_Common.mk

@@ -56,6 +56,7 @@ BSC_COMPILATION_FLAGS += \
 	-D FABRIC64    \
 	-D BLUESIM \
 	-D PERFORMANCE_MONITORING \
+	-D PERF_COUNT \
 	-keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \
 	-suppress-warnings G0020 -steps-max-intervals 10000000   \
 	-steps-warn-interval 1000000 \

src_Core/CPU/Core.bsv

@@ -918,6 +918,7 @@ module mkCore#(CoreId coreId)(Core);
     // incr cycle count
     (* fire_when_enabled, no_implicit_conditions *)
     rule incCycleCnt(doStats);
+        $display("calling cycle");
         cycleCnt.incr(1);
     endrule
 

src_Core/CPU/CsrFile.bsv

@@ -330,7 +330,7 @@ interface StatsCsr;
 endinterface
 
 module mkStatsCsr(StatsCsr);
-    Reg#(Bool) doStats <- mkConfigReg(False);
+    Reg#(Bool) doStats <- mkConfigReg(True);
 
     FIFO#(Bool) writeQ <- mkFIFO1;