Add support for external debug module.
This commit is contained in:
Darius Rad
519
src_bsc_lib_RTL/SyncFIFOLevel.v
Normal file
519
src_bsc_lib_RTL/SyncFIFOLevel.v
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// Copyright (c) 2000-2012 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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`ifdef BSV_RESET_FIFO_HEAD
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`define BSV_RESET_EDGE_HEAD or `BSV_RESET_EDGE dRST
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`else
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`define BSV_RESET_EDGE_HEAD
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`endif
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// A clock synchronization FIFO where the enqueue and dequeue sides are in
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// different clock domains.
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// There are no restrictions w.r.t. clock frequencies
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// The depth of the FIFO must be a power of 2 (2,4,8,...) since the
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// indexing uses a Gray code counter.
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// FULL and EMPTY signal are pessimistic, that is, they are asserted
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// immediately when the FIFO becomes FULL or EMPTY, but their deassertion
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// is delayed due to synchronization latency.
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// dCount and sCount are also delayed and may differ because of latency
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// from the synchronization logic
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module SyncFIFOLevel(
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sCLK,
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sRST,
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dCLK,
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sENQ,
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sD_IN,
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sFULL_N,
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dDEQ,
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dD_OUT,
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dEMPTY_N,
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dCOUNT,
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sCOUNT,
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sCLR,
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sCLR_RDY,
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dCLR,
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dCLR_RDY
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) ;
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parameter dataWidth = 1 ;
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parameter depth = 2 ; // minimum 2
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parameter indxWidth = 1 ; // minimum 1
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// input clock domain ports
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input sCLK ;
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input sRST ;
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input sENQ ;
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input [dataWidth -1 : 0] sD_IN ;
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output sFULL_N ;
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// destination clock domain ports
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input dCLK ;
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input dDEQ ;
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output dEMPTY_N ;
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output [dataWidth -1 : 0] dD_OUT ;
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// Counts of capacity need extra bit to show full, e.g., range is 0 to 32
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output [indxWidth : 0] dCOUNT;
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output [indxWidth : 0] sCOUNT;
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// Clear signals on both domains
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input sCLR;
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output sCLR_RDY;
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input dCLR;
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output dCLR_RDY;
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// constants for bit masking of the gray code
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wire [indxWidth : 0] msbset = ~({(indxWidth + 1){1'b1}} >> 1) ;
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wire [indxWidth - 1 : 0] msb2set = ~({(indxWidth + 0){1'b1}} >> 1) ;
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wire [indxWidth : 0] msb12set = msbset | {1'b0, msb2set} ; // 'b11000...
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// FIFO Memory
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reg [dataWidth -1 : 0] fifoMem [0: depth -1 ] ;
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reg [dataWidth -1 : 0] dDoutReg ;
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// Enqueue Pointer
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reg [indxWidth : 0] sGEnqPtr, sBEnqPtr ; // Flops
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reg sNotFullReg ;
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wire [indxWidth : 0] sNextGEnqPtr, sNextBEnqPtr ;
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wire [indxWidth : 0] sNextCnt, sFutureCnt ;
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wire sNextNotFull, sFutureNotFull ;
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// Dequeue Pointer
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reg [indxWidth : 0] dGDeqPtr, dBDeqPtr ; // Flops
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reg dNotEmptyReg ;
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wire [indxWidth : 0] dNextGDeqPtr, dNextBDeqPtr ;
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wire [indxWidth : 0] dNextCnt ;
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wire dNextNotEmpty;
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// Rgisters needed for capacity counts
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reg [indxWidth : 0] sCountReg, dCountReg ;
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// Note for Timing improvement:
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// These signals can be registers to improve a long path from the
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// second stage of the synchronizer to the input of the
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// CountReg. The path includes a Gray to Binary conversion and a
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// subtraction, which can easily be a long path.
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// The effect is that the count is delayed one additional cycle.
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wire [indxWidth : 0] sBDeqPtr, dBEnqPtr ;
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// flops to sychronize enqueue and dequeue point across domains
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reg [indxWidth : 0] dSyncReg1, dEnqPtr ;
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reg [indxWidth : 0] sSyncReg1, sDeqPtr ;
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// Indexes for fifo memory is one bit smaller than indexes
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wire [indxWidth - 1 :0] sEnqPtrIndx, dDeqPtrIndx ;
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// wires needed for clear processing
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wire dRST;
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wire sCLRSynced; // dCLR synced to sCLK
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wire sCLR_RDY_int;
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wire dCLRSynced; // sCLR synced to dCLK
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wire dCLR_RDY_int;
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wire sClear;
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wire dClear;
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// Clear processing requires the use of 2 handshake synchronizers
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SyncHandshake #(.delayreturn(1))
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sClrSync ( .sCLK(sCLK),
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.sRST(sRST),
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.dCLK(dCLK),
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.sEN(sCLR),
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.sRDY(sCLR_RDY_int),
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.dPulse(dCLRSynced));
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SyncHandshake #(.delayreturn(1))
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dClrSync ( .sCLK(dCLK),
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.sRST(sRST),
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.dCLK(sCLK),
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.sEN(dCLR),
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.sRDY(dCLR_RDY_int),
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.dPulse(sCLRSynced));
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// Outputs
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assign dD_OUT = dDoutReg;
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assign dEMPTY_N = dNotEmptyReg ;
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assign sFULL_N = sNotFullReg ;
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assign sCOUNT = sCountReg;
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assign dCOUNT = dCountReg;
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assign sCLR_RDY = sCLR_RDY_int;
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assign dCLR_RDY = dCLR_RDY_int;
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// Indexes are truncated from the Binary counter
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assign sEnqPtrIndx = sBEnqPtr[indxWidth-1:0] ;
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assign dDeqPtrIndx = dBDeqPtr[indxWidth-1:0] ;
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// clear signals
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assign sClear = sCLR || !sCLR_RDY_int || sCLRSynced;
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assign dClear = dCLR || !dCLR_RDY_int || dCLRSynced;
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assign dRST = sRST;
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// Fifo memory write
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always @(posedge sCLK)
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begin
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if ( sENQ )
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fifoMem[sEnqPtrIndx] <= `BSV_ASSIGNMENT_DELAY sD_IN ;
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end // always @ (posedge sCLK)
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////////////////////////////////////////////////////////////////////////
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// Enqueue Pointer and increment logic
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assign sNextBEnqPtr = sBEnqPtr + 1'b1 ;
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assign sNextGEnqPtr = sNextBEnqPtr ^ (sNextBEnqPtr >> 1) ;
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assign sNextNotFull = (sGEnqPtr ^ msb12set) != sDeqPtr ;
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assign sFutureNotFull = (sNextGEnqPtr ^ msb12set) != sDeqPtr ;
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assign sNextCnt = sBEnqPtr - sBDeqPtr ;
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assign sFutureCnt = sNextBEnqPtr - sBDeqPtr ;
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assign sBDeqPtr = grayToBinary( sDeqPtr ) ;
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always @(posedge sCLK or `BSV_RESET_EDGE sRST)
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begin
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if (sRST == `BSV_RESET_VALUE)
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begin
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sBEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
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sGEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
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sNotFullReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; // Mark as full during reset
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sCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
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end // if (sRST == `BSV_RESET_VALUE)
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else
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begin
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if (sClear)
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begin
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sBEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
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sGEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
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sNotFullReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
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sCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth +1 ) {1'b0}} ;
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end
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else if ( sENQ )
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begin
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sBEnqPtr <= `BSV_ASSIGNMENT_DELAY sNextBEnqPtr ;
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sGEnqPtr <= `BSV_ASSIGNMENT_DELAY sNextGEnqPtr ;
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sNotFullReg <= `BSV_ASSIGNMENT_DELAY sFutureNotFull ;
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sCountReg <= `BSV_ASSIGNMENT_DELAY sFutureCnt ;
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end
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else
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begin
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sNotFullReg <= `BSV_ASSIGNMENT_DELAY sNextNotFull ;
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sCountReg <= `BSV_ASSIGNMENT_DELAY sNextCnt ;
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end // else: !if( sENQ )
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end // else: !if(sRST == `BSV_RESET_VALUE)
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end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
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// Enqueue pointer synchronizer to dCLK
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always @(posedge dCLK or `BSV_RESET_EDGE sRST)
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begin
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if (sRST == `BSV_RESET_VALUE)
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begin
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dSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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dEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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end // if (sRST == `BSV_RESET_VALUE)
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else
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begin
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dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sGEnqPtr ; // Clock domain crossing
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dEnqPtr <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
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end // else: !if(sRST == `BSV_RESET_VALUE)
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end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Enqueue Pointer and increment logic
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assign dNextBDeqPtr = dBDeqPtr + 1'b1 ;
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assign dNextGDeqPtr = dNextBDeqPtr ^ (dNextBDeqPtr >> 1) ;
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assign dNextNotEmpty = dGDeqPtr != dEnqPtr ;
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assign dNextCnt = dBEnqPtr - dBDeqPtr ;
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assign dBEnqPtr = grayToBinary( dEnqPtr ) ;
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always @(posedge dCLK or `BSV_RESET_EDGE dRST)
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begin
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if (dRST == `BSV_RESET_VALUE)
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begin
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dBDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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dGDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; // Mark as empty to avoid dequeues until after reset
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dCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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end // if (sRST == `BSV_RESET_VALUE)
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else
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begin
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if (dClear) begin
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dBDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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dGDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
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dCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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end
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else if (!dNotEmptyReg && dNextNotEmpty) begin
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dBDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextBDeqPtr ;
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dGDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextGDeqPtr ;
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dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
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dCountReg <= `BSV_ASSIGNMENT_DELAY dNextCnt ;
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end
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else if (dDEQ && dNextNotEmpty) begin
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dBDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextBDeqPtr ;
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dGDeqPtr <= `BSV_ASSIGNMENT_DELAY dNextGDeqPtr ;
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dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
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dCountReg <= `BSV_ASSIGNMENT_DELAY dNextCnt ;
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end
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else if (dDEQ && !dNextNotEmpty) begin
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dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
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dCountReg <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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end
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else begin
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dCountReg <= `BSV_ASSIGNMENT_DELAY dNextCnt ;
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end
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end // else: !if(sRST == `BSV_RESET_VALUE)
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end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
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always @(posedge dCLK `BSV_RESET_EDGE_HEAD)
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begin
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`ifdef BSV_RESET_FIFO_HEAD
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if (dRST == `BSV_RESET_VALUE)
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begin
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dDoutReg <= `BSV_ASSIGNMENT_DELAY { dataWidth { 1'b0 }} ;
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end // if (dRST == `BSV_RESET_VALUE)
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else
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`endif
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begin
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if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin
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dDoutReg <= `BSV_ASSIGNMENT_DELAY fifoMem[dDeqPtrIndx] ;
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end
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end
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end
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// Dequeue pointer synchronized to sCLK
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always @(posedge sCLK or `BSV_RESET_EDGE sRST)
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begin
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if (sRST == `BSV_RESET_VALUE)
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begin
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sSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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sDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
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end // if (sRST == `BSV_RESET_VALUE)
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else
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begin
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sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dGDeqPtr ; // clock domain crossing
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sDeqPtr <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
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// sBDeqPtr <= `BSV_ASSIGNMENT_DELAY grayToBinary( sDeqPtr ) ;
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end // else: !if(sRST == `BSV_RESET_VALUE)
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end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
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////////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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// Run time assertion check
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always @(posedge sCLK)
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begin
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if ( sENQ && ! sNotFullReg ) $display ("Warning: SyncFIFOLevel: %m -- Enqueing to a full fifo");
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end
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always @(posedge dCLK)
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begin
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if ( dDEQ && ! dNotEmptyReg ) $display ("Warning: SyncFIFOLevel: %m -- Dequeuing from empty fifo");
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end
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// synopsys translate_on
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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// synopsys translate_off
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initial
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begin : initBlock
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integer i ;
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// initialize the FIFO memory with aa's
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for (i = 0; i < depth; i = i + 1)
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begin
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fifoMem[i] = {((dataWidth + 1)/2){2'b10}} ;
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end
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dDoutReg = {((dataWidth + 1)/2){2'b10}} ;
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// initialize the pointer
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sGEnqPtr = {((indxWidth + 1)/2){2'b10}} ;
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sBEnqPtr = sGEnqPtr ;
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sNotFullReg = 1'b0 ;
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dGDeqPtr = sGEnqPtr ;
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dBDeqPtr = sGEnqPtr ;
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dNotEmptyReg = 1'b0;
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// initialize other registers
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sSyncReg1 = sGEnqPtr ;
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sDeqPtr = sGEnqPtr ;
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dSyncReg1 = sGEnqPtr ;
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dEnqPtr = sGEnqPtr ;
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end // initial begin
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// synopsys translate_on
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// synopsys translate_off
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initial
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begin : parameter_assertions
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integer ok ;
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integer i, expDepth ;
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ok = 1;
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expDepth = 1 ;
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// calculate x = 2 ** (indxWidth - 1)
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for( i = 0 ; i < indxWidth ; i = i + 1 )
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begin
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expDepth = expDepth * 2 ;
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end
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if ( expDepth != depth )
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begin
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ok = 0;
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$display ( "ERROR SyncFiFOLevel.v: index size and depth do not match;" ) ;
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$display ( "\tdepth must equal 2 ** index size. expected %0d", expDepth );
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end
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#0
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if ( ok == 0 ) $finish ;
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end // initial begin
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// synopsys translate_on
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`endif // BSV_NO_INITIAL_BLOCKS
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function [indxWidth:0] grayToBinary ;
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input [indxWidth:0] grayin;
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begin: grayToBinary_block
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reg [indxWidth:0] binary ;
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integer i ;
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for ( i = 0 ; i <= indxWidth ; i = i+1 )
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begin
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binary[i] = ^( grayin >> i ) ;
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end
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grayToBinary = binary ;
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end
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endfunction
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endmodule // FIFOSync
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`ifdef testBluespec
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module testSyncFIFOLevel() ;
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parameter dsize = 8;
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parameter fifodepth = 32;
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parameter fifoidx = 5;
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wire sCLK, dCLK, dRST ;
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wire sENQ, dDEQ;
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||||
wire sFULL_N, dEMPTY_N ;
|
||||
wire [dsize -1:0] sDIN, dDOUT ;
|
||||
|
||||
reg [dsize -1:0] sCNT, dCNT ;
|
||||
reg sRST ;
|
||||
|
||||
wire [fifoidx:0] dItemCnt, sItemCnt ;
|
||||
wire sCLR_RDY;
|
||||
wire dCLR_RDY;
|
||||
wire sCLR;
|
||||
wire dCLR;
|
||||
reg [31:0] count ;
|
||||
reg started ;
|
||||
reg ddeq ;
|
||||
|
||||
|
||||
ClockGen#(14,15,10) sc( sCLK );
|
||||
ClockGen#(11,12,2600) dc( dCLK ); // Pause the generation of the destination side clock
|
||||
|
||||
initial
|
||||
begin
|
||||
sCNT = 0;
|
||||
dCNT = 0;
|
||||
sRST = `BSV_RESET_VALUE ;
|
||||
count = 0;
|
||||
started = 0;
|
||||
ddeq = 0;
|
||||
|
||||
$display( "running test" ) ;
|
||||
|
||||
$dumpfile("SyncFIFOLevel.vcd");
|
||||
$dumpvars(10,testSyncFIFOLevel) ;
|
||||
#1
|
||||
$dumpon ;
|
||||
#200 ;
|
||||
sRST = !`BSV_RESET_VALUE ;
|
||||
|
||||
|
||||
#50000 $finish ;
|
||||
end
|
||||
|
||||
SyncFIFOLevel #(dsize,fifodepth,fifoidx)
|
||||
dut( sCLK, sRST, dCLK, sENQ, sDIN,
|
||||
sFULL_N, dDEQ, dDOUT, dEMPTY_N, dItemCnt, sItemCnt,
|
||||
sCLR, sCLR_RDY, dCLR, dCLR_RDY );
|
||||
|
||||
assign sDIN = sCNT ;
|
||||
assign sENQ = sFULL_N ;
|
||||
|
||||
assign dCLR = ((count[7:0] == 8'b0010_0011) && dCLR_RDY);
|
||||
assign sCLR = ((count[7:0] == 8'b0000_0001) && sCLR_RDY);
|
||||
|
||||
always @(posedge sCLK)
|
||||
begin
|
||||
count <= count + 1 ;
|
||||
$display( "scount is %d", sItemCnt ) ;
|
||||
if (sENQ )
|
||||
begin
|
||||
sCNT <= `BSV_ASSIGNMENT_DELAY sCNT + 1;
|
||||
$display( "enqueuing is %d", sCNT ) ;
|
||||
end // if (sENQ )
|
||||
end // always @ (posedge sCLK)
|
||||
|
||||
assign dDEQ = ddeq ;
|
||||
|
||||
always @(dItemCnt or dEMPTY_N or started or count)
|
||||
begin
|
||||
ddeq = (count > 40) && dEMPTY_N && (started || dItemCnt > 4);
|
||||
end // always @ (dItemCnt or dEMPTY_N or started)
|
||||
|
||||
always @(posedge dCLK)
|
||||
begin
|
||||
$display( "dcount is %d", dItemCnt ) ;
|
||||
if (ddeq)
|
||||
begin
|
||||
started <= 1;
|
||||
$display( "dequeing %d", dDOUT ) ;
|
||||
end // if (dDEQ )
|
||||
else
|
||||
begin
|
||||
started <= 0;
|
||||
end
|
||||
end // always @ (posedge dCLK)
|
||||
|
||||
endmodule // testSyncFIFO
|
||||
`endif
|
||||
Reference in New Issue
Block a user