From 4dd0a73051e183f61d0b670a6335f2321b70030d Mon Sep 17 00:00:00 2001 From: Jonathan Woodruff Date: Thu, 17 Dec 2020 15:02:05 +0000 Subject: [PATCH] Port to internal AXI interfaces for the debug module. --- src_Core/Debug_Module/DM_System_Bus.bsv | 14 ++++++-------- src_Core/Debug_Module/Debug_Module.bsv | 8 ++++---- src_SSITH_P3/src_BSV/P3_Core.bsv | 7 ++++--- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src_Core/Debug_Module/DM_System_Bus.bsv b/src_Core/Debug_Module/DM_System_Bus.bsv index a6f9abc..08417d2 100644 --- a/src_Core/Debug_Module/DM_System_Bus.bsv +++ b/src_Core/Debug_Module/DM_System_Bus.bsv @@ -54,9 +54,9 @@ interface DM_System_Bus_IFC; // ---------------- // Facing System - interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master; + interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ @@ -197,10 +197,8 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // ---------------------------------------------------------------- // Interface to memory fabric - AXI4_Master_Xactor#(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) - master_xactor <- mkAXI4_Master_Xactor; + let master_xactor <- mkAXI4ShimFF; + // ---------------------------------------------------------------- // System Bus state @@ -680,7 +678,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC); // ---------------- // Facing System - interface AXI4_Master_IFC master = master_xactor.masterSynth; + interface master = master_xactor.master; endmodule // ================================================================ diff --git a/src_Core/Debug_Module/Debug_Module.bsv b/src_Core/Debug_Module/Debug_Module.bsv index cb96e8c..1178891 100644 --- a/src_Core/Debug_Module/Debug_Module.bsv +++ b/src_Core/Debug_Module/Debug_Module.bsv @@ -155,9 +155,9 @@ interface Debug_Module_IFC; interface Client #(Bool, Bool) ndm_reset_client; // Read/Write RISC-V memory - interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, - Wd_AW_User, Wd_W_User, Wd_B_User, - Wd_AR_User, Wd_R_User) master; + interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph, + Wd_AW_User, Wd_W_User, Wd_B_User, + Wd_AR_User, Wd_R_User) master; endinterface // ================================================================ @@ -481,7 +481,7 @@ module mkDebug_Module (Debug_Module_IFC); interface Client ndm_reset_client = dm_run_control.ndm_reset_client; // Read/Write RISC-V memory - interface AXI4_Master_IFC master = dm_system_bus.master; + interface master = dm_system_bus.master; endmodule // ================================================================ diff --git a/src_SSITH_P3/src_BSV/P3_Core.bsv b/src_SSITH_P3/src_BSV/P3_Core.bsv index 6fb6d87..5c4b81a 100644 --- a/src_SSITH_P3/src_BSV/P3_Core.bsv +++ b/src_SSITH_P3/src_BSV/P3_Core.bsv @@ -293,15 +293,16 @@ module mkP3_Core (P3_Core_IFC); // ================================================================ // INTERFACE - + let master0_synth <- toAXI4_Master_Synth(corew.cpu_imem_master); + let master1_synth <- toAXI4_Master_Synth(corew.cpu_dmem_master); // ---------------------------------------------------------------- // Core CPU interfaces // CPU IMem to Fabric master interface - interface AXI4_Master_Synth master0 = corew.cpu_imem_master; + interface AXI4_Master_Synth master0 = master0_synth; // CPU DMem to Fabric master interface - interface AXI4_Master_Synth master1 = corew.cpu_dmem_master; + interface AXI4_Master_Synth master1 = master1_synth; // External interrupts method Action interrupt_reqs (Bit #(N_External_Interrupt_Sources) reqs);